User`s Manual
Contents
1. USBD General USB Host Controller Output port Driver ii USB Host Controller DIP Switches and Jumpers Block Diagram Above block diagram shows 5 main components on the PDIUSBD12 evaluation board Beside bus transceiver address command decoder and PDIUSBD12 a general input port and a general output port are included in the design These input and output ports are designed for test purposes such as test switches and test LEDs They also act as glue logic to adapt the PDIUSBD12 to the ISA bus For example ISA interrupt is edge triggered but PDIUSBD12 interrupt is level triggered The MSB of the general output port is used as interrupt enable to convert level triggered interrupt to edge triggered VO Mapping PDIUSBD12 evaluation board uses 8 I O addresses Offset Usage 0 D12 data register R W 1 D12 command register W only 2 General input port R only 3 General output port W only 4 to 7 Reserved for expansion board Bit description for general input port Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 8 USER S MANUAL REV 2 1 Usage Key S1 0 for pressed Key S2 0 for pressed Key S3 0 for pressed Key S4 0 for pressed D12 GoodLink pin state USB bus power state 1 for USB2. U1 74HCT688 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com
3. 14 De g DATAS XTALI Hss 221 cis 15 16 pz g DATAS GL N 25 1 cs 1 0 1 3 ADD 17 Hs Tog OMIA ORESELN Lie AZP R7 RB R9 R10 ADDR1 n 35 DRQ cs Di H sN DMAGK N 18 DAK Pn C6 aS 10K 10K 10K 10K voc l ai ADDED 15s 24 IRQ 4 SUSPEND f SUSPEND DMREQ me 6 22P 25 WE O4 CLKOUT WR N 4s 308 Shell to GND T INT N RBUN DOM pa 7 5 5 ofS BdL VGC 4 o o 1 Lin v ES cate B1 HF i po 18 2 T M UM 2 7 A2 B2 i6 po ied yt 1A1 PR e 5 A3 B3 45 1Y2 1A2 T o 4 s3 D3 D2 14 6 amp A4 B4 Gabe ES 312 18 143 Fg iiis A5 B5 1Y4 1A4 o o 7 13 D5 D4 9 1 V BUS 8 6 B6 15 De E 2Y1 2A1 5 7 13 9 7 B7 F1 D7 D8 5 22 202 15 OSCl is optional replacement cc A8 B8 p 3 23 2A3 17 T for Yl C5 and C6 T 19 2Y4 2A4 I r 39 a u2 1 1 R11 R12 RIS RI4 2 RIS E DIR 74LS245 1G 2G pis 1K 470 470 2 470 Q 470 DIR 245 E m D2 D3 D4 D5 74HCT244 5 Kio RED RED RED RED 1M w cc cw Cw E x y dx x U4A 74LS05 4 3 1 3 74LS05 DO 3 2 s 4 DI gja Qt F5 os 702 Q2 wc D3 Q3 74LS05 D3 8 9 m 13 4 a iz 5 6 Ds 14 09 O5 ds 2 cas EA pe 16 X 13 12 1000P pz 15 7 RAEE 9 8 n U4F ig ek 74LS05 U4D CLR 74LSO 11 10 2 UG UAE 4 74HCT273 74L805 C8 i0 Ch C2 vec 8s ow 2m 40 OW 01 01 01 04 041 12 IOR ge il Title 14 ADDR2 D12 EVALUATION BOARD 16 ADORI ab e 17 18 ADDRO T 10 TANT Size Document Number Rev AG 20 LX L I I1 1 g A D12 EVAL 200 2 00 gt VERSA D
4. 35 c rece edere titi dee lero M ect ee eee eden 9 Nui Supi C sioi oas 10 Schematics for PDIUSBDI2 evaluation board eessssssseesseeeeeeeen eene 10 Schematic for PDIUSBDI2 ISA bridging board ssseeeeeeeenen een 11 Bil EodiPiIVr e C 12 Bill of materials of the PDIUSBDI2 evaluation board sess 12 Bill of materials of the PDIUSBDI2 ISA bridging board sse 12 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 2 USER S MANUAL REV 2 1 INSTALLATION OF PDIUSBD12 EVALUATION BOARD Introduction The PDIUSBD12 evaluation kit uses 2 PC as a complete USB development environment a host PC with USB host capability and a device PC running PDIUSBD12 s firmware The PDIUSBD12 ISA bridging board is plugged inside the device PC and connects to the evaluation board using a 25 wire cable So the device PC behaves as a big USB device Features evaluation of PDIUSBD12 firmware and product prototype development can be easily done with this setup without the resource limitation of a micro controller Customers can also connect the evaluation board to their own CPU and bus through the 25 wire cable for final product development The firmware is carefully developed for high rate
5. data transmission and is written in C that supports Borland Turbo C for x86 and Keil C51 for 8031 currently Supporting to other CPU platforms will be available soon System Requirements PDIUSBD12 evaluation board and ISA bridging board 25 wire shielding data switch cable Host PC with USB motherboard or add on card Microsoft Windows 98 or Windows NT 5 0 Beta 2 Device PC running Microsoft DOS 6 x PDIUSBD12 evaluation diskette O gt O1 e G3 O For firmware development 1 X86 CPU platform Borland Turbo C 3 0 or above 2 8031 Keil C51 4 0 or above PDIUSBD12 Evaluation Disk pd b p m BAM ENS we CORR BN EH USB MA mm 25 Wire Cable ni m add WJ 1 p Device PC with PDIUSBD12 ISA Bridging Board PDIUSBD12 Evaluation Board Host PC with USB host Controller Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 3 USER S MANUAL REV 2 1 Installation Jumper s setting on PDIUSBD12 ISA bridging board The PDIUSBD12 ISA bridging board is plugged inside the device PC It will occupy I O IRQ and DMA resources of the device PC To avoid possible conflicts in setting
6. the maximal Bulk In transfer rate Print mode The PDIUSBD12 evaluation board acts like a printer It receives data packets from the host PC as fast as possible This mode is used to evaluate the maximal Bulk Out transfer rate Loop back mode In this mode the PDIUSBD12 evaluation board receives data packets on Main Out endpoint and sends them back to the host PC on Main In endpoint This mode is used to test the data integrity of transfers The Buffer Size setting on the test applet is determined by the firmware and hardware ability of the evaluation board For PC kit the maximal size is limited to 64000 On USB EPP kit this is limited to 16384 The Repeat Times for loop back test controls the numbers of iterations of loop back which is useful for debugging 1 means it is infinite Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 7 USER S MANUAL REV 2 1 HARDWARE DESCRIPTION System Block Diagram of D12 Evaluation Kit Customer s System CPU Memory and DMA Controller 25 Pin Interface 1 VCC GND USB Host PC 2 D0 D7 3 ADDRESS ENABLE 4 IOW IOR IRQ RESET 5 DREQ DACK EOT D12 Evaluation Board Bi direction B i Transceiver USB Device PC Command and Address Decoder General Input port E E
7. time that the evaluation board is connected to host PC host OS Device Manager will prompt installation of INF and driver Select the location of D12TEST INF and D12TEST SYS and complete installation procedure Some useful key command is supported when the firmware is running Key Operation ESC Disconnect USB and quit PDIUSBD12 firmware ENTER Reconnect USB using SoftConnect Display firmware status information V Switch on off verbose mode normally turned off for faster operation Using the Host Applet The test applet D12TEST EXE exercises all PDIUSBD12 endpoints Testing of control endpoints can be further done by standard USB Chapter 9 test programs cA PDIUSBD12 Test Application x Interrupt In Endpoint 1 M Generic Out Endpoint 1 D4 D3 D2 p1 Scan Test Endpoint 2 Print Test Endpoint 2 Bytes Transfered Bytes Transfered Current Rate Current Rate Average Rate Average Rate Maximal Rate Maximal Rate Stat Ste J Buffer cie 64000 Star Br Buffer Size E4000 Loopback Endpoint 2 Passed Failed Bytes Compared _Start por Repeat Times Buffer Size 4000 PHILIPS The operation of each endpoint is designed according to its nature that is supported in PDIUSBD12 Generic in and generic out endpoints has max packet size of 16 bytes and supports I O access only So they are suitable for small size and low rate data transfer like keyboard and
8. 7 O DATAO 18 T C Terminal Count This line provides a pulse when terminal count for any DMA channel is reached This signal is active high 19 ADDR2 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 9 USER S MANUAL REV 2 1 20 DACK This line is used to acknowledge DMA request and is active low 21 ADDR 1 22 O DRQ This line is asynchronous channel request used by peripheral devices to gain DMA service A DMA request is generated by bringing DRQ line to an active high 23 ADDRO 24 O IRQ This line is raising edge triggered An interrupt request is generated by raising this line high and hold until it is acknowledged by the processor 25 POWER GND PAL Equations Address and command decoder Inputs Pin 1 ADDR2 Pin 2 ADDR1 Pin 3 ADDRO Pin 4 IOW Pin 5 IOR Pin 6 IDACK Pin 7 AD_EN Pin 8 RESET Pin 9 INT_N Pin 11 INT EN Outputs Pin 12 IRQ Pin 13 RESET_N Pin 14 RD_N Pin 15 WAIT Pin 16 CS_D12 Pin 17 WR_273 Pin 18 RD_244 Pin 19 DIR 245 Logic Equations IDIR 245 IAD EN amp IDACK IOR RESET IRD 244 AD EN ADDR2 amp ADDR1 amp ADDRO IOR IWR 273 AD EN ADDR2 amp ADDR1 amp ADDRO IOW ICS D12 AD_EN ADDR2 amp ADDR1 IO
9. DUCTORS HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 1 USER S MANUAL REV 2 1 TABLE OF CONTENTS DISCLAIMER a rerit nk nk kd aic nd ndr 2 TABLE OF CONTENT Si csciccsicciexciensdexsncnehensnensdexenenenensnenenensnekshexsnexenetsncssnessnenenecenenes 1 INSTALLATION OF PDIUSBD12 EVALUATION BOARD 2 JENE walo LECA NCIS i pP M 2 System RequireMents e M 2 Installation E EETA TT A E 3 Jumper s setting on PDIUSBD12 ISA bridging board sesseseessseesssreeresreresreeresterrsrerresertesrereserresreersst ren 3 Location of key components on the PDIUSBDI2 evaluation board sse 4 Installation of firmware INF and driver sess nn en entrate seseeccecesnsaeeeeees 5 Using the Host Applet RRRR n 5 HARDWARE DESCRIPTIO N ires pen eeE een pep oen rne nee nEE poen En eER Re on ERRREE oC ne nen ne rREMPE 7 Block S DET Vc RR 7 VO Mapping rr seesodessooneee 7 COMME CONS iM E 8 PAL Equation E E AE E AE A EE EET 9 Address and command decoder
10. PHILIPS Philips Semiconductors Connectivity and Interoperability Solutions PDIUSBD12 Evaluation Board PC Kit User s Manual Rev 2 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com PHILIPS Philips Semiconductors Connectivity and Interoperability Solutions This is a legal agreement between you either an individual or an entity and Philips Semiconductors By accepting this product you indicate your agreement to the disclaimer specified as follows DISCLAIMER PRODUCT IS DEEMED ACCEPTED BY RECIPIENT THE PRODUCT IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW PHILIPS SEMICONDUCTORS FURTHER DISCLAIMS ALL WARRANTIES INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANT ABILITY FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT THE ENTIRE RISK ARISING OUT OF THE USE OR PERFORMANCE OF THE PRODUCT AND DOCUMENTATION REMAINS WITH THE RECIPIENT TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW IN NO EVENT SHALL PHILIPS SEMICONDUCTORS OR ITS SUPPLIERS BE LIABLE FOR ANY CONSEQUENTIAL INCIDENTAL DIRECT INDIRECT SPECIAL PUNITIVE OR OTHER DAMAGES WHATSOEVER INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF BUSINESS PROFITS BUSINESS INTERRUPTION LOSS OF BUSINESS INFORMATION OR OTHER PECUNIARY LOSS ARISING OUT OF THIS AGREEMENT OR THE USE OF OR INABILITY TO USE THE PRODUCT EVEN IF PHILIPS SEMICON
11. VBUS present D12 SUSPEND pin state D12 INT N pin state i o 01 o m o ng Bit description for general output port Bit Usage 0 LED D2 1 lights up LED 1 LED D3 1 lights up LED 2 LED D4 1 lights up LED 3 LED D5 1 lights up LED 4 Reserved 5 Reserved 6 Suspend control 1 forces D12 SUSPEND pin low 7 Interrupt enable 1 enables interrupt Connectors 25 wire connector for PDIUSBD12 evaluation board Pin Type Description 1 POWER VCC 2 POWER GND 3 y o DATA7 4 V O Zero Wait State 5 y o DATAG 6 y o Reserved 7 O DATA5 8 O CLKOUT This line is connected to PDIUSBD12 CLKOUT pin 9 y o DATA4 10 AD_EN This line is the decoder output for address decoding A3 to A9 This signal is active low when PDIUSBD12 evaluation board I O address is selected 11 V O DATA3 12 RESET This line is used to reset or initialize system logic upon power up and is active high 13 y o DATA2 14 IOW This command line instructs an I O device to read the data on the data bus It may be driven by the processor or the DMA controller This signal is active low 15 yo DATA1 16 IOR This command line instructs an I O device to drive its data onto the data bus It may be driven by the processor or the DMA controller This signal is active low 1
12. W amp IOR RESET N RESET IRQ INT_N amp INT EN WAIT OE CS_D12 WAIT RESET RD_N IOR Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 10 USER S MANUAL REV 2 1 Schematics Schematics for PDIUSBD12 evaluation board cc Ct 13 v Bus 5 vec Rt NC al pm ENTIS JA DNE VE wj Ferrite Bead a IT BUS POWERED i aor LL f J2 470P Ceramic v 4 7 TANT 1 veus DB25 d R4 R5 Ut PDIUSBD12 GREEN e 3 D E D 1 2 4 7K 4 7K Bee DATAO ao 38 Aboko u pp E 4 GND 3 4 vec bes DATA VOUT3 3 55 22 1 YY SHIELD 5 6 PX D3 4 DATA2 D 55 7 8 3 DATAS D 53 i UP CONN 9 10 Di 6 GND vcc 23 XIAL2 Yi 6MHz f R3 Ferrite Bead u 12 D5 7 DATA4 XTAL2 55 KTALI H cle 13
13. ate Thursday April 23 1998 Bheet 1 of 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 11 USER S MANUAL REV 2 1 T Je JA VOC Dos GND VCC RESET ZERO WAIT TL sv Lx Bae B4 A4 20K E AV ps A5 AD EN DAG Fe ae RESET VCC 12V O Aanwaaon IOW ZERO WAT gs As 15 16 E 12V vec nofaol TC Ri B9 A9 17 18 GND DACK 10K B10 A10 19 20 MEMW_ B11 A11 21 22 pna MEMR p42 A12 ADDRIS 23 A RQ Jow ADDR18 8 9 18 B13 A13 4 Q7 25 AGA ol aig A14 ADDRI7 y E10 ar 18 df DACKS3 B15 A15 ADDR16 6 Em 11 14 as Shell to GND Ra bie A16 L ADDRIS 5 em 12 12305 DACK1 ADDR14 4 13 9 B17 A17 rra Q3 DRO1 ADDR13 3 14 7 B18 A18 ERES Q2 DACKO ADDR12 2 15 5 B19 A19 E a1 CLOCK ADDR 1 1 16 3 IRQS T B20 A20 Lr X Qo JP1 IRQ Bi A21 ADDRIO IRQ7 0o o IRQS ADDR9 17 JP2 B22 A22 P7 IRO Bs fog ADDRB iR ad B B24 A24 DDR 13 ps IRQ ADDRG Tn DRQ1 B25 A25 P4 o UPB DACK2 ADDB5 8 DROS B26 A26 P3 o JP4 Tc ADDRA 6 DACK1 B27 A27 P2 o O JPS VCC ALE ADDR3 4 DACK B28 A28 Pt DACK3 5 o YPS B29 A29 DDR 2 p ra OSC ADDR GND E A30 ADDRO a 561 A81 ADDRO N s 74HCT688 gt CONATE2 ADDRO 2 v
14. ec vec c2 cA C3 c5 T 4 7u T 0 1 gis 47u J 0 1 Title D12 SA BRIDGNG BOARD size A Document Number D12 ISA 200 Rev 2 00 Date Tuesday February 24 1998 Sheet 1 of 1 Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions USER S MANUAL 09 01 98 Page 12 REV 2 1 Bill of Materials Bill of materials of the PDIUSBD12 evaluation board Item Quantity Reference C2 C1 4 7 TANT C3 C8 C9 C10 C11 C12 C14 C16 0 1 U5 16L8 2 2 8 Ila H C5 47P 4 1 C6 22P 5 1 C7 l6 H C13 470P Ceramic 7 1 C15 1000P 8 H D1 GREEN 9 4 D2 D3 D4 D5 RED HO N J1 UP CONN Hi N J2 12 H J3 H3 l2 JL1 L2 Ferrite Bead 14 1 OSC1 Crystal Oscillator 5 5 R1 R12 R13 R14 R15 470 16 l2 R2 R3 22 1 17 2 R4 R5 4 7K M8 M4 R7 R8 R9 R10 10K 19 1 R11 1K 2o H R16 1M 21 4 S1 S2 S3 S4 SW PUSHBUTTON 22 n S5 BUS POWERED 23 H U1 PDIUSBD12 24 H U2 74LS245 25 H U3 74HCT244 26 H U4 74LS05 H 1 U6 74HCT273 Y1 6MHz Bill of materials of the PDIUSBD12 ISA bridging board Item Quantity Reference Part 1 3 C1 C4 C5 0 1 2 2 C2 C3 4 7u 3 6 JP1 JP2 JP3 JP4 JP5 JP6 JUMPER J1 CON AT62 J2 DB25 RP1 20K R1 10K S1 SW DIP 8 i NTO T
15. logic controls The main endpoints have max packet size of 64 bytes or 128 bytes with double buffering and DMA support So they are suitable for high data rate large size data transfer See the table below for the description of endpoints operations on PDIUSBD12 evaluation board Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 6 USER S MANUAL REV 2 1 Endpoint Endpoint Operations Number Type 1 Generic This pipe is defined as Interrupt In pipe The PDIUSBD12 evaluation In board sends key press release data packet to the host when test keys are pressed or released The firmware uses I O accesses on this endpoint 1 Generic This pipe is defined as Interrupt Out pipe Data packet received from Out host is interpreted as LED control and the D12 evaluation board firmware will light up the corresponding LED The firmware uses I O accesses on this endpoint 2 Main In These pipes are defined as Bulk In Out endpoints Test applet and the Main Out PDIUSBD12 evaluation board supports 3 test modes loop back mode print mode and scan mode The firmware uses DMA for data transfer on these endpoints Main endpoints support 3 different test modes 1 2 3 Scan mode The PDIUSBD12 evaluation board acts like a scanner It sends data packets to the host PC as fast as possible This mode is used to evaluate
16. s we suggest removal of all the unnecessary cards from the device PC Sound card and network card may cause conflict in IRQ and DMA setting JP5 JP6 UH Uo JP1JP2 JP3 JP4 Switch S1 sets the base I O address for the D12 evaluation board Default base address is 0x368 The D12 evaluation board occupies 8 I O locations AO to A2 are decoded on the D12 evaluation board Switch S1 sets the address decoding of A3 to A9 Please notice that a switch ON is logic 0 SW n 1 2 3 4 5 6 7 8 Address X A3 A4 A5 A6 A7 A8 A9 Default OFF OFF ON OFF OFF ON OFF OFF Jumpers JP1 and JP2 set the IRQ number for the D12 evaluation board Default setting is IRQ5 or JP1 is shorted IRQ Number IRQ5 IRQ7 Jumper s Setting JP1 JP2 Default ON OFF Jumpers JP3 to JP6 set the DMA number for the D12 evaluation board Default setting is DMA3 or JP4 and JP6 are shorted Please note that a respective pair of jumpers is needed to set a particular DMA channel DMA Number DMA1 DMAS Jumper s Setting JP3 JP5 JP4 JP6 Default OFF OFF ON ON Possible conflict table Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 4 USER S MANUAL REV 2 1 IRQ or DMA Possible Conflict Number IRQ5 Creative SoundBlaster and compatible so
17. und cards always occupy this IRQ by default If this kind of sound card is installed you should check its settings or remove it Some network cards may also use this IRQ IRQ7 Used by parallel port by default May cause printing problem on device PC DMA1 Creative SoundBlaster and compatible sound cards always occupy this DMA by default If this kind of sound card is installed you should check its settings or remove it DMA3 No conflict Location of key components on the PDIUSBD12 evaluation board D5 D4 D3 D2 0000 See the table below for the list of connectors Connector Descriptions J1 USB upstream connector J2 DB25 data bus connector J3 Extension board connector See the table below for the list of switch and LEDs Name Descriptions S1 S2 S3 S4 Test switches D1 GoodLink LED D2 D3 D4 D5 Test LEDs Philips Semiconductors Asia Product Innovation Centre Visit http www flexiusb com Connectivity and Interoperability Solutions 09 01 98 Page 5 USER S MANUAL REV 2 1 Installation of firmware INF and driver The firmware D12FW EXE runs on the device PC under DOS mode When D12FW starts it lights up test LEDs on the evaluation board for 1 second This means that the I O address setting is correct And the evaluation board is disconnected and re connected to USB by SoftConnect f this is the first
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