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MN101C527 LSI User`s Manual

1. 5 Functions 13 1 5 LCD Driver Wl CD Driver Circuit Block Diagram HNOO EWOO ZIA SSA 0036 19389 6668 18938 WOO IMA 890A 2219 e e e INDIO 10151591 SJOALp UOUMIOS 091 1 1sooq eDeyoA Jopialp k 4 111 no 1 5 eDeyoA 16 09 2 ISIWOO 01502 4 N3001 27 Ee _ ener ee s Dew Heh 4 N3dn pe E B 0 39091 Sore ae 7 219091 0935 1935 22945 M09091 me LS ARM yoye 1ndino 2 5 039091 a Lanao Qe 4 2 lt 27 280 Figure 13 1 1 LCD Driver Circuit Block Diagram Chapter 13 LCD Functions 13 2 Control Registers The LCD is controlled by LCD mode control register 1 LCDMD1 LCD mode control register 2 LCDMD2 LCD output control register 1 LCCTR1 and LCD output control register 2 LCCTR2 The LCD display data is stored in the segment output latch 13 2 1 Registers
2. Bit Symbol Initial Value Description Address Register e 2 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit2 Bit 1 Bit 0 TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 58 2 Timer 2 Binary Counter VI 9 TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BC0 59 TM3BC Timer 3 Binary Counter VI 9 TM20C7 2 6 2 5 2 4 TM2OC3 2 2 2 1 20 0 5 2 2 Compare Register VI 8 7 6 5 4 TM30C3 30 2 0 1 TM30C0 5 TM3OC Timer 3 Compare Register VI 8 TM2ADD2 TM2ADD1 TM2MOD TM2PWM TM2EN 2 2 TM2CK1 TM2CKO X 3F5C TM2MD Position of Pulse Width Timer 2 Timer 2 Clock Source Selection VI 12 Measure Operation Mode Additional Pulse Control Selection Count Control TM3CAS TM3CK2 TM3CK1 TM3CK0 X 3F5D TM3MD Timer 3 Timer 3 Clock Source Selection VI 13 Operation Mode Selection Count Control TM2PSC1 TM2PSCO TM2BAS X 3F5E CK2MD Count Clock Selection V 8 Prescaler Output TM3PSC1 5 0 TM3BAS X 3F5F CK3MD Count Clock Selection V 8 Prescaler Output TM6BC7 TM6BC6 TM6BC5 TM6BC4 TM6BC3 TM6BC2 TM6BC1 TM6BCO X 3F68 TM6BC Timer 6 Binary Counter VIII 5 TM60C7 60 6 TM60C5 TM60C4 TM60C3 TM60C2 TM60C1
3. 2 t SVOSINL _ NAL 10501 0548 Spe 0 0398IA L x 8WMd LNO8SWL RE pn x x X uoneziuouipu s 158 HO88N1 SH n n H X ho Jejunoo u amp uiq 10 91 5 4 n Tm gl n U vul an I N indui OI8NL n peay SSS s i 9 9 N gt n jue e 1ndino snouoJuou s C WEN Jejeoseud W ae 280 LOHISINL 7 4 eoa cnius no Pe 2 zanen 20 4 Indino 559226 1dnu lu A Y 9 qesip ojqeua gt uowesado __ uomeje ELERIN T x x C Latii zu mese JR Im pais Hn eee WMd8N1 6 uoneredo eui d 00ul ESHIBWNL V N39I81_ HONE ides OE 903081 0 1 19181 Lore SBP 0 18 0719181 ZNL peag 1 eade epeoseo ZNL ZW L 9peoseo ZWL OL Figure 7 1 2 Timer 8 Block Diagram VII 4 Overview 7 2 Control Registers Chapter7 16 bit Timers Timer 7 contains the binary counter TM7BC the compare register 1 TM7OC1 with its double buffer preset register 1 TM7PR1 the compare reg
4. Bit Symbol Initial Value Description Address Register f Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM8ICL7 TM8ICL6 TM8ICL5 TM8ICL4 TM8ICL3 TM8ICL2 TM8ICL1 TM8ICL0 X 3F86 TM8ICL Timer 8 Input Capture Register Lower 8 Bit VII 9 TM8ICH7 TM8ICH6 TM8ICH5 TM8ICH4 TM8ICH3 TM8ICH2 8 TM8ICH0 X 3F87 TM8ICH Timer 8 Input Capture Register Upper 8 Bit VII 9 RESERVED TM8CAS TM8CL TM8EN TM8PS1 TM8PSO TM8CK1 8 0 X 3F88 TM8MD1 Set 7 8 Timer Output 8 Count Clock Selection Clock Source Selection VII 12 ur Cascade Reset always 0 Control Control Count Control TM8ICEDG RESERVED TM8BCR TM8PWM TMBIRS1 TM8ICEN TM8ICT1 TM8ICTO 3F89 TM8MD2 i Set Timer 8 Timer Timer8 Input Capture i lecti VII 1 iid Capture Trigger anu Counter Clear Output Wavelorm Interrupt Factor Operation Capture Trigger Selection Edge Selection always 0 Factor Selection Selection Selection Enable P21IM NF1SCK1 NF1SCK0 NF1EN NFOSCK1 NFOSCKO NFOEN X 3F8E NFCTR ACZ Input IRQ1 Noise Filter IRQ1 Noise IRQ0 Noise Sampling IRQ0 Noise IIl 40 5 Filter Filter Operation Enable Sampling Cycle Selection Operation Setup Cycle Selection Setup EDGSEL2 X 3F8F EDGDT Set IRQ2 both edge III 41 Interrupt always 0 Operation Setup SCOCE1 SCOREN SCOTRN SCODIR SCOSTE SCOLNG2 SCO
5. Oscillation stabilization wait DLYS1 DLYSO period setting 4 0 fs 214 1 05 210 1 01 26 1 15 22 Note After reset is released the oscillation stabilization wait period is fixed at fs 210 Buzzer output BUZS2 BUZS1 BUZSO frequency selection 4 0 fosc 214 1 fosc 213 0 0 fosc 21 1 fosc 2 0 0 fosc 210 1 1 fosc 29 0 fx 24 1 1 fx 23 BUZOE 06 output selection 0 port output 1 P06 buzzer output Figure 2 6 4 Osillation stabilization wait time control register DLYCTR x O3F03 R W mControl the Osillation Stabilization Wait Time At recovering from STOP mode the bit 3 2 DLYS1 DLYSO of the oscillation stabilization wait time control register can be set to select the oscillation stabilization wait time from 214 210 2 2 x system clock The DLYCTR register is also used for controlling of buzzer functions t Chapter 10 Buzzer At releasing from reset the oscillation stabilization wait time is fixed to 219 x system clock System clock is controlled through the CPU mode control register CPUM Table 2 6 1 DLYS1 DLYSO Oscillation stabilization wait time Oscillation Stabilization Wait Tim II 28 Reset 3 Interrupts Chapter 3 Interrupts 3 1 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corresponding interrupt service routine
6. Rating Parameter Symbol Conditions Unit MIN TYP MAX VO pin 5 P70 to P77 62 Input high voltage 1 0 8 63 high voltage 2 Vpp24 5 V to 5 5 V 0 7 Vpp V 64 low voltage 1 0 0 2 Vpp 65 low voltage 2 Vop 4 5 V to 5 5 V 0 0 3 Vpp 66 Input leakage current lia ViN 0 V to t 10 67 Input current 1 Man D reso X 30 100 300 uA Vpp 5 0 V Vin 3 5 V 68 Input current 2 ILis Pula eter ON 30 100 300 69 Output high voltage Vpp 5 0 V 0 5 mA 4 5 70 low voltage VoL13 Vpp 5 0 V lo 21 0 mA 0 5 VO pin 6 P80 to P87 71 Input high voltage 1 15 0 8 72 Input high voltage 2 4 5 V to 5 5 0 7 Vpp Vpp V 73 low voltage 1 115 0 0 2 74 Input low voltage 2 ViL16 4 5 V to 5 5 V 0 0 3 75 Input leakage current lis ViN 0 V to t 10 E z uA 76 Input high current 15 Hin DISSE ON 30 100 300 77 Output high voltage VoHts 5 0 V lou 0 5 mA 4 5 78 Output low voltage VoLt5 Vpp 5 0 V 0 1 0 mA 0 5 Boost output pin 1 Vici Vic2 boost output 79 Vpp 3 V 1 5 V 4 3 4 5 4 7 Output voltage LCD OFF V 80 Vice SEG COM pins no load 2 8 3 0 3 2 Display output pin 1 COMO to COM3 81 Ricom1 Vpp 5 V 0 5 V 3 6 Output impedance 82 Vpp 3 V 0 3 V 8 15 Display output 2
7. P50 LEDO TMOO P51 LED1 TM7O Port 5 4 9 521 02 20 lt P53 LED3 TM8O Figure 4 1 1 Port Functions IV 2 Overview Chapter 4 Ports 4 1 2 I O Port Status at Reset Table 4 1 1 I O Port Status at Reset Single chip mode Port Name VO mode Pull up Pull down resistor VO port special functions Port 0 Input mode No pull up resistor VO port Port 1 Input mode No pull up resistor VO port Font Mpu MODE A Caer VO p r Port 3 Input mode No pull up resistor VO port Port 5 Input mode No pull up resistor VO port Port 6 Input mode No pull up pull down resistor port Port 7 Input mode No pull up pull down resistor VO port Port 8 Input mode No pull up resistor VO port Port A Input mode No pull up pull down resistor port The values of pull up pull down resistors should be caluculated in following ways based on the electrical characteristics in LSI User s Manual of each model How to determine pull up resistor value ex When pins maintain the low level guaranteed performance not 0 V as specified in the electrical characteristics and at Vpp 5 V VIN 1 5 V input current is min 30 uA typ 100 max 300 uA means current passing from microcontroller When convert above values to resistor value typ 35 Note that this value varies wildely depending on the temperature In tem
8. Luo uou s zx I XJ JejeoseJg ZADONL LMOOIALL OMOOWL Indu OIOIA L Timers 0 and 1 Block Diagram Figure 6 1 1 VI 3 Overview Chapter 6 8 bit Timers Timers 2 and Block Diagram 2 OWMd 1ndino OIZNL zx sind euon ppy 1ndino snououuou s OYIEWL 140 4 0 108 4 158 16 01 indino 21 x n N peoy 198 JgENL Jejunoo 1Iq g yew OOSWL 1 15 luwpe tu N3 N1 SVOEWL ZADENL Jaysi6e1 luwpe 9u dols qunod 20 2 luoI4yoUAS ndu OIEIALL X JejeoseJd OMOEIALL OMOcCIA L Figure 6 1 2 Timers 2 and 3 Block Diagram Overview VI 4 Chapter 6 8 bit Timers mRemote Control Carrier Output Block Diagram Remote control carrier output TMOIO output RMDT
9. SCOTIR Interrupt request flag 0 No interrupt request Generate interrupt request SCOTIE Interrupt enable flag 0 Disable interrupt Enable interrupt SCOT SCOT LV1 LV0 Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 16 Serial 0 Interrupt Control Register 2 SCOTICR x 03FF6 R W HI 32 Control Registers Chapter 3 Interrupts A D Conversion Interrupt Control Register ADICR The A D conversion interrupt control register ADICR controls interrupt level of A D conversion interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 AD AD ADICR ADIE ADIR At reset 0 0 0 0 ADIR Interrupt request flag 0 No interrupt request Generate interrupt request ADIE Interrupt enable flag 0 Disable interrupt Enable interrupt AD AD LV1 LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt level flag Figure 3 2 17 A D Conversion Interrupt Control Register ADICR R W Control Registers III 33 Chapter3 Interrupts 33 Exter
10. 2 0 4 gt 1000 1111 BLE label if VFANF ZF 1 PC 5 d1 t label if VFANF ZF 0 PC 5 PC 1001 1111 BGT label XIV 16 if VEANF ZF 0 PC 5 d7 label H gt PC if VF NF ZF 1 PC 5 gt PC Instruction Set 0010 0010 0001 74 2 3 d4 sign extension d7 sign extension d11 sign extension Chapter 14 Appendices MN101C SERIES INSTRUCTION SET Mnemonic Operation Machine Code i 6 7 8 BGT label F ZF 0 PC 6 d11 label H PG if VF NF ZF 1 PC 6 gt PC BHI label it CFIZF 0 PC 5 d7 label H gt PC 5 34 0010 0010 0010 lt d7 2 if CFIZF 1 PC 5PC BHI label if CFIZF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0010 dii a if CFIZF 1 6 BLS label if CFIZF 1 PC 5 d7 label HPC 5 3 4 0010 0010 0011 lt 7 H 2 if CFIZF 0 5 BLS label if CFIZF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0011 dii a if CFIZF 0 6 BNC labe if NF 0 PC 5 d7 label H gt PC 5 3 4 0010 0010 0100 d7 2 if NF 1 PC 5PC BNC labe if NF 0 PC 6 d11 label H PC 6 3 4 0010 0011 0100 dii
11. 6 7 0001 001H d 6 gt 4 PC 6 bp15 8 mem8 SP 1 PC 6 H gt mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 6 0 17 16 8 5 2 0 1 0 PC 6 d16 label H3PC JSR label SP 3 9SP PC 7 bp7 0 gt mem8 SP 7 8 0011 1001 1aaH abs 18 b 15 0 gt 5 PC 7 bp15 8 mem8 SP 1 PC 7 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 7 bp17 16 mem8 SP 2 bp1 0 abs18 label H5PC JSRV tbl4 SP 3 9SP PC 3 bp7 0 smem8 SP 3 9 1111 1110 lt t4 gt PC 3 bp15 8 mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 3 bp17 16 gt mem8 SP 2 bp1 0 mem8 x 004080 tbl4 lt lt 2 PC bp7 0 mem8 x 004080 tbi4 lt lt 2 1 PC bp15 8 mem8 x 004080 tbl4 lt lt 2 2 bp7 PC H mem8 x 004080 tbl4 lt lt 2 2 bp1 0 gt PC bp17 16 NOP NOP 2 2 110 0000 0000 1 47 sign extension 2 411 sign extension 8 412 4 416 sign extension 5 aa abs18 17 16 XIV 18 Instruction Set 101 SERIES INSTRUCTION Operation mem8 SP PC bp7 0 mem8 SP 1 PC bp15 8 mem8 SP 2 bp7 PC H mem8 SP 2 bp1 0 PC bp17 16 SP 3 SP 0000 0001 Machine Code Chapter 14 Appendices mem8 SP gt PSW mem8 SP 1 gt PC bp7 0 8 5 2 gt 15 8 mem8 SP 3 bp7 PC H mem8 SP 3 bp1 0 gt PC bp17 16 mem8 SP 4 HA I mem8
12. At reset 00000000 28 LCD output control register 2 LCCTR2 X 03FDC R W LC2SL0 SEG16 Port 67 selection 0 Port 67 selection 1 SEG16 selection LC2SL1 SEG17 Port 66 selection 0 Port 66 selection 1 SEG17 selection LC2SL2 SEG18 Port 65 selection 0 Port 65 selection 1 SEG18 selection LC2SL3 SEG19 Port 64 selection 0 Port 64 selection 1 SEG19 selection LC2SL4 SEG20 Port 63 selection 0 Port 63 selection 1 SEG20 selection LC2SL5 SEG21 Port 62 selection 0 Port 62 selection 1 SEG21 selection LC2SL6 SEG22 Port 61 selection 0 Port 61 selection 1 SEG22 selection LC2SL7 SEG23 Port 60 selection 0 Port 60 selection 1 SEG23 selection Figure 4 7 3 Port 6 Registers 3 3 Chapter 4 Ports 4 7 3 Block Diagram FX Reset R 0107 uj Pull up pull down resistor control DQ Write ck N Z Read R FLOAT bp4 Pull up pull down resistor selection D Q 1 Write CK Read Reset P6DIRO to 7 gt direction control D Q 8 Write N
13. IM1 to 0 Interrupt mask level Controls maskable interrupt acceptance MIE Maskable interrupt enable 0 All maskable interrupts disabled 1 Enables xxxLVn xxxIE for each interrupt Reserved Setalways 0 Figure 2 1 3 Processor Status Word PSW 8 Overview Chapter2 Basic CPU ZF Zero flag ZF is set to 1 when all bits are 0 in the operation result Otherwise zero flag is cleared to 0 mCarry Flag CF Carry flag CF is set to 1 when carry from or a borrow to the MSB occurs Carry flag is cleared to 0 when no carry or borrow occurs mNegative Flag NF Negative flag NF is set to 1 when MSB is 1 and reset to 0 when MSB is 0 Negative flag is used to handle a signed value WOverflow Flag VF Overflow flag VF is set to 1 when the arithmetic operation results overflow as a signed value Other wise overflow flag is cleared to O Overflow flag is used to handle a signed value iinterrupt Mask Level IM1 and IMO Interrupt mask level IM1 and IMO controls the maskable interrupt acceptance in accordance with the interrupt factor interrupt priority for the interrupt control circuit in the CPU The two bit control flag defines levels 0 to 3 Level 0 is the highest mask level The interrupt request will be accepted only when the level set in the interrupt level flag xxxLVn of the interrupt control registe
14. 2 0 V to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP Power supply fosc lt 20 0 MHz 1 40 C to 70 C 4 5 5 5 2 Vpp2 fosc lt 8 39 MHz 2 7 5 5 Power supply voltage 3 fosc lt 2 00 MHz 20 5 5 4 Vpp4 32 768 kHz 2 0 5 5 5 Voltage for maintaining RAM data Vpps During STOP mode 1 8 5 5 Operation speed 4 6 Vpp 4 5 V to 5 5 V 0 100 7 tc2 Vpp 2 7 V to 5 5 V 0 238 Instruction execution time fs us 8 Vpp 2 0 V to 5 5 V 1 00 9 tea Vpp 2 0 V to 5 5 V 61 Crystal oscillator 1 Figure 1 5 1 10 Crystal frequency fatal 4 5 V to 5 5 V 1 0 20 0 MHz 11 Cu 20 External capacitors pF 12 C12 20 13 Internal feedback resistor Rito 400 Crystal oscillator 2 Figure 1 5 2 14 Crystal frequency fxtai2 32 768 kHz 15 C21 20 External capacitors pF 16 C22 20 17 Internal feedback resistor Rizo 3 5 MQ 4 tc2 1 OSC1 is the CPU clock 4 is the CPU clock OSC1 XI dn 3 5 400 ka e Typ MN101C 15 o MN101C oscz XO C12 C11 C22 C21 I 18 gt gt feedback resistor is built in Figure 1 5 1 Crystal Oscillator 1 Electrical Characteristics The fe
15. 42 External Interrupts Chapter 3 Interrupts 3 3 5 Both Edges Interrupt Both Edges Interrupt External interrupts 2 Both edges interrupt can generate interrupt at both the falling edge and the rising edge by the input signal from external input pins CPU also can be returned from standby mode Both Edges Interrupt Setup Example External interrupts 2 External interrupt 2 IRQ2 is generated at the both edges of the input signal from P22 pin An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the both edges interrupt 1 Set the EDGSEL2 flag of the both edges EDGDT x SF8F interrupt control register EDGDT to 1 to bp2 EDGSEL2 1 select the both edges interrupt 2 Set the interrupt level 2 Set the interrupt level by the IRQ2LV1 0 flag of IRQ2ICR x 3FE4 the IRQ2ICR register bp7 6 IRQ2LV1 0 10 The interrupt request flag of the IRQ2ICR register may be set so make sure to clear the interrupt request IRQ2IR a Chapter 3 3 1 4 Interrupt flag setup 3 Enable the interrupt 3 Set the IRQ2IE flag of the IRQ2ICR register IRQ2ICR x 3FE4 to 1 to enable the interrupt bp1 IRQ2IE 1 At the both edge of the input signal from P22 pin an external interrupt 2 is generated When the both edge interrupt is selected the interrupt request is generated at the both edge regardless of the REDGn flag of the exte
16. Insert three nop instructions right after the instruction of transition to HALT SLOW modes II 22 Standby Functions Chapter2 Basic CPU 2 5 Clock Switching This LSI select the best operation clock for system by switching clock cycle division rate through program Division rate is determined by both flags of the CPU mode control register CPUM At the highest frequency CPU can be operated in the same clock cycle to the external clock hence providing a wider operating frequency range 7 6 5 4 3 2 1 0 CPUM OSCSEL1 5 HALT 0561 0560 Atreset 1100000 OSCDBL Internal System Clock 0 Standard Input the oscillation clock cycle divided by 2 1 2x speed Input the oscillation clock cycle e 222222220224 42 Division factor NORMAL mode SLOW mode 0 0 1 1 0 1 4 4 1 0 16 16 1 1 64 16 Set always 0 Figure 2 5 1 CPU Mode Control Register CPUM x 03F00 R W CPU 4 1 fosc High frequency g 00 cU 1 4 d System OSCDBL OSC0 16 fs Low frequency x 2 f OSCSEI 1 0 Figure 2 5 2 Clock Switching Circuit Clock Switching II 23 Chapter2 Basic CPU Division factor for OSCSEL1 OSCSEL0 OSCDBL High freq
17. TM2MD bit 6 7 Addend pulse x TM2MD bit 6 7 or o i i additional PWM basic waveform 1 256 pulse width TM2MD bit 6 7 Aa SN additional bit TM2MD bit 6 7 n1 I I additional bit During 4 cycles of the PWM basic waveform additional pulses 1 256 pulse width of PWM basic wave form can be added in any of the periods 0 to 3 Figure 6 6 5 8 bit PWM Output VI 31 Chapter 6 8 bit Timers 6 7 Synchronous Output 6 7 1 Operation When the binary counter of the timer reaches the set value of the compare register the latch data is output from port 6 at the next count clock BSynchronous Output Operation by 8 bit timer Timer 1 Timer 2 The port 6 latched data is output from the port 6 output pin in synchronization with the interrupt request generation by the match of the binary counter and the compare register Only port 6 can perform synchronous output operation and individual bits can be set 8 bit timers that have synchronous output operation are timer 1 and timer 2 Table 6 7 1 Synchronous Output Port Timer 1 Timer 2 Timer 1 Timer 2 Synchronous output port Port 6 Port 6 Timing of Synchronous Outpu
18. 7 x SEQO sss x x Vic2 Vics data Vss 1 2 A electrode 0 COM1 SEG6 1 2 1 2Vucp B electrode 0 COM0 SEG6 1 2 same not lit not lit Figure 13 4 2 LCD Display 1 2 Duty Display XIII 29 Chapter 13 LCD Functions 13 4 4 Setup Example 1 2 duty mSetup example of the LCD 1 2 duty An example of setup procedure to display 8 shaped double figures 23 with both segment signals SEGO to SEG7 and common signals COMO to COM 1 in 1 2 duty 1 2 bias using an external divider resistor is Shown below t Chapter 13 13 4 3 LCD Display 1 2 duty Clock source fosc 4 MHz LDC clock source 05 2 2122 Hz and flame 61 Hz are selected in this example Setup Procedure Description Stop the LCD operation LCDMD1 X 3FD9 bp7 LCDEN 1 Setup the display duty LCDMD1 X 3FD9 bp5 4 LCDDTY1 0 11 Select the LCD clock source LCDMD1 X 3FD9 bp3 0 LCDCK3 0 0100 Select the segment output port pin Select the common output port LCCTR2 X 3FDB bp3 0 LC1SL3 0 LCDMD2 X 3FDA bp5 4 COMSL1 0 1111 11 Setup the LCD panel display data Segment output latch SEG1 0 2 00 X 31 Segment output latch X2bE01 X 22 Segment output latch 2 02 X 30 Segment output latch 2 03
19. TT b 1 3 duty 1 3 bias 1 4 duty 1 3 bias 2 V Vicp 3 V 3 2 and 1 2 times voltage booster 101 527 Voo Input 2 V reference voltage pue 8 V Vic Vien 2 V 1 V Vics 4 Vss CP 1 T 2 c Static 1 2 duty 1 2 bias Vpp 2 5 V Vicp 5 V 2 times voltage booster MN101C527 VoD ieee 112 Input 2 5 V reference voltage P Gace 5 Vict Vicb 2 5 V Vico 4 Cv 2 5 V Vica eddie mer Vss CP Ci EF m Tr C2 Figure 13 3 6 Operation XIII 19 Chapter 13 LCD Functions 13 3 4 Frame Cycle mSetup of the LCD frame cycle The clock fosc or fx is divided by the prescaler and supplied as the LCD clock Set the LCD clock with bit0 to 3 and set the LCD frame cycle with bit4 to 5 of the LCDMD1 register Table 13 3 4 shows reference input frequencies and the matching of the LCD clock and the LCD frame cycle Table 13 3 4 Input Frequency and the LCD Clock Input frequency Input clock Duty 20 MHz 16 MHz 8 MHz 4 MHz 32 768 kH
20. A D Conversion Starting Setup A D conversion starting is set with the ANST flag of the ANCTR2 register The ANST flag of the ANCTR2 register is set to 1 to start A D conversion Also the ANST flag of the ANCTR2 register is set to 1 during A D conversion then cleared to 0 as the A D conversion complete interrupt is generated Table 12 3 5 A D Conversion Starting ANST A D conversion activation factor 1 A D conversion started or in progress 0 A D conversion completed or stopped Operation XII 11 Chapter 13 A D Converter 12 3 2 Setup Example of A D Converter Setup by Registers A D conversion is started by setting registers The analog input pins are set to ANO the converter clock is set to fs 4 and the sampling hold time is set to TAD x 6 Then A D conversion complete interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Setthe analog input pin PAIMD x 3F3A bpO PAIMDO 1 PAPLUD x 3F4A bpO PAPLUDO 0 2 Select the analog input pin ANCTR1 x 3FB1 bp2 0 ANCHS2 0 000 ANCTRO x 3FB0 bp5 4 ANCK1 0 01 4 Setthe sample and hold time ANCTRO x 3FBO bp7 6 ANSH1 0 01 5 Setthe interrupt level ADICR x 3FFA bp7 6 ADLV1 0 00 6 Enable the interrupt ADICR x 3FFA bp1 ADIE 1 7 A D ladder resistance ANCTRO x 3FB0 bp3 ANL
21. Instruction queue Stores up to 2 bytes of pre fetched instructions Instruction decoder Decodes the instruction queue sequentially generates the control signals needed for instruction execution and executes the instruction by controlling the blocks within the chip Instruction execution controller Controls CPU block operations in response to the result decoded by the instruction decoder and interrupt requests ALU Executes arithmetic operations logic operations shift operations and calculates operand addresses for register relative indirect addressing mode Internal ROM RAM Assigned to the execution program data and stack region Address register Stores the addresses specifying memory for data transfer Stores the base address for register relative indirect addressing mode Data register Holds data for operations Two 8 bit registers can be connected to form a 16 bit register Interrupt controller Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing Bus controller Controls connection of CPU internal bus and CPU external bus Includes bus usage arbitration function Internal peripheral functions Includes peripheral functions timer serial interface A D converter D A converter etc Peripheral functions vary with model Figure 2 1 1 Block Diagram and Function Overview 2 Basic CPU
22. SC0ODC register a SCOODCO flag Reget R POPLUO Pull up resistor control gt Write jCK N Z Read Reset PODIRO direction control DQ e Write Read Y 4 3 POOUTO 5 Port output data DQ s alas 1 5 Write CK Read x 7 7 POINO Port input data N Serial 0 data input Serial 0 transmission data output SC0MD1 register 5 05 5 flag Figure 4 2 2 Block diagram P00 Re Bese POPLU1 Pull up resistor control D Q D E Write A Read o Rese R PODIR1 I O direction control DQ bb gt 2 Write 4CK N Z Read 3 E Y DX Por POOUT1 A Port output data D Fi Write Read 777 Port input data N NA Serial 0 reception data input Figure 4 2 3 Block diagram 01 IV 8 0 SCOODC register SCOODC flag Chapter 4 Ports ANN N N Reset k POPLU2 Pull up resistor control DQ T gt Write CK Read Reset V O direction control Da FODIBE gt Write JcK lt Read e P02 Y HX 8 2 0 1
23. 6 3 0001 0100 abs 8 lt 8 gt MOV imm8 abs12 imm8 mem8 abs12 7 3 0001 0101 abs 12 gt lt 8 gt MOV imm8 abs16 imm8 mem8 abs16 9 5 0011 1101 1001 lt abs 16 gt HB gt Dn HA Dn mem 8 HA 2 2 1101 00Dn MOVW MOVW An DWm mem16 An gt DWm 2 3 1110 00 MOVW mem16 An Am 314 0010 1110 10 4 MOVW d4 SP DWm mem16 d4 SP gt DWm 8 3 1110 011d lt d4 gt 2 MOVW d4 SP Am mem16 d4 SP gt Am 313 1110 010 lt d4 gt 72 MOVW d8 SP DWm mem16 d8 SP gt DWm 5 4 0010 1110 0114 lt 8 gt 3 MOVW d8 SP Am mem16 d8 SP gt Am 5 4 0010 1110 010a lt 8 gt 3 MOVW d16 SP DWm mem16 d16 SP gt DWm 7 5 0010 1110 0014 lt d16 gt MOVW d16 SP Am mem16 d16 SP 5Am 7 1 5 0010 1110 000a di 6 gt MOVW abs8 DWm mem16 abs8 DWm 4 3 1100 0114 lt abs 8 gt MOVW abs8 Ai mem16 abs8 5Am 4 3 1100 010 lt abs 8 gt MOVW abs16 DWm meml6 abs16 gt DWm 7 5 0010 1100 0114 lt abs 16 m MOVW abs16 Am mem16 abs16 5Am 7 5 0010 1100 010 lt abs 16 m MOVW DWn Am DWn mem16 Am 2 3 1111 00aD MOVW gt 16 31 4 0010 1111 10 4 MOVW DWn d4 SP DWn mem16 d4 SP 3 3 1111 0110 lt d4 gt 22 MOVW An d4 SP 16 84 5 pepe 1111
24. LCD PANEL LCD ON COM S SEG S COM S SEG S SEG N COM N SEG N LCD OFF LCD clock Data 1 Vict Vica Vss COM undefined undefined Vict Vics Vss SEG Vico COM SEG 1 8Vicp 1 3Vicp Vicp Lit Not lit Not lit Not lit Not lit S selective voltage N non selective voltage VLco LCD driver voltage 36 Display LCD Functions Chapter 13 frame cycle gt O COM2 1 Vss ERIT Vici Vice Vica COMO SEG3 1 3Vucp A electrode 1 3 COM3 SEG3 1 3 B electrode COM1 SEG3 1 3 Figure 13 4 4 LCD Display 1 4 XIII 37 Display Chapter 13 LCD Functions 13 4 8 Setup Example 1 4 duty mSetup example of the LCD 1 4 duty An example of setup procedure to display 8 shaped 2 figures 23 with both segment signals SEGO to SEG3 and common signals COMO to COM3 in 1 4 duty 1 3 bias using an external divider resistor is shown below t Chapter 13 13 4 7 LCD Display 1 4 duty Clock source fosc 4 MHz LDC clock source fosc 2 5 2122 Hz and flame cycle 31 Hz are selected in this exmple Setup Procedure
25. Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 TM7EN 0 2 Set the special function pin to output mode P1OMD x 3F2F bp4 PIOMD4 1 P1DIR x 3F31 bp4 P1DIR4 1 3 Set the PWM output TM7MD2 x 3F79 bp4 TM7PWM 1 4 Set the high precision PWM output 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop timer 7 counting Set the P1OMD4 flag of the porti output mode register P1OMD to 1 to set the p14 as special function pin Set the P1DIR4 flag of the porti direction control register P1DIR to 1 for output mode Add pull up pull down resistor if necessary Chapter 4 I O Ports Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 to 1 to select the PWM output Set the TM7BCR flag of the TM7MD2 register operation to 1 to select the 7 1 compare match TM7MD2 x 3F79 as a clear source of binary counter bp5 TM7BCR 1 Also set the T7PWMSL flag to 1 to select the bp6 T7PWMSL 1 TM7OC2 compare match as a duty select source of the PWM output 34 16 bit High Precision PWM Output Chapter 7 16 bit Timers Setup Procedure Description 5 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 01 6 Set the PWM output cycle TM7PR1 x 3F75 x 3F74 x 61a7 7 Set the period of the PWM output TM7PR2 x 3F7D
26. TMnEN T flag A Compare register 1 Compare register 2 M Yeon ele eye counter PWM source waveform A TM7IO output PWM output Setup time for compare register 2 PWM basic component Setup time for compare register 1 Figure 7 7 1 Count Timing of High Precision PWM Output at Normal PWM source waveform A shows H until the binary counter reaches the compare register from x 0000 B shows L after the TMnOC2 compare match the binary counter then counts up until the binary counter reaches the TMnOC1 compare register is cleared C shows H again when the binary counter is cleared The PWM output from pin is 1 count clock delay of PWM source waveform This is happened to form waveform inside microcontroller to correct the output cycle VII 32 16 bit High Precision PWM Output 7 16 bit Timers ilCount Timing of High Precision PWM Output When compare register 2 is x 0000 Timer 7 Here is the count timing as the compare register 2 is set to x 0000 Count clock TM7EN flag Compare register 1 Compare register 2 Binary 0000 0000 counter H TM7IO output PWM output L Figure 7 7 2 Count Timing of High Precision PWM Output When compare register 2 is x 0000 0000 When the TMnEN flag is stopped at 0 the PWM output shows H Count Timing of High
27. Chapter 4 I O Port Function 3 Select the normal timer operation 3 Set the TMOPWM flag and TMOMOD flag of TMOMD x 3F54 the TMOMD register to 0 to select the normal bp4 STMOPWM 0 timer operation bp5 TMOMOD 0 4 Select the count clock source 4 Select the clock source to TMOIO input by the TMOMD x 3F54 TMOCK2 0 flag of the TMOMD register bp2 0 2 0 110 5 Set the interrupt generation cycle 5 Set the timer 0 compare register TMOOC the x 3F52 x 04 interrupt generation cycle Counting is 5 so the setting value should be 4 At that time the timer 0 binary counter TMOBC is initialized to x 00 6 Set the interrupt level 6 Set the interrupt level by the TMOLV1 0 flag TMOICR x 3FE9 of the timer 0 interrupt control register bp7 6 TMOLV1 0 10 TMOICR If the interrupt request flag may be already set cancel all existing interrupt requests t Chapter 3 3 1 4 Interrupt Flag Setting 8 bit Event Count VI 21 Chapter6 8 bit Timers Setup Procedure Description 7 Enable the interrupt 7 Set the TMOIE flag of the TMOICR register to TMOICR x 3FE9 1 to enable the interrupt bp1 TMOIE 1 8 Start the event counting 8 Set the TMOEN flag of the TMOMD register to TMOMD x 3F54 start timer 0 bp3 TMOEN 1 Every time detects the falling edge of TM0IO input counts up from x00 When reaches
28. 32 SEG3 2 SEG5 4 SEG7 6 6 Start the LCD operation LCDMD1 X 3FD9 bp7 LCDEN Set 0 to the LCDEN flag of the LCD mode control register 1 LCDMD1 to stop the LCD operation Set 0 to the LCDTY1 0 flag of the LCD mode control register 1 LCDMD1 to set the display duty 1 2 Select fosc 2 5 as the LCD clock source with LCDCK3 to 0 flags of the LCD mode control register 1 LCDMD1 Select SEGO to 7 with the LC1SL3 0 of the output control register LCCTR1 and select COM1 0 with the COMSL1 0 of the LCD mode control register 2 LCDMD2 Display 23 on the display panel with the ad dress X 2E00 to X 2E03 of the segment out put latch SEGO 7 Chapter 13 13 4 3 the LCD display example 1 2 duty Set 1 to the LCDEN flag of the LCD mode control register 1 LCMD1 to start the LCD operation XIII 30 Display Chapter 13 LCD Functions Display XIII 31 Chapter 13 LCD Functions 13 4 5 1 3 Duty 32 Display 1 3 MN101C527 Segment Latch 2 2 02 X 2E02 X 2E01 2 01 2 00 2 00 SEG3 SEG2 A electrode B electrode LCD PANEL LCD ON COM S COM N COM S COM N LCD OFF SEG S SEG S SEG N SEG N LCD clock undefined Data 0 undefined Vict COM Vics H Vss Vici SEG Vica Vss
29. R W Readable Writable R Readable only Control Registers VI 7 Chapter 6 8 bit Timers 6 2 2 Programmable Timer Registers Each of timers 0 to 3 has 8 bit programmable timer registers Programmable timer register consists of compare register and binary counter Compare register is 8 bit register which stores the value to be compared to binary counter are stocked Timer 0 Compare Register TM0OC 7 6 5 4 3 2 1 0 TMOOC 0067 TM0OC6 5 2 TM0OOC1 Atreset X XX XX XXX Figure 6 2 1 Timer 0 Compare Register TMOOC x 03F52 R W 1 Compare Register TM10C 7 6 5 4 3 2 1 0 TM1OC TMIOC7 TM1OC6 TM1OC5 TM1OC4 TM1OC3 TM10C2 TMIOC1 TM1OCO0 Atreset X X XXX XXX Figure 6 2 2 Timer 1 Compare Register TM10OC 03 53 R W 2 Compare Register TM2OC 7 6 5 4 3 2 1 0 TM2OC TM20C7 TM20C6 TM20C5 TM2004 TM2003 TM20C2 20 1 TM20C0 Atreset X X XX X X X X Figure 6 2 3 Timer 2 Compare Register 2 x 03F5A R W 3 Compare Register TM3OC 7 6 5 4 3 2 1 0 3067 30 6 TM3OC5 TM30C4 TM30C3 TM30C2 TM30C1 TM30C0 Atreset X X X X X X X Figure 6 2 4 3 Compare Register TM3OC x 03F5B R W VI 8 Control Registers Chapter 6
30. Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 TM7EN 0 2 Set the special function pin to output mode P1OMD x 3F2F bp4 P1OMDA 1 P1DIR 1 bp4 P4DIRA 21 3 Setthe timer pulse output TM7MD2 x 3F79 bp4 TM7PWM 0 4 Select the condition for timer clear TM7MD2 x 3F79 bp5 TM7BCR 1 5 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop timer 7 counting Set the P1OMDA flag of the port 1 output mode register P1OMD to 1 to set P14 pin as the special function pin Set the P1DIR4 flag of the port 1 direction control register P1DIR to 1 to set output mode Add pull up pull down resistor if necessary Chapter 4 I O Ports Set the TMPWM flag of the timer 7 mode register 2 TM7MD2 to 00 to select the timer pulse output Set the TM7BCR flag of the TM7MD2 register to 1 to select the compare match as a clear source of a binary counter Select fosc as a clock source by the TM7CK1 0 flag of the TM7MD1 register Also select 1 1 frequency as the count clock source by the TM7PS1 0 flag VII 26 16 bit Timer Pulse Output Chapter 7 16 bit Timers Setup Procedure Description 6 Set the timer pulse output cycle 6 Set 1 2 cycle of the timer pulse output TM7PR1 X 3F75 X 3F74 x 00C7 to the t
31. Ve 1 3 1 3VLcp Lit Not lit Not lit Not lit Not lit S selective voltage N non selective voltage LCD driver voltage open LCD Functions Chapter 13 frame cycle COM2 1 COM0 2 5 gt o9 gt T m Se ov gt gt gt 4 _ notli Dues ene eei d eese enge SEG5 data A electrode COM2 SEG5 u 0 9 1 3Vicp Figure 13 4 3 LCD Display 1 3 Duty Display XIII 33 Chapter 13 LCD Functions 13 4 6 Setup Example 1 3 duty mSetup example of the LCD 1 3 duty An example of setup procedure to display 8 shaped double figures 23 with both segment signals SEGO to SEG5 and common signals COMO to COM2 in 1 3 duty 1 3 bias using an external divider resistor is shown below t Chapter 13 13 4 5 LCD Display 1 3 duty Clock source fosc 4 MHz LDC clock source fosc 2 2122 Hz and flame cycle 41 Hz are selected in this example Setup Procedure Description 1 Stop the LCD operation LCMD1 X SFD9 bp7 LCDEN 2 Setup the display duty LCMD1 X 3FD9 bp5 4 LCDDTY1 0 11 3 Select the LCD clock source LCMD1 X 3FD9 bp3 0 LCDCK3 0 4 Select the segment output port pin Select the common output port pin LCC
32. ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am MOV d16 SP Dm MOV d8 SP Dm d16 An D MOV Dn d16 SP MOV Dn d8 SP MOV Dn d16 Am MOVW DWn DWm NOPL n m CMPW DWn DWm ADDUW Dn Am EXT Dn DWm_ AND 8 PSW OR 8 PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm MOV abs16 Dm abs16 Am MOVW abs16 DWm CBEQ 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d12 8 abs8 d7 d11 CBNE 8 abs8 d7 d1 1 MOVW d16 SP Am MOVW d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 Am DIVU MOVW An d16 SP XIV 20 MOVW DWn d16 SP Instruction Map MOVW An d8 SP MOVW DWn d8 SP MOVW An Am ADDW 16 SP MULU Extension code b 0011 2nd nibble 3rd nibble 0 1 2 Chapter 14 Appendices TBZ abs8 bp d1 1 TBNZ abs8 bp d7 TBNZ abs8 bp d11 CMP Dn Dm ADD Dn Dm TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 TBNZ io8 bp d1 1 OR Dn Dm AND Dn Dm BSET io8 bp BCLR io8 bp JMP abs18 label JSR abs18 label Dn Dm 8 Dm ADDC Dn Dm BSET abs16 bp BCLR abs16 bp BTST abs16 bp 8 abst6 mov 8 20910 8 abs16 d7 11 8 abs16 d7 11 TBZ
33. CO CO O O LO LO O OO O O On OR OO QN ee ork 10 st QC C 0n a cC q DODO gt O O O O O O O O 5 0 x R O uc m OD O GO O O O O Vici SEG12 P73 PAB11 OPEN Vicine Vice2 SEG13 P72 10 SEG14 P71 PAB9 OPEN C1 SEG15 P70 8 OPEN C2 SEG16 KEY7 P67 SDO7 PAB7 Vss TM0O LED0 P50 SEG17 KEY6 P66 SDO6 PAB6 Vss TM70 LED1 P51 SEG18 KEY5 P65 SDO5 5 Vss 8 TM20 LED2 P52 MN101CP52A SEG19 KEY4 P64 SD04 PAB4 PAB16 9 TM8O LED3 P53 LCD Version SEG20 KEY3 P63 SDO3 PAB3 Vss 10 Vss SEG21 KEY2 P62 SD02 PAB2 OPEN OSC2 SEG22 KEY1 P61 SDO1 PABI Vss 12 OSC1 SEG23 KEY0 P60 SDO0 Vss MMOD P22 IRQ2 Vss Vss 14 P21 IRQ1 ACZ Vss Vss XO P20 RQO 34 VPP P15 TM8IO Vss 28 RMOUT TMOIO P10 29 TM1IO P11 24 TXD SBO0 P00 30 TM2IO P12 17 NRST P27 19 20 AN1 PA1 21 AN2 PA2 22 25 RXD SBI0 P01 26 SBTO P02 27 BUZZER P06 31 TMGIO P13 32 TMT7IO P14 Vss NOE NCE NPGM Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Figure 14 1 2 EPROM Programming Adapter Connection EPROM Versions XIV
34. CPU control signals Figure 2 1 2 Instruction Execution Controller Configuration Overview 5 2 Basic CPU 2 1 4 Pipeline Process Pipeline process means that reading and decoding are executed at the same time on different instruc tions which are given nonstop Pipeline process realizes speedy processing of consective instructions executions This process is executed with instruction queue and instruction decoder Instruction queue is buffer that fetches the second instruction in advance That is controlled to fetch the next instruction when instruction queue is empty at each cycle on execution At the last cycle of instruc tion execution the first word operation code of executed instruction is stored to instruction register At that time the next operand or operation code is fetched to instruction queue so that the next instruction can be executed immediately even if register direct da or immediate imm are needed at the first cycle of the next instruction execution But on some other instruction such a branch instruction instruction queue becomes empty on the time that the next operation code to be executed is stored to instruction register at the last cycle Therefore only when instruction queue is empty and direct address da or immediate data imm are needed instruction queue keeps waiting for a cycle Instruction queue is controlled automatically by hardware so that there is no need to control by software
35. Operation soe edere en rir X 4 10 3 2 Setup Example nee ent bpm e RE pres X 5 Chapter 11 Serial Interface 0 et dietro ente d tod rette tentes XI 2 11 1 1 Eunctios oet eke ee XI 2 1151 2 Block Diagram oec tht eoe teret toten XI 3 Control Registers 2r e UR re e ho e RR XI 4 11 2 EYES XI 4 11 2 2 Data Butter Registers onec e ref tereti XI 5 11 2 3 Mode Registers eee see nee er tee e in XI 6 Operation nh I ee rh i e EO P eh E eget e es XI 12 11 3 1 Clock Synchronous Serial XI 12 11 3 2 Setup Example i y eek D SIN RIDERS XI 27 11 3 3 Serial Interface XI 30 11 3 4 Setup irent utes dette ebhSepe ete XI 44 Vli contents Chapter 12 A D Converter 12 1 12 2 12 3 Ru ate vie seh eee tu usa ees XII 2 12 11 eene t et mere e tete XII 2 1221 22 Block Diagram Leuten rettet tertie rg eee lees XII 3 Control Registers ciere ore ir qe e recep ete er re P XII 4 122221 Registers iei tree e esee vx suu XII 4 12 2 2 7 Control Registers ione PRU EO REPRE HR XII 5 12 2 3 Data Buffers i ER EORR SERM en XII 7 nu p uu a nis ua Dp Dae
36. RD D e aie epi RENE IV 6 4 2 2 Registers ien e a E Rr REC HERD RE IV 7 4 2 3 Block Diagram uet eR RU PEDES IV 8 ili contents 4 3 Perth A EE EE Uo ue ct oed IV 10 4 3 1 Description 52 eene bete Het retra IV 10 4 3 2 Registers deh Moin ipe ee Bae IV 11 4 3 3 Block Dia Brann eget Regem IV 13 4 4 Port Duss So Hed deena RR IV 14 4 4 1 Descr p on u su up EE RERO kas 14 4 4 2 RGBISICES iir tb eo Nerii tod 15 4 4 3 Block Diagram eerte IV 16 455 IV 17 4 5 1 DURER RIED IV 17 4 5 2 RegisterSs isu spp uapa eee IV 18 4 5 3 Block Diagram teretes IV 20 4 6 e eter e eda IV 21 4 6 1 Description eene ai ete ete eet eite IV 21 4 6 2 REgIStErS c e de ree pe ed eue D dero saa IV 22 4 6 3 Block Diagram ose ee tree e eter 24 27 ORE EU REUNIR IV 25 4 7 1 Description isi peu ete he Real IV 25 4 7 2 Registers nep tende IV 26 4 7 3 Block DIagrTato eet n dieit RE IV 29 4 8 Pott usasapa s IB DUI HU RR ODDO ERR LR EORR IV 30 4 8 1 Description aq a a n er RE Eris IV 30 4 8 2 d IV 31 4 8 3 Block Diagram een oreet e E IV 34 429 P
37. Read Y 4 P60 to P67 0 to 7 M D D JE Port output data 9 DQ x Write 19 N Z Read 2 7 output value store register Synchronous output event gos P6IN0 to 7 1 ort input data e TNU Read Key input interrupt signal Reset Y P6SYO0 to 7 ve Synchronous output control L ite NS Write 4 CK Read Vic2 Segment output control E mm 4 Segment output data pu Vica Y When segment output is selected segment output control automatically sets port I O direction control to Vss input mode and segment output control is set to without pull up resistors Y TS Figure 4 7 4 Block Diagram P60 to P67 IV 29 Chapter 4 Ports 4 8 4 8 1 Description Port Setup Each bit can be set individually to either an input or output by the port 7 I O direction control register P7DIR The control flag of the port 5 direction control register P7DIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 7 direction control register P7DIR to 0 and read the value of the port 7 input register P7IN To output data to pin set the control flag of the port 7 direction control register P7DIR to 1 and write data to the port 7 output register P7OUT Each bit can be set individually if pull up pull down resistor is added or not by the port 7 pull up pull
38. Select the normal operation TMOMD x 3F54 bp4 0 bp5 TMOMOD 0 Select the count clock source TMOMD x 3F54 bp2 0 TMOCK2 0 001 Select the prescaler output and enable the counting CKOMD x 3F56 bp2 1 TMOPSC1 0 01 bpO STMOBAS 1 PSCMD x SF6F bpO PSCEN 1 Set the cycle of the interrupt generation TMOOC x 3F52 x F9 Set the interrupt level TMOICR x 3FE9 bp7 6 TMOLV1 0 10 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the counting of timer 0 Set the TMOPWM flag and TMOMOD flag of the TMOMD register to 0 to select the normal timer operation Select the prescaler output to the clock source by the TMOCK2 0 flag of the TMOMD register Select fs 4 to the prescaler output by the TMOPSC1 0 TMOBAS flag of the timer 0 prescaler selection register CKOMD Also set the PSCEN flag of the prescaler control register PSCMD to 1 to enable the counting of the prescaler Set the value of the interrupt generation cycle to the timer 0 compare register The cycle is 250 so that the setting value is set to 249 9 At that time the timer 0 binary counter is initialized to x 00 Set the interrupt level by the TMOLV1 0 flag of the timer 0 interrupt control register TMOICR 6 Chapter 3 3 1 4 Interrupt flag setting If the interrupt request flag may be already set clear the request flag VI 1
39. Setup Example mTimer Operation Setup Example Timer 7 Timer 8 Timer 7 generates an interrupt constantly for timer function Fosc 2 fosc 20 MHz at operation is se lected as a clock source to generate an interrupt every 1000 cycles 100 us An example setup procedure with a description of each step is shown below Setup Procedure Description Stop the counter TM7MD1 x 3F78 bp4 TM7EN 0 Select the timer clear source TM7MD2 x 3F79 bp5 TM7BCR 1 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 01 Set the interrupt generation cycle TM7PR1 x 3F75 x 3F74 x 03E7 Set the interrupt level TM7ICR x 3FF1 bp7 6 TM7LV1 0 10 Enable the interrupt TM7ICR x 3FF1 bp1 TM7IE 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop timer 7 counting Set the TM7BCR flag of the timer 7 mode register 2 TM7MD2 to 1 to select the compare match as a binary counter clear source Select fosc as a clock source by the TM7CK1 0 flag of the TM7MD 1 register Also select 1 2 fosc as a count clock source by TM7PS1 0 flag Set the interrupt generation cycle to the timer 7 preset register 1 TM7PR1 The cycle is 1000 The set value should be 1000 1 999 x 03E7 At that time the same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter TM7BC is initialized to x 0000 Set the interrup
40. The setting value should be 200 12199 x C7 for 100 kHz to be divided by 20 MHz At that time the timer O binary counter is initialized to x 00 Set the TMOEN flag of the TMOMD register to 1 to start timer O VI 24 8 bit Timer Pulse Output Chapter 6 8 bit Timers counts up from x 00 If TMOBC reaches the setting value of the register then is cleared to x 00 TMOIO output signal is inverted TMOBC restart to count up from x 00 At TMnOC 00 timer pulse output has the same waveform to at x 01 If any data is written to compare register binary counter is stopped timer output is reset to nm Compare register value calculation Timer pulse output cycle i lue 1 Compare registenvalte Selected clock cycle x 2 8 bit Timer Pulse Output VI 25 Chapter 6 8 bit Timers 6 6 8 bit PWM Output The TMnIO pin outputs the PWM waveform which is determined by the match timing for the compare register and the overflow timing of the binary counter 6 6 1 Operation BOperation of 8 bit PWM Output Timers 0 and 2 The PWM waveform with an arbitrary duty cycle is generated by setting the duty cycle of PWM period to the compare register TMnOC The cycle is the period from the full count to the overflow of the 8 bit timer Table 6 6 1 shows PWM output pins Table 6 6 1 Output Pins of PWM Output T
41. VII 20 7 4 1 Operation eee eR bo Reed OT e Rete VII 20 7 4 2 Setup nemis sete ee eo Ante etit iege VII 22 16 bit Timer Pulse Output ee eret e re e perte diee VII 24 7 5 1 Operations ipu sone ederet Od VII 24 7 5 2 Setup Example us Nie tr re ete e e e menn VII 26 16 bit Standard PWM Output Only duty can be changed consecutively VII 28 7 6 1 OperatiOn ica i tet m eite e e Gua ne VII 28 7 6 2 Setup Exampl s tet ee e teme VII 30 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VII 32 7 7 1 Operation iine aet 32 7 7 2 Setup 34 16 bit Timer Synchronous VII 36 7 8 1 ea e D repe oe ia eoa te iaces petis VII 36 7 8 2 Setup Example 5 m Det Opp Rr eei notorie VII 37 16 bit Timer Capture e err VII 39 7 9 1 Operatl ft coton eet ie ed e e edens VII 39 7 9 2 Setup Example eee pe tee eed ederet VII 42 Cascade Connection e A Ite VII 44 7 10 l Operation isis Re eR te VII 44 1 10 2 Example eee tete VII 46 Chapter8 Time Base Timer 8 bit Free running Timer contents
42. gt P60 SEG23 KEYO SDOO lt P61 SEG22 KEY1 SDO1 lt gt P62 SEG21 KEY2 SDO2 63 5 20 5 RMOUT TMOIO P10 lt J lt P64 SEG19 KEY4 SDO4 4 8 P65 SEG18 KEY5 SDO5 lt P66 SEG17 KEY6 SDO6 4 67 5 16 7 50 7 TM1IO P11 TM2IO P12 TMSIO P13 14 4 70 5 15 71 5 14 P72 SEG13 15 0 20 ACZ IRQ1 P21 IRQ2 P22 NRST P27 lt P73 SEG12 P74 SEG11 4 75 5 010 4 76 5 9 4 P77 SEG8 I 16 Block Diagram gt P80 SEG7 lt P81 SEG6 4 P82 SEG5 P83 SEG4 4 84 5 lt 85 5 2 4 86 5 1 P87 SEGO Q o gt gt gt gt LELEFEFE Ww Le uiu uiu _ 28 gt Snags x X gt gt 25 5 Sub clock System clock CPU oscillator oscillator MN101G uU 2 o o A ROM RAM 16 1 5 E 8 bit Timer 0 External interrupt zx v Q 8 bit Timer 1 Serial interface 0 a A 8 bit Timer 2 Time base timer 6 8 bit Timer 3 Watchdog timer 2 16 bit 7 LCD g 16 bit 8 Port3 A D Conversion 88554 Port A 252222 on 009009 5
43. mReception BUSY flag When the start condition is reagrded the SCORBSY flag of the SCOMDS register is set to 1 That is cleared to 0 by the generation of the reception complete interrupt SCORIRQ If the SCOSBIS flag is set to 0 during receptin the SCORBSY flag is reset to O BUSY flag When any data is set to TXBUFO the SCOTBSY flag of the SCOMD3 register is set to 1 That is cleared to 0 by the generation of the transmission complete interrupt SCOTIRQ During continuous communi cation the SCOTBSY flag is always set If the transmission buffer empty flag SOTEMP is set to 0 as the transmission complete interrupt SCOTIRQ is generated the SCOTBSY is cleared to 0 If the SCOSBOS flag is set to 0 the SCOTBSY flag is reset to O iFrame Mode and Parity Check Setup Figure 11 3 15 shows the data format at UART communication frame parity bit 4g character bit Figure 11 3 15 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 11 3 13 shows its kinds to be set Table 11 3 13 UART Serial Interface Transmission Reception Data Start bit 1 bit Character bit 7 8 bits Parity bit fixed to 0 fixed to 1 even odd none Stop bit 1 2 bits XI 32 Operation Chapter 11 Serial Interface 0 The SCOFM1 to 0 flag of the SCOMD2 registe
44. 27 Chapter3 Interrupts 3 1 3 2 3 3 OVerVIeW on edo S eir ap SG epp doi II 2 3 1 1 F nctions eat eh tek edu Aie ade e te III 3 3 1 2 Block Diagram onmi pre III 4 3 1 3 Operation iue eet e peer tiere tees be eet ee eaten 5 3 1 4 Interr pt Flag Set p 2 ree eie fees edens III 14 Control Registers eee RU ERG Ete III 15 3 2 1 Registers Dist 2e nee aee e E es III 15 3 2 2 Interrupt Control Registers III 16 External Interrupts ete et tsp III 34 3 3 1 OVERVIEWS ad OU nup ER Or oM tg III 34 3 3 2 Block Diagram etn eres III 35 3 3 3 Control Registers 2001 III 38 3 3 4 Programmable Active Edge Interrupt eese III 42 3 3 5 Both Edges Interrupt s eter metet t III 43 3 3 6 Key Input Interrupt azu tert etre e erred III 45 3 3 7 Noise e etit eed III 47 3 3 8 AC Zero Cross Detector essere rennen III 50 Chapter 4 I O Ports 4 1 4 2 OV ELVIS W M IV 2 4 1 1 W O Port Diagram pee iced IV 2 4 1 2 LO Port Status at Reset IV 3 4 1 3 Control Registers neenon eot editore bo ie Ode IV 4 Ports ies did IV 6 4 2 1 D Scrptlon
45. 7 16 bit Timers 7 2 2 Programmable Timer Registers Timer 7 and Timer 8 each have a set of 16 bit programmable timer registers which contains a compare register a preset register a binary counter and a capture register Each register has 2 sets of 8 bit register Operate these registers by 16 bit access A compare register is a 16 bit register which stores comparative value of compare register and binary counter Comparative value written to the preset register in advance is loaded to the register mTimer 7 Compare Register 1 TM7OC1 7 6 5 4 3 2 1 0 TM7OC1L 700117 IM OC1L6 TM OC1L5 TM7OC1L4 TM7OC1L3 TM70C1L2 TM7OC1L1 700110 At reset X X X X XXXX Figure 7 2 1 Timer 7 Compare Register 1 Lower 8 bits TM7OC1L 0 72 7 6 5 4 3 2 1 0 TM7OC1H TM OCtH7 T OCtH6 1 5 TM7OC1H4 TM7OC1H3 TM70C1H2 7 1 1 TM7OC1HO Atreset XX X XX XXX Figure 7 2 2 Timer 7 Compare Register 1 Upper 8 bits TM7OC1H x 03F73 R mTimer 7 Compare Register 2 TM7OC2 7 6 5 4 3 2 1 0 TM7OC2L 70 217 TM70C2L6 TM70C2L5 TM7OC2L4 TM70C2L3 TM70C2L2 TM7OC2L1 TM OC2L0 Atreset X X X X XXXX Figure 7 2 3 Timer 7 Compare Register 2 Lower 8 bits TM7OC2L x O3F7A R 7 6 5 4 3 2 1 0 TM7OC2H TM OC2H7 TM7OC2H6 TM7OC2H5 TM7OC2H4 TM7OC2H3 TM7OC2H2 TM70C2H1 TM7OC2H0 Atr
46. Chapter 4 Ports 4 7 2 P6OUT P6IN P6DIR P6PLUD Registers 7 6 5 4 3 2 1 0 P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 PeOUTO Atreset XXXXXXXX P6OUT Output data 0 Low Vss level is output 1 High level is output Port 6 output register PEOUT x 03F16 R W 6 5 4 3 2 P6IN7 P6IN6 P6INS P6IN4 P6IN3 P6IN2 P6IN1 P6INO 7 Port 6 intput register P6IN 03 26 R 6 5 4 At reset X XXX XXXX 3 2 1 0 P6DIR7 P6DIR6 P6DIRS P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIRO 7 Port 6 direction control register P6DIR x 03F36 R W 6 5 4 P6IN Input data 0 Pin is Low Vss level 1 Pin is High Vpp level Atreset 00000000 3 2 1 0 P6PLUD7 P6PLUD6 P6PLUD5 P6PLUD4 P6PLUD3 P6PLUD2 P6PLUD1 P6PLUDO 26 P6DIR I O mode selection 0 Input mode 1 Output mode Atreset 00000000 P6PLUD Pull up pull down resistor selection 0 No pull up pull down resistor 1 Pull up pull down resistor Port 6 pull up pull down resistor control register x 03F46 R W Figure 4 7 1 Port 6
47. Description 1 Stop the LCD operation LCMD X 3FD9 bp7 LCDEN ll Setup the display LCDMD1 X 3FD9 bp5 4 LCDDTY1 0 00 Select the LCD clock source LCDMD1 X 3FD9 bp3 0 LCDCK3 0 0100 Select the segment output port pin Select the common output port pin LCCTR1 X 3FDB bp3 2 iC1SL3 2 11 LCDMD2 x 3FDA 161611 1 bp7 4 COMSL3 0 1111 Setup the LCD panel display data Segment output latch SEG1 0 X 2bE00 Segment output latch SEG3 2 X 2E01 Start the LCD operation LCDMD1 X 3FD9 bp7 LCDEN Set 0 to the LCDEN flag of the LCD mode control register 1 LCDMD1 to stop the LCD operation Set the display duty 1 4 with the LCODTY1 0 flag of the LCD mode control register 1 LCDMD1 Select fosc 2 gt as the LCD clock source with LCDCKS to 0 flags of the LCD mode control register 1 LCMD1 Select SEGO to 3 with the LS1SL3 2 of the output control register 1 LCCTR1 and select COM3 0 with the COSL3 0 of the LCD mode control register 2 LCDMD2 Display 23 on the display panel with the ad dress X 2E00 to X 2ED1 SEGO 3 6 Chapter 13 13 4 7 the LCD display example 1 4 duty Set 1 to the LCDEN flag of the LCD mode control register 1 LCDMD1 to start the LCD operation 38 Display Chapter 14 Appendices Chapter 14 Appendices 14 1 EPROM Version 14 1 1 Overview The EPROM version is equivalen
48. Needs to be set before interrupt request flag is cleard 7 Clear the interrupt request flag IRQnIR 0 8 Disable the interrupt flag to be writen by software IRWE 0 9 Enable the interrupt IRQnIE 1 10 Enable all the maskable interrupt 1 44 External Interrupts Chapter 3 Interrupts 3 3 6 Key Input Interrupt Key Input Interrupt External interrupt 4 This LSI can set port 6 P60 to P67 pin by 1 bit to key input pin Key input interrupt can generate an interrupt at the falling edge if at least 1 key input pin outputs low level Key input pin should be pull up in advance External Interrupts 45 3 Interrupts Key Input Interrupt Setup Example External interrupt 4 After P60 to P63 of port 6 are set to key input pins and key is input low level the external interrupt 4 IRQ4 is generated An example setup procedure with a description of each step is shown below Setup Procedure Description Set the key input pin to input P6DIR x 3F36 bp3 0 P6EDIR3 0 0000 Set the pull up resistance P6PLUD x 3F46 bp3 0 P6BPLU3 0 1111 FLOAT x 3F2E bp3 P6RDWN 0 Select the key input P6IMD x 3F3E bp3 0 0 1111 Set the interrupt level IRQ4ICR x 3FE6 bp7 6 IRQ4LV1 0 10 Enable the interrupt IRQ4ICR x 3FE6 bp1 IRQ4IE 1 Set the P6DIR3 0 flag of the port 6 direction control register P6DIR to
49. Pana NSeries TheOnetoWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER MN101C 101 527 LSI User s Manual Pub No 21452 034E Panasonic Series is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations 2 3 4 5 Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The contents of this book are subject to change without notice in matters of improved function When finalizing your design therefore ask for the most up to date version in advance in order to check for any changes We are not liable for any damage arising out of the use of the contents of this book or for any infringement of patents or any other rights owned by a third party No part of this book may be reprinted or reproduced by any means without written permission from our company This book deals with standard specification Ask for the latest individual Product Standards or Specifications in advanc
50. Parity enable 0 Enable parity bit 1 Disable parity bit Added bit specification SCOPM1 SCOPMO 7 Transmission Reception 0 0 Add 0 Check for 0 Add 1 Check for 1 0 Addodd parity Check for odd parity 1 Add even parity Check for even parity SCOFM1 SCOFMO Frame mode specification 7 data bits 1 stop bit 7 data bits 2 stop bits 8 data bits 1 stop bit 8 data bits 2 stop bits OO o Figure 11 2 5 Serial Interface 0 Mode Register 2 SC0NMD2 x 03F92 R W XI 8 Control Registers mSerial Interface 0 Mode Register SC0MD3 All flags are only for reading SC0MD3 Chapter11 Serial Interface 0 7 6 5 4 3 2 1 0 SCOTBSY SCORBSY SCOTEMP SCOREMP SCOFEF SCOPEK SCOORE SCOERE At reset 00000000 SCOERE Error monitor flag 0 No error 1 Error SCOORE Overrun error detection 0 No error 1 Error SCOPEK Parity error detection 0 error 1 Error SCOFEF Framing error detection 0 No error 1 Error SCOREMP Receive buffer empty flag 0 Empty 1 Full SCOTEMP Transfer buffer empty flag 0 Empty 1 Full SCORBSY Serial bus status 0 Other use 1 Serial reception in progress SCOTBSY Serial bus status 0 Other use 1 Serial transmis
51. Port output data D U gi Write Ck N Z Read 1 x 77 POIN2 Port input data M AY Serial 0 clock input Serial 0 clock output SCOMD register SCOSBTS flag Figure 4 2 4 Block diagram 02 aw Reset Pull up resistor control Do POPLU6 gt gt Write Read Reset PODIR6 direction control Da gt gt Write Read V P06 E POOUT6 0 M 04 5 Port output data 2 D Q U P a Write 4CK Read X 7 7 POING i Port input data Read NJ Buzzer output DLYCTR register bp7 Figure 4 2 5 Block diagram P06 Port 0 IV 9 Chapter 4 Ports 4 3 Port 1 4 3 1 Description Port Setup Each bit can be set individually as either an input or output by the port 1 I O direction control register P1DIR The control flag of the port 1 direction control register P1DIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 1 direction control register P1DIR to 0 and read the value of the port 1 input register To output data to pin set the control flag of the port 1 direction control register P1DIR to 1 and write the value of the port 1 output register P1 OUT Each bit can be set individually if pull up resistor is added or not with the port 1 pull up resistor control register P1PLU Set the control flag of the port 1 pull up resistor control register P1PLU to 1 to add pull up resis
52. Read ee 5 to Port output data E gt Write L N Z Read 7 7 to Port input data Read one Vici Vice Common output control y gt Common output data Vics Y When common output is selected common output control automatically sets port I O direction control to input mode and common output is set to without pull up resistors Vss EAM Figure 4 5 3 Block Diagram P30 to P33 IV 20 Port3 P30 to P33 Chapter 4 Ports 4 6 Port 5 4 6 1 Description Port Setup Each bit can be set individually to either an input or output by the port 5 I O direction control register P5DIR The control flag of the port 5 direction control register P5DIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 5 direction control register P5DIR to 0 and read the value of the port 5 input register To output data to pin set the control flag of the port 5 direction control register P5DIR to 1 and write data to the port 5 output register Each bit can be set individually if pull up resistor is added or not by the port 5 pull up resistor control register PBPLU Set the control flag of the port 5 pull up resistor control register PBPLU to 1 to add pull up resistor li Special Function Pin Setup
53. TM2BC counts up from 00 If any data is written to the port 6 output register PGOUT the data of port 6 is output from the synchronous output pin in every time an interrupt request is generated by the match of TM2BC and the set value of the 2 register VI 34 Synchronous Output Chapter 6 8 bit Timers 6 8 Serial Transfer Clock Output 6 8 1 Operation Serial transfer clock can be created by using the timer output signal mSerial Transfer Clock Operation by 8 bit Timer Timer 3 Timer 3 output can be used as a transfer clock source for serial interface 0 Table 6 8 1 Operation Timer for Serial Transfer Clock Serial transfer clock Timer 3 Serial interface 0 of the timer If other clock is selected normal transfer of serial interface data is not guaran 1 When timer output is selected serial interface transfer clock select fosc as clock source teed mTiming of Serial Transfer Clock Timer TMnEN flag Compare register pake J 00 fot J counter Interrupt request flag Timer output Serial transfer clock Figure 6 8 1 Timing of Serial Transfer Clock Timer 3 1 The timer output is synchronized to the serial transfer clock by the timer count clock and its fre quency is 1 2 of the set frequency set by the compare register Other count timings are same as the timing of timer operation For the baud rate calcula
54. TM2MD TM2ADD2 TM2ADD1 marco ner TM2EN TM2CK2 TM2CK1 2 0 At reset 00000000 TM2CK2 TM2CK1 TM2CK0 Clock source selection fosc tm2psc Prescaler output fx Synchronous fx 21 input O Synchronous TM2IOinput TM2EN Timer 2 count control Halt the count Operate the count TM2PWM Timer 2 operation mode selection 0 Normal timer operation PWM operation TM2MOD Pulse width measurement control Normal timer operation P22 IRQ2 pulse width measurement Figure 6 2 11 VI 12 Control Registers TM2ADD2 TM2ADD1 Additional pulse position No additional pulse 0 9 1 2 period j 0 1 3 period 1 1 2 3 period Timer 2 Mode Register TM2MD 5 R W Chapter6 8 bit Timers Timer 3 Mode Register TM3MD 7 6 5 4 3 2 1 0 TM3MD 5 TM3EN 2 TM3CK1 Atreset 00000 TM3CK2 TM3CK1 Clock source selection fosc tm3psc Prescaler output fx Synchronous fx TMSIO input Synchronous TM3IO input OO TM3EN Timer 3 count control 0 Halt the count 1 Operate the count TM3CAS Timer 3 operation mode selectio
55. Timer Mode Registers This is a readable writable register that controls timer 6 and time base timer 6 Mode Register TM6MD Atreset 00000000 Time base timer clock TM6CKS0 source selection 0 fosc fx Timer 6 clock source TM6CK3 TMeCK2 TMeCK1 selection 0 0 fosc 0 1 fs 1 0 fx 1 Synchronous fx O Time base selection clock x 1 2 1 1 Synchronous time base selection clock x 1 2 O base selection clock 1 2 1 Synchronous time base selection clock x 1 27 TM6IR2 TMGIRI TM6IRO 0 Time base selection clock x 1 27 0 1 Time base selection clock x 1 2 0 Time base selection clock x 1 2 1 Time base selection clock x 1 2 0 Time base selection clock x 1 2 1 Time base selection clock x 1 2 TM6CLRS counter clear 0 Enable the initialization of TM6BC as TM6OC is written 1 Disable the initialization of TM6BC as TM6OC is written TM6IRQ is disable as TM6CLRS 0 TMG6IRQ is enable as TM6CLRS 1 Figure 8 2 4 Timer 6 Mode Register TM6MD x 03F6A R W 7 6 5 4 3 2 1 0 TM6MD TM amp CLRS TM6IR2 TM6IR1 TM6IR0 TM6CK3 TM6CK2 TM6CK1 TM6CKO VIII 6 Control Registers Chapter 8 Time Base Timer 8 bit Free running Timer 83 8 bit Free running Timer 8 3 1 Operation m bit Free running Timer Timer
56. XII 8 12 3 ett ette better xime iie pes XII 10 12 3 2 Setup Example 5 1 nu se eet amete ere etes XII 12 12 3 8 CautlOns siete ege per HR e RR e EO XII 14 Chapter 13 LCD Vlil contents 13 1 LECD Fu nctions aaa noie ameet De dette eere RU eie un 2 13 1 BUNCHONS tete ee Beso a XII 2 13 12 LCD Operation in Standby Mode esee XIII 3 13 5 Maximum Pixels sessi amupa uui ass XIII 3 13 14 Switching I O ports and LCD segment pins eese XIII 4 13 1 5 LCD Driver Circuit Block Diagram eee XIII 5 13 2 Control Registers uyan aaah i Wick agag XIII 6 13 22 Registers Loic eee ERE e a P oS e tee XII 6 13 2 2 Mode Control Register 1 LCDMDI eee XIII 7 13 2 3 Mode Control Register2 LCDMD2 XIII 8 13 2 4 Output Control Register 1 2 00000222 XIII 9 13 2 5 Output Control Register 2 LCCTR2 eee XIII 10 13 26 Segment Output XIII 11 Operation acusa nre ror RED ER ore XIII 12 13 31 Circuit Operation for LCD 4 XIII 12 13 32 Voltage Booster Circuit for LCD Drive 2444442021 XIII 13 13 3 3 Power Supply esee rere tie mets XIII 15 13 3 4 Frame Cycle i4 thee treni eite reget XI
57. 0000 to set P60 to P63 pins to input pins Set the P6PLUD3 0 flag of the port 6 pull up pull down resistor control register P6PLUD 1111 to add the pull up resistors to P60 to P63 pins Set the 0 flag of the port 6 key interrupt control register P6IMD to 1111 to set P60 to P63 pins to key input pins Set the interrupt level by the IRQ4LV1 0 flag of the IRQ4ICR register If the interrupt request flag has been already set clear the request flag t Chapter 3 3 1 4 Interrupt flag setup Set the IRQ4IE flag of the IRQ4ICR register to 1 to enable the interrupt Note Above 2 and 3 are set at the same time If there is at least one input signal from the 40 to P47 pins shows low level the external interrupt 4 is generated at the falling edge The key input setings must be completed before the interrupt is accepted 46 External Interrupts 3 3 7 Noise Filter Noise Filter External interrupts 0 and 1 Noise filter reduce noise by sampling the input waveform from the external interrupt pins IRQ0 IRQ1 Its sampling cycle can be selected from 4 types fosc fosc 2 fosc 2 fosc 2 mNoise Remove Selection External interrupts 0 and 1 Noise remove function can be selected by setting the NFnEN flag of the noise filter control register NFCTR to 1 mSampling Chapter 3 Table 3 3 3 Addition of Noise Remove Function NFnEN IRQO input
58. 16 bit Timer Pulse Output VH 27 Chapter 7 16 bit Timers 7 6 16 bit Standard PWM Output Only duty can be changed consecutively The TMnIO pin outputs the standard PWM output which is determined by the overflow timing of the binary counter and the match timing of the timer binary counter and the compare register It can also be output from the TMnO high current pin 7 6 1 Operation E 16 bit Standard PWM Output Timer 7 Timer 8 PWM waveform with an arbitrary duty is generated by setting a duty of PWM H period to the compare register 1 TMnOC 1 Its cycle is the time of the 16 bit timer full count overflow Table 7 6 1 shows the PWM output pin Table 7 6 1 PWM Output Pin Timer 7 Timer 8 TM7IO output pin TM8IO output pin P14 P15 PWM output pin z TM7IO output pin TM8IO output pin P51 P53 iCount Timing of Standard PWM Output at Normal Timer 7 Timer 8 TMnEN flag Compare register 1 eed counter PWM source 2210 waveform A TMnIO output PWM output 2 gt Setup time for compare register 1 1 PWM basic component overflow time of the binary counter Figure 7 6 1 Count Timing of Standard PWM Output at Normal PWM source waveform A shows until the binary counter reaches the compare register value from x 0000 B shows L after the compare match then the binary counter counts up till the overf
59. 2 and 3 TMOIO pin outputs 50 kHz pulse by using timer 0 For this select fosc for clock source and set a 1 2 cycle 100 kHz for the timer 0 compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD x 3F54 bp3 TMOEN 20 2 Setthe special function pin to the output mode P1OMD x 3F2F bpO P1OMDO 1 P1DIR x 3F31 P1DIRO 1 3 Select the normal timer operation TMOMD x 3F54 bp4 TMOPWM 0 bp5 0 4 Select the count clock source TMOMD x 3F54 bp2 0 2 0 000 5 Set the timer pulse output cycle x 3F52 x C7 6 Start the timer operation TMOMD x 3F54 bp3 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop timer 0 counting Set the P1OMDO flag of the port 1 output mode register P1OMD to 1 to set P10 the special function pin Set the P1DIRO flag of the port 1 direction control register P1DIR to 1 to set output mode Add pull up pull down resistor if necessary Chapter 4 I O Ports Set the TMOPWM flag and TMOMOD flag of the TMOMD register to O to select the normal timer operation Select fosc for the clock source by the 2 0 flag of the TMOMD register Set the timer 0 compare register to the 1 2 of the timer pulse output cycle
60. 2 1 1 Block Diagrami sy spe erede e eR po II 3 2 1 2 CPU Control Registers ree emet p RERO reperit II 4 2 1 3 Instruction Execution Controller II 5 2 1 4 Pipeline Process uan IRURE ener 6 2 1 5 Registers for Address eie geste eee ph eee 6 2 1 6 Registers for Operation H 7 2 1 7 Processor Status Word as aasan aaa 8 2 1 8 Addressing Modes iiie iere heres II 10 Memoty ote Eu te C ooa OR II 12 2 2 1 Memory Mode rcs ete tre et II 12 2 2 2 Single chip neis pae 13 2 2 3 Special Function Registers II 14 2 3 2 5 2 6 Bus Interface 15 2 3 1 Bus Controller C UR inu II 15 2 3 2 Control Registers teet E errore Tes II 16 Standby Function e iei ip Ri II 17 2 4 1 etenim ERE EG 17 2 4 2 CPU Mode Control Register II 19 2 4 3 Transition Between SLOW and NORMAL Modes II 20 2 4 4 Transition to STANDBY Modess II 21 Clock Switching c a inn ih tette t ert et e e II 23 Buka E tiones II 25 2 6 1 Reset Operation ene aree II 25 2 6 2 Oscillation Stabilization Wait Time II
61. 60 0 X 3F69 6 6 Compare Register VIII 5 TM6CLRS TM6IR2 TM6IR1 TM6IR0 TM6CK3 TM6CK2 TM6CK1 TM6CK0 X 3F6A TM6MD Timer 6 Time Base Interrupt Cycle Selection Timer 6 Clock Source Selection TimerBase Timer VIII 6 Binary Counter Clock Source Clear Selection Selection X 3F6B TBCLR Time Base Timer Clear Register Write Only VIII 5 TMORM RMOEN RMDTYO RMBTMS X 3F6E RMCTR P10 Remote Control Remote Control Remote Control 14 Special Function Carrier Output Carrier Output Carrier Base Timer Output Selection Enable Duty Selection Selection PSCEN X 3F6F PSCMD Prescaler V 6 Operation Enable TM7BCL7 TM7BCL6 TM7BCL5 TM7BCL4 TM7BCL2 TM7BCL1 TM7BCL0 X 3F70 TM7BCL Timer 7 Binary Counter Lower 8 Bit VII 8 TM7BCH7 TM7BCH6 TM7BCH5 TM7BCH4 TM7BCH3 TM7BCH2 TM7BCH1 TM7BCHO X 3F71 TM7BCH Timer 7 Binary Counter Upper 8 Bit VII 8 70 117 7 116 TM7OC1L5 70 114 TM7OC1L8 7 112 TM7OC1L1 TM7OC1L0 X 3F72 TM7OC1L Timer 7 Compare Register 1 Lower 8 Bit VII 6 Special Function Registers List XIV 25 Chapter 14 Appendices Bit Symbol Initial Value Description Address Register
62. 7 6 5 4 3 2 1 0 Atreset 00000000 P7DIR P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIR0 P7DIR mode selection 0 Input mode 1 Output mode Port 7 direction control register P7DIR x 03F37 R W 7 6 5 4 3 2 1 0 eruoepruns P7PLUD4 P7PLUDS P7PLUD2 P7PLUD1 P7PLUDO Atreset 00000000 P7PLUD P7PLUD7 Pull up pull down P7PLUD resistor selection 0 No pull up pull down resistor 1 Pull up pull down resistor Port 7 pull up pull down resistor control register P7PLUD x 03F47 R W Figure 4 8 1 Port 7 Registers 1 3 Pot7 IV 31 Chapter 4 I O Ports 7 6 5 4 3 2 1 0 FLOAT PARDWN P7RDWN P6RDWN SYOEVS1 SYOEVS0 At reset 000 0 0 SVOEVE P6 synchronous output 0 event selection 0 0 External interrupt IRQ2 1 Timer 7 interrupt 0 Timer 2 interrupt 1 1 Timer 1 interrupt P6 pull up pull down POBDWM resistor selection 0 Pull up resistor 1 Pull down resistor P7 pull up pull down PYRDWN resistor selection 0 Pull up resistor Pull down resistor PA pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor Pull up Pull down resistor selection Pin control register FLOAT 2 R W Figure 4 8 2 Port 7 R
63. A electrode COMO SEG4 B electrode COMO SEG6 lit Figure 13 4 1 LCD Display in Static Display XIII 25 Chapter 13 LCD Functions 13 4 2 Setup Example static mSetup example of the LCD static An example of setup procedure to display 2 with both segment signals SEGO to SEG7 and common signals COMO using an external divider resistor is shown below 4 Chapter 13 13 4 1 LCD Display static Clock source fosc 4 MHz a LDC clock source 05 2 122 Hz and flame cycle 122 Hz are selected in this example Setup Procedure Description 1 Stop the LCD operation 1 Set 0 to the LCDEN flag of the LCD mode LCMD1 X 3FD9 control register LCMD to stop the LCD op bp7 LCDEN 0 eration 2 Setup the display duty 2 Set 0 to the LC1SEL flag of the LCD mode LCMD1 X 3FD9 control register LCMD to enter the static bp5 4 LCDDTY1 0 11 drive mode 3 Select the LCD clock source 3 Select fosc 2 as a LCD clock source with LCMD1 X 3FD9 LCDCK3 to 0 flags of the LCD mode control bp3 0 CDCK3 0 0100 register LCMD 4 Select the segment output port pin 4 Select SEGO to 7 with the output control reg Select the common output port pin ister LCCTR1 and select COM1 with the LCCTR1 X 3FDB COMSLO with the LCD mode control register bp3 0 LC1SL3 0 1111 2 LCDMD2 LCCTR2 X 3FDA bp4 COMSLO 1 5 Setup the LCD panel display data 5 Display 2 on the disp
64. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM70C1H7 TM7OC1H6 7 1 5 TM7OC1H4 TM7OC1H3 TM7OC1H2 TM7OC1H1 70 1 0 X 3F73 TM70C1H Timer 7 Compare Register 1 Upper 8 Bit VII 6 TM7PR1L7 7 116 TM7PR1L5 114 TM7PRiL3 TM7PR1L2 TM7PR1L1 TM7PR1LO X 3F74 TM7PRIL Timer 7 Preset Register 1 Lower 8 Bit VII 7 TM7PR1H7 TM7PR1H6 TM7PR1H5 TM7PR1H4 TM7PR1H3 TM7PR1H2 TM7PR1H1 7 75 TM7PR1H Timer 7 Preset Register 1 Upper 8 Bit VII 7 TM7ICL7 6 TM7ICL5 TM7ICL4 2 TM7ICL1 TM7ICLO X 3F76 TM7ICL Timer 7 Input Capture Register Lower 8 Bit VII 9 TM7ICH7 TM7ICH6 5 TM7ICH4 TM7ICH3 TM7ICH2 TM7ICH1 TM7ICHO X 3F77 TM7ICH Timer 7 Input Capture Register Upper 8 Bit VII 9 RESERVED RESERVED TM7CL TM7EN TM7PS1 TM7PSO TM7CK1 7 0 X 3F78 TM7MD1 Set always 0 Timer Output Timer 7 Count Clock Selection Clock Source Selection VII 10 Reset Control Count Control T7ICEDG T7PWMSL TM7BCR TM7PWM TM7IRS1 T7ICEN T7ICT1 T7ICTO X 3F79 TM7MD2 Capture Trigger PWM Mode Timer7 Timer Output Timer7 Input Capture Capture Trigger Selection VII 11 Counter Clear Waveform Interrupt Factor Operation Edge Selection Selection Factor Selection Selection Selection Enable TM7OC2L7 TM7OC2L6 TM7OC2L5 TM7OC2L4 TM70C2L3 TM7OC2L2 TM7OC2L1 70 210 X 3F7A TM7OC2L Timer 7 Compare Register 2 Lower 8 Bit VI
65. CK Read NS DE Analog input Figure 4 10 3 Block Diagram to IV 42 PortA gt PA0 to PA3 Chapter 4 Ports 4 11 Synchronous output Port 6 Port 6 has the synchronous output function that outputs the arbitrary set data to pins in synchronization with the generation of the specified event without setting program Synchronous event is selected from the external interrupt 2 P22 IRQ2 timer 1 interrupt timer 2 interrupt or timer 7 interrupt signal 4 11 1 Block Diagram 0 P6OUTO to 7 M 1 U Output data Port output data DO DQ Write CK L NT X Read Synchronous output value 11 Store register Timer 1 interrup M Timer 2 interrup 10 o U Timer 7 Synchronous output event 00 External interrupt Pin control register FLOAT bp1 bpO Rese P6SYO0 107 Synchronous output control Write 7 Read Figure 4 11 1 Synchronous Output Control Block Diagram Synchronous Output Port6 IV 43 Chapter 4 I O Ports 4 11 2 Registers Table 4 11 1 shows the synchronous output control registers of port 6 Table 4 11 1 Synchronous Output Control Registers Register Address R W Function Page FLOAT x 03F2E R W Pin control register 1 27 P6SYO X 03F1E R W Synchronous output control register 27 Port 6 P6DIR x 03F36 R W P
66. Data is received at the opposit output edge of the transmission data so that the input edge of the received data should be the opposide output edge of the transmission data from the other side SBT pin Data is received at the rising edge of clock SBI pin Data is output at the falling edge of clock Figure 11 3 13 Transmission Reception Timing Reception at rising edge Transmission at falling edge SBT pin Data is received at the falling of clock SBI pin Data is output at the ricing of clock Figure 11 3 14 Transmission Reception Timing Reception at falling edge Transmission at rising edge Operation XI 23 Chapter 11 Serial Interface 0 WPins Setup with 3 channels at transmission Table 11 3 6 shows the setup for synchronous serial interface pin with 3 channels SBO pin SBI pin SBT pin at transmission Table 11 3 6 Setup for Synchronous Serial Interface Pin with 3 channels at transmission Data output pin Data input pin Clock VO pin Setup item SBT pin SBO pin SBI pin Internal clock External clock Port pin 1 2 SBI SBO independent SBI SBO pin SCOMD1 SC1IOM Serial data output 1 input Serial clock VO Serial clock VO Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Push pull Push pull Push pull Style Nch open drain Nch open drain Nch open drain SC0ODC SC0ODC0 SC0ODC SC0ODC
67. EPROM Version differs from the MN101C527 series mask ROM version in some of its electrical charac teristics The user should be aware of the following cautions 1 To prevent data from being erased by ultraviolet light after a program is written affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU PX AP101C52 BC 2 Because of device characteristics of the MN101CP52ABL a writing test cannot be performed on all bits Therefore the reliability of data writing may not be 100 ensured 3 When a program is written be sure that power supply 6 V is connected before applying the Ver power supply 12 5 Disconnect the Ver supply before disconnecting the supply 4 should never exceed 13 5 V including overshoot 5 If a device is removed while a VPP of 12 5 V is applied device reliability may be damaged 6 At NCE Vi do not change Vpp from to 12 5 V or from 12 5 V to Vit 7 After a program is written screening at a high temperature storage is recommended before mounting Program Read 4 Heat treat at 125 C for 48 hours Read Mount 2 4 EPROM Versions XIV 3 Chapter 14 Appendices 14 1 3 Erasing Data in Windowed Package 101 52 Irradiating the chip through the window PX AP101C52 BC with 253 7 nm ultraviolet radiation erases the data by changing all 0 bits 1 The recommended exposure is 10 Wes cm the
68. H1981 OdI81 Dx Oul9IA L snouoJuou S 158 OS9WI suioeni Jejunoo 16 8 ZHIOWL Sian ZOOWL DOS 0 yoe 110 9 9 Block Diagram 6 Time Base Figure 8 1 1 VIII 3 Overview Chapter 8 Time Base Timer 8 bit Free running Timer 8 2 Control Registers Timer 6 consists of binary counter TM6BC compare register TM6OC and is controlled by mode register TM6MD Time base timer is controlled by mode register TM6MD and time base timer clear register TBCLR 8 2 1 Control Registers Table 8 2 1 shows the registers that control timer 6 time base timer Table 8 2 1 Control Registers Register Address R W Function Page TM6BC x 03F68 Timer 6 binary counter VIII 5 ae TM6OC x 03F69 R W Timer 6 compare register VIIL 5 TM6MD x O3F6A RAN Timer 6 mode register VIII 6 TM6ICR x O3FEF RW Timer 6 interrupt control register Ill 25 TM6MD RW Timer 6 mode register VIII 6 Time base timer TBCLR x 03F6B W Time base timer clear control register VIII 5 TBICR xO3FFO Time base interrupt control register Ill 26 R W Readable Writable R Readable only W Wriiable only 4 Control Register
69. Interrupt service routine 1 1 72 1 0 10 Interrupt acceptance cycle Interrupt generated xxxLV1 0 11 Interrupt 2 generated xxxLV1 0 10 om IM1 0 11 Interrupt service routine 2 RTI Not accepted because IM IL Y Parentheses indicate hardware processing 1 If during the processing of the first interrupt an interrupt request with an interrupt level IL numerically lower than the interrupt mask IM arrives it is accepted as a nested interrupt If IL 2 IM however the interrupt is not accepted 2 second interrupt postponed because its interrupt level IL was numerically greater than the interrupt mask IM for the first interrupt service routine is accepted when the first interrupt handler returns IM1 0 11 Figure 3 1 6 Processing Sequence for Maskable Interrupts III 11 Overview Chapter 3 Interrupts Multiplex Interrupt When an MN101C527 series device accepts an interrupt it automatically disables acceptance of subse quent interrupts with the same or lower priority level When the hardware accepts an interrupt it copies the interrupt level xxxLVn for the interrupt to the interrupt mask IM in the PSW As a result subse quent interrupts with the same or lower priority levels are automatically masked Only interrupts with higher priority levels are accepted The net result is that
70. MOV abs12 Dm abs8 Dm MOV An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV io8 D MOV d4 SP Dm MOV d8 An Dm MOV Dn io8 MOV Dn d4 SP MOV Dn d8 Am ADD 4 Dm SUB Dn Dn 07 BRA 07 BEQ d7 BNE d7 d7 BCS d7 BLT d7 BLE d7 BEQ d4 BNE d4 MOVW DWn HA MOVW d11 BRA d11 BEQ d11 BNE 411 BCC d11 BCS 411 BLT 011 BLE 011 MOV Dn Dm MOV 8 BSET abs8 bp BCLR abs8 bp CMP 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVW DWn abs8 CBNE 8 Dm d7 CMPW 16 Am MOVW 16 MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 Am BRA d4 MOVW DWn Am Extension code 6 0010 2nd nible 3rd nibble 0 1 MOVW An Am An d4 SP CMPW An Am MOVW DWn d4 SP PUSH Dn 9 A B MOVW SP Am MOVW An SP ADDW 8 SP ADDW MSP 5 8 Dm JSRV 00 JMP A0 JSR A0 JMP A1 JSR A1 MOV PSW Dm REP BGT d7 BHI d7 BLS d7 BNC d7 5 47 BVC d7 5 d7 NOT Dn ROR Dn 411 BHI d11 BLS 411 BNC 011 5 411 BVC d11 BVS d11 ASR Dn LSR Dn SUBW DWn DWm SUBW 16 DWm SUBW 16 Am SUBW DWn Am MOVW DWn Am ADDW DWn DWm
71. Model 101 527 Customer kaq Name sign 1 Supply voltage operating range 2 Type and frequency of oscillation input Supply Voltage System Clock Timer Clock CPU Operation Used Unused during Operation Type OSC Input XI Input Atr High Speed External OSC1 Operation V to V Clock At Low Speed XI Operation Vto V Crystal At HALTO Vto V Ceramic At HALT1 V to V Frequency MHz kHz At STOP V to V Unused 3 System operating clock 4 Setting of oscillation divider OSC1 Only Normal mode Slow mode Switching OSC1 and XI 2 divide 2 divide 4 divide 8 divide 5 LCD display mode 8 divide 32 divide LCD unused 16 Static 1 2 duty 1 2bias Seance 1 3 duty 1 3 bias O4 aide 1 4 duty 1 3 bias 6 LCD power supply LCD Voltage At 2 times 3 times boost VLC3 active booster circuit At 2 3 times 1 2 times boost VLC2 V active At 2 times boost 2 V Unused Internal voltage divider active Vict External voltage _ divider active R vici LCD unused When placing an order for masks please present this document Operation Mode Check List 1 35 2 Basic CPU Chapter2 Basic CPU 2 1 Overview The MN101C series has a flexible optimized hardware configuration as an embedded microcomputer and a simple efficient instruction set for both economy and speed Specific features are as follows 1 Minimized code sizes with instruction lengths based on 4 bit increments The series keeps code sizes down by adopti
72. No pull up resistor 1 Pull up resistor Port 5 pull up resistor control register P5PLU x 03F45 R W Port 5 Figure 4 6 1 Port 5 Registers 1 2 P5OMD 6 5 4 3 2 1 0 Chapter4 Ports P5OMD3 P5OMD2 At reset 0 00 0 P5OMD0 I O port timer 0utptu selection 0 I O port 1 Timer 0 output P5OMD1 port timer 7 output selection 0 port 1 Timer 7 output P5OMD2 port timer 2 output selection 0 port 1 Timer 2 output P5OMD3 port timer 8 output selection 0 I O port 1 Timer 8 output Port 5 output mode register PSOMD X 03F3F R W Figure 4 6 2 Port 5 Registers 2 2 Pot5 IV 23 Chapter 4 Ports 4 6 3 Block Diagram N gae PBPLUO to 2 Pull up resistor control gt Write N Z Read P5DIR0 to 2 xe direction control DQ gt Write jCK Read CT 34 P50 to P52 8 PSOUTO to 2 M Port output data 5 B 1 U Write Read X 777 Rese P5OMDO to 2 Output mode control D Q Write CK Read P5IN0 to 2 Port
73. P30 to P33 Schmitt trigger input 41 Input high voltage 0 8 VoD 42 low voltage Vig 0 0 2 Vpp i 43 Input leakage current Vin 0 V to 10 44 Input current 1 30 100 300 2i 45 Output high voltage Vous Vpp 5 0 V lou 0 5 mA 45 46 Output low voltage 5 0 V 0 1 0 mA 0 5 d VO pin 3 P50 to P53 47 Input high voltage 1 Vino 0 8 48 Input high voltage 2 Vpp 4 5 V to 5 5 V 0 7 Vpp 49 Input low voltage 1 Vito 0 0 2 50 low voltage 2 4 5 V to 5 5 V 0 0 3 Vpp 51 Input leakage current Vin 0 V to 10 52 Input current 1 lino Puls eee ON 30 100 300 2d 53 Output high voltage 5 0 V lou 0 5 4 5 54 Output low voltage Voto 5 0 V 0 15 mA 1 0 VO pin 4 P60 to P67 Schmitt trigger input 55 Input high voltage Viri 0 8 Vpp Vpp 56 low voltage 0 0 2 57 Input leakage current 1 ViN 0 V to Vpp 10 58 Input current 1 522 d 30 100 300 wa 59 Input current 2 2 ON 30 100 300 60 Output high voltage 5 0 V 0 5 mA 4 5 61 Output low voltage Vpp 5 0 V 0 1 0 mA 0 5 1 24 Electrical Characteristics Chapter 1 Overview Ta 40 C to 85 2 0 V to 5 5 V Vss 0 V
74. P77 input mode Pin Description I 11 Chapter 1 Overview Table 1 3 4 Pin Function Summary 3 6 Name No yo Other Function Description Function P80 53 VO SEG7 VO port 8 8 bit CMOS tri state VO port P81 54 SEG6 Eachindividual bit can be switched to an input or output P82 55 SEG5 bythe P8DIR register A pull up resistor for each bit can P83 56 SEG4 be selected individually by the P8PLU register At P84 57 SEG3 output LED can be directly driven P85 58 SEG2 Atreset when the single chip mode is selected pull up P86 59 SEG1 resistor is disabled high impedance output on P80 to P87 60 SEGO P87 input mode PAO 19 Input ANO Input port A 4 bit input port PA1 20 1 A pull up or pull down resistor for each bit can be PA2 21 AN2 selected individually by the PAPLUD resister However PA3 22 AN3 pull up and pull down resistors cannot be mixed At reset pull up resistor is disabled high impedance output on PAO to PA3 input mode 5 0 24 Output POO TXD Serial interface Transmission data output pins for serial interface 0 SBIO 25 Input P01 RXD transmission data output pins Serial interface received data input pins For the output configuration either CMOS push pull or n channel open drain can be selected Pull up resistor can be selected by the POPLU register Select output mode by the PODIR register and serial data output mode by serial mode register 1 SCOMD1 This can be used as a normal l O
75. PC 10 d1 label HPC e e e 10 6 7 0010 1101 1101 abs 8 48 gt dii 33 if mem8 abs8 4imm8 PC 10 PC CBEQ imm8 abs16 label _ if mem8 abs16 imm8 PC 11 d7 label HPC e e 11 7 8 0011 1101 1100 abs 16 48 gt lt d7 2 if mem8 abs16 4imm8 PC 113PC CBEQ imm8 abs16 label if mem8 abs16 imm8 PC 12 d1 label HPC e 12 7 8 0011 1101 1101 abs 16 gt lt 8 gt dii 2 13 if mem8 abs16 imm8 PC 123PC CBNE CBNE imm8 Dm label if Dm4imm8 PC 6 d7 label H3PC e o 3 4 1101 10Dm lt 8 gt lt d7 H 2 if Dm imm8 PC 6 gt PC CBNE imm8 Dm label if Dmzimm8 PC 8 dtt labe HGPC e e e e 8 4 5 0010 1101 10Dm 48 gt dii 3 8 8 CBNE imm8 abs8 label if mem8 abs8 Zimm8 PC 9 d7 label HOPO e e 9 6 7 0010 1101 1110 abs 8 gt lt 8 gt lt 7 12 if mem8 abs8 imm8 PC 92PC CBNE imm8 abs8 label _ if mem8 abs8 4imm8 PC 10 d1 1 label HPC e 10 6 7 0010 1101 1111 abs 8 gt lt 8 gt dii 3 if mem8 abs8 imm8 PC 10 PC CBNE imm8 abs16 label if mem8 abs16 4imm8 PC 11 d7 label HPC le e 11 7 8 0011 1101 1110 abs 16 gt 48 gt lt d7 2 if memB abs16 imm8 PC 1 1 2PC CBNE imm8 abs16 label if mem8 abs16 4imm8 PC 12 d1 1 label H PC 12 7 8 0011 1101 1111 abs 16 gt 8 dii 3 if mem8 abs16 imm8
76. Table 13 2 1 shows the LCD control registers Tabel 13 2 1 LCD Control Registers List Register abbreviation Address R W Register Name Page LCDMD1 X 03FD9 R W LCD mode control register 1 XIII 6 LCDMD2 X 03FDA R W LCD mode control register 2 19 XIII 7 LCCTR1 X OSFDB RW LCD output control register 1 brad LCCTR2 X 03FDC R W LCD output control register 2 IV 28 XIII 9 Address x 02E00 to x O2EOB are assigned to the segment output latch Chapter 13 13 2 6 Segment Output Latch XIII 6 Control Registers 13 2 2 Mode Control Register 1 LCDMD1 The LCD mode control register 1 LCDMD1 is a 8 bit register that controls the LCD clock LCD display ON OFF internal voltage divider resistors ON OFF and the display duty The address assigned to this register is X 3FD9 The value of the LCDMD1 register is initialized at reset 7 6 5 4 3 2 1 0 LCDMD1 LCDEN LCREN LCDTY1 LCDTYO LCDCK3 LCDCK2 LCDCK1 LCDCKO at reset 00000000 Chapter 13 LCD Functions LEDCK3 LCDCK2 _ SD clock source selection 0 0 OSC1 2 1 OSC1 2 0 13 1 0 OSC1 2 1 05 1 214 0 0 OSC1 2 5 1 1 OSC1 2 5 0 OSC1 27 1 05 1 218 0 XI 2 0 7 1 X 1 XI 2 0 XI 28 1 XI 29 LCDTY1 LCDTYO LCD display duty selection 1
77. This can be used as a normal IO pin when remote control is not used BUZZER 27 Output P06 Buzzer output Piezoelectric buzzer driver pin The driving frequency can be selected by the DLYCTR register Select output mode by the PODIR register and select buzzer output by DLYCTR register When not used as a buzzer output pin this can be used as a normal VO pin Pin Description 1 13 Chapter 1 Overview Table 1 3 6 Pin Function Summary 5 6 Name No yo Other Function Function Description TM7IO 32 VO P14 Timer VO pin Event counter clock input pin timer output and PWM TM8IO 33 P15 signal output pin for 16 bit timer 7 To use this pin as event clock input configure this as input by the P1DIR register In the input mode pull up resistor can be selected by the P1PLU register For timer output and PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register When not used for timer this be used as normal VO pin SDOO 37 Output P60 KEYO SEG23 Synchronous 8 bit synchronous output pins SDO1 38 P61 KEY1 SEG22 output pins Synchronous output for each bit can be selected SDO2 39 P62 KEY2 SEG21 individually by the port 6 synchronous output control SDOS3 40 P63 KEY3 SEG20 register 65 Set to the output mode by the P6DIR SDO4 41 P64
78. abs16 bp d7 TBZ abs16 bp d11 TBNZ abs16 bp d7 TBNZ abs16 bp d11 Ver2 1 2001 03 26 Instruction Map XIV 21 Chapter 14 Appendices 14 5 Special Function Registers List Address Register Bit Symbol Initial Value Description Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OSCSEL1 OSCSELO OSCDBL STOP HALT OSC1 05 0 00 Devision Rate Setup Internal System STOP mode HALT mode Oscillation Control 1 23 0 Clock Setup Setup Setup IOW1 IOW0 IVBM EXMEM RESERVED IRWE RESERVED RESERVED X 3F01 MEMCTR VO Wait Setup Interuupt Vector Set Set Software Write Set always 11 1 16 Address always 0 always 1 Setup WDTC2 WDTC1 WDTCO WDTS1 WDTSO WDEN X 3F02 WDCTR The lowest value for WDT clear setup Watchdog Time out WDT IX 3 period Setup Activation BUZOE BUZS2 BUZS1 0750 DLYS1 DLYSO X 3F03 DLYCTR P06 Output Buzzer Output Frequency Setup Oscillation Stabilization ee I X 3 Selection Wait Cycle Setup POOUT6 POOUT2 POOUT1 POOUTO X 3F10 POOUT Port 0 Output Data 7 P1OUT5 P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUTO X3F11 P1OUT Port 1 Output Data IV 11 P20UT7 X3F12 P20UT Port 2 Output Data IV 15 P30UT3 P30UT2 P30UT1 X3F13 P3OUT Port 3 Output Data IV 18 P5OUT3 500 2
79. and that may lower the brightness of LCD display In this case set 1 to the voltage booster operation speed control bit of the LCD mode control register 2 LCDMD2 to increase the operation speed This also increases charge supply capacity of the voltage booster circuit To use the voltage booster circuit start the voltage booster operation right after the power is turned on or reset is released 22 Operation Chapter 13 LCD Functions Operation XIII 23 Chapter 13 LCD Functions 13 4 Display Figures 13 4 1 to 13 4 4 show examples of connections displays and waveforms of the LCD panel in these condition in 1 2 duty 1 3 duty 1 4 duty and static 13 4 1 Static MN101C527 i Static Segment Latch X 2E03 X2E03 X 2E02 X2E02 X2E01 2 01 X 2E00 X 2E00 0 E bit7 bit3 bite bit 0 0 bit5 bit1 bit4 bitO SEG4 SEG3 SEG2 SEG1 SEGO A electrode B electrode notiit LCD PANEL LCD ON COM S COM S LCD OFF SEG S SEG N LCD clock undefined Data 1 0 undefined COM SEG COM SEG Lit Not lit Not lit S selective voltage N non selective voltage Vucp LCD driver voltage In case of static always outputs selective voltage 24 Display Chapter13 LCD Functions COM0 ViCD SEG4 data SEG6 data
80. awoyo GWOWL OOOWL 98IWL OgOIAL 4olsi6 u med 194409 GWI9d sod d 191909 aWold 1VO14 NIVd Ni d indino 1HOd OAS9d LNOZd LNOSd LNOSd 1noed 1 014 10009 Jouoo Aiowaw apow H1OA TG Wndo 3 3 q g V 6 8 L 9 S 2 0 X43480 X34860 Xq3eo X84680 60 6 60 X83 0 X44 0 X93 0 XSAE0 Xv4 0 X 4 0 0 X03 0 Memory Space 14 Chapter 2 Basic CPU 2 3 Bus Interface 2 3 1 Bus Controller The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation There are four such buses ROM bus RAM bus and peripheral expansion bus I O bus They are connected to the internal ROM internal RAM internal peripheral circuits and external interfaces respec tively The bus control block controls the parallel operation of instruction read and data access the access speed adjustment for lo
81. fosc 64 baud rate timer output fulfill 71 fs fosc 32 fosc 64 baud rate timer output fulfill 1 fs fosc 64 baud rate timer output fulfill 1 Operation 47 12 A D Converter Chapter 12 A D Converter 12 1 Overview This LSI has A D converter with 10 bits resolution It contains a built in sample hold circuit channels 0 to 3 AN0 to AN3 of analog input can be switced by software When A D converter is stopped the power consumption can be reduced by turning the built in ladder resistance OFF A D conversion is activated by a register setup 12 1 1 Functions Table 12 1 1 shows the A D converter functions Table 13 1 1 A D Converter Functions A D Input Pins 4 pins Pins to Interrupt ADIRQ Resolution 10 bits Conversion Time Min 9 6 us TAD as 800 ns Input range Vref to Vref Power Consumption Built in Ladder Resistance ON OFF XII 2 Overview Chapter 12 Converter 12 1 2 Block Diagram ANCTR1 ANCTRO ANCTR2 0 ANCHSO 2 ANCHS1 ANBUF1 _ 4 ANCHS2 ANBUF10 ANLADE ANBUF11 r ANBUF12 ANBUF13 LF _ 5 A D conversion ANB
82. the A D conversion complete interrupt is generated and the ANST flag of the A D converter control register 2 ANCTR2 is cleared to 0 The result of the conversion is stored to the A D converter buffer ANBUFO 1 Note The above 3 to 4 can be set at the same time Operation 13 Chapter 12 A D Converter 12 3 3 Cautions A D conversion be damaged by noise easily therefore anti noise measures should be taken equately mAnti noise measures To A D input analog input pin add condenser near the Vss pins of micro controller Digital Vpp Analog Vpp VDD Vss Vref ANO Power supply to AN15 T Digital Vss Vref Analog Vss Set near the Vss Figure 12 3 2 A D Converter Recommended Example 1 Vpp Vss Power supply TY Set near the Vss pin Figure 12 3 3 A D Converter Recommended Example 2 14 Operation Chapter 13 Converter This microcontroller contains a sample hold capacitor 10 pF Set the sample hold time based on the capacitor C and the time constant of impedance R of the external analg signal output circuit For the sample hold time 3 x the time constant CR or longer is recomended At A D conversion cycle Tap 800 ns 1 6 us 4 8 us and 14 4 us can be selected as a sample hold time Each impedance value of the external analog signal output circuit should be under the follow
83. 010A lt d4 gt 2 MOVW DWn d8 SP DWn gt mem16 d8 SP 5 4 0010 1111 0110 lt 8 gt 3 MOVW An d8 SP An mem16 d8 SP 5 4 0010 1111 010A d8 gt 3 MOVW 416 5 DWn gt mem16 d16 SP 7 5 0010 1111 0010 lt d16 gt MOVW An d16 SP An mem16 d16 SP 7 5 0010 1111 000A lt 16 c MOVW DWn abs8 DWn mem16 abs8 41 3 1101 0110 lt abs 8 gt MOVW 058 An mem16 abs8 4 3 1101 010 lt 8 gt MOVW DWn abs16 DWn mem16 abs16 7 5 0010 1101 0110 lt abs 16 gt MOVW An abs16 An mem16 abs16 7 5 0010 1101 010 lt abs 16 m MOVW DWn HA DWn mem 16 HA 2 3 1001 0100 MOVW gt 16 2 3 1001 011 MOVW imm8 DWm sign imm8 DWm 4 2 0000 1104 lt 8 gt 5 MOVW imm8 Am 8 gt 4 2 0000 111 lt 8 gt 6 MOVW imm16 DWm imm16 5DWm 6 3 1100 1114 lt 16 gt XIV 14 Instruction Set 1 2 d4 zero extension 3 48 zero extension d8 sign extension 4 A An 5 8 sign extension 6 8 zero extension 101 SERIES INSTRUCTION SET Chapter 14 Appendices Mnemonic Operat
84. 1 SC0MD1 SCOMD1 7 6 5 4 3 0 SCOIOM SCOSBTS SCOSBIS 5605805 SCOCKM 50 MST SCOCMD Chapter 11 Serial Interface 0 At reset 000000 0 Synchronous serial Duplex UART selection 0 Synchronous serial 1 Duplex UART scoMsr Clock master slave selection 0 slave 1 master SCOCKM 1 8 dividing of transfer clock selection 0 divide by 8 Divide by 8 SC0SBOS SBO0 TXD pin function selection 0 Port 1 Serial data output SC0SBIS Serial input control 0 input Serial input SCOSBTS SBT pin function selection 0 Port 1 Transfer clock I O SCOIOM Serial data I O selection 0 Data input from SBI RXD Data input from SBO TXD Figure 11 2 4 Serial Interface 0 Mode Register 1 SCOMD1 x 03F91 R W Control Registers XI 7 Chapter 11 Serial Interface 0 Serial Interface 0 Mode Register 2 SCOMD2 SCOBRKF flag is only for reading 7 6 5 4 3 2 1 0 At reset 00000 00 SCOMD2 SCOFM SCOFMO SCOPM SCOPMO SCONPE _ SCOBRKF SCOBRKE SCOBRKE Break status transmit control 0 Data 1 Break 2 Break status receive monitor 0 Data 1 Break Only read access is available 5
85. 1 5 1 6 1 7 1 8 OV EIVICW eve tee arte ee ie a e E ee en ER ERE N n is I 2 1 1 1 OVV EW a Su I 2 1 1 2 Product Summary on dependet etie emeret tenia I 2 Hardware Functions pee eere there amete Shina qaya I 3 Pin Description OS A e elem thee I 8 1 3 1 Pin Configuration 2 reete sheen e p e EUR I 8 1 3 2 Pin Specifica OT adore cio e On GIO eO ORI E I 9 1 3 3 Pin Functions y skua 1 10 Block Diagr m 3s a u REPRE 1 16 1 4 1 Block Diagram uaa egerat eu I 16 Electrical Characteristics uu q Per WR ERE I 17 1 5 1 Absolute Maximum Ratings eene I 17 1 5 2 Operating Conditions genie aene ee ederet I 18 1 5 3 DC Characteristics ne ente bee edere I 21 1 5 4 A D Converter Characteristics essere I 26 Cautions Tor Carcuit Setup siepe ere eee te qe pe peteret ene I 27 1 6 1 General Usage une oU UO pun ew I 27 1 6 2 Uriused Pins 1 28 1 6 3 Power Supply oett rente Hber I 30 1 6 4 Power Supply Circuit essere I 31 1 6 5 arriere I 32 Package Dimension iui ui ER E PE PD E S ESAE SSe I 34 Operation Mode Check List sese I 36 Chapter 2 Basic CPU contents 2 1 2 2 tee n HH DEO tee ER RR II 2
86. 1 Operation The watchdog timer counts system clock fs as a clock source If the watchdog timer is overflowed the watchdog interrupt WDIRQ is generated as a non maskable interrupt NMI At reset the watchdog timer is stopped but once the operation is enabled it cannot be stopped except at reset The watchdog timer control register WDCTR sets when the watchdog timer is released or how long the time out period should be This watchdog timer can detect a runaway such that the watchdog timer clear is repeated in short cycle If the watchdog timer clear is repeated in shorter cycle than the set time the lowest value watchdog timer can clear it is regarded as an error and the watchdog interrupt WDIRQ is generated If the watchdog interrupt WDIRQ is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware 1 watchdog timer cannot stop once it starts operation ilUsage of Watchdog Timer When the watchdog timer is used constant clear in program is needed to prevent an overflow of the watchdog timer As a result of the software failure the software cannot execute in the intended se quence thus the watchdog timer overflows to detect errors Programming of the watchdog timer is generally done in the last step of its programming to Detect Incorrect Code Execution The watchdog timer i
87. 1 Overview LCD driver clock The source clock is the main clock fosc 1 218 1 217 1 26 1 215 1 214 1 213 1 212 1 21 The source clock is the sub clock fx 1 29 1 28 1 27 1 26 LCD power supply LCD power supply is separated from Vpp Available at gt lt 5 5 V Supply voltage can be selected from internal voltage booster output or external supply voltage The voltage booster performs three times boosting input voltage or 3 2 times boosting of input voltage External supply voltage is input from Vice and Vics pins Or voltage applied to Vic pin is divided by internal resistance to be used ports 42 ports LED large current driver ports 4 ports push pull configuration All 4 ports can be switched to PWM output LCD segment ports 24 ports LCD common ports 4 ports Serial ports 3 ports Timer I O ports 5 ports Timer remote control carrier output port 1 port Buzzer output port 1 port Input ports 7 ports External interrupt 3 ports one pin is also used as zero cross input A D input ports 4 ports Special pins 15 ports Analog reference voltage input pins 2 pins Operation mode input port 1 pin Reset input pins 1 pin Connection pins for boost up capacitor 2 pins LCD power supply pin including reference power supply for boosting 3 pins Oscillation pins 4 pins Power pins 2 pins 64 LQFP 14 m
88. 1 output 4 Set the standard PWM output 4 Set the TM7BCR flag of the TM7MD2 register operation to 0 to select the full count overflow as the TM7MD2 x 3F79 binary counter clear source bp5 TM7BCR 0 VII 30 16 bit Standard PWM Output Chapter 7 16 bit Timers Setup Procedure Description 5 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 6 Set period of the PWM output TM7PR1 x 3F75 x 3F74 x 4000 7 Start the timer operation TM7MD 1 x 3F78 bp4 7 1 5 Select fosc as the clock source by the TM7CK1 0 flag of the TM7MD1 register Also select 1 1 frequency no division at count clock source by the TM7PS1 0 flag Set H period of the PWM output to the timer 7 preset register 1 TM7PR1 To be a 1 4 duty of the full count 65536 set as follows 65536 4 16384 x 4000 At that time the same value is loaded to the timer 7 compare register 1 7 1 and the timer 7 binary counter TM7BC is initialized to x 0000 Set the TM7EN flag of the TM7MD1 register to 1 to start timer 7 TM7BC counts up from x 0000 The PWM source waveform outputs H until TM7BC reaches the set value of the TM7OC1 register then after the match it outputs L After that TM7BC continues to count up Once a overflow occurs the PWM source waveform outputs H again and TM7BC counts up from x 0000 again TM7IO pin outpu
89. 2 fs 4 fs 8 as cycle clock Use the prescalers when cycle clock based on fosc and fs is used on the following peripheral functions External interrupt 0 interface with noise filter External interrupt 1 interface with noise filter Timer 0 8 bit timer counter Timer 1 8 bit timer counter Timer 2 8 bit timer counter Timer 3 8 bit timer counter Serial 0 Clock synchronous Duplex UART Refer to chapter 2 2 5 Clock Switching 11 23 for fosc and fs V 2 Overview Chapter5 Prescaler 5 1 1 Peripheral Functions Table 5 1 1 shows the selectable clock sources used each functions used with prescaler block output Table 5 1 1 Functions Used with Prescaler Output Peripheral functions Clock source Meque Missi Timer 0 Timer 1 Timer 2 Timer 3 Serial 0 fosc 2 3 M fosc 4 4 4 4 J 4 fosc 16 4 4 NI N fosc 32 4 NI fosc 64 4 d 4 NI fosc 128 4 4 fosc 2 gt 4 fosc 2 5 5 5 4 fs 2 N N J fs 4 I 4 3 4 15 8 J Timer 3 output 4 Overview V 3 Chapter5 Prescaler 5 1 2 5 TMOPSCO TM2PSC1 SCOCKS SCOPSCO SCOPSCT SCOPSC2 V 4 Block Diagram TM1BAS TM1PSCO TM1PSC1 TM3BAS TM3PSCO TM3PSC1 Overview E Timer3 Ou X o9 Naso Si co sre 259 22829292229 9899
90. 21 VDLH 3 5 High detection voltage 22 VDHL 1 5 23 Von Figure 1 5 5 4 5 V Low detection voltage 24 0 5 25 Input leakage current 10 ViN 0 V 10 10 26 clamp current gt lt 0 V 400 ACZ pin 27 Rising time trs 30 Figure 1 5 5 us 28 Falling time tis 30 1 22 Electrical Characteristics Chapter 1 Overview Figure 1 5 5 Operation of AC Zero Cross Detection Circuit Electrical Characteristics 1 23 Chapter 1 Overview Ta 40 C to 85 2 0 V to 5 5 V Vss 0 V Parameter Symbol Conditions P a Unit MIN TYP MAX Input 4 PAO to 29 Input high voltage 1 0 8 30 Input high voltage 2 V pp 4 5 V to 5 5 V 0 7 Vpp 31 Input low voltage 1 Vis 0 0 2 32 Input low voltage 2 Vite V pp 4 5 V to 5 5 V 0 0 3 Vpp 33 leakage current ILks Vin 0 V to 2 34 Input current 1 5 30 100 300 uA 85 Input current 2 lus kis age oa 30 100 300 VO pin 1 P27 NRST 36 Input high voltage 0 8 37 low voltage 0 0 2 Vpp i 38 leakage current L ViN 0 V to 10 39 Input current 1 100 300 40 Output low voltage 5 0 V lo 21 0 mA 0 5 V VO pin 2 P00 P01 P02 P06 P10 to P15
91. 3 3 LCD Power Supply Connection 2 The LCD power supply Vict to is supplied as shown in the following figure 13 3 4 Vicp value varies depending on the type of LCD Refer to the specifications of LCD for the appropreate value Vici Vss Vic2 2 3 Vpp Vss Vics 1 3 Vss Usually Vpp Vss are divided by resistors and supplied to the LCD Standard registance voltage ranges from tens to several hundreds kQ In figure 13 3 4 a bypass capacitor C app 0 1 uF is used to lower the impedance of power supply Vpp Figure 13 3 4 Supplying voltage to Vici to 3 Operation XIII 17 Chapter 13 LCD Functions mSupplying voltage when using the internal voltage divider circuit Supply the voltage as shown in table 13 3 2 Table 13 3 2 LCD Power Supply Bias Lop s Method Static 1 2 1 3 Power Supply 2 Not used Connect 2 3 is output Vice to Vics I put 1 2 Vico is output 1 3 Vip is output Figure 13 3 5 shows examples of LCD power supply connection Stabilization condenser C for LCD power supply is recommended to be C 0 1 uF Cv20 1 should be connected as Stabilization condenser Cv for VDD power supply 1 2 duty 1 2 bias Vpp Vucp MN101C527 9 Input lt O 4 2 mT TI TI
92. 3F74 x 0004 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop timer 7 counting Set the P1DIR4 flag of the port 1 direction control register P1DIR to 0 to set P14 pin to input mode Add pull up pull down resistor if necessary 4 Ports Set the TM7BCR flag of the timer 7 mode register 2 TM7MD2 to 1 to select the compare match as a clear source for the binary counter Select the TM71O input as a clock source by the TM7CK1 0 flag of the TM7MD1 register Also select 1 1 no division as a count clock source by the TM7PS1 0 flag Set the interrupt generation cycle to the timer 7 preset register 1 TM7PR1 The set value should be 4 because the counting is 5 times At that time the same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter TM7BC is initialized to x 0000 VII 22 16 bit Event Count Chapter 7 16 bit Timers Setup Procedure Description 6 Set the interrupt level 6 Set the interrupt level by the TM7LV1 0 flag of TM7ICR x SFF1 the timer 7 interrupt control register TM7ICR bp7 6 STM7LV1 0 10 If any interrupt request flag is already set clear those request flags Chapter 3 3 1 4 Interrupt Flag Setup 7 Enable the interrupt 7 Setthe TM7IE flag of the TM7ICR register to TM7ICR x 3FF1 1 to enable interrupt bp1 1 8 Start the event count 8 Set
93. 5 2 4 2 Prescaler Selection Register CK2MD x 03F5E R W mTimer 3 Prescaler Selection Register CK3MD 2 1 0 CK3MD TM3PSC1 TMSPSCO TM3BAS At reset XXX 5 1 5 0 TM3BAS Clock source selection 0 fosc 4 1 0 fosc 16 3 0 fosc 64 1 fosc 128 0 15 2 1 15 8 Figure 5 2 5 Timer Prescaler Selection Register CK3MD x 03F5F R W V 8 Control Registers Chapter5 Prescaler serial interface transfer clock selection register SCnCKS selects the transfer clock used for serial interface transfer mSerial Interface 0 Transfer Clock Selection Register SCOCKS 7 6 5 4 3 2 1 0 SCOCKS SCOTMSEL SCOPSC2 SCOPSC1 SCOPSCO Atreset XXXX Clock source SCOTMSEL SCOPSC2 SCOPSC1 SCOPSCO selection 0 fosc 2 i i 1 fosc 4 _ 0 fosc 16 1 fosc 64 0 fs 2 0 4 1 15 4 0 Disable 0 1 3 1 Timer 3 output 1 0 Disable 1 Disable Figure 5 2 6 Serial Interface 0 Transfer Clock Selection Register SCOCKS x 03F97 R W Control Registers V 9 Chapter5 Prescaler 5 5 Operation 5 3 1 Operation Prescalers 0 and 1 Prescaler 0 and prescaler 1 15 bit 3 bit free running counter that divide the base clock The PSCEN flag of the prescaler con
94. 5 4 bit CMOS tri state VO port P51 7 LED1 Each bit can be set individually as either an input or P52 8 20 LED2 output by the P5DIR register A pull up resistor for each P53 9 LED3 bit can be selected individually by the P5PLU register At reset when the single chip mode is selected pull up resistor is disabled high impedance output on P50 to P53 input mode P60 37 vO SEG23 VO port 6 8 bit CMOS tri state VO port P61 38 KEY1 SEG22 Each bit can be set individually as either an input or P62 39 2 SEG21 output by the P6DIR register A pull up pull down P63 40 KEY3 SEG20 resistor for each bit can be selected individually by the P64 41 KEY4 SEG19 P6PLUD register However pull up pull down P65 42 KEY5 SEG18 resistors cannot be mixed P66 43 KEY6 SEG17 At reset when the single chip mode is selected pull up P67 44 KEY7 SEG16 resistor is disabled high impedance output on P60 to P67 input mode P70 45 VO SEG15 VO port 7 8 bit CMOS tri state VO port P71 46 SEG14 Each bit can be switched individually as either an input P72 47 SEG13 or output by the P7DIR register A pull up pull down P73 48 SEG12 resistor for each bit can be selected individually by the P74 49 SEG11 P7PLUD register However pull up and pull down P75 50 SEG10 resistors cannot be mixed P76 51 SEG9 At reset when the single chip mode is selected pull up P77 52 SEG8 resistor is disabled high impedance output on P70 to
95. 6 input mode register III 40 P6DIR x 03F36 RW 6 direction control register 26 P6PLUD x 03F46 R W Port 6 pull up pull down resistor control register 26 P6SYO x 03F1E R W Port 6 synchronous output control register 27 P7OUT x 03F17 R W Port 7 output register 31 P7IN x 03F27 R Port 7 input register 31 poe P7DIR x 03F37 RW Port 7 direction control register 31 P7PLUD x 03F47 R W Port 7 pull up pull down resistor control register 31 x 03F18 R W Port 8 output register IV 36 FORE P8IN x 03F28 8 input register 36 P8DIR x 03F38 RW Port 8 direction control register 36 x 03F48 R W Port 8 pull up resistor control register 36 2 R input register 40 Port A PAIMD x 03F3A R W Port A input mode register 40 R W Port A pull up pull down resistor control register 40 Pin control FLOAT x 03F2E R W Pull up Pull down resistor selection pin control register re 32 LCDMD2 xOSFDA RA LCD mode control register 2 19 XIII 7 ue LCCTR1 RA LCD output control register 1 V 33 37 control ANE LCCTR2 xOSFDC LCD output control register 2 IV 28 XIII 9 Overview IV 5 Chapter 4 Ports 4 2 Port 0 4 2 1 Description Port Setup Each bit can be set individually as either an input or output by the port 0 control I O directio
96. 7 6 T7OC2 T7OC2ICR 7 2 LV0 T7OC2 IE T7OC2 IR At 00 00 T7OC2IR Interrupt request flag 0 No interrupt request Generate interrupt request T7OC2IE Interrupt enable flag 0 Disable interrupt Enable interrupt T7OC2 T70C2 LVI LVO Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 13 Timer 7 Compare Register 2 match Interrupt Control Register T7OC2ICR x 03FF2 R W Control Registers HI 29 Chapter3 Interrupts mTimer 8 Interrupt Control Register TM8ICR The timer 8 interrupt control register TM8ICR controls interrupt level of timer 8 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 TM8 TM8 _ _ _ TM8ICR LVO 8 TM8IR At reset 0 0 00 TM8IR Interrupt request flag 0 No interrupt request 1 Generate interrupt request TM8IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt TMB Interrupt level LV1 LVO P 9 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 14
97. 8 1 esfera ec e ole sx MEM Ne eae VIII 2 8 1 1 ode ch bab dares VIII 2 8 1 2 Block Di gram pte EE ie 3 8 3 8 4 Control Registers npe Oe env ota cio oup p e Pe 4 8 2 1 Control Registers ther ptr 4 8 2 2 Programmable Timer Registers eee VIII 5 8 2 3 Timer Mode 2o eee Regem idest 6 8 bit Free running Timer iir prre tecti e rers 7 8 3 1 Operation aeree RUP eI EHE ER 7 8 3 2 Setup Example os eben oerte teet VIII 10 Time Dmet ee eee paier VIII 12 8 4 1 Operation t hm eget E VIII 12 8 4 2 Setup oo eer Rte Tere itg VIII 14 Chapter9 Watchdog Timer 9 1 9 2 9 3 OVE RUD UU RE UID IX 2 9 1 1 Block Dia Sram eR epe IX 2 Control Registers a eee p o Eee IX 3 Operation MC IX 4 9 3 1 niit e EOD Eo eed Sap 4 9 3 2 Setup Example eee tive IX 7 10 Buzzer 10 1 10 2 10 3 O aA TEA AR ERREUR X 2 10 1 1 Block Diagram eese nennen nennen nennen nenne X 2 Control Register eaten us e S X 3 pte t aer ER E B tede X 4 10 3 1
98. 8 bit Timers Binary counter is 8 bit up counter If any data is written to compare register the counting is stopped and binary counter is cleared to x 00 Timer 0 Binary Counter TMOBC 7 6 5 4 3 2 1 0 TMOBC 0 7 0 6 5 0 4 0 2 0 1 TMOBCO XX XXXXXX Figure 6 2 5 Timer 0 Binary Counter TMOBC x O3F50 R 1 Binary Counter TM1BC 7 6 5 4 3 2 1 0 TM1BC 1 7 TM1BC6 TM1BC5 1 1 TM1BC2 TM1BC1 TM1BCO Atreset X X X X X X X Figure 6 2 6 Timer 1 Binary Counter TM1BC 03 51 R 2 Binary Counter TM2BC 7 6 5 4 3 2 1 0 TM2BC TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 At reset X X X X X X X X Figure 6 2 7 Timer 2 Binary Counter TM2BC x 03F58 R mTimer 3 Binary Counter TM3BC 7 6 5 4 3 2 1 0 TM3BC TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 _ At reset X X X X X X X Figure 6 2 8 Timer Binary Counter TM3BC 03 59 R Control Registers VI 9 Chapter 6 8 bit Timers 6 2 3 Timer Mode Registers Timer mode register is readable writable register that controls timers 0 to 3 Timer 0 Mode Register TMOMD 7 6 5 4 3 2 1 0 TMOMD TMOMOD TMOPWM TMOEN TMOCK T
99. 9 Chapter 14 Appendices 14 2 Probe Switches 14 2 1 PRB MBB101C52 M This probe must be used with the following boards Connector board PX CN101 M MBB board PRB MBB101C52 M Adapter board PRB ADP101C64 M Dummy target PRB DMY101C52 M The dummy target should be connected when ICE is operated independently the adapter board should be connected at connection to the target This probe is mounted the switches for mask option The option switches are not available Figure1 Layout of option switches Option switches Default control Top view of MBB board Figure2 Composition with PRB MBB101C52 M Connector ji board 101 e MBB board PRB MBB101C52 M Dummy target Adapter board PRB DMY101C52 M PRB ADP101C52 M When ICE is operated independently At connection to the target XIV 10 Probe Switches Chapter 14 Appendices 14 2 2 101 This board can be used for MBB models product No PRB MBB101 M of MN101 series Please visit our website for the latest information on the product Figure1 PX CN101 M Layout n lt How to connect gt Figure2 Connecting a PX CN101 M to a MBB board Connector board PX CN101 M L V sure that points marked would be put together Caution MBB board PRB MBB101 M Caution
100. But when instruction execution time is estimated operation of instruction queue should be into consider ation Instruction decoder generates control signal at each cycle of instruction execution by micro pro gram control Instruction decoder uses pipeline process to decode instruction queue at one cycle before control signal is needed 2 1 5 Registers for Address Registers for address include program counter PC address registers 0 1 and stack pointer SP iProgram Counter This register gives the address of the currently executing instruction It is 19 bits wide to provide access to a 256 KB address space in half byte 4 bit increments The LSB of the program counter is used to indicate half byte instruction The program counter after reset is stored from the value of vector table at the address of 4000 18 Program counter 6 Overview Chapter 2 Basic CPU E Address Registers 0 1 These registers are used as address pointers specifying data locations in memory They support the operations involved in address calculations i e addition subtraction and comparison Those pointers are 2 byte data Transfers between these registers and memory are always in 16 bit units Either odd or even address can be transferred At reset the value of address register is undefined 15 0 mStack Pointer SP This register gives the address of the byte at the top of the stack It is decremented d
101. Chapter 6 8 bit Timers 6 6 3 PWM Output With Additional Pulse BPWM Output with Additional Pulse Method Timer 2 In the additional pulse method an additional bit is added to the 8 bit basic PWM output The bitO to3 can be added during 4 cycle of basic PWM output Whether or not and to which the additional bit is added during 4 cycles of basic PWM output can be controlled with the Timer 2 mode register TM2MD bit 6 7 iSetting the position of the Additional Pulses The positions of the additional pulse is set in the Timer 2 mode register TM2MD at bits 6 and 7 When TM2MD bits 6 and 7 are set as 00 no additional pulse is added to the basic PWM cycle When set as 11 3 out of the 4 periods in the basic PWM cycle are each added with an additional bit pulse Table 6 6 3 shows the relationship between the values TM2MD bits 6 and 7 and the additional pulses Figure 6 6 5 shows the relationship between values of TM2MD bits 6 and 7 and the positions of the additional pulses Table 6 6 3 TM2MD register set value Additional Pulse position PWM basic wave form 4 periods bit7 bit6 0 0 No additional Pulse 0 1 2 period 1 0 1 and 3 period 1 1 1 2 and 3 period VI 30 8 bit PWM Output Chapter 6 8 bit Timers PWM basic waveform 4 periods 1 gt PWM basic waveform 8bit 256 resolution
102. Figure 4 9 2 Port 8 Registers 2 2 Pot8 IV 37 Chapter 4 Ports 4 9 3 Block Diagram N R P8PLU0 to 7 Pull up resistor control gt Write L Y Read Hese R P8DIRO to 7 0 4 direction control DQ Write L Read 8 v Y 5 353 c P8OUTO to 7 Port output data 4 Write Read P8INO to 7 a Port input data Read Vict __ kH Data input Vic2 Segment output control gt Segment output data When segment output is selected segment output control automatically sets port I O direction control to input mode and segment output control is set to without pull up resistors Figure 4 9 3 Block Diagram P80 to P87 38 8 80 87 Chapter 4 Ports 4 10 PortA 4 10 1 Description Port Setup All bits of port A are for input only To read input data of pin read out the value of the port A input register PAIN Each bit can be set individually if pull up pull down resistor is added or not by the port A pull up pull down resistor control register PAPLUD Set the control flag of the port A pull up pull down resistor control register PAPLUD to 1 to add pull up or pull down resistor The pull up pu
103. IRQOICR x 3FE2 rising edge as the interrupt generation valid bp5 REDGO 1 edge 42 16 bit Timer Capture Chapter 7 Setup Procedure Description 6 Select the capture trigger generation edge TM7MD2 x 3F79 bp7 T7ZICEDG 1 Set the compare register TM7PR1 x 3F75 x 3F74 x FFFF 8 Set the interrupt level IRQOICR x 3FE2 bp7 6 IRQOLV1 0 10 9 Enable the interrupt IRQOICR x 3FE2 bp1 IRQOIE 1 10 Enable the capture trigger generation TM7MD2 x 3F79 bp2 7 1 11 Start the timer operation TM7MD 1 x 3F78 bp4 TM7EN 1 10 11 Set the T7ICEDG flag of the TM7MD2 register to 1 to select the external interrupt valid edge as a capture trigger source Set the timer 7 preset register 1 TM7PR1 to x FFFF At that time the same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter TM7BC is initialized to x 0000 Set the interrupt level by the IRQOLV1 0 flag of the IRQOIR register If any interrupt request flag is set already clear it t Chapter 3 3 1 4 Interrupt Flag Setup Enable the interrupt by setting the IRQ1IE flag of the IRQOICR register to 1 Enable the capture trigger generation by setting the T7ICEN flag of the TM7MD2 register to 1 Set the TM7EN flag of the TM7MD1 register to 1 to start timer 7 TM7BC counts up from x 0000 At the t
104. KEY4 SEG19 register SDO5 42 P65 KEY5 SEG18 When not used as synchronous output these can be SDO6 43 P66 KEY6 SEG17 used as normal pins SDO7 44 P67 KEY7 SEG16 Vret 18 power supply for Reference power supply pins for the A D converter A D converter Normally the value of VDD Vref and VDD Vref are Vret 23 power supply for used A D converter ANO 19 Input PAO Analog input pins Analog input pins for an 4 channel 10 bit A D AN1 20 PA1 converter AN2 21 PA2 When not used as an analog input pin these can be AN3 22 PA3 used as normal input pins IRQO 34 Input P20 External interrupt External interrupt input pins IRQ1 35 P21 ACZ input pins The valid edge for IRQ0 to 2 can be selected with the IRQ2 36 P22 IRQnICR register IRQ1 is able to deternine AC zero crossings Both edge for IRQ2 is valid for interrupt When not used as a interrupt pin these can be used as normal input pins ACZ 35 Input P21 IRQ1 AC zero cross Input pins for an AC zero cross detection circuit detection input The AC zero cross detection circuit outputs a high level pins when the input is at an intermediate level It outputs a low level at all other times ACZ input signal is connected to the P21 input circuit and the IRQ1 interrupt circuit When the AC zero cross detection circuit is not used this pin can be used as a normal P21 input KEYO 37 Input P60 SEG23 SDOO Key interrupt input Input pins for interrupt based on ORed result of pi
105. NORMAL mode HALTO mode fs is based on fosc high speed oscillation In SLOW mode IDLE mode HALT1 mode fs is based on fx low speed oscillation Chapter 2 2 5 Clock Switching Standby Functions II 19 2 Basic CPU 2 4 3 Transition between SLOW and NORMAL This LSI has two CPU operating modes NORMAL and SLOW Transition from SLOW to NORMAL requires passing through an idle state A sample program for transition from NORMAL to SLOW mode is shown below Program 1 MOV x 3 D0 MOV DO CPUM Set SLOW mode Transition from NORMAL to SLOW mode when the low frequency clock has fully stabilized can be done by writing to the CPU mode control register In this case transition through the idle state is not necessary For transition from the SLOW to NORMAL mode the program must maintain the idle state until high frequency clock oscillation is fully stable In the idle state the CPU operates on the low frequency clock do the counting a This stabilization time is the same as that required after a reset but here the program must 5 We recommend selecting the oscillation stabilization interval after consulting with the oscilla tor manufacturer Sample program for transition from SLOW to NORMAL mode is shown below Program 2 MOV x 01 DO Set IDLE mode MOV DO CPUM Program 3 MOV x 0B DO A loop to keep approx 6 7 ms with low frequency cl
106. OSF7B Timer 7 compare register 2 upper 8 bits VII 6 TM7PR2L X OSF7C R Timer 7 preset register 2 lower 8 bits VII 7 TM7PR2H X 03F7D RAN 7 preset register 2 upper 8 bits VII 7 TM7ICR 1 RAN Timer 7 interrupt control register 27 T OC2ICR X OSFF2 RA 7 compare register 2 match interrupt control register III 28 P1OMD 2 R W 1 output mode register 12 P1DIR X 03F31 RW 1 direction control register IV 11 TM8BCL X 03F80 Timer 8 binary counter lower 8 bits VII 8 TM8BCH X 03F81 R Timer 8 binary counter upper 8 bits VII 8 8 1 X 03F82 R Timer 8 compare register 1 lower 8 bits VII 6 TM8OC1H X 03F83 R Timer 8 compare register 1 upper 8 bits VII 6 TM8PR1L X 03F84 R W Timer 8 preset register 1 lower 8 bits VIL 7 TM8PR1H 85 R W Timer 8 preset register 1 upper 8 bits VII 7 Timer 8 TM8ICL X 03F86 R Timer 8 capture register 1 lower 8 bits VII 9 TM8ICH X 03F87 R Timer 8 capture register 1 upper 8 bits VII 9 TM8MD1 X 03F88 R W Timer 8 mode register 1 VII 12 TM8MD2 X 03F89 R W Timer 8 mode register 2 VII 13 TM8ICR X 03FF3 R W Timer 8 interrupt control register VII 29 P1OMD X OSF2F R W 1 output mode register 12 P1DIR X 03F31 RW Port 1 direction control register IV 11 R W Readable Writable R Readable only Control Registers VII 5
107. P1PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 1 pull up resistor control register P1PLU x 03F41 R W Figure 4 3 1 Port 1 Registers 1 3 Pot IV 11 Chapter 4 I O Ports 5 4 3 1 0 P1OMD P10 OMD4 P10MD3 P10 D2 P1OMD1 P1OMDO IV 12 Portl Atreset 0 00000 P1OMDO port timer 0 output selection 0 I O port 1 Timer 0 output P1OMD1 port timer 1 output selection 0 port 1 Timer 1 output P1OMD2 port timer 2 output selection 0 I O port 1 Timer 2 output P1OMD3 port timer output selection 0 I O port 1 Timer 3 output P1OMD4 port timer 7 output selection 0 I O port 1 Timer 7 output P1OMD5 port timer 8 7 output selection 0 I O port Timer 8 output Port 1 output mode register P1OMD x O3F2F R W Figure 4 3 2 Port 1 Registers 2 3 Chapter 4 Ports 4 3 3 Block Diagram Rese E P1PLUO r Pull up resistor control DQ gt Write Read Res
108. P20 IRQ1 input P21 0 IRQO Noise filter OFF IRQ1 Noise filter OFF 1 IRQO Noise filter ON IRQ1 Noise filter ON Cycle Setup External interrupts 0 and 1 The sampling cycle of noise remove function can be set by the NFnSCK1 0 flag of the NFCTR register Table 3 3 4 Sampling Cycle Time of Noise Remove Function 81 NFnckso Sampling High frequency oscillation cycle fosc 20 MHz fosc 8 MHz 0 fosc 20 MHz 50 ns 8 MHz 125 ns 9 1 28 78 13 kHz 12 80 us 31 25 kHz 32 us 0 fosc 2 39 06 kHz 25 60 us 15 62 kHz 64 us 1 fosc 2 19 53 kHz 51 20 us 7 81 kHz 128 us When fosc 25 fosc 2 or fosc 2 is selected as a sampling cycle set the PSCEN flag of the prescaler control register PSCMD to 1 for the prescaler to be in operating state in ad vance External Interrupts III 47 Interrupts 3 Interrupts iNoise Remove Function Operation External interrupts 0 and 1 After sampling the input signal to the external interrupt pins IRQO IRQ1 with the set sampling time if the same level comes continuously three times that level is sent to the inside of LSI If the same level does not come continuously three times the previous level is sent It means that only the signal with the amplitude of longer than Sampling time X 3 sampling clock can pass through the noise filter and other signals with amplitude shorter than this are
109. P50 to P53 are large current output pins and can be used as output pins of timer 0 timer 7 timer 2 and timer 8 The output mode for each pin can be selected with port 5 output mode register PBOMD When 1 is set to the port 5 output mode resister PSOMD each pin be used as the timer output pin When 0 is set to the port 5 output mode register PSOMD each pin can be used as the general purpose port pin Pot5 IV 21 Chapter 4 I O Ports 4 6 2 P5OUT P5IN P5DIR P5PLU IV 22 Registers 3 2 1 0 P5OUT3 P5OUT2 P5OUT1 P5OUTO Atreset XXXX P5OUT Output data 0 Low Vss level is output 1 High level is output Port 5 output register PBOUT x 03F15 R W 3 2 PSINO Port 5 input register P5IN x 03F25 R 3 2 1 0 PSDIR3 PSDIR2 PSDIR1 PSDIR0 Port 5 direction control register P5DIR x 03F35 R W 3 2 Atreset XXXX P5IN Input data 0 Pin is Low Vss level 1 Pin is High Vpp level Atreset 0000 1 0 P5PLU3 P5PLU2 P5PLU1 P5PLUO P5DIR mode selection 0 Input mode 1 Output mode Atreset 0000 P5PLU Pull up resistor selection 0
110. PC 12PC TBZ TBZ abs8 bp label if mem8 abs8 bp 0 PC 7 d7 label H PC 0 e 016 7 6 7 0011 0000 abs 8 d7 2 if mem8 abs8 bp 1 PC 73PC TBZ abs8 bp label if mem8 abs8 bp 0 PC 8 d1 label HPC O e 0 e 8 6 7 0011 0000 1bp abs 8 dii if mem8 abs8 bp 1 PC 8 PC 51 d4sign extension 2 d7 sign extension 3 411 sign extension Instruction Set XIV 17 Chapter 14 Appendices MN101C SERIES INSTRUCTION SET Mnemonic Operation Machine Code 6 7 8 TBZ TBZ io8 bp label if mem8 OTOP i08 bp 0 PC 7 d7 label H4PC O e 0 7 6 7 0011 0100 lt 08 gt d7 t 8 08 1 7 TBZ i08 bp label if mem8 IOTOP io8 bp 0 PC 8 d1 0 0 8 6 7 0011 0100 1bp lt 8 gt lt 41 72 8 08 1 8 2 abs16 bp label if mem8 abs16 bp 0 PC 9 d7 label HPC 0 0 9 7 8 0011 1110 abs 16 gt d 4 if mem8 abs16 bp 1 PC 9 PC TBZ abs16 bp label if mem8 abs16 bp 0 PC 10 d11 label HPC O amp 0 10 7 8 0011 1110 1bp abs 16 dil 2 if memB8 abs16 bp 1 PC 105PC TBNZ 2 abs8 bp label if mem8 abs8 bp 1 PC 7 d7 label HPC O 0 7 6 7 0011 0001 abs 8 d7 4 if mem8 abs8 bp 0 PC 7 PC TBNZ abs8 bp labe
111. RXD 25 Input 580 P01 UART received data input pin When the serial interface is used in UART mode this pinis configured as the received data input pin Pull up resistor can be selected by the POPLU register Select the input mode by the PODIR register and the serial input mode by the serial 0 mode register 1 SCOMD1 This can be used as a normal VO pin when the serial interface is not used TM2IO 28 29 30 31 VO P10 RMOUT P11 P12 P13 Timer VO pins Event counter clock input pins timer output and PWM signal output pins for 8 bit timers 0 to 3 To use these pins as event clock inputs configure them as inputs by the P1DIR register When the pins are used as inputs pull up resistor can be specified by the P1PLU register For timer output and PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register When not used for timer VO these can be used as normal VO pins RMOUT 28 vO P10 TMOIO Remote control transmission signal output pin Output pin for remote control transmission signal with a carrier signal For remote control carrier output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register Also set to the remote control carrier output by the remote control carrier output control register RMCTR
112. SEGO to SEG23 83 Vpp 5 V 0 5 V 15 30 Output impedance 84 RisEG2 Vpp 3 V 0 3 V 30 60 Dislpay power supply pin 1 Vici Vica Vics 85 Internal divided resistor Rv Ta 25 8 475 95 190 Vss impedance Display power supply pin 2 VLciv2 Vicins 86 ViciN2 at 3 2 times boost 2 3 3 6 Input voltage V 87 at 3 times boost Vpp 3 1 8 Electrical Characteristics I 25 Chapter 1 Overview 1 5 4 A D Converter Characteristics 40 to 85 C Vpp 20Vto 55V 55 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Nondinearity error 1 Vpp 5 0 V Vss 0 V Diff ial Vret 5 0 V Vret 5 0 V LSB 3 ifferential non linearity Tap 1 00 us 7 3 error 1 4 Zero transition voltage Vpp 5 0 Vss 0 V 30 100 Vret 5 0 V Vret 5 0 V mV 5 Full scale transition voltage 1 00 us 4900 4970 fosc 8 MHz 1 00 us te 28 A D conversion time 268 KH X 32 2 7 Tap 15 2 us 183 12 427 28 f 8 MH ES OSC 2 8 1 00 us 2d 180 Sampling time 32 2 9 Tap 15 2 30 52 274 68 10 Vret 2 0 Reference voltage 11 Vref Vss 3 0 V 12 Analog input voltage Vret 13 Analog input When channel is OFF 2 0 V to 5 V e 14 Reference voltage pin When is OFF 10 input leakage current Vret lt Vret lt VDD 15 Ladder re
113. Select the normal lower timer 2 operation TMOMD x 3F54 bp4 bp5 TM0MOD 0 0 Set the cascade connection 3 TM1MD x 3F55 bp4 1 5 1 Select the count clock source 4 TMOMD x 3F54 bp2 0 TMOCK2 0 001 Select the prescaler output and 5 enable counting CK0MD x 3F56 bp2 1 TMOPSC1 0 01 bp0 TMOBAS 1 PSCMD x 3F6F bp0 PSCEN 1 Set the interrupt generation cycle 6 TMnOC x 3F53 x 3F52 x 09C3 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 the TM1EN flag of the timer 1 mode register to 0 to stop timer 0 and timer 1 counting Set both of the TMOPWM flag and TMOMOD flag of the TMOMD register to 0 to select the normal timer 0 operation Set the TM1CAS flag of the TM1MD register to 1 to connect 1 and timer 0 in cascade connection Set the clock source to prescaler output by the 2 0 flag of the TMOMD register Set the prescaler output to fs 4 by the TMOPSC1 0 TMOBAS flag of the timer 0 prescaler selection register CKOMD Also set the PSCEN flag of the prescaler control register PSCMD to 1 to enable the prescaler counting Set the timer 1 compare register timer 0 compare register TM1OC to the interrupt generation cycle x O9C3 2500 cycles 1 At that time timer 1 binary counter timer 0 binary counter TM1BC are initialized to x 0000 VI 43 Cascade Connection Chapter
114. TM7CK1 7 0 Atreset 00100000 TM7CK1 TM7CKO Clock source selection 0 f 0 OSC 1 fs 0 TM7IO input 1 Synchronous TM71O input 7 51 TM7PSO Count clock selection 0 0 1 1 of clock 1 1 2 of clock 1 0 1 4 of clock 1 1 16 of clock TM7EN Timer 7 count control 0 Halt the count 1 Operate the count TM7CL Timer output reset control 0 Operate timer output 1 Disable timer output reset RESERVED Set always 0 Figure 7 2 21 Timer 7 Mode Register 1 TM7MD1 x 03F78 R W Control Registers Chapter7 16 bit Timers 7 Mode Register 2 TM7MD2 7 6 5 4 3 2 1 0 TM7MD2 T7ICEDG T7PWMSL TM7BCR TM7PWM 7 51 T7ICEN T7ICT1 T7ICTO Atreset 00000000 T7ICT1 T7ICTO Capture trigger selection 0 0 IRQO External interrupt 0 1 IRQ1 External interrupt 1 1 0 IRQ2 External interrupt 2 1 Unavailable T7ICEN Input capture operation enable flag 0 Disable capture operation 1 Enable capture operation Timer 7 interrupt 1 1 source selection 0 Counter clear 1 Match of BC and OC1 Timer output waveform selection 0 Timer output 1 PWM output Timer 7 counter clear TM7BCR source selection 0 Full count OVF 1 Matc
115. Timer 8 Interrupt Control Register TM8ICR x OSFF3 R W HI 30 Control Registers Chapter 3 Interrupts Serial 0 Interrupt Control Register 1 SCORICR The serial 0 interrupt control register 1 SCORICR controls interrupt level of serial 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 SCOR SCOR up se f SCORICR LV1 LVO SCORIE SCORIR at reset 0 0 00 SCORIR Interrupt request flag 0 No interrupt request flag 1 Generate interrupt request SCORIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SCOR SCOR LV1 LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt level flag Figure 3 2 15 Serial 0 Interrupt Control Register 1 SCORICR x 03FF5 R W Control Registers III 31 Chapter3 Interrupts Serial 0 Interrupt Control Register 2 SCOTICR The serial 0 interrupt control register 2 SCOTICR controls interrupt level of serial 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 SCOT SCOT 00 SCOTICR LV1 Lvo 5 E SCOTIE SCOTIR At reset 0 0 0 0
116. Timing of Simple Pulse Width Measurement Timer 0 Timer 2 Count clock source External interrupt IRQ TMnEN flag Compare FF regster Binary 00 01 Y 02 03 04 counter Figure 6 9 1 Count Timing at Measurement of Simple Pulse Width Timer 0 Timer 2 When the input signal of the external interrupt pin for simple pulse width measurement is L at TMnEN flag operation is 1 timer counts up VI 38 Simple Pulse Width Measurement 6 9 2 Setup Example Chapter6 8 bit Timers iSet up Example of Simple Pulse Width Measurement by 8 bit Timer Timers 0 and 2 The pulse width of L period of the external interrupt 0 IRQO input signal is measured by timer 0 The clock source of timer 0 is selected to fosc A setup procedure example with a description of each step is shown below Setup Procedure Description Stop the counter TMOMD x 3F54 bp3 TMOEN 0 Set the pulse width measurement operation TM0MD x 3F54 bp4 TMOPWM 0 bp5 TMOMOD 1 Select the count clock source TMOMD x 3F54 bp2 0 TMOCK2 0 000 Set the compare register TMOOC X 3F52 X FF Set the interrupt level IRQOICR x 3FE2 bp7 6 IRQOLV1 0 10 Set the interrupt valid edge IRQOICR x 3FE2 bp5 REDGO 1 Set the TMOEN flag of the timer 0 mode register TMOMD to stop timer 0 counting Set the TMOPWM flag of the TMOMD register to 0 and TMOMOD flag to 1 to enable the timer ope
117. Transmission Clock Selection Prescaler Output ANSH1 ANSH0 ANCK1 ANCK0 ANLADE X 3FB0 ANCTRO Sample Hold Time Conversion Clock A D Rudder XII 5 Resistance Control RESERVED RESERVED ANCHS1 ANCHSO X 3FB1 ANCTR1 Set always 0 Analog Input Channel XII 6 ANST RESERVED 2 2 Set XII 6 Conversion Status always 0 Special Function Registers List XIV 27 Chapter 14 Appendices Bit Symbol Initial Value Description Address Register Page Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 ANBUFO7 ANBUFO6 X 3FB3 ANBUFO A D Conversion Data XII 7 Storage Register Lower 2 Bits ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 X 3FB4 ANBUF1 Conversion Data Storage Register XII 7 Upper 8 Bits LCDEN LCREN LCDTY1 LCDTYO LCDCK3 LCDCK2 LCDCK1 LCDCK0 X 3FD9 LCDMD1 LCD Driver Internal Voltage LCD Display Duty Selection LCD Clock Source Selection XII 6 Circuit Divider Resistor Start Selection COMSL3 COMSL2 COMSL1 COMSLO UPCK UPEN X 3FDA LCDMD2 COM3 Port 33 COM2 Port 32 COM1 Port 31 COMO Port 30 Set always 0 E Voltage Booster yi Selection Selection Selection Selection Speed Control Operation LC1SL7 LC1SL6 LC1SL5 LC1
118. Y MMOD pin L Figure 2 2 1 Single chip Mode The value of internal RAM is uncertain when power is applied to it It needs to be initialized before it is used Memory Space II 13 2 Basic CPU Special Function Registers 2 2 3 MN101C series locates the special registers I O spaces at the address x 03F00 to x 03FFF in memory space The special function registers of this LSI are located as shown below Table 2 2 3 Register Map yoldy HOIL0OS HOIH00S HOVINL 03009 1dnui lul HOI9N1 HOISWL HOIZIAL HOILIAL HOIOWL YOIPOUI HOI0OHI HOIIAN loquo 407 2H1001 181901 a y LANNY 03n8NV ZHLONV EHLONV OHLONV 4 1 830095 20008 4 1 20 005 20 026 1014025 joawoos 10903 H193N eae LONSWL HOISIALL TOISWL HLOOSIL 1120901 1O088WL ZOWZWL HOIZWL HEYA ZW THA ZL HLOOZN1 I HOSZINLL 70811 1 H1981 209 1 ooenL OOZINL
119. Y PWM output Y Y High current timer output pin Y Y Additional pulse method PWM 2bit i Y E Synchronous output Y Serial transfer clock output Y Pulse width measurement Y Y Cascade connection Remote control carrier output Y Y fosc fosc fosc fosc fosc 4 fosc 4 fosc 4 fosc 4 fosc 16 fosc 16 fosc 16 fosc 16 fosc 32 05 213 fosc 32 fosc 64 Clock source fosc 64 fosc 2 fosc 64 fosc 128 fs 2 fs 2 fs 2 fs 2 fs 4 fs 8 fs 4 fs 8 fx fx fx fx TMOIO input TM11O input 2 input input fosc Machine clock High frequency oscillation fx Machine clock Low frequency oscillation fs System clock q Chapter 2 2 5 Clock Switching When timers 3 are used as a baud rate timer for serial function it is not used as a general timer Overview Chapter 6 8 bit Timers Block Diagram 6 1 2 Timers 0 and 1 Block Diagram OYIONL OWMd 1ndino OIOIALL jue e 1ndino snouo4upu S indino OI LIALL Jejunoo 16 8 1 ewwpeeu gt AAO 164 Jejunoo 119 8 2 a SVOE pomi DONN Toon uen SOOWL J9 s 6a1 aredwo9 luwpe u dois 1unoO 0 2 juoJuouAS GOWOWL 00482
120. at the same time When only reception with 3 channels are operated set SCOSBOS of the SC0MD1 register to 0 and select a port The SBO pin can be used as a general port When SBO SBI pin are connected for communication with 2 lines the SBO pin inputs outputs serial data The port direction control register PODIR switches I O At reception set SCOSBIS of the SCOMD1 register to 1 always to select serial data input The SBI pin can be used as a general port This serial interface contains a emergency reset function If the communication should be stopped by force set SCOSBOS and SCOSBIS of the SCOMD1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers except Table 11 2 1 TXBUFO RXBUFO are set Transfer rate of transfer clock set by SCOCKS register should be under 2 5 MHz When timer output is selected as serial interface transfer clock select fosc as a clock source of the timer If other clock is selected normal transfer of serial interface data is not guaran teed alealea mm Operation XI 29 Chapter 11 Serial Interface 0 11 3 3 UART Serial Interface Serial 0 can be used for duplex UART communication Table 11 3 12 shows UART serial interface functions Table 11 3 12 Serial Interface Functions XI 30 Operation Communication style UART dupl
121. b5 2a Data is rewritten by instruction Operation VII 15 Chapter 7 16 bit Timers Table 7 3 2 shows the clock source that can be selected Table 7 3 2 Clock Source at Timer Operation Timer 7 Timer 8 Clock source 1 count time fosc 50 ns fosc 2 100 ns fosc 4 200 ns fosc 16 800 ns fs 100 ns fs 2 200 ns fs 4 400 ns fs 16 1 6 us as fosc 20 MHz fs fosc 2 10 MHz mCount Timing of Timer Operation Timer 7 Timer 8 The binary counter counts up with the selected clock source as the count clock The basic operation of whole 16 bit timer functions is as bellow Count clock TMnEN flag Preset register Compare register Binary A m E D counter 0000 0002 000010001100021 0003 E Interrupt request flag Figure 7 3 1 Count Timing of Timer Operation Timer 7 Timer 8 A When a data is written to the preset register while the TMnEN flag is stopped 0 the same value is loaded during the writing cycle and the binary counter is cleared to x 0000 B When TMnEN flag is 1 the binary counter starts counting The counting starts at the falling edge of the count clock VII 16 Operation 7 16 bit Timers C Even if the preset register is rewritten when the TMnEN flag is 1 the binary counter is not changed D When the binary counter reaches value of compare register 1 the set v
122. bit timer counter which cannot stop operation except with a 8 bit free running timer at stand by mode STOP mode 8 1 1 Functions Table 8 1 1 shows the clock sources and the interrupt generation cycles that timer 6 and time base timer can use Table 8 1 1 Source and Generation Cycle Timer 6 8 bit free running 8 bit timer operation Interrupts TBIRQ TM6IRQ fosc fx fs fosc fosc X 1 212 7 fx fosc X 1 213 fk X 1 272 7 fx X 1 23 2 source fosc X 1 27 fosc X 1 25 fosc X 1 29 fosc X 1 2 9 7 fosc X 1 213 1 The interrupt generation Interrupt generation fosc X 1 25 cycle is decided by the cycle fx X 1 27 arbitrary value written to fx X 1 28 6 fx X 1 29 2 fx X 1 2109 72 fx X 1 28 72 fx X 1 215 72 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation fs System clock g Chapter 2 2 4 Clock Switching be used when a clock source of time base timer is selected to be used when a clock source of time base timer is selected to fx Time base timer and timer 6 cannot stop timer 6 counting VIII 2 Overview Chapter8 Time Base Timer 8 bit Free running Timer Block Diagram 8 1 2 Timer 6 Time Base Timer Block Diagram euin eseq Lak g o b e ell or g k o b Tu mt x St 1s n N
123. bp7 0 POOUT7 0 x 55 Set the synchronous output pin P6SYO x 3F1E bp7 0 65 07 0 xFF P6DIR x 3F36 bp7 0 P6DIR7 0 x FF Set the synchronous output data P6OUT x 3F 16 bp7 0 0 Event is generated Rising edge is generated at P22 Setthe SYOEVS1 0 flag of the FLOAT register to 00 to set the synchronous output event to the IRQ2 Set the REDG flag of the IRQ2ICR register to 1 to set the active edge of the IRQ2 at the rising edge Set the EDGSEL2 flag of the EDGDT register 0 to select the programmable active edge interrupt Set the initial output data 55 to the POOUT register Port 6 outputs 55 Set port 6 to synchronous output pin by setting the P6SYO7 0 flag of the PeSYO register to FF Select the output mode by setting the P6DIR7 0 flag of the P6DIR register to FF Set the synchronous output data AA to the P6OUT register Port 6 outputs AA at the rising edge of IRQ2 Synchronous Output Port 6 IV 47 5 Prescaler Chapter5 Prescaler 5 1 Overview This LSI contains 2 prescalers that are used among the peripheral functions simultaneously Each prescaler counts with fosc or fs as a base clock The hardware is as follows Prescaler 0 fosc base 15 bit prescaler Prescaler 1 fs base 3 bit prescaler Prescaler 0 outputs fosc 2 fosc 4 fosc 16 fosc 32 fosc 64 fosc 128 fosc 2 3 fosc 2 5 as cycle clock Prescaler 1 outputs fs
124. can be used for both clock synchronous and duplex UART 11 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 11 3 1 shows activation factors for communication At master communication the transfer clock is generated by setting data to the transmission data buffer TXBUFO or by receiving a start condition Except during communication the input signal from SBT pin is masked to prevent errors by noise or so This mask can be released automatically by setting a data to TXBUFO access to the TXBUFO register or by inputting a start condition to the data input pin Therefore at slave communication set data to TXBUFO or input an external clock after a start condition is input Table 11 3 1 Synchronous Serial Interface Activation Factor Activation factor Transmission Reception Set dummy data at master Set transmission data Input start condition Input clock Input clock after after dummy data is set at slave transmission data is set Input clock after start condition is input mTransfer bit Setup The transfer bit count is selected from 1 bit to 8 bits Set them by the SCOLNG 2 to 0 flag of the SCOMDO register at reset 111 The SCOLNG 2 to 0 flag holds the former set value until it is set again Except during communication SBT pin is masked to prevent errors by noise At slave communication set data to TXBUFO or input clock to SBT pin after a start condition is inp
125. contains an internal LCD driver circuit with 24 segment pins and 4 common pins The LCD driver consists of a segment output latch LCD control registers a prescaler a timing control circuit a multiplexer segment drivers common drivers a LCD voltage control circuit voltage booster circuit and voltage divider resistors 13 1 1 Functions Table 13 1 1 shows the functions of the LCD driver circuits XII 2 Table 13 1 1 LCD Functions Duty Static 1 2 Duty 1 3 Duty 1 4 Duty Common Output Pins COMO to COM3 Booster Circuit to drive LCD VLc1 input voltage can be divided into 2 8 1 8 Selectable from High resistance or low resistance LCD Voltage Divider Resistor fosc 2 fosc 2 2 05 213 fosc 214 fosc 2 5 Clock Source fosc 216 LCDCLK fosc 2 fosc 2 8 fx 26 fx 27 fx 28 fx 29 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation LCDCLK LCD clock source selected with LCDCKO to LCDCK3 When LCD function is unused VLC1 VLC2 VLC3 C1 and C2 pins should be fixed to VDD level Use the LCD panel driver voltage VLcp as Vpp lt VLCD lt 5 5 V Functions Chapter 13 LCD Functions 13 1 2 LCD Operation in Standby Mode Certain LCD driver operation could be limited in standby mode Table 13 1 2 shows the LCD operation capabilities in standby mode Table 13 1 2 LCD Operation in Standby Mode LCD Clock stow Operation Mode e TES O LC
126. control register P8DIR x 03F38 R W 7 6 5 4 3 2 1 0 P8PLU P8PLU7 P8PLUG P8PLUS P8PLU4 P8PLUS P8PLU2 P8PLU1 Atreset 00000000 P8PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 8 pull up resistor control register P8PLU x 03F48 RAW Figure 4 9 1 Port 8 Registers 1 2 IV 36 Port8 Chapter 4 Ports 7 6 5 4 3 2 1 0 LCCTR1 LC1SL7 LC1SL6 LC1SL5 LC1SL4 LC1SL3 LC1SL2 LC1SL1 LC1SLO At reset 00000000 LC1SLO SEG7 6 Port 80 81 selection 0 Port 80 81 selection 1 SEG7 6 selection LC1SL1 SEG5 4 Port 82 83 selection 0 Port 82 83 selection 1 SEG5 4 selection LC1SL2 SEG3 2 Port 84 85 selection 0 Port 84 85 selection 1 SEG3 2 selection LC1SL3 SEG1 0 Port 86 87 selection 0 Port 86 87 selection 1 SEG1 0 selection LC1SL4 SEG8 9 Port 77 76 selection 0 Port 77 76 selection 1 SEG8 9 selection LC1SL5 SEG10 11 Port 75 74 selection 0 Port 75 74 selection 1 SEG10 11 selection LC1SL6 SEG12 13 Port 73 72 selection 0 Port 73 72 selection 1 SEG12 13 selection LC1SL7 SEG14 15 Port 71 70 selection 0 Port 71 70 selection 1 SEG14 15 selection LCD output control register 1 LCCTR1 X 03FDB R W
127. d4 SP Dm 44 5 3 2 0110 01Dm lt d4 gt 2 MOV d8 SP Dm mem8 d8 SP Dm 5 3 0010 0110 01Dm lt d8 gt 3 d16 SP Dm mem8 d16 SP gt Dm 7 4 0010 0110 00Dm lt d16 gt MOV i08 Dm mem8 IOTOP i08 Dm 412 0110 00Dm io8 gt abs8 Dm 8 58 4 2 0100 01Dm abs 8 gt abs12 Dm mem8 abs12 5Dm 5 2 0100 00Dm abs 12 gt abs16 Dm mem8 abs16 5Dm 7 4 0010 1100 00Dm lt abs 16 gt MOV Dn Am Dn mem8 Am 2 2 0101 1aDn Dn d8 Am gt 8 08 412 0111 1aDn d8 gt zi MOV Dn d16 Am Dn mem8 d16 Am 7 4 0010 0111 laDn lt d16 gt MOV Dn d4 SP Dn mem8 d4 SP 312 0111 01Dn lt d4 gt 72 MOV Dn d8 SP Dn mem8 d8 SP ce 5 3 0010 0111 01Dn lt 8 gt 3 Dn d16 SP Dn mem8 d16 SP 7 4 0010 0111 00Dn lt d16 gt MOV Dn io8 Dn mem8 IOTOP i08 4 2 0111 00Dn io8 gt Dn abs8 Dn mem8 abs8 41 2 0101 01Dn lt abs 8 gt MOV Dn abs12 Dn mem8 abs12 5 2 0101 00Dn abs 12 gt MOV Dn abs16 6516 7 4 0010 1101 00Dn abs 16 MOV imm8 io8 imm8 mem8 IOTOP i08 6 3 0000 0010 lt io8 gt lt 8 gt MOV imm8 abs8 imm8 gt mem8 abs8
128. data to address X 00000 to X 1 FFFF 4 After confirming the device type write the loaded program in 3 to this LSI address from 4000 to the final address of the internal ROM The internal ROM space of this LSI starts from x 4000 t Chapter 2 Memory Space auto device selection command of ROM writer If the auto device selection command is to be a This writer has no internal ID codes of Silicon Signature and Intelligent Identifier of the for this writer the device is likely damaged Therefore never use this command When the writing is disabled When the writing is disabled check the following points 1 Check that the device is mounted correctly on the socket pin bending connection failure 2 Check that the erase check result is no problem 3 Check that the adapter type is identical to the device name 4 Check that the writing mode is set correctly 5 Check that the data is correctly transferred to the ROM writer 6 Recheck the check points 1 2 and 3 provided on the above paragraph of Cautions on Handling the ROM writer nw eNO XIV 8 EPROM Versions Chapter 14 Appendices 14 1 7 Programming Adapter Connection O QN FOr m m m m m m m m m m m m 9 99 g82 QQ O G n lt lt lt lt gt gt gt gt n n n n n n n n tT MON rT sb QN ODO
129. equivalent of 15 to 20 minutes 2 cm to 3 cm below a commercial ultraviolet lamp producing an illumination intensity of 12 000 uW cm at the package surface Remove any filters attached to the lamp Installing a lamp reflector increases the illumination intensity by a factor of 1 4 to 1 8 decreasing the erasure time If the window becomes dirty with oil adhesive etc UV light permeability will decrease causing the erasure time to increase considerably If this happens clean with alcohol or another solvent that will not harm the package The recommended above provides sufficient leeway with several times the amount of time it takes to erase all the bits However this value will reliably erase data over all temperature and voltage ranges and should not be altered The level of illumination should be regularly checked and the lamp operation verified Erasure begins when the EPROM is exposed to light with a wavelength shorter than 400 nm Since fluorescent light and sunlight have wavelengths in this range exposure to these light sources for ex tended periods of time could cause inadvertant erasure To prevent this cover the window with an opaque label Data is not erased at wavelengths However because of typical semiconductor characteristics the circuit may malfunction if the chip is exposed to an extremely high illumination intensity The chip will operate normally if this exposure is stopped However for areas where it is continuous take n
130. except at recovering from STOP mode and at reset releasing The watchdog timer is initialized at reset or at STOP mode and counts system clock fs as a clock source from the initial value x 0000 The oscillation stabilization wait time is set by the oscillation stabilization control register DLYCTR After the oscillation stabilization wait time is over counting is continued as a watchdog timer 4 2 2 6 Reset Ix 2 Overview Chapter 9 Watchdog Timer 9 2 Control Registers The watchdog timer is controlled by the watchdog timer control register WDCTR iIWatchdog Timer Control Register WDCTR 7 6 5 4 3 2 1 0 WDCTR WDTC2 WDTC1 WDTCO WDTS1 WDTSO WDEN 000 110 WDEN Watchdog timer enable 0 Watchdog timer is stopped 1 Watchdog timer is operated WDTS1 WDTSO Watchdog time out period setup 0 216 of system clock 218 of system clock 1 x 220 of system clock WDTC2 WDTC1 WDTC0 Watchdog timer can be cleared at the following cycle or more 215 of system clock 217 of system clock 219 of system clock 0 0 no limit Q 1 27 of system clock 0 29 of system clock 1 211 of system clock 0 213 of system clock 1 0 1 Figure 9 2 1 Watchdog Timer Control Register WDCTR x 03F02 R W Control Registers 3 Chapter9 Watchdog Timer 9 3 Operation 9 3
131. frequency oscillator is turned off the device consumes less power while executing the software Mode This mode allows time for the high frequency oscillator to stabilize when the software is changing from SLOW to NORMAL mode To reduce power dissipation in STOP and HALT modes it is necessary to check the stability of both the output current from pins and port level of input pins For output pins the output level should match the external level or direction control should be changed to input mode For input pins the external level should be fixed This LSI has two system clock oscillation circuits OSC is for high frequency operation NORMAL mode and XI is for low frequency operation SLOW mode Transition between NORMAL and SLOW modes or to standby mode is controlled by the CPU mode control register CPUM Reset and interrupts are the return factors from standby mode A wait period is inserted for oscillation stabilization at reset and when returning from STOP mode but not when returning from HALT mode High low frequency oscillation mode is automatically returned to the same state as existed before entering standby mode quency and low frequency high frequency oscillation frequency fosc should be set to 2 5 1 To stabilize the synchronization at the moment of switching clock speed between high fre times or higher frequency than the low frequency oscillation frequency fx II 18 Standby Functions Chap
132. from an interrupt vector table reset non maskable interrupts NMI 9 maskable peripheral interrupts and 14 internal interrupts For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing After the interrupt is accepted the program counter PC and processor status word PSW and handy addressing data HA are saved onto the stack And an inter rupts handler ends by restoring using the POP instruction and other means the contents of any regis ters used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was interrupted Max 12 machine cycles before execution and max 11 machine cycles after execution Each interrupt has a interrupt control register which controls the interrupts Interrupt control register consists of the interrupt level field LV1 0 interrupt enable flag IE and interrupt request flag IR Interrupt request flag IR is set to 1 by an interrupt request and cleared to 0 by the interrupt accep tance This flag is managed by hardware but can be rewritten by software Interrupt enable flag IE is the flag that enables interrupts in the group There is no interrupt enable flag in non maskable interrupt NMI Once this interrupt request flag is set it is accepted without any condi tions Interrupt enable flag is set in maskable interrupt Interrupt enable flag o
133. generated depending on the setting of the lowest value for clear ilMain Routine Program Watchdog Timer Constant Clear Setup Example Setup Procedure Description 1 Setthe watchdog timer for the 1 Clear the watchdog timer by the cycle from 2 constant clear x system clock up to 2 x system clock Writing to WDCTR x O3F02 cf BSET WDCTR WDEN The watchdog timer clear should be inserted in 6 WDEN 1 the main routine with the same cycle and to be the set cycle The recommended instruction is the bit set BSET does not change value for clear Operation IX 7 Chapter9 Watchdog Timer Service Routine Setup Setup Procedure Description 1 Set the watchdog interrupt service routine NMICR x 03FE1 TBNZ NMICR WDPRO 1 If the watchdog timer overflows the non maskable interrupt is generated Confirm that the WDIR flag of the non maskable interrupt control register NMICR is 1 on the interrupt service routine to manage the suitable execution 1 The operation just before the WDOG interrupt may be executed wrongly Therefore if the WDOG interrupt is generated initialize the system IX 8 Operation Chapter 10 Buzzer Chapter 10 Buzzer 10 1 Overview This LSI has a buzzer It can output the square wave that multiply by 1 2 to 1 2 of the high frequency oscillation clock or by 1 2 to
134. in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out in out PODIR6 P1DIRO P1DIR1 P1DIR2 P1DIR3 P1DIR4 P1DIR5 P3DIRO P3DIR1 P3DIR2 P3DIR3 P5DIRO P5DIR1 P5DIR2 P5DIRS3 P6DIRO P6DIR1 P6DIR2 P6DIR3 P6DIR4 P6DIR5 P6DIR6 P6DIR7 P7DIR0 P7DIR1 P7DIR2 P7DIR3 P7DIR4 P7DIR5 P7DIR6 P7DIR7 P8DIR0 P8DIR1 P8DIR2 P8DIR3 P8DIR4 P8DIR5 P8DIR6 P8DIR7 POPLU6 P1PLU0 P1PLU1 P1PLU2 P1PLU3 P1PLU4 P1PLU5 P2PLU0 P2PLU1 P2PLU2 P3PLU0 P3PLU1 P3PLU2 P3PLU3 P5PLU0 P5PLU1 P5PLU2 P5PLU3 P6PLUD0 P6PLUD1 P6PLUD2 P6PLUD3 P6PLUD4 P6PLUD5 P6PLUD6 P6PLUD7 P7PLUD0 P7PLUD1 P7PLUD2 P7PLUD3 P7PLUD4 P7PLUD5 P7PLUD6 P7PLUD7 P8PLU0 P8PLU1 P8PLU2 P8PLU3 P8PLU4 P8PLU5 P8PLU6 P8PLU7 PAPLUD0 PAPLUD1 PAPLUD2 PAPLUD3 BUZZER Buzzer output Timer 0 input output 1 Timer 1 nitput output 2 Timer 2 input output Timer 3 input output TM7IO Timer 7 input output TMBIO Timer 8 input output IRQO External interruption 0 IRQ1 External interruption 1 IRQ2 External interruption 2 NRST Reset COMO LCD common output COM1 LCD common output COM2 LCD common output COM3 LCD common output TMOO Ti
135. input data N Read Timer output Figure 4 6 3 Block Diagram P50 to P52 ne nese 2 2 axe Pull up resistor control D Q gt Write Read P5DIR3 direction control D Q gt Write ck N Z Read e P53 E P50UT3 M Port output data 5 U ru Write jCK N FA Read X 777 Pese P5OMD3 Output mode control D Q e Write Read Port input data x N Timer 8 output IV 24 Port5 Read Figure 4 6 4 Block Diagram P53 Chapter 4 Ports 4 7 Port 6 4 7 1 Description ilGeneral port Setup Each bit can be set individually to either an input or output by the port 6 I O direction control register P6DIR The control flag of the port 6 direction control register PeDIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port 6 direction control register PEDIR to 0 and read the value of the port 6 input register P6IN To output data to pin set the control flag of the port 6 direction control register P6DIR to 1 and write data to the port 6 output register PEOUT Each bit can be set individually if pull up pull down resistor is added or not by the port 6 pull up pull down resistor control register Set the control flag of the port 6 pull up pull down resistor control register P6PLUD to 1 to add pull up or pull down resist
136. interrupt at the selected edge iaProgrammable Active Edge Interrupt Setup Example External interrupt 0 to 2 External interrupt 0 IRQO is generated at the rising edge of the input signal from P20 The table below provides a setup example for IRQO Setup Procedure Description IRQOICR x 3FE2 bp5 REDGO 2 Setthe interrupt level IRQOICR x 3FE2 bp7 6 3 Enable the interrupt IRQOICR x 3FE2 bp1 IRQOIE 1 Specify the interrupt active edge 1 IRQOLV1 0 10 1 Set the REDGO flag of the external interrupt 0 control register IRQOICR to 1 to specify the rising edge as the active edge for interrupts Set the interrupt priority level in the IRQOLV1 0 flag of the IRQOICR register If the interrupt request flag has been already set clear the request flag t Chapter 3 3 1 4 Interrupt flag setup Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt External interrupt O is generated at the rising edge of the input signal from P20 1 Interrupt request flag set at switching the interrupt edge so specify the interrupt valid edge before the interrupt permission The external interrupt pin is recommended to be pull up advance g When the programmable active edge interrupt is specified for external interrupt 2 IRQ2 set the EDGSELn flag of the both edge interrupt control register EDGDT to 0
137. is selected by the port 6 direction control register PeDIR if the synchronous output is enabled by the synchronous output control register P6SYO the value of the synchronous output value stored register is output from pins If the synchronous output event that is set by the pin control register FLOAT is never generated the synchronous output value stored register holds the same value when the synchronous output event is enabled Store the value that should be output from pin after the synchronous output event is generated to the port 6 output register POUT Once the synchronous output event that is set by the pin control register FLOAT is generated the data of the synchronous output value stored register is switched to the data of the port 6 output register PGOUT and the output value from pin is changed Before the synchronous output is enabled by the synchronous output control register P6SYO set the initial value of the synchronous output to the port 6 output register 6 in advance Synchronous Output Port 6 IV 45 Chapter 4 I O Ports 6 Synchronous Output External interrupt 2 IRQ2 The synchronous output timing when the synchronous output event is set at the falling edge of the external interrupt 2 is shown below The latched data on port 6 is output in synchronization with the falling edge of the IRQ2 Port 6 output X latch data mE NE ts i External interrupt IRQ2 F
138. may cause any damage to the ICE Figure 1 PRB DMY101C52 M Layout lt How to connect gt Connector board PX CN101 M COC v R MBB board 101 52 Make sure that the points marked would be put together Caution1 Dummy target PRB DMY101C52 M Caution Connect CNE of PRB MBB101C52 M to CNE of PRB DMY101C52 M and CNF of PRB MBB101C52 M to CNF of PRB DMY101C52 M When connect the boards make sure that they are connected without tilt If put pressure on one side of the board that cause any damage to the pins Probe Switches 13 Chapter 14 Appendices 14 3 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag CodeCycle Re Machine Code Notes CF zF Size peat Ex 1 2 3 4 5 6 7 8 9 10 11 Data Move Instructions MOV MOV Dn Dm Dn Dm 2 1 1010 DnDm imm8 Dm imm8 Dm 41 2 1010DmDm lt 8 gt Dn PSW Dn PSW eee e 3 3 0010 1001 01Dn MOV PSW Dm PSWDm 31 2 0010 0001 01Dm MOV An Dm mem8 An Dm 2 2 0100 1ADm MOV d8 An Dm mem8 d8 An gt Dm 412 0110 1ADm lt 08 gt MOV d16 An Dm 416 7 4 0010 0110 1ADm lt d16 gt
139. of TXBUFO the transmission is operated from A to F TXBUFO F E D C B Figure 11 3 1 Transfer bit Count and First Transfer bit starting with MSB TXBUF0 F E D C B Figure 11 3 2 Transfer bit Count and First Transfer bit starting with LSB bit Count and First Transfer bit When the transfer bit count is 1 bit to 7 bits the data storing method to the received data buffer RXBUF0 is different depending on the first transfer bit At MSB first data are stored to the lower bits of RXBUF0 When there are 6 bits to be transfered as shown on figure 11 3 3 if data to F are stored to bp0 to bp5 of RXBUF0 the transmission is operated from F to A At LSB first data are stored to the upper bits of RXBUF0 When there 6 bits to be transfered as shown on figure 11 3 4 if data A to F stored to bp2 to bp7 of RXBUF0 the transmission is operated from A to F RXBUF0 F E D Figure 11 3 3 Receive bit Count and Transfer First bit starting with MSB bit RXBUF0 F E D Figure 11 3 4 Receive bit Count Transfer First bit starting with LSB bit 14 Operation Chapter11 Serial Interface 0 iContinuous Communication This serial has function for continuous communication If data is set to the transmission data buffer TXBUFO during communication the transmission buffer empt
140. or to low frequency input low speed mode The system clock is generated by dividing the oscillation clock The best operation clock for the system can be selected by switching its frequency by software A machine cycle min instruction execution time is 250 ns when the oscillation source fosc is 8 MHz and a machine cycle is 100 ns when fosc is 20 MHz Two types of packages are available 64 pin LQFP 1 1 2 Product Summary This manual describes the following models of the MN101C52 series These products have identical functions Table 1 1 1 Product Summary ROM Size RAM Size Classification MN101C527 16 KB 1 5 KB Mask ROM version MN101CP52A 32 KB 1 5 KB EPROM version I 2 Overview Chapter 1 Overview 1 2 Hardware Functions CPU Core Internal memory Interrupts MN101C Core LOAD STORE architecture 3 stage pipeline Half byte instruction set Handy addressing Machine cycle at 2 divide of crystal oscillation High speed mode 0 10 us 20 MHz 4 5 V to 5 5 V 0 25 us 8 MHz 2 7 V to 5 5 V 0 5 us 4 MHz 2 3 V to 5 5 V 1 0 us 2 MHz 2 0 V to 5 5 V 1 Low speed mode 62 5 us 32 kHz 2 0 V to 5 5 V 1 1 Minimum rating for EPROM vers is 2 3 V to 5 5 V Clock gear The operation speed of system clock can be changed by switching divide ratio of the oscillation with software Operation modes NORMAL mode High speed mode SLOW mode Low speed mode HALT mode STOP mode The operation c
141. pins LCDMD2 X 3FDA bp7 4 COMSL3 0 LCCTR1 X SFDB bp3 2 LC1SL3 2 1111 11 Select the LCD clock source LCDMD1 X 3FD9 bp3 0 CDCK3 0 0111 Select the LCD display duty LCDMD1 X 3FD9 bp5 4 CDTY1 0 00 Setup the LCD panel display data X 2E00 5 X 2bE01 X C7 Start the LCD driver circuit LCDMD1 X 3FD9 bp7 LCDEN 1 6 t Refer to 13 4 Display Set the UPEN flag of the LCD mode control register 2 LCDMD2 to 1 to operate voltage booster circuit Set the UPCK frag to 0 to set up the voltage booster speed to normal Set COMSLS to 0 flags of the LCD mode control register 2 LCDMD2 to 1111 to set up the common pins 3 to O Set the LC1SL3 2 flag of the LCD output con trol register LCCTR1 to 11 to set up the segment pins 3 to 0 Select OSC1 2 as the LCD clock source by LCDCKG to 0 flags of the LCD mode control register 1 LCDMD1 Set LCDTY1 to 0 flags of the LCD mode control register 1 LCDMD1 to 00 to set up the display duty Set up the display data on the address X 2E00 X 2E01 of the segment output latch Set the LCDEN flag of the LCD mode control register 1 LCDMD1 to 1 to start the LCD driver circuit Operation XIII 21 LCD Functions Chapter 13 LCD Functions If internal voltage booster circuit is used voltages of Vici Vice and Vic3 could be dropped depending on the load of used LCD panel
142. program counter and the processor status word PSW to the stack and branches program to the interrupt handler using the starting address in the vector table The following is the hardware processing sequence invoked by interrupt acceptance 1 stack pointer is updated SP 6 SP 2 The contents of the handy address register HA are saved to the stack Upper half of HA SP 5 Lower half of HA SP 4 3 The contents of the program counter PC i e the return m address are saved to the stack PC bits 18 17 and 0 SP 3 New SP PSW Lower after interrupt r PC bits 16 9 SP 2 PC8 1 PC bits 8 1 SP 1 016 97 4 contents of the PSW saved to the stack POO resewed pc 18 i7 Address PSW gt SP 7 0 5 interrupt level xxxLVn for the interrupt is copied to Old SP Higher the interrupt mask IMn in the PSW j before interrupt Interrupt level xxxLVn IMn acceptance 6 The hardware branches program to the address nc in the vector table Figure 3 1 5 Stack Operation Binterrupt Return Operation during interrupt acceptance An interrupt handler ends by restoring the contents of any registers saved to the stack during processing by the POP instruction and other means and the RTI instruction restores the program to the point at execution was interrupted The following is the
143. reduces code size 1 half byte bit Overview II 11 Chapter2 Basic CPU 2 2 Memory Space 2 2 1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable writable data In addition to these peripheral resources such as memory mapped special registers are allocated The MN101C52 series supports one memory mode single chip mode its memory model Table 2 2 1 Memory Mode Setup flag in Memory mode MMOD pin MEMCTR register Single chip mode L 0 Set the MMOD pin always to L level II 12 Memory Space Chapter 2 Basic CPU 2 2 2 Single chip Mode In single chip mode the system consists of only internal memory This is the optimized memory model and allows construction of systems with the highest performance The single chip mode uses only internal ROM and internal RAM The MN101C series devices offer up to 12 KB of RAM and up to 240 KB of ROM This LSI offers 1536 bytes of RAM and 16 KB of ROM A x 00000 256 bytes abs 8 addressing access area Internal RAM space 1536 bytes x 00100 Data Y x 00600 Y x 02E00 CD display data x 02E0B x 03F00 256 bytes Special function registers Y EE 04000 Interrupt 128 bytes vector table Y x 04080 Subroutine 64 bytes vector table T Internal 16 040 0 ROM space Instruction code table data x 07FFF
144. removed because those are regarded as noise meee IRQn pin input signal Waveform after filtering noise Figure 3 3 7 Noise Remove Function Operation Noise filter can not be used at STOP mode HALT mode and SLOW mode 48 External Interrupts Chapter 3 Interrupts iNoise Filter Setup Example External interrupt 0 and 1 Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 IRQO at the rising edge The sampling clock is set to fosc and the operation state is fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description Specify the interrupt active edge IRQOICR x 3FE2 bp5 REDGO 1 Select the sampling clock x 3F8E bp2 1 NFOSCK1 0 000 Set the noise filter operation bp0 NFOEN 1 Set the interrupt level IRQ0ICR x 3FE2 bp7 6 IRQOLV1 0 10 Enable the interrupt IRQOICR x 3FE2 bp1 IRQOIE 21 1 Setthe REDGO flag of the external interrupt 0 control register IRQOICR to 1 to specify the interrupt active edge to the rising edge 2 Select the sampling clock to fosc by the 05 1 0 flag of the noise filter control register NFCTR 3 Setthe NFOEN flag of the NFCTR register to 1 to add the noise filter operation 4 Setthe interrupt level by the IRQOLV 1 0 flag of the IRQOICR register If
145. s starting mode is NORMAL mode in which high oscillation is the base clock If the low power voltage detection circuit is connected to NRST pin design the circuit to supply enough low level time pulse at sudden disconnect Also beware of noise as reset could be generated even with the low level time pulse of less than 4 OSC clock cycle Reset II 25 Chapter 2 Basic CPU mSequence at Reset T 1 When reset pin comes to high level from low level system closk starts count operation by the ion The period from starting its count from its internal 10 bit counter watchdog timer dual funct overflow is called oscillation stabilization wait time After oscillation stabilization wait time is finished i During reset internal register and special function register are initiated nternal reset is released and program is started from the address written on x 04000 of vector table NRST internal NRST Oscillation sta pilization wait time Figure 2 6 2 Reset Released Sequence II 26 Clock Switching 2 6 2 Oscillation Stabilization Wait time Chapter 2 Basic CPU Oscillation stabilization wait time is the period from the stop of oscillation circuit to the stablization for oscillation Oscillaion stabilization wait time is automatically inserted at releasing from reset and at recov ering from STOP mode At recovering from STOP mode the oscillation stabilization
146. synchro nizing circuit output signal or the synchronizing circuit output signal that passed through the division circuit TMnIO input Systema sss clock fs Synchronous circuit output count clock TMnEN flag Compare register 1 Binary eee counter 0000 0001 0002 0003 N 1 0000 1 0001 Interrupt request flag Figure 7 4 2 Count Timing of Synchronous TMnIO Input Timer 7 Timer 8 The timer n binary counter counts up the binary counter at the signal in synchronization with the system clock so that correct value is read out from the timer n binary counter The return from STOP HALT mode is not possible by the synchronous TMnIO input 16 bit Event Count VII 21 Chapter 7 7 4 2 16 bit Timers Setup Example Count Setup Example Timer 7 Timer 8 When the falling edge of the TM7IO input pin signal is detected 5 times using timer 7 an interrupt is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 7 0 Set the special function pin to input mode P1DIR x 3F31 bp4 P1DIRA 0 Select the condition for timer clear TM7MD2 x 3F79 bp5 TM7BCR 1 Select the count clock source TM7MD1 x 3F78 bp1 0 TM7CK1 0 10 bp3 2 TM7PS1 0 00 Set the interrupt generation cycle TM7PR 1 x 3F75 x
147. the P2OUT register to 0 outputs low level at P27 NRST pin And transfering to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P2OUT7 flag becomes 1 and reset is released Key information Chapter 4 4 4 2 Registers Important information from the text On this LSI the starting mode is NORMAL mode that high oscillation is the base clock enough low level time at sudeen unconnected And reset can be generated even if its pulse 1 When the power voltage low circuit is connected to NRST pin circuit that gives pulse for z is low level as the oscillation clock is under 4 clocks take notice of noise I 44 Reset Summary Introduction to the section References References for the main text Precautions and warnings Precautions are listed in case Be sure to read these of lost functionality or damage About This Manual 2 mFinding Desired Information This manual provides three methods for finding desired information quickly and easily 1 2 3 Consult the index at the front of the manual to locate the beginning of each section Consult the table of contents at the front of the manual to locate desired titles Chapter names are located at the top outer corner of each page and section titles are located at the bottom outer corner of each page mRated Manuals Note that the following related
148. the TM7EN flag of the TM7MD1 register to TM7MD 1 x 3F78 1 to start timer 7 bp4 TM7EN 1 Every time TM7BC detects the falling edge of the TM7IO input it counts up x 0000 When the TM7BC reaches the set value of the TM7OC1 register the timer 7 interrupt request flag is set at the next count clock and the value of TM7BC becomes x 0000 to restart counting up 16 bit Event Count VII 23 Chapter 7 16 bit Timers 7 5 16 bit Timer Pulse Output 7 5 1 Operation TMnIO pin can output a pulse signal with an arbitrary frequency The pin large current pin output it too 16 bit Timer Pulse Output Operation Timer 7 Timer 8 These timers can output 2 x cycle signal compared with the set value of the compare register 1 TMnOC1 and the 16 bit full count Output pins are as follows Table 7 5 1 Timer Pulse Output Pin Timer 7 Timer 8 output TM8IO output P14 P15 Pulse output pin 7 output TM8O output P51 P53 Table 7 5 2 shows the timer interrupt generation sources and the flags that control the timer pulse output cycle Table 7 5 2 16 bit Timer Interrupt Generation Source and Timer Pulse Output Cycle Timer 7 Timer 8 TMnMD2 register TMnIRS1 flag TMnBCR flag Interrupt source Timer pulse output cycle 1 1 TMnOC1 compare match set value of TMnOC1 x 2 0 1 TMnOC1 compare match set value of TMnOC1 x 2
149. the execution time for main routine of program That should be set the longer cycle than the value of the execution time for main routine divided by natural number 1 2 And set the command of the watchdog timer clear to the main routine so that value makes the same cycle Lowest Value for Watchdog Timer Clear The lowest value for watchdog timer clear is decided by the bp5 4 3 WDTC2 WDTC1 WDTCO of the watchdog timer control register WDCTR Table 9 3 2 Lowest Value for Watchdog Timer Clear WDTC2 WDTC1 WATCO paie CS aiino 0 0 0 no limit 0 0 1 27 X system clock 0 1 0 29 X system clock 0 1 1 211 X system clock 1 0 0 213 X system clock 1 0 1 215 X system clock 1 1 0 217 X system clock 1 1 1 219 X system clock Operation IX 5 Chapter9 Watchdog Timer ilWatchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features as follows 1 2 3 4 5 6 In NORMAL IDLE SLOW mode the system clock is counted The counting is continued regardless of switching at NORMAL IDLE SLOW mode In HALT mode the watchdog timer is stopped In STOP mode the watchdog timer is cleared automatically In STOP mode the watchdog interrupt cannot be generated After releasing reset or recovering from STOP the counting is executed for the period of the oscillation stabilization wait time wre wre DHS DY Generally in t
150. the one with the lowest vector number takes priority For example if a vector 3 set to level 1 and a vector 4 set to level 2 request interrupts simultaneously vector 3 will be accepted Vector 1 Non maskable interrupt Priority Interrupt vector 1 Vector 1 Level 0 Vectors 2 5 6 2 Vector 2 3 Vector 5 Level 1 Vector 3 4 Vector 6 5 Vector 3 Level 2 Vectors 4 8 6 Vector 4 7 Vector 8 Figure 3 1 3 InterruptPriority Outline Overview HI 7 3 Interrupts mDetermination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance 1 a G gt gt The interrupt request xxxIR the corresponding external interrupt control register IRQnICR and internal interrupt control register xxxICR are set to 1 An interrupt request is input to the CPU If the interrupt enable flag xxxIE of the same register is 1 The interrupt request signal is set for each interrupt The interrupt level IL is input to the CPU The interrupt request is accepted If IL has higher priority than IM and MIE is 1 After the interrupt is accepted the hardware resets the interrupt request flag xxxIR in the interrupt control register xxxICR to O Current interrupt mask level IM Psw TI ZF Level judgement Accepted if IL IM 7 xxxICR ooLVipoxL V0
151. the range of 1 3 x Vica lt 1 8 V For 3 2 times 1 2 times voltage boosting input reference voltage Vica to voltage booster circuit in the range of 2 3 Vpp x Vice lt 3 6 V For 2 times voltage boosting input reference voltage Vic2 Vica to voltage booster circuit in the range of 1 2 Vpp lt Vice lt 2 7 V To generate LCD power supply Vic using LCD voltage booster circuit start the LCD volt age booster circuit and supply voltage right after reset For transition to STOP mode disable set 0 to the start flag of the LCD driver circuit and stop set 0 to the voltage booster start flag in advance Power from microcontroller is supplied to the LCD power supply Vic by this procedure after voltage booster circuit is switched to STOP mode 14 Operation Chapter 13 LCD Functions 13 3 3 Power Supply The LCD driver power pins are Vici Vice and Vics This LSI contains the internal voltage booster circuit as a dedicated power source for LCD drive and the voltage divider resistor to divide voltage for LCD drive There are three ways to supply voltage to the LCD driver to supply voltage to the Vici Vice and Vic3 pins from external source when external voltage divider resistor is used to supply voltage to Vict pin from external source and use internal divider resistor and to supply voltage to the Vic pin from external source and use the internal voltage divider resistor The power source for LCD drive a
152. timer 3 compare register TM3OC x 3F5B 2x67 such a value that baud rate comes to 300 bps t Chapter 11 Table 11 3 23 At that time the timer 3 binary counter is initialized to 00 6 Start the timer operation 6 Set the TMSEN flag of the TM3MD register to TM3MD x 3F5D to start timer 3 bp3 1 VI 36 Serial Transfer Clock Output Chapter6 8 bit Timers counts up from 00 Timer output is the clock of the serial interface 0 at transmission and reception For the compare register setup value and the serial operation setup refer to chapter 11 Serial Interface 0 Serial Transfer Clock Output VI 37 Chapter 6 8 bit Timers 6 9 Simple Pulse Width Measurement 6 9 1 Operation Timer measures the L duration of the pulse signal input from the external interrupt pin Pulse Width Measurement Operation by 8 bit Timer Timers 0 and 2 When the input signal of the external interrupt pin simple pulse width is L the binary counter of the timer counts up Pulse width L period can be measured by reading the count of timer 8 bit timers that have the simple pulse width measurement function are timers 0 and 2 Table 6 9 1 Simple Pulse Width Measurement Able Pins Timers 0 and 2 Timer 0 Timer 2 Simple pulse width External interrupt 0 External interrupt 2 measurement enable pin P20 IRQO P22 IRQ2 mCount
153. to read out the correct counting value during timer operation Chapter 7 9 1 Operation p VII 38 VII 14 Operation 7 16 bit Timers Clock TMnBC TMnOC1 TMnPR1H TMnPR1L Data e12a is loaded to OC1 as PR1rewrting e1b5 gt 8e2a and loading to OC1 are operated at the same time When a data is written to 16 bit timer preset register TM7PR1 TM7PR2 it is recognized as a 8 bit unit data inside LSI even if it is a 16 bit access MOVW instruction After lower 8 bits of preset register is written if data loading from preset register to compare register is started before the upper 8 bits is written data which is not rewritten is loaded to the upper 8 bits and rewritten data is loaded to the lower 8 bits Therefore writing data to the preset register TM7PR1 TM7PR2 need to be completed before data loading from the preset register to the compare register is started Shown below is timing chart of TM7PR1 and TM7OC1 data rewriting and the data loading When data is written to TM7PR2 wrong data could be loaded due to the same problem TM7BC and TM7OC1 compare match and load timing of TM7PR1 e1b0 e1b1 152 e1b3 e1b4 165 0000 0001 0002 0003 0004 0005 Data loading from PR1 to is started Data loading from PR2 to OC2 is started e1b5 12 at the same time el 8e
154. to select divided by 8 at source clock And the SCOMST flag should be always set to 1 to select colck master Set the SCOSBOS SCOSBIS flag of the SCOMD register to 1 to set the TXD pin to serial data output and the RXD pin to serial data input Set the SCORIE flag of the SCORICR register to 1 and set the SCOTIE flag ot the SCOTICR register to 1 to enable the interrupt request If any interrupt request flag is already set clear them t Chapter 3 3 1 4 Interrupt Flag Setup Operation XI 45 Chapter11 Serial Interface 0 Setup Procedure Description 14 Setthe baud rate timer 14 Set the baud rate timer by the TM3MD register the TM3OC register Set the TM3EN flag to 1 to start timer 3 Chapter 6 8 bit Timer 15 Start serial communication 15 The transmission is started by setting the The transmission data gt transmission data to the serial transmission data x 3F95 buffer TXBUFO When the transmission is The received data input to RXD finished the serial 0 transmission interrupt 5 is generated After the serial data is input from the RXD pin and the start condition is recognized the received data is stored When the reception is finished the received data is stored to the serial received data buffer RXBUFO and the serial 0 reception data buffer interrupt SCORICR is generated Note 5 to 6 7 to 9 10 to 12 can b
155. to set the P51 pin as a special function pin and set the P5DIR1 flag of the port 5 direction control register to 1 to set output mode Hd In the initial state of the PWM output it is changed to H output from L output at the timing that the PWM operation is selected with the TMPWM flag of the TM7MD register ki V Set as the set value of TM7OC2 lt the set value of TM7OC1 If it is set as the set value of 7 2 gt the set value of TM7OC1 the IGBT output is H fixed output 16 bit High Precision PWM Output V 35 Chapter 7 16 bit Timers 7 8 16 bit Timer Synchronous Output 7 8 1 Operation If the binary counter of the timer reaches the set value of the compare register port 6 outputs the port 6 output latched data at the next count clock 16 bit Timer Synchronous Output Operation Timer 7 Port 6 outputs the port 6 output latched data at a TM7OC1 compare register reaches a binary counter or at an interrupt request generation by the full count overflow Only port 6 can be used this operation and each bit can be set individually ilCount Timing of Synchronous Output Timer 7 TM7EN flag Compare register 1 Port 6 output latch data Binary counter Interrupt request flag Port 6 synchronous output data Figure 7 8 1 Count Timing of Synchronous Output Timer 7 Output pin outputs the port 6 output latch data at an interrupt request generation by
156. to stop the timer 2 counting Set the SYOEVS1 0 flag of the pin control register FLOAT to 10 to set the synchronous output event to timer 2 interrupt Set the port 6 synchronous output control register P6SYO to x FF to set the synchronous output pin P67 to P60 are synchronous output pin Set the port 6 direction control register P6DIR to x FF to set port 6 to output mode Add pull up resistor if necessary Chapter 4 I O Ports Set the TM2PWM flag and TM2MOD flag of the TM2MD register to 0 to select the normal timer operation Select the prescaler output for clock source by TM2CK2 0 flag of the TM2MD register Select fs 4 for the prescaler output by TM2BAS flag TM2PSC1 0 of the timer 2 prescaler selection register CK2MD Also set the PSCEN flag of the prescaler control register PSCMD to 1 to enable the prescaler counting VI 33 Synchronous Output Chapter 6 8 bit Timers Setup Procedure Description 7 Set the synchronous output event 7 Set the synchronous output generation cycle generation cycle to the timer 2 compare register 2 2 x 3F5A x 63 The setting value is set to 100 1 99 x 63 because 1 MHz is divided by 10 kHz At that time the timer 2 binary counter TM2BO is initialized to x 00 8 Start the timer operation 8 Setthe TM2EN flag of the TM2MD register to TM2MD x 3F5C 1 to start timer 2 bp3 2 1
157. to the Vica pin and connect capacity to and Vice pins to be connected to Vss Connect capacity between C1 and C2 pin as well 3 times of Vica reference voltage is applied to the pin and 2 times of Vica reference voltage is applied to Vice pin Chapter 13 13 3 3 Voltage supply when using internal voltage booster circuit 2 3 times 1 2 times boosting This is applied when LCD panel is used with 1 3 bias To operate 2 3 or 1 2 times voltage boost input reference voltage to the Vic and connect capacity and pins to be connected to Vss Connect capacity between C1 and C2 pin as well 2 3 times of Vice reference voltage is applied to the Vici and 1 2 times of Vice reference voltage is applied to Vica pin Chapter 13 13 3 3 Voltage supply when using internal voltage booster circuit B2 times boosting This is applied when LCD panel is used with 1 2 bias To operate 2 times voltage boost input reference voltage to short circuited Vice and Vica pins Connect capacity between Vici and Vss pins Connect capacity between C1 and C2 pin as well 2 times of Vice reference voltage is applied to Vici pin Chapter 13 13 3 3 Voltage supply when using internal voltage booster circuit When voltage booster circuit is active internal voltage divider resistors cannot be used For 2 times 3 times voltage boosting input reference voltage Vics to voltage booster circuit in
158. transfer is started as SCOTEMP is cleared to 0 Overrun Error and Error Monitor Flag If after reception complete the next data has been already received before reading out of the data of the received data buffer RXBUFO overrun error is generated and the SCOORE flag of the SCOMD3 register is set to 1 And at the same time the error monitor flag SCORE is set to indicate that error is occurred on reception The SCOORE flag holds the status unless the data of RXBUFO is read out SCOERE is cleared as SCOORE flag is cleared These error flags have no effect on communication operation mReception BUSY Flag When any data is set to TXBUFO or when the SCOSBIS flag of the SCOMD1 register is 1 as start condition is input the SCORBSY flag of the SCOMDS register is set to 1 And on the generation of the communication complete interrupt SCOTIRQ the flag is cleared to 0 And during continuous commu nication the SCORBSY flag is always set If the transmission buffer empty flag SCOTEMP is cleared to 0 as the communication complete interrupt SCOTIRQ is generated SCORBSY is cleared to 0 If the SCOSBIS flag is set to 0 during communication the SCORBSY flag is cleared to 0 Transmission BUSY When any data is set to TXBUFO or when the SCOSBOS flag of the SCOMD1 register is 1 as start condition is input the SCOTBSY flag of the SC0MD3 register is set to 1 And on the generation of the communication complete interrupt SCOTIRQ the
159. wait time control register DLYCTR is set to select the oscillation stabilization wait time At releasing from reset oscilla tion stabilization wait time is fixed The timer that counts oscillation stabilization wait time is also used as a watchdog timer That is used as a runaway detective timer at anytime except at releasing from reset and at recovering from STOP mode Watchdog timer is initiated at reset and at STOP mode and starts counting from the initialize value x 0000 when system clock fs is as clock source After oscillation stabilization wait time is finished it Chapter 9 Watchdog timer continues counting as a watchdog timer t mBlock Diagram of Oscillation Stabilization Wait Time Function watchdog timer STOP NRST E writeWDCTR I HALT R 0d j 1 2 1 214 15 1 215 1 220 sysclk DLYCTR m internal reset release 16 214 fs 210__ 15 28 fs 22 MUX G fs 220 fs 218 5 2168 p MUX WDIRQ Figure 2 6 3 Block Diagram of Osillation Stabilization Wait Time Function watchdog timer Reset H 27 Chapter 2 Basic CPU Oscillation Stabilization Wait Time Control Register 7 6 5 4 3 2 DLYCTR BUZOE BUZS2 BUZS1 BUZSO DLYS1 DLYSO Atreset 000001
160. 1 Output mode Output mode Input mode VO PODIR PODIRO PODIR PODIR2 Added Not added Added Not added Added Not added Pull up Pull down 2 POPLU POPLU0 POPLU POPLU2 Pins Setup with channels at reception Table 11 3 7 shows the setup for synchronous serial interface pin with 3 channels SBO7 pin SBI pin SBT pin Table 11 3 7 Setup for Synchronous Serial Interface Pin with 3 channels at reception Data output pin Data input pin Clock VO pin Setup item SBT pin SBO pin SBI pin Internal clock External clock Port pin P01 P02 SBI SBO independent SBI SBO SCOMD1 SCOIOM Port Serial data input Serial clock VO Serial clock VO Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Push pull Push pull Style _ _ Nch open drain Nch open drain SC0ODC SC0ODC1 Input mode Output mode Input mode VO PODIR PODIR1 PODIR PODIR2 Added Not added Added Not added Pull up Pull down POPLU POPLU2 XI 24 Operation Chapter11 Serial Interface 0 gmPins Setup with channels at transmission reception Table 11 3 8 shows the setup for synchronous serial interface pin with 3 channels SBO SBI SBT pin at transmission reception Table 11 3 8 Setup for Synchronous Serial Interface Pin with 3 channels at transmission reception Data output pin Data input p
161. 1 1 2 1 4 1 16 of the external clock Hardware organization Compare register with double buffer 2 sets Input capture register 1 set Timer interrupt 2 vectors Timer functions Square wave output Timer pulse output Event count High precision PWM output Cycle Duty can be changed constantly Timer synchronous output Input capture function Both edges can be operated Square wave output and PWM output can be output to large current driver port P51 TM7O Timer 8 16 bit timer for general use Clock source fosc fosc 2 fosc 4 fosc 16 fs 16 2 fs 4 fs 16 1 1 1 2 1 4 1 16 of the external clock Hardware organization Compare register with double buffer 1 set Input capture register 1 set Timer interrupt 1 vector Timer functions Square wave output Timer pulse output Event count Standard PWM output Duty can be changed constantly Input capture function Both edges can be operated 32 bit cascade connection connected to timer 7 Square wave output Input capture function Square wave output and PWM output can be output to large current driver port P53 Hardware Functions 1 5 Chapter 1 Overview Watchdog timer Time out period can be selected from fs 216 15 278 fs 2 On detection of errors hardware reset is done by force in LSI Synchronous output function Timer synchronous output Interrupt synchronous output Port 6 outputs the latched data on the event timing of t
162. 1 14 2 3 101 64 XIV 12 14 2 4 PRB DMYIOICS2 M eie tpi tet e ben XIV 13 Instruction Set eee sei ri e o EGO ere e ee tr E ORE XIV 14 Instruction Map ert eie eene m mr ei de XIV 20 Special Function Registers List essent XIV 22 1X contents Chapter 1 Overview Chapter 1 Overview 1 1 Overview 1 1 1 Overview The MN101C series of 8 bit single chip microcomputers incorporate multiple types of peripheral func tions This chip series is well suited for camera VCR MD TV CD LD printer telephone home automa tion pager air conditioner PPC remote control fax machine musical instrument Health care and other applications This LSI brings to embedded microcomputer applications flexible optimized hardware configurations and a simple efficient instruction set This LSI has an internal 16 KB of ROM and 1 5 KB of RAM Peripheral functions include 4 external interrupts 13 internal interrupts including NMI 9 timer counters 2 sets of serial interfaces A D converter watchdog timer synchronous output function buzzer output and remote control output The configuration of this microcomputer is well suited for application as a system controller in a camera a sohygmomanometer CD player or MD With two oscillation system max 20 MHz 32 kHz contained on the chip the system clock can be switched to high frequency input high speed mode
163. 1 0 TM8MD2 T8ICEDG RESERVED TM8BCR TM8PWMITM8IRS1 T8ICENI T8ICT1 At reset 00000000 T8ICT1 T8ICTO Capture trigger selection 0 0 IRQO External interrupt 0 1 IRQ1 External interrupt 1 1 0 IRQ2 External interrupt 2 1 Unavailable 8 Input capture operation enable flag 0 Disable capture operation 1 Enable capture operation Timer 8 interrupt TM8IRS1 source selection 0 Counter clear 1 Match of BC and OC1 Timer output waveform TM8PWM selection 0 Timer output 1 PWM output Timer 8 counter TM8BCR clear source selection 0 Full count OVF 1 Match of BC and OC1 RESERVED Set always 0 T8ICEDG Capture trigger edge selection 0 Both edges selection 1 Specified edge selection Figure 7 2 24 Timer 8 Mode Register 2 TM8MD2 x 03F89 R W Control Registers VII 13 7 16 bit Timers 7 3 Operation 7 3 1 Operation The timer operation can constantly generate interrupts m16 bit Timer Operation Timer 7 Timer 8 The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register 1 TMnOC1 in advance When the binary counter TMnBC reaches the set value of the compare register 1 an interrupt is generated at the next count clock There are 2 sources to be selected to clear the binary counter the TMnOC1 compare match and the full count overflow After the binary counter is cleared the counting up is restarted from x 0000 Tabl
164. 1 0 TMnOC1 compare match full count of TMnBC x 2 0 0 full count overflow full count of TMnBC x 2 24 16 bit Timer Pulse Output 7 16 bit Timers mCount Timing of Timer Pulse Output by Compare Match Timer 7 Timer 8 TMnEN flag Compare register 1 Jerem eee e counter Interrupt request flag TMnIO output Figure 7 5 1 Count Timing of Timer Pulse Output Timer 7 Timer 8 7 TMnlO output pin outputs 2 x cycle compared with the value of Compare Register 1 signal If the binary counter reaches the compare value or full count overflow is occurred the binary counter is cleared to x 0000 and the TMnIO output timer output is inverted The inversion of the timer output is changed at the count clock at the rising edge These form the correct output signal and internal waveform In the initial state after releasing reset the timer pulse output is reset and low output is fixed Therefore release the reset of the timer pulse output by setting the TMnCL flag of the TMnMD 1 register to 0 16 bit Timer Pulse Output VII 25 Chapter 7 16 bit Timers 7 5 2 Setup Example mTimer Pulse Output Setup Example Timer 7 Timer 8 output pin outputs a 50 kHz pulse using timer 7 For this select fosc as the clock source and set 1 2 cycle 100 kHz to the timer 7 compare register at fosc 20 MHz An example setup procedure with a description of each step is shown below
165. 1 24 of the low frequency oscillation clock 10 1 1 Block Diagram mBuzzer Block Diagram fosc MUX 1 2 to 1 2 4 fx 05 214 fosc 213 05 212 fosc 2 DLYCTR osgo MX BUZZER fosc 29 r apt Bese 0 fx 24 na e fx 23 DLYSO _DLYS1 80780 N BUZS1 80252 BUZOE 7 e Figure 10 1 1 Block Diagram Buzzer xX 2 Overview Chapter 10 Buzzer 10 2 Control Register Oscillation Stabilization Wait Time Control Register 7 6 5 4 3 2 1 0 DLYCTR 7 0752 02751 BUZSO DLYS1 DLYSO At reset 000001 Oscillation stabilization wait period selection DLYS1 DLYSO 4 0 fs 214 1 fs 210 1 0 15 26 1 15 22 Note After reset is released the oscillation stabilization wait period is fixed at fs 2 Buzzer output frequency BUZS2 BUZS1 BUZSO selection 0 fosc 214 1 fosc 213 0 0 fosc 21 1 fosc 2 3 0 fosc 210 j 1 fosc 29 0 fx 24 1 1 fx 23 BUZOE output selection 0 06 port output 06 buzzer output Figure 10 2 1 Oscillation Stabilization Wait Time Control Register DLYCTR x 03F03 R W Control Register X 3 Chapter 10 Buzzer 10 3 Operation 10 3 1 mBuzzer Buzzer outputs the square wave having freq
166. 1 4 duty 38 Hz 31Hz 15Hz 8Hz 0110 01 1 3 duty 51 Hz 41 Hz 20 Hz 10Hz OSC1 27 10 1 2 153 Hz 76Hz 12282 Hz 81HZ 3112 1562 11 static 153 Hz 122 Hz 61 Hz 31 Hz 00 1 4 duty 19 Hz 15 Hz 8 Hz 4 Hz 0111 01 1 3 duty 25 2 20 Hz 10 Hz 5 Hz OSC1 218 10 4 2 duty 76 2 2 3182 1 15Hz 11 static 76 2 61 2 31 Hz 15 Hz 00 1 4 duty 128 Hz 1x00 01 1 3 duty 171 Hz 25 10 1 2 duty 512 Hz 556 Hz 11 static 512 Hz 00 1 4 64 2 1 01 01 1 3 85 Hz 1 27 10 1 2 256 Hz Fae Hz 11 static 256 Hz 00 1 4 32 2 1 10 01 1 3 43 Hz 28 10 1 2 duty 128 Hz 64 Hz 11 static 128 Hz 00 1 4 duty 16 Hz 1x11 01 1 3 duty 21 Hz X1 29 10 1 2 duty 64 Hz 32Hz 11 static 64 Hz 20 Operation Chapter 13 13 3 5 Setup Example of the LCD Driver Circuit mSetup example of the LCD driver circuit using internal voltage booster circuit An example of setup procedure to display 23 1 4 duty 1 3 bias with both segment signals SEGO to SEG3 and common signals COMO to using internal voltage booster circuit is shown below Refer to XIII 18 fig 13 3 6 for the LCD power supply connection Refer to 13 4 LCD display for connec tion of LCD panel Setup Procedure Description Start the voltage booster circuit operation LCDMD2 X 3FDA bpO UPEN 1 0 Setup
167. 1 Fax 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Ltd PSI SZ 7A 107 International Bussiness amp Exhibition Centre Futian Free Trade Zone Shenzhen 518048 CHINA Tel 86 755 8359 8500 Fax 86 755 8359 8516 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai HONG KONG Tel 852 2529 7322 Fax 852 2865 3697 e Taiwan Sales Office Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 TAIWAN Tel 886 2 2757 1900 886 2 2757 1906 Kaohsiung Office 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 TAIWAN Tel 886 7 346 3815 886 7 236 8362 e Korea Sales Office Panasonic Industrial Korea Co Ltd PIKL Kukje Center Bldg 11th Fl 191 Hangangro 2ga Youngsan ku Seoul 140 702 KOREA Tel 82 2 795 9600 Fax 82 2 795 1542 050702 Printed in JAPAN
168. 1 KEY P60 KEY III 41 Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Interrupt Selection Selection Selection Selection selection Selection Selection Selection P5OMD3 P5OMD2 P5OMD1 P5OMD0 X 3F3F P5OMD Port VO Port I O Port Port IV 23 Timer 8 Timer 2 Timer 7 Timer 0 Output Selection Output Selection Output Selection Output Selection Special Function Registers List XIV 23 Chapter 14 Appendices Bit Symbol Initial Value Description Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POPLU6 POPLU2 POPLU1 POPLUO X 3F40 POPLU Port 0 Pull up Resistor ON OFF Control 7 P1PLU5 P1PLUS P1PLU2 P1PLU1 P1PLUO X 3F41 P1PLU Port 1 Pull up Resistor ON OFF Control IV 11 P2PLU2 P2PLU1 P2PLU0 X 3F42 P2PLU Port 2 Pull up Resistor ON OFF Control 15 P3PLU3 P3PLU2 P3PLU1 P3PLU0 X 3F43 P3PLU Port 3 Pull up Resistor ON OFF Control IV 18 P5PLU3 P5PLU2 P5PLU1 P5PLUO X 3F45 PSPLU Port 5 Pull up Resistor ON OFF Control 22 P6PLUD7 P6PLUD6 P6PLUD5 P6PLUD4 P6PLUD3 P6PLUD2 P6PLUDO X 3F46 P6PLUD Port 6 Pull up pull down Resistor ON OFF Control 26
169. 1 register can select if the serial data is input to SBI pin or SBO pin When data input from SBO pin is selected to set the 2 lines type the PODIRO flag of the PODIR register controls direction of SBO pin to switch transmission reception At this time SBI pin can be used as a general port too 1 The transfer speed should up to 2 5 MHz If the transfer clock is over 2 5 MHz the transmission data not be sent correctly At reception if SCOIOM of the SC0MD1 register is set to 1 and serial data input from SBO is selected SBI pin can be used as a general port 16 Operation Chapter11 Serial Interface 0 mReception Buffer Empty Flag When SCOTIRQ is generated data is automatically stored to RXBUFO from the internal shift register If data is stored to the shift register RXBUF0 the reception buffer empty flag SCOREMP of the SC0MD3 register is set to 1 This indicates that the received data is going to read out SCOREMP is cleared to 0 by reading out the data of RXBUFO Transmission Buffer Empty If any data is set to TXBUFO again during communication after setting data to TXBUFO and before the communication complete interrupt SCOTIRQ is generated the transmission buffer empty flag SCOTEMP of the SCOMD3 register is set to 1 This indicates that the next transmission data is going to be loaded Data is loaded to the inside shift register from TXBUFO by generation of SCOTIRQ and the next
170. 2 1 2 CPU Control Registers This LSI locates the peripheral circuit registers in memory space x 03F00 to x 03FFF with memory mapped CPU control registers are also located in this memory space Table 2 1 2 CPU Control Registers Address Registers pyw Function X 3F00 CPUM R W CPU mode control register X 3F01 MEMCTR R W Memory control register X 3F0A Reserved X 3F0B Reserved X 3F0D Reserved X 3FE0 Reserved for debugger X 3FE1 NMICR R W Non maskable interrupt control register E Chapter 3 X 3FE2 to xxxICR R W Mascable interrupt control register t Chapter 3 X 3FFE X 3FFF Reserved For reading out interrupt vector data in interrupt process Part of the register is only readable 4 Overview Chapter 2 Basic CPU 2 1 3 Instruction Execution Controller The instruction execution controller consists of four blocks memory instruction queue instruction regis ters and instruction decoder Instructions are fetched in 1 byte units and temporarily stored in the 2 byte instruction queue Transfer is made in 1 byte or half byte units from the instruction queue to the instruction register to be decoded by the instruction decoder 7 0 eee Memory 1 p 5 0 1 byte or a half byte Instruction queue Instruction register Hala asi Instruction decoder h 4 Instruction decoding
171. 2 768 kHz square wave of VDD and Vss amplitudes is input to the XI pin The supply current during STOP mode 1006 is measured under the following conditions After the oscillation is set to STOP mode the MMOD pin is at Vss level the input pins are at VDD level and the 5 1 and XI pins are unconnected Electrical Characteristics I 21 Chapter 1 Overview Ta 40 C to 85 2 0 V to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 1 MMOD 8 Input high voltage 1 0 8 9 high voltage 2 4 5 V to 5 5 V 0 7 Vpp 10 Input low voltage 1 0 0 2 Voo V 11 Input low voltage 2 4 5 V to 5 5 V 0 0 3 12 Input leakage current la ViN 0 V to t 10 uA Input 2 20 and P22 Schmitt trigger input 13 Input high voltage 0 8 14 Input low voltage 0 0 2 V 15 Input leakage current ILk3 Vin 0 V to 10 E uA 16 Input current 1 Pull ease ON 30 100 300 Input pin 3 to 1 P21 Schmitt trigger input 17 Input high voltage 0 8 18 low voltage Via 0 0 2 V 19 leakage current ViN 0 V 10 10 A Vpp 5 0 V Vin 1 5 V 20 Input current 1 Pul up resistor 30 100 300 Input pin 3 to 2 P21 When used as ACZ
172. 200 00 ns 477 33 122 07 us 0 unusable unusable unusable 400 00ns 244 14 us unusable 99 65 16 unusable 0 5 8 800 00 1 91 us 488 28 Us 1 unusable 1 15 26 us 15 26 us 15 26 us For the system clock fs refer to Chapter 2 2 5 Clock Switching BA D Converter Sampling Time Ts Setup The sampling time of A D converter is set with the ANSH1 to 0 flag of the ANCTR0 register The sam pling time of A D converter depends on external circuit so set the right value by analog input impedance Table 12 3 3 Sampling Time of Conversion Conversion Time ANSH1 ANSH0 Sampling time conversion time 15 at TAD 800 ns at TAD 954 65 ns at TAD 1 91 us at TAD 15 26 us 0 TAD x2 9 60 us 11 46 us 22 92 US 183 12 us 1 TAD x 6 12 80 us 15 27 us 30 56 Us 244 16 us i 0 TAD x 18 22 40 us 26 73 us 53 48 us 427 28 us 1 Reserved 10 Operation Chapter 12 Converter mBuilt in Ladder Resistor Control The ANLADE flag of the register is set to 1 to send a current to the ladder resistance for A D conversion When A D converter is stopped the ANLADE flag of the ANCTRO register is set to 0 to save the power consumption Table 12 3 4 A D Ladder Resistor Control ANLADE A D ladder resistance control 0 A D ladder resistance OFF A D conversion stopped 1 A D ladder resistance ON A D conversion operated
173. 3 1 6 BNS label if NF 1 PC 5 d7 label H PC 5 34 0010 0010 0101 lt 7 2 if NF20 PC 52PC BNS labe if NF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0101 dii 3 if NF20 PC 62PC BVC labe 0 5 7 5 3 4 0010 0010 0110 d7 2 1 5 BVC label if VF 0 PC 6 d11 label H gt PC 6 3 4 0010 0011 0110 dii if VF21 PC 62PC BVS label if VF21 PC 5 d7 label H2PC 5 3 4 0010 0010 0111 d7 H 2 if VF 0 PC 53PC BVS label if VF 1 PC 6 d11 label H PC 6 3 4 0010 0011 0111 dii 3 0 6 BRA label PC 3 d4 label H PG 3 1110 111 lt d4 gt label PC 4 d7 label H gt PC 4 1000 1001 d7 72 BRA label PC 5 d11 label H gt PC 5 1001 1001 lt d11 3 CBEQ CBEQ imm8 Dm label if Dm imm8 PC 6 d7 label H3PC e o 3 4 1100 10Dm 8 gt lt d7 2 8 6 CBEQ imm8 Dm label 8 8 011 1 e e 8 4 5 0010 1100 10Dm 48 gt dii 3 if Dm imm8 PC 8 gt PC CBEQ imm8 abs8 abel if mem8 abs8 imm8 PC 9 07 label H gt PC0 e e e 9 67 0010 1101 1100 abs 8 lt 8 gt d 2 if mem8 abs8 zimm8 PC 92PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8
174. 4 duty 1 3 duty 1 2 duty o Static LCREN Internal voltage divider resistor connection No connection Connection LCD driver circuit start Stop Start Figure 13 2 1 Mode Control Register1 LCDMD1 X 3FD9 R W Control Registers 7 Chapter 13 LCD Functions 13 2 3 Mode Control Register2 LCDMD2 The LCD mode control register 2 LCDMD2 is a 6 bit register that controls switching of internal booster circuit operation ON OFF and of Port I O P30 to P33 and common output The address assigned to this register is x 3FDA The value of the LCDMD 2 register is initialized at reset 7 6 5 4 3 2 1 0 LCDMD2 COMSL3 COMSL2 COMSL1 COMSLO UPCK at reset 00000000 Voltage booster enable disable 0 Stop 1 Operate Voltage booster operation UPCK speed control 0 Normal speed 1 High speed Set always 0 COMSLO COMO Port 30 select 0 Port 30 1 COMO COMSL1 Port 31 select 0 Port 31 1 1 COMSL2 COM2 Port 32 select 0 Port 32 1 COM2 COMSL3 Port 33 select 0 Port 33 1 COM3 Figure 13 2 2 Mode Control Register 2 LCDMD2 X 3FDA R W XIII 8 Control Registers Chapter 13 LCD Functions 13 2 4 Output Con
175. 5 6 6 6 7 6 8 6 10 OVerVI8W ehe eset ieee hashes iti cael DE De VI 2 6 1 1 FUNCHONS cals VI 2 6 1 2 Block Di graim iiec tte teet tete E VI 3 Control Registers n eO PERCD ERREUR VI 6 6 2 1 RESISTORS eere P ID URDU P EE VI 6 6 2 2 Programmable Timer Registers 0 VI 8 6 2 3 Timer Mode Registers VI 10 Ope ratiOnD kas ne op emet esiertetate eui VI 15 6 3 1 Op ration neri am depot Oei e De IRR rh VI 15 6 3 2 Setup Example eorom aep pee estre tiere eds VI 17 S bit Event Count need n e etek e ieee beret eet VI 19 6 4 1 Operation ien ubere rp E pee VI 19 6 4 2 Setup Example e ote t VI 21 S bit Timer Pulse Output eco ttr E tette VI 23 6 5 1 Operation e aiU SPON OP Eee ees VI 23 6 5 2 Setup E e s VI 24 8 bit PWM QUtpUt ss assesses nebenbei d i Ote eios VI 26 6 6 1 eto oder pendens VI 26 6 6 2 Setup Example eene pe ree ei e e entre VI 28 6 6 3 PWM Output With Additional Pulse eee VI 30 Synchronous eret pre PREPARES VI 32 6 7 1 indien fpe ett e ecd e een VI 32 6 7 2 Setup Example is aii eer eee e Sonepat adele VI 33 Serial Transfer Clock Output essere nennen nennen VI 35 6 8 1
176. 6 The generation cycle of the timer interrupt should be set in advance by the set value of the compare register TM6OC and the clock source selection When the binary counter 6 reaches the set value of the compare register an interrupt request is generated at the next count clock and the binary counter is cleared to restart count up from x 00 Table 8 3 1 shows selectable clock sources Table 8 3 1 Clock Source at Timer Operation Timer 6 Clock source One count time fosc 50 ns fx 30 5 us fs 100 ns fosc X 1 21 204 8 us fosc X 1 2 3 409 6 us fx X 1 27 125 ms fx X 1 27 250 ms fosc 20 2 fx 32 768 kHz fs fosc 2 10 MHz a Timer 6 does not stop the operation 8 bit Free running Timer VIII 7 Chapter 8 Time Base Timer 8 bit Free running Timer B8 bit Free running Timer as a 1 minute timer a 1 second timer Table 8 3 2 shows the clock source selection and the TM6OC register setup when a 8 bit free running timer is used as a 1 minute timer a 1 second timer Table 8 3 2 1 minute timer 1 second timer Timer 6 Setup ib Source TM6OC Register 1 min fx x 1 218 X EF fx x 1 272 1s fx x 1 273 fx 32 768 2 When the 1 minute timer 1 m is set on Table 8 3 2 the bp1 waveform frequency cycle of the TM6BC register is 1 Hz 1 s So that can be used for adjusting the seconds TM6B
177. 6 8 bit Timers Setup Procedure Description 10 Disable the lower timer interrupt TMOICR x 3FE9 bp1 TMOIE 0 Set the level of the upper timer interrupt TM1ICR x 3FEA bp7 6 TM1LV1 0 10 Enable the upper interrupt TM1ICR x 3FEA bp1 TM1IE 1 Start the upper timer operation TM1MD x 3F55 bp3 TM1EN 1 11 Start the lower timer operation TMOMD x 3F54 bp3 TMOEN 1 7 Set the TMOIE flag of the timer 0 interrupt control register TMOICR to 0 to disable the interrupt 8 Set the interrupt level by the TM1LV1 0 flag of the timer 1 interrupt control register TM1ICR If any interrupt request flag may be already set clear all request flags t Chapter 3 3 1 4 Interrupt Flag Setup 9 Setthe TM1IE flag of the TM1ICR register to 1 to enable the interrupt 10 Set the TM1EN flag of the TM1MD register to 1 to start timer 1 11 Set the TMOEN flag of the TMOMD register to 1 to start timer TM1BC TMOBC counts up from x 0000 as a 16 bit timer When TM1BC TMOBC reaches the set value of TM1OC TMOOC register the timer 1 interrupt request flag is set at the next count clock and the value of TM1BC TMOBC becomes x 0000 and restarts count up Use 16 bit access instruction to set the 1 register Start the upper timer operation before the lower timer operation VI 44 Cascade Co
178. 7 Operation Chapter 6 8 bit Timers Setup Procedure Description 7 Enable the interrupt 7 Set the TMOIE flag of the TMOICR register to TMOICR 3 9 1 to enable the interrupt bp1 TMOIE 1 8 Start the timer operation 8 Set the TMOEN flag of the TMOMD register to TMOMD x 3F54 1 to start the timer 0 bp3 1 starts to count up from x00 When the reaches the setting value of the register the timer 0 interrupt request flag is set at the next count clock then the value of the TM0BC becomes x 00 and restart to count up When the TMnEN flag of the TMnMD register is changed at the same time to other bit binary counter may start to count up by the switching operation When fx is selected as a count clock source and if binary counter value is read out during opeartion the read value may be uncertain To prevent this select synchronous fx as a count clock source To do so timer n counts up the binary counter with a signal that is sync with the system clock and you can always read out correct value from the binary counter But with synchronous fx return from STOP HALT modes is disabled 2 VI 18 Operation 6 4 6 4 1 Operation 8 bit Event Count Chapter 6 8 bit Timers Event count operation has 2 types TMnIO input and synchronous input according to the clock source selection W8 bit Event Cou
179. 7CK1 0 01 bp3 2 TM7PS1 0 10 6 Set the interrupt generation cycle TM7PR1 x 3F75 x 3F74 x FFFF TM8PR1 x 3F 85 x 3F84 x 86A0 1 Set the TM7EN flag of the timer 7 mode register TM7MD1 to 0 the TM8EN flag of the timer 8 mode register to 0 to stop timer 7 and timer 8 counting Set the TM7BCR flag of TM7MD2 register and TM8BCR flag of TM8MD2 register to 1 to se lect compare match as a clear source of the binary counter Set the TM7ICEN flag and the TM7PWM flag of the TM7MD2 register to 0 to select normal timer operation Set the TM8CAS flag of the TM8MD1 register to 1 to connect timer 7 and timer 8 in cascade connection Select fs as the clock source by the TM7CK1 0 flag of the TM7MD1 register Also select 1 4 dividing of fs as the count clock source by the TM7PS1 0 flag Set the timer 7 preset register 1 TM7PR1 and timer 8 preset register 1 TM8PHR1 to the interrupt generation cycle 100000 cycles 1 At that time the same values as the preset registers are loaded to the timer compare register TM7OC1 and timer 8 compare register 1 TM8OC1 and the binary counters are initialized to x 0000 46 Cascade Connection 7 16 bit Timers Setup Procedure Description Disable the lower timer interrupt TM7ICR x 3FF1 bp1 TM7IE 0 8 Setthe level of the upper timer interrupt TM8ICR x 3FF3 bp7 6 TM8LV1 0 10 9 Enable the
180. 8 B 8858 gt gt gt gt lt lt lt lt OnNr 2222 tite Figure 1 4 1 Block Diagram 1 5 1 5 1 51 2 8 Electrical Characteristics Chapter 1 Overview This LSI user s manual describes the standard specification Machine cycle system clock fs is describe based on the standard mode 1 2 of high oscillation at NORMAL mode or on the clock frequency 1 2 of low oscillation at SLOW mode Please ask our sales offices for its own product specifications CMOS integrated circuit Appliction General purpose CMOS 8 bit single chip microcontroller Absolute Maximum Ratings 2 3 Dee p pee Output pin voltage VO pin voltage ETT Peak output current Other than P5 lo2 peak All pins peak s Average output Other than P5 lo 2 avg current 1 All pins avg Power dissipation Operating ambient temperature Topr Storage temperature Tstg Applied to any 100 ms period 0 3 to VDD 0 3 0 3 to VDD 0 3 40 to 85 C 55 to 125 Connect at least one bypass capacitor of 0 1 uF or larger between the power supply pin and the ground for latch up prevention The absolute maximum ratings are the tolerance for the LSI to be operated properly Electrical Characteristics I 17 Chapter 1 Overview 1 5 2 Operating Conditions NORMAL mode fs fosc 2 SLOW mode fs fx 2 Ta 40 C to 85
181. 8008 0 9095 810005 5085005 AdNOOS 8150095 INM202S 2031098 1611005 005 LON100S m 3488008 001025 2095 31S09S 0 0 oawoos 0 1awoos Indino sayeosud nouo 4 yore 104002 250025 005 Jejunoo pes Te 71 081095 lt i rau 8 1 14055 x 4 0005 4 JOUS 0 14005 591095 4 gt nee uogejeuef ASSHODS Asna 1006 gt 5 yag F d 006 lt w 34 c 204 0185 ______ 144006 4 dois Wao 739095 lt 0 9095 49095 5195095 5_ 4 I 393095 Y 393028 X HA3090S 0 014025 o 3788005 Y Y u 7 5185005 uoneJeuo NE i rn US W lt X 00d 008S 00d 008S lt uonipuoo much uondeo H n n i ze aso 0 5085005 0142006 215095 em uoissiuusue1l Jayng es 910095 857 lt gt 85 IN dVMS eww peeu Serial Interface 0 Block Diagram Figure 11 1 1 XI 3 Overview Chapter 11 Serial Interface 0 11 2 Control Registers 11 2 1 Registers Table 11 2 1 shows registers to contr
182. 9992292 Figure 5 1 1 Prescaler Block Diagram PSCMD PSCEN __ __ ____ l J L C i Timer 0 Timer 1 Timer 2 Timer 3 Serial 0 Chapter 5 Prescaler 5 2 Control Registers 5 2 1 Registers List Table 5 2 1 shows registers control prescaler Table 5 2 1 Prescaler Control Registers Register Address R W Function Page PSCMD x 03F6F R W Prescaler control register V 6 CK0MD x 03F56 R W 0 prescaler selection register V 7 CK1MD x 03F57 R W 1 prescaler selection register V 7 CK2MD X 03F5E R W Timer 2 prescaler selection register V 8 CK3MD X 03F5F R W Timer prescaler selection register V 8 SCOCKS x 03F97 R W Serial 0 transfer clock selection register V 9 XI 11 R W Readable Writable Control Registers V 5 Chapter5 Prescaler 5 2 2 Control Registers There are three types of Prescaler control registers the register controls prescaler operation is the prescaler control register PSCMD and the register select prescaler output are the timer prescaler selection register CKnMD and the serial interface transfer clock selection register SCnCKS The prescaler control register controls prescaler count operation iPrescaler Control Register PSCMD PSCMD PSCEN At reset 0 PSCEN Prescaler 0 1 count control 0 Disable the count 1 Enable the co
183. ADE 1 3 Select the A D converter clock 1 Set the analog input pin set in 2 as the special function pin with the port A input mode register PAIMD Also set no pull up pull down resistance with the port A pull up pull down resistance control register PAPLUD Select the analog input pin from AN2 0 PA3 0 by the ANCHS3 0 flag of the A D converter control register 1 ANCTR1 Select the A D converter clock by the ANCK1 ANCKO flag of the A D converter control register 0 ANCTRO Set the sample and hold time by the ANSH1 ANSHO flag of the A D converter control register 0 ANCTRO Set the interrupt level by the ADLV1 0 flag of the A D conversion complete interrupt control register ADICR If any interrupt request flag is already set clear it 6 Chapter 3 3 1 4 Interrupt Flag Setting Enable the interrupt by setting the ADIE flag the ADICR register to 1 Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 send a current to the ladder resistance for the A D conversion 12 Operation Chapter 12 Converter Setup Procedure Description ANCTR2 2 7 ANST 1 9 Complete the A D conversion ANBUFO x 3FB3 ANBUF1 x 3FB4 8 Start the A D conversion operation 8 Set the ANST flag of the A D converter control register 2 ANCTR2 to 1 to start the A D conversion When the A D conversion is finished
184. C ea m ee ms o 71 Hz 1 s Figure 8 3 1 Waveform of TM6BC Register Timer 6 8 8 bit Free running Timer Chapter 8 Time Base Timer 8 bit Free running Timer ECount Timing of Timer Operation Timer 6 Binary counter counts up with the selected clock source as a count clock Count clock TM6CLRS flag Compare register Binary counter Interrupt request flag C E Figure 8 3 2 Count Timing of Timer Operation Timer 6 A When any data is written to the compare register as the TM6CLRS flag is 0 the binary counter is cleared to x 00 B Even if any data is written to the compare register as the TM6CLRS flag is 1 the binary counter is not changed C When the binary counter reaches the value of the compare register as the TM6CLRS flag is 1 aninterrupt request flag is set at the next count clock D When an interrupt request flag is set the binary counter is cleared to x 00 and restarts the counting E Even if the binary counter reaches the value of the compare register as the TM6CLRS flag is 0 nointerrupt request flag is set When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the fx input is selected as a clock source and the value of timer 6 binary coun
185. COCKS register selects a clock source from the special prescaler and timer output The special prescaler starts its operation after the PSCMD x 03F6F register selects prescaler operation The SCOMST flag of the SCOMD1 register can select the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock that has the same clock cycle or below to the external clock by the SCOCKS register That is happened because the interrupt flag SCOTIRQ is generated by the internal clock Here is the internal clock source that can be set by the SCOCKS register Also the SCOCKM flag of the SCOMD1 register can divide the internal clock by 8 Table 11 3 3 Synchronous Serial Interface Internal Clock Source Serial 0 fosc 2 fosc 4 fosc 16 Internal clock fosc 64 fs 2 16 4 3 output of the timer If other clock is selected normal transfer of serial interface data is not guaran 1 When timer output is selected serial interface transfer clock select fosc as clock source teed mData Input Pin Setup 3 channels type clock pin SBT pin data output pin SBO pin data input pin SBI pin or 2 channels type clock SBT data pin SBO pin can be selected as a communication mode SBI pin can be used for only serial data input SBO pin can select serial data input or output The SCOIOM flag of the SC0MD
186. COCMD flag of the SCOMD1 register to 0 to select synchronous serial 12 Set the SCOMST flag of the SCOMD1 register to 1 to select clock master inside clock Set the SCOCKM flag to 1 to select divide by 8 for source clock 13 Set the SCOSBOS SCOSBIS SCOSBTS flag of the SCOMD1 register to 1 to set SBO pin serial data output SBI pin serial data input and SBT pin serial clock I O Set the SCOIOM flag 0 to set serial data input from SBI pin 14 Set the interrupt level by the SCOTLV1 0 flag of the serial 0 transmission interrupt control register SCOTICR Set level 2 XI 28 Operation Chapter 11 Serial Interface 0 Setup Procedure Description 15 Enable the interrupt 15 Set the SCOTIE flag of the SCOTICR register to SCOTICR x 3FF6 1 to enable interrupts bp1 5 1 If any interrupt request SCOTIR of the SCOTICR register is already set clear SCOTIR before an interrupt is enabled 0 Chapter 3 3 1 4 Interrupt Flag Setup 16 Start serial transmission 16 Set the transmission data to the serial Transmission data TXBUFO x 3F95 transmission data buffer TXBUFO Then an Received data input to SBI pin internal clock is generated to start transmission reception After the transmission is finished serial0 transmission interrupt SCOTIRQ is generated Note Each procedure 5 to 8 9 to 11 and 11 to 13 can be set
187. Connect CNC of PX CN101 M to CNC of PRB MBB101 M and CND of PX CN101 M to CND of PRB MBB101 M When connecting the boards make sure that they are connected without tilt If you put pressure on one side of the board that may cause any damage to the pins Probe Switches XIV 11 Chapter 14 Appendices 14 2 3 PRB ADP101 64 M When connected to the target use this board with MBB board This board can be used with the following boards The product type is subject to change without prior notice The latest information should be confirmed on our web site PRB MBB101C52 M PRB MBB101C58 M Improper matching may cause any damage to the ICE Figure 1 Adapter Board Layout lt How to connect gt Connector board PX CN101 M MBB board PRB MBB101 M Make sure that the points marked would be put together Caution1 Adapter board PRB ADP101 64 M Caution1 Connect CNE of PRB MBB101 M to CNE of PRB ADP101 64 M and of PRB MBB101 M to of PRB ADP101 64 M When connecting the boards make sure that they are connected without tilt If you put pressure on one side of the board that may cause any damage to the pins XIV 12 Probe Switches Chapter 14 Appendices 14 2 4 PRB DMY101C52 M Dummy target boards differ depending upon the models This board can be used for only 101052 When unconnected to the target use this board with the PRB MBB101C52 M Improper matching
188. D Operation is available A Holding Display is available x LCD Operation is not available OFF the LCD and switch from segment output to port before transition to the CPU mode in which LCD operation is disabled 13 1 3 Maximum Pixels Table 13 1 3 shows the maximum pixels Table 13 1 3 Maximum Pixels Maximum Pixels 8 segment Segment x Common LCD Panel Segment Output Latch bits Static 24 24 x 1 COM0 bit0 bit4 1 2 48 24 x 2 to COM1 bit0 to bit4 to bit5 72 24 x 3 to COM2 bit0 to bit2 bit4 to bit6 96 24 x 4 12 figures COMO to COM3 bit0 to bit3 bit4 to bit7 Functions 3 Chapter 13 LCD Functions 13 1 4 Switching I O ports and LCD segment pins Switching of port output and segment output is controlled with the LCD output control register 1 2 LCCTR1 LCCTR2 Chapter 13 2 LCD Control Registers Switching of normal port and common pin is controlled with the LCD mode control register 2 LCCTR2 Chapter 13 2 LCD Control Registers Port 7 Port 8 Port 6 Port 3 SEG8 to 15 are switchable to I O ports in 2 bit unit SEGO to 7 is switchable to I O ports 2 bit unit SEG16 to 23 is switchable to I O ports in 1 bit unit to 3 is switchable to I O ports in 1 bit unit XIII 4 Functions LCD Functions Chapter 13 it Block Diagram
189. DLV1 ADLVO ADIE ADIR X 3FFA ADICR Specify Interrupt Level Interrupt Interrupt Ill 34 Enable Request Special Function Registers List XIV 29 Record of Changes MN101C527 LSI User s Manual Record of Changes Ver 3 3 to Ver 3 4 1 2 Definiti Details of Changes Page Section dh PreviousEdition Ver 3 3 New Edition Ver 3 4 Machine cycle at 2 divide of crystal oscillation High speed mode 1 0 us 2 MHz 2 0 V to 5 5 V 1 13 Line 8 9 Addition Low speed mode 62 5 us 32 kHz 2 0 V to 5 5 V 1 51 Minimum rating for EPROM vers is 2 3 V to 5 5 V capacitor is to be inserted between NRST and If a capacitor is to be inserted between NRST and VSS it VDD jit is recommended that a discharge diode be is recommended that a discharge diode be placed placed between NRST and VDD between NRST and VDD Unused Pins only for output Unused Pins output exclusive pins and LCD output pins 1 28 Unused pins only for output should be open pins output exclusive pins and LCD output 242 Key mark Set the always to L level System clock fs changes depending on the CPU operation mode It changes to fosc high frequency in 219 Addition NORMAL and HALTO modes and to fx low frequency in SLOW IDLE and HALT1 modes us Insert three nop instructions right after the instruction of cf 4 transition to HALT SLOW mo
190. ESERVED Set always 1 EXMEM Set always 0 IVBM Base address setting for interrupt vector table 0 Interrupt vector base x 04000 1 Interrupt vector base x 00100 Set number of wait cycles when Bus cycle at IOW1 to 0 accessing special register area 20 MHz oscillation 00 No wait cycles 100 ns 01 1 wait cycle 150 ns 10 2 wait cycles 200 ns 11 3 wait cycles 250 ns Figure 2 3 2 Memory Control Register MEMCTR x 3F01 R W The IOW1 IOWO0 wait settings affect accesses to the special registers located at the ad dresses x 3F00 x 3FFF After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles Wait setting of IOW is a function which CPU supports for special use for ex ample when special function register or I O is expanded to external For this LSI wait cycle setting is not always necessary Select no wait cycle for high performance system con struction II 16 Bus Interface 2 4 2 4 1 Outline Standby Function Chapter2 Basic CPU This LSI has two sets of system clock oscillator pins high and low frequency for two CPU operating modes NORMAL and SLOW each with two standby modes HALT and STOP Reset CPU
191. Functions Figure 13 3 2 shows examples of the LCD power supply connection Stabilization condenser C for LCD power supply is recommended to be C 0 1 uF Cv20 1 uF should be connected as Stabilization condenser Cv for VDD power supply a Static 101 527 Vici Vice2 Vics Vss C1 C2 o Input b 1 2 duty 1 2 bias MN101C527 VoD Vics Vss C1 C2 Input TIT 1 3 duty 1 3 bias 1 4 duty 1 3 bias 2 V 3 V MN101C527 Vice Vics Vss C1 C2 o Input 2 V reference voltage d 1 3 duty 1 3 bias 1 4 duty 1 3 bias Vpp VLcp MN101C527 Vics Vss C1 C2 O D Jim 0 Input Figure 13 3 2 LCD power supply connection when external divider resistor is used 16 Operation Chapter 13 LCD Functions 1 In figure 13 3 2 current always flows through the voltage divider resistors The following connection is used to cut the current flowing through these dividing resistors at VLci Vpp 101 527 Input Figure 13
192. I 6 TM7OC2H7 TM7OC2H6 7 2 5 7 2 4 TM7OC2H3 TM7OC2H2 7 2 1 TM7OC2H0 X 3F7B TM7OC2H Timer 7 Compare Register 2 Upper 8 Bit VII 6 TM7PR2L7 TM7PR2L6 TM7PR2L5 TM7PR2L4 TM7PR2L3 TM7PR2L2 TM7PR2L1 TM7PR2LO X 3F7C TM7PR2L Timer 7 Preset Register 2 Lower 8 Bit VII 7 TM7PR2H7 TM7PR2H6 TM7PR2H5 TM7PR2H4 TM7PR2H3 TM7PR2H2 TM7PR2H1 TM7PR2H0 X 3F7D TM7PR2H Timer 7 Preset Register 2 Upper 8 Bit VII 7 TM8BCL7 TM8BCL6 TM8BCL5 TM8BCL4 TM8BCL3 TM8BCL2 TM8BCLi TM8BCLO X 3F80 TM8BCL Timer 8 Binary Counter Lower 8 Bit VII 8 TM8BCH7 TM8BCH6 TM8BCH5 TM8BCH4 TM8BCH3 TM8BCH2 TM8BCH1 TM8BCHO X 3F81 TM8BCH Timer 8 Binary Counter Upper 8 Bit VII 8 TM8OC1L7 8 116 TM8OC1L5 TM8OC1L4 TM8OC1L3 80 112 TM8OC1L1 TM8OC1L0 X 3F82 TM8OC1L Timer 8 Compare Register 1 Lower 8 Bit VII 6 TM80C1H7 8 1 6 TM8OC1H5 TM8OC1H4 TM8OC1H3 TM8OC1H2 TM8OC1H1 TM80C1HO 83 TM8OC1H Timer 8 Compare Register 1 Upper 8 Bit VII 6 TM8PR1L7 TM8PR1L6 TM8PR1L5 TM8PR1L4 TM8PR1L3 TM8PRiL2 TM8PRiL1 TM8PR1LO X 3F84 TM8PR1L Timer 8 Preset Register 1 Lower 8 Bit VII 7 TM8PR1H7 TM8PR1H6 TM8PR1H5 TM8PR1H4 TM8PR1H3 TM8PR1H2 TM8PR1H1 TM8PR1H0 85 TM8PR1H Timer 8 Preset Register 1 Upper 8 Bit VII 7 XIV 26 Special Function Registers List Chapter 14 Appendices
193. II 20 13 3 5 Setup Example of the LCD Driver Circuit 24 4022222 XIII 21 Display s unun uu EE XIII 24 13 45 sunan na Sh Sua XIII 24 13 42 Setup Example XIII 26 13 453 AAU ete eere PEE DID as XIII 28 13 44 Setup Example 1 2 duty XIII 30 13 4 5 1 3 d ty eerte prre ees XIII 32 13 4 6 Setup Example 1 3 duty sse XIII 34 13 457 duty orien t en cepe XIII 36 13 4 8 Setup Example 1 4 XIII 38 14 Appendices 14 1 14 2 14 3 14 4 14 5 EPROM Versions 5 ie ett ertet rente eate set e XIV 2 SD ener te ee eee need teet XIV 2 14 1 2 Caution on Use isset eee et Re Ier RESTE Rede cunts XIV 3 14 1 3 Erasing Data in Windowed Package see XIV 4 14 1 4 Differences between Mask ROM Version and EPROM Version XIV 5 14 1 5 Writing to EPROM built in Microcontroller XIV 6 14 1 6 Cautions on Operation of ROM 04444012 XIV 8 14 1 7 Programming Adapter Connection 2 2 4 XIV 9 Probe vedi hae 10 14 2 1 101 52 XIV 10 4 2 2 PXCCN101 MOO ees XIV 1
194. II 6 Control Registers Chapter 12 Converter 12 2 3 Data Buffers A D Conversion Data Storage Buffer 0 ANBUFO The lower 2 bits results from A D conversion are stored to this register 7 6 5 4 3 2 1 0 Atreset X X ANBUFO ANBUFO7 ANBUFO6 Figure 12 2 4 A D Conversion Data Buffer 0 ANBUFO x 03FB3 A D Conversion Data Storage Buffer 1 ANBUF1 The upper 8 bits results from A D conversion are stored to this register 7 6 5 4 3 2 1 0 At reset X X X X X X X X ANBUF1 ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 Figure 12 2 5 A D Conversion Data Buffer 1 ANBUF1 x 03FB4 R Control Registers XII 7 Chapter 13 Converter 12 3 Operation is a description of A D converter circuit setup procedure 1 XIII 8 Set the analog pins Set the analog input pin set in 2 to special function pin by the port A input mode register PAIMD Setup of the port A input mode register should be done before analog voltage is put to pins Select the analog input pin Select the analog input pin from to ANO to by the ANCHS1 to ANCHSO flag of the A D converter control register 1 ANCTR1 Select the A D converter clock Select the A D converter clock by the ANCK1 ANCKO flag of the A D converter control register 0 ANCTRO Setup should be such a way that converter clo
195. Jaqunoo 119 91 dap 2 9 NI peau x n eX HLOOZWL 319 9 2 2171 1l FAS MdL pe y jeufis eq L HIHdZWL THe ZINE 491sI6 1 eseid 19 91 i HOUNL 01921 1 10 91 me qe amdeg eAnisog uogejedo ende l 39121 epeoseo 01 uono l p yow eyeq X uoneziuuouuou s p N indui OIZIALL 5 n 050 yoo g 1dnuejul ndino X coi out lt 0Oul 0 1Idq qW W1 Timer 7 Block Diagram Figure 7 1 1 VII 3 Overview 16 bit Timers Chapter 7 mTimer 8 Block Diagram 5 SYO SNL
196. LNG1 SCOLNGO X 3F90 SCOMDO Transmission Reception Data Reception Data Specify Start Synchronous Serial Transfer Bit Count XI 6 Reception Data Polarity Polarity First Bit Condition lect Edge Selection Change Change Transferred Selection Selection SCOIOM SCOSBTS SCOSBIS SCOSBOS SCOCKM SCOMST SCOCMD X 3F91 SCOMD1 Serial Data SBT Pin Serial SBO Pin Transfer Clock Clock Synchronous Serial XI 7 Input Function Function Dividedby Master Slave Duplex UART Selection Selection put Control Selection 8 Selection Selection Selection SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE SCOBRKF SCOBRKE X 3F92 SCOMD2 Specify Frame Mode Added Bit Specify Parity Break Status Break Status 8 Reception Transmit Enable Monitor Control SCOTBSY SCORBSY SCOTEMP SCOREMP SCOFEF SCOPEK SCOORE SCOERE X 3F93 SCOMD3 Serial Bus Serial Bus Transmission Reception Frame Parity Overrun Error Monitor XI 9 Stat Stat Buffer Buffer Error Error Error FI aus aus Empty flag Empty flag Detection Detection Detection 89 RXBUFO7 RXBUFO6 RXBUFO5 RXBUFO4 RXBUFO3 RXBUFO2 RXBUFO1 RXBUF00 X 3F94 RXBUF0 Serial Interface 0 Reception Buffer XI 5 TXBUFO7 TXBUFO6 05 TXBUFO4 TXBUFO3 TXBUFO2 TXBUFO1 TXBUF00 X 3F95 TXBUF0 Serial Interface 0 Transmission Buffer XI 5 SCOODC1 SCOODCO X 3F96 SCOODC P02 N ch P00 N ch 10 Open Drain Open Drain Control Control SCOPSC2 SCOPSC1 5 0 5 0 7 9 X 3F97 SCOCKS
197. M1 SCOFMO flags to 0 0 Cautions about full duplex UART communication using OFF the LCD and switch from segment output to port Key mark Addition before transition to the CPU mode in which LCD operation is disabled Figure 13 3 1 LCD Power Section Block Diagram Figure 13 3 1 LCD Power Section Block Diagram 3 times boost 3 times boost Level shifter Level shifter Figure lt 13 13 13 3 1 Change pacc a LCDVss J ODV 3 Chapter Deletion Description about MN101CP52AHT 14 101 52 Table Oscillation characteristics 5 Addition Noise characteristics 14 1 1 Operating tempreture 14 8 Addition The internal ROM space of this LSI starts from x4000 Change Instruction Set Ver 3 1 Instruction Set Ver 3 2 When timer output is selected as serial interface transfer clock select fosc as a clock source of the timer If other clock is selected normal transfer of serial interface data is not guaranteed Cautions about write timing to16 bit timer preset register 11 47 1 13 4 1 101 527 LSI User s Manual Record of Changes 3 2 to 3 3 Definiti Details of Changes Page Section bn PreviousEdition Ver 3 2 New Edition Ver 3 3 All The value of internal RAM is uncertain when power is applied to it It needs to be initialized before it is used Description of t
198. M2 COM1 COMO l address bit6 bit5 bit4 bit3 bit2 bit1 bit0 X 2E00 5 52 SEG Pee SEG ORS ___ __ __ 4 1 1 SEG 2 85 X 2E02 111 SEG5P82 1 __ 5 2 X 2E03 2 22 45 SEG P80 X SEG 6 P81 X2E04 SRS SEG 9S P76 i SEG 8 P77 2 05 __ __ __ SEGIIP74 __ __ __ ___ 5 10 75 X2E06 11 1 __ 5 13 72 1 1 1 SEGI2 P73 __________________ 1570 SEG14 P71 X 2E08 _ Se c SEGIT PSO SEG16 P67 X2E09 11 1 __ 5 19 64 __ __ ___ 18 65 X2EON __ __ 21 62 1 1 ___ SEG20 P63 XeEOB 17 1 31 9EGeXPe0 ___ ___ __ SEG22 Pel at static at static lt at 1 2 duty at 1 2 duty at 1 3 duty S gt at 1 3 duty at 1 4 duty E x at 1 4 duty gt Figure 13 2 5 Matching of the Segment Output Latch and the Segment Common Pins ControlRegisters XIII 11 Chapter 13 LCD Functions 13 3 Operation 13 3 1 Circuit Operation for LCD drive The LCD driver is capable of static display and dynamic display 1 2 duty 1 2 bias 1 3 duty 1 3bias 1 4 duty 1 3 bias through the segment output pins SEG0 to SEG23 and the common output pins COMO to Circuit Operation for LCD drive The LCD driver circuit generates the timing siginals which are necessary for controling 1 2 duty 1 3 duty 1 4 duty and stati
199. MOCK1 Atreset 000000 TMOCK2 TMOCK1 0 0 Clock source selection fosc tmOpsc prescaler output fx Synchronous fx TMOIO input Synchronous TMOIO input O 0 count control 0 Halt the count 1 Operate the count TMOPWM Timer 0 operation mode selection 0 Normal timer operation 1 PWM operation TMOMOD Pulse width measurement control 0 Normal timer operation 1 Measure the pulse width of P20 IRQ0 Figure 6 2 9 Timer 0 Mode Register TMOMD x 03F54 R W VI 10 Control Registers Chapter 6 8 bit Timers Timer 1 Mode Register TM1MD 7 6 5 4 3 2 1 0 TM1MD TM1CK2 TM1CK1 Atreset 00000 TM1CK2 TM1CK1 TM1CKO Clock source selection 0 fosc 0 1 tm1psc Prescaler output 0 fx 0 1 1 Synchronous fx 1 0 TM1IO input 1 Synchronous TM1IO input TM1EN Timer 1 count control 0 Halt the count 1 Operate the count TM1CAS Timer 1 operation mode selection 0 Normal timer operation 1 Cascade connection Figure 6 2 10 Timer 1 Mode Register TM1MD x 03F55 R W Control Registers 11 Chapter 6 8 bit Timers Timer 2 Mode Register TM2MD 7 6 5 3 2 1 0
200. Maskable Interrupt Control Register NMICR address x 3FE1 The non maskable interrupt control register NMICR is stored the non maskable interrupt request When the non maskable interrupt request is generated the interrupt is accepted regardless of the inter rupt mask level IMn of PSW The hardware then branches program to the address stored at location x 4004 in the interrupt vector table The watchdog timer overflow interrupt request flag WDIR is set to 1 when the watchdog timer overflows The program interrupt request flag PIR is set to 1 when the undefined instruction is executed Setting PIR or WDIR flag to be 1 enable non maskable interrupt request to be set compulsory 7 6 5 4 3 2 1 0 NMICR Reserved At reset 000 L Reserved Always set to 0 WDIR Watchdog interrupt request 0 No interrupt request 1 Interrupt request generated PIR Program interrupt request 0 No interrupt request 1 Interrupt request generated Figure 3 2 1 Non Maskable Interrupt Control Register NMICR x 03FE1 R W This LSI generates non maskable interrupt and sets the program interrupt request flag PIR at the same time before undefined instruction is exected If setting of the PIR flag is detected in the non maskable interrupt service routine use the software reset which outputs 0 to the reset pin P27 value d
201. MnEN flag Compare TE Po i fFF register coin oo J ot 527 ooog FE FF EE counter TMnIO output PWM output Figure 6 6 3 Count Timing of PWM Output when compare register is x FF 8 bit PWM Output VI 27 Chapter 6 8 bit Timers 6 6 2 Setup Example BPWM Output Setup Example Timers 0 and 2 The 1 4 duty cycle PWM output waveform is output from the TMOIO output pin at 128 Hz by using timer 0 Low frequency oscillation fx is at 32 768 kHz Cycle period of PWM output waveform is decided by the overflow of the binary counter H period of the PWM output waveform is decided by the setting value of the compare register An example setup procedure with a description of each step is shown below TMOIO output 128 Hz Figure 6 6 4 Output Waveform of TMOIO Output Pin Setup Procedure Description 1 Stop the counter 1 Set the TMOEN flag of the timer 0 mode TMOMD x 3F54 register TMOMD to 0 to stop the timer 0 bp3 TMOEN 0 counting 2 Setthe special function pin to 2 Setthe P1OMDO flag of the port 1 output mode the output mode register P1OMD to 1 to set P10 pin to the P1OMD x 3F2F special function pin bp0 P1OMDO 1 Set the P1DIRO flag of the port 1 direction P1DIR x 3F31 control register P1DIR to 1 for the output bp0 P1DIR0 1 mode Add pull up pull down resistor if necessary Chapter 4 I O Ports 3 Select the PWM operation 3 Se
202. O register to 1 to enable start condition XI 44 Operation Chapter 11 Serial Interface 0 Setup Procedure Description 6 Select the first bit to be transfered SCOMDO x 3F90 bp4 SCODIR 20 7 Set the SCOMD2 register Control the output data SCOMD2 x 3F92 bp0 SCOBRKE 0 8 Selectthe added parity bit SC0MD2 x 3F92 bp3 SCONP 0 5 4 SCOPM1 0 00 9 Specify the flame mode SC0MD2 x 3F92 bp7 6 SCOFM1 0 11 10 Set the SCOMD 1 register Select the communication type SCOMD1 x 3F91 bp0 SCOCMD 1 11 Select the clock frequency SCOMD1 x 3F91 bp3 SCOCKM 1 bp2 SCOMST 1 12 Control the pin function SCOMD1 x 3F91 bp4 SCOSBOS 1 bp5 SCOSBIS 1 bp7 SCOIOM 0 13 Enable the interrupt SCORICR x 3FF5 SCORIE 1 SCOTICR x 3FF6 SCOTIE 1 10 11 12 13 Set the SCODIR flag of the SCOMDO register to 0 to select MSB as first transfer bit Set the SCOBRKE flag of the SCOMD register to 0 to select serial data transmission Set the SCOPM1 0 flag of the SCOMD2 register to 00 to select 0 parity and set the SCONPE flag to 0 to add parity bit Set the SCOFM1 0 flag of the SCOMD2 register to 11 to select 8 bits 2 stop bits at the flame mode Set the SCOCMD flag of the SCOMD1 register to 1 to select duplex UART Set the SCOCKM flag of the SCOMD1 register to 1
203. OO At reset Figure 11 2 1 Serial Interface 0 Received Data Buffer RXBUFO 94 R Serial Interface 0 Transmissin Data Buffer TXBUFO 7 6 5 4 3 2 1 0 TXBUFO TXBUFO7 TXBUFOO At reset X XX X X X X X Figure 11 2 2 Serial Interface 0 Transmission Data Buffer TXBUF0 x 03F95 R W Control Registers XI 5 Chapter 11 Serial Interface 0 11 2 3 Mode Registers Serial Interface 0 Mode Register 0 SCOMDO 7 6 5 4 3 2 1 0 SCOMDO SCOCE SCOREN SCOTRN SCODIR 50097 m SCOLNG2 SCOLNG1 SCOLNGO At reset 00000111 Synchronous serial SCOLNG2 SCOLNG1 SCOLNGO transtar bil count 0 1 bits 0 1 2 bit 0 5 0 3 bits 1 4 bits 5 bits 0 0 5 1 1 6 bits 1 0 7 bits 1 8 bits SCOSTE Start condition selection 0 Disable start condition 1 Enable start condition SCODIR First bit to be transfered 0 MSB first 1 LSB first Transmission data polarity SCOTRN selection 0 Positive polrity 1 Negative polrity Receiv lari 0 Positive polrity 1 Negative polrity 0 falling rising 1 rising falling Figure 11 2 3 Serial Interface 0 Mode Register 0 SCOMDO x 03F90 R W XI 6 Control Registers mSerial Interface 0 Mode Register
204. Operation ete e ete i e Ope shes VI 35 6 8 2 Setup Examples re et ES VI 36 Simple Pulse Width Measurement sese VI 38 6 9 1 VI 38 6 9 2 Setup Example Rete ete e ote I RES VI 39 Cascade CONNECTOR dore ete d pro ee prete repete fee VI 41 6 10 Operation osos reete tei ately VI 41 6 10 2 Setup Example n UOCE tabs tees cs essing lead Es VI 43 Remote Control Carrier Output 2 VI 45 6 11 1 Operation ues eee et ee ceat ed itunes VI 45 V contents 6211 2 Setup Example n ia met babi VI 46 Chapter 7 16 bit Timers 7 1 7 2 7 3 7 4 7 5 7 6 7 8 7 9 7 10 OV rVIew e PR rp o ert eri VII 2 7 1 1 FUNCUONS ah aeree BOB rette ett eret 2 7 1 2 1 u ert a re be VII 3 Control Registers scenes eee Ue P ere tee Pe 5 7 2 1 Registers one iv UR URP NUDO IE ERN VII 5 7 2 2 Programmable Timer Registers 6 7 2 3 Timer Mode Registers VII 10 Succ H O INR VII 14 7 3 1 Operation rede e e REO UE VII 14 7 3 2 Setup Example s n eere EU Re ete den qeu VII 18 16 bit Event Co nt ctr pred pe e e ites
205. Ort8La eerte ede te e e Mok ed ito e Eee AIRE IV 35 4 9 1 Description ORE UH IV 35 4 9 2 Registers 2i oen aC dedu edite IV 36 4 9 3 Block Dia Stain uer ec me t ren ic es IV 38 4 10 teet reti red IV 39 4 10 D scrption eoi 39 4 10 22 40 4 10 3 Block Diagram a ns m Pa D SS IV 42 4 11 Synchronous Output Port 6 IV 43 4 11 1 Block Diagtam eee eene tene fene IV 43 4 11 22 R PiSters i e trie pr PE eR ER rers IV 44 4 11 3 Operation aoo oeste pepe ree eite IV 45 4 11 4 Setupexample rette IV 47 Chapter5 _ Prescaler S L OVerVIOWi i qe EUR HI P ERE i UP V 2 5 1 1 Peripheral a oe eta eerte terit V 3 5 1 2 Block Dl fram eb Up Su bue hU 4 iv contents 5 3 Control doce do Dea bud eremita mei ie ee V 5 5 2 1 Registers Tastiere eG ee deem ebed ei V 5 5 2 2 Control Registers a eee US p a ukasa V 6 Operation cre tete ire qe tr pes eene in ee AE 10 5 3 1 Op ration nene em Ep UR UE P be ERR eps V 10 5 3 2 Setup Examples u ue E RO EEEE 1 Chapter6 8 Timers 6 1 6 4 6
206. P50UT1 P5OUTO X3F15 5 Port 5 Output Data IV 22 7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 16 6 Port 6 Output Data IV 26 P7OUT7 P7OUT6 P7OUT5 P7OUT4 P7OUT3 P7OUT2 P7OUT1 P7OUTO X3F17 P7OUT Port 7 Output Data IV 31 P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUTO 18 P8OUT Port 8 Output Data IV 36 65 07 65 06 65 05 65 04 P6SYO3 P6SYO2 P6SYO1 65 00 X 3F1E P6SYO Port 6 Synchronous Output Control IV 27 POING POIN2 POINO X 3F20 POIN Port 0 Input Data 7 P1IN3 P1IN2 P1IN1 P1INO 21 Port 1 Input Data V 11 P2IN7 P2IN2 P2IN1 P2IN0 X 3F22 P2IN Port 2 Input Data V 15 P3IN3 P3IN2 P3IN1 0 X 3F23 Port 3 Input Data V 18 XIV 22 Special Function Registers List Chapter 14 Appendices Bit Symbol Initial Value Description Address Register y gt Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 P5IN3 P5IN2 P5IN1 P5INO X 3F25 P5IN Port 5 Input Data 22 P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6INO X 3F26 P6IN Port 6 Input Data V 26 P7IN7 P7IN6 P7IN5 P7IN4 P7IN3 P7IN2 P7IN1 P7INO X 3F27 P7IN Port 7 Input Data 31 P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 X 3F28 P8IN Port 8 Input Data V 36 PAIN3 PAIN2 PAIN1 PAINO
207. P7PLUD7 P7PLUD6 P7PLUD5 P7PLUD4 P7PLUD3 P7PLUD2 P7PLUD1 P7PLUDO X 3F47 P7PLUD Port 7 Pull up pull down Resistor ON OFF Control V 31 P8PLU7 P8PLU6 P8PLU5 P8PLU4 P8PLU3 P8PLU2 P8PLU1 X 3F48 P8PLU Port 8 Pull up Resistor ON OFF Control 36 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO Port Pull up pull down Resistor ON OFF Control 40 7 TM0BC6 TM0BC5 TM0BC4 TM0BC3 TM0BC2 TM0BC1 TM0BC0 X 3F50 TM0BC Timer 0 Binary Coutner VI 9 TM1BC7 TM1BC6 TM1BC5 TM1BC4 TM1BC3 TM1BC2 TM1BC1 TM1BCO X 3F51 1 1 VI 9 00 7 00 6 00 5 00 4 00 3 00 2 00 1 00 0 52 00 0 Compare Register VI 8 10 7 10 6 10 5 10 4 TM1OC3 TM1OC2 TM1OC1 TM1OC0 X 3F53 TM1OC Timer 1 Compare Register VI 8 TMOMOD TMOPWM TMOEN TMOCK2 TMOCK1 TMOCKO X 3F54 TMOMD Pulse Width Timer 0 Timer 0 Clock Source Selection VI 10 Measure Operation Count Control Selection countro TM1CAS TM1EN TM1CK2 TM1CK1 1 0 X 3F55 TM1MD Timer 1 Timer 1 Clock Source Selection VI 11 Operation Mode Count Selection Countrol TMOPSC1 TMOPSCO 5 X 3F56 CKOMD Count Clock Selection V 7 Prescaler Output 5 TM1PSCO TM1BAS X 3F57 CK1MD Count Clock Selection V 7 Prescaler Output XIV 24 Special Function Registers List Chapter 14 Appendices
208. Precision PWM Output at compare register 2 compare register 1 Timer 7 Here is the count timing as the compare register 2 is set the same value to the compare register 1 Count clock TM7EN flag Compare register 1 Compare register 2 Binary 0000 ou Me eee mo 0000 TM7IO output PWM output Figure 7 7 3 Count Timing of High Precision PWM Output at compare register 2 compare register 1 To output the high precision PWM output set the TMBCR flag of the TM7MD2 register to 1 to select the TM7OC1 compare match as the clear source for the binary counter and the set H output source of the PWM output Also set the T7PWMSL flag to 1 to select the 7 2 compare match as the reset L output source of the PWM output 16 bit High Precision PWM Output VII 33 Chapter 7 16 bit Timers 7 7 2 Setup Example mHigh Precision PWM Output Setup Example Timer 7 Timer 8 The TM7IO output pin outputs the 1 4 duty PWM output waveform at 400 Hz with timer 7 Select fosc 2 at fosc 20 MHz as the clock source One cycle of the PWM output waveform is decided by the set value of a compare register 1 H period of the PWM output waveform is decided by the set value of a compare register 2 An example setup procedure with a description of each step is shown below TM7IO output 400 Hz Figure 7 7 4 Output Waveform of TM7IO Output Pin
209. RMOUT pin outputs the 1 3 duty carrier pulse signal with H period of 36 7 kHz by using timer 0 The source clock of timer 0 is set to fosc 8 MHz at operation An example setup procedure with a description of each step is shown below Base period set by timer 0 Base period set by timer 0 36 7 kHz lt gt li hit RMOUT output 1 3 duty Figure 6 11 3 Output Wave Form of RMOUT Output Pin Setup Procedure Description 1 Disable the remote control carrier output RMCTR x 3F6E bp3 0 2 Selectthe base cycle setting timer RMCTR x 3F6E bp0 RMBTMS 0 3 Select the carrier output duty RMCTR x 3F6E bp1 RMDTYO 1 4 Stop the counter TMOMD x 3F54 bp3 TMOEN 0 5 Setthe remote control carrier output of the special function pin P1OMD x 3F2F bpO P1OMDO 1 P1DIR x 3F31 PIDIR0 1 RMCTR x 3F6E bp4 TMORM 1 Set the RMOEN flag of the remote control carrier output control register RMCTR to 0 to disable the remote control carrier output Set the RMBTMS flag of the RMCTR register 0 to set the timer as a base cycle setting timer Set the RMDTYO flag of the RMCTR register to 1 to select 1 3 duty Set the TMOEN flag of the timer 0 mode register TMOMD to stop the timer 0 counting Set the P1OMDO flag of the port 1 output mode register P1OMD to 1 to set P10 pin as a special function pin Set the P1DIRO flag of the po
210. RQ1 Point Figure 3 3 8 AC Line Waveform and IRQ1 Generation Timing Actual IRQ1 interrupt request is generated several times at crossing the 1 2 Vpp of AC line wave form So the filtering operation by the program is needed The interrupt request is generated at the rising edge of the AC zero cross detector signal 50 External Interrupts Chapter 3 Interrupts BAC Zero Cross Detector Setup Example External interrupt 1 AC zero cross detector generates the external interrupt 1 IRQ1 by using P21 ACZ An example setup procedure with a description of each step is shown below Setup Procedure Description Select the AC zero cross detector signal x 3F8E bp7 P211M 1 Set the interrupt level IRQ1ICR x 3FE3 bp7 6 IRQ1LV1 0 10 Enable the interrupt IRQ1ICR x 3FE3 bp1 IRQ1IE 1 1 Set P21IM flag of the noise filter control register NFCTR to 1 to select the AC zero cross detector signal as the external interrupt 1 generation factor Set the interrupt level by the IRQ1LV 1 0 flag of the IRQ1ICR register If the interrupt request flag has been already set clear the interrupt flag Chapter 3 3 1 4 Interrupt flag setup Set the IRQ1IE flag of the IRQ1ICR register to 1 to enable the interrupt When the input level of the input signal from P21 ACZ pin cross 1 2Vpp the external interrupt 1 is generated III 51 Exter
211. Registers 1 3 Chapter 4 Ports 7 6 5 4 3 2 1 0 P6SYO 65 07 65 06 65 05 65 04 65 03 65 02 65 01 PeSYOO At reset 00000000 port synchronous output pin 65 selection 0 port Disable synchronous output Synchronous output Enable synchronous output Port 6 synchronous output control register P6SYO x 03F1E R W 7 6 5 4 3 2 1 0 FLOAT PARDWN P7RDWN P6RDWN SYOEVS SYOEVS0 At reset 0 0 0 00 SYOEVS1 SYOEVSO P6 synchronous output event selection External interrupt IRQ2 Timer 7 interrupt Timer 2 interrupt O a O Timer 1 interrupt P6RDWN P6 pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor P7RDWN P7 pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor PARDWN PA pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor Pull up Pull down resistor selection Pin control register FLOAT X 03F2E R W Figure 4 7 2 Port 6 Registers 2 3 Pot6 27 Chapter 4 I O Ports 7 6 5 4 3 2 1 0 LCCTR2 LC2SL7 LC2SL6 LC2SL5 LC2SL4 LC2SL3 LC2SL2 LC2SL1 LC2SL0
212. SL4 LC1SL3 LC1SL2 LC1SL1 LC1SLO X 3FDB LCCTR1 14 15 SEG12 13 SEG10 11 SEG8 9 SEG1O SEG3 2 SEG54 V 3337 Port 71 70 Port73 72 Port75 7 4 Port77 76 86 87 Port84 85 Port82 83 Port80 81 XIII 8 Selection Selection Selection Selection Selection Selection Selection Selection LC2SL7 LC2SL6 LC2SL5 LC2SL4 LC2SL3 LC2SL2 LC2SL1 62510 X 3FDC LCCTR2 5 023 60 SEG22 Port 61 SEG21 Port 62 SEG20 Port 63SEG19 Port 64 SEG18 Port 65 SEG17 Port 66SEG16 Port 67 Selection Selection Selection Selection Selection Selection Selection Selection PIR WDIR RESERVED X 3FE1 NMICR Program Watchdog Set Ill 16 Interrupt Interrupt unn Request Request aways 0 IRQOLV1 IRQOLVO REDGO IRQOIE IRQOIR X 3FE2 IRQOICR Specify Externa External External External IIl 19 Interrupt Interrupt Interrupt nterrupt Level Valid Edge Enable Request IRQ1LV1 IRQ1LVO REDG1 IRQ1IR X 3FE3 IRQ1ICR Specify Externa External External External III 20 Interrupt Interrupt Interrupt nterrupt Level Valid Edge Enable Request IRQ2LV1 IRQ2LV0 REDG2 IRQ2IE IRQ2IR X 3FE4 IRQ2ICR Specify Externa External External External III 21 Interrupt Interrupt Interrupt nterrupt Leve Valid Edge Enable Request IRQ4LV1 IRQ4LV0 IRQ4IE IRQ4IR X 3FE6 IRQ4ICR Specify External Set External External Ill 22 Interrupt Interrupt Interrupt Leve always 0 Enable Request TMOLV1 TMOLVO TMOIE TMOIR X 3FE9 TMOICR Specify Interrupt Level Int
213. SP 5 HA h SP 6 SP 0000 0011 Contorl instructions REP imm3 imm3 1RPC 0010 0001 1 1 repeat whn imm3 0 rep imm3 1 Other than the instruction of MN101C Series the assembler of this Series has the following instructions as macro instructions The assembler will interpret the macro instructions below as the assembler instructions macro instructions replaced instructions remarks INC Dn ADD 1 Dn DEC Dn ADD 1 Dn INC An ADDW 1 An DEG An ADDW 1 An INC2 An ADDW 2 An DEC2 ADDW 2 An CLR Dn SUB Dn Dm ASL Dn ADD Dn Dm LSL Dn ADD Dn Dm ROL ADDC Dn Dm NEG NOT ADD Dn 1 Dn NOPL DWn DWm MOV MOV 0 SP Dn MOV MOV Dn 0 SP MOVW MOVW 0 SP DWn MOVW MOVW DWn 0 SP MOVW MOVW 0 5 MOVW MOVW An 0 SP Ver3 2 2002 01 31 Instruction Set XIV 19 Chapter 14 Appendices 14 4 Instruction Map 101 SERIES INSTRUCTION MAP istribble2ndnibble MOV 8 108 RTI CMP 8 abs8 abs12 POP An D E F ADD 8 Dm MOVW 8 DWm MOVW 8 Am JSR d12 label JSR d16 label PUSH An MOV 8 abs8 abs12 OR 8 Dm AND 8 Dm When the exension code is b oo10 When the extension code is b 0011
214. T b 1 3 duty 1 3 bias 1 4 duty 1 8 bias 2 V Vicp 3 V MN101C527 Von o Input 2 V basic voltage o Input 3 V basic voltage 2 1 3 duty 1 3 bias 1 4 duty 1 3 bias 101 527 o Input C2 T 13 3 5 18 Operation Chapter 13 LCD Functions Supplying voltage when using the internal voltage booster circuit Supply the voltage as shown in table 13 3 3 Table 13 3 3 LCD Power Supply Voltage booster 2 times 2 times 2 times 3 times 3 2 times 1 2 times Action voltage booster voltage booster voltage booster voltage booster Bias Method Static 1 2 1 3 1 3 ower Supply VLC1 2 Vic is output 3 Vics is output 3 2 is output VLC2 2 Vics is output Input 2 3 Connect and Vics and intput 1 2 VLC3 Input 1 3 1 2 Vic is output Figure 13 3 6 shows examples of the LCD power supply connection 1 3 duty 1 3 bias 1 4 duty 1 3 bias 2 V Vicp 3 V 2 and 3 times voltage booster MN101C527 Input 2 V reference voltage P 3 V cv 2 EE 4 1 V Vica o Input 1 V reference voltage Ju nor CP C1
215. TR1 X 3FDB bp1 LC1SL1 LCCTR2 X 3FDA bp6 4 COMSK2 0 II b Setup the LCD panel display data Segment output latch 5 1 0 2 00 76 Segment output latch 2 01 X 40 Segment output latch X2E02 X 27 SEG3 2 SEG5 4 6 Startthe LCD operation LCDMD1 X 3FD9 bp7 LCDEN 1 0100 111 Set 0 to the flag of the LCD mode control register 1 LCDMD1 to stop the LCD operation Set 0 to the LC1SEL flag of the LCD mode control register 1 LCDMD1 to set display duty 1 3 Select 5 215 as the LCD clock source with LCDCKGS to 0 flags of the LCD mode control register 1 LCDMD1 Select SEGO to 5 with the LC1SL3 of the out put control register LCCTR 1 and select 2 0 with the COMSL2 0 of the LCD mode control register 2 LCDMD2 Display 23 on the display panel with the ad dress X 2E00 to X 2E02 segment out put latch SEGO 5 Chapter 13 13 4 5 the LCD display example 1 3 duty Set 1 to the LCDEN flag of the LCD mode control register 1 LCDMD1 to start the LCD operation 34 Display Chapter 13 LCD Functions Display 35 Chapter 13 LCD Functions 13 4 7 1 4 duty 81 4 Duty MN10 Segment Latch X 2EOB X 2E01 X 2E01 2 00 10527 X 2E00 bit7 bit3 bit6 bit2 bit5 bit1 bit4 bitO SEG3 A electrode B electrode iit not lit SEG2
216. UF14 ANSH1 ANST control ANBUF15 7 ANBUF16 ANBUE06 ANBUF17 ANBUFO7 gt A A 3 Vret RS 2 2 A D conversion data ANO Y upper 8 bits 1 Sample and 10 bits A D MUX gt AN2 hold comparator 5 AN3 A D conversion data lower 2 bits Vret fs 2 fs 4 15 8 MUX fx x 2 gt 1 6 MUX 1 18 Figure 12 1 1 A D Converter Block Diagram Overview XII 3 Chapter 12 A D Converter 12 2 Control Registers A D converter consists of the control register ANCTRn and the data storage buffer ANBUFn 12 2 1 Registers Table 12 2 1 shows the registers used to control A D converter Table 12 2 1 A D Converter Control Registers Register Address RAN Function Page ANCTRO x 0O3FBO R W A D converter control register 0 XII 5 ANCTR1 1 R W A D converter control register 1 XII 6 ANCTR2 x 0O3FB2 R W A D converter control register 2 XII 6 ANBUFO A D converter data storage buffer 0 7 ANBUF1 x 03FB4 R A D converter data storage buffer 1 XII 7 ADICR xO3FFA R W A D converter interrupt control register IIl 32 PAIMD R W Port input mode register 40 PAPLUD X 03F4A RAW Port A pull up pull down resistance control register IV 40 R W Readable Writable R Readable only XII 4 Control Registers Chapter 12 Converter 12 2 2 Control Registers A D Converter Co
217. VO PODIR PODIRO PODIR PODIR2 Added Not added Added Not added Added Not added Pull up 5 POPLU POPLU0 POPLU POPLU2 Pins Setup with 2 channels at reception Table 11 3 10 shows the setup for synchronous serial interface pin with 2 channels SBO pin SBT pin at reception SBI pin can be used as a port Table 11 3 10 Setup for Synchronous Serial Interface Pin with 2 channels at reception Data input pin Clock VO pin Setup item SBT pin SBO pin SBI pin Internal clock External clock Port pin POO 2 SBI SBO connected SBI SBO pin 5 SCOMD1 SCOIOM Port Serial data input Serial clock VO Serial clock VO Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Push pull Push pull Style P _ Nch open drain Nch open drain SC0ODC SC0ODC1 Input mode Output mode Input mode VO PODIR PODIRO PODIR PODIR2 Added Not added Added Not added Pull up i POPLU POPLU2 XI 26 Operation 11 3 2 Setup Example gmTransmission Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown Table 11 3 11 shows the conditions at transmission reception Chapter11 Serial Interface 0 Table 11 3 11 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item set to Setup item set to Independent SBI SBO pin with 3 ch
218. W Port 0 pull up resistor control register 7 P1OUT xO3F11 R W Port 1 output register IV 11 P1IN xOSF21 R 1 input register 11 1 P1DIR x 03F31 R W Port 1 direction control register IV 11 P1PLU 41 R W Port 1 pull up resistor control register IV 11 P1OMD x 03F2F RAW Port 1 output mode register 12 2 x 03F12 R W Port 2 output register 15 Port 2 2 x 03F22 R Port2 input register 15 P2PLU x 03F42 R W Port 2 pull up resistor control register 15 x 03F13 R W Port output register IV 18 pons x 03F23 R 3 input register 18 P3DIR x 03F33 R W Port direction control register 18 x 03F43 RAN Port 3 pull up resistor control register 18 IV 4 Overview Chapter 4 Ports Table 4 1 3 Port Control Registers List 2 2 Register Address RW Function Page P5OUT X O3F15 R W Port 5 output register 22 x 03F25 R Port5 input register 22 Port 5 P5DIR x 03F35 R W Port 5 direction control register V 22 P5PLU x 03F45 R W Port 5 pull up resistor control register 22 x 03F3F R W 5 output mode register 23 6 x 03F16 R W Port 6 output register 26 x 03F26 6 input register 26 P6IMD x 03F3E R W
219. X 3F2A PAIN Port A Input Data V 40 PARDWN P7RDWN P6RDWN SYOEVS1 SVOEVSO X 3F2E FLOAT PA Pull up down P7 Pull up down P6 Pull up down P6 Synchronous Output IV 27 32 41 Resistor Resistor Resistor lecti Selection Selection Selection vent Selection P1OMD5 P1OMD4 P1OMD3 P1OMD2 P1OMD1 P1OMDO X 3F2F P1OMD Port Port Port Port Port Port IV 12 Timer 8 7 Timer 3 Timer 2 1 0 Output Selection Output Selection Output Selection Output Selection Output Selection Output Selection PODIR6 PODIR2 PODIR1 PODIRO X 3F30 PODIR Port 0 I O Derection Control 7 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO 1 P1DIR Port 1 I O Derection Control V 11 P3DIR3 P3DIR2 P3DIR1 P3DIRO X 3F33 P3DIR Port 3 Derection Control V 18 P5DIR3 P5DIR2 P5DIR1 P5DIR0 X 3F35 P5DIR Port 5 Derection Control 22 P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0 X 3F36 P6DIR Port 6 Derection Contro V 26 P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIR0 X 3F37 P7DIR Port 7 Derection Contro V 31 P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0 X 3F38 P8DIR Port 8 Derection Contro V 36 PAIMD3 PAIMD2 PAIMD1 PAIMD0 X 3F3A PAIMD Port Analog n Input Pin Selection IV 40 6 7 P6KYEN6 P6KYEN5 P6KYEN4 6 2 P6KYEN1 P6KYEN0 X 3F3E P6IMD P67 KEY P66 KEY P65 KEY P64 KEY P63 KEY P62 KEY P6
220. XXIE Generated interrupt level IL Figure 3 1 4 Determination of Interrupt Acceptance 1 Acceptance of an interrupt does not reset the corresponding interrupt enable xxxIE to Or When set as xxxLV1 1 xxxLV0 1 the set interrupt is disabled regardless of the values of XXXIR 8 Overview Chapter 3 Interrupts 0 and interrupts are disabled when MIE in the PSW is reset to 0 by a program Reset is detected MIE 1 and interrupts are enabled when MIE in the PSW is set to 1 by a program The interrupt mask level IM IM1 IMO in the processor status word PSW changes when The program alters it directly A reset initializes it to 0 000 Maskable interrupt is accepted the interrupt level becomes the interrupt mask level Execution of the RTI instruction at the end of an interrupt service routine restores the processor status word PSW and thus the previous interrupt mask level 1 101 series does not reset the maskable interrupt enable MIE flag of the processor status word PSW to 0 when accepting interrupts Non maskable interrupts have priority over maskable ones Overview HI 9 Chapter 3 Interrupts minterrupt Acceptance Operation When accepting an interrupt hardware of this LSI saves the handy address register the return address from the
221. YO RMOEN TMORM Timer 0 output Timer 3 output Figure 6 1 3 Remote Control Carrier Output Block Diagram Overview VI 5 Chapter 6 8 bit Timers 6 2 Control Registers Timers 0 to 3 consist of the binary counter TMnBC and the compare register TMnOC And they are controlled by the mode register TMnMD When the prescaler output is selected as the count clock source of timers 0 to 3 they should be con trolled by the prescaler control register PSCMD and the prescaler selection register CKnMD Remote control is controlled by the remote control carrier output control register RMCTR 6 2 1 Registers Table 6 2 1 shows registers that control timers 0 to 3 and remote control Table 6 2 1 8 bit Timer Control Registers Register Address R W Function Page x 03F50 R Timer 0 binary counter VI 9 TMOOC x 03F52 RAW Timer 0 compare register VI 8 TMOMD x 03F54 R W Timer 0 mode register VI 10 CKOMD x 03F56 R W Timer 0 prescaler selection register V 7 PSCMD x 03F6F R W Prescaler control register V 6 TMOICR x 03FE9 R W Timer 0 interrupt control register Ill 21 P1OMD xO3F2F R W 1 output mode register 12 P1DIR x 03F31 R W Port 1 direction control register 11 1 x 03F51 R Timer 1 binary counter VI 9 1 x 03F53 RAW Timer 1 compare register VI 8 TM1MD x 03F55 R W Timer 1 mode reg
222. acter bit is odd SCOFEF Framing error Stop bit is not detected iJudgement of Brake Status Reception Reception at brake status can be judged If all received data from start bit and stop bit is 0 the SCOBRKF flag of the SCOMD2 register is set and regards the brake status The SCOBRKF flag is set at generation of the reception complete interrupt SCORIRQ ilContinuous Communication This serial interface has continuous communication function If data is set to the transmission data buffer TXBUFO during communication the transmission buffer empty flag SCOTEMP is set to continue auto matic communication This does not generate any blank in communication Set data to TXBUFO be tween previous data setup and generation of the communication complete interrupt SCOTIRQ XI 34 Operation Chapter 11 Serial Interface 0 iChanging Polarity of Transmission Reception Data The polarity of the transmission reception data can not be swtched during UART communication Therefore setting SCOTRN and SCOREN flags of the SCOMDO register has no effect during UART communication iClock Setup Transfer clock is not necessary for UART communication itself but necessary for setup of data transmis sion reception timing in the serial interface Select the timer to be used as a baud rate timer by the SCOCKS register and set the SCOMST flag of the SCOMD register to 1 to select the internal clock clock master 1 At UART communication se
223. ag 0 Disable interrupt Enable interrupt TM2 TM2 LV1 LVO Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 8 Timer 2 Interrupt Control Register TM2ICR x O3FEB R W 24 Registers mTimer 3 Interrupt Control Register Chapter3 Interrupts The timer 3 interrupt control register TM3ICR controls interrupt level of timer 3 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 TMSICR 7 6 1 0 Lvi LVO At 0 0 0 0 TMSIR Interrupt request flag 0 No interrupt request 1 Generate interrupt request TMSIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Ts TMS Interrupt level fla LVO P 9 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 9 Timer Interrupt Control Register TMSICR x 03FEC R W Control Registers III 25 Chapter3 Interrupts mTimer 6 Interrupt Control Register TM6ICR The timer 6 interrupt control register TM6ICR controls interrupt level of timer 6 interrupt interrupt enable flag and interrup
224. als of the 16 bit timers 7 and 8 are generated by fosc or fs When the 1 timer s clock source fosc they generated by fosc Other than that they generated by fs This requires cautions when external event frequency TMnIO input is counted with event frequency higher than fs as this setting could cause inaccurate counting Switching the clock source to use fs as a system clock by dividing oscillation clock fosc requires extra attention 16 bit Timer Capture VII 39 Chapter 7 16 bit Timers When setup is as following 1 2 and external interrupt valid edge is switched by program interrupt request and capture trigger are generated 1 at switching the valid edge from the falling to the rising when the interrupt pin is H level 2 at switching the valid edge from the rising to the falling when the interrupt pin is L level This does not happen if the interrupt edge is switched after the generation of an valid edge interrupt set in advance But when the both edges interrupt function is used this could happen The noise influence should be considered when operating the interrupt flag on program Chapter 3 3 3 4 Specified Polarity Edge Interrupt Capture Count Timing as a Both Edges of External Interrupt Signal is selected as a Trigger Timer 7 TM7EN flag Compare N register Binary 0000 o001 40111 0112 0113X0114 5555545556 5557 5558 c counter External interrupt
225. alue is written to an input capture register Directly writing to the register by program is disabled mTimer 7 Input Capture Register TM7IC 7 6 5 4 3 2 1 0 TM7ICL5 TM7ICL4 TM7ICL3 TM7ICL2 TM7ICL1 TM7ICLO Atreset XXXXXXXX TM7ICL TM7ICL6 Figure 7 2 17 Timer 7 Input Capture Register Lower 8 bits TM7ICL 03 76 R 7 6 5 4 3 2 1 0 TM7ICH TM7ICH7 TM7ICH6 TM7ICHS TM7ICH4 TM7ICH3 TM7ICH2 TM7ICH1 TM7ICHO At reset X X X X XXXX Figure 7 2 18 Timer 7 Input Capture Register Upper 8 bits TM7ICH x 03F77 R Timer 8 Input Capture Register TM8IC 7 6 5 4 3 2 1 0 TM8ICL TMBICL7 TM8ICL6 TM8ICL5 TM8ICL4 TM8ICL3 TM8ICL2 TM8ICL1 TM8ICLO At reset XX XX X X X X Figure 7 2 19 Timer 8 Input Capture Register Lower 8 bits TM8ICL x 03F86 R 7 6 5 4 3 2 1 0 TM8ICH TM8ICH7 TM8ICH6 TM8ICH5 TM8ICH4 TM8ICH3 TM8ICH2 TM8ICH1 TM8ICHO Atreset XXX XX XXX Figure 7 2 20 8 Input Capture Register Upper 8 bits TM8ICH x 03F87 R Control Registers VII 9 Chapter7 16 7 2 3 bit Timers Timer Mode Registers This is a readable writable register that controls timer 7 Timer 7 Mode Register 1 TM7MD1 TM7MD1 VII 10 7 6 5 4 3 2 1 0 RESERVED RESERVED 7CL TM7PS1 7 50
226. alue of the preset register is loaded to the compare register at the next count clock And the interrupt request flag is set at the next count clock and the binary counter is cleared to x 0000 to restart counting up E When the TMnEN flag is 0 the binary counter is stopped When the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock and the binary counter is cleared So set the compare register as the set value of the compare register the counts till the interrupt generation 1 When timer n compare register 2 match interrupt is generated and TMnOC1 compare match is selected as a binary counter clear source the set value of the compare register 2 should be smaller than the set value of the compare register 1 On the interrupt service routine clear the timer interrupt request flag before the timer is started At 0000 x 0001 the timer n interrupt request generation has the same wave form When more than 2 waits is set at access to the special register area by the IOW1 IOWO flag of the MEMCTR register write the same value 2 times at setup of the preset register when the timer is stopped When 1 wait or no wait is set there is no need to do this This is for the functions of a 16 bit timer Chapter 2 2 3 2 Control Registers Operation VII 17 Chapter 7 7 3 2 16 bit Timers
227. ang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang MALAYSIA Tel 60 4 201 5113 Fax 60 4 261 9989 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor MALAYSIA Tel 60 7 331 3822 Fax 60 7 355 3996 Oe Thailand Sales Office Panasonic Industrial THAILAND Ltd PICT 252 133 Muang Thai Phatra Complex Building 31st FI Rachadaphisek Rd Huaykwang Bangkok 10320 THAILAND Tel 66 2 693 3428 Fax 66 2 693 3422 Philippines Sales Office PISP Panasonic Indsutrial Sales Philippines Division of Matsushita Electric Philippines Corporation 102 Laguna Boulevard Bo Don Jose Laguna Technopark Santa Rosa Laguna 4026 PHILIPPINES Tel 63 2 520 8615 Fax 63 2 520 8629 lndia Sales Office National Panasonic India Ltd NPI E Block 510 International Trade Tower Nehru Place New Delhi_110019 INDIA Tel 91 11 629 2870 91 11 629 2877 Indonesia Sales Office P T MET amp Gobel M amp G JL Dewi Sartika Cawang 2 Jakarta 13630 INDONESIA Tel 62 21 801 5666 62 21 801 5675 Sales Office Panasonic Industrial Shanghai Co Ltd PI SH Floor 6 Zhong Bao Mansion 166 East Road Lujian Zui PU Dong New District Shanghai 200120 CHINA Tel 86 21 5866 6114 86 21 5866 8000 Panasonic Industrial Tianjin Co Ltd PI TJ Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 CHINA Tel 86 22 2313 977
228. annels Clock source fs 2 Transfer bit count 8 bits Clock source 1 8 dividing divided by 8 Start condition none SBT SBO pin style Nch open drain First transfer bit MSB SBT pin pull up resistor Added Input edge falling edge SBO pin pull up resistor Added E Serial 0 communication Output edge rising edge complete interrupt Enable Clock Internal clock An example setup procedure with a description of each step is shown below Setup Procedure Description bp2 0 bp1 0 bp2 0 bp2 0 bp2 0 1 Select the prescaler operation PSCMD x 3F6F bpO PSCEN 2 Select the clock source SCOCKS x 3F97 SCOPSC2 0 100 bp3 SCOTMSEL 0 3 Control the pin type SCOODC x 3F96 SCOODC1 0 11 POPLUD x 3F40 POPLUD2 0 1 1 4 Control the pin direction PODIR x 3F30 PODIR2 0 101 5 Setthe SCOMDO register Select the transfer bit count SCOMDO x 3F90 SCOLNG2 0 111 1 1 Setthe PSCEN flag of the PSCMD register to 1 to select prescaler operation 2 Select the clcok source by the SCOCKS register Set bp3 0 to 0100 to select fs 2 3 Set the SCOODC1 0 flag of the SCOODC register to 11 to select N ch open drain to the SBO SBT pin Set the POPLUD2 0 flag of the POPLUD register to 1 1 to add pull up pull down resistor 4 Set the PODIR2 0 flag of the port 0 pindirection control register PODIR to 101 to set POO P02 output mode and to set input m
229. asurement is enabled by loading the value of the binary counter to the capture register at the interrupt generation edge of the external interrupt 0 input signal with timer 7 In the example setup procedure shown below rising edge is selected to be an interrupt generation edge interrupt interrupt External interrupt 0 IRQ 0 input Pulse width to be measured Figure 7 9 3 Pulse Width Measurement of External Interrupt 0 Setup Procedure Description 1 Stop the counter 1 Setthe TM7EN flag of the timer 7 mode TM7MD1 x 3F78 register 1 TM7MD1 to 0 to stop timer 7 bp4 TM7EN 0 counting 2 Select the timer clear condition 2 Setthe TM7BCR flag of the timer 7 mode TM7MD2 x 3F79 register 2 TM7MD2 to 1 to select the bp5 TM7BCR 1 compare match as the source to clear the binary counter 3 Select the count clock source 3 Select fosc as a clock source by the TM7CK1 TM7MD1 x 3F78 0 flag of the TM7MD1 register And select 1 1 bp1 0 TM7CK1 0 00 no dividing of fosc as the count clock source bp3 2 TM7PS1 0 00 by the 7 51 0 flag 4 Select the capture trigger interrupt 4 Select the external interrupt 0 IRQO input as source the generation source of capture trigger by the TM7MD2 x 3F79 T7ICT1 0 flag of the TM7MD2 register bp1 0 7 0 00 5 Select the interrupt generation valid 5 Set the REDGO flag of the external interrupt 0 edge control register IRQOICR to 1 to select the
230. ation set the TM7EN flag of the lower 16 bit timers to 1 to be operated Also select the clock source with the lower 16 bit timer Other setup and count timing are the same as the 16 bit timer at independently operation When timer 7 and timer 8 are used in cascade connection timer 8 is used as an interrupt request flag Timer pulse output of timer 7 is L fixed output Timer 7 interrupt should be disabled as interrupt request of timer 7 is generated Cascade Connection VII 45 Chapter 7 16 bit Timers 7 10 2 Setup Example Timer Operation Connection Timer Setup Example Timer 7 Timer 8 Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 7 and timer 8 as a 32 bit timer is shown An interrupt is generated in every 100000 cycles 40 ms by selecting source clock to fs 4 fosc 20 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD1 x 3F78 bp4 7 0 TM8MD1 88 bp3 0 2 Selectthe condition for timer clear TM7MD2 x 3F79 bp5 STM7BCR TM8MD2 89 bp5 TM8BBCR 1 3 Select the normal lower timer operation TM7MD2 x 3F79 bp2 TM71CEN 00 bp4 TM7PWM 00 4 Set the cascade connection TM8MD1 x 3F88 TM8CAS 1 5 Select count clock source TM7MD1 x 3F78 bp1 0 TM
231. bitrary value to the input capture register TMnIC In synchronized with this capture trigger the value of the binary counter is loaded to the input capture register TMnEN flag Compare register Binary m ME EST ems jejeje System clock Capture trigger Synchronous to writing signal Capture register 0000 0114 Y 5558 Figure 7 9 2 Capture Count Timing Triggered by Writing Software Timer 7 Timer 8 N A capture trigger is generated at the writing signal to the input capture register The writing signal is generated at the last cycle of the writing instruction In synchronized with this capture trigger the value of the binary counter is loaded to the input capture register That value is depending on the value of the binary counter at the falling edge of the capture trigger The other timing is the same as the timer operation The writing to the input capture register to generate a capture trigger should be done with a 8 bit access instruction of the TMnICL register or the TMnICH register At this time data is not actually written to the TMnIC register hardware there is flag to disable the capture operation triggered writing software Capture operation is enabled regardless of the TnICEN flag of the TMnMD2 register 16 bit Timer Capture VII 41 Chapter 7 16 bit Timers 7 9 2 Setup Example iCapture Function Setup Example Timer 7 Timer 8 Pulse width me
232. bs8 bp BCLR abs16 bp mem8 abs16 amp bpdata PSW 0 meme8 abs16 bp BTST imm8 Dm Dm amp immea8 PSW BTST abs16 bp Branch instructions mem8 abs16 amp bpdata PSW if ZF 1 3 4 if ZF 0 PC 3 PG 1001 000H BEQ label if ZF 1 PC 4 d7 label H PC if ZF 0 PC 4 PC 1000 1010 BEQ label if ZF 1 PC 54d1 1 label H gt PC PC 5PC 1001 1010 BNE labe if ZF 0 PC 3 d4 label H PC if ZF 1 PC 3 PC 1001 001H BNE labe if ZF 0 PC 4 d7 label H gt PC 4 1000 1011 BNE labe 0 5 411 1 5 1001 1011 label label F 0 PC 4 d7 label H gt PC 1 4 0 PC 5 d11 label H PC F 1 PC 5 gt PC 1000 1001 1000 1000 BCC label PC 4 d7 label H PC 4 1000 1100 BCC label 5 11 5 1001 1100 BCS label C 4 d7 label H PC 4 1000 1101 BCS label 5 11 1001 1101 BLT label PC 5 PC if VF NF 1 PC 44d7 label H PC if VF NF 0 PC 4 PC 1000 1110 BLT label if VF4NF 1 PC 5 d1 t label H PC 0 5 1001 1110 BLE label 7 1 4 07
233. c at the timing control circuit based on the LCD clock divided by the prescaler and supplies them to the common driver and the multiplexer The common driver outputs the common signals which are necessary for the LCD display based on the voltage from the LCD power supply When the LCD is OFF Vss is output and the potential difference between the LCD electrodes becomes 0 V The multiplexer selects the segment output latched data in response to the signal from the timing control circuit and supplies it to the segment driver The segment driver converts the content of the segment output latch into the signals which is capable of driving the LCD based on the voltage supplied to LCD power supply then outputs the segment signal When the LCD is OFF Vss is output and the potential difference between the LCD electrodes becomes 0 At reset common pins and segment pins become high impedance Therefore when reset input from external sources is long there could be some adverse effects such as blinks of the LCD display In STOP mode supplies from the main clocks is stopped and the LCD drive cannnot be operated Set 0 to the enable flag of the LCD driver circuit before entering STOP mode 12 Operation Chapter13 LCD Functions 13 3 2 Voltage Booster Circuit for LCD Drive This LSI has internal booster circuit for LCD drive This booster circuit contains reference voltage input pin Vice or Vics pin capacitor connection pins
234. cation of transfer bit 7 bits 1STOP 7 bits 2STOPs count Frame selection 168 bil 8 bits 1STOP 8 bits 2STOPs Selection of parity bit Y 0 parity 1 bit control odd even parity Selection of start condition Y only enable condition is available Specify of the first transfer 4 bit Specify of input edge 4 2 output edge Continuous operation Y Internal clock 1 8 dividing N only 1 8 dividing is available fosc 2 fosc 2 fosc 4 fosc 4 fosc 16 fosc 16 Clock source fosc 64 fosc 64 fs 2 fs 2 fs 4 fs 4 Timer 3 output External clock Timer 3 output Maximum transfer rate 2 5 MHz 300 kbps standard 300 bps to 38 4 kbps timer 3 output fosc Machine clock High speed oscillation fs System clock q Chapter 2 2 5 Clock Switching Serial Interface 0 Chapter 11 11 1 2 Block Diagram Serial Interface 0 Block Diagram 2 4 2 LWd409S 110005 1005 0 14025 N3H0DS S18S00S LWd09S 91095 519
235. ck TAD does not drop less than 800 ns with any oscillator Set the sample hold time Set the sample hold time by the ANSH1 ANSHO flag of the A D converter control register 0 ANCTRO The sample hold time should be based on analog input impedance Set the A D ladder resistance Set the ANLADE flag of the A D converter control register 0 ANCTRO to 1 and a current flow through the ladder resistance and A D converter goes into the waiting 2 to 5 are not in order 3 4 and 5 can be operated simultaneously Select the A D converter activation factor then start A D conversion Set the ANST flag of the A D converter control register 2 ANCTR2 to 1 to start A D converter A D conversion After sampling with the sample and hold time set in 3 A D conversion is decided in comparison with MSB in order Complete the A D conversion When A D conversion is finished the ANST flag is cleared to 0 and the result of the conversion is stored to the A D buffer ANBUFO 1 At the same time the A D complete interrupt request ADIRQ is generated Operation Chapter 12 Converter 1 2 3 4 12 A D conversion clock ANST flag conversion start conversion complete J i 674 ___ A D conversion Sampling Hold bit 8 comparison bit 9 comparison bit 0 comparison Determine Determine Determine Determi
236. d as a PWM output reset L output source with the T7PWMSL flag of the TM7MD2 register 16 bit Standard PWM Output VH 29 Chapter 7 16 bit Timers 7 6 2 Setup Example Standard PWM Output Setup Example Timer 7 Timer 8 The TM7IO output pin outputs the 1 4 duty PWM output waveform at 305 18 Hz with timer 7 at the high frequency oscillation fosc 20 MHz One cycle of the PWM output waveform is decided by the overflow of a binary counter H period of the PWM output waveform is decided by the set value of a compare register 1 An example setup procedure with a description of each step is shown below TM71O output 305 18 Hz Figure 7 6 4 Output Waveform of TM7IO Output Pin Setup Procedure Description 1 Stop the counter 1 Set the TM7EN flag of the timer 7 mode TM7MD1 x 3F78 register 1 TM7MD1 to 0 to stop timer 7 bp4 7 0 counting 2 Set the special function pin to output 2 Set the P1OMD4 flag of the port 1 output mode mode register P1OMD to 1 to set the P14 pin as a P1OMD x 3F2F special function pin Set the P1DIR4 flag of the bp4 PIOMDA 1 porti direction control register P1DIR to 1 P1DIR x 3F31 to set output mode bp4 PMDIRA 1 Add pull up pull down resistor if necessary 4 Ports 3 Setthe output 3 Set the TMPWM flag of the timer 7 mode TM7MD2 x 3F79 register 2 TM7MD2 to 1 to select the PWM bp4 TM7PWM
237. de signal Polarity inversion AC zero cross detection circuit NF1SCK1 IRQOICR IRQOIR 7 o IRQOIE REDGO IRQ0LV0 IRQoLV1 IRQO Interrupt request 16 bit timer IRQ1ICR o IRQ1IR IRQ1IE REDG1 IRQ1LVO I IRQ1LV1 IRQ1 Interrupt request 16 bit timer 3 3 1 External Interrupt 0 Interface and External Interrupt 1 Interface Block Diagram External Interrupts III 35 Chapter3 Interrupts mExternal Interrupt 2 Interface Block Diagram IRQ2ICR 0 EDGDT P22 IRQ2 4 Polarity Inversion Edge detection IRQ2 interrupt request 16 bit timer Figure 3 3 2 External Interrupt 2 Interface Block Diagram HI 36 External Interrupts Chapter 3 Interrupts mExternal Interrupt 4 Interface Block Diagram IRQ4ICR_ o IRQ4IR Interrupt request IRQ4E _ gt Interrupt enable MEX noe Interrupt level 7 60 0 61 IRQ4 Interrupt request P66 KEY6 P67 KEY7 X P6IMD _ 7 Figure 3 3 3 External Interrupt 4 Interface Block Diagram External Interrupts 37 3 Interrupts 3 33 Control Registers The external Interrupt input signals which passed through each external interrupt interface 0 to 2 and 4 generate interrupt requests External inter
238. dependent with 2 channels Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source timer 3 TXDO RXDO pin type Nch open drain Pull up resistor of TXD pin added Parity bit add check O add check Serial 0 transmission complete interrupt Enable Serial 0 reception complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation PSCMD x 3F6F bp0 PSCEN 1 Select the clock source SC0CKS x 3F97 bp2 0 SCOPSC2 0 111 SCOTMSEL 0 Control type SCOODC x 3F96 SCOODOO 1 POPLU x 3F40 bpO POPLUO 1 Control the pin direction PODIR x 3F30 bp1 0 PODIR1 0 01 Set the SCOMDO register Select the start condition SCOMDO x 3F90 bp3 SCOSTE 1 1 Set the PSCEN flag of the PSCMD register to 1 to select prescaler operation Set the bp3 0 flag of the SCOCKS register to 0111 to select timer 3 output as a clock source Set the SCOODCO flag of the SCOODC register to 1 to select N ch open drain for the TXD pin Set the POPLUO flag of the POPLU register to 1 to add pull up resistor Set the PODIR1 0 flag of the port 0 pin direction control register PODIR to 01 to set to output mode and P01 to input mode Set the SCOSTE flag of the SCOMD
239. des Table Maskable interrupt Maskable interrupt 3 1 1 Change Vector number 2 to 28 Vector number 2 to 30 Table address 04008 to x04070 Table address 04008 to x 04078 Write an address to which the RTI instruction is written to 3 6 Key mark Addition memory space of the vector addresss of reserved or unused instruction When set as xxxLV1 1 xxxLV0 1 interrupt of the set 3 8 Key mark Addition interrupt vector address is disabled dispite of the values of XxxlE XXXIR This LSI generates non maskable interrupt and sets the program interrupt request flag PIR at the same time Key mark Addition before undefined instruction is exected If setting of the PIR flag is detected in the non maskable interrupt service 3 16 routine use the software reset which outputs 0 to the reset pin P27 Once a non maskable interrupt is generated and value of Caution Addition the WDIR turns to 1 the value does not return to 0 unless it is cleared by program Cautions about interrrupts generated by undefined Aditionf Cautions for use of both Cautions for use of both edges interrupts interrupts When fosc 28 fosc 29 or fosc 210 is selected as a sampling cycle set the PSCEN flag of the prescaler Addition control register PSCMD to 1 for the prescaler to be see ng state in advance 43 Key mark Addition How to determine pull up pull down resis
240. documents are available MNIOIC Series LSI User s Manual lt Describes the device hardware gt MNIOIC Series Instruction Manual lt Describes the instruction set gt MNIOIC Series C Compiler User s Manual Usage Guide lt Describes the installation the commands and options of the C Compiler gt MNIOIC Series C Compiler User s Manual Language Description lt Describes the syntax of the C Compiler gt MNIOIC Series C Compiler User s Manual Library Reference lt Describes the standard library of the C Compiler gt MNIOIC Series Cross assembler User s Manual lt Describes the assembler syntax and notation gt MNIOIC Series C Source Code Debugger User s Manual lt Describes the use of C source code debugger gt MNIOIC Series PanaX Series Installation Manual Describes the installation of C compiler cross assembler and C source code debugger and the procedure for bringing up the in circuit emulator About This Manual 3 Chapter 1 Chapter 2 3 Chapter 4 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Overview Basic CPU Interrupts I O Ports Prescaler 8 bit Timers 16 bit Timers Time Base Timer 8 bit Free running Timer Watchdog Timer Buzzer Serial Interface 0 A D Converter LCD Appendices ue Co i Contents Chapter 1 Overview 1 1 1 2 1 3 1 4
241. down resistor control register P7PLUD Set the control flag of the port 7 pull up pull down resistor control register P7PLUD to 1 to add pull up or pull down resistor The pull up pull down resistor selection register FLOAT select if pull up resistor or pull down resistor is added The bp5 of the pull up pull down resistor control register FLOAT is set to 1 for pull down resistor set to 0 for pull up resistor ilSpecial Function Pin Setup P70 to P77 can be used as the LCD segment output pins as well When used as SEG8 to SEG15 pins set 1 of bit 4 to 7 LC2SL4 to LC2SL7 in the LCD output control register 1 LCCTR1 The ports and the segments can be switched by 2 bits When segment output is selected input mode is set and the pull up resistors are set to without pull up resistors automatically IV 30 Port7 Chapter 4 Ports 4 8 2 Registers 7 6 5 4 3 2 1 0 P7OUT P7OUT7 P7OUT6 5 P7OUT4 P7OUT3 P7OUT2 700 1 P7OUTO Atreset XX XX X X X X P7OUT Output data 0 Low Vss level is output 1 High level is output Port 7 output register P7OUT x 03F17 R W 7 6 5 4 3 2 1 0 P7IN P7IN7 6 P7IN5 P7IN3 P7IN2 P7IN1 P7IN0 Atreset XXXXXXXX P7IN Input data 0 Pin is Low Vss level 1 Pin is High Vpp level Port 7 input register P7IN x 03F27 R
242. e P1DIRO direction control DQ Write CK N Z Read 8 V 1 8 100 0 qr 7A Port output data 0 J Write Read X gt Reset P1OMDO Output mode control DQ Write Read P1INO I Port input data XY Read Timer input Timer output remote control carrier output Figure 4 3 3 Block Diagram P10 rN mE 2 R P1PLU1 to 5 Pull up resistor control gt Write 4CK Read iid R P1DIR1 direction control 5 gt Write ck A Read WV P11 to P15 5 P10UT1 to 5 M Port output data s D Q 0 U J lt E Write 1CK N FA Read x 77 Reset P1OMD1 to 5 Output mode control DQ Write Read to 5 Port input data M Read Timer input Timer output Figure 4 3 4 Block Diagram P11 to P15 Pot IV 13 Chapter 4 Ports 4 4 Port 2 4 4 1 Description General Port Setup Port 2 is input port except P27 To read input data of pin read out the value of the port 2 input register P2IN P27 is reset pin When the software is reset write 0 to the bp7 of the port 2 output register 2 The port 2 pull up resistor control register P2PLU can select if port 2 is added pull up resistor or not by 1 bit When the control flag of the port 2 pull up resistor control register P2PLU is set to 1 pull up resistor is added P27 is always added pull up res
243. e When the selected interrupt generation cycle is passed the interrupt request flag of the time base interrupt control register TBICR is set to 1 14 Time Base Timer Chapter 9 Watchdog Timer 9 Chapter9 Watchdog Timer 9 1 Overview This LSI has a watchdog timer This timer is used to detect software processing errors That is controlled by the watchdog timer control register WDCTR And once an overflow of watchdog timer is generated a watchdog interrupt WDIRQ is generated If the watchdog interrupt is generated twice consecutively it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware 9 1 1 Block Diagram MWatchdog Timer Block Diagram NRST STOP write WDCTR I R R di O 12 12 1721571 220 m gt internal reset release E 20 84 sysclk 15 2145 fs 210 p DLYCTR 15 26 MUX z 0 fs 2 DLYSO Y _DLYS1_ 250 80251 BUZS2 BUZOE 7 5 220 fs 218 MUX WDIRQ WDCTR fs 216 0 Y WDTS1 WDTCO WDTC1 WDTC2 7 Figure 9 1 1 Block Diagram Watchdog Timer The watchdog timer is also used as a timer to count the oscillation stabilization wait time This is used as a watchdog timer
244. e 7 3 1 16 bit Timer Interrupt Source and Binary Counter Clear Source Timer 7 Timer 8 TMnMD2 register Interrupt source Binary counter clear source TMnIRS1 flag TMnBCR flag 1 1 TM7nOC1 compare match TMnOC1 compare match 0 1 TMnOC1 compare match TMnOC1 compare match 1 0 TMnOC1 compare match full count overflow 0 0 full count overflow full count overflow Timer 7 can generate another set of an independent interrupt timer 7 compare register 2 match inter rupt by the set value of the timer 7 compare registers TM7OC2 At the time of the interrupt the binary counter is cleared as the above setup The compare register is double buffer type So when the value of the preset register is changed during the counting the changed value is stored to the compare register when the binary counter is cleared This function can change the compare register value constantly without disturbing the cycle during timer operation Reload function units even if it is a 16 bit MOVW instruction As a result it will read the data incorrectly ifa a When the CPU reads the 16 bit binary counter TMnBC the read data is handled in 8 bits from the lower 8 bits the upper 8 bits occurs during counting operation To read the correct value of the 16 bit counting TM7BC use the writing program function to the input capture register TM7IC By writing to the TM7IC the counting data of TM7BC can be stored to TM7IC
245. e Base Timer 8 bit Free running Timer 8 4 Time Base Timer 8 4 1 Operation Base Timer Time Base Timer Interrupt is constantly generated by a selected clock source and a interrupt generation cycle Table 8 4 1 shows the interrupt generation cycle in combination with the clock source Table 8 4 1 Selection of Time Base Timer Interrupt Generation Cycle Selected clock generation cycle source fosc X fosc X 1 28 fosc X 1 2 fosc X 1 219 fosc X 1 213 fosc X 1 215 fx X 1 27 fx X 1 28 fx X 1 2 fx X 1 270 fx X 1 213 fx X 1 275 6 4 us 12 8 us 25 6 us 51 2 us 409 6 us 1 64 ms 3 9 ms 7 8 ms 15 6 ms 31 2 ms 250 ms fosc 20 2 fx 2 32 768 kHz 12 Time Base Timer Chapter 8 Time Base Timer 8 bit Free running Timer mCount Timing of Timer Operation Time Base Timer The counter counts up with the selected clock source as a count clock 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fase fx 13 10 8 7 1 2 1 2 1 2 1 2 1 2 1 2 Figure 8 4 1 Count Timing of Timer Operation Time Base Timer When the selected interrupt cycle is passed the interrupt request flag of the time base interrupt control register TBICR is set An interrupt may be generated at switching of the clock source Enable the interrupt after switching the clock source Time base timer cannot stop the operation The initialization can be done by writing an arbitrary value to the time base timer clear con
246. e for more detailsd infomation required for your design purchasing and applications If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual In this LSI manual this LSI functions presented the following order overview basic CPU functions interrupt functions port functions timer functions serial functions and other peripheral hardware functions Each section contains overview of function block diagram control register operation and setting example About This Manual 1 Configuration Each section of this manual consists of a title summary main text key information precautions warnings and references The layout and definition of each section are shown below Su btitle Chapter 2 Basic CPU Sub subtitle 3 2 8 Reset The smallest block N in this manual 2 8 1 Reset operation Main text The CPU contents are reset and registers are initialized when the NRST pin P 27 is pulled to low m Initiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low for at least four clock cycles NRST pin should be holded low for more than 4 clock cycles 200 nS at a 20 MHz NRST pin 4 clock cycles 200 nS at a 20 MHz Figure 2 8 1 Minimum Reset Pulse Width 2 Setting the P2OUT7 flag of
247. e selected by the TM6CK3 1 flag of the TM6MD register Actually fx is selected Set the interrupt generation cycle to the timer 6 compare register 6 At that time TM6BC is initialized to 00 Set the TM6CLRS flag of the TM6MD register to 1 to enable the interrupt request generation Set the interrupt level by the TM6LV1 0 flag of the timer 6 interrupt control register TM6ICR If the interrupt request flag may be already set clear them 6 Chapter 3 3 1 4 Interrupt Flag Setup Set the TMGIE flag of the TM6ICR register to 1 to enable the interrupt the above steps 1 2 can be set at once VIII As TM6OC is set TM6BC is initialized to x 00 to count up When TM6BC matches 6 the timer 6 interrupt request flag is set at the next count clock and TM6BC is cleared to 00 to restart counting 10 8 bit Free running Timer Chapter 8 Time Base Timer 8 bit Free running Timer If the TM6CLRS flag of the TM6MD register is set to 0 TM6BC can be initialized at every rewriting of TM6OC register but in that state the timer 6 interrupt is disabled If the timer 6 interrupt should be used set the TM6CLRS flag to 1 after rewriting the TM6OC register On the timer 6 clock source selection if the time base timer output or the time base timer synchronous output is selected the clock setup of time base timer is necessary 8 bit Free running Timer 11 Chapter 8 Tim
248. e set at the same time When the TXD RXD are connected for communication with 1 channel the TXD inputs outputs serial data The port direction control register PODIR switches I O At recep tion set SCOSBIOS of the SCOMD1 register to 1 to select serial data input The RXD pin can be used as a general port This serial interface contains emergency reset function If communication need to be stopped by force set SCOSBOS and SCOSBIS of the SCOMD1 register to 0 Each flag should be set as the setup procedure in order Activation of communication should be operated after all control registers except Table 11 2 1 TXBUFO RXBUFO are set Only timer 3 can be used as a baud rate timer Refer to Chapter 6 8 bit Timer for baud rate setup Cc cm When timer output is selected as serial interface transfer clock select fosc as a clock source of the timer If other clock is selected normal transfer of serial interface data is not guaran teed XI 46 Operation Chapter 11 Serial Interface 0 In full duplex UART communication using serial interface 0 abnormal reception may occur if data transmission is started during data reception transmission data is set to transmission data buffer Therefore run the following program under the condition that data reception may occur However do not use full duplex UART communication for sequence communication as the software counterm
249. e value can be specified in half byte 4 bit increments so that instruction length can be shorter Handy addressing reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combining handy addresssing with absolute addressing reduces code size For transfer data between memory 7 addressing modes register indirect register relative indirect stack relative indirect abso lute RAM short I O short handy can be used For operation instruction register direct and immediate can be used Refer to instruction s manual for the MN101C series This LSI is designed for 8 bit data access It is possible to tranfer data in 16 bit increments by specifying either all odd or all even addresses H 10 Overview 2 Basic CPU Table 2 1 4 Addressing Modes Addressing mode Effective address Explanation i Dn DWn Directly specifies the oe Only internal i An SP i imm4 imm8 Directly specifies the operand or mask Immediate i imm16 value appended to the instruction code Specifies the address using an address Register indirect register Specifies the address using an address register with 8 bit displacement Specifies the address using an address d16 An Andis register with 16 bit displacement Register relative 94 17 Specifies the address using the program PC d4 counter with 4 bit displacement and H bit ranch instructions only Specifies t
250. easure cannot be used Basic flow of countermeasure program 1 Confirm reception status by SCORBSY flag of SCOSTR register before transmission data is set 2 At SCORBSY O other use set transmission data to TXBUFO 3 At SCORBSY 1 serial reception in progress wait untill SCORBSY O other use Examples of recommended program Label 1 tbnz x 03F93 6 Label 2 1 Branches Label2 at SCORBSY 1 mov 55 x 03F95 2 Set transfer data x 55 to TXBUFO jmp Label 3 Branches to Label3 Label 2102 03 93 6 Label 1 3 Branches to Label1 at SCORBSY 0 loop Label 2 Label 3 To prevent abnormal operation UART transfer rate must be set as follows even when data reception is started after reception status is confirmed 1 before transmission data is set 2 transfer rate selected clock frequency 8 x fs 10 fs system clock frequency Selectable transfer clock sources are shown in following table 2 Operation 2 needs to be executed right after the operation 1 is completed During these procedure prevent branching by disable interrupts or other methods System clock fs Selectable serial interface 0 transfer clock source fs fosc All clock sources fs fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 baud rate timer output fulfill 1 fs fosc 4 fosc 16 fosc 64 fs 4 baud rate timer output fulfill 41 fs fosc 8 fosc 16 fosc 64 baud rate timer output fulfill 1 fs fosc 16
251. ecessary precautions XIV 4 EPROM Versions Chapter 14 Appendices 14 1 4 Differences between Mask ROM Version and EPROM Version The differences between the Mask ROM version and the EPROM version of this LSI are as follows Table 14 1 1 Differences between the Mask ROM version and the EPROM version E MN101C527 Masked ROM Version EPROM version 4 5 V to 5 5 V at 0 1 us 20 MHz 4 5 V to 5 5 V at 0 1 us 20 MHz Operationg voltage 2 7 V to 5 5 V at 0 25 us 8 MHz 2 7 V to 5 5 V at 0 25 us 8 MHz 2 0 V to 5 5 V at 1 00 us 2 MHz 2 3 V to 5 5 V at 1 00 us 2 MHz The masked ROM and EPROM versions share the same design specifications Pin DG characteristics for VO currents input levels etc ROM capacity 16 KB 32 KB Matching evaluation of each version is neccessary when these versions are rotated for mass production Oscillation characteristics Matching evaluation of each version is neccessary when these versions are rotated for mass production Operating tempreture 40 C to 85 20 to 70 s At machine cycle is 2 x cycle of the oscillation clock Noise characteristics There are no other functional differences EPROM Versions 5 Chapter 14 Appendices 14 1 5 Writing to EPROM built in Microcontroller The device type set by each ROM writer should be set to the mode for writing 1 M bit EPROM Set the writing voltage to 12 5 V B Mounting the device on the programming adapter and the
252. ed onto the stack and program is branched to the address specified by the corresponding interrupt vector An interrupt handler ends by restoring the contents of any registers used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was inter rupted Interrupt service routine Main program Interrupt request xxxIR N Hardware processing flag cleared Save up PC PSW etc at head Interrupt g Max 12 machine cycles 11 machine cycles Restart Restore PSW PC up etc E 7771 RTI Figure 3 1 2 Interrupt Processing Sequence maskable interrupts Overview 5 Chapter3 Interrupts Group and Vector Addresses Here is the list of interrupt vector address and interrupt group Table 3 1 2 Interrupt Vector Address and Interrupt Group Vector Vector Interrupt group Control Register Number Address Interrupt source address 0 x 04000 Reset 1 x 04004 Non maskable interrupt NMI NMICR x O3FE1 2 x 04008 External interrupt 0 IRQ0 IRQOICR x 03FE2 3 x 0400C External interrupt 1 IRQ1 IRQ1ICR x 03FE3 4 04010 External interrupt 2 IRQ2 IRQ2ICR x 03FE4 5 x 04014 Reserved 6 04018 External interrupt 4 IRQ4 IRQ4ICR x 03FE6 7 x 0401C Reserved 8 04020 Reserved 9 x 04024 Timer 0 inter
253. edback resistor is built in Figure 1 5 2 Crystal Oscillator 2 Chapter 1 Overview Ta 40 C to 85 C Vpp 2 0 V to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX External clock input 1 5 1 0502 is unconnected 18 Clock frequency 0561 1 0 20 0 2 19 High level pulse width lwhi 22 5 5 Figure 1 5 3 20 Low level pulse width twit 22 5 ns 21 Rising time twrt 5 0 Figure 1 5 3 22 Falling time twit 5 0 External clock input 2 XI XO is unconnected 23 Clock frequency fosc2 32 768 100 kHz 24 High level pulse width twh2 4 5 5 Figure 1 5 4 5 25 Low level pulse width twi2 45 26 Rising time twr2 20 Figure 1 5 4 ns 27 Falling time twi2 20 5 The clock duty rate in the standard mode should be 45 to 55 Electrical Characteristics 1 19 Chapter 1 Overview re are A eee date MM ee MR HMM eem x twh1 gt lt twit gt gt 0 gt lt twf1 lt twc1 2 Figure 1 5 3 OSC1 Timing Chart Figure 1 5 4 XI Timing Chart 1 20 Electrical Characteristics 1 5 3 Chapter 1 Overview DC Characteristics Ta 40 C to 85 2 0 V to 5 5 V Vss 0 V Rating Parameter Symbol Conditions Uni
254. egisters 2 3 IV 32 Port7 Chapter 4 Ports 7 6 5 4 3 2 1 0 LCCTR1 LC1SL7 LC1SL6 LC1SL5 LC1SL4 LC1SL3 LC1SL2 LC1SL1 LC1SLO Atreset 00000000 LC1SLO SEG7 6 Port 80 81 selection 0 Port 80 81 selection 1 5 7 6 selection LC1SL1 SEG5 4 Port 82 83 selection 0 Port 82 83 selection 1 SEG5 4 selection LC1SL2 SEG3 2 Port 84 85 selection 0 Port 84 85 selection 1 SEG3 2 selection LC1SL3 SEG1 0 Port 86 87 selection 0 Port 86 87 selection 1 SEG1 0 selection LC1SL4 SEG8 9 Port 77 76 selection 0 Port 77 76 selection 1 SEG8 9 selection LC1SL5 SEG10 11 Port 75 74 selection 0 Port 75 74 selection 1 SEG10 11 selection LC1SL6 SEG12 13 Port 73 72 selection 0 Port 73 72 selection 1 SEG12 13 selection LC1SL7 SEG14 15 Port 71 70 selection 0 Port 71 70 selection 1 SEG14 15 selection LCD output control register 1 LCCTR1 X 03FDB R W Figure 4 8 3 Port 7 Registers 3 3 Pot7 IV 33 Chapter 4 Ports 4 8 3 Block Diagram Reset Px R P7PLUDO to 7 Pull up pull down resistor control t 1 gt Write Read Reset R FLOAT bp4 Pull u
255. el by assigning an interrupt level of 0 to 3 to interrupt requests Time Base Interrupt Control Register TBICR x O3FFO R W Control Registers III 27 Chapter3 Interrupts mTimer 7 Interrupt Control Register TM7ICR The timer 7 interrupt control register TM7ICR controls interrupt level of timer 7 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 TM7 TM7 _ sase TM7ICR LV1 LVO TM7IE TM7IR At reset 0 0 00 TM7IR Interrupt request flag 0 No interrupt request 1 Generate interrupt request TM7IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt TMy Interrupt level fla LV1 LVO up 9 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 12 Timer 7 Interrupt Control Register TM7ICR x 03FF1 R W HI 28 Control Registers Chapter 3 Interrupts Timer 7 Compare Register 2 match Interrupt Control Register T7OC2ICR The timer 7 compare register 2 match interrupt control register T7OC2ICR controls interrupt level of timer 7 compare register 2 match interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0
256. er PBPLU Set the control flag of the port pull up resistor control register P3PLU to 1 to add pull up resistor Special Function Pin Setup PBO to PB3 can be used as the LCD common output pins COMO to COM3 Set 1 to bit 4 to 7 COMSLO to 3 of the LCD output control register 2 LCCTR2 to use these ports When common output is selected input mode is set and the pull up resistors are set to without pull up resistor automatically Pot3 IV 17 Chapter 4 I O Ports 4 5 2 P3DIR P3PLU IV 18 Port3 Registers 3 2 1 0 P30UT3 P3OUT2 P30UT1 3 1 0 2 0 3 Port output register PSOUT x 03F13 R W 2 1 Port input register P3IN x O3F23 R 0 P3DIR3 P3DIR2 P3DIR1 P3DIR0 3 2 1 0 P3PLU3 P3PLU2 P3PLU1 At reset XXXX Output data 0 Low Vss level is output 1 High level is output At reset XXXX Input data 0 Pin is Low Vss level 1 Pin is High Vpp level Atreset 0000 P3DIR mode selection 0 Input mode 1 Output mode Port direction control register P3DIR x O3F33 R W Atr
257. er 6 8 bit Timers Table 6 3 1 Clock Source Timers 0 1 2 and 3 at Timer Operation Clock source per Count Timer 0 Timer 1 Timer 2 Timer 3 8 bit 8 bit 8 bit 8 bit fosc 50 ns y y Y 4 fosc 4 200 ns y fosc 16 800 ns V fosc 32 1 6 us 5 4 fosc 64 3 2 us V 5 y fosc 128 6 4 us NI fosc 2 409 6 us d 2 fosc 25 1 64 ms z fs 2 200 ns V Y Y 1 4 400 ns 15 8 800 ns y fx 30 5 us y Notes fosc 20 MHz fx 32 768 kHz fs fosc 2 10 MHz Operation 15 Chapter 6 8 bit Timers ilCount Timing of Timer Operation Timers 0 1 2 and 3 Binary counter counts up with selected clock source as a count clock The basic operation of the whole function of 8 bit timer is as follows Count clock TMnEN flag Compare register D EB NSOCOLSOOGOOOC counter Interrupt request flag Figure 6 3 1 Count Timing of Timer Operation Timers 0 1 2 and 3 A If the value is written to the compare register during the TMnEN flag is stopped 0 the binary counter is cleared to x 00 at the writing cycle B If the TMnEN flag is operated 1 the binary counter is started to count The counter starts to count up at the falling edge of the count clock C If the binary counter reaches the value of the compare register the interrupt request flag is set at the n
258. er 7 Preset Register 1 Lower 8 bits TM7PR1L x 03F74 R W 7 6 5 4 3 2 1 0 TM7PR1H TM7PRIH7 TM PRIH6 TM7PRIH4 7 1 TM7PR1H2 TM7PRIH1 TM7PR1HO Atreset XXX XX XXX Figure 7 2 8 Timer 7 Preset Register 1 Upper 8 bits TM7PR1H x 03F75 R W Eimer 7 Preset Register 2 TM7PR2 7 6 5 4 3 2 1 0 TM7PR2L 7 27 TM7PR2L6 TM PR2L5 TM7PR2L4 TM7PR2L3 TM7PR2L2 TM7PR2L1 TM7PR2L0 Atreset XX XXX XX X Figure 7 2 9 Timer 7 Preset Register 2 Lower 8 bits TM7PR2L x 03F7C R W 7 6 5 4 3 2 1 0 TM7PR2H TM7PR2H7 TM7PR2H6 TM7PR2H5 TM7PR2H4 7 2 TM7PR2H2 TM7PR2H1ITM7PR2H0 Atreset XX XXX XX X Figure 7 2 10 7 Preset Register 2 Upper 8 bits TM7PR2H x 03F7D R W 8 Preset Register 1 TM8PR1 7 6 5 4 3 2 1 0 TM8PR1L TM8PRIL7 TM8PR1L6 TM8PR1L5 TM8PR1L4 TM8PR13L TM8PR1L2 TM8PR1L1 TM8PR1LO At reset XX X X XXXX Figure 7 2 11 Timer 8 Preset Register 1 Lower 8 bits TM8PR1L x 03F84 R W 7 6 5 4 3 2 1 0 TM8PR1H TM8PR1H7 TM8PR1H6 TM8PR1H5 TM8PR1H4 TM8PR1H3 TM8PR1H2 TM8PR1H1 Atreset X X X XX XX X Figure 7 2 12 Timer 8 Preset Register 1 Upper 8 bits TM8PR1H x 03F85 R W Control Registers VII 7 7 16 bit Timers Binary c
259. er11 Serial Interface 0 mReception Timing Tmin 0 5T 4 Stp Stop RXD pin bit SCORBSY A input start condition Interrupt i SCORIRQ Figure 11 3 22 Reception Timing parity bit is enabled Tmin 0 5T RXD pin SCORBSY SACS gt input start condition Interrupt m SCORIRQ Figure 11 3 23 Reception Timing parity bit is disabled Operation XI 39 Chapter 11 Serial Interface 0 Transfer Speed Setup Baud rate timer can set any transfer rate Table 11 3 17 shows the setup example of the transfer speed Refer to chapter 6 8 bit Timer for baud rate timer setup Table 11 3 17 UART Serial Interface Transfer Speed Setup Register Setup Register Page Serial 0 clock source timer output SCOCKS XI 11 Timer clock source TMnMD VI 10 to 13 Timer compare register TMnOC VI 8 Timer compare register is set as follows overflow cycle set value of compare register 1 x timer clock cycle baud rate 1 overflow cycle x 2 x 8 8 means that clock source is divided by 8 therefore set value of compare register timer clock frequency baud rate x 2 x 8 1 For example if baud rate should be 300 bps at timer clock source fs 4 fosc 8 MHz fs fosc 2 set value should be as follows Set value of comapre register 8 10 2 4 300 x2 x 8 1 207 Timer clock source and the set value of comapre register at the s
260. errupt Interrupt Ill 23 Enable Request TM1LV1 TM1LV0 TM1IE TM1IR X 3FEA TM1ICR Specify Interrupt Level Interrupt Interrupt Ill 24 Enable Request TM2LV1 TM2LV0 TM2IE TM2IR TM2ICR Specify Interrupt Level Interrupt Interrupt IIl 25 Enable Request TM3LV1 TM3LVO TMSIE X 3FEC TMSICR Specify Interrupt Level Interrupt Interrupt Ill 26 Enable Request TM6LV1 TM6LVO TM6IE TM6IR X 3FEF TM6ICR Specify Interrupt Level Interrupt Interrupt Ill 27 Enable Request TBLV1 TBLVO TBIE TBIR X 3FF0 TBICR Specify Interrupt Level Interrupt Interrupt III 28 Enable Request XIV 28 Special Function Registers List Chapter 14 Appendices Bit Symbol Initial Value Description Address Register 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TM7LV1 TM7LVO 7 TM7IR 1 TM7ICR Specify Interrupt Level Interrupt Interrupt III 29 Enable Request T7OC2LV1 T7OC2LVO T7OC2IE T7OC2IR X 3FF2 T7OC2ICR Specify Interrupt Level Interrupt Interrupt Ill 30 Enable Request TM8LV1 TM8LVO TM8IE TM8IR X 3FF3 TM8ICR Specify Interrupt Level Interrupt Interrupi IIl 31 Enable Requesi SCORLV1 SCORLVO SCORIE SCORIR 5 SCORICR Specify Interrupt Level Interrupt Interrupi IIl 32 Enable Requesi SCOTLV1 SCOTLVO SCOTIE SCOTIR X 3FF6 SCOTICR Specify Interrupt Level Interrupt Interrup Ill 33 Enable Reques A
261. eset 0000 Figure 4 5 1 P3PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 3 Registers 1 2 Port 3 pull up resistor control register P3PLU x 03F43 R W Chapter 4 Ports 7 6 5 4 3 2 1 0 LCDMD2 COMSL3 COMSL2 COMSL1 COMSLO At 00000000 UPEN Voltage booster start flag 0 Stop 1 Start UPCK Voltage booster operation speed control bit 0 Normal speed 1 High speed Set always 0 COMSLO COMO Port 30 selection 0 Port 30 selection 1 COMO selection COMSL1 COM1 Port 31 selection 0 Port 31 selection 1 COMI selection COMSL2 Port 32 selection 0 Port 32 selection 1 CON2 selection COMSL3 COM3 Port 33 selection 0 Port 33 selection 1 selection LCD mode control register 2 LCDMD2 R W Figure 4 5 2 Port 3 Registers 2 2 Pot3 IV 19 Chapter 4 Ports 4 5 3 Block Diagram Rese N to b Pull up resistor control D Write L N Z Read Rese P3DIRO to 3 direction control gt Write JL N Z
262. eset XX X XX XXX Figure 7 2 4 Timer 7 Compare Register 2 Upper 8 bits TM7OC2H x O3F7B R 8 Compare Register 1 TM8OC1 7 6 5 4 3 2 1 0 TM8OC1L TM amp OC1L7 TM8OC1L6 115 TM8OC1L4 TM8OCIL2 TM80C1L1 TM8OC1LO At reset X X X X XXXX Figure 7 2 5 Timer 8 Compare Register 1 Lower 8 bits TM8OC1L x O3F82 7 6 5 4 3 2 1 0 TM8OC1H TMeOCtH7 TM80C1H6 TM8OC1H5 TM8OC1H4 TM8OC1H3 TM8OC1H2 TM80C1HO At reset X X X Figure 7 2 6 Timer 8 Compare Register 1 Upper 8 bits TM8OC1H x O3F83 R VII 6 Control Registers Chapter7 16 bit Timers The timer 7 preset registers 1 and 2 are buffer registers of the compare registers 1 2 of timer 7 If the set value is written to the timer 7 preset registers 1 2 when the counting is stopped the same set value is loaded to timer 7 compare registers 1 2 If the set value is written to timer 7 preset registers 1 2 during counting the set value of timer 7 preset registers 1 2 is loaded to timer 7 compare registers 1 2 at the timing that the timer 7 binary counters are cleared Eimer 7 Preset Register 1 TM7PR1 7 6 5 4 3 2 1 0 TM7PR1L TMPRIL7 TM PRIL6 TM7PRILS 7 114 TM7PRIL3 TM7PRIL2 TM PRIL1 TM7PRILO At reset XX X XX XXX Figure 7 2 7 Tim
263. ewritten in everytime when communication is completed so read out data of RXBUFO till the next receive is completed The received data buffer empty flag SCOREMP is set to 1 at the same time SCOTIRQ is generated SCOREMP is cleared to 0 after RXBUFO is read out If a start condition is input to restart during communication the transmission data is not valid Set the transmission data to TXBUFO again to operate the transmission again Start condition should be switched after both the SCOSBOS and the SCOSBIS flags of the SCOMD 1 register are set to 0 If they are not set to 0 the switching is not valid lt RXBUFO is rewritten everytime when communication is completed At continuous communi cation data of RXBUFO should be read out until the next reception is completed Operation XI 13 Chapter 11 Serial Interface 0 mTranfer bit Count and First Transfer bit When the transfer bit is 1 bit to 7 bits the data storing method to the transmission data buffer TXBUFO is different depending on the first transfer bit selection At MSB first use the upper bits of TXBUFO for storing When there are 6 bits to be transfered as shown on figure 11 3 1 if data A to F are stored to bp2 to bp7 of TXBUFO the transmission is operated from F to A At LSB first use the lower bits of TXBUFO for storing When there are 6 bits to be transfered as shown on figure 11 3 2 if data A to F are stored to bpO to bp5
264. ex SCOTIRQ transmission P SCORIRQ reception TXD output input Used pins RXD input Specification the first MSB LSB transfer bit Selection of parity bit 0 parity 1 parity Parity bit control odd parity even parity Frame selection 7 bits 1 STOP 7 bits 2 STOPs 8 bits 1 STOP 8 bits 2 STOPs Continuous operation V Maximum transfer rate 300 kbps standard 300 bps to 38 4 kbps with baud rate timer Chapter11 Serial Interface 0 WActivation Factor for Communication At transmission if any data is set to the transmission data buffer TXBUF0 a start condition is generated to start transfer At reception if a start condition is received communication is started At reception if the data length of L for start bit is longer than 0 5 bit that can be regarded as a start condition Transmission Data transfer is automatically started by setting data to the transmission data buffer TXBUFO When the transmission is completed the serial 0 transmission interrupt SCOTIRQ is generated ilReception Once a start condition is received reception is started after the transfer bit counter that counts transfer bit is cleared When the reception is completed the serial 0 reception interrupt SCORIRQ is generated mDuplex communication On duplex communication the transmission and reception can be operated separately at the same time The frame mode and parity bit of the used data on tra
265. ext count clock then the binary counter is cleared to x 00 and the counting is restarted D Even if the compare register is rewritten during the TMnEN flag is enabled 1 the binary counter is not changed E If the TMnEN flag is stopped 0 the binary counter is stopped When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the compare register is set the smaller than the binary counter during the count operation the binary counter counts up to the overflow at first If the interrupt is enabled the timer interrupt request flag should be cleared before timer is started The timer n interrupt request generation at TMnOC 00 has the same waveform at TMnOC 01 2 VI 16 Operation 6 3 2 Setup Example Chapter 6 8 bit Timers Timer Operation Setup Example Timers 0 1 2 and 3 Timer function can be set by using timer 0 that generates the constant interrupt Interrupt is generated every 250 cycles 100 us by selecting fs 4 at fosc 20 MHz operation as a clock source A setup procedure example with a description of each step is shown below Setup Procedure Description Stop the counter TMOMD x 3F54 bp3 0
266. f maskable interrupt is valid when the maskable interrupt enable flag MIE flag of PSW is 1 Maskable interrupts have had vector numbers by hardware but their priority can be changed by setting interrupts level field There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority Maskable interrupts are accepted when its level is higher than the interrupt mask level IM1 0 of PSW Non maskable interrupts are always ac cepted regardless of the interrupt mask level II 2 Overview 3 Interrupts 3 1 1 Functions Table 3 1 1 Interrupt Functions 2 Non maskable Interrupt type Reset interrupt interrupt Maskable interrupt Vector number 0 1 2 to 30 Table address x04000 x 04004 x 04008 to x 04078 Starting address Address specified by vector table Interrupt level Can be set to levels 0 to 2 by software Interrupt factor External NRST pin input Errors detection Pl interrupt External pin input Internal peripheral function Generated operation Direct input to CPU core Input to CPU core from non maskable interrupt control register NMICR Input interrupt request level set interrupt level flag xxxLVn of maskable interrupt control register xxxICR to CPU core Accept operation Always accepts Always accepts Accepted only by the interrupt control of the register x
267. fer to the documents attached to the diagnotic tool for how to use it If above problem is identified with the diagnostic tool insert nop instruction to avoid the above relevant condition to be fulfilled Example Addr Code Nmonic 04100 mov A0 DO 04100 89F7 bra 7 If above problem is identified with the diagnostic 04102 00 nop lt tool insert a nop instruction to avoid the 04103 2F dc F2 above relevant condition to be fulfilled 04104 DO dc 00 diagnostic tool be downloaded from our Web site of TECHNICAL REPORT Control Registers HI 17 Chapter3 Interrupts mExternal Interrupt 0 Control Register IRQOICR The external interrupt 0 control register IRQ0ICR controls interrupt level of the external interrupt 0 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 IRQ0ICR 7 6 5 2 1 0 IRQ0 IRQ0 5 LVI LVO REDGO IRQOIEIRQOIR Atreset 000 00 External interrupt IRQOIR request flag 0 No interrupt request 1 Generate interrupt request External interrupt IRQOIE enable flag 0 Disable interrupt 1 Enable interrupt External interrupt valid REDGO edge flag 0 Falling edge 1 Rising edge IRQO IRQO Interrupt level flag LV1 LVO for external interrupt The CPU has interru
268. flag is cleared to 0 And during continuous commu nication the SCOTBSY falg is always set If the transmission buffer empty flag SCOTEMP is cleared to 0 as the communication complete interrupt SCOTIRQ is generated SCOTBSY is cleared to 0 If the SCOSBOS flag is set to 0 during communication the SCOTBSY flag is cleared to 0 Operation XI 17 Chapter 11 Serial Interface 0 mEmergency Reset This serial interface contains emergency reset for abnormal operation For emergency reset the SCOSBOS flag and the SCOSBIOS flag of the SCOMD1 register should be set to 0 SBO pin port input data 1 input At emergency reset the status registers the SCOBRKF flag of the SCOMD2 register all flags of the SCOMDS register are initialized as they are set at reset but the control register holds the set value Bl ast bit of Transfer Data Table 11 3 4 shows the data output holding period of the last bit at transmission and the minimum data input period of the last bit at reception After data output holding period of the last bit H is output Table 11 3 4 Last bit Data Length of Transfer Data The last bit data holding period The last data input period at transmission at reception At master 1 bit data length 1 bit data length Minimum Atslave 1 bit data length x 1 to 1 5 BOther Control Flag Setup Table 11 3 5 shows flags that are not used at clock synchronous communication So they are not needed to set or monitor Tab
269. for boost operation C1 C2 booster output pins Vics Either 2 3 3 2 or 1 2 times boost operation can be selected by changing deference voltage input pin Vic3 or Vice Figure 13 3 1 shows a block diagram of LDC power section including booster circuit gt R R me ed e 5 as ge R LCRON F VLCKP VLCK1 UPON Booster clock VLCK2 59 Ver2 UPMD control circuit VLCK3 amp Booster circuit VoL RESET VSS C2 C1 S L4 G s 55 1l jo T TET m A DD DD T AAAA CDS EE RON CUN Reference 2 voltage 3 3210 NK D3 2 1 0 Level shifter Level shifter Y YY YY YvvYvvvvv LCDVpp lt SEG LCD power supply circuit lt LCDVss o Qmn 3 NOMO gt gt gt Ce zOO lt lt 0 0 _ Figure 13 3 1 LCD Power Section Block Diagram 3 times boost Operation XIII 13 Chapter 13 LCD Functions 2 times times boosting This is applied when LCD panel is used with 1 3 bias To operate 2 or times voltage boost input reference voltage
270. fter evaluate the actual oscillating on the target board dumping resistance may be set if necessary We do not evaluate oscillating of crystal Oscillator on this LSI Set the circuit constant as is recommen dation of the Oscillator manufacturer OSC1 OSC2 or differs depending on stray capacitance of the oscillator or on the mounting circuit So consult the Oscillator manufacturer for the appropreate circuit constant 1 Circuit constant of each ceramic crystal Oscillator which is connected to 1 Cautions for Circuit Setup I 33 Chapter 1 Overview 1 7 Package Dimension Package Code LQFP064 P 1414 Units mm 16 00 0 20 14 00 0 10 48 33 16 00 0 20 14 00 0 10 1 40 0 10 0 10 0 10 100 427 910 SEATING PLANE 0 15 0 05 Sealing material EPOXY resin Lead material Alloy of Cu Lead surface processing Pd plate 0 50 020 Figure 1 7 1 64 LQFP package dimension is subjected to change Before using this product please obtain product specifications from the sales office I 34 Package Dimension Chapter 1 Overview 1 8 Operation Mode Check List Date SE No
271. gnal is inputted to the timer n count clock The synchronous circuit output signal is in synchronization with the falling edge of the system clock derived the TMnIO input signal TMnlO input a N System clock fs Synchronous i i i i I circuit output Count clock Y Y Vosa TMnEN flag Compare register Binary 00 01 02 N N o0 counter Interrupt request flag Figure 6 4 2 Count Timing of Synchronous TMnIO Input Timers 0 to 3 When the synchronous input is selected as the count clock source the timer counter counts up in synchronization with system clock therefore the correct value is always read out Synchronous TMnIO input cannot return from STOP HALT mode VI 20 8 bit Event Count Chapter6 8 bit Timers 6 4 2 Setup Example Count Setup Example Timers 0 1 2 and 3 If the falling edge of the TMnIO input pin signal is detected 5 times an interrupt is generated A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter 1 Setthe TMOEN flag of the timer 0 mode TMOMD x 3F54 register TMOMD to 0 to stop timer 0 bp3 TMOEN 0 counting 2 Set the special function pin to input 2 Set the P1DIRO flag of the port 1 direction P1DIR x 3F31 control register P1DIR to 0 to set P10 pin to bp0 P1DIR0 0 input mode Add pull up pull down resistor if necessary
272. h of BC and OC1 T7PWMSL PWM mode selection 0 Set duty by OC1 1 Set by 2 T7ICEDG Capture trigger edge selection 0 Both edges selection 1 Specified edge selection Figure 7 2 22 Timer 7 Mode Register 2 TM7MD2 x 03F79 R W Control Registers 11 7 16 bit Timers 8 Mode Register 1 TM8MD1 TM8MD1 12 7 6 5 4 3 2 1 0 RESERVEDITM8CAS TM8CL TM8EN TM8PS1 TM8PS0 TM8CK1 TM8CK0 Atreset 00100000 TM8CK1 TM8CK0 Clock source selection 0 fosc 0 1 fs 0 TM8IO input 1 Synchronous TM8IO input TM8PS1 8 50 Count clock selection 0 0 1 1 of clock 1 1 2 of clock 1 0 1 4 of clock 1 1 16 of clock TM8EN Timer 8 count control 0 Halt the count 1 Operate the count TM8CL Timer output reset control 0 Operate timer output 1 Reset Timer 7 8 cascade connection TM8CAS control 0 Timer 7 8 individual operation 1 Timer 7 8 cascade connection operation RESERVED Set always 0 Figure 7 2 23 8 Mode Register 1 TM8ND1 x 03F88 R W Control Registers Chapter7 16 bit Timers 8 Mode Register 2 TM8MD2 7 6 5 4 3 2
273. he address using the program 97 7 counter with 7 bit displacement and H bit _____ 7 _____ ranch instructions only 911 PC 17 OH Specifies the address using the program PG d11 counter with 11 bit displacement H bit branch instructions only d12 PC 17 Specifies the address using the program Yt 412 counter with 12 bit displacement bit branch instructions only d16 PC 17 Specifies the address using the program i branch instructions only 16 counter with 16 bit displacement H bit 15 0 Specifies the address using the stack SP d4 pointer with 4 bit displacement Stack relative indirect Specifies the address using the stack pointer with 8 bit displacement Specifies the address using the stack 5 0 916 SP SP d16 pointer with 16 bit displacement i 7 0 Absolute 99 abs12 11 0 Specifies the address using the operand value appended to the instruction code 15 Optimum operand length be used to abs16 specify the address abs18 17 0 1 i branch instructions only 53 7 0 Specifies 8 bit offset from the address RAM short 00000 Specifies 8 bit offset from the top address enon i IOTOP i08 03 00 of the special function register area Reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combined use with absolute addressing
274. he next count clock Table 7 4 1 Event Count Input Clock Source Timer 7 Timer 8 TM7IO input TM8IO input Event input P14 P15 Synchronous 7 input Synchronous TM8IO input As an actual count clock a signal divided by 1 2 4 16 is selected iCount Timing of TMnIO Input When falling edge is selected Timer 7 8 When TMnIO input is selected TMnIO input signal is input to the timer n count clock The binary counter counts up at the falling edge of the TMnIO input signal or TMnIO input signal that passed the divider TMnEN flag Compare register 1 Ju y nrinnnn AN Binary 0000 0001 0002 wa 00 0001 counter Interrupt request flag Figure 7 4 1 Count Timing TMnIO Input Timer 7 Timer 8 following page If the binary counter is read out during operation incorrect data at counting up may be read To prevent this use the event count by the synchronous input which is shown in the VII 20 16 bit Event Count 7 16 bit Timers mCount Timing of Synchronous TMnIO Input When falling edge is selected Timer 7 Timer 8 If the synchronous TMnIO input is selected the synchronizing circuit output signal is input to the timer n count clock The synchronizing circuit output signal is changed at the falling edge of the system clock after the TMnIO input signal is changed The binary counter counts up at the falling edge of the
275. he synchronous output signal of timer 1 2 or 7 or of the external interrupt 2 IRQ2 Buzzer output Output frequency can be selected from fosc 2 fosc 2 fosc 2 fosc 2 fosc 2 3 fosc 2 fx 2 and fx 2 Remote control output Based on the timer 0 and timer 3 output a remote control carrier with duty cycle of 1 2 or 1 3 can be output A D converter 10 bits X 4 channels Serial interface 1 type Serial 0 Duplex UART Synchronous serial interface Synchronous serial interface Transfer clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 1 2 of UART baud rate timer timers 3 output MSB LSB can be selected as the first bit to be transferred Any transfer size from 1 to 8 bits can be selected Sequence transmission reception or both are available Duplex UART Baud rate timer Timers 3 Parity check Overrun error framing error detection Transfer size 7 to 8 bits can be selected LED driver 4 pins push pull configuration LCD driver LCD driver pins Segment output 24 pins max SEGO to 23 SEGO to 15 are switchable to I O ports in unit of 2 pins SEG16 to 23 are switchable to I O ports in 1 pin unit Note At reset SEGO to 23 are input ports Common output pins 4 pins to 3 are switchable to I O ports in 1 pin unit Display mode selection static 1 2 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias 1 6 Hardware Functions Port Package Package code Chapter
276. he system using STOP mode if the STOP mode is done or not is divided on the program execution but in this case the counting value of the watchdog timer differs So the watchdog interrupt should be prevented by setting the lowest value for watchdog timer clear IX 6 Operation Chapter 9 Watchdog Timer 9 3 2 Setup Example The watchdog timer detects errors On the following example the time out period is set to 2 8 x system clock the lowest value for watchdog timer clear is set to 2 x system clock An example setup procedure with a description of each step is shown below Wilnitial Setup Program Watchdog Timer Initial Setup Example Setup Procedure Description 1 Setthe time out period 1 Setthe WDTS1 0 flags of the watchdog timer WDCTR x O3F02 control register WDCTR to 01 to select the bp2 1 WDTS1 0 01 time out period to 2 x system clock 2 Setthe lowest value for clear 2 Setthe WDTC2 0 flag of the WDCTR register WDCTR x O3F02 to 010 to select the lowest value for clear to bp5 3 WDTC2 0 010 2 x system clock 3 Start the watchdog timer operation 3 Setthe WDEN flag of the WDCTR register to WDCTR x 03F02 start the watchdog timer operation 1 setting If the watchdog control register WDCTR is changed after starting the operation the 1 The command of setting the WDEN flag to 1 should be done on the last step of the initial watchdog interrupt may be
277. igh frequency clock operation If the clock is an external input connect it to OSC1 and leave OSC2 open The chip will not operate with an external clock when using either the STOP or SLOW modes XI 14 Input Clock input pin Connect these oscillation pins to ceramic or crystal XO 15 Output Clock output pin oscillators for low frequency clock operation If the clock is an external input connect it to Xl and leave XO open The chip will not operate with an external clock when using the STOP mode If these pins are not used connect XI to Vss and leave XO open NRST 17 Input P27 Reset pin This pin resets the chip when power is turned on is Active low allocated to P27 and contains an internal pull up resistor Setting this pin low initializes the internal state of the device Thereafter setting the input to high releases the reset The hardware waits for the system clock to stabilize then processes the reset interrupt Also if 0 is written to P27 and the reset is initiated by software a low level will be output The output has an n channel open drain configuration If a capacitor is to be inserted between NRST and Vss it is recommended that a discharge diode be placed between NRST and Vpp POO 24 vO SBOO TXD VO port 0 4 bit CMOS tri state VO port 1 25 SBI0 RXD Each bit can be set individually as either an input or P02 26 SBTO output by the PODIR register A pull up resistor for each P06 27 bit can be selected individually b
278. igure 4 11 2 Synchronous Output Timing by Event Generation IRQ2 BPort 6 Synchronous Output Timer 1 Timer 2 Timer 7 The timer interrupt flag TMnIRQ is generated when the set values of binary counter and compare regis ter are matched The latched data on port 6 is output from the port 6 in synchronization with the rising edge of the TMnIRQ About the setting of each timer operation refer to chapter 6 8 bit timers and chapter 7 16 bit timers Timer count clock S NAE ees Timer compare register iis me ooog 7 m naX N X 00 X dd 51 Port 6 output Y Y latch data i i Interrupt request flag ron Output b Figure 4 11 3 Synchronous Output Timing by Event Generation Timers 1 2 and 7 IV 46 Synchronous Output Port 6 4 11 4 Setup Example Chapter 4 Ports A setup example of the port 6 synchronous output by the external interrupt 2 IRQ2 is shown as follows As it is operated the initial output data of port 6 is 55 the synchronous output data is AA and the rising edge of the IRQ2 is selected at the synchronous event An example setup procedure with description of each step is shown below Setup Procedure Description Select the synchronous output event FLOAT x 3F2E bp1 0 SYOEVS1 0 00 Specify the interrupt edge IRQ2ICR x SFE4 bp5 REDG2 1 EDGDT x 3F8F bp2 EDGSEL2 0 Set the initial output data P6OUT x 3F16
279. imer 0 Timer 2 TMOIO output pin TM2IO output pin PWM output pin P10 P12 iCount Timing of PWM Output at Normal Timers 0 and 2 TMnEN flag Compare register counter PWM source wave form A B TMnIO output PWM output um gt Time set in the compare register PWM basic components overflow time of binary counter Figure 6 6 1 Count Timing of PWM Output at Normal PWM source waveform A is while counting up from 00 to the value stored in the compare register B is L after the match to the value in the compare register then the binary counter continues counting up till the overflow C is again if the binary counter is overflown The PWM outputs PWM source waveform with 1 count clock delay because the waveform is cre ated inside to correct the output cycle VI 26 8 bit PWM Output iCount Timing of PWM Output when the compare register is x 00 Timers 0 and 2 Here is the count timing when the compare register is set to x 00 TMnEN flag Compare register 00 H TMnIO output PWM output L Chapter 6 8 bit Timers counter Figure 6 6 2 Count Timing of PWM Output when compare register is x 00 When TMnEN flag is stopped 0 PWM output is H iCount Timing of PWM Output when the compare register is x FF Timers 0 and 2 Here is the count timing when the compare register is set to x FF T
280. imer 7 preset register 1 TM7PH1 To set 100 kHz by dividing 20 MHz set as follows 200 1 199 xC7 The same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter TM7BC is initialized to x 0000 7 Release the reset of the timer pulse 7 Setthe TN7CL flag of the TM7MD1 register to output 0 to enable the timer pulse output TM7MD 1 x 3F78 bp5 TM7CL 0 8 Start the timer operation 8 Setthe TM7EN flag of the TM7MD1 register to TM7MD 1 x 3F78 1 to start timer 7 bp4 TM7EN 1 TM7BC counts up from x 0000 If TM7BC reaches the set value of the TM7OC1 register and TM7BC is cleared to x 0000 the signal of the TM7IO output is inverted and TM7BC counts up from x 0000 again To output the timer pulse output from the TM7O large current pin set the PSOMD1 flag of the port 5 output mode register PSOMD to 1 at the setup example 2 to set the P51 pin as a special function pin and set the P5DIR1 flag of the port 5 direction control register to 1 to set output mode 4 At TMnOC1 x 0000 and x 0001 the timer pulse output have the same waveform when the TMnCL flag of the TMnMD1 register is set to 1 Regardless of whether the binary counter is stopped or operated the timer output is L Compare register value calculation Timer pulse output cycle u 4 Compareragister value Selected clock cycle x 2
281. iming of the rising edge of the external interrupt 0 input signal the value of TM7BC is loaded to the register At that time the pulse width between rising edge of the external interrupt input signal can be measured by reading the value of TM7IC register through interrupt service routine and calculating the difference between the capture values 16 bit Timer Capture VII 43 16 bit Timers Chapter 7 16 bit Timers 7 10 Cascade Connection 7 10 1 Operation Cascading timers 7 and 8 forms a 32 bit timer 16 bit Timer Cascade Connection Operation Timer 7 Timer 8 Timer 7 and timer 8 are combined to be a 32 bit timer Cascading timer is operated at clock source of timer 7 which are lower 16 bits Table 7 13 1 Timer Functions at Cascade Connection Timer 7 Timer 8 32 bit Interrupt source TM8IRQ Timer operation Event count input Timer pulse output 8 output PWM output Synchronous output Capture function y Pulse width measurement fosc fosc 2 fosc 4 fosc 16 fs fs 2 Clock source fs 4 fs 16 TM7IO input input 2 input 4 TM7IO input 16 fosc Machine clock High frequency oscillation fs System clock 4 Chapter 2 2 5 Clock Switching VII 44 Cascade Connection 7 16 bit Timers At cascade connection the binary counter and the compare register are operated as a 32 bit register At oper
282. in Clock VO pin Setup item SBT pin SBO pin SBI pin Internal clock External clock Port pin Poo 1 2 SBI SBO independent SBI SBO pin 2 SCOMD1 SCOIOM Serial data output Serial data input Serial clock VO Serial clock VO Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Push pull Push pull Push pull Style Nch open drain Nch open drain Nch open drain SC0ODC SC0ODC0 SC0ODC SC0ODC1 Output mode Input mode Output mode VO PODIR PODIRO PODIR PODIR1 PODIR PODIR2 Added Not added Added Not added Added Not added Pull up POPLU POPLUO POPLU POPLU2 Operation 25 Chapter 11 Serial Interface 0 WPins Setup with 2 channels at transmission Table 11 3 9 shows the setup for synchronous serial interface pin with 2 channels SBO pin SBT pin at transmission SBI pin can be used as a port Table 11 3 9 Setup for Synchronous Serial Interface Pin with 2 channels at transmission Data output pin Clock VO pin Setup item SBT pin SBO pin SBI pin Internal clock External clock Port pin 2 SBVSBO connected SBI SBO SCOMD1 SCOIOM Serial data output 1 input Serial clock VO Serial clock VO Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Push pull Push pull Push pull Style Nch open drain _ Nch open drain Nch open drain SC0ODC SC0ODC0 SC0ODC SC0ODC1 Output mode Output mode Input mode
283. ing values Sample hold time At 800 ns Impedance of analog signal output circuit TaD x 2 1 6 us R lt 1 6 us 10 pF 3 53 TAD x 6 4 8 us R 4 8 us 10 pF 3 160 TAD x 18 14 4 us R lt 14 4 us 10 pF 3 480 External analg signal output circuit block Microcontroller start verter should be strictly kept 1 Input impedance R of A D input pin should be under 500 And connect the external capacitor C over 1000 pF under 1 uF between Vss and the A D input pin 2 Setthe A D conversion frequency depending on the time constant of R and C 3 Changing the output level of the microcontroller or switching ON OFF of the periph eral added circuit while the A D conversion is in progress may lower the precision of A D conversion for these may fluctuate the values of the analog input pin and the power pin Check the waveform of the analog input pin before the system evaluation a To maintain high precision of A D conversion following instructions on use of A D con Equivalent circuit block that outputs analog signal microcontroller R NW A D input pin ILE 1 55 w S eae 1 gt gt 1000 pF 1 as R lt 500 1 That value is for reference Recommended Connection with A D Converter Operation XIII 15 Chapter 13 LCD Chapter 13 LCD Functions 13 1 Functions This LSI
284. interrupts are normally processed in decreasing order of priority It is however possible to alter this arrangement 1 To disable interrupt nesting Reset the MIE bit in the PSW to 0 Raise the priority level of the interrupt mask IM in the PSW 2 To enable interrupts with lower priority than the currently accepted interrupt Lower the priority level of the interrupt mask IM in the PSW Multiplex interrupts are only enabled for interrupts with levels higher than the PSW interrupt mask level IM It is possible to forcibly rewrite IM to accept an interrupt with a priority lower than the interrupt being processed but be careful of stack overflow Do not operate the maskable interrupt control register xxxICR when multiple interrupts are enabled If operation is necessary first clear the PSW MIE flag an x 12 Overview Chapter 3 Interrupts Figure 3 1 7 shows the processing flow for multiple interrupts interrupt 1 xxxLV1 xxxLV0z 10 and interrupt 2 xxxLV1 xxxLV0 00 1 0 11 Interrupt 1 generated zw Accepted because IL lt IM xxxLV1 0 10 IM1 0 1 0 rterupt acceptance Interrupt service routine 1 Interrupt 2 generated 2 gt Accepted because IL IM 1 0 00 acceptance cycle 1m1 0 00 Interrupt service routine 2 p Restart interrupt processing pr
285. ion Machine Code 6 7 8 MOVW imm16 Am imm16 gt Am 6 3 111a H6 MOVW SP Am 5 3 3 100a MOVW An SP An SP 3 83 101A MOVW DWn DWm DWn DWm 3 3 00Dd MOVW DWn Am DWnAm 8 8 11Da MOVW An DWm An gt DWm 3 11Ad MOVW An Am 3 3 00 PUSH SP 1 SP Dn mem8 SP 2 3 10Dn PUSH An SP 22SP Anmemt16 SP 215 011A POP Dn 8 5 gt 5 1 gt 5 2 3 10Dn POP An 16 5 gt 5 2 gt 5 2 4 011A EXT Dn DWm sign Dn BDWm 3 3 000d Arithmetic manupulation instructions ADD ADD Dn Dm Dm Dn Dm e eee 3 2 0011 0011 DnDm ADD imm4 Dm Dm sign imm4 gt Dm 2 1000 00Dm lt 4 gt 6 ADD imm8 Dm Dm imm8 Dm o ooo 4 2 0000 10Dm lt 8 gt ADDG ADDC Dn Dm Dm Dn CF Dm 3 O 0011 1011 ADDW ADDW DWn DWm DWm DWn DWm e 3 3 O 0010 0101 5 ADDW DWn Am Am DWn Am ee e e 3 3 0010 0101 10Da ADDW imm4 Am Am sign imm4 5Am 2 1110 110 lt 4 gt 6 ADDW imm8 Am Am sign imm8 gt Am 5 3 0010 1110 110a lt 8 gt T ADDW imm16 Am Am imm16 gt Am 7 4 0010 0101 011a lt 16 gt ADDW 4 5 SP sign imm4 SP 3 2 1111 1101 lt 4 gt 6 ADDW imm8 SP SP sign imm8 SP 4 2 1111 1100 lt 8 gt gi ADDW imm16 SP SP imm16 SP 714 0010 1111 1100 H6 Am ADDW imm16 DWm DWm imm16 DWm 4 0010 0101 0104 lt 16 gt ADDUW ADDUW Dn Am Am zero Dn gt Am e 3 3 0010 1000 1aD
286. is 0 the remote control carrier pulse signal output is stopped Remote Control Carrier Output VI 47 7 16 bit Timers 7 16 bit Timers 7 1 Overview This LSI contains two general purpose 16 bit timers Timer 7 Timer 8 The timer 7 is high efficiency 16 bit timer and the timer 8 is standard 16 bit timer The high efficiency 16 bit timer is the timer counter extended from standard 16 bit timer and is upwardly compatible with standard 16 bit timer The 16 bit timer has compare register with double buffer High precision 16 bit timer has 2 sets of compare regis ters with double buffering 7 1 1 Functions Table 7 1 1 shows the functions of timer 7 and timer 8 Table 7 1 1 16 bit Timer Functions Timer 7 Timer 8 High precision 16 bit timer Standard 16 bit timer Interrupt source TM7IRQ1 TM7IRQ2 TM8IRQ1 Timer operation Y Y Event count y N Timer pulse output Y PWM output duty is variable y Y High precision PWM output duty and cycle are 4 _ variable Synchronous output Y Capture function V Pulse width measurement 32 bit cascade connection Timer cycle Event count Standard PWM output High precision PWM output capture fosc fosc fosc 2 fosc 2 fosc 4 fosc 4 fosc 16 fosc 16 fs fs fs 2 fs 2 Clock source 15 4 5 4 15 16 15 16 TM7IO input TM8IO input TM7IO input 2 TM8IO input 2 input 4 TMBIO input 4 TM7IO inpu
287. ister 2 TM7OC2 with its double buffer preset register 2 TM7PR2 and the input capture register TM7IC The mode register 1 TM7MD1 the mode register 2 TM7MD2 and control timer 7 Timer 8 contains the binary counter TM8BC the compare register 1 TM8OC1 with its double buffer preset register 1 TM8PR1 and the input capture register TM8IC The mode register 1 TM8MD1 the mode register 2 TM8MD2 and control timer 8 7 2 1 Registers Table 7 2 1 shows the registers that control timer 7 Table 7 2 1 16 bit Timer Control Registers Register Address R W Function Page TM7BCL X 03F70 7 binary counter lower 8 bits VII 8 TM7BCH X 03F71 R Timer 7 binary counter upper 8 bits VII 8 TM7OC1L X 03F72 R Timer 7 compare register 1 lower 8 bits VII 6 7 X 03F73 R 7 compare register 1 upper 8 bits VII 6 TM7PR1IL X 03F74 Timer 7 preset register 1 lower 8 bits VII 7 TM7PR1H X OSF75 RAN Timer 7 presets register 1 upper 8 bits VII 7 TM7ICL X 03F76 R Timer 7 capture register lower 8 bits VII 9 TM7ICH X 03F77 R Timer 7 capture register upper 8 bits VII 9 TM7MD1 X 03F78 R W Timer 7 mode register 1 VII 10 TM7MD2 X 03F79 R W Timer 7 mode register 2 VII 11 TM7OC2L X O3F7A R Timer 7 compare register 2 lower 8 bits VII 6 7 2 X
288. ister VI 11 ras CK1MD x 03F57 R W Timer 1 prescaler selection register V 7 PSCMD x 03F6F R W Prescaler control register V 6 TM1ICR RW Timer 1 interrupt control register IIl 22 P1OMD xO3F2F R W 1 output mode register 12 P1DIR x 03F31 R W Port 1 direction control register 11 2 x 03F58 R Timer 2 binary counter VI 9 2 x 03F5A RAW Timer 2 compare register VI 8 TM2MD XO3F5C R W Timer 2 mode register VI 12 CK2MD x 03F5E R W Timer 2 prescaler selection register V 8 PSCMD x 03F6F R W Prescaler control register V 6 TM2ICR RAN Timer 2 interrupt control register IIl 23 P1OMD xO3F2F R W 1 output mode register 12 P1DIR x 03F31 RW Port 1 direction control register 11 VI 6 Control Registers Chapter 6 8 bit Timers Register Address Function Page TM3BC x 03F59 Timer 3 binary counter VI 9 TM3OG x 03F5B Timer 3 compare register VI 8 TM3MD x 03F5D Timer 3 mode register VI 13 macs CK3MD x 03F5F Timer 3 prescaler selection register V 8 PSCMD x 03F6F Prescaler control register V 6 Timer 3 interrupt control register Ill 24 P10MD x 03F2F Port 1 output mode register 12 P1DIR x 03F31 Port 1 direction control register IV 11 Remote control RMCTR Remote control carrier output control register VI 14
289. istor ilSpecial Function Pin Setup P20 and P22 are used as external interrupt pins as well P21 is used as an input pin for external interrupt and AC zero cross To read data of AC zero cross set 1 to the bp7 of the noise filter control register NFCTR and read the value of the port 2 input register P2IN IV 14 2 Chapter 4 Ports 4 4 2 Registers P2OUT P20UT7 Atreset 1 2 Output data 0 Low Vss level is output 1 High level is output Port 2 output register P2OUT x 03F12 R W 7 6 5 4 3 2 1 0 2 21 7 P2IN2 P2IN1 P2INO Atreset 1 XXX 2 Input data 0 Pin is Low Vss level 1 Pin is High Vpp level Port 2 input register P2IN x 03F22 R 7 6 5 4 3 2 1 0 P2PLU P2PLU2 P2PLU1 P2PLUO At reset 000 P2PLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 2 pull up resistor control register P2PLU x 03F42 RAW Figure 4 4 1 Port 2 Registers Pot2 15 Chapter 4 Ports 4 4 3 Block Diagram ae Reset Pull up resistor control Dd P2PLUO 2 D gt Wr
290. ite CK N A Read a gt AXX P20 P22 21 0 2 N Read Schmitt trigger input External interrupt Figure 4 4 2 Block Diagram P20 and P22 FNG Hese 5 Pull up resistor control Do UT D Write Read E 5 Ij n t gt P21 M 1 AC zero cross P2IN1 U detection circuit Port input data 0 NJ B X A Schmitt trigger input NFCTR register bp7 AC zero cross input External intrerrupt Figure 4 4 3 Block Diagram P21 777 pS Reset T 3 L1 P20UT7 Port output data DQ lt Write N E Read 7 7 F t X P27 Port input data P2IN7 4 Schmitt trigger input N Reset Figure 4 4 4 Block Diagram P27 IV 16 Port2 Chapter 4 Ports 4 5 Port 3 4 5 1 Description Port Setup Each bit can be set individually as either an input or output by the port 3 I O direction control register P3DIR The control flag of the port direction control register P3DIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port direction control register PSDIR to 0 and read the value of the port 3 input register To output data to pin set the control flag of the port 3 direction control register P3DIR to 1 and write data to the port 3 output register PSOUT Each bit can be set individually if pull up resistor is added or not by the port 3 pull up resistor control regist
291. l if mem8 abs8 bp 1 PC 8 d1 1 label H PC O 0 8 6 7 0011 0001 1bp abs 8 dii 2 8 8 0 8 2 io8 bp label if mem8 io bp 1 PC 7 d7 label H PC O 0 7 6 7 0011 0101 lt 08 gt lt d7 4 if mem8 io bp 0 PC 73PC TBNZ io8 bp label if mema io bpzt PC 8 dtt labeeHGPC O e 8 6 7 0011 0101 1bp lt 8 gt dii 12 iflmem8 io bp 0 PC 82PC TBNZ abs16 bp label if mem8 abst6 bp 1 PC 9 d7 abe HHOPC e 0 e 9 7 8 0011 1111 abs 16 gt lt 7 4 if mem8 abs16 bp 0 PC 9 PC TBNZ abs16 bp label _f mem8 abs16 bp 1 PC 10 d1 Iabel H PC O o 10 7 8 0011 1111 1bp abs 16 gt dii if mem8 abs16 bp 0 PC 102PC JMP JMP An 02PC 17 16An2PC 15 02PC H 3 4 0010 0001 00A0 JMP label abs18 label H3PC 7 5 0011 1001 OaaH abs 18 6 15 0 gt 5 JSR JSR An SP 3 9SP PC 3 bp7 0 gt mem8 SP 3 7 0010 0001 00 1 PC 3 bp15 8 mem8 SP 1 PC 3 H mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 3 bp17 16 smems8 SP 2 bp1 0 05PC bp17 16 An PC bp15 0 0 PC H JSR label SP 3 9SP PC 5 bp7 0 gt mem8 SP 5 6 0001 OOOH lt di2 gt 3 PC45 bp15 82mem8 SP 1 5 5 2 7 0 mem8 SP 2 bp6 2 5 0 17 16 8 5 2 0 1 0 PC 5 d12 label H3PC JSR label SP 3 9SP PC 6 bp7 0 gt mem8 SP
292. l interrupt 2 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 7 6 5 1 0 IRQ2 IRQ2 IRQ2ICR LVI LVO REDG2 IRQ2IEIRQ2IR reset 000 0 0 IRQ2IR External interrupt request flag 0 No interrupt request Generate interrupt request IRQ2IE External interrupt enable flag 0 Disable interrupt Enable interrupt REDG2 External interrupt valid edge flag 0 Falling edge 1 Rising edge IRQ2 IRQ2 LV1 LVO Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests Figure 3 2 4 External Interrupt 2 Control Register IRQ2ICR x 03FE4 R W 20 Control Registers Chapter 3 Interrupts mExternal Interrupt 4 Control Register IRQ4ICR The external interrupt 4 control register IRQ4ICR controls interrupt level of external interrupt 4 valid edge interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 IRQ4 IRQ4 IRQ4ICR Lyo REDG4 lRosie Roain At reset 000 00 IRQ4IR External interrupt request flag 0 No interrupt request Generate interrupt req
293. lay panel with the ad Segment output latch SEG1 0 dress X 2E00 to X 2E03 of the segment out 2 00 00 put latch SEGO 7 Segment output latch SEG3 2 Chapter 14 14 4 1 the LCD display 2 01 X11 example static Segment output latch SEG5 4 X2E02 X 10 Segment output latch SEG7 6 X2bE03 X 11 6 Start the LCD operation 6 Set 1 to the LCDEN flag of the LCD mode LCMD1 X 3FD9 control register LCMD1 to start the LCD bp7 LCDEN 1 operation XIII 26 Display Chapter 13 LCD Functions Display 27 Chapter 13 LCD Functions 13 4 3 1 2 duty m1 2 Duty MN101C527 Segment Latch X 2EOB s X 2E03 X 2E03 X 2E02 X 2E02 X 2E01 X 2E01 X 2E00 2 00 bit7 bit3 open bit6 bit2 open bit5 bit1 bit4 bit0 A electrode B electrode l not iit LCD PANEL LCD ON COM S COM N COM S COM N LCD OFF SEG S SEG S SEG N SEG N LCD clock undefined Data 4 0 undefined Vict COM Vic2 Vic3 Vss Vict SEG Vic2 Vics Vss Vico 1 2 COM SEG 0 1 2 Vicb Lit Not lit Not lit Not lit Not lit S selective voltage N non selective voltage LCD driver voltage XIII 28 Display Chapter 13 LCD Functions frame cycle COM1 Vic2 Vic3 Vicp Vss Vici COMO Vicez Vica x
294. le 11 3 21 UART Serial Interface Pin Setup with 1 channel at reception Data output pin Data input pin Setup item TXD pin RXD pin Port pin P00 P01 TXD RXD pins connected TXD RXD pin SCOMD1 SCOIOM Port Serial data input Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Input mode VO PODIR PODIRO Pull up x Setup with 2 channels at transmission reception Table 11 3 22 shows the pin setup at UART serial interface transmission reception with 2 channels TXD pin RXD pin Serial Interface 0 Table 11 3 22 UART Serial Interface Pin Setup with 2 channels at transmission reception Setup item Data output pin Data input pin TXD pin RXD pin Port pin 1 TXD RXD pins TDX RXD pins independent SCOMD1 Serial data output SCOIOM Serial data input Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS Push pull Style Nch open drain SC0ODC SC0ODC0 Output mode Input mode VO PODIR P0DIR0 PODIR PODIR1 Added Not added Pull up POPLU POPLUO Operation XI 43 Chapter 11 Serial Interface 0 11 3 4 Setup Example Transmission Reception Setup The setup example at UART transmission reception with serial 0 is shown Table 11 3 23 shows the conditions at transmission reception Table 11 3 23 UART Interface Transmision Reception Setup Setup item set to TXD RXD pin in
295. le 11 3 5 Other Control Flag Register Flag Detail SCOBRKF Brake status reception monitor SCONPE Parity is enabled SCOMD2 SCOPM1 to 0 Added bit specification SCOFM to 0 Frame mode specification SCOPEK Parity error detection SCOMD3 SCOFEF Frame error detection 18 Operation Chapter11 Serial Interface 0 Timing at master at slave Tmax 25T T Tmax 2 T Clock SBT pin Output pin SBO pin Transfer bit counter SCOTBSY Set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 5 Transmission Timing at falling edge start condition is enabled at master at slave 157 2 SBT Output 5 Transfer bit counter SCOTBSY Set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 6 Transmission Timing at falling edge start condition is disabled Operation XI 19 Chapter 11 Serial Interface 0 at master at slave 25 T Tmax 2T I Clock SBT pin Output pin SBO pin Transfer bit counter SCOTBSY i Set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 7 Transmission Timing at rising edge start condition is enabled at master at slave Tmax 1 5T T A 2 SBO Transfer bit c
296. ll down resistor selection register FLOAT select if pull up resistor or pull down resistor is added The bp6 of the pull up pull down resistor control register FLOAT is set to 1 for pull down resistor set to 0 for pull up resistor Special Function Pin Setup PAO to PAS are used as input pins for analog Each bit can be set individually as an input by the port A input mode register PAIMD When they are used as analog input pins set the port A input mode register PAIMD to 1 Then the value of the port A input register PAIN is read to be 1 1 setting the control flag of the PAIMD register to 1 the through current is not occurred when an analog voltage is set to pin PotA IV 39 Chapter 4 I O Ports 4 10 2 Registers 7 6 5 4 3 2 1 0 PAIN PAIN2 PAIN1 At reset X X X X PAIN Input data 0 Pin is Low Vss level 1 Pin is High Vpp level Port A input register PAIN X OSF2A R 7 6 5 4 3 2 1 0 PAIMD PAIMD3PAIMD2PAIMD1 PAIMDO At reset 0000 port PAIMD analog n input pin selection 0 port 1 Analog n input pin Port A input control register PAIMD X OSF3A R W 7 6 5 4 3 2 1 0 PAPLUD PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO At reset 000 0 Pull up pull dow
297. lock can be switched in each mode ROM 16 KB RAM 1 5 KB 13 Internal interrupts lt Non maskable interrupt NMI gt Incorrect code execution interrupt lt Timer interrupts gt Timer 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 6 interrupt Time base interrupt Timer 7 interrupt Match interrupt for Timer 7 compare register 2 Timer 8 interrupt Hardware Functions 1 3 Chapter 1 Overview lt Serial interrupts gt Serial 0 interrupt 1 Serial 0 interrupt 2 lt A D interrupt gt A D conversion interrupt 4 External interrupts IRQO Edge selectable With without noise filter IRQ1 Edge selectable With without noise filter AC zero cross detector IRQ2 Edge selectable Both edges interrupt STOP HALT can be recovered at the both edges IRQ4 Key interrupt only Timers Counters 9 timers 8 be operated independently 8 bit timer for general use 4 sets 8 bit timer used as UART baud rate timer as well 1 set 8 bit free running timer 1 set Time base timer 1 set 16 bit timer for general use 2 sets Timer 0 8 bit timer for general use Square wave output Timer pulse output PWM output Event count Remote control carrier output Simple pulse width measurement Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock Square wave output and PWM output can be output to large current drive
298. low C shows H again if the binary counter overflow The PWM output form pin is 1 count clock delay of PWM source waveform This is happened to form waveform inside the microcontroller to correct the output cycle VII 28 16 bit Standard PWM Output 7 16 bit Timers mCount Timing of Standard PWM Output when Compare Register 1 is x 0000 Timer 7 Timer 8 Here is the count timing at setting x 0000 to the compare register 1 TMnEN flag Compare regsiter 1 Binary Iy IN soa 2 2 H TMnIO output PWM output L Figure 7 6 2 Count Timing of Standard PWM Output when Compare Register 1 is x 0000 10000 PWM output shows when TMnEN flag is stopped at 0 iCount Timing of Standard PWM Output when Compare Register 1 is x FFFF Timer 7 Timer 8 Here is the count timing at setting to the compare register 1 flag Compare register 1 Binary I N 33Y N YN VY N24 4 0000 2055 Frrejrrrr oooo TMnIO output ccc 1877 5 PWM output Figure 7 6 3 Count Timing of Standard PWM Output when Compare Register 1 is X FFFF iFFFF To output the standard PWM output set the TMnBCR flag of the 2 register to 0 to select the full count overflow as the binary counter clear source and the PWM output set H output source The TM7OC1 compare match or the TM7OC2 compare match can be selecte
299. lways 0 Figure 3 3 5 Both Edges Interrupt Control Register EDGDT x 03F8F R W HI 40 External Interrupts Chapter 3 Interrupts Port 6 Key Interrupt Control Register P6IMD The port 6 key interrupt control register P6IMD selects if key interrupt is accepted Also this register assigns port6 pin to key interrupt in 1 bit unit 7 6 5 4 3 2 1 0 P6IMD _ 7 2 PGKYEN1 PEKYENO Atreset 00 00 0000 PekvENo 60 key interrupt selection 0 disable 1 enable P61 key interrupt P6KYEN1 selection 0 disable 1 enable PeKYEN P62 key interrupt selection 0 disable enable P63 key interrupt P6KYEN3 selection 0 disable enable P6KYEN4 0 disable 1 enable i 0 disable 1 enable 0 disable enable UG ern 0 disable 1 enable Figure 3 3 6 Port 6 Key Interrupt Control Register P6IMD x 03F3E R W External Interrupts 41 Chapter3 Interrupts 3 3 4 Programmable Active Edge Interrupt iProgrammable Active Edge Interrupts External interrupts 0 to 2 Through register settings external interrupts 0 to 2 are generated at either the rising or falling edge of the IRQ input signal And this function can generate
300. m Capture 1 trigger Capture 000 MEUM 0114 5558 register Figure 7 9 1 Capture Count Timing as an External Interrupt Signal is selected as a Trigger Timer 7 Timer 8 A capture trigger is generated at the both edges of the external interrupt m input signal In synchronized with this capture trigger the value of binary counter is loaded to the input capture register The value loaded to the capture register is depending on the value of a binary counter at the falling edge of a capture trigger When the specified edge is selected as a capture trigger source a capture trigger is generated only at that edge The other count timing is same as the count timing of the timer operation e When the binary counter is used as a free counter which counts x 0000 to x FFFF set the compare register 1 to x FFFF or set the TMnBCR flag of the TM7MD2 to 0 Even if an event is generated before the value of the input capture register is read out the value of the input capture register can be rewritten k signal is disabled Set the TnICEN flag of the TMnMD2 register to 1 to enable the trigger generation In the initial state after releasing the reset the generation of trigger by the external interrupt 40 16 bit Timer Capture 7 16 bit Timers mCapture Operation triggered by writing software Timer 7 Timer 8 A capture trigger can be generated by writing an ar
301. m square 0 8 mm pitch LQFP064 P 1414 Hardware Functions 1 7 Chapter 1 Overview 1 3 1 3 1 TMOO TM70 20 TM8O Pin Description Pin Configuration Vict Vicine Vice Vicins Vic3 C1 C2 LEDO P50 LED1 P51 LED2 P52 LED3 P53 Pin Description COMS P33 COM2 P32 COM1 P31 COMO P30 1 2 3 4 5 6 7 8 9 1 1 NRST P27 Vref AN1 PA1 AN2 PA2 Figure 1 3 1 SEGO P87 SEG1 P86 SEG2 P85 SEG3 P84 SEG4 P83 SEG5 P82 SEG6 P81 SEG7 P80 SEG8 P77 SEG9 P76 SEG10 P75 SEG11 P74 MN101C527 LCD version Vref TXD SBOO P00 SBTO P02 BUZZER P06 RMOUT TMOIO P10 TM110 P11 TM2IO P12 13 TM7IO P14 RXD SBIO P01 Pin Configuration 64LQFP Top view SEG12 P73 SEG13 P72 SEG14 P71 SEG15 P70 SEG16 KEY7 P67 SDO7 SEG17 KEY6 P66 SDO6 SEG18 KEY5 P65 SDO5 SEG19 KEY4 P64 SDO04 SEG20 KEYS3 P63 SDO3 SEG21 KEY2 P62 SDO2 SEG22 KEY1 P61 SDO1 SEG23 KEYO P60 SDOO P22 IRQ2 P21 IRQ1 ACZ P20 IRQO P15 TM8lIO Chapter 1 Overview 1 3 2 Pin Specification Table 1 3 1 Direction Pin 7 Descr n Control Control Functions Descroptio POPLUO SBOO Serial 0 transmission data output UART transmission data output POPLU1 SBIO Serial 0 reception data input RXD UART reception data input POPLU2 SBTO Serial 0 clock input output Pin Specification Special Funcion VO in out PODIRO in out PODIR1 in out PODIR2
302. mer 0 output TM7O Timer 7 output TM2O Timer 2 output 8 Timer 8 output KEYO KEY interrupt input 0 KEY1 KEY interrupt input 1 KEY2 KEY interrupt input 2 KEY interrupt input 3 4 KEY interrupt input 4 KEY interrupt input 5 KEY6 KEY interrupt input 6 KEY7 KEY interrupt input 7 LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output ANO Analog 0 input 1 Analog 1 input AN2 Analog 2 input AN3 Analog 3 input RMOUT Remoto control carrier output ACZ Zero cross input LEDO LED driver pin LED1 LED driver pin LED2 LED driver pin LED3 LED driver pin LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output LCD segment output Pin Description 1 9 Chapter 1 Overview 1 3 3 Pin Functions Table 1 3 2 Pin Function Summary 1 6 Name No VO Other Function Function Description Vss 10 Power supply Supply 2 0 V to 5 5 V to Vpp and 0 V to Vss VDD 16 OSC1 12 Input Clock input pin Connect these oscillation pins to ceramic or crystal OSC2 11 Output Clock output pin oscillators for h
303. mer 2 interrupt control register Timer 2 compare match Ill 24 TM3ICR XO3FEC RW Timer 3 interrupt control register Timer compare match IIl 25 TM6ICR R W Timer 6 interrupt control register Timer 6 compare match IIl 26 TBICR x 03FF0 R W Time base interrupt control register Time base period III 27 TM7ICR X03FF1 R W Timer 7 interrupt control register Timer 7 compare match IIl 28 2 x 03FF2 R W Timer 7 compare register 2 match interrupt control register III 29 TM8ICR x 03FF3 R W Timer 8 interrupt control register Timer 8 compare match IIl 30 SCORICR x 03FF5 R W Serial 0 nterrupt control register 1 31 SCOTICR xOSFFe R W Serial 0 interrupt control register 2 Ill 32 ADICR X 03FFA R W A D conversion interrupt control register A D conversion complete Ill 33 Writing to the interrupt control register should be done after that all maskable interrupts set to be disable by the MIE flag of the PSW register If the interrupt level flag xxxLVn is set to level 3 its vector is disabled regardless of interrupt enable flag and interrupt request flag Control Registers III 15 Chapter3 Interrupts 3 2 2 Interrupt Control Registers The interrupt control registers include the non maskable interrupt control register NMICR the external interrupt control register and the internal interrupt control registers xxxICR mNon
304. mers 6 10 Cascade Connection 6 10 1 Operation Cascading timers 0 and 1 or timer 2 and 3 forms a 16 bit timer B8 bit Timer Cascade Connection Operation Timer 0 Timer 1 Timer 2 Timer 3 Timer 0 and timer 1 or timer 2 and timer 3 are combined to be a 16 bit timer Cascading timer is operated at clock source of timer 0 or timer 2 which are lower 8 bits Table 6 10 1 Timer Functions at Cascade Connection Timer 0 Timer 1 Timer 2 Timer 3 16 bit 16 bit Interrupt source TM1IRQ operation Event count TMOIO input 2 input Timer pulse output TM11O output TMSIO output PWM output Synchronous output Serial transfer clock output eh O Pulse width measurement Remote control carrier y output fosc fosc fosc 4 fosc 4 fosc 16 fosc 16 fosc 32 fosc 32 Clock source fosc 64 fosc 64 fs 2 fs 2 fs 4 fs 4 fx fx input 2 input fosc Machine clock High frequency oscillation fx Machine clock Low frequency oscillation fs System clock g Chapter 2 2 5 Clock Switching Cascade Connection VI 41 Chapter 6 8 bit Timers At cascade connection the binary counter and the compare register are operated as a 16 bit regis ter At operation set the TMnEN flag of the upper and lower 8 bit timers to 1 to be operated Also select the clock source by the lower 8 bit timer Other setup and count timi
305. mon space External bus Address 18 bit max Data 8 bit Minimum bus cycle 1 clock 100 ns Interrupt Vector interrupt 3 interrupt levels Low power STOP mode dissipation mode HALT mode H 2 Overview 2 1 1 2 Basic CPU Data registers D0 Processor status word Source oscillation Address registers D1 PSW T2 generator Stack pointer D2 SP A1 D3 ry Instruction execution ABUS controller BBUS Program counter nstruction decoder Incrementer N Z Instruction Interrupt queue controller 1 Program address Operand address Interrupt bus 1 1 Bus controller ry 1 bus bus gt Y External interface Intemal peripheral Internal ROM Internal RAM i i functions Extemal expansion ie Uses clock oscillator circuit driven by external crystal ceramic oscillator to supply clock signals to CPU blocks Program counter Generates addresses for the instructions to be inserted into the instruction queue Normally incremented by sequencer indication but may be set to branch destination address or ALU operation result when branch instructions or interrupts occur
306. n 0 Normal timer operation 1 Cascade connection Figure 6 2 12 Timer 3 Mode Register TM3MD x 03F5D R W Control Registers VI 13 Chapter 6 8 bit Timers mRemote Control Carrier Output Control Register RMCTR 7 6 5 4 3 2 1 0 RMCTR TMORM RMDTYO RMBTMS Atreset 00 00 Remote control carrier base RMBTMS timer selection 0 Timer 0 output selection 1 Timer 3 output selection Remote control carrier output RMDTYO duty selection 0 1 2 duty 1 1 3 Enable remote control carrier output 0 Output low level 1 Output remote control carrier TMORM P10 special function output selection 0 TMOIO 1 RMOUT Figure 6 2 13 Remote Control Carrier Output Control Register RMCTR x 03F6E R W VI 14 ContolRegisters Operation Operation m8 bit Timer Operation Timers 0 1 2 and 3 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register TMnOC in advance If the binary counter TMnBC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from 00 Table 6 3 1 shows clock source that can be selected by timer The timer operation can constantly generate interrupts Chapt
307. n 8 ADDSW ADDSW Dn Am Am sign Dn gt Am ee ee 3 3 O 0010 1001 1aDn SUB SUB Dn Dm when DnzDm 2 000 1010 SUB Dn Dn Dn Dn Dn 0 0 0111 2 1 1000 01Dn SUB imm8 Dm Dm imm8 Dm 3 0010 1010DmDm lt 8 gt SUBC SUBC Dn Dm Dm Dn CF gt Dm e ee 3 O 0010 1011 SUBW SUBW DWn DWm DWm DWnDWm 3 0010 0100 00Dd i SUBW DWn Am Am DWn gt Am 3 0010 0100 10Da SUBW imm16 DWm DWm imm16 DWm 4 0010 0100 010d lt 16 gt SUBW imm16 Am 16 gt 7 4 0010 0100 011 lt 16 gt MULU MULU Dn Dm Dm Dn DWk 01 8 0010 1111 1110 4 DIVU DIVU Dn DWm DWm Dn DWm DWm h 9 0010 1110 1114 5 CMP CMP Dn Dm Dm Dn PSW eee 532 0011 0010 DnDm CMP imm8 Dm Dm imm8 PSW e eee 1 2 1100 00Dm lt 8 gt imm8 abs8 mem8 abs8 imm8 PSW e ojo 6 3 0000 0100 abs 8 gt lt 8 gt CMP imm8 abs12 mem8 abs12 imm8 PSW 7 3 0000 0101 abs 12 gt lt 8 gt CMP imm8 abs16 memg8 abs16 imm8 PSW 9 5 0011 1101 1000 lt abs 16 gt lt 8 gt CMPW DWn DWm DWm DWn PSW 3 0010 1000 01Dd 4 CMPW DWn Am Am DWn PSW 0010 0101 11Da CMPW Am An PSW 3 0010 0000 01 2 CMPW imm16 DWm DWm imm16 PSW o ojo 3 1100 110d lt 16 e CMPW imm16 Am Am imm16 PSW 3 1101 110 lt 16 Logical manipulation i
308. n KEY1 38 P61 SEG22 SDO1 pins inputs KEY2 39 P62 SEG21 SDO2 Key input pin by 1 bit can be selected individually by 40 P63 SEG20 SDO3 the key interrupt control register P6IMD KEYA 41 P64 SEG19 SDO4 When not used as KEY input these can be used as KEYS 42 P65 SEG18 SDO5 normal pins KEY6 43 66 SEG17 SDO6 KEY7 44 P67 SEG16 SDO7 I 14 Pin Description Chapter 1 Overview Table 1 3 7 Pin Function Summary 6 6 Name No IO Other Function Function Description C1 4 Capacitor Capacitor connection pins for LCD voltage booster C2 5 connection pins for LCD voltage booster VLCIN2 2 Reference power Reference power supply input pins for LCD voltage VLCN3 3 supply pins for LCD booster 71 voltage booster 1 Input for LCD Supply LCD power VLC2 2 VLCIN2 power supply Supply 5 5 V gt Vic1 gt VLC2 gt VLO3 gt 0 V 2 VLC3 3 VLCIN3 COMO 61 output P30 Output pins for LCD These pins output the common signal with the required 1 62 1 timing the LCD display 2 63 2 Connect to the common pins of LCD display panel 64 P33 When the LCD display panel is turned off Vss is output 3 SEGO 60 output P87 LCD segment These pins are LCD segment output pins SEG1 59 P86 output pins When not used as segment output these pins can be SEG2 58 P85 used as normal I O pins by setting the LCD control SEG3 57 P84
309. n PAPLUD resistor selection 0 No pull up pull down resistor 1 Pull up pull down resistor Port A pull up pull down resistor control register PAPLUD X 03F4A R W Figure 4 10 1 Port A Registers 1 2 IV 40 Port A FLOAT 6 5 4 1 0 PARDWN P7RDWN P6RDWN SYOEVS1 SYOEVSO Chapter 4 Ports At reset 000 00 SYOEVS1 SYOEVSO P6 synchronous output event selection External interrupt IRQ2 Timer 7 interrupt Timer 2 interrupt 0 1 0 1 Timer 1 interrupt P6RDWN P6 pull up pull down resistor selection 0 Pull up resistor 1 Pull down resistor P7RDWN P7 pull up pull down resistor selection 0 Pull up resistor Pull down resistor PARDWN PA pull up pull down resistor selection 0 Pull up resistor Pull down resistor Pull up Pull down resistor selection Pin control register FLOAT X 03F2E R W Figure 4 10 2 Port A Registers 2 2 PotA IV 41 Chapter 4 Ports 4 10 3 Block Diagram Pull up pull down resistor selection FLOAT register bp6 Reset AG R PAPLUDO to Pull up pull down resistor control DQ 1 Write Read 5 2 8 s Read PAINO to Port input data Rese R PAIMDO to 3 Input mode control D Q t Write
310. n The pins setup is common to the TXD pin RXD pin regardless of those pins are independednt connected Table 11 3 19 UART Serial Interface Pin Setup with 1 2 channels at transmission Setup item Data output pin Data input pin TXD pin RXD pin Port pin 1 TXD RXD pins TXD RXD pins connected or independent SCOMD1 SCOIOM Serial data output 1 input Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS Push pull Style Nch open drain SCOODC SCOODCO Output mode vO PODIR PODIRO Added Not added Pull up POPLU POPLUO Pin Setup with 2 channels at reception Table 11 3 20 shows the pins setup at UART serial interface reception with 2 channels TXD pin RXD pin Table 11 3 20 UART Serial Interface Pin Setup with 2 channels at reception 42 Operation Data output pin Data input pin Setup item TXD pin RXD pin Port pin 1 TXD RXD pins connected or independent TXD RXD pin SCOMD1 SCOIOM port serial data input Function SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style input mode VO PODIR PODIR1 Pull up Setup with 1 channel at reception Table 11 3 21 shows the pin setup at UART serial interface reception with 1 channel TXD pin The RXD pin is not used so can be used as a port Chapter 11 Tab
311. n register PODIR The control flag of the port 0 direction control register PODIR is set to 1 for output mode and 0 for input mode To read input data of pin set the control flag of the port O direction control register PODIR to 0 and read the value of the port 0 input register POIN To output data to pin set the control flag of the port 0 direction control register PODIR to 1 and write the data to the port 0 output register POOUT Each bit can be set individually if pull up resistor is added or not by the port 0 pull up resistor control register POPLU Set the control flag of the port 0 pull up resistor control register POPLU to 1 to add pull up resistor ilSpecial Function Pin Setup POO to P02 are used as l O pin for serial 0 as well POO is output pins of the serial 0 transmission data When the SCOSBOS flag of the serial interface 0 mode register 1 SCOMD1 is 1 POO is serial data output pins PO1 is the input pins of the serial 0 reception data is I O pins of the serial 0 clock When the SCOSBTS flag of serial interface 0 mode register 1 SCOMD1 is 1 is serial clock output pins POO and P01 can be selected as either an push pull output or Nch open drain output by the serial interface 0 port control registers GCOODC t Chapter 11 11 2 Control registers P06 is used as a buzzer output pin as well When the bp7 of the oscillation stabilization control register DLYCTR is 1 buzzer ou
312. nal Interrupts Chapter 4 I O Ports Chapter 4 Ports 4 1 Overview 4 1 1 Port Diagram A total of 50 pins on this LSI including those shared with special function pins are allocated for the 9 O ports of port 0 to port 3 port 5 to port 8 and port A Each I O port is assigned to its corresponding special function register area in memory I O ports are operated in byte or bit units in the same way as RAM P00 SBOO TXD SODO SEG23 KEYO P60 T P01 SBI0 RXD SOD1 SEG22 KEY1 P61 Port 0 PO2 SBTO SOD2 SEG21 KEY2 P62 P P06 BUZZER SOD3 SEG20 KEY3 P63 gt gt Port 6 SOD4 SEG19 KEY4 P64 SOD5 SEG18 KEY5 P65 SOD6 SEG17 KEY6 P66 SOD7 SEG16 KEY7 P67 y 10 SEG15 P70 4 9 P11 TM110 5 14 71 mM P12 TM2IO SEG13 P72 amp Port 1 P13 TM3IO SEG12 P73 4 lt P14 TM7IO SEG11 P74 Port 7 lt P15 TM8IO SEG10 P75 SEG9 P76 a a SEG8 P77 P20 IRQO SEG7 P80 lt e P21 IRQ1 ACZ SEG6 P81 Port 2 9 p22 IRQ2 SEG5 P82 r gt P27 NRST SEG4 P83 4 SEG3 P84 gt Port 8 SEG2 P85 SEG1 P86 SEGO P87 P30 COMO amp P P31 COM1 AN1 PA1 Port 3 lt gt P32 com2 AN2 PA2 C Port
313. nal Interrupts There 4 external interrupts in this LSI The circuit external interrupt interface operates the external interrupt input signal is built in between the external interrupt input pin and the external interrupt block This external interrupt interface can manage to do with any kind of external interrupts 3 3 1 Overview Table 3 3 1 shows the list of functions which external interrupts 0 to 2 and 4 are used Table 3 3 1 External Interrupt Functions External External External External interrupt 0 interrupt 1 interrupt 2 interrupt 4 IRQO IRQ1 IRQ2 IRQ4 iic P20 P21 P22 Interrupts put p Only Programmable active V y edge interrupt Both edges interrupt Key input interrupt Y P60 P67 Noise filter built in y y I AC zero cross _ 4 detection 34 External Interrupts 3 3 2 mExternal Interrupt 0 Interface External Interrupt 1 Interface Block Diagram 3 fosc 27 gt Prescaler output signal fosc X Block Diagram Standby mode signal Chapter 3 Interrupts NFCTR NFOSCKO NFOSCK1 NF1SCKO bit prescaler fosc 29 fosc 28 Noise filter 0 Polarity P21 IRQ1 ACz DQ Figure gt Noise filter 1 inversion Standby mo
314. nd power supply for the microcontroller are separated so that the voltage Vpp for LCD panel drive be used at higher voltage than the Vpp power supply usable at lt lt 5 5 V The LCD driver voltage supplied through the LCD driver power pins VLc2 and Vics is converted by the LCD clock signal and the timing control signal and then supplied to the segment driver and the common driver Use the LCD panel driver voltage VLCD at lt Vicp lt 5 5 V If internal voltage divider resistor or voltage booster circuit is used voltages of Vict Vica and Vics could be dropped depending on used LCD panel and that may lower the brightness of LCD display Use the external divider resistor when this is occured When LCD function is used without voltage booster circuit when voltage is supplied to the VLc2 and VLC3 pins from external source and internal voltage devider resistor is used fix C1 and C2 pins to following potential C12Vics 2 iSupplying voltage with the external voltage divider resistor Supply the voltage shown in table 13 3 1 Table 13 3 1 LCD Power Supply Bias Lop Method Static 1 2 1 3 Power Supply VLC1 VLCD VSS Vss rs 55 VLC2 2 3 Vss 1 2VLCD Vss VLC3 Vss 1 3 Vicp Vss LCD panel driver voltage Maximum voltage to the LCD panel Operation 15 Chapter 13 LCD
315. ne bit 9 bit 8 bit 1 bit 0 p 3l interrupt ADIRQ Figure 12 3 1 Operation of A D Conversion To read out the value of the A D conversion A D conversion should be done several times to prevent noise error by confirming the match of level by program or by using the average value difference more than 2 V between and 1 There is no problem for reference voltage to be below However there should be LI Operation XII 9 Chapter 12 A D Converter 12 3 1 Setup Binput Pins of A D Converter Setup Input pins for A D converter is selected by the ANCH3 to 0 flag of the ANCTR1 register Table 12 3 1 Input Pins of Converter Setup ANCHS1 ANCHSO A D pin 0 1 AN1 pin 0 AN2 pin 1 AN3 mA D Converter Setup A D converter clock is set with the ANCK1 to 0 flag of the ANCTRO register Set the A D converter clock more than 800 ns and less than 15 26 us Table 12 3 2 shows the machine clock fosc fx fs and the A D converter clock calculated as fs fosc 2 fx 2 Table 12 3 2 A D Conversion Clock and A D Conversion Cycle A D conversion cycle TAD A D conversion Te oscillation ANCK1 clock at oscillation for high speed for low speed at fosc 20 MHz at fosc 8 38 MHz at fx 32 768 kHz 0 5 2
316. ng a basic instruction length of one byte and variable word lengths based on 4 bit increments As a result the series minimizes code sizes in spite of its simple instruction set limiting data transfers to and from memory to load store operations 2 Minimum instruction execution time of one cycle in this LSI is 100 ns 3 Minimized register set that simplifies the architecture and supports C language The instruction set has been determined depending on the size and capacity of hardware after an analysis of embedded application programing code and creation code by C language compiler Therefore the set is simple instruction using the minimal register set required for C language compiler 101 LSI User s Manual Architecture Instructions Table 2 1 1 Basic Specifications Structure Load store architecture Six registers Data 8 bitx 4 Address 16 bit x 2 Other PC 19 bit PSW 8 bit SP 16 bit Instructions Number of instructions 37 Addressing modes 9 Instruction length Basic portion 1 byte min Extended portion 0 5 byte x n 0 lt lt 9 Basic Internal operating frequency 10 MHz performance Instruction execution Min 1 cycle Inter register operation Min 2 cycles Load store Min 2 cycles Conditional branch 2 to 3 cycles Pipeline 3 stage instruction fetch decode execution Address space 256 KB max 64 KB for data Instruction data com
317. ng is the same to the 8 bit timer at independently operation When timer 0 and timer 1 are used in cascade connection timer 1 is used as an interrupt request flag Timer pulse output of timer 0 is L fixed output An interrupt request of timer 0 is not generated but the timer 0 interrupt should be disabled When timer 2 and timer 3 are used in cascade connection timer 3 is used as an interrupt request flag Timer pulse output of timer 2 is L fixed output An interrupt request of timer 2 is not generated but the timer 2 interrupt should be disabled If you want to clear the binary counter by rewrite of the compare register value during cas cade connection set the TMnEN flag of the mode register of both upper lower 8 bit timers to 0 to stop counting before rewrite VI 42 Cascade Connection 6 10 2 Setup Example Chapter6 8 bit Timers mCascade Connection Timer Setup Example Timer 0 Timer 1 Timer 2 Timer 3 Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 0 and timer 1 as a 16 bit timer is shown An interrupt is generated 2500 times every 1 ms by selecting source clock to fs 4 fosx 20 MHz at operation An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter 1 TMOMD x 3F54 bp3 TMOEN TM1MD x 3F55 bp3 0 0
318. nnection Chapter 6 8 bit Timers 6 11 Remote Control Carrier Output 6 11 1 Operation Carrier pulse for remote control can be generated Operation of Remote Control Carrier Output Timer 0 Timer 3 Remote control carrier pulse is generated with output signal of timer 0 or timer 3 Duty rate is selected from 1 2 1 3 RMOUT P10 outputs remote control carrier output signal Base period set by timer Base period set by timer timer output RMOUT 1 2 duty RMOUT 1 3 duty Figure 6 11 1 Duty Rate of Remote Control Carrier Output Signal mCount Timing of Remote Control Carrier Output Timer 0 Timer 3 Base period set by timer timer output Output ON RMOEN Output OFF 1 P1OMD0 0 RMOUT 1 3 duty A Figure 6 11 2 Count Timing of Remote Control Carrier Output Function Timer 0 Timer 3 A Even if the RMOEN flag is off when the carrier output is high the carrier waveform is held by the synchronous circuit When the RMOEN flag is switched to on set the P1OMDO flag to 1 When it is switched to off set it to O When the RMOEN flag is changed do not change the base cycle and its duty at the same time If they are changed at the same time the carrier wave form is not output properly Remote Control Carrier Output VI 45 Chapter 6 8 bit Timers 6 11 2 Setup Example mRemote Control Carrier Output Setup Example Timer 0 Timer 3 Here is the setting example that the
319. nsmission reception should have the same polarity mTransfer bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SCOFM1 to 0 flag of the SCOMD2 register If the SCOCMD flag of the SCOMD1 register is set to 1 and UART communica tion is selected the setup by the synchronous serial transfer bit count selection flag SCOLNG2 to 0 is no more valid mData Input Pin Setup The communication mode can be selected from with 2 channels data output pin TXD pin data input pin RXD or with 1 channel data pin TXD pin The RXD pin be used only for serial data input The TXD pin can be used for serial data input or output The SCOIOM flag of the SCOMD 1 register can specify which pin RXD or TXD inputs the serial data If data input from TXD pin is selected to be with 1 line communication transmission reception is switched by controlling TXD pin s direction by the PODIRO flag of the PODIR register At that time the RXD pin can be used as a general port mReception Buffer Empty Flag When SCORIRQ is generated data is stored to RXBUFO from the internal shift register automatically If data is stored to the shift register RXBUFO the reception buffer empty flag SCOREMP of the SCOMD3 register is set to 1 That indicates that the received data is going to be read out SCOREMP is cleared to 0 by reading out the data of RXBUFO Operation XI 31 Chapter 11 Serial Interface 0
320. nstructions AND Dn Dm Dm amp Dn Dm 0011 0111 DnDm AND imm8 Dm Dm amp imm8 Dm 0001 11Dm AND imm8 PSW PSW amp imm8 PSW 0010 1001 0010 OR Dn Dm DmIDn Dm 0011 0110 DnDm OR imm8 Dm Dmlimm8 Dm 0001 10Dm OR imm8 PSW PSWlimm8 PSW 0010 1001 0011 lt 8 XOR Dn Dm Dm Dn oDm 0011 1010 DnDm XOR imm8 Dm Dm imm8 5Dm S o co o ajv a 0011 1010 DmDm lt 8 D DWn d DWm A An a Am d DWm D DWk D DWm 4 sign extension 8 sign extension Dn zero extension 9 15 Instruction Set Chapter 14 Appendices MN101C SERIES INSTRUCTION SET Mnemonic Operation CodeCycla Re Dn Dn Size peat Machine Code 6 7 8 Dn msb temp Dn Isb CF Dn gt gt 1 Dn temp Dn msb Dn isb CF Dn gt gt 1 Dn 0 Dn msb Bit manipulation instructions BSET io8 bp Dn Isb temp Dn gt gt 1 Dn CF Dn msb temp gt CF mem8 IOTOP io8 amp bpdata PSW 1 mem8 IOTOP i08 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 1 mem8 abs8 bp BSET abs16 bp mem8 abs16 amp bpdata PSW 1 mem8 abs16 bp BCLR io8 bp mem8 IOTOP i08 amp bpdata PSW 0 mem8 IOTOP io8 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 0 mem 8 a
321. nt Operation Event count operation means that the binary counter TMnBC counts the input signal from external to the TMnIO pin If the value of the binary counter reaches the setting value of the compare register TMnOC interrupts can be generated at the next count clock Table 6 4 1 Event Count Input Clock Timer 0 Timer 1 Timer 2 Timer 3 TMOIO input TM11O input 2 input input Event input P10 P11 P12 P13 Synchronous Synchronous Synchronous Synchronous TMOIO input 1 input 2 input input mCount Timing of TMnIO Input Timers 0 1 2 and 3 When TMnIO input is selected TMnIO input signal is directly input to the count clock of the timer n The binary counter is started to count up at the falling edge of the TMnIO input signal TMnEN flag TMnIO input Compare register con os A n counter Figure 6 4 1 Interrupt request flag Count Timing of TMnIO Input Timers 0 to 3 When the TMnIO input is selected for count clock source and the value of the timer n binary counter is read out during operation incorrect value at count up may be read out To prevent this use the event count by synchronous TMnIO input as the following page 8 bit Event Count VI 19 Chapter 6 8 bit Timers mCount Timing of Synchronous TMnIO Input Timers 0 1 2 and 3 If the synchronous TMnIO input is selected the synchronous circuit output si
322. nterrupt cycle change Set the IRWE flag of MEMCTR to enable the interrupt request flag to be rewritten This is necessary only when the interrupt request flag is changed by the software Rewrite the interrupt request flag xxxIR of the interrupt control register XxxICR Clear the IRWE flag so that interrupt request flag can not be rewritten by the software Set the interrupt level by the xxxLV1 0 flag of the interrupt control register xxxICR Set the IM1 0 flag of PSW when the interrupt acceptance level of CPU should be changed Set the xxxIE flag of the interrupt control register xxxICR to enable the interrupt Set the MIE flag of PSW to enable maskable interrupts 14 Overview 3 2 Control Registers Chapter3 Interrupts 3 2 1 Registers List Table 3 2 1 Interrupt Control Registers Register Address RW Functions Page NMICR xO3FE1 R W Non maskable interrupt control register IIl 16 IRQOICR x 03FE2 R W External interrupt 0 control register 18 IRQ1ICR x 03FE3 R W External interrupt 1 control register II 19 IRQ2ICR x 03FE4 R W External interrupt 2 control register III 20 IRQ4ICR x 03FE6 R W External interrupt 4 control register IIl 21 TMOICR 9 R W Timer 0 interrupt control register Timer 0 compare match Ill 22 TM1ICR XOSFEA R W Timer 1 interrupt control register Timer 1 compare match lll 23 TM2ICR x 03FEB R W Ti
323. ntrol Register 0 ANCTRO 7 6 5 4 3 2 1 0 Atreset 0000 ANCTRO ANSH1 ANSHO ANCK1 ANLADE ANLADE A D ladder resistance control 0 A D ladder resistance OFF 1 A D ladder resistance ON ANCK1 ANCKO conversion clock ftad 1 TAD 0 fs 2 1 fs 4 1 0 fs 8 1 fx x 2 as 800 ns lt TAD lt 15 26 us ANSH1 ANSHO Sample and hold time 0 x 2 1 Tap x 6 0 Tap x 18 1 Not to use Figure 12 2 1 A D Control Register 0 ANCTRO x O3FBO R W Control Registers XII 5 Chapter 12 A D Converter mA D Converter Control Register 1 ANCTR1 7 6 5 4 3 2 1 0 Atreset 0000 ANCTR1 RESERVED RESERVED ANCHS aNCHSO ANCHS1 50 Analog Input Channel 0 ANO 9 1 AN1 i 0 AN2 PA2 1 AN3 RESERVED Set always 0 Figure 12 2 2 A D Converter Control Register 1 ANCTR1 x 03FB1 R W A D Converter Control Register 2 ANCTR2 7 6 5 4 3 2 1 0 0 0 ANCTR2 ANST RESERVED z 2 RESERVED Set always 0 ANST A D conversion status 0 Finish Hold 1 Start Converting Figure 12 2 3 Converter Control Register 2 ANCTR2 x 03FB2 R W X
324. ock 32 kHz LOOP ADD 1 DO operation when changed to high frequency clock 20 MHz BNE LOOP SUB DO CPUM Set NORMAL mode II 20 Standby Functions Chapter 2 Basic CPU 2 4 4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY HALT STOP modes by specifying the new mode in the CPU mode control register CPUM Interrupts initiate the return To initiating a transition to a STANDBY mode the program requires in advance to 1 Set the maskable interrupt enable flag MIE in the processor status PSW to 0 to disable all maskable interrupts temporarily 2 Set the interrupt enable flags in the interrupt control registers xxxICR to 1 or 0 to specify which interrupts do and do not initiate the return from the STANDBY mode Set MIE 1 to enable those maskable interrupts NORMAL SLOW mode Clear flag the PSW all interrupt enable flags xxx IE All interrupts disabled in the maskable interrupt control register Enable interrupt which Set the xxx IE of the return factor will trigger return and set MIE flag in the PSW Set HALT STOP mode HALT STOP mode Processing inside parentheses is handled by hardware When returning from STOP mode wait for oscillation stabilize Watchdog timer NORMAL SLOW HALT restar
325. ode 5 Set the SCOLNG2 0 flag of the serial 0 mode register SCOMDO to 111 to set the transfer bit count 8 bits Operation 27 Chapter 11 Serial Interface 0 Setup Procedure Description 6 Select the start condition SCOMDO x 3F90 bp3 SCOSTE 0 7 Select the first bit to be transfered SCOMDO 3 90 bp4 SCODIR 0 8 Select the transfer edge SCOMDO x 3F90 bp7 SCOCE1 1 9 Set SC0MD2 register Control the output data SC0MD2 x 3F92 bp0 SCOBRKE 0 10 Set other mode registers SCOMD2 x 3F92 bp7 3 11 Set the SCOMD 1 register Select the communication type SCOMD1 x 3F91 bpO SCOCMD 0 12 Select the transfer clock SCOMD1 x 3F91 bp2 SCOMST 1 bp3 SCOCKM 1 13 Control the pin function SCOMD1 x 3F91 bp4 SCOSBOS 1 bp5 SCOSBIS 1 bp6 SCOSBTS 1 bp7 5 0 14 Set the interrupt level SCOTICR x 3FF6 bp7 6 SCOTLV1 0 10 6 Setthe SCOSTE flag of the SCOMDO register to 0 to disable start condition 7 Setthe SCODIR flag of the SCOMDO register to 0 to set MSB as a transfer first bit 8 Setthe SCOCE1 flag of the SCOMDO register to 1 to set the transmission data output edge rising and the received data input edge falling 9 Setthe SCOBRKE flag of the SCOMD2 register to 0 to select serial data transmission 10 No need at synchronous serial communication 11 Set the S
326. oes not return to 0 unless it is cleared by program 1 Once non maskable interrupt is generated and the value of the WDIR changes to 1 the 16 Control Registers Chapter 3 Interrupts Faulty interrupt that does not occur under normal conditions could be occurred with certain combinations of instruction codes In programming please follow the instructions shown below Faulty interrupt could be occurred independently of issue of a branch instruction if the instruc tion code right after the one of the following 19 branch instructions in a program is 2FD 3DA or 3DB which is identical to relevant unspecified instructions The relevant 19 branch instructions are BEQ BNE BGE BCC BCS BLT BLE BGT BHI BLS BNC BNS BVC BVS BRA CBEQ CBNE TBZ TBNZ This faulty interrupt halts the ICE operation with Illegal instruction break and also causes a non maskable interrupt on Mask ROM EEPROM and Flash ROM products The cause is a design error in the hardware circuits Example When a branch instruction is placed right in front of a ROM data and if the instruction right behind a branch instruction code 89 is 2FD above faulty interrupt is occurred Addr Code Nmonic 04100 AA mov A0 DO 04100 8907 bra 7D The instruction code ROM data right behind the branch 04102 2F dc F2 instruction code 89 is 2FD 04103 DO dc oD We are providing a software diagnostic tool Please re
327. ogram 1 RTI m 0 10 RTI tos Parentheses indicate hardware processing Figure 3 1 7 Processing Sequence with Multiple Interrupts Enabled Overview HI 13 Chapter 3 Interrupts 3 1 4 Interrupt Flag Setup B Interrupt request flag IR setup by the software The interrupt request flag is operated by the hardware That is set to 1 when any interrupt factor is generated and cleared to 0 when the interrupt is accepted If you want to operate it by the software the IRWE flag of MEMCTR should be set to 1 B Interrupt flag setup procedure A setup procedure of the interrupt request flag set by the hardware and the software shows as follows Setup Procedure Description 1 Disable all maskable interrupts PSW bp6 MIE 0 Select the interrupt factor Enable the interrupt request flag to be rewritten MEMCTR x 3F01 bp2 IRWE 1 Rewrite the interrupt request flag xxxICR bpO xxxIR Disable the interrupt request flag to be rewritten MEMCTR x 3F01 bp2 IRWE 0 Set the interrupt level xxxICR bp7 6 xxxLV1 0 PSW bp5 4 IM1 0 Enable the interrupt xxxICR xxxlE 1 Enable all maskable interrupts PSW bp6 MIE 1 1 Clear the MIE flag of PSW to disable all maskable interrupts This is necessary especially when the interrupt control register is changed Select the interrupt factor such as interrupt edge selection or timer i
328. ol serial interface 0 Table 11 2 1 Serial Interface 0 Control Registers Regoster Address R W Function Page SCOMDO X 03F90 R W Serial interface 0 mode register 0 6 SCOMD1 X 03F91 RW Serial interface 0 mode register 1 XI 7 SCOMD2 X 03F92 R W Serial interface 0 mode register 2 8 SC0MD3 9 R Serial interface 0 mode register XI 9 RXBUF0 X 03F94 Serial interface 0 reception data buffer XI 5 TXBUF0 X 03F95 RAN Serial interface 0 transmission data buffer XI 5 Serial 0 SC0ODC 03 96 RAN Serial interface 0 port control register XI 10 SCOCKS X 03F97 R W Serial interface 0 transfer clock selection register V 9 XI 11 PSCMD X O3F6F RW control register V 6 PODIR X 03F30 RA Port 0 direction control register 7 X 03F40 RW Port 0 pull up control register 7 SCORICR X OSFF5 R W Serial interface 0 reception interrupt control register Ill 30 SCOTICR X 03FF6 RAN Serial interface 0 transmission interrupt control register Ill 31 R W Readable Writable R Readable only XI 4 Control Registers Chapter11 Serial Interface 0 11 2 2 Data Buffer Registers Serial Interface 0 has each 8 bit data buffer register for transmission and for reception Serial Interface 0 Received Data Buffer RXBUFO T 6 5 4 3 2 1 0 RXBUFO a RXBUF03 RXBUF02 RXBUFO1 RXBUF
329. operation mode STANDBY mode Interrupt NORMAL mode OSC Hat Program 5 T XI NORMAL OSC Oscillation N XI Oscillation Interrupt 3 Oscillation 3 Program 4 Program 3 STOP mode Idle state OSC Oscillation XI Oscillation 1 HALT mode Program 2 Interrupt STOP1 1 8 SLOW E Halt OSC Program 5 XI Oscillation N 2 ES Interrupt SLOW mode FOSC Hat E Oscillation Program 4 Wait period for oscillation stabilization is inserted OSC High frequency oscillation clock XI Low frequency oscillation clock 32 kHz Figure 2 4 1 Transition Between Operation Modes Standby Functions H 17 2 Basic CPU Modes HALTO HALT1 The CPU stops operating But both of the oscillators remain operational HALTO and only the high frequency oscillator stops operating in HALT1 An interrupt returns the CPU to the previous CPU operating mode that is to NORMAL from HALTO to SLOW from HALT1 ESTOP Modes STOPO STOP1 The CPU and both of the oscillators stop operating Aninterrupt restarts the oscillators and after allowing time for them to stabilize returns the CPU to the previous CPU operating mode that is to NORMAL from or to SLOW from STOP1 BSLOW Mode This mode executes the software programs using the low frequency clock Since the high
330. or The pull up pull down resistor selection register FLOAT select if pull up resistor or pull down resistor is added The bp4 of the pull up pull down resistor control register FLOAT is set to 1 for pull down resistor set to 0 for pull up resistor ilSpecial Function Pin Setup P60 to P67 be used as the LCD segment output pins as well To use these ports as SEG16 to SEG23 pins set 1 to to 7 LC2SLO to LC2SL 7 in the LCD output control register 2 LCCTR2 The ports and the segments can be switched in 1 bit unit When segment output is selected input mode is set and the pull up resistors are set to without pull up resistors automatically P60 to P67 are used as input pins for KEY interrupt as well 0 Chapter 3 3 3 6 Key Input Interrupt 0 Chapter 3 3 3 2 Block Diagram 3 3 3 Control Registers Each bit can be set individually to synchronous output by the port 6 synchronous output control register P6SYO The port 6 synchronous output control register 65 is set to 1 for synchronous output and for general port The pin control register FLOAT can select the event that generates synchronous output When the bp1 bpO of the pin control register FLOAT is 00 the external interrupt 2 IRQ2 is selected And 01 for the timer 7 interrupt 10 for the timer 2 interrupt 11 for the timer 1 interrupt For further detail refer to 4 14 Synchronous output function p IV 43 Pot6 IV 25
331. ort at reset 00000000 LC2SL0 SEG16 Port 67 select 0 Port 67 1 SEG16 LC2SL1 SEG17 Port 66 select 0 Port 66 1 SEG17 LC2SL2 SEG18 Port 65 select 0 Port 65 1 SEG18 LC2SL3 SEG19 Port 64 select 0 Port 64 1 SEG19 LC2SL4 SEG20 Port 63 select 0 Port 63 1 SEG20 LC2SL5 SEG 21 Port 62 select 0 Port 62 1 SEG21 LC2SL6 SEG22 Port 61 select 0 Port 61 1 SEG22 LC2SL7 5 23 Port 60 select 0 Port 60 1 SEG23 values 7 6 5 4 3 2 1 0 LCCTR2 LC2SL7 LC2SL6 LC2SL5 LC2SL4 LC2SL3 LC2SL2 LC2SL1 LC2SL0 Figure 13 2 4 Output Control Register 2 LCCTR2 X 3FDC R W 10 Control Registers Chapter 13 LCD Functions 13 2 6 Segment Output Latch A 4 bit latch is allocated per segment BitO and bit4 are read out at the timing of COMO bit1 and bit5 are read out at that of COM1 bit2 and bit6 are read out at that of COM2 and bit3 and bit7 are read out at that of COMS If a bit points 1 the segment pin outputs the selected voltage and if a bit points 0 the segment pin outputs non selected voltage The assigned address are X 2E00 to X 2EOB and segment output latch value is indefined at reset Figure 13 2 5 shows the matching of the segment output latch and the segment common pins COM3 COM2 COM1 COMO COM3 CO
332. ort 6 direction control register 26 P6PLUD x 03F46 R W Port 6 pull up pull down resistor control register IV 26 P6OUT x 03F16 R W Port 6 output register IV 26 IV 44 Synchronous Output Port 6 Chapter 4 Ports 4 11 3 Operation i Synchronous Output Setup The synchronous output control register PESYO selects the synchronous output pin of the port 6 in each bit The synchronous output event is selected by the pin control register FLOAT Table 4 11 2 Synchronous Output Event Specify to Page Synchronous output port Port 6 27 External interrupt 2 802 Il 19 35 Timer 1 VI 32 Output event Timer 2 VI 32 Timer7 VII 35 When the external interrupt 2 IRQ2 is selected the interrupt edge should be specified The interrupt edge can be specified by the external interrupt 2 control register IRQ2ICR or the both edges interrupt control register EDGDT The synchronous output recognizes the generation of the specified edge as an event ilSynchronous Output Operation When the synchronous output control register P6SYO is set to disable the synchronous output I O port the port 6 is functioned as a general port When the port 6 is set to disable the synchronous output the same value to the port 6 output register P6OUT is always loaded to the synchronous output value stored register amp Figure 4 11 1 Synchronous Output Control Block Diagram After the output mode
333. ounter SCOTBSY A Set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 8 Transmission Timing at rising edge start condition is disabled XI 20 Operation Chapter11 Serial Interface 0 mReception Timing at master Tmax 25T Clock SBT pin Input pin SBI pin Transfer bit counter SCORBSY Set data to TXBUF0 Interrupt SCOTIRQ Figure 11 3 9 Reception Timing at rising edge start condition is enabled at master Tmax 1 5T T Clock SBT pin Input pin SBI pin Transfer bit counter SCORBSY Set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 10 Reception Timing at rising edge start condition is disabled Operation 21 Chapter 11 Serial Interface 0 at master Tmax 25T Clock SBT pin Input pin SBI pin Transfer bit counter SCORBSY Set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 11 Reception Timing at falling edge start condition is enabled at master Tmax 1 5T rar Clock SBT pin Input pin SBI pin Transfer bit counter SCORBSY 2 o o Set data to TXBUF0 Interrupt SCOTIRQ Figure 11 3 12 Reception Timing at falling edge start condition is disabled 22 Operation Chapter11 Serial Interface 0 mg Transmission Reception Timing When transmission and reception are operated at the same time set the SC0CE1 flag of the SC0MD0 register to 0 or 1
334. ounter is a 16 bit up counter If any data is written to a preset register when the counting is stopped the binary counter is cleared to x 0000 mTimer 7 Binary Counter TM7BC 7 6 5 4 3 2 1 0 TM7BCL TM BCL7 TM7BCL6 TM7BCL5 TM7BCL4 TM7BCL3 TM7BCL2 TM7BCL1 TM7BCLO Atreset X X X X X XXX Figure 7 2 13 Timer 7 Binary Counter Lower 8 bits TM7BCL 70 R 7 6 5 4 3 2 1 0 TM7BCH TM7BCH6 7 5 TM7BCH4 TM7BCHS TM7BCH2 TM7BCH1 TM7BCHO At reset X X X X XXXX Figure 7 2 14 Timer 7 Binary Counter Upper 8 bits TM7BCH x 03F71 R 8 Binary Counter TM8BC 7 6 5 4 3 2 1 0 TM8BCL TM8BCL7 6 TM8BCL5 TM8BCL4 TM8BCL3 TM8BCL2 TM8BCL1 TM8BCLO Atreset XX XX XXXX Figure 7 2 15 Timer 8 Binary Counter Lower 8 bits TM8BCL x O3F80 R 7 6 5 4 3 2 1 0 TM8BCH TM8BCH7 TM8BCH6 8 5 8 4 TM8BCH3 TMBBCH2 8 1 8 0 Atreset XX X XX XXX Figure 7 2 16 Timer 8 Binary Counter Upper 8 bits TM8BCH 03 81 R VII 8 Control Registers Chapter7 16 bit Timers Input capture register is a register that holds the value loaded from a binary counter by a capture trigger A capture trigger is generated by an input signal from an external interrupt pin and when an arbitrary v
335. p pull down resistor selection DQ I p D 4 Write N Z Read Reset R P7DIRO to 7 direction control D Q 8 Write N Z Read c S 9 eoe I Y Port output data P7OUTO to 7 PE E d Write ck 2 Read 7 7 D P7INO to 7 777 Port input data Read Vice Segment output control gt m E 4 Segment output data When segment output is selected segment output control automatically sets port I O direction control to input mode and segment output control is set to without pull up resistors Figure 4 8 4 Block Diagram P70 to P77 IV 34 Port7 P70 to P77 Chapter 4 Ports 4 9 Port 8 4 9 1 Description Port Setup Each bit be set individually to either an input or output by the port 8 control I O direction register P8DIR The control flag of the port 8 direction control register P8DIR is set to 1 for output mode and for input mode To read input data of pin set the control flag of the port 8 direction control register P8DIR to 0 and read the value of the port 8 input register P8IN To output data to pin set the control flag of the port 8 direction control register P8DIR to 1 and write data to the port 8 output register P8OUT Each bit can be set individually if pull up resistor is added or not by the port 8 pull u
336. p resistor control register PBPLU Set the control flag of the port 8 pull up resistor control register P8PLU to 1 to add pull up resistor Special Function Pin Setup P80 to P87 can be used as the LCD segment output pins To use these ports as SEGO to SEG7 pins set 1 to bit 0 to 3 LC1SLO to LC1SL3 in the LCD output control register 1 LCCTR1 The ports and the segments can be switched in 2 bits unit When segment output is selected input mode is set and the pull up resistors are set to without pull up resistors automatically Pot8 IV 35 Chapter 4 Ports 4 9 2 Registers 7 6 5 4 3 2 1 0 P8OUT P8OUT7 PBOUT6 5 PBOUTS PSOUT2 P8OUT1 PBOUTO At reset XX XXXXXX P8OUT Output data 0 Low Vss level is output 1 High level is output Port 8 output register P8OUT x O3F18 R W 7 6 5 4 3 2 1 0 Input data Pin is Low Vss level Pin is High Vpp level mode selection Input mode Output mode P8IN P8IN7 P8ING 8 5 PBIN3 PBIN2 P NO Atreset XXXXXXXX P8IN 0 1 Port 8 input register P8IN x OSF28 R 7 6 5 4 3 2 1 0 P8DIR _ PBDIR7 PBDIR P8DIR5 PBDIR4 PBDIR3 PBDIR2 P8DIR1 PBDIRO Atreset 00000000 P8DIR 0 1 Port 8 direction
337. perature variation from 40 C to 85 C the resistor value varies from min 11 7 KQ to max 117 How to determine pull down resistor value ex When pins maintain the high level guaranteed performance not Vpp as speci fied in the electrical characteristics and at Vpp 5 V VIN 3 5 V input current is 30 uA typ 100 max 300 uA When convert these values to resistance value typ 35 Note that this value varies wildely depending on the temperature In temperature variation from 40 C to 85 the resistor value varies from min 11 7 kQ to max 117 Overview IV 3 Chapter 4 I O Ports 4 1 3 Control Registers Ports 0 to port 5 to 8 and port A are controlled by the data output register PNOUT the data input register PnIN the I O direction control register PnDIR the pull up resistor control register PnPLU or the pull up pull down resistor control resister PnPLUD and registers that control special function pin P1OMD P5OMD PAIMD P6IMD P6SYO FLOAT Table 4 1 2 shows the registers to control ports O to 3 port 5 to 8 and port A Table 4 1 2 1 O Port Control Registers List 1 2 Register Address RW Function Page x 03F10 RAW Port 0 output register 7 buda POIN x O3F20 R Port 0 input register IV 7 PODIR xO3F30 RAN Port 0 direction control register 7 POPLU x 03F40 R
338. pin when the serial interface is not used Receive data input pins for serial interface 0 Pull up resistor can be selected by the POPLU register Select input mode by the PODIR register and serial input mode by the serial mode register 1 SCOMD1 This be used as a normal I O pin when the serial interface is not used SBTO 26 VO P02 Serial interface clock VO pins Clock IO pins for serial interface 0 For the output configuration either CMOS push pull or n channel open drain can be selected Pull up resistor can be selected by the POPLU register Select clock for each communication mode by the PODIR register and serial mode register 1 SCOMD1 This be used as a normal pin when the serial interface is not used 1 12 Pin Description Chapter 1 Overview Table 1 3 5 Pin Function Summary 4 6 Name No Other Function Function Description 24 Output SBO0 P00 UART transmission data output pins When the serial interface is used in UART mode this pin is configured as the transmission data output pin For the output configuration either CMOS push pull or n channel open drain can be selected Pull up resistor be selected by the POPLU resister Select output mode by the P0DIR register and serial data output by serial 0 mode register 1 SC0MD1 This can be used as a normal pin when the serial interface is not used
339. position of the No 1 pin Align device s pin 1 to this corner A SO LAS Package type Model number 64 LQFP 641 14 101 52 64 TQFP OTP64TF10 101CP52 Pin 1 indicator Top view Pin 1 indicator MN101CPS2A 1 E Side view PX AP101C52 BL Figure 14 1 1 Mounting a Device on Programming Adapter and the Position of No 1 Pin XIV 6 EPROM Versions Chapter 14 Appendices ROM writer Refer followig table for device type selection Table 14 1 2 Device Type Selection Pecker30 Aval Data Corporation Hitachi 27C101 K R4945A Advantest Corporation Hitachi 27C101 LabSite Data Corporation Hitachi 27C101 checks pin connection check are forbidden AF 9704 AF 9705 Ando Electric Co Ltd Hitachi 27C101 21 Versions 7 Chapter 14 Appendices 14 1 6 Cautions on Operation of ROM Writer Cautions on Handling the ROM writer 1 The Vee programming voltage for the EPROM versions is 12 5 V Programming with a 21 V ROM writer can lead to damage The ROM writer specifications must match those for standard 1 M bit EPROM 12 5 V tow 0 2 ms 2 Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter Faulty connections can damage the chip 3 After clearing all memory of the ROM writer load the program to the ROM writer Write
340. processing sequence invoked by the RTI instruction 1 The contents of the PSW are restored from the stack SP 2 The contents of the program counter PC i e the return address are restored from the stack SP 1 to SP 3 3 The contents of the handy address register HA are restored from the stack SP 4 SP 5 4 The stack pointer is updated SP 6 SP 5 Execution branches program to the address in the program counter The handy address register is an internal register used by the handy addressing function The hardware saves its contents to the stack to prevent the interrupt from interfering with operation of the function 1 Registers such as data register address register not saved so that PUSH instruction from program should be used to save them onto the stack if necessary 1 The address bp6 to 2 when program counter saved to the stack are reserved Do change it program 10 Overview iMMaskable Interrupt Chapter 3 Interrupts Figure 3 1 6 shows the processing flow when a second interrupt with a lower priority level xxxLV1 xxxLV0 10 arrives during the processing of one with a higher priority level xxxLV1 xxxLV0 00 Main program 0 1 00 1 0 11 Interrupt 1 generated z xxxLV1 0 00 Accepted because IL lt IM and MIE 1 1 0 00 Interrupt acceptance cycle
341. pt levels from 0 to 3 This flag sets the interrupt level for interrupt requests Figure 3 2 2 External Interrupt 0 Control Register IRQOICR x O3FE2 R W III 18 Control Registers Chapter 3 Interrupts mExternal Interrupt 1 Control Register IRQ1ICR The external interrupt 1 control register IRQ1ICR controls interrupt level of external interrupt 1 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 IRQ1 IRQ1 E IRQIICR LVO IRQTIE RO1TIR At reset 0 0 0 0 0 IRQ1IR External interrupt request flag 0 No interrupt request 1 Generate interrupt request IRQ1IE External interrupt enable flag 0 Disable interrupt 1 Enable interrupt REDG1 External interrupt valid edge flag 0 Falling edge 1 Rising edge IRQ1 IRQ1 Interrupt level flag LV1 LVO for external interrupt The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests Figure 3 2 3 External Interrupt 1 Control Register IRQ1ICR x 03FE3 R W Control Registers III 19 Chapter3 Interrupts mExternal Interrupt 2 Control Register IRQ2ICR The external interrupt 2 control register IRQ2ICR controls interrupt level of externa
342. r port P50 Timer 1 8 bit timer for general use Square wave output Timer pulse output Event count 16 bit cascade connection connected to timer 0 Timer synchronous output Clock source fosc fosc 4 fosc 16 fosc 2 3 fosc 2 5 fs 2 fs 8 fx external clock Timer 2 8 bit timer for general use Square wave output Timer pulse output Added pulse 2 bit type PWM output Event count Timer synchronous output Simple pulse width measure ment Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock Square wave output and PWM output can be output to large current driver port P52 2 1 4 Hardware Functions Chapter 1 Overview Timer 3 8 bit timer for general use Square wave output Timer pulse output Event count Serial transfer clock 16 bit cascade connection connect to timer2 Remote control carrier output Clock source fosc fosc 4 fosc 16 fosc 64 fosc 128 fs 2 fs fx external clock Can be used as UART baud rate timer as well Timer 6 8 bit free running timer Time base timer 8 bit free running timer Clock source fosc fosc 27 105 213 fs fx fx 2 fx 21 Time base timer Interrupt generation cycle fosc 2 fosc 2 fosc 2 fosc 2 9 5 213 105 215 1x 27 28 fx 2 fx 219 213 215 Timer 7 16 bit timer for general use Clock source fosc fosc 2 fosc 4 fosc 16 fs fs 2 fs 4 fs 16 1
343. r xxxICR is higher than the interrupt mask level When the interrupt is accepted the level is reset to IM1 IMO and interrupts whose mask levels are the same or lower are rejected during the accepted interrupt processing Table 2 1 3 Interrupt Mask Level and Interrupt Acceptance Interrupt mask level Priority Acceptable interrupt levels IM1 IMO Mask level 0 0 0 High Non maskable interrupt NMI only Mask level 1 0 1 Level 0 Mask level 2 1 0 NMI Level 0 to 1 Mask level 3 1 1 Low NMI Level 0 to 2 iMaskable Interrupt Enable MIE Maskable interrupt enable flag MIE enables disables acceptance of maskable interrupts by the CPU s internal interrupt acceptance circuit A 1 enables maskable interrupts a 0 disables all maskable inter rupts regardless of the interrupt mask level IM1 IM0 setting in PSW This flag is not changed by interrupts Overview H 9 2 Basic CPU 2 1 8 Addressing Modes This LSI supports the nine addressing modes Each instruction uses a combination of the following addressing modes 1 Register direct 2 Immediate 3 Register indirect 4 Register relative indirect 5 Stack relative indirect 6 Absolute 7 RAM short 8 I O short 9 Handy These addressing modes are well suited for C language compilers All of the addressing modes can be used for data transfer instructions In modes that allow half byte addressing the relativ
344. r selection register CKOMD bpO TMOBAS 0 2 Enable the prescaler output 2 Enable the prescaler counting by setting the PSCMD x 3F6F PSCEN flag of the prescaler control register bpO PSCEN 1 PSCMD to 1 Enable the prescaler counting by the PSCEN flag of the prescaler control register PSCMD The prescaler counting is started after it is enabled Start the timer operation after the prescaler is set Also the selection of the prescaler output should be set by the timer mode register Operation V 11 6 8 bit Timers rm Chapter6 8 bit Timers 6 1 This LSI contains four general purpose 8 bit timers Timers 0 1 2 and 3 The general purpose 8 bit timers are configured in pairs so that they can be used as 16 bit timers with cascade connection Ina cascade connecion timers 0 and 2 form the timer 0 or the lower 8 bits of 16 bit counter and timers 1 and 3 form the timer 1 or the upper 8 bits Fosc or fs can be selected as the clock source for each timer by using the prescaler Also remote control Overview output circuit is built in 6 1 1 Functions Table 6 1 1 shows functions that can be used with each timer VI 2 Table 6 1 1 Timer Functions Timer 0 Timer 1 Timer 2 Timer 3 8 bit 8 bit 8 bit 8 bit Interrupt source TMOIRQ TM1IRQ TM2IRQ TM3IRQ Timer operation Y Y Event count Y y Y Y Timer pulse output Y Y
345. r sets the frame mode Table 11 3 14 shows the UART serial interface frame mode settings If the SCOCMD flag of the SCOMD1 register is set to 1 and UART communication is selected the transfer bit count on the SCOLNG2 to 0 flag of the SCOMDO register is no more valid Table 11 3 14 UART Serial Interface Frame Mode SCOMD register Frame mode SCOFM1 SCOFMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits Parity bit is to detect wrong bits with transmission reception data Table 11 3 15 shows kinds of parity bit The SCONPE SC0PM1 to 0 flag of the SCOMD2 register set parity bit Table 11 3 15 Parity bit of UART Serial Interface SCOMD register Parity bit Setup SCONPE SCOPM1 SCOPMO 0 0 0 fixed to 0 Set parity bit to O 0 0 1 fixed to 1 Set parity bit to 1 Control that the total of 1 of bit and 9 9 paniy bit should be Control that the total of 1 of parity bit and character 2 1 1 bit should be even 1 none Do not add parity bit 1 Do not set following flame modes when SCONPE flag is 1 parity bit is disabled Character 7 bits Stop 2 bits of the flame mode Set the SCOFM1 SCOFMO flags to 0 1 Character 7 bits S
346. ransfer bit count of 7 bits data the first 11 36 Addition Following reference page guide is delited Transfer Bit Count and First Transfer Bit Delition Refer to 14 Reception Bit Count and First Transfer Bit Refer to XI 14 transfer bit in UART communication is added Organization of the section is changed 101 527 LSI User s Manual July 2002 3rd Edition 4th Printing Issued by Matsushita Electric Industrial Co Ltd Matsushita Electric Industrial Co Ltd Semiconductor Company Matsushita Electric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http www panasonic co jp semicon SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company PIC New Jersey Office Two Panasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 1 201 392 4652 Chicago Office 1707 Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 1 847 468 5725 Milpitas Office 1600 McCandless Drive Milpitas California 95035 U S A Tel 1 408 942 2912 1 408 946 9063 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee GA 30024 U S A Tel 1 770 338 6953 1 770 338 6849 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Tel 1 619 503 2903 1 858 715 5545 e Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Missi
347. ration during L period to be measured Set the clock source to fosc by the 2 0 flag of the TMOMD register Set the timer 0 compare register to the bigger value than the cycle of fosc L period of measured pulse width At that time the timer 0 binary counter is initialized to x 00 Set the interrupt level by the IRQOLV1 0 flag of the external interrupt 0 control register IRQOICR If interrupt request flag is already set clear all interrupt request flags t Chapter 3 3 1 4 Interrupt Flag Setup Set the REDGO flag of the IRQOICR register to 1 to specify the interrupt valid edge to the rising edge VI 39 Simple Pulse Width Measurement Chapter 6 8 bit Timers Setup Procedure Description 7 Enable the interrupt 7 Set the IRQOIE flag of the IRQOICR register to IRQOICR x 3FE2 1 to enable the interrupt IRQ0IE 1 8 Enable the timer operation 8 Setthe flag of the TM0MD register to TM0MD x 3F54 1 to enable timer 0 operation bp3 TMOEN 1 starts to count up with negative edge of the external interrupt 0 IRQ0 input as a trigger Timer 0 continues to count up during L period of IRQO input then stop the counting with positive edge of IRQO input as a trigger At the same time reading the value of TM0BC by interrupt handling can detects L period VI 40 Simple Pulse Width Measurement Chapter 6 8 bit Ti
348. register LCCTR1 2 SEG4 56 P83 SEGO to 15 can be switched in 2 bits units to VO ports SEG5 55 P82 SEG16 to 23 can be switched in 1 bit units to O ports SEG6 54 P81 SEG7 53 P80 SEG8 52 P77 SEG9 51 P76 SEG10 50 P75 SEG11 49 P74 SEG12 48 P73 SEG13 47 P72 SEG14 46 P71 SEG15 45 P70 SEG16 44 P67 KEY7 SDO7 SEG17 43 P66 KEY6 SDO6 SEG18 42 P65 KEY5 SDO5 SEG19 41 P64 KEY4 SDO4 SEG20 40 P63 KEY3 SDO3 SEG21 39 P62 KEY2 SDO2 SEG22 38 P61 KEY1 SDO1 SEG23 37 P60 0 SDOO MMOD 12 input Momory mode This pin set the mode for memory expansion switch input pin Input L This LSI does not have the memory expasion mode 1 When the reference voltage is input to 3 2 times voltage of the reference voltage is output to Vici 1 2 times voltage of the reference voltage is output to Vics pin When the reference voltage is input to pin times voltage of the reference voltage is output to Vic pin twice voltage of the reference voltage is output to Vice pin 2 The voltage input to Vic2 pin can be devided to Vic2 pin and Vics pin with the internal voltage divider resistors 3 to 3 be switched to normal ports 1 bit unit with the LCDMD2 register I 15 Pin Description Chapter 1 Overview 1 4 1 4 1 Block Diagram Block Diagram TXD SBOO P00 4 RXD SBIO PO1 lt SBT0 P02 4 BUZZER P06
349. rnal interrupt control register IRQnICR interrupt request flag set at switching the interrupt edge So clear the interrupt m request flag before the interrupt acceptance Also select the both edge interrupt before the interrupt acceptance The external interrupt pin is recommended to be pull up in advance External Interrupts 43 Chapter 3 Interrupts 1 Interrupt is not accepted when the both edges interrupt is selected for external interrupt and both following conditions 1 2 are fulfilled and also the timings of the following two operations a b match 1 The IRWE flag of the memory control register MEMCTR is set to 1 Enable the interrupt request flag to be written by software 2 Interrupt request flag IRQnIR of the external interrupt control register IRQnICR is set to 0 no interrupt request a Generation of write pulse which rewrites 0 to the interrupt request flag IRQnIR of the IRQnICR b Generation of interrupt request signal interrupt edge from external interface When using both edges interrupt rewrite to the interrupt request flag by software in following proce dures 1 Disable all the maskable interrupts MIE 0 2 Disable interrupt IRQnIE 0 3 Select both edges interrupt EDGSELn 1 4 Set the interrupt level 5 Enable the interrupt request flag to be written by software IRWE 1 6 Set the interrupt request flag IRQnIR 1
350. rt 1 direction control register P1DIR to 1 for output mode Set the TMORM flag of the RMCTR register to 1 to select the remote control carrier output VI 46 Remote Control Carrier Output Chapter6 8 bit Timers Setup Procedure Description 6 Select the normal timer operation TMOMD x 3F54 bp4 TMOPWM 0 bp5 TMOMOD 0 Select the count clock source TMOMD x 3F54 bp2 0 TMOCK2 0 000 7 8 Set the base cycle of remote control carrier x 3F52 x 6C 9 Start the timer operation TMOMD x 3F54 bp3 1 10 Enable the remote control carrier output RMCTR x 3F6E bp3 RMOEN 1 10 Set both of the TMOMOD flag and TMOPWM flag of the TMOMD register to 0 to select normal timer operation Select fosc to clock source by the TMOCK2 0 flag of the TMOMD register Set the base cycle of remote control carrier by writing x 6C to the timer 0 compare register TMOOC The set value should be 8 2 73 4 kHz 1 108 x 6C 8 MHz is divided to be 73 4 kHz 2 times 36 7 kHz Set the TMOEN flag of the TMOMD register to 1 to stop the timer 0 counting Set the RMOEN flag of the RMCTR register to 1 to enable the remote control carrier output TMOBC counts up from 00 Timer 0 outputs the base cycle pulse set in TMOOC Then the 1 3 duty remote control carrier pulse signal is output If the RMOEN flag of the RMCTR register
351. rupt 0 to 2 and 4 interface are controlled by the external interrupt control register IRQnICR External interrupt interface 0 to 1 are controlled by the noise filter control register NFCTR external interrupt interface 2 is controlled by the both edges interrupt control register EDGDT and external interrupt interface 4 is controlled by the port 6 key interrupt control register P6IMD Table 3 3 2 shows the list of registers which control external interrupt 0 to 2 and 3 Table 3 3 2 External Interrupt Control Register External Interrupt Register Address Function Page IRQOICR x O3FE2 External interrupt O control register IIl 18 External interrupt 0 Noise filter control register 39 IRQ1ICR External interrupt 1 control register II 19 External interrupt 1 NFCTR Noise filter control register Ill 39 IRQ2ICR 4 External interrupt 2 control register Ill 20 External interrupt 2 EDGDT x 03F8F Both edges interrupt control register III 40 IRQ4ICR x 03FE6 External interrupt 4 control register III 21 External interrupt 4 P6IMD x 03F3E Port 6 key interrupt control register III 41 R W Readable Writable HI 38 External Interrupts Chapter 3 Interrupts mNoise Filter Control Register NFCTR The noise filter control register NFCTR set the noise remove function to IQRO and IRQ1 and also selects the
352. rupt Signal as a Trigger Timer 7 Timer 8 Input capture trigger is generated at the external interrupt signal that passed through the external inter rupt interface block The capture trigger is selected by the timer n mode register 2 TMnMD2 and the external interrupt control register IRQ0ICR IRQ1ICR IRQ2ICR Selectable capture triggers and the interrupt flag setup are shown below Table 7 9 1 Capture Trigger Timer 7 mo External interrupt n control Both edges interrupt Interrupt starting edge Capture trigger source register 2 register IRQnICR control register EDGDT of external interrupt n de T7ICT1 0 T7ICEDG REDGn bp5 EDGSEL3 EDGSEL2 IRQO falling edge IRQO falling edge 00 IRQO IRQO rising edge 00 0 IRQ0 rising edge IRQ0 falling edge IRQO both edges 000800 i IRQ0 rising edge s IRQ1 rising edge Im p m o 1 1 IRQ1 falling edge 01 IRQ1 IRQ1 rising edge IRQ2 falling edge IRQ2 rising edge IRQ2 falling edge IRQ2 rising edge 1 0 1 10 IRQ2 IRQ2 rising edge IRQ2 both edges 1 The external interrupt 2 IRQ2 have the function of both edges interrupt However input 7 capture can not be used together with both edges interrupt table 7 9 1 0 1 IRQ1 rising edge 01 IRQ1 1 IRQ1 both edges 01 IRQ1 0 IRQ2 falling edge 1 1 Input capture sign
353. rupt TMOIRQ TMOICR 9 10 04028 1 interrupt TM1IRQ TM1ICR 11 x 0402C Timer 2 interrupt TM2IRQ TM2ICR 12 04030 Timer 3 interrupt TM3IRQ TMSICR 13 x 04034 Reserved 14 04038 Reserved 15 x 0403C Timer 6 interrupt TM6IRQ TM6ICR 16 x04040 Time base interrupt TBIRQ TBICR x 03FF0 17 x 04044 Timer 7 interrupt TM7IRQ TM7ICR xO3FF1 18 04048 Timer 7 compare2 match T70C2IRQ T7OC2ICR x 03FF2 19 x 0404C Timer 8 interrupt TM8IRQ TM8ICR 20 04050 Reserved 21 x04054 Serial 0 interrupt 1 SCORIRQ SCORICR 5 22 x 04058 Serial 0 interrupt 2 SC0TIRQ SCOTICR x 03FF6 23 x 0405C Reserved 24 x 04060 Reserved 25 x 04064 Reserved 26 x 04068 conversion interrupt 27 x 0406C Reserved 28 x 04070 Reserved 29 x 04074 Reserved 30 04078 Reserved Write address which the RTI instruction is written to memory space the vector addresss of reserved or unused interrupt HI 6 Overview Chapter Interrupts minterrupt Level and Priority This LSI allocated vector numbers and interrupt control registers except reset interrupt to each inter rupt The interrupt level except reset interrupt non maskable interrupt can be set by software per each interrupt group There are three hierarchical interrupt levels If multiple interrupts have the same priority
354. s Chapter 8 Time Base Timer 8 bit Free running Timer 8 2 2 Programmable Timer Registers Timer 6 is a 8 bit programmable counter Programmable counter consists of compare register TM6OC and binary counter TM6BC Binary counter is a 8 bit up counter When the TM6CLRS flag of the timer 6 mode register TM6MD is 0 and the interrupt cycle data is written to the compare register 6 the timer 6 binary counter TM6BC is cleared to x 00 Timer 6 Binary Counter TM6BC 7 6 5 4 3 2 1 0 TM6BC TM6BC7 TM6BC6 TM6BC5 6 4 TM6BC3 TM6BC2 6 00 Atreset X X XX X X X X Figure 8 2 1 Timer 6 Binary Counter TM6BC 03 68 R 6 Compare Register TM6OC 7 6 5 4 3 2 1 0 TM6OC TM6OC7 TM6OC6 TM6OC5 TM60C4 TMeOC2 TM6OC1 TM60C0 Atreset X X XXXXXX Figure 8 2 2 Timer 6 Compare Register TM6OC 03 69 R W Time base timer cannot stop counting but the software can reset its operation Time base timer can be cleared by writing an arbitrary value to the time base timer clear control register TBCLR Time Base Timer Clear Control Register TBCLR TBCLR gt 5 5 For writing only Figure 8 2 3 Time Base Timer Clear Control Register TBCLR x 03F6B Control Registers VIII 5 Chapter 8 Time Base Timer 8 bit Free running Timer 8 2 3
355. s Timer 1 Interrupt Control Register TM11CR The timer 1 interrupt control register TM1ICR controls interrupt level of timer 1 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 TM1 TM1 _ _ PE TM1ICR LV1 LVO TM1IE TM1IR At reset 0 0 0 0 TM1IR Interrupt request flag 0 No interrupt request 1 Generate interrupt request TM1IE Interrupt enable flag 0 Disable interrupt Enable interrupt TMI Interrupt level fla LV1 LVO WR 9 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 7 Timer 1 Interrupt Control Register TM1ICR x 03FEA R W Control Registers III 23 Chapter3 Interrupts mTimer 2 Interrupt Control Register TM2ICR The timer 2 interrupt control register TM2ICR controls interrupt level of timer 2 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 TM2 TM2 1 00 TM2ICR TM2IE TM2IR At reset 0 0 00 TM2IR Interrupt request flag 0 No interrupt request Generate interrupt request TM2IE Interrupt enable fl
356. s executed to be cleared in the certain cycle on the correct code execution In this LSI the watchdog timer detects errors when 1 the watchdog timer overflows 2 the watchdog timer clear is happened in the shorter cycle than the watchdog timer clear possible lowest value set in the watchdog timer control register WDCTR When the watchdog timer detects any error the watchdog interrupt WDIRQ is generated as a non maskable interrupt NMI IX 4 Operation Chapter 9 Watchdog Timer to Clear Watchdog Timer The watchdog timer can be cleared by writing to the watchdog timer control register WDCTR The watchdog timer can be cleared regardless of the writing data to the register The bit set BSET instruc tion that does not change the value is recommended iIWatchdog Time out Period The watchdog time out period is decided by the bp2 1 WDTS1 0 of the watchdog timer control register WDCTR and the system clock fs If the watchdog timer is not cleared by this set value that is regarded as an error and the watchdog interrupt WDIRQ of the non maskable interrupt NMI is gener ated Table 9 3 1 Watchdog Time out Period WDTS1 WDTSO Watchdog time out period 0 0 218 X systemclock 0 1 218 X systemclock 1 X 220 X systemclock System clock is decided by the CPU mode control register CPUM g Chapter2 2 4 Clock Switching The watchdog time out period is generally decided from
357. sampling cycle of noise remove function And this register also set the AC zero cross detec tion function to IRQ1 7 6 5 4 3 2 1 0 NFCTR P21IM NFISCK1 NFTISCKO0 NFIEN NFOSCKT NFOSCKO NFOEN Atreset 0000 000 NFOEN IRQO noise filter setup 0 Noise filter OFF 1 Noise filter ON 05 05 0 RQO noise sampling period 0 0 fosc 1 fosc 2 0 2 1 fosc 2 IRQ1 noise filter setup 0 Noise filter OFF 1 Noise filter ON 15 15 IRQ1 noise sampling period 0 fosc 1 fosc 2 0 fosc 2 1 fosc 2 P211M ACZ input enable flag 0 Disable ACZ input 1 Enable ACZ input Figure 3 3 4 Noise Filter Control Register R W External Interrupts 39 3 Interrupts mBoth Edges Interrupt Control Register EDGDT The both edges interrupt control register EDGDT selects interrupt edges of IRQ2 Interrupts are gener ated at both edges or at single edge The external interrupt control register IRQ2ICR specifies whether interrupts are generated 7 6 5 4 3 2 1 0 EDGDT EDGSE2 z At reset 00 EDGSEL2 IRQ2 Both edges interrupt selection 0 Programmable active edge interrupt selection 1 Both edges interrupt selection Set a
358. scillation clock can be used with a ceramic and crystal Oscillator mRecomended Oscillators Figure 1 6 8 shows basic configuration connected with a ceramic Oscillator and table 1 6 1 shows rec ommended Oscillators and the circuit constant Ceramic Oscillator C1 7 7 TH Feedback Resistance 800 kQ TYP MN101C527 Figure 1 6 8 Basic Configuration Connected with a Ceramic Oscillator Table 1 6 1 Recommended Ceramic Oscillator and the Circuit Cosntant Recommended circuit constant Manufacturer Frequency Part Number Load Capacity Dumping Resistance Feedback Resistance C1 pF C2 pF Rd 0 Rd 0 2MHz EFOMC2004A4 33 33 3 3k Matsushita 4MHz 4004 4 33 33 1 0k Electronic 8 MHz EFOMC8004A4 33 33 560 Components Co Ltd 16MHz 1605 4 33 33 0 5 20 MHz EFOMC2005A4 33 33 0 Wh CSTLS2M00G56 BO 47 47 Open 470 2 z CSTCC2 00MG0H6 47 47 Open 470 CSTS0400MG06 47 47 Open 4 MHz 5 4 00055 0 39 39 CSTS0800MG06 47 47 Open Manufacturing 8 MHz Company Ltd CSTCC8 00MG0H6 47 47 Open CSALS16M0X55 B0 7 7 Open 16 2 CSTCV16 00MXJ0C1 5 5 Open CSTLS20M0X51 BO 5 5 33 k 20 MHz CSTCV20 00MXJOH1 5 5 15k 1 32 Cautions for Circuit Setup Chapter 1 Overview Above recommended ranges are result obtained from unit oscillating evaluation of this LSI A
359. sion in progress Figure 11 2 6 Serial Interface 0 Mode Register 3 SCOMD3 03 93 R Control Registers XI 9 Chapter 11 Serial Interface 0 Serial Interface 0 Port Control Register SCOODC 7 6 5 4 3 2 1 0 SC0ODG 0 0001 500000 At reset 00 SC1ODCO P00 PB5 N ch open drain control 0 Push pull 1 N ch open drain SC1ODC1 P02 PB7 N ch open drain control 0 Push pull 1 N ch open drain Figure 11 2 7 Serial Interface 0 Port Control Register SCOODC x O3F96 R W XI 10 Control Registers Chapter 11 Serial Interface 0 Serial Interface 0 Transfer Clock Selection Register SCOCKS 7 6 5 4 3 2 1 0 SCOCKS SCOPSC1 SCOPSCO At reset XXX SCOPSC2 SCOPSC1 SCOPSCO Clock selection 0 0 fosc 2 1 fosc 4 0 0 fosc 16 1 1 fosc 64 0 fs 2 1 fs 4 0 Forbidden 1 1 3 output Figure 11 2 8 Serial Interface 0 Tranfer Clock Selection Register SC0CKS x 03F97 R W When timer output is selected as serial interface transfer clock select fosc as a clock source of the If other clock is selected normal transfer of serial interface data is guaran teed Control Registers 11 Chapter 11 Serial Interface 0 11 5 Operation Serial Interface 0
360. sistance 5 0 V 20 50 80 7 means conversion clock cycle 1 26 The values of 2 and 3 are guaranteed on the condition that Vob Vret 5 V and Vss Vret 0 V Note The gap between Vref and Vret should be set over 2 V Electrical Characteristics Chapter 1 Overview 1 6 Cautions for Circuit Setup 1 6 1 General Usage iConnection of VDD pin and Vss pin All of the and Vss pins should be connected directly to the power source and ground in the external Put them on printed circuit board after the location of LSI package pin is considered Incorrect connection may lead a fusion and break a microcontroller Cautions for Operation 1 Ifyou install the product close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 X Operation temperature should be well considered Each product has different condition For example if the operation temperature is over the condition its operation may be executed wrongly 3 Operation voltage should be also well considered Each product has different operating range f the operation voltage is over the operating range it can be shortened the length of its life If the operation voltage is below the operating range the operation may be executed wrongly Cautions for Circuit Setup I 27 Chapter 1 Overview 1 6 2 Unused Pins mUnused Pins output exclusi
361. sistor if necessary Chapter4 I O Ports Set the TM7BCR flag of the TM7MD2 register to 1 to select the compare match as the clear source for the binary counter Select fs as a clock source by the TM7CK1 0 flag of the TM7MD1 register Also select 1 4 dividing as a clock source by the 7 51 0 flag Set the synchronous output event generation cycle to the timer 7 preset register 1 TM7PR1 To set 10 kHz by dividing 1 MHz set as 100 1 99 x 0063 At the same time the same value is loaded to the timer 7 compare register 1 TM7OC1 and TM7BC is initialized to x 0000 16 bit Timer Synchronous Output VII 37 Chapter 7 16 bit Timers Setup Procedure Description 7 Start the timer operation TM7MD 1 x 3F78 bp4 TM7EN 1 7 Setthe TM7EN flag of the TM7MD1 register to 1 to start timer 7 TM7BC counts up from 0000 If any data is written to the port 6 output register TM7BC is set to the set value of TM7OC1 register and the synchronous output pin outputs data of port 6 in every time an interrupt request is generated VII 38 16 bit Timer Synchronous Output 7 16 bit Timers 7 9 16 bit Timer Capture 7 9 1 Operation The value of binary counter is read out at the timing of the external interrupt input signal or at the timing of the writing operation with an any value to the capture register mCapture Operation with External Inter
362. ssauga Ontario LAW 2T3 CANADA Tel 1 905 238 2315 1 905 238 2414 E LATIN AMERICA e Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F MEXICO Tel 52 5 488 1000 Fax 52 5 488 1073 Guadalajara Office SUCURSAL GUADALAJARA Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44920 MEXICO Tel 52 3 671 1205 OG Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Tel 55 12 335 9000 55 12 331 3789 B EUROPE OG Europe Sales Office Panasonic Industrial Europe GmbH PIE U K Sales Office Willoughby Road Bracknell Berks RG12 8FP THE UNITED KINGDOM Tel 44 1344 85 3671 44 1344 85 3853 Germany Sales Office Hans Pinsel Strasse 2 85540 Haar GERMANY Tel 49 89 46159 119 49 89 46159 195 ASIA e Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 The Concourse Singapore 199555 THE REPUBLIC OF SINGAPORE Tel 65 6390 3688 Fax 65 6390 3689 e Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office Tingkat 16B Menara PKNS Petaling Jaya No 17 Jalan Yong Shook Lin 46050 Petaling Jaya Selangor Darul Ehsan MALAYSIA Tel 60 3 7951 6601 60 3 7954 5968 Fax 52 3 671 1256 Matsushita Electric Industrial Co Ltd 2002 Pen
363. t MIN TYP MAX Power supply current without load at output 6 fosc 20 0 MHz Vpp 5 V 1 1 40 C to 85 C 25 60 fs fosc 2 mA 2 Power supply current isos fosc 8 39 MHz Vpp 5 V 10 25 fs fosc 2 fx 32 768 kHz Vpp 3 V 3 ps 18 1504 30 100 4 92768 kHz 3 V 4 8 Supply surrent during Ta 25 5 HALT1 mode Ke fx 32 768 kHz 3 V 40 C to 85 C uA 5 V 6 ps 3 2 Supply current during Ta 25 C STOP mode Vpp 5 V 2 E Ta 40 C to 85 C 5 8 Measured under conditions without load The supply current during operation IDD1 IDD2 is measured under the following condi tions After all I O pins are set to input mode and the oscillation is set to lt NORMAL mode the MMOD pin is at Vss level the input pins are at VDD level and a 20 MHz 8 39 MHz square wave of VDD and Vss amplitudes is input to the OSC1 pin The supply current during operation IDD3 is measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt SLOW mode the MMOD is at Vss level the input pins are at VDD level and a 32 768 kHz square wave of VDD and Vss amplitudes is input to the XI pin The supply current during HALT1 mode IDD4 IDD5 is measured under the following condi tions After all I O pins are set to input mode and the oscillation is set to HALT mode the MMOD pin is at Vss level the input pins are at VDD level and an 3
364. t Timer 1 Timer 2 TMnEN flag Compare register 1 Port 6 output latch data Binary counter Interrupt request flag Port 6 synchronous output data Figure 6 7 1 Timing of Synchronous Output Timer 1 Timer2 The port 6 output latched data is output from the output pin in synchronization with the interrupt request generation by the match of binary counter and compare register VI 32 Synchronous Output 6 7 2 Setup Example Chapter 6 8 bit Timers Synchronous Output Setup Example Timer 1 Timer 2 Setup example that latch data of port 6 is output constantly 100 us by using timer 2 from the synchro nous output pin is shown below The clock source of timer 2 is selected fs 4 fosc 8 MHz at operation A setup procedure example with a description of each step is shown below Setup Procedure Description Start the counter TM2MD x 3F5C bp3 TM2EN 0 Select the synchronous output event FLOAT 2 bp1 0 SYOEVS1 0 10 Set the synchronous output pin P6SYO x 3F1F X FF P6DIR x 3F36 X FF Select the normal timer operation TM2MD x 3F5C bp4 STM2PWM 0 bp5 2 0 Select the count clock source TM2MD x 3F5C bp2 0 TM2CK2 0 001 Select the prescaler output and enable counting CK2MD x 3F5E bp2 1 TM2PSC1 0 01 bpO 2 5 1 PSCMD x SF6F bpO PSCEN 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0
365. t 16 input 16 fosc Machine clock High frequency oscillation fx Machine clock Low frequency oscillation fs System clock Synchronous output can not be used at the processor mode VII 2 Overview 16 bit Timers Chapter 7 Block Diagram 7 1 2 mTimer 7 Block Diagram epeoseo 9 z 1919 60 195910 119 91 Tedd ZN peau jeu amp is SVO f 08005 eeg Hc90 INL 2 1eisiBo eyeduiooandino 10 91 TeOOZWL lt ZINMd ndino ul BNL 0 _ reuBis JAO jue eindjno snouoJu2uAS 4 LOHIZIALL ul 8 1 01 reus 166811 eunde lt 18 025810 19 2dq ZqWZWL NOIL lq sip lqeu OMOZWL LOWZWL 1 ende uonoejep lt t t GERA 98 TSWMd ZL 5 X X 0 H n n We IN 1 eda 158 98 1 ISH 108 1 Y X li
366. t ON DLYCTR x 3F03 bp7 BUZOE 1 Buzzer output OFF DLYCTR x 3F03 bp7 BUZOE 0 Set the BUZS2 0 flag of the oscillation stabilization wait control register DLYCTR to 010 to select fosc 2 to the buzzer frequency When the high oscillation clock fosc is 8 38 MHz the buzzer output frequency is 2 05 kHz Set the output data POOUTE6 of P06 to and set the direction control PODIR6 of P06 pin to 1 to select output mode Port 06 pin outputs low level Set the BUZOE flag of the oscillation stabilization wait control register DLYCTR to 1 to output the square wave of the buzzer output frequency set by P06 pin Set the BUZOE flag of the oscillation stabilization wait control register to DLYCTR 0 to clear and pin outputs low level Operation X 5 Chapter 11 Serial Interface 0 Chapter 11 11 1 This LSI contains serial interface 0 that used for both communication types of clock synchronous Serial Interface 0 Overview and UART duplex 11 1 1 Functions Table 11 1 1 shows functions of serial interface 0 XI 2 Overview Table 11 1 1 Serial Interface 0 Functions Communication style clock synchronous UART duplex SCOTIRQ on transmission completion Interrupt SCOTIRQ SCORIRQ on reception completion Used pins SBOO SBIO SBTO TXD RXD 3 channels type Y 2 channels type Y SBOO SBTO Y 1 channel type V TXD Specifi
367. t level by the TM7LV1 0 flag of the timer 7 interrupt control register TM7ICR If the interrupt request flag may be already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup Set the TM7IE flag of the TM7ICR register to 1 to enable the interrupt VII 18 Operation Chapter 7 16 bit Timers Setup Procedure Description 7 Start the timer operation TM7MD 1 x 3F78 bp4 TM7EN 1 7 Set the TM7EN flag of the TM7MD1 register to 1 to start timer 7 TM7BC counts up from x 0000 When TM7BC reaches the set value of the TM7OC1 register the timer 7 interrupt request flag is set at the next count clock and the TM7BC becomes x 0000 and counts up again When the TMnEN flag of the TMnMD register is changed with other bits the binary counter may count up by switching operation Operation VII 19 Chapter 7 16 bit Timers 7 4 16 bit Event Count 7 4 1 Operation Event count operation has 2 types TMnIO input and synchronous TMnIO input These can be selected as the count clock Each type can select 1 1 1 2 1 4 1 16 as a count clock source Timer 7 can also select the count edge falling or both edges 16 bit Event Count Operation Timer 7 Timer 8 The binary counter TMnBC counts the external signal input to the TMnIO pin If the binary counter reaches the set value of the compare register TMnOC an interrupt can be generated at t
368. t request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 TMe 6 _ D ers LU EVO TM6IE TM6IR At reset 0 0 00 TM6IR Interrupt request flag 0 No interrupt request Generate interrupt request TM6IE Interrupt enable flag 0 Disable interrupt Enable interrupt TM6 TM6 LV1 LVO Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 10 Timer 6 Interrupt Control Register TM6ICR x O3FEF R W 26 Control Registers mTime Base Interrupt Control Register TBICR The time base interrupt control register TBICR controls interrupt level of time base interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 TBICR 7 6 TB LV1 TB LV0 TBIE TBIR Figure 3 2 11 Chapter 3 Interrupts At reset 0 0 0 0 TBIR Interrupt request flag No interrupt request Generate interrupt request Interrupt enable flag Disable interrupt Enable interrupt TB LV1 TB LVO Interrupt level flag This 2 bit flag sets the interrupt lev
369. t the SC0MST flag of the SC0MD1 register to 1 If 0 is set the communication is disabled When timer output is selected as serial interface transfer clock select fosc as a clock source of the timer If other clock is selected normal transfer of serial interface data is not guaran a teed Operation 35 Chapter 11 Serial Interface 0 mTranfer Bit Count and First Transfer Bit When the transfer bit is 7 bits the data storing method to the transmission data buffer TXBUFO is different depending on the first transfer bit selection At MSB first use the upper bits of TXBUFO for storing When there are 7 bits to be transfered as shown on figure 11 3 16 if data A to are stored to bp1 to bp7 of TXBUFO the transmission is operated from G to A At LSB first use the lower bits of TXBUFO for storing When there are 7 bits to be transfered as shown on figure 11 3 17 if data A to are stored to bpO to bp6 of TXBUFO the transmission is operated from A to G 7 6 5 4 3 2 1 0 Txeuro G F D C B Figure 11 3 16 Transfer Bit Count and First Transfer Bit starting with MSB TXBUF0 G F E D Figure 11 3 17 Transfer Bit Count and First Transfer Bit starting with LSB Receive Bit Count and First Transfer Bit When the transfer bit count is 7 bits the data storing method to the received data buffer RXBUFO is different depending on the firs
370. t the TMOPWM of the TMOMD register TMOMD x 3F54 to 1 the TMOMOD flag to 0 to select the bp4 STMOPWM 1 PWM operation bp5 TMOMOD 0 4 Select the count clock source 4 Select fs for the clock source by the TMOMD x 3F54 TMOCK2 0 flag of the TMOMD register bp2 0 2 0 010 VI 28 8 bit PWM Output Chapter6 8 bit Timers Setup Procedure Description 5 Set the period of PWM output x 3F52 40 6 Start the timer operation TMOMD x 3F54 bp3 1 5 Set the period of PWM output to the timer 0 compare register TM0OC The setting value is set to 256 4 64 407 because it should be the 1 4 duty of the lull count 256 At that time the timer 0 binary counter is initialized to x 00 Set the TMOEN flag of the TMOMD register to 1 to operate timer TMOBC counts up from x 00 PWM source waveform outputs till TMOBC reaches the setting value of the TMOOC register and outputs L after that Then TMOBC continues counting up and PWM source waveform outputs H again once overflow is happened and TMOBC restarts counting up from x 00 TMOIO pin outputs the PWM source waveform with 1 count clock delay The initial setting of PWM output is changed from L output to H output at the selection of PWM operation by the TMnPWM flag of the TMnMD register 8 bit PWM Output VI 29
371. t to MN101C527 excepts its Mask ROM is substituted with an electri cally programmable EPROM We offer MN101CP52ABL and 101 52 for 101 527 The MN101CP52ABL is sealed in plastic Once a data is written to the internal EPROM it cannnot be erased PX AP101C52 BC is sealed in a ceramic package with a window Written data can be erased by expos ing the physical chip to intense ultraviolet radiation We offer 64 pin flat package for the PX AP101C52 BC When the EPROM version is set to EPROM programming mode its functions as a microcontroller is halted and then the internal EPROM can be programmed For EPROM mode pin connection refer to figure 14 1 2 Programming Adapter Connection The specification for writing to the internal EPROM are the same as for a general purpose 1 M bit EPROM 12 5 V tpw 0 2 ms Therefore by useing a dedicated programming adapter supplied by Panasonic which can convert the 64 pin EPROM versions to 32 pin having the same configuration as a normal EPROM a general purpose EPROM writer can be used for read and write operations This EPROM Version is described on the following items Cautions on use of the internal EPROM Erasing data in windowed package PX AP101C52 BC Differences between Mask ROM version and EPROM versions Writing to the EPROM built in microcontroller Cautions on use of the ROM writer XIV 2 EPROM Versions Chapter 14 Appendices 14 1 2 Caution on Use
372. t transfer bit selection At MSB first data are stored to the upper bits of RXBUFO When there are 7 bits to be transfered as shown on figure 11 3 18 if data to A are stored to bp7 to of RXBUFO At LSB first data are stored to the lower bits of RXBUFO When there are 7 bits to be transfered as shown on figure 11 3 19 if data A to G are stored to to bp6 of RXBUFO RXBUFO G F E D C B Figure 11 3 18 Receive Bit Count Transfer First Bit starting with MSB bit RXBUF0 G G F E D Figure 11 3 19 Receive Bit Count and Transfer First Bit starting with LSB bit XI 36 Operation following items same clock synchronous serial Reference as follows mFirst Transfer bit Setup Refer to XI 13 mTransmission Data Buffer Refer to 13 mReceived Data Buffer Refer to 13 iTransmission Buffer Empty Refer to 17 Reset Refer to 18 Chapter 11 Operation Serial Interface 0 XI 37 Chapter 11 Serial Interface 0 Transmission Timing SENE gt parity x TXD pin SCOTBSY A set data to TXBUFO Interrupt SCOTIRQ Figure 11 3 20 Transmission Timing parity bit is enabled TXD pin SCOTBSY set data to TXBUF0 Interrupt SCOTIRQ Figure 11 3 21 Transmission Timing parity bit is disabled 38 Operation Chapt
373. tandard rate shown in the following page 1 Transfer rate should selected under 300 kbps of the timer If other clock is selected normal transfer of serial interface data is not guaran 1 When timer output is selected serial interface transfer clock select fosc as clock source LI teed XI 40 Operation Chapter 11 Serial Interface 0 Table 11 3 18 1 Setup Value of UART Serial Interface Transfer Speed decimal fosc Clocksouce 30 90 1200 2400 4800 ime mE EORR SNNT RS 1202 2404 4808 ES e re E 120 2403 4761 8 38 fosc 217 4805 ee 16 00 fosc 4808 er f ese 20 00 fosc E 5 P Table 11 3 18 2 Setup Value of UART Serial Interface Transfer Speed decimal Transfer rate bps Clock source 9600 19200 28800 31250 38400 timer 9615 12 19231 ee 2 31250 9699 E E L Te m r fosc 54 9523 F 19398 i foc 77 9615 38 1931 25 28846 23 31250 fosc 103 9615 51 1929 31 31250 25 38462 9 5 mee 20 00 fosc 129 9615 19231 31250 x Operation 41 Chapter 11 Serial Interface 0 Setup with 1 2 channels at transmission Table 11 3 19 shows the pins setup at UART serial interface transmissio
374. ter is read out at operation an incorrect value could be read out To prevent this select a synchronous fx as the count clock source But if the synchronous fx is selected as the count clock source CPU mode cannot return from STOP HALT mode If the smaller value than the binary counter is set to the compare register at counting opera tion the binary counter continues counting till overflow 8 bit Free running Timer VIII 9 Chapter 8 Time Base Timer 8 bit Free running Timer 8 3 2 Setup Example mTimer Operation Setup Timer 6 Timer 6 generates interrupts constantly for timer function Interrupts are generated in every 250 dividing 25 us by selecting fs fosc 20 MHz at operation as clock source An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Enable the binary counter initialization TM6MD x 3F6A bp7 TM6CLRS 0 Select the clock source TM6MD x 3F6A bp3 1 IM6CK3 1 001 Set the interrupt generation cycle TM6OC X 3F69 x FQ Enable the interrupt request generation TM6MD x 3F6A bp7 TM6CLRS 1 Set the interrupt level TMG6ICR x 3FEF bp7 6 TM6LV1 0 01 Enable the interrupt TM6ICR x 3FEF bp1 TM6IE 1 Set the TM6CLRS flag of the timer 6 mode register TM6MD to 0 At that time the initialization of the timer 6 binary counter TM6BC is enabled Clock source can b
375. ter2 Basic CPU 2 4 2 Mode Control Register Transition to other modes is controlled by operating the related flags in the CPU mode control register CPUM 7 6 5 4 3 2 1 0 CPUM osceetioscstia OSCDBL STOP HALT OSC1 OSCO At reset 1 1 0 0 0 0 0 cea STOP HALT OSC1 osco ond CPU NORMAL 0 0 0 0 QOscillationOscillaion OSCI Operating IDLE 0 0 0 1 QscillationOscillation XI Operating SLOW 0 0 1 1 Halt Oscillation XI Operating HALTO 0 1 0 0 QscillationOscillaion OSCI Halt HALT1 0 1 1 1 Halt Oscillation XI Halt STOPO 1 0 0 0 Halt Halt Halt Halt STOP1 1 0 1 1 Halt Halt Halt Halt Figure 2 4 2 Operating Mode Control and Clock Oscillation On Off CPUM x 3F00 R W The procedure for transition from NORMAL to HALT or STOP mode is shown below 1 If the return factor is a maskable interrupt set the MIE flag in the PSW to 1 and set the interrupt mask IM to a level permitting acceptance of the interrupt 2 Clear the interrupt request flag xxxIR in the maskable interrupt control register XxxICR set the interrupt enable flag xxxlE for the return factor and set the IE flag in the PSW 3 Set CPUM to HALT or STOP mode IRWE flag of Memory control MEMCTR should be set for interrupt request flag to be cleared by software System clock fs is changed depending on CPU operation mode In
376. the interrupt request flag has been already set clear the request flag Chapter 3 3 1 4 Interrupt flag setup 5 Setthe IRQOIE flag of the IRQOICR register to 1 to enable the interrupt Note Above 2 and 3 are set at the same time The input signal from the P20 pin generates the external interrupt 0 at the rising edge of the signal after passing through the noise filter a The setup of the noise filter should be done before the interrupt is enabled LI The external interrupt pins are recommended to be pull up in advance III 49 External Interrupts 3 Interrupts 3 3 8 Zero Cross Detector This LSI has AC zero cross detector circuit The P21 ACZ pin is the input pin of AC zero cross detector circuit AC zero cross detector circuit output the high level when the input level is at the middle and outputs the low level at other level Zero Cross Detector External interrupt 1 AC zero cross detector set the IRQ1 pin to the high level when the input signal 21 2 pin is at intermediate range by AC zero cross detector circuit At the other level IRQ1 pin is set to the low level AC zero cross detector is set by setting the P211M flag of the noise filter control register NFCTR to 1 approx 10 ms at 50 Hz approx 8 3 ms at 60 Hz AC line waveform VS sana eter Ideal IRQ1 Actual I I
377. the match of a binary counter and a compare register 1 VII 36 16 bit Timer Synchronous Output 7 8 2 Setup Example Synchronous Output Setup Example Timer 7 Chapter 7 16 bit Timers Here is an example to output the port 6 latch data from the synchronous output pin constantly in every 100 us with timer 7 As a clock source of timer 7 fs 4 fosc 8 MHz is selected An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 TM7EN 0 2 Select the synchronous output event FLOAT x 3F2E bpi 0 SYOEVS1 0 01 3 Setthe synchronous output pin P6SYO x 3F1E x FF P6DIR x 3F36 X FF 4 Select the timer clear factor TM7MD2 x 3F79 bp5 TM7BCR 1 5 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 01 bp3 2 TM7PS1 0 10 6 Setthe synchronous output event generation cycle TM7PR1 x 3F75 x 3F74 x 0063 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop timer 7 counting Set the SYOEVS1 0 flag of the pin control register FLOAT to 01 to set the synchronous output event to the timer 7 interrupt Set the port 6 synchronous output control register P6SYO to x FF to set the synchronous output pin P67 to P60 Synchronous output pin Set the port6 direction control register P6DIR to x FF to set port 6 to output pin Add pull up re
378. the setting value of the TMOOC register the timer 0 interrupt request flag is set at the next count clock then the value of TMOBC becomes 00 and counting up is restarted VI 22 8 bit Event Count Chapter 6 8 bit Timers 6 5 8 bit Timer Pulse Output 6 5 1 Operation The TMnIO pin can output a pulse signal at any frequency B Operation of Timer Pulse Output Timers 0 1 2 and 3 The timers can output signals of 2 x cycle of the setup value in the compare register TMnOC Output pins are as follows Table 6 5 1 Timer Pulse Output Pins Timer 0 Timer 1 Timer 2 Timer 3 P lse Guu DIA TMOIO output TM1IO output TM2IO output output put p P10 P11 P12 P13 mCount Timing of Timer Pulse Output Timers 0 1 2 and 3 flag Compare br v4 M LN register counter Interrupt request flag TMnIO output Figure 6 5 1 Count Timing of Timer Pulse Output Timers 0 to 3 The TMnIO pin outputs signals of 2 x cycle of the setup value in the compare register If the binary counter reaches the compare register and the binary counter is cleared to 00 TMnlO output timer output is inverted The inversion of the timer output is changed at the rising edge of the count clock This is happened to form waveform inside to correct the output cycle 8 bit Timer Pulse Output VI 23 Chapter 6 8 bit Timers 6 5 2 Setup Example Timer Pulse Output Setup Example Timer 0 1
379. tion and the serial interface setup refer to chapter 11 Serial Interface 0 and chapter 12 Serial Interface 2 Serial Transfer Clock Output VI 35 Chapter 6 8 bit Timers 6 8 2 Setup Example Serial Transfer Clock Setup Example Timer 3 How to create a transfer clock for half duplex UART Serial 0 using with timer 3 is shown below The baud rate is selected to be 300 bps the source clock of timer 3 is selected to be 15 4 at fosc 8 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter 1 Set the flag of the timer 3 mode x 3F5D register TM3MD to 0 to stop timer 3 bp3 TM3EN 0 counting 2 Selectthe normal timer operation 2 Set the TM3CAS flag flag of the TM3MD x 3F5D register to 0 to select the normal timer bp4 SMSCAS 0 operation 3 Select the count clock source 3 Select the clock source to prescaler output by TMS3MD x 3F5D the 2 0 flag of the TM3MD register bp2 0 TM3CK2 0 001 4 Select the prescaler output and 4 Select the prescaler output to fs 8 by the enable counting TM3PSC1 0 TM3BAS flag of the timer 3 CK3MD x 3F5F prescaler selection register CK3MD bp2 1 TM3PSC1 0 01 Also set the PSCEN flag of the prescaler bp0 1 control register PSCMD to 1 to enable the PSCMD x 3F6F prescaler counting bp0 PSCEN 1 5 Set the baud rate 5 Set the
380. top 1 bit of the flame mode Set the SCOFM1 SCOFMO flags to 0 0 Status Transmission Control Setup The SCOBRKE flag of the SCOMD2 register generates the brake status If SCOBRKE is set to 1 to select the brake transmission all bits from start bits to stop bits transfer O Operation 33 Chapter 11 Serial Interface 0 Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be determined by the SCOORE SCOPEK SCOFEF flag of the SCOMDS register Even one of those errors is detected the SCOERE flag of the SCOMD3 register is set to 1 The SCOPEK the SCOFEF flags in recepption error flag are renewed at generation of the reception complete interrupt SCORIRQ The SCOORE flag holds the status unless data of RXBUFO is read out The decision of the received error flag should be operated until the next communication is finished Those error flag has no effect on communication operation Table 11 3 16 shows the list of reception error source Table 11 3 16 Reception Error Source of UART Serial Interface Flag Error Error source SCOORE Overrun error Next data is received before reading the receive buffer at fixed to 0 when parity bit is 1 at fixed to 1 when parity bit is 0 SCOPEK Parity error odd parity The total of 1 of parity bit and character bit is even even parity The total of 1 of parity bit and char
381. tor ilSpecial Function Pin Setup P10 to P15 are used as timer I O pin as well P10 is used as remote control carrier output pin as well The port 1 output mode register P1OMD can select P10 to P15 output mode by each bit When the port 1 output mode register P1OMD is 1 special function data is output and when it is 0 they are used as general port 10 Portl 4 3 2 P1OUT P1IN P1DIR P1PLU Registers 7 6 5 4 3 2 1 0 1 5 100 4 P1OUT3 P1OUT2 P1OUT1 P1OUTO Chapter 4 Ports At reset XXXXXX P1OUT Output data 0 Low 55 level is output 1 High level is output Port 1 output register P1OUT x 03F11 R W 4 3 2 1 0 P1IN5 P1IN4 P1IN3 2 P1IN0 Atreset XXXXXX Port 1 input register x 03F21 R 7 6 5 4 3 2 1 0 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO Port 1 direction control register P1DIR 03 31 R W 7 6 5 4 3 P1IN Input data Pin is low Vss level Pin is high VDD level Atreset 000000 2 1 0 P1PLUS5 P1PLUA P1PLUS P1PLU2 P1PLU1 P1PLUO P1DIR mode selection 0 Input mode 1 Output mode Atreset 000000
382. tor values MN101C527 LSI User s Manual Record of Changes Ver 3 3 to Ver 3 4 2 2 Definiti Details of Changes Section n PreviousEdition Ver 3 3 New Edition Ver 3 4 binary counter But with synchronous fx return from Key mark Addition STOP HALT modes is disabled Compare register value calculation Key mark Addition Timer pulse output cycle Compare register value Selected clock cycle x2 1 When fx is selected as a count clock source and if binary counter value is read out during opeartion the read value may be uncertain To prevent this select synchronous fx as a count clock source To do so timer n counts up the binary counter with a signal that is sync with the system clock and you can always read out correct value from the If you want to clear the binary counter by rewrite of the Key mark Addition compare register value during cascade connection set 6 35 11 11 T 16 29 Caution Addition 35 40 48 the TMnEN flag of the mode register of both upper lower 8 bit timers to 0 to stop counting before rewrite 7 15 Addition Do not set following flame modes when SCONPE flag is Do not set as following combination T and parity bitis disabled 11 33 Caution Change no bit to eren fla and data 7 bits ota Dits ofthe lame mode i s 2 bits to de mode fla Set ne SGOEMT SOOENU flags 16 D 1 9 Character 7 bits Stop 1 bit of the flame mode Set the SCOF
383. tput is enabled IV 6 Pot0 Chapter 4 Ports 4 2 2 Registers 7 6 5 4 3 2 1 0 POOUT 0 76 POOUT2 POOUTI POOUTO Atreset X X XX Output data 0 L Vss level is output 1 H VDpD level is output Port 0 output register POOUT x 03F10 R W 7 6 5 4 3 2 1 0 POIN POIN2 POINT Atreset X XXX POIN Input data 0 Pin is low Vss level 1 Pin is high Vpp level Port 0 input register x 03F20 R 6 5 4 2 1 0 PODIR PoDIR6 PODIR2 PODIR1 PODIRO At reset 0 000 PODIR mode selection 0 Input mode 1 Output mode Port 0 direction control register PODIR x 03F30 R W 6 5 4 2 1 0 POPLU 6 POPLU2 POPLU1 POPLUO At reset 0 000 POPLU Pull up resistor selection 0 No pull up resistor 1 Pull up resistor Port 0 pull up resistor control register POPLU x 03F40 R W Figure 4 2 1 Port 0 Registers 1 2 Port 0 7 Chapter4 Ports 4 2 3 Block Diagram
384. trol register TBCLR Time Base Timer VIII 13 Chapter 8 Time Base Timer 8 bit Free running Timer 8 4 2 mTimer Operation Setup Time Base Timer An interrupt can be generated constantly with time base timer in the selected interrupt cycle The inter Setup Example generation cycle is fosc x 1 21 0 977 ms fosc 8 38 MHz to generate interrupts An example setup procedure with a description of each step is shown below Setup Procedure Description Select the clock source TM6MD x 3F6A bp0 TM6CK0 0 Select the interrupt generation cycle TM6MD x 3F6A bp6 4 TM6IR2 0 100 Initialize the time base timer TBCLR x 3F6B x 00 Set the interrupt level TBICR x 3FF0 bp7 6 TBLV1 0 01 Enable the interrupt TBICR x 3FF0 1 Select fosc as clock source by the TM6CKO flag of the timer 6 mode register TM6MD Select the selected clock x 1 213 as an interrupt generation cycle by the TM6IR2 0 flag of the TM6MD register Write value to the time base timer clear control register TBCLR to initialize time base timer Set the interrupt level by the TBLV1 0 flag of the time base interrupt control register TBICR If any interrupt request flag may be already set clear them Chapter 3 3 1 4 Interrupt Flag Setup Set the flag of the TBICR register to 1 to enable the interrupt the above steps 1 2 can be set at onc
385. trol Register 1 LCCTR1 The LCD output control register 1 LCCTR1 switches port output P7 P8 and segment output SEGO to SEG15 The address assigned to this register is BFDB At reset LCCTR1 is set to the input port values 7 6 5 4 3 2 1 0 LCCTR1 LC1SL7 LC1SL6 LC1SL5 LC1SL4 LC1SL3 LC1SL2 LC1SL1 LCISLO at reset 00000000 SEG7 to 6 Port 80 to 81 LC1SL0 0 Port 80 to 81 1 SEG7 to 6 SEGS5 to 4 Port 82 to 83 LC1SL1 select 0 Port 82 to 83 1 SEG5 to 4 SEG3 to 2 Port 84 to 85 LC1SL2 select 0 Port 84 to 85 1 SEG3 to 2 SEG1 to 0 Port 86 to 87 LC1SL3 select 0 Port 86 to 87 1 SEG to 0 5 8 to 9 Port 76 to 77 LC1SL4 Select 0 Port 76 to 77 1 SEG8 to 9 SEG10 to 11 Port 75 to 74 LC1SL5 0 Port 75 to 74 1 SEG10 to 11 SEG12 to 13 Port 73 to 72 LC1SL6 0 73 72 1 SEG12 to 13 SEG14 to 15 Port 71 to 70 LC1SL7 select 0 Port 71 to 70 1 SEG14 to 15 Figure 13 2 3 Output Control Register 1 LCCTR1 X 3FDB R W Control Registers 9 Chapter 13 LCD Functions 13 2 5 Output Control Register 2 LCCTR2 The LCD output control register 2 LCCTR2 switches port output P6 and segment output SEG16 to SEG23 The address assigned to this register is x 3FDC At reset LCCTR2 is set to the input p
386. trol register PSCMD starts or stops the count up operation mCount Timing of Prescaler Operation Prescalers 0 1 Prescaler 0 counts up at the falling edge of fosc Prescaler 1 counts up at the falling edge of fs Functions with Prescaler Output Cycle Clock Table 5 3 1 shows the peripheral functions that are capable of using prescaler output clock as a clock source and the control registers that select the clock source Table 5 3 1 Peripheral Functions Used with Prescaler Output Cycle Clock Peripheral functions Control register External interrupt 0 Noise filter sampling clock External interrupt 1 Noise filter sampling clock Timer 0 Count clock CK0MD Timer 1 Count clock CK1MD Timer 2 Count clock CK2MD Timer 3 Count clock CK3MD Serial 0 Transfer clock SCOCKS 1 When the prescaler output clock source is used counting of prescaler should be enabled before starting the functions V 10 Operation Chapter5 Prescaler 5 3 2 Setup Example Setup Example Timer 0 count clock Select the clock of fosc 16 output from the prescaler 0 for the count clock of the timer 0 Example of the setup procedure is shown below Setup Procedure Description 1 Select the prescaler output 1 Select the prescaler output to fosc 16 by the CKOMD x 3F56 TMOPSC1 0 TMOBAS flag of the timer 0 bp2 1 TMOPSC1 0 01 prescale
387. ts counting mode STOP enabled Interrupt acceptance cycle Return factor interrupt occured Y Figure 2 4 3 Transition to from STANDBY Mode or higher than the mask level in PSW before transition to HALT or STOP mode it is impos 1 If the interrupt is enabled and interrupt priority level of the interrupt to be used is not equal to sible to return to CPU operation mode by maskable interrupt Standby Functions II 21 Chapter2 Basic CPU Transition to HALT modes The system transfers from NORMAL mode to HALTO mode and from SLOW mode to HALT1 mode The CPU stops operating but the oscillators remain operational There are two ways to leave a HALT mode a reset or an interrupt A reset produces a normal reset an interrupt an immediate return to the CPU state prior to the transition to the HALT mode The watchdog timer if enabled resumes counting Program 4 MOV x4 DO Set HALT mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Transition to STOP mode The system transfers from NORMAL mode to STOPO mode and from SLOW mode to STOP1 mode In both cases oscillation and the CPU are both halted There are two ways to leave a STOP mode a reset or an interrupt Program 5 MOV x 8 DO Set STOP mode MOV DO CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed
388. ts one count clock delay of the PWM source wave form To output the timer pulse output from the TM7O large current pin set the PSOMD1 flag of the port 5 output mode register PSOMD to 1 at the setup example 2 to set the P51 pin as a special function pin and set the P5DIR1 flag of the port 5 direction control register to 1 to set output mode In the initial state of the PWM output it is changed to H output from L output at the timing that the PWM operation is selected with the TM7OUT1 0 flag of the TM7MDS register As for timer 8 it can be selected with the TM8PWMF flag of TM8MD3 16 bit Standard PWM Output VII 31 Chapter 7 16 bit Timers 7 7 16 bit High Precision PWM Output Cycle Duty can be changed consecutively The TMnIO pin outputs high precision PWM output which is determined by the match timing of the timer binary counter and the compare register 1 and match timing of the binary counter and the compare register 2 It can be also output from the TMnO high current pin 7 7 1 Operation m16 bit High Precision PWM Output Operation Timer 7 Timer 8 The PWM waveform of an any cycle duty is generated by setting the cycle of PWM to the compare register 1 TMnOC1 and setting the duty of the H period to the compare register 2 TMnOC2 The 16 bit timer that provides high precision PWM output function is timer 7 iCount Timing of High Precision PWM Output at Normal Timer 7 Timer 8 Count clock
389. tween Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on If the input voltage supplies before is on alatch up occurs and causes the destruction of micro controller by a large current flow Input Input protection resistance Forward current generates N VDD Figure 1 6 5 VDD and Input Pin Voltage i The Relation between VDD and Reset Input Voltage After power supply is on reset pin voltage should be low for sufficient time before rising in order to be recognized as a reset signal Power voltage Reset pins Low level Under Input voltage Enough time is necessary to recognize it as reset Figure 1 6 6 Power Supply and Reset Input Voltage I 30 Cautions for Circuit Setup Chapter 1 Overview 1 6 4 Power Supply Circuit Cautions for Setting Circuits with VDD The MOS logic such a microcomputer is high speed and high density So the power circuit should be designed taking into consideration of AC line noise ripple caused by LED driver Figure 1 6 6 shows an example for a circuit with VDD Emitter follower type WAn Example for a Circuit of Supply Employing Emitter Follower Type Set condensors for noise filter near microcontroller power pins Microcontroller Vss For Noise filter Figure 1 6 7 An Example for a Circuit of Vpp Supply Emitter follower type Cautions for Circuit Setup 1 31 Chapter 1 Overview 1 6 5 Oscillators This LSI s o
390. uency OSC Input NORMAL mode 0 0 0 2 0 0 1 Forbidden 0 1 0 8 0 1 1 4 1 0 0 32 1 0 1 16 1 1 0 64 1 1 1 64 Figure 2 5 3 Setting Division Rate at NORMAL mode by combination of OSCSEL and OSCDBL Division factor for Low frequency XI XO Input SLOW mode OSCSEL1 OSCSELO 2 8 32 32 Figure 2 5 4 Setting Division Rate at SLOW mode by combination of OSCSEL 1 On clock switching set each flag of OSCDBL OSCSEL and OSCO individualy Even if z those flags are mapped on the same special functions register set three times II 24 Clock Switching Chapter 2 Basic CPU 2 6 Reset 2 6 1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin P27 is pulled to low minitiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low for at least four clock cycles NRST pin should be holded low for more than 4 clock cycles 200 ns at a 20 MHz NRST ae 4 clock cycles 200 ns at a 20 MHz ee Figure 2 6 1 Minimum Reset Pulse Width 2 Setting the P2OUT7 flag of the P2OUT register to 0 outputs low level at P27 NRST And transfering to reset by program software reset can be executed If the internal LSI is reset and register is initiated the P2OUT7 flag becomes 1 and reset is released Chapter 4 4 4 2 Registers This LSI
391. uency 1 2 to 1 21 of the high oscillation clock fosc or 1 23 to 1 24 of the low oscillation clock The BUZS 2 1 0 flag of the oscillation stabilization wait control register DLYCTR set the frequency of buzzer output The BUZOE flag of the oscillation stabili zation wait control register DLYCTR sets buzzer output ON OFF Operation iBuzzer Output Frequency The frequency of buzzer output is decided by the frequency of the high oscillation clock fosc or the low oscillation clock fx and the bit 6 5 4 BUZS2 BUZS1 BUZSO of the oscillation stabilization wait control register DLYCTR X 4 Table 10 3 1 Buzzer Output Frequency fosc fx BUZS2 BUZS1 BUZSO Buzzer output frequency 20 MHz 5 0 0 0 1 22 2 20 MHz 0 0 1 2 44 2 20 MHz 0 1 0 4 88 kHz 8 38 MHz 0 1 0 2 05 kHz 8 38 MHz 0 1 1 4 09 2 2 2 1 0 0 1 95 2 2 2 1 0 1 3 91 kHz 32 2 1 1 0 2 kHz 32 kHz 1 1 1 4 kHz Operation 10 3 2 Setup Example Chapter 10 Buzzer Buzzer outputs the square wave of 2 kHz from P06 pin It is used 8 38 MHz as the high oscillation clock fosc An example setup procedure with a description of each step is shown below Setup Procedure Description Set the buzzer frequency DLYCTR x 3F03 bp6 4 BUZS2 0 010 Set P06 pin POOUT x 3F 10 bp6 6 0 PODIR x 3F30 bp6 PODIR6 1 Buzzer outpu
392. uest IRQ4IE External interrupt enable flag 0 Disable interrupt Enable interrupt REDG4 External interrupt valid edge flag 0 Falling edge Rising edge IRQ4 IRQ4 LV1 LVO Interrupt level flag for external interrupt The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests Figure 3 2 5 External Interrupt 4 Control Register IRQ4ICR x 03FE6 R W Control Registers 21 Chapter3 Interrupts mTimer 0 Interrupt Control Register TM0ICR The timer 0 interrupt control register TM0ICR controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 7 6 5 4 3 2 1 0 Tuo _ _ TMOICR TMOIE TMOIR At reset 0 0 0 0 TMOIR Interrupt request flag 0 No interrupt request Generate interrupt request TMOIE Interrupt enable flag 0 Disable interrupt Enable interrupt TMO TMO LV1 LVO Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Figure 3 2 6 Timer 0 Interrupt Control Register TMOICR x O3FE9 R W 22 Control Registers Chapter 3 Interrupt
393. unt Figure 5 2 1 Prescaler Control Register PSCMD x O3F6F R W V 6 Control Registers Chapter 5 Prescaler The timer prescaler selection register selects the count clock used for 8 bit timer Timer 0 Prescaler Selection Register CKOMD 7 6 5 4 3 2 1 0 CKOMD TMOPSC1 TMOPSCO TMOBAS At reset XXX 5 1 5 TMOBAS Clock source selection fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 es alo Figure 5 2 2 0 Prescaler Selection Register CK0MD x 03F56 R W mTimer 1 prescaler selection register CK1MD 7 6 5 4 3 2 1 0 CK1MD 5 1 TM1PSCO TMIBAS At reset XXX TM1PSC1 TM1PSCO TM1BAS Clock source selection 0 0 fosc 4 1 fosc 16 0 0 fosc 2 1 05 215 0 16 2 1 15 8 Figure 5 2 3 1 Prescaler Selection Register CK1MD x 03F57 R W Control Registers V 7 Chapter5 Prescaler mTimer 2 Prescaler Selection Register CK2MD 2 1 0 CK2MD TM2PSC1 2 500 TM2BAS At reset XXX 2 5 1 2 5 0 TM2BAS source selection 0 0 fosc 4 1 fosc 16 0 fosc 32 1 fosc 64 0 i fs 2 i 1 fs 4 Figure
394. upper timer interrupt TMB8ICR x 3FF3 bp1 TM8IE 1 10 Start the lower timer operation TM8MD 1 88 bp4 TM8EN 1 11 Start the lower timer operation TM7MD 1 x 3F78 bp4 TM7EN 1 7 10 Set the TM7IE flag of the timer 7 interrupt control register TM7ICR to 0 to disable the interrupt Set the interrupt level by the TM8LV1 0 flag of the timer 8 interrupt control register TM8ICR If any interrupt request flag is already set clear it t Chapter 3 3 1 4 Interrupt Flag Setup Set the TM8IE flag of the TM8ICR register to 1 to enable the interrupt Set the TM8EN flag of the TM8MD 1 register to 1 to start timer 8 11 Set the TM7EN flag of the TM7MD1 register to 1 to start timer TM7BCL TM7BCH TM8BCL TM8BCH counts up from x 00000000 as a 32 bit timer When TM7BCL TM7BCH TM8BCL TM8BCH reaches the set value of TM7OC1L TM7OC1H TM8OC1L TM80C1H register the timer 8 interrupt request flag is set at the next count clock and the value of TM7BCL TM7BCH TM8BCL TM8BCH becomes x 00000000 to restarts count up Start upper timer operation before lower timer operation Cascade Connection VII 47 Time Base Chapter8 g_bit Free running Timer re Chapter 8 Time Base Timer 8 bit Free running Timer 8 1 Overview This LSI has a time base timer and a 8 bit free running timer timer 6 Time base timer is a 15
395. uring push opera tions and incremented during pop operations Ar reset the value of SP is undefined 15 0 2 1 6 Registers for Operation Registers for operation include four data registers DO D1 D2 D3 mData Registers 00 D1 D2 D3 Data registers DO to D3 are 8 bit general purpose registers that support all arithmetic logical and shift operations All registers can be used for data transfers with memory The four data registers may be paired to form the 16 bit data registers DWO D0 D1 and DW1 02 03 At reset the value of Dn is undefined Data DO DW0 registers D3 D2 Dwi Overview 7 2 Basic CPU 2 1 7 Processor Status Word Processor status word PSW is 8 bit register that stores flags for operation results interrupt mask level and maskable interrupt enable PSW is automatically pushed onto the stack when an interrupt occurs and is automatically popped when the interrupt service routine returns PSW IM1 IMO VF NF CF ZF Atreset 0000 0000 ZF Zero flag 0 Operation results are not all 0 1 All operation results are 0 CF Carry flag 0 A carry or a borrow from MSB did not occur A carry or a borrow from MSB occured NF Negative flag 0 MSB of operation results is 0 1 MSB operation results is 1 VF Overflow flag 0 Overflow did not occur 1 Overflow occured
396. ut XI 12 Operation Chapter11 Serial Interface 0 iStart Condition Setup The SCOSTE flag of the SCOMDO register sets if a start condition is enabled or not If a start condition is selected and input at communication a bit counter is cleared to restart the communication The start condition is regarded that when a clock line SBT pin is H data line SBI pin with 3 lines or SBO pin with 2 lines is changed from H to L Both the SCOSBOS flag and the SCOSBIS flag of the SCOMD1 register should be set to 0 before the start condition setup is changed WFirst Transfer bit Setup The SCODIR flag of the SCOMDO register can set the transfer first bit MSB first or LSB first can be selected m Transmission Data Buffer The transmission data buffer TXBUFO is a buffer of reserve that stores data to load the internal shift register Data to be transfered should be set to the transmission data buffer TXBUFO to be loaded to the internal shifr register automatically The first data loading to the internal shift register is done at the same timing of the data setting to TXBUFO iReceived Data Buffer The received data buffer RXBUFO is a buffer of reserve that pushed the received data in the internal shift register After the communication complete interrupt SCOTIRQ is generated all data stored in the inter nal shift register are stored to the received data buffer RXBUFO automatically RXBUFO can store data up to 1 byte RXBUFO is r
397. ve pins and LCD output pins Set unused pins output exclusive pins and LCD output pins open Output Figure 1 6 1 Unused Pins output exclusive pins and LCD output pins mUnused Pins only for input Insert some 10 kO resistor to unused pins only for input for pull up or pull down If the input is unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and causes power supply noise Input pin Some 10 Input Input Some 10 Input Through current Figure 1 6 2 Unused Pins only for input Current 0 5 Input voltage Pch Input pin Input X Nch 5 V Input inverter organization Input inverter characteristics Figure 1 6 3 Input Inverter Organization and Characteristics 1 28 Cautions for Circuit Setup Chapter 1 Overview mUnused pins for I O Unused I O pins should be set according to pins condition at reset If the output is high impedance Pch Nch transistor output off at reset to stabilize input set some 10 resistor to be pull up or pull down If the output is on at reset set them open Output control Output control some 10 Output OFF Output OFF Data Data Output OFF Output OFF Figure 1 6 4 Unused I O pins high impedance output at reset Cautions for Circuit Setup 1 29 Chapter 1 Overview 1 6 3 Power Supply The Relation be
398. w speed external devices and arbitration of bus access when using master devices on the external bus lines A functional block diagram of the bus controller is given below Instruction Interrupt queue Program address Operand address control Bus controller Interrupt bus Memory control register Memory mode setting Bus access wait control Address decode Bus arbiter Peripheral extension bus Er Internal Internal RAM BR BG peripheral functions External interface Internal ROM External expansion bus Figure 2 3 1 Functional Block Diagram of the Bus Controller Bus Interface 15 Chapter2 Basic CPU 2 3 2 Control Registers Bus interface is controlled by two registers the memory control register MEMCTR and the expansion address register EXADV mMemory Control Register 7 6 5 4 3 2 1 0 MEMCTR IOW1 IOW0 EXMEM PESERIED IRWE EXW1 EXW0 Atreset 11001011 RESERVED Set always 11 IRWE Set software write for interrupt request flag Writing software is forbidden 0 When data is written to each interrupt control register xxxICR the state of the interrupt request flag xxxIR will not change 1 Software write enable R
399. x 3F7C x 186a 8 Start the timer operation TM7MD1 x 3F78 bp4 TM7EN 1 5 Select fosc as the clock source by the TM7CK1 0 flag of the TM7MD1 register Also select 1 2 dividing as count clock source by the TM7PS1 0 flag Set the PWM output cycle to the timer 7 preset register 1 TM7PR1 To be 400 Hz by dividing 10 MHZ set as follows 25000 1 24999 61 7 At that time the same value is loaded to t timer 7 compare register 1 TM7OC1 and the timer 7 binary counter 7 is initialized to x 0000 Set the H period of the PWM output to the timer 7 preset register 2 TM7PR2 To bea 1 4 duty of 25000 dividing set as follows 25000 4 6250 186 At that time the same value is loaded to t timer 7 compare register 2 TM7OC2 Set the TM7EN flag of the TM7MD1 regist 1 to start timer 7 he he er to TM7BC counts up from x 0000 The PWM source waveform outputs H until TM7BC matches the set value of the 7 2 register Once they matches it outputs L After that TM7BC continues to count up Once TM7BC matches the TM7OC1 register to be cleared the PWM source waveform outputs again and TM7BC counts up from x 0000 again TM7IO pin outputs one count clock delay of the PWM source waveform To output the timer pulse output from the TM7O large current set the PSOMD1 flag of the port 5 output mode register PSOMD at the setup example 2 to 1
400. xxICR and the interrupt mask level in PSW Machine cycles i 12 12 12 till acceptance Values of the interrupt level flag PSW status All flags are The interrupt mask level xxxLVn are set to the interrupt after acceptance cleared flag in PSW is cleared mask level masking all interrupt to 0 to 00 requests with the same or the lower priority II 3 Overview 3 Interrupts 3 1 2 Block Diagram Interrupt IRQLVL 2 0 Il 4 Overview IRQNMI CPU core Vector 1 1 WDOG IRQOICR xxxLV1 0 Peripheral function xxxLV Interrupt Level xxxIE Interrupt Enable xxxIR Interrupt Request 7 6 5 4 xxLV1 0 Peripheral function xxxLV Interrupt Level xxxlE Interrupt Enable xxxlR Interrupt Request Figure 3 1 1 Interrupt Block Diagram Chapter 3 Interrupts 3 1 3 Operation interrupt Processing Sequence For interrupts other than reset the interrupt processing sequence consists of interrupt request interrupt acceptance and hardware processing The program counter PC and processor status word PSW and hard addressing data HA are sav
401. y flag SCOTEMP is automatically set to communicate continuously Data setup to TXBUF0 should be done till the communication complete interrupt SCOTIRQ is generated after the former data is set At master communication there is a sus pension of communication for 3 transfer clocks till the next transmission clock is output after the SCOTIRQ generation iBinput Edge Output Edge Setup The SCOCE 1 flag of the SCOMDO register set an output edge of the transmission data an input edge of the received data As the SCOCE1 flag 0 the transmission data is output at the falling edge and as 1 output at the rising edge As SCOCE1 0 the received data is received at the inversion edge to the output edge of transmission data and as 1 stored at the same edge Table 11 3 2 Transmission Data Output Edge and Received Data Input Edge SCOCE1 Transmission data output edge Received data input edge 0 Y A 1 4 Y mChange of Polarity of Transmission Reception Data It is possible to change the polarity of the transmission reception data When the SC0REN flag of SCOMDO register is set to 1 the polarity inverted input signals from the data input pins are loaded to reception shift register When the SCOTRN flag of SCOMDO register is set to 1 the inverted signals of the data set in the transmission buffer TXBUFO is output to the data output pins Operation XI 15 Chapter 11 Serial Interface 0 Clock Setup The S
402. y the POPLU register At reset the input mode is selected and pull up resistor is disabled high impedance output P10 28 vO TMOIO RMOUT VO port 1 6 bit CMOS tri state VO port P11 29 Each bit be set individually either input or P12 30 TM2IO output by the P1DIR register A pull up resistor for each P13 31 TM3IO bit can be selected individually by the P1PLU register P14 32 TM7IO At reset the input mode is selected and pull up resistor P15 33 TM8IO is disabled high impedance output 1 10 Pin Description Chapter 1 Overview Table 1 3 3 Pin Function Summary 2 6 Name No y o Other Function Function Description P20 34 Input IRQO Input port 2 3 bit input port P21 35 IRQ1 ACZ A pull up resistor for each bit can be selected P22 36 IRQ2 individually by the P2PLU register At reset pull up resistor is disabled 27 17 Input NRST VO port 2 Port P27 has an n channel open drain configuration When 0 is written and the reset is initiated by software a low level will be output P30 61 VO COM0 VO port 3 4 bit CMOS tri state VO port P31 62 1 Each bit be set individually as either input or P32 63 COM2 output by the P3DIR register A pull up resistor for each P33 64 bit selected individually by the P3PLU register At reset the input mode is selected and pull up resistor is disabled high impedance output P50 6 VO LEDO VO port
403. z LCDCK3 to 0 LCDTY1 to 0 LCD clock frame LCDclock frame LCDclock frame LCDclock flame LCDclock frame 00 1 4 duty 2441 Hz 1953 Hz 977 Hz 488 Hz 0000 01 1 3 duty 3255 Hz 2604 Hz 1302 Hz 651 Hz 08C1 2 1 2 duty 9766 Hz 4883 Hz 7813 HZ 3906 Hz 3906 Hz 195 Hz 1953 HZ 977 Hz 11 static 9766 Hz 7813 Hz 3906 Hz 1953 Hz 00 1 4 duty 1221 Hz 977 Hz 488 Hz 244 Hz 0001 01 1 3 duty 1628 1302 Hz 651 Hz 326 Hz 08 1 22 10 1 2 duty 4883 Hz 7441 Hz 3906 Hz 1953 Hz 1953 HZ 977 Hz 977 2 488 Hz 11 static 4883 Hz 3906 Hz 1953 Hz 977 Hz 00 1 4 duty 610 Hz 488 Hz 244 Hz 122 Hz 0010 01 1 3 duty 814 Hz 651 Hz 326 Hz 163 Hz OSC1 27 10 1 2 duty 2441Hz 1551 Hz 1953 HZ 977 Hz 977 Hz 488 Hz 244 11 static 2441 Hz 1953 Hz 977 Hz 488 Hz 00 1 4 duty 305 Hz 244 Hz 122 Hz 61 Hz 0011 01 1 3 duty 407 Hz 326 Hz 163 Hz 81 Hz 5 1 2 4 10 1 2 duty 1221 Hz lig uz 977 HZ uz 488 Hz 244 Hz M122 Hz 11 static 1221Hz 977 Hz 488 Hz 244 Hz 00 1 4 duty 153 Hz 122 Hz 61 Hz 31 Hz 0100 01 1 3 duty 203 Hz 163Hz 81 Hz 41 Hz OSC1 255 10 1 2 duty 610 Hz 488 Hz pz 244 12 12262 122 2 gu 11 static 610 Hz 488 Hz 244 Hz 122 Hz 00 1 4 duty 76 Hz 61 Hz 31 Hz 15Hz 0101 01 1 8 duty 102 Hz 81 Hz 41Hz 20 Hz 081 216 10 1 2 duty 305 Hz isa 24442 12262 12242 61Hz gru 11 static 305 Hz 244 Hz 122 Hz 61 Hz 00

MN101C527 LSI User`s Manual

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