PowerDNA DIO-403 User Manual - United Electronic Industries
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1. lt lt 8 United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 8 Adding these bits into configuration word causes layer to switch respective ports into outputs 3 3 Channel list settings Channel list is not currently supported for this layer 3 4 Layer specific commands and parameters There are three layer specific function used to access and control the state of I O lines e DgqAdv403SetIo This function selects which ports are inputs and which are outputs Ports are represented as individual bits port 0 bit 0 etc while 1 represents output Thus to configure ports 0 thru 3 as inputs and ports 4 and 5 as outputs Mask 110000b 0x30 e DqAdv403Write This function writes data to DIO 403 ports Firmware writes data into ports regardless of the state of the port input or output User can write set the state of the output line by writing into ports and then enable output on all ports simultaneously e DgAdv403Read This function returns the input status of all DIO 403 ports 3 5 Using layer in ACB mode The DIO 403 layer does not currently support Advanced Circular Buffer mode United Electronics Industries Inc www ueidag com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 9 3 6 Using layer in DMap mode include PDNA h 1 Start DQE engine ifndef WIN32 DgqInitDAQLib endif Start engine DqStartDQEngine 102. 00 10 amp pDge NULL open communication with IOM DqOpenIOM IOM_IPADDRO DQ UDP_DAQ PORT TIMEOUT DELAY amp DQRACEg Set hysteresis at this point DgAdv40xSetHyst hd0 DEVNIN 0x132 Ox2CA Receive IOM crucial identification data DqCmdEcho hd0 DQRdCfg for i 0 i lt DQ MAXDEVN i if DQRdCfg gt devmod i printf Model x Option x n DQRdCfg gt devmod il DQORdCfg gt soption i else break 2 Create and initialize host and IOM sides DqDmapCreate pDge hd0 amp pBcb UPDATE PERIOD amp dmapin amp dmapout 3 Add channels into DMap DqDmapSetEntry pBcb DEVNIN DQ _SSOIN 0 DQ ACB DATA RAW 1 amp ioffset DqDmapSetEntry pBcb DEVNOUT DQ SSOOUT 0 DQ ACB DATA RAW 1 amp ooffset DqDmapInitOps pBcb United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 10 DgeSetEvent pBcb DQ eDataAvailable DQ ePacketLost DQ eBufferError DQ ePacketOOB 4 Start operation DgeEnable TRUE amp pBcb 1 FALSE 5 Process data while keep looping DqeWaitForEvent amp pBcb 1 FALSE timeout amp eventsin if eventsin amp DQ eDataAvailable datarcv printf ndata 08x uint32 ioffset uint32 ooffset datarcv 6 Stop operation DgeEnable FALSE amp pBcb 1 FALSE 7 Clean up DqDmapDestroy pBcb DqStopDQEngine pDqe DqCloseIOM hd0 ifndef WIN3
3. 08 921 4600 Fax 508 668 2350 PowerDNA DIO 403 Layer li Table of Contents Introduction sssssssssesiesssersezessersesssvssireesennineereaeernineeeeebEeeeeeeeNNi es iii Organization of this manual cccceseeeeseeeeeeeeeeeeeeeeeeeeeeees iii CONVENTIONS vecaiisicesatusig tncstanvannnstsenbcucisvninnnanivseusisesminnniuubensede iv 1 The DIO 403 LAV CF isi tisiscsstiniecessiessintsieicinssinsssebitetesnastebisebitebainasieadinasd 1 1 1 Device architecture is icniicscrcntrcnccantversrentrercrantversrentvercrantranaranes 2 1 2 Layer capabilities siasisisinceisauees clsavenunderednwwdeatinnvduanscesdeanteavienssis 2 1 3 Layer connectors and WITFiING ecceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 3 2 Programming using the UeiDaq Framework ssssccccccccsessseesesesessnees 5 2 1 Creating a SCSSION sssseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeesenseeeeneeeeeeeees 5 2 2 Configuring the resource String eccceeeseseeeseeeeeeeeeeees 5 2 3 Configuring the timing ccccccesseseseeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 5 2 4 Reading Gata viiicsiecviicsisstinsneetsanenenseunnewstcunsenntsinsesnaunwenisineianes 6 2 5 Cleaning up the session ccccccssessseeeeeeeeeeeeeeeeeeeeeneeeeeeeees 6 3 Programming using the Low Level API 1000ssssssssseseeesseeees 7 3 1 Data representation ssesesssessssessssseesssessesssseseneeeeeeees 7 3 2 Configuration settings ccccccssessseeeeeeeeeeeeeesee
4. 1 2891 PowerDNA DIO 403 Layer Index 6 Index A Advanced Circular Buffer 8 APCHItECtULe oe ee eeeeeeeeceeeeeeees 2 B BUFET S Vises 3 hss ia 2 D data amp word SIZE oe eeeeeeeee 7 F features near E i 1 G glossary of terms ccceseeeeee 13 United Electronics Industries Inc Tel 781 821 2890 17 M mode PCB erat uidalais nnt ieoi 8 DIM ap fyccceti inns R 9 O over voltage protection 6 1 P programming low level commands xicasc5e arevekinsl aecueaes 8 layer configuration cee a T throughput rate eee eeeeereees 1 W WIDE aeaniee aoar 3 www ueidaq com Fax 781 821 2891
5. 2 DqCleanUpDAQLib endif United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 11 4 Appendix Appendix A Accessories The following cables boards and layers are available for the DIO 40x layer DNA CBL 62 2 5ft 62 way round shielded cable for connection to panel s DNA DIO O022 Accessory panel for PowerDNA DIO layers panel distributes 24 DIO channels into single group of 24 lines or in case with 48 DIO channels into 3 groups of 16 lines which connect to three Opto 22 compatible connectors DNA STP 62 62 channel screw terminal panel United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 5 Glossary A API bit byte C coupling crosstalk current drive capability current sourcing I input bias current input impedance input offset current United Electronics Industries Inc Tel 781 821 2890 13 Application Programming Interface a collection of high level language function calls that provide access the functions in a driver or other utility One binary digit either 0 or 1 Eight related bits of data an 8 bit binary number Also used to denote the amount of memory required to store one byte of data The manner in which a signal is connected from one location to another An unwanted signal on one channel due to an input on a different channel The amo
6. PowerDNA DIO 403 User Manual 48 channel Digital O layer for the PowerDNA Cube September 2008 Edition PN Man DNA DIO 403 0908 Version 3 3 Copyright 1998 2008 United Electronic Industries Inc All rights reserved United Electronic Industries Inc Version 3 3 PowerDNA DIO 403 Layer i No part of this publication may be reproduced stored in a retrieval system or transmitted in any form by any means electronic mechanical by photocopying recording or otherwise without prior written permission Information furnished in this manual is believed to be accurate and reliable However no responsibility is assumed for its use or for any infringements of patents or other rights of third parties that may result from its use All product names listed are trademarks or trade names of their respective companies See UEI s website for complete terms and conditions of sale http www ueidaq com company terms aspx Contacting United Electronics Industries Mailing Address 27 Renmar Avenue Walpole MA 02081 U S A For a list of our distributors and partners in the US and around the world please see http www ueidaq com partners Support Telephone 508 921 4600 Fax 508 668 2350 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidag com Web Site www ueidaq com FTP Site ftp ftp ueidaq com United Electronics Industries Inc www ueidag com Tel 5
7. direct access to PowerDNA DAQBios protocol and also allows you to access device registers directly We recommend that you use the UeiDaq framework see Section 2 above which is easier to use You should need to use the low level API only if you are using an operating system other than Windows 3 1 Data representation Internally the DIO 403 presents the state of its line in two 32 bit words each one contains 24 bits of data At the user level read or write data is presented in an array of six bytes Each byte represents one of the six I O ports available 3 2 Configuration settings Configuration settings are passed in the DgaCmdSetCfg function Not all configuration bits apply to DIO 403 layers Following bits are used define DQ LN MAPPED 1L lt lt 15 For WRRD DMAP devices automatically selected define DQ LN ACTIVE 1L lt lt 1 STS LED status define DQ LN ENABLED 1L lt lt 0 enable operations DQ LN ACTIVE is needed to switch on STS LED on the CPU layer DQ LN ENABLE enables all operations with the layer Layer specific bits are the follows enable ports 0 5 for write otherwise they are in tristate read define DQ _DI0403_ENPORTS5 1UL lt lt 13 define DQ DI0O403_ENPORT4 1UL lt lt 12 define DQ _DI0403_ENPORT3 1UL lt lt 11 define DQ _DI0403_ENPORT2 1UL lt lt 10 define DQ DI0403_ENPORT1 1UL lt lt 9 define DQ _DI0403_ENPORTO 1UL
8. eeeseeeeeeenees 7 3 3 Channel list settings cccccceeseseeeeeeeeeeeeeeeeseneeeeeneeeeeenees 8 3 4 Layer specific commands and parameters 000 8 3 5 Using layer in ACB MOdEC sssseeeeeeeeeeeeeneeeeeeeeeeeeeeeeeeeeees 8 3 6 Using layer in DMap MOdeC ecceeeeeeeeeeeeeeeeeeeeeeeeeeeeeeees 9 A PRD DONIIOIX PE EPE E E A T 11 E ET OLF lA E E E 13 GANG OX iiine anann aa a aaa e raa aaa 17 United Electronics Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 403 Layer iii Introduction This document outlines the feature set and use of the DIO 403 layer This layer is a digital input and output module for the PowerDNA I O Cube Organization of this manual This PowerDNA DIO 403 User Manual is organized as follows Introduction This chapter provides an overview of PowerDNA Digital Input Series board features the various models available and what you need to get started The DIO 403 layer This chapter provides an overview of the device architecture connectivity and logic of the DIO 403 layer Programming using the UeiDaq Framework High Level API This chapter provides an overview of the how to create a session configure the session for digital data acquisition output and format relevant output Programming using the Low Level API Low level API commands for configuring and using the DIO 403 series layer Appendix A Accessories This appendix provid
9. efer to the UeiDaq Framework User s Manual to learn how to use the other timing modes session ConfigureTimingForSimpleI0 2 4 Reading data Reading data from the DIO 403 is done by using a reader object The following sample code shows how to create a scaled reader object and read samples Create a reader and link it to the session s stream CUeiDigitalReader reader di_session GetDataStream read one scan the buffer must be big enough to contain one value per channel uInt16 data reader ReadSingleScan amp data Writing data is done by using a writer object The following sample shows how to create a writer object and write data Create a writer and link it to the session s stream CUeiDigitalWriter writer do_session GetDataStream write one scan the buffer must contain one value per channel uInt16 data OxXFEFE writer WriteSingleScan amp data 2 5 Cleaning up the session The session object will clean itself up when it goes out of scope or when it is destroyed However you can manually clean up the session to reuse the object with a different set of channels or parameters as follows session CleanUp United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 7 3 Programming using the Low Level API This section describes how to program the PowerDNA cube using the low level API The low level API offers
10. es a list of accessories available for DIO 403 series layer Appendix B Layer Verification This appendix outlines how to verify calibration for the DIO 403 series layer Glossary This is an alphabetical listing of key terms you will encounter in working with the PowerDNA cube and test systems in general Index This is an alphabetical listing of the topics covered in this manual United Electronics Industries Inc www ueidag com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 403 Layer iV Conventions To help you get the most out of this manual and our products please note that we use the following conventions Tips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can represent a command as in the following example You can instruct users how to run setup using a command such as setup exe United Electronics Industries Inc www ueidaq com Tel 508 921 4600 Fax 508 668 2350 PowerDNA DIO 403 Layer 1 1 The DIO 403 Layer The DIO 403 is a 48 line digital I O layer that operates at TTL levels Features Triggering available on digital inputs Change of state detection on
11. etting processed at a later time Software developer s kit a collection of drivers and utilities that allow engineers to write their own application programs see single ended www ueidaqg com Fax 781 821 2891 PowerDNA DIO 403 Layer single ended S s S sec system noise TCP IP throughput rate transfer rate 16 a term used to describe an analog input configuration where you measure each channel with respect to a common analog ground samples sec samples per second A measure of the amount of noise seen by an analog circuit or an A D when the analog inputs are grounded Transmission Control Protocol Internet Protocol the basic multi layer communication protocol of the Internet but that is also used in a private network either an intranet or an extranet The higher layer TCP manages the assembling of a message or file into smaller packets that are transmitted and received by a TCP layer that reassembles the packets into the original message IP handles the address portion of each packet so it gets to the right destination The flow of data measured in bytes sec for a given continuous operation The rate measured in bytes sec at which data is moved from a source to a destination after software initialization and setup operations the maximum rate at which the hardware can operate U UCT User counter timer United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 82
12. he user can select lines to be input or output with the granularity of eight lines at a time 1 2 Layer capabilities The DIO 403 layer is capable of single read write into the registers as well as continuous clock reads and writes Current firmware supports single read writes only United Electronics Industries Inc www ueidaq com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 3 1 3 Layer connectors and wiring Wiring of DIO 403 is very simple The user should wire input and output lines relative to DGND DB 62 female 62 pin connector N C DGND 5V 140mA DIO2 DIO1 DIOO DIOS DIO4 DIO3 DIO8 DIO7 DIO6 DION DIO10 DIOS DIO14 DIO13 DIO12 DIO17 DIO16 DIO15 DIO20 DIO19 DIO18 DIO23 DIO22 DI0O21 DIO26 DIO25 DIO24 DIO29 DIO28 DIO27 DIO32 DIO31 DIO30 DIO35 DIO34 DIO33 DIO38 DIO37 DIO36 DIO41 DIO40 DIO39 DIO44 DIO43 DIO42 DIO47 DIO46 DIO45 TRIG TRIG2 TRIGO DGND N C N C DGND DGND DGND DGND DGND 21 1 42 62 43 e TRIGx line is an input for external trigger United Electronics Industries Inc www ueidag com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 5 2 Programming using the UeiDaq Framework This section describes how to program the PowerDNA DIO 403 using the UeiDaq s framework API The UeiDaq framework is object oriented and its objects can be manipulated in the same manner from different development environments such as Visual C Visual Basic or LabVIEW The follo
13. inputs Onboard FIFO memory 128 32 bit words input 128 32 bit words output Pattern output I O throughput rate is 10k samples sec 20k aggregate Digital Lines 48 direction selectable in groups of 8 Output Drive Capacity 16 mA per pin i e 16mA per channel Input High Voltage 2 4V Input Low Voltage 0 8V Output High Voltage 4 5V 2mA 3V 16mA Output Low Voltage 0 5V 22Q current limiting resistors Timestamp resolution 15 ns Lines protected to 30V overvoltage peak to peak 7kV ESD Output protection 140mA PTC fuse Isolation 350Vims Power Consumption 1 2W 0 007W mA of load current United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 2 1 1 Device architecture Architecturally the DIO 403 is divided into a non isolated logic part and an isolated part with I O buffers Every line is protected from overvoltage and electrostatic discharge by a Harris SP720 overvoltage amp ESD electronic protection array One 22 current limiting resistor limits current in every line Control Logic 32 bit 66 MHz bus E Y v S c 2 w 2 A Optical Isolation T O lines are neither pulled up nor pulled down Thus connected equipment should actively drive these lines high or low An unconnected or not driven input line will remain in an arbitrary state The layer employs 16 543 buffers with two by eight architecture Thus t
14. splays computers electrical storms welders radio transmitters as well as internal sources such as semiconductors resistors and capacitors The technique of using an optoelectronic transmitter and receiver to transfer data without electrical continuity to eliminate high potential differences and transients www ueidaqg com Fax 781 821 2891 PowerDNA DIO 403 Layer output slew rate overhead P PID control PLC Polled mode R real time SDK SE United Electronics Industries Inc Tel 781 821 2890 15 The rate of change of an analog output voltage from one level to another The amount of computer processing resources such as time or memory required to accomplish a task A 3 term control algorithm combining proportional integral and derivative control actions Programmable logic controller a special purpose computer used in industrial monitoring and control applications PLCs typically have proprietary programming and networking protocols and special purpose digital and analog I O ports DAQ card operating mode whereby the user application queries the board about the status of various subsystems as needed A system in which the desired action takes place immediately when all input conditions are fulfilled it never has to wait for other processes to complete before it can start In DAQ terms it generally refers to the processing of data as it is acquired instead of being accumulated and g
15. unt of current a digital or analog output channel can source or sink while still operating within voltage range specifications The ability of a DAQ card to supply current for analog or digital output signals The current that flows into the inputs of a circuit The measured resistance and impedance between the input terminals of a circuit The difference in the input bias currents of the two inputs of an instrumentation amplifier www ueidaq com Fax 781 821 2891 PowerDNA DIO 403 Layer integral control isolation voltage Mbytes s N noise O optical isolation United Electronics Industries Inc Tel 781 821 2890 14 A control action that eliminates the offset inherent in proportional control The voltage that an isolated circuit can normally withstand usually specified from input to input and or from any input to the amplifier output or to the computer bus kilo the standard metric prefix for 1000 or 10 used with units of measure such as volts Hertz and meters mega the standard metric prefix for 1 million or 10 when used with units of measure such as volts and Hertz the prefix for 1 048 576 or 2 when used to quantify data or computer memory A unit for data transfer that means 1 million or 10 bytes sec An undesirable electrical signal Noise comes from external sources such as the AC power line motors generators transformers fluorescent lights soldering irons CRT di
16. wing section will focus on the C API but the concept stay the same no matter what programming language you use Please refer to the UeiDaq Framework User Manual to get more information on using other programming languages 2 1 Creating a session The Session object controls all operations on your PowerDNA device Therefore the first task is to create a session object CUeiSession session 2 2 Configuring the resource string The framework uses resource strings to select which device subsystem and channels to use within a session The resource string syntax is similar to a web URL lt device class gt lt IP address gt lt Device Id gt lt Subsystem gt lt Channel list gt For PowerDNA the device class is pdna For example the following resource string selects digital input channels 0 1 2 3 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Di0 3 session CreateDIChannel pdna 192 168 100 2 Dev1 Di0 3 2 3 Configuring the timing You can configure the DIO 403 to run in simple mode point by point or buffered mode ACB mode In simple mode the delay between samples is determined by software on the host computer In buffered mode the delay between samples is determined by the DIO 403 on board clock United Electronics Industries Inc www ueidaqg com Tel 781 821 2890 Fax 781 821 2891 PowerDNA DIO 403 Layer 6 The following sample shows how to configure the simple mode Please r
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