User`s Manual Addendum - Freescale Semiconductor
Contents
1. There are various corrections that apply to both Table 3 1 and Table 3 2 The same set of corrections applies to each table but the information is presented twice because the tables are arranged differently 1 2 1 Corrections to Table 3 1 Programmer s Memory Map Sorted by Address In Table 3 1 the following changes apply e At the address OXFFFFFIOA page 3 2 Change the Name to CSCTRLI Change the Description to Chip select control register 1 Change the Page Number to 6 17 e Create new table rows for the addresses OxFFFFF1OC and OxFFFFF150 page 3 2 See the corrected version of Table 3 1 for complete information e At the address OXFFFFF902 change the Reset Value to 0x0002 page 14 12 e At the address OXFFFFF912 change the Reset Value to 0x0002 page 14 12 e Inthe row for the LRRA register which is listed at the address OxFFFFFA29 make these corrections page 3 6 Change the Address to OxFFFFFA28 Change the Width to 16 Change the Reset Value to OxOOFF e At the address OXFFFFFBOC change the Width to 16 page 3 7 e At the address OXFFFFFB12 change the Width to 16 page 3 7 The following partial reproduction of Table 3 1 incorporates these corrections New and corrected information appears in red and is underlined Address Name Width Description Reset Value Page Number OxFFFFF10A CSCTRL1 16 Chip select control register 1 0x0000 6 17 AX2. change the Width to 16 page 3 12 e Inthe row for the UBAUD1 change the Reset Value to 0x0002 page 14 12 e In the row for the UBAUD2 change the Reset Value to 0x0002 page 14 12 MC68VZ328 Integrated Processor User s Manual Addendum A MOTOROLA Corrections to Chapter 6 Chip Select Logic The following version of portions of Table 3 2 incorporates these corrections New and corrected information appears in red and is underlined Name Address Width Description Reset Value Page Number CSCTRL1 OxFFFFF10A 16 Chip select control register 1 0x0000 6 17 CSCTRL2 OxFFFFF10C 16 Chip select control register 2 0x1000 6 18 CSCTRL3 OxFFFFF150 16 Chip select control register 3 0x9C00 6 20 LRRA OxFFFFFA28 16 LCD refresh rate adjustment register OxOOFF 8 18 RTCCTL OxFFFFFBOC 16 RTC control register 0x0080 11 10 STPWCH OxFFFFFB12 16 Stopwatch minutes register 0x003F 11 14 UBAUD1 OxFFFFF902 16 UART unit 1 baud control register 0x0002 14 12 UBAUD2 OxFFFFF912 16 UART unit 2 baud control register 0x0002 14 12 z GG m z 33 1 3 Corrections to Chapter 6 Chip Select Logic In Section 6 1 page 6 1 in the fourth paragraph the third sentence refers to CDL Change CDL to CSL for chip select logic 1 4 Corrections to Chapter 7 DRAM Controller In Table 7 9 SDRAM Bank Address Programming Examples page 7 17 the unit for the memory
3. 1 Errata in Multiple Locations Continued Error Locations Error Corrections Section 8 2 1 page 8 3 Table 8 12 page 8 17 The mnemonic that is used for the LCD Frame Marker signal FLM is incorrect The mnemonic for the LCD Frame Marker signal is LFRM Replace all occurrences of FLM with LFRM Section 8 2 5 page 8 9 Section 8 2 5 1 page 8 9 Table 8 19 page 8 21 The mnemonic that is used for the LCD Frame Marker signal FRM is incorrect The mnemonic for the LCD Frame Marker signal is LFRM Replace all occurrences of FRM with LFRM Section 8 2 1 1 page 8 3 LPOLCF register page 8 16 Table 8 16 page 8 16 The mnemonic that is used for the frame marker polarity bit FLMPOL s incorrect The mnemonic for the frame marker polarity bit is FRMPOL Replace all occurrences of FLMPOL with FRMPOL Section 8 2 page 8 2 Section 8 2 1 page 8 3 Section 8 2 5 page 8 9 Section 8 2 5 1 page 8 9 Table 8 12 page 8 17 Table 8 19 page 8 21 The mnemonic that is used for the LCD Line Pulse signal LP is incor rect The mnemonic for the LCD Line Pulse signal is LLP Replace all occurrences of LP with LLP Table 3 1 page 3 5 Table 3 2 page 3 13 Section 14 4 2 page14 12 The UBAUD1 reset value 0x003F is incorrect The reset value is 0x0002 See Section 1 2 and Section 1 8 of this document Table 3 1 page 3 6 Table 3 2 page 3 13 Se
4. MOTOROLA User s Manual Errata 3 Corrections to Chapter 3 Memory Map Address Name Width Description Reset Value eee OxFFFFF10C CSCTRL2 16 Chip select control register 2 0x1000 6 18 OxFFFFF150 CSCTRL3 16 Chip select control register 3 0x9C00 6 20 OxFFFFF902 UBAUD1 16 UART unit 1 baud control register 0x0002 14 12 OxFFFFF912 UBAUD2 16 UART unit 2 baud control register 0x0002 14 12 OxFFFFFA28 LRRA 16 LCD refresh rate adjustment register OxOOFF 8 18 OxFFFFFBOC RTCCTL 16 RTC control register 0x0080 11 10 OxFFFFFB12 STPWCH 16 Stopwatch minutes register 0x003F 11 14 1 2 2 Corrections to Table 3 2 Programmer s Memory Map Sorted by Register Name In Table 3 2 the following changes apply e Inthe row for the chip select control register whose name is listed as CSCR make these corrections page 3 8 Change the Name to CSCTRLI Change the Description to chip select control register 1 Change the Page Number to 6 17 e Add new rows for registers with the names CSCTRL2 and CSCTRL3 page 3 8 See the corrected version of Table 3 2 for complete information e In the row for the LRRA register page 3 9 Change the Address to OxFFFFFA28 Change the Width to 16 Change the Reset Value to OxOOFF e Inthe row for the RTCCTL register change the Width to 16 page 3 12 e In the row for the STPWCH register
5. OP RESE TRIG CONT S2 LO C PERR T EN L L T T OP TYPE rw rw rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 0 0 0 0 0 O RESET 0x0000 In Table 14 14 make the following changes In the seventh row Inthe Name column change the identification of the reserved bits from Bits 9 8 to Bit 9 In the Setting column change the text to This bit is reserved and should be set to 0 Just after the seventh row insert a new row that contains information for the RTS2 TRIG bit In the eighth row for bit 7 in the Setting column change the text to 0 RTS2 pin is controlled by the RTS2 bit 1 RTS2 pin is controlled by the receiver FIFO and RTS2 TRIG bit The following table excerpt displays the new and corrected information which appears in red and is underlined Reserved Reserved This bit is reserved and should be Bit 9 set to 0 RTS2 RTS2 Trigger Source Select This bit selects the control of 0 RTS2 pin is asserted when the TRIG the RTS2 pin when the RTS2 CONT bit bit 7 is 1 number of filled slots is equal Bits to RxFIFO level marker 1 RTS2 pinis asserted when only one slot is available in the receiver FIFO RTS2 RTS2 Control This bit selects the function of the RTS2 pin 0 RTS2 pin is controlled by the CONT RTS2 bit Bit 7 1 RTS2 pin is controlled by the receiver FIFO and RTS2 TRIG bit 10 MC68VZ328 Integrated Processor User s Manual A
6. and 2 This section contains corrections to Chapter 14 of the MC68VZ328 Integrated Processor User s Manual Table 5 presents a correction to Section 14 1 Introduction to the UARTs Table 5 Correction to Section 14 1 Errata Error Corrections Location Section 14 1 In the second bulleted list of features Add the following bullet to the end of the list Introductionto which is introduced by the statement The e The non integer prescaler value can the UARTs UART 2 module is an enhanced version of be programmed to be 1 which page 14 2 a UART 1 an additional feature is miss provides the maximum nonstandard baud rate of 2 07 MHz with the 16x sample clock 1 8 1 Corrections to Table 14 1 Non Integer Prescaler Values Table 14 1 s final row for the select field value of 111 erroneously omits information page 14 8 Corrections to this row are as follows e The Minimum Divisor value is 1 UART 2 only e The Maximum Divisor value is 1 UART 2 only The following table excerpt displays the corrected information which appears in red and is underlined Select Binary Minimum Divisor Maximum Divisor Step Size 111 1 UART 2 only 1 UART 2 only 1 8 2 Corrections to Section 14 4 2 UART 1 Baud Control Register In the Reset row of the register display the correct reset value is Ox0002 A corrected version of the register display follows wi
7. o 0 0 0 1 1 1 1 1 1 RESET 0x0002 1 8 5 Corrections to Section 14 4 11 UART 2 Transmitter Register In the Type row of the register display bits 10 and 9 are read only A corrected version of the register display follows with the new information in red and underlined UTX2 UART 2 Transmitter Register Ox FF FFF916 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 B FIFO FIFO TX SEND NO U CTS2 CTS2 TX DATA EMPTY HALF AVAIL BREAK CTS2 S STAT DELTA Y TYPE r r r rw rw r r rw W W W W W W wW w 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESET 0x0000 A MOTOROLA User s Manual Errata 9 Corrections to Chapter 14 Universal Asynchronous Receiver Transmitier 1 and 2 1 8 6 Corrections to Section 14 4 12 UART 2 Miscellaneous Register Bit 8 of this register is incorrectly represented as being reserved page 14 26 It is the RTS2 TRIG bit This correction affects the display of the UMISC2 register and Table 14 14 In the display of the UMISC2 register ignore the grey fill for bit 8 In the cell for the bit name abbreviation insert RTS2 TRIG In the TYPE row insert rw A corrected version of the register display follows with the new information in red and underlined UMISC2 UART 2 Miscellaneous Register Ox FF FFF918 Bi 14 13 12 11 10 9 8 F4 6 5 4 3 2 1 BIT 15 0 BAU BAU IRD D r ce to D res sts arse RT oa A po po TES
8. the trench etch thickness in MOS 13 No product function is affected 1 With regard to variations between masks some information in the MC68VZ328 Integrated Processor Us er s Manual rev 0 is specific only to mask 2K85C 2 3 4 Differences Between Masks 4K85C and 5K85C Table 10 on page 14 summarizes the differences between these two masks of the MC68VZ328 W MOTOROLA Additional Information 13 Table 10 Differences Between MC68VZ328 Masks 4K85C and 5K85C Feature Mask 4K85C Mask 5K85C Reset value of ID reg 0x5601 0x5700 ister OxFFFFFO04 SPI 1 SPI 1 transmits a wrong bit if a write This problem is fixed occurs to SP1 TXFIFO during data exchanges see the MC68VZ328 Chip Errata document P D function on PG3 The P D function on the PG3 HIZ P D pin is HIZ P D pin replaced by CSB1 1 With regard to variations between masks some information in the MC68VZ328 Integrated Processor Us er s Manual rev 0 is specific only to mask 2K85C 2 To enable the CSB1 function the Port G direction register s bit 3 should be set to 1 and the Port G select register s bit 3 should be set to 0 2 4 External Pin Pull down Consideration When connecting an external pull down resistor users are cautioned to use a resistor with a maximum value of 15 kohm This value ensures that a logic low level appears to the internal detection circuit Motorola reserves the right to make cha
9. values in the Application column is incorrect In the second row through the fifth row change all instances of Mbyte to Mbit The following version of Table 7 9 incorporates these corrections Corrected information appears in red and is underlined Application BNKADDH BNKADDL Remarks Make all SDRAM appear as one 11 11 None single bank Two banks of SDRAM for exam 00 11 Choose PA20 as bank selection address ple 16 Mbit A MOTOROLA User s Manual Errata Corrections to Chapter 8 LCD Controller Application BNKADDH BNKADDL Remarks Four banks of SDRAM for 01 10 Choose PA22 and PA21 as bank selection example 64 Mbit address Four banks of SDRAM for 01 10 Choose PA22 and PA23 as bank selection example 128 Mbit address Four banks of SDRAM for 10 10 Choose PA24 and PA23 as bank selection example 256 Mbit address Note These bits are all set in EDO RAM or Fast Page Mode allowing the use of only one page register 1 5 Corrections to Chapter 8 LCD Controller Table 3 identifies corrections to Chapter 8 of the MC68VZ328 Integrated Processor User s Manual Table 3 Corrections to Chapter 8 Error Location Error Correction Connecting the LCD Controller to an LCD Panel page 8 3 signal is provided lows Section 8 1 The third bullet refers to support for Delete the reference to color pan
10. 2 MC68VZ328 Integrated Processor User s Manual Addendum A MOTOROLA Summaries of Differences Between Masks 2 3 2 Differences Between Masks 2K85C and 3K85C Table 8 summarizes the differences between these two masks of the MC68VZ328 Table 8 Differences Between MC68VZ328 Masks 2K85C and 3K85C Feature Mask 2K85C Mask 3K85C Reset value of ID reg 0x5600 0x5601 ister OxFFFFFO04 SPI 1 There are problems with reading These problems are fixed SPI 1 RXFIFO and writing to SPI 1 TXFIFO during data exchanges see the MC68V2Z328 Chip Errata document EMUCS function on The EMUCS function on the PG4 EMUCS pin is PG4 EMUGCS pin replaced by CSCO The PB2 CSCO0 RASO pin remains unchanged It provides one more opening for CSCO The CSCO can function on the PG4 EMUCS pin even when the DRAM bit in chip select register D is set The memory map and function of CSCO are still con trolled by the registers related to chip select C 1 With regard to variations between masks some information in the MC68VZ328 Integrated Processor Us er s Manual rev 0 is specific only to mask 2K85C 2 3 3 Differences Between Masks 3K85C and 4K85C Table 9 summarizes the differences between these two masks of the MC68VZ328 Table 9 Differences Between MC68VZ328 Masks 3K85C and 4K85C Feature Mask 3K85C Mask 4K85C Wafer fabrication The wafer fabrication process has been changed to process standardize
11. ction 14 4 9 page14 22 The UBAUD2 reset value 0x003F is incorrect The reset value is 0x0002 See Section 1 2 and Section 1 8 of this document 1 1 Corrections to Chapter 1 Introduction Table 2 corrects errors in Chapter 1 of the MC68VZ328 Integrated Processor User s Manual Table 2 Corrections to Chapter 1 Error Location Error Correction Chapter 1 The third sentence of the second Delete this sentence Introduction paragraph reads as follows page 1 1 Additionally the new DragonBall VZ integrates the logic needed to support color LCD panels on chip Section 1 1 Under the bullet for Real time Delete this sub bullet Features of the clock sampling timer the first sub MC68VZ328 bullet states Separate power sup page 1 3 ply for the RTC 2 MC68VZ328 Integrated Processor User s Manual Addendum A MOTOROLA Corrections to Chapter 3 Memory Map Table 2 Corrections to Chapter 1 Continued Error Location Error Correction Section 1 1 Under the bullet for LCD control The sub bullet should read as follows Features of the ler the first sub bullet identifies MC68VZ328 support for color STN panels e LCD controller page 1 3 Software programmable screen size to support single nonsplit monochrome panel up to 640 x 512 pixels 1 2 Corrections to Chapter 3 Memory Map
12. ddendum AX MOTOROLA Corrections to Chapter 20 Mechanical Data and Ordering Information 1 8 7 Corrections to Table 14 15 UART 2 Non Integer Prescaler Register Description For the select field bits 10 8 Table 14 15 incorrectly presents the Setting for the option 111 as Disable the non integer prescaler page 14 28 The correct Setting for this option is Divide value is 1 The following table excerpt displays the correct information which appears in red and is underlined Name Description Setting SELECT Tap Selection This field selects atap from 000 Divide range is 2 to 3 127 128 in 1 128 steps Bits 10 8 the non integer divider 001 Divide range is 4 to 7 63 64 in 1 64 steps 010 Divide range is 8 to 15 31 82 in 1 32 steps 011 Divide range is 16 to 31 15 16 in 1 16 steps 100 Divide range is 32 to 63 7 8 in 1 8 steps 101 Divide range is 64 to 127 3 4 in 1 4 steps 110 Divide range is 128 to 255 1 2 in 1 2 steps 111 Divide value is 1 1 9 Corrections to Chapter 20 Mechanical Data and Ordering Information Table 6 corrects information in Figure 20 1 Table 6 Correction to Figure 20 1 Error Location Error Correction Figure 20 1 MC68VZ328 TQFP Pin Pin 73 is labeled as Vgs Pin 73 should be labeled as NC Assignments Top View page 20 2 2 Additional Information This section provides information that is not included i
13. els and all subsequent LCD Controller color text in this bullet The third bullet should read Features e Support for single e Support for single nonsplit monochrome page 8 1 nonsplit monochrome screen screen and color STN LCD panels through preprocessing of image data with software Section 8 2 1 No description of the CONTRAST Adda bullet describing the CONTRAST signal as fol CONTRAST The LCD CONTRAST output signal may be used to control the contrast of an LCD panel The CONTRAST signal provides a pulse width modulated signal whose pulse width and clock source are adjustable in software See Section 8 3 18 PWM Contrast Control Register for more information 1 6 Corrections to Chapter 12 General Purpose Timers Table 4 contains a correction to Chapter 12 of the MC68VZ328 Integrated Processor User s Manual MC68VZ328 Integrated Processor User s Manual Addendum AX MOTOROLA Corrections to Chapter 13 Serial Peripheral Interface 1 and 2 Table 4 Correction to Chapter 12 Error Location Error Correction Table 12 2 In the row for bit 4 the IRQEN interrupt Change the listed setting options from 2 bit page 12 7 request enable bit the Setting column pre values to 1 bit values as follows sents the bit as a 2 bit field 0 Disable the compare interrupt default 1 Enable the compare interrupt 1 7 Corrections to Chapter 13 Serial Peripheral Inter
14. face 1 and 2 This section contains corrections to Chapter 13 of the MC68VZ328 Integrated Processor User s Manual 1 7 1 Corrections to Section 13 3 1 SPI 1 Receive Data Register The SPI 1 receive data register is presented as an 8 bit register which is incorrect It is a 16 bit register On page 13 4 replace the SPIRXD register display with the following one SPIRXD SPI 1 Receive Data Register 0x FF FFF700 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 DATA TYPE r r r r r r r r r r r r r r r r RESET 0x0000 In addition in the Name column of Table 13 1 replace the identifier Bits 7 0 with Bits 15 0 1 7 2 Corrections to Section 13 3 2 SPI 1 Transmit Data Register The SPI 1 transmit data register is presented as an 8 bit register with a reset value of 0x00 which is incorrect It is a 16 bit register with a reset value of 0x0000 On page 13 5 replace the SPITXD register display with the following one SPITXD SPI 1 Transmit Data Register Ox FF FFF702 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BIT 0 DATA TYPE w w w w w w w w w w w w w w w w 0 0 0 0 RESET 0x0000 In addition in the Name column of Table 13 2 replace the identifier Bits 7 0 with Bits 15 0 A MOTOROLA User s Manual Errata 7 Corrections to Chapter 14 Universal Asynchronous Receiver Transmitier 1 and 2 1 8 Corrections to Chapter 14 Universal Asynchronous Receiver Transmitter 1
15. intelligence Q everywhere Addendum to MC68VZ328UMAD D Rev 7 10 2001 MC68V Z328 MC68VZ328 Integrated Processor User s Manual DragonBall VZ This addendum supplements and should be used in conjunction with the MC68VZ328 Integrated Processor User s Manual rev 0 order number MC68VZ328UM D Section 1 User s Manual Errata corrects information in the user s manual and Section 2 Additional Information provides supplemental information 1 User s Manual Errata Table 1 identifies and corrects errata that appear in more than one location in the user s manual Subsequent subsections identify and correct errata in specific chapters Table 1 Errata in Multiple Locations Error Locations Error Corrections Figure 2 1 page 2 2 Table 2 1 page 2 3 Section 2 8 page 2 7 Section 8 2 page 8 3 Section 8 2 1 page 8 3 Section 8 2 1 1 page 8 3 Figure 8 2 page 8 4 Table 10 14 page 10 13 Figure 19 13 page 19 17 Figure 19 14 page 19 18 Table 19 15 page 19 18 The mnemonic that is used for the LCD Frame Marker signal LFLM is incorrect The mnemonic for the LCD Frame Marker signal is LFRM Replace all occurrences of LFLM with LFRM Specifications and information herein are subject to change without notice Motorola Inc 2001 All rights reserved MOTOROLA V digitaldna Corrections to Chapter 1 Introduction Table
16. n the MC68VZ328 Integrated Processor User s Manual or that supplements information in the manual 2 1 System Power up Time and HIZ Pin Design Consideration The MC68VZ328 enters 68K test mode if the HIZ pin is toggled once when the reset signal is still asserted In this mode many MC68VZ328 signals become 68K core signals and the default reset states of the I O pins are overridden Some pins could oscillate due to the 68K core running with the 32 kHz clock provided through the normal oscillator circuit input To switch the MC68VZ328 back to normal mode apply a normal reset with the HIZ pin staying high after the power up Due to this consideration take special care in designing the HIZ pin connection W MOTOROLA Additional Information 11 VCO Operation Frequency Range Consideration Another situation can produce the same result If the system power up sequence has a long intermediate voltage level below 1 8 V the HIZ pin may have undetermined and toggling states when its voltage level is increased slowly with the power source due to internal pull up resistors This situation may wrongly instruct the MC68VZ328 to enter 68K test mode The I O pins will then become 68K core signals and oscillate Unexpected noise may be generated before a valid reset is re asserted after the system is fully powered up 2 2 VCO Operation Frequency Range Consideration The PLL design allows the VCO operation frequency range of 50 MHz to 80 MHz For best PLL
17. nges without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters which may be provided in Motorola data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal inj
18. performance the recommended range of operation is at 60 MHz to 70 MHz Therefore setting the nominal default frequency at 66 MHz already covers the allowable drift introduced by process variation Any change to PC or QC values in PLLFSR for other VCO frequencies is not recommended and may cause PLL stability issues or jitter 2 3 Summaries of Differences Between Masks The following subsections identify differences between various pairs of masks of the MC68VZ328 2 3 1 Differences Between Masks OK85C and 2K85C Table 7 summarizes the differences between these two masks of the MC68VZ328 Table 7 Differences Between MC68VZ328 Masks OK85C and 2K85C Feature Mask 0K85C Mask 2K85C Reset value of ID register 0x5601 0x5600 OxFFFFF004 ICEM control bits The ICEM control bits have a short The problem is fixed The SWEN bit in circuit problem see the MC68VZ328 the ICE module control register Chip Errata document The SWEN OxFFFFFDOC is bit 6 bit in the ICE module control register OxFFFFFDOC is bit 5 DTACK pin output function The DTACK pin output function is fixed The DTACK can be programmed to out put by setting bit O of the Port G direc tion register OxFFFFF430 to 1 Schmitt trigger hythesis of the The hythesis is enhanced RESET pin 1 With regard to variations between masks some information in the MC68VZ328 Integrated Processor Us er s Manual rev 0 is specific only to mask 2K85C 1
19. th the new information in red and underlined UBAUD1 UART 1 Baud Control Register 0x FF FFF902 BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO UCL BAU KDI D DIVIDE PRESCALER R SRC TYPE rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 RESET 0x0002 8 MC68VZ328 Integrated Processor User s Manual Addendum A MOTOROLA Corrections to Chapter 14 Universal Asynchronous Receiver Transmitter 1 and 2 1 8 3 Corrections to Section 14 4 4 UART 1 Transmitter Register In the Type row of the register display bits 10 and 9 are read only A corrected version of the register display follows with the new information in red and underlined UTX1 UART 1 Transmitter Register 0Ox FF FFF906 BIT 15 14 13 12 11 10 9 8 7654321 a FIFO FiFo 1X senp No CTS1 CTS1 EMPTY HALF wi BREAK cts1 BUSY stat DELTA TX DATA TYPE r r r rw rw r a rw W W W W W W W W 0 0 0 0 0 0 0 0000000 0 RESET 0x0000 1 8 4 Corrections to Section 14 4 9 UART 2 Baud Control Register In the Reset row of the register display the correct reset value is Ox0002 A corrected version of the register display follows with the new information in red and underlined UBAUD2 UART 2 Baud Control Register Ox FF FFF912 BIT15 14 13 12 11 10 9 8 76 5 4 3 2 1 BIT O UCLK BAUD DIR SRC DIVIDE PRESCALER TYPE rw rw rw rw rw rw rw rw rw rw rw 0 0 0 0 0
20. ury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regardina the design or manufacture of the part Motorola Inc is an Equal Opportunity Affirmative Action Employer Motorola the stylized and all other trademarks indicated as such herein are registered trademarks of Motorola Inc Registered U S Pat and Tm Office All other tradenames trademarks and registered trademarks are the property of their respective owners How to reach us USA EUROPE Locations Not Listed Motorola Literature Distribution P O Box 5405 Denver Colorado 80217 1 303 675 2140 or 1 800 441 2447 JAPAN Motorola Japan Ltd SPS Technical Information Center 3 20 1 Minami Azabu Minato ku Tokyo 106 8573 Japan 81 3 3440 3569 ASIA PACIFIC Motorola Semiconductors H K Ltd Silicon Harbour Centre 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 852 26668334 Technical Information Center 1 800 521 6274 HOME PAGE hitp www motorola com semiconductors AA MeTORVES MC68VZ328UMAD D
Download Pdf Manuals
Related Search