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1. 2 DoclD15962 Rev 14 Pin n mber Input Output o ei Se t o o 25 k o SE 28 Default alternate uu ag Pin name a 313 S S G Zn Zlo c SI e5 function 2 ail Ei O S gt 3 E s O aR SS ei eil OI a E ell sc 1255 s Lu uo OO I sl 2 1 1 C3 NRST PA1 1 0 X HS X Reset PA1 HSE oscillator input PA2 OSC_IN 3 2 2 BA USARTI DN vol X Xl X HS X X Port A2 n E e SPI1 MISO out HSE oscillator output 4 3 3 C4 PAYONG RETA 1 0 X X X HS X X Port A3 USART1 receive SPI1 RXJ SPI1 MOSIf master out slave in etum sik Ce 5 LCD_COM0 ADC1_IN2 VO 3 X X X HS X X Port Ad 151 Comparator 1 COMP1_INP pur e somp positive input Timer 2 break input PA4 TIM2_BKIN Timer 2 external TIM2 Ern TT trigger LCD COM 0 4 4 D3 LCD COMOO Oil X X X HS X X Port A4 ADC1 input 2 ADC1 IN2 COMP1 INP Comparator 1 positive input Timer 3 break input PA5 TIM3_BKIN TT LCD COM 1 ADC1 6 LCD COMIO ADCI IN1 I O X X X HS X X Port A5 input 1 COMP1 INP Comparator 1 positive input 29 142 Pinout and pin description STM8L151x4 6 STM8L152x4 6 Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued PAA Input Output o a S t o o 0 amp Z o o sl 53 Default alternate LL A g Pin name e 2 y 213 55
2. 1 millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 Al 0 000 0 020 0 050 0 0000 0 0008 0 0020 6 900 7 000 7 100 0 2717 0 2756 0 2795 6 900 7 000 7 100 0 2717 0 2756 0 2795 D2 5 500 5 600 5 700 0 2165 0 2205 0 2244 E2 5 500 5 600 5 700 0 2165 0 2205 0 2244 0 300 0 400 0 500 0 0118 0 0157 0 0197 T 0 152 0 0060 0 200 0 250 0 300 0 0079 0 0098 0 0118 e 0 500 0 0197 ddd 0 080 0 0031 Values in inches are converted from mm and rounded to 4 decimal digits Figure 47 UFQFPNAS 48 lead 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint A 7 30 6 20 7 30 Y HOOO gt o Y o 00000000000 D00000t gt BOD00000000 se FUUUUUUUUUUE 0 50 0 75 lt 5 80 gt lt q AOB9_FP_V2 1 2 Dimensions are expressed in millimeters DoclD15962 Rev 14 121 142 Package information STM8L151x4 6 STM8L152x4 6 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 48 UFQFPN48 marking example package top view Product identification Standard ST logo Revision code Pin 1 identifier MS37784V1 1 Parts marked as ES E or accompanied by an Engineering Sample notif
3. 1 Data based on characterization results not tested in production Static latch up e LU 3 complementary static tests are required on 6 parts to assess the latch up performance A supply overvoltage applied to each power supply pin and a current injection applied to each input output and configurable I O pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 61 Electrical sensitivities Symbol Parameter Class LU Static latch up class II DoclD15962 Rev 14 115 142 Package information STM8L151x4 6 STM8L152x4 6 10 10 1 10 2 116 142 Package information ECOPACK In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACKO is an ST trademark LQFP48 package information Figure 43 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE Cc NC DNE AUGE PLANE Yk S ch L1 IDENTIFICATION al 12 Ee 5B ME V2 1 Drawing is not to scale 2 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information 2 Table 62 LQFP48 48 pin 7 x 7 mm l
4. 12 Nov 2013 12 Updated Table WLCSP28 package mechanical data Updated Table Medium density STM8L15x pin description Updated Table 2 Medium density STM8L 15x low power device features and peripheral counts Added Figure Recommended LQFP48 footprint and Figure Recommended LQFP32 footprint DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Revision history 2 Table 69 Document revision history continued Date 12 Aug 2013 Revision Changes Changed the default setting value of OPT5 to 0x00 in Table Option byte addresses Added tTEMP BOR detector enabled and disabled characteristics in Table Embedded reset and power control block characteristics Updated E2 D2 and ddd in Table UFQFPN48 package mechanical data 21 Apr 2015 Added Figure 45 LQFP48 marking example package top view Figure 48 UFQFPN48 marking example package top view Figure 51 LQFP32 marking example package top view Figure 54 UFQFPN32 marking example package top view Figure 57 UFQFPN28 marking example package top view Figure 59 WLCSP28 marking example package top view DoclD15962 Rev 14 141 142 STM8L151x4 6 STM8L152x4 6 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST
5. ms erase write cycles on programmed byte t Programming time for 1 to 64 bytes block 3 ms write cycles on erased byte Ta 25 C Vpp 3 0 V 0 7 lorog Programming erasing consumption mA Ta 25 C Vpp 1 8 V 0 7 Data retention program memory after 10000 erase write cycles at TA 40 to 85 C Tret 85 C 301 6 suffix Data retention program memory after 10000 erase write cycles at Ta 40 to 125 C Tret 125 C 5 i 3 suffix tret years Data retention data memory after 300000 erase write cycles at Ta 40 to 85 C Tret 85 C 3001 S S 6 suffix Data retention data memory after 300000 erase write cycles at Ta 40 to 125 C Tret 125 C 5 3 suffix Erase write cycles program memory Ta 40 to 85 C 10 Naw 3 6 suffix 30061 kcycles Erase write cycles data memory TA 40 to H 25 C 4 3 suffix 1 Data based on characterization results not tested in production Conforming to JEDEC JESD22a117 The physical granularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte 4 Data based on characterization performed on the whole data memory 2 88 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters 9 3 6 9 3 7 2 1 O current injection characteristics As a general rule current injection to the I O pins due to external v
6. tc SCk th NSS e CPHA 0 2 CPOL 0 x CPHA 0 cPoL 1 ta SO 1 U SCK tdis S0 tf SCk MISO OUTP UT MOSI INPUT ai14134c Figure 35 SPI1 timing diagram slave mode and CPHA 1 NSS input f MISO OUTPUT MOSI INPUT SCK Input DO SE nF d oO a led A p n Pit i at Sl a E tdis SO ite lt a Lisou OUT d MSB IN BITI D LSB IN ai14135 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp 98 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Electrical parameters Figure 36 SPI1 timing diagram master mode High NSS input SCK Output SCK Output oo 32 it O LI l CPHA 1 d A CPOL 1 N FIN a te l l l tsu ze ail SE eege ie I SCK Da tw SCKL gt Te MISO usen GEET INPUT wenn BITS IN o em IN mt ar My OUTPUT wear 1 B 1 OUT s80 OU ai14136V2 1 Measurement points are done at CMOS levels 0 3Vpp and 0 7Vpp d DoclD15962 Rev 14 99 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 12C Inter IC control interface Subject to general operating conditions for Vpp fsysci ke and T4 unless otherwise specified The STMBL I2C interface I2C1 meets the requirements of the Standard IC communication protocol described in the following table with the restriction mentioned below Refer to I O port characteristics for more details on the input outp
7. TA 85 C 1 5 3 4 Ta 105 C 26 G Ta 125 C 51 12 TA 40 C to 25 C 14 34 LCD ON Je ee 15 33 static duty external Ta 85 C 1 9 4 3 Vico Ta 105 C 29 68 pe an Supply current in LSI RC TA 125 C 5 5 13 uA ab Active halt mode at 38 kHz Ta 40 Cto25C 19 43 LCD ON Ta 255 C 1 95 4 4 1 4 duty A external Ta 85 C 2 4 5 4 Vico Ta 105 C 3 4 7 6 Ta 125 C 6 0 15 Ta 40 Cto25 C 3 9 8 75 LCD ON TA 55 C 4 15 9 3 1 4 duty A internal Ta 85 C 4 5 10 2 Vico 9 Ta 105 C 5 6 13 5 Ta 125 C 6 8 16 3 78 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Electrical parameters Table 24 Total current consumption and timing in Active halt mode at Vpp 1 65 V to 3 6 V Symbol Parameter Conditions Typ Max Unit TA 40 C to 25 C 0 5 1 2 Ta 55 C 0 62 1 4 LCD OFF TA 85 C 0 88 2 1 TA 105 C 2 1 4 85 TA 125 C 4 8 11 TA 40 C to 25 C 0 85 1 9 LCDON IT 55 e 0 95 22 static duty external Ta 85 C 1 3 3 2 LSE external Vico Ta 105 C 2 3 5 3 Supply current in clock TA 125 C 5 0 12 e DD AH Active haitmode 32 768 kHz TA 40 Cto25 C 15 25 6 LCD ON TA 55 C 1 6 3 8 1 4 duty A external Ta 85 C 1 8 4 2 Vicp Y Ta 105 C 29 7 0 Ta 125 C 5 7 14 Ta A0 Cto25 C 34 7 6 LCD ON TA
8. Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued Pin numb r Input Output o S t o o 25 SE o amp 5 SS Default alternate uu ag Pin name e 2 y 213 SE oO OIZ a s o E 5 o o function L L A A a 2 x O n E e sl sl BO o z ES c oja o c ei a OI a 9 16 Gg 5 sis ind ira s OO I a sl Timer 2 external PB3 TIM2 ETRJ paa i d GE dek 116 CN SO 1 0 ju X X X HS X X Port B3 segment 13 ADC1 IN15 ADC1 IN15 COMP1 INP B Comparator 1 positive input 4 Timer 2 external PB3 TIM2 ETRJ trigger Timer 1 inverted UBE al TT channel 1 LCD segment 15 E2 LCD SEG132 1 0 X X X HS X X Port B3 ien NE ADC1 IN15 RTC ALARM RTC alarm Comparator COMP1_INP add P 1 positive input SPI1 master slave PB4 SP11 NSSI TT select LCD segment 28 LCD SEG140 O 3 X X9 x HS X X Port B4 14 ADC1 IN14 ADC1 IN14 COMP1 INP Comparator 1 positive input SPI1 master slave PB4 SP11 NSSf select LCD segment LCD SEG140 TT 6 ye 14 ADC1 IN14 17 16 D2 ADC1_IN14 1 0 gy X X X HS X X Port B4 DAC output COMP1 INP DAC OUT Comparator 1 positive input SPI1 clock LCD PB5 SPI1_SCK T segment 15 29 LCD SEG150 O X X X HS X X Port BS ADC1 IN13 ADC1_IN13 COMP1_INP Comparator 1 positive input SPI clock LCD PB5 SP
9. STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Reset Address Block Register label Register name status 0x00 5055 to Reserved area 27 bytes 0x00 506F 0x00 5070 DMA1 GCSR DMA1 global configuration amp status OXFC register 0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00 0x00 5072 to 0x00 5074 Reserved area 3 bytes 0x00 5075 DMA1_COCR DMA1 channel 0 configuration register 0x00 0x00 5076 DMA1_COSPR DMA1 channel 0 status amp priority register 0x00 0x00 5077 DMA1 CONDTR DMA1 number of data to transfer register 0x00 channel 0 DMA1 peripheral address high register 0x00 5078 DMA1_COPARH channel 0 0x52 0x00 5079 DMA1_COPARL DMA1 peripheral address low register 0x00 channel 0 0x00 507A DMA Reserved area 1 byte 0x00 507B DMA1_COMOARH DMA1 memory 0 address high register 0x00 channel 0 0x00 507C DMA1 COMOARL DMA1 memory 0 address low register 0x00 channel 0 0x00 507D to 0x00 507E Reserved area 2 bytes 0x00 507F DMA1_C1CR DMA1 channel 1 configuration register 0x00 0x00 5080 DMA1_C1SPR DMA1 channel 1 status amp priority register 0x00 0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register 0x00 channel 1 0x00 5082 DMA1_C1PARH DMA1 peripheral address high register 0x52 channel 1 0x00 5083 DMA1 C1PARL DMA1 peripheral addres
10. 26 38 56 kHz Luten LSI oscillator wakeup time E 2 2002 us LSI oscillator frequency Goen arift 0 C TA 85 C 12 11 Lo 1 Vop 1 65 V to 3 6 V Ta 40 to 125 C unless otherwise specified 2 Guaranteed by design not tested in production 3 This is a deviation for an individual part once the initial frequency has been measured 2 86 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters Figure 20 Typical LSI frequency vs Vpp LSI frequency kHz VDD V ai18219b 2 DoclD15962 Rev 14 87 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 5 Memory characteristics Ta 40 to 125 C unless otherwise specified Table 35 RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1 Halt mode or Reset 1 65 V 1 Minimum supply voltage without losing data stored in RAM in Halt mode or under Reset or in hardware registers only in Halt mode Guaranteed by characterization not tested in production Flash memory Table 36 Flash program and data EEPROM memory Symbol Parameter Conditions Min Typ MX Unit Vpp OPerating voltage f 16MHz 165 36 V DD all modes read write erase SYSCLK i i Programming time for 1 or 64 bytes block 6
11. 567 6 1 all peripherals OFF Ta 85 5 85 63 Ta 105 C 7 11 7 6 LSE external Ta 125 C 9 84 12 on kHz Ta 40 sol e to 25 C f Ta 55 C 6 10 6 4 with TIM2 active Ta 850 630 7 TA 105 C 7 55 84 TA2125 C 10 1 15 1 No floating I Os 2 Timer 2 clock enabled and counter running 3 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for external crystal the LSE consumption Ibp Lse must be added Refer to Table 32 74 142 DoclD15962 Rev 14 Unit 2 STM8L151x4 6 STM8L152x4 6 Electrical parameters Figure 15 Typ IDD LPR VS Vpp LSI clock Source 18 16 14 40 C mu 25 C 12 85 C 10 lpp LPR Lsi HA 4 2 0 1 8 2 1 2 6 3 1 3 6 Von V ai18216b Ly DoclD15962 Rev 14 75 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 In the following table data is based on characterization results unless otherwise specified Table 23 Total current consumption in Low power wait mode at Vpp 1 65 V to 3 6 V Symbol IDD LPW Parameter Supply current in Low power wait mode Conditions Typ Max Unit Ta 40 Cto25T 3 33 Ta 55 C 3 3 3 6 all peripherals OFF T4 85 C 4 4 5 Ta 105 C 67 8 LSI RC osc Ta 125 C 11 14 at 38 kHz Ta 40 CT to 25 CT 3 4 37 Ta 55 C 37 4 with
12. fe y life augmented STM8L151x4 STM8L151x6 STM8L152x4 STM8L152x6 8 bit ultra low power MCU up to 32 KB Flash 1 KB Data EEPROM RTC LCD timers USART I2C SPI ADC DAC comparators Features e Operating conditions Operating power supply range 1 8 V to 3 6 V down to 1 65 V at power down Temp range 40 C to 85 105 or 125 C e Low power features 5 low power modes Wait Low power run 5 1 UA Low power wait 3 uA Active halt with full RTC 1 3 uA Halt 350 nA Consumption 195 pA MHz 440 pA Ultra low leakage per 1 0 50 nA Fast wakeup from Halt 4 7 us e Advanced STM8 core Harvard architecture and 3 stage pipeline Max freq 16 MHz 16 CISC MIPS peak Up to 40 external interrupt sources e Reset and supply management Low power ultra safe BOR reset with 5 selectable thresholds Ultra low power POR PDR Programmable voltage detector PVD e Clock management 1to 16 MHz crystal oscillator 32 kHz crystal oscillator Internal 16 MHz factory trimmed RC Internal 38 kHz low consumption RC Clock security system e Low power RTC BCD calendar with alarm interrupt Auto wakeup from Halt w periodic interrupt e LCD up to 4x28 segments w step up converter e Memories Upto 32 KB of Flash program memory and 1 Kbyte of data EEPROM with ECC RWW Flexible write and read protection modes Upto 2 Kbyte of RAM e DMA 4channels supported perip
13. 0x00 50D2 0x00 50D3 WWE WWDG CR WWDG control register Ox7F 0x00 50D4 WWDG WR WWDR window register Ox7F 0x00 50D5 to Reserved area 11 bytes 00 50DF 0x00 50E0 IWDG KR IWDG key register OxXX 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50ES3 to Reserved area 13 bytes 0x00 50EF 0x00 50FO BEEP CSR1 BEEP control status register 1 0x00 0x00 50F1 0x00 50F2 BEEP Reserved area 2 bytes 0x00 50F3 BEEP_CSR2 BEEP control status register 2 Ox1F 0x00 50F4 to Reserved area 76 bytes 0x00 513F 44 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name Ween 0x00 5140 RTC TR1 Time register 1 Ox00 0x00 5141 RTC TR2 Time register 2 Ox00 0x00 5142 RTC TR3 Time register 3 0x00 0x00 5143 Reserved area 1 byte 0x00 5144 RTC DR1 Date register 1 0x01 0x00 5145 RTC DR2 Date register 2 0x21 0x00 5146 RTC DR3 Date register 3 0x00 0x00 5147 Reserved area 1 byte 0x00 5148 RTC CR1 Control register 1 0x00 0x00 5149 RTC_CR2 Control register 2 0x00 0x00 514A RTC CR3 Control register 3 0x00 0x00 514B Reserved area 1 byte 0x00 514C RTC ISR1 Initialization and status register 1 0x00 0x00 514D RTC_ISR
14. 40 1054 6 suffix version Ti Junction temperature 40 C lt TA lt 105 C 40 1100 C range 7 suffix version 40 C lt Ta lt 125 C 40 130 3 suffix version 1 fsvscik fepu 2 1 8 V at power up 1 65 V at power down if BOR is disabled 3 To calculate Pomax Ta use the formula Pomax TJmax TA OjA with Tjmax in this table and Oj4 in Thermal characteristics table 4 TJmax is given by the test limit Above this value the product behavior is not guaranteed 66 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Electrical parameters 9 3 2 Embedded reset and power control block characteristics Table 19 Embedded reset and power control block characteristics Symbol Parameter Conditions Min Typ Max Unit iius BOR detector 1 a Vpp rise time rate enabled 0 tvpp us F BOR detector Vpp fall 1 co 1 pp fall time rate enabled 20 Vpp rising BOR detector 3 enabled tremp Reset release delay ms Vpp rising BOR detector 1 E disabled Vppg Power down reset threshold Falling edge 1 302 1 50 1 65 V V Brown out reset threshold 0 Falling edge 1 67 1 70 1 74 BORO BOR_TH 2 0 000 Rising edge 1 69 1 75 1 80 V Brown out reset threshold 1 Falling edge 1 87 1 93 1 97 BOR Jl BOR TH 2 0 001 Rising edge 1 96 2 04 2 07 V Brown out reset threshold 3 Falling edge 2 22
15. A 0 540 0 570 0 600 0 0213 0 0224 0 0236 Al 0 190 0 0075 S A2 0 380 0 0150 pe 0 240 0 270 0 300 0 0094 0 0106 0 0118 D 1 668 1 703 1 738 0 0657 0 0670 0 0684 E 2 806 2 841 2 876 0 1105 0 1119 0 1132 e S 0 400 S 0 0157 B e1 S 1 200 0 0472 e2 2 400 0 0945 F 0 251 0 0099 G 0 222 0 0087 aaa 0 100 0 0039 bbb 0 100 0 0039 ccc 0 100 0 0039 ddd 0 050 0 0020 eee 0 050 0 0020 1 Values in inches are converted from mm and rounded to 4 decimal digits 2 Dimension is measured at the maximum bump diameter parallel to primary datum Z Device marking The following figure gives an example of topside marking orientation versus ball A1 identifier location DoclD15962 Rev 14 133 142 Package information STM8L151x4 6 STM8L152x4 6 134 142 Figure 59 WLCSP28 marking example package top view Dot ball 1 Product identification Date code Revision code MS37788V1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qual
16. C 0 4 90 C 130 C 03 5 gt a os 0 1 o o 1 2 3 4 lon mA ai18231 94 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Electrical parameters NRST pin Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 42 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit ViL NRST NRST input low level voltage 1 J Vss 0 8 ViH NRST NRST input high level voltage 1 1 4 Vpp lot 2mA V for 2 7 V Npp lt 3 6 V 7 VoL nrsT NRST output low level voltage 1 0 4 lot 1 5mA for Von lt 2 7 V 10 Vpp VHysT NRST input hysteresis 2 S mV RpuiNRST SE pull up equivalent resistor 30 45 60 kO VENRST NRST input filtered pulse 3 50 ns VNF NRST NRST input not filtered pulse 9 300 d Data based on characterization results not tested in production 200 mV min Data guaranteed by design not tested in production Figure 31 Typical NRST pull up resistance Rpy Vs Vpp 60 55 50 45 40 Pull up resistance kQ 35 30 1 8 2 22 24 26 28 3 3 2 34 36 Voo V ai18224b 2 DoclD15962 Rev 14 95 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 96 142 Figure 32 Typical NRST pull up current ly vs Vpp 120 40 C 100 m 25 C 85 C T 80 e 5 E 60 2 o o 2 40 2 a 20
17. LCD No 4x17 0 4x28 1 Basic 8 bit Timers General purpose 2 purp 16 bit 1 Advanced control 16 bit SPI 1 Communication oC 1 interfaces USART 1 GPIOs 269 30 28 or 29 1 3 41 12 bit synchronized ADC 1 1 1 number of channels 18 22 9 or 21 1 25 12 Bit DAC number of channels 1 1 Comparators COMP1 COMP2 2 Others CPU frequency RTC window watchdog independent watchdog 16 MHz and 38 kHz internal RC 1 to 16 MHz and 32 kHz external oscillator 16 MHz Operating voltage 1 8 V to 3 6 V down to 1 65 V at power down Operating temperature 40 to 85 C 40 to 105 C 40 to 125 C Packages 1 STM8L152xx versions only 2 STM8L151xx versions only UFQFPN28 4x4 LQFP48 0 6 mm thickness UFQFPNAS 4x4 WLCSP28 0 6 mm thickness LQFP32 7x7 UFQFPN32 5x5 0 6 mm thickness 3 The number of GPIOs given in this table includes the NRST PA1 pin but the application can use the NRST PA1 pin as general purpose output only PA1 12 142 d DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Description 2 2 Note 2 Ultra low power continuum The ultra low power medium densitySTM8L151x4 6 and STM8L152x4 6 devices are fully pin to pin software and feature compatible Besides the full compatibility within the family the devices are part of STMicroelectronics microcontrollers ultra low power strategy which also includes STM8L101xx and S
18. V13 Segment Common 1 3 level voltage 1 3Vi cp S V Vo Segment Common lowest level voltage 0 V 1 LCD enabled with 3 V internal booster LCD CR1 0x08 1 4 duty 1 3 bias division ratio 64 all pixels active no LCD connected Run is the total high value resistive network Rin is the total low value resistive network VLCD external capacitor STM8L152xx only The application can achieve a stabilized LCD reference voltage by connecting an external capacitor Cgxr to the Vi cp pin Geer is specified in Table 45 DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Electrical parameters 9 3 10 Embedded reference voltage In the following table data is based on characterization results not tested in production unless otherwise specified Table 46 Reference voltage characteristics Symbol Parameter Conditions Min Typ Max Unit eae ee T voltage 14 uA AE w Zenn 1 os m ya VREFINT out Reference voltage output 1 2020 1 224 1 242 V Internal reference voltage low lLPBUF power buffer consumption used for z 730 1200 nA comparators or output IReFrour Buffer output current 3 1 uA CREFOUT Reference voltage output load z E 50 pF Internal reference voltage startup tVREFINT time i 2 3 ms Internal reference voltage buffer teuren 5 S g 10 us startup time once enabled 1 Accuracy of Vrerint Stored in the ACCv
19. down to 1 65 V at power down external power supply for I Os and for the internal regulator Provided externally through Von pins the corresponding ground pin is Vgg Vssa VppA 1 8 to 3 6 V down to 1 65 V at power down external power supplies for analog peripherals minimum voltage to be applied to Vppa is 1 8 V when the ADC1 is used Vppa and Vssa must be connected to Vpp and Vasen respectively e Vgso Vppo 1 8 to 3 6 V down to 1 65 V at power down external power supplies for l Os Vpp2 and Vgs must be connected to Vpp and Vas respectively e Vngr Vrer for ADC1 external reference voltage for ADC1 Must be provided externally through Vpee and Vgpgr pin e VrEr for DAC external voltage reference for DAC must be provided externally through VREF Power supply supervisor The device has an integrated ZEROPOWER power on reset POR power down reset PDR coupled with a brownout reset BOR circuitry At power on BOR is always active and ensures proper operation starting from 1 8 V After the 1 8 V BOR threshold is reached the option byte loading process starts either to confirm or modify default thresholds or to disable BOR permanently in which case the Vpp min value at power down is 1 65 V Five BOR thresholds are available through option bytes starting from 1 8 V to 3 V To reduce the power consumption in Halt mode it is possible to automatically switch off the internal reference voltage and conse
20. of lio l o ports and control pins must not exceed lyss Table 41 Output driving current PAO with high sink LED driver capability UO Symbol Parameter Conditions Min Max Unit Type 1 lio 20 mA c VoL Output low level voltage for an I O pin Vpp 2 0 V 0 45 V The lig current sunk must always respect the absolute maximum rating specified in Table 16 and the sum of lio l o ports and control pins must not exceed lyss 2 DoclD15962 Rev 14 93 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 Figure 25 Typ VoL Vpp 3 0 V high sink ports 40 C VoL V 0 2 4 6 8 10 12 14 16 18 20 Jo mA ai18226 Figure 26 Typ Vo O Vpp 1 8 V high sink ports 4 lo mA ai18227 Figure 27 Typ Vo O Vpp 3 0 V true open drain ports 40 C 0 4 0 4 25 C 40 C 0 3 iis 0 3 e e d jo z s 90 C 3 3 130 C 0 2 0 2 0 1 a aah 0 1 ft D DE 0 1 2 3 4 5 6 7 o 1 2 3 4 5 6 7 lo mA lo mA ai18228 ai18229 Figure 28 Typ Vo O Vpp 1 8 V true open drain ports Figure 29 Typ Vpp Von Y Vpp 3 0 V high sink ports 1 75 40 C 15 25 C z 1 25 90 C 3 130 C gt 1 8 gt 0 75 0 5 0 25 oF 0 a 4 6 8 10 12 14 16 18 20 lon MA ai12830 Figure 30 Typ Vpp Vou Y Vpp 1 8 V high sink ports 40 C 25
21. 0 1 8 1 95 2 1 2 25 24 2 55 2 7 285 3 3 15 33 3 45 3 6 Von V ai18225b The reset network shown in Figure 33 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vu wrst max level specified in Table 42 Otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If the NRST signal is used to reset the external circuitry attention must be paid to the charge discharge time of the external capacitor to fulfill the external devices reset timing conditions The minimum recommended capacity is 10 nF Figure 33 Recommended NRST pin configuration External reset circuit Internal reset STM8 Optional MS34928V1 d DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters 9 3 8 Communication interfaces SPI1 Serial peripheral interface Unless otherwise specified the parameters given in Table 43 are derived from tests performed under ambient temperature fsysc x frequency and Vpp supply voltage conditions summarized in Section 9 3 1 Refer to 1 O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 43 SPI characteristics Symbol Parameter
22. 0x00 8030 11 EXTIS External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTIA External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 16 LCD LCD interrupt S Yes Yes 0x00 8048 CLK system clock switch 17 a ri CSS interrupt Yes Yes 0x00 804C TIM 1 break DAC COMP1 interrupt COMP1 COMP2 interrupt 18 COMP2 ACD1 end of conversion Yes Yes Yes Yes 0x00 8050 ADC1 analog watchdog overrun interrupt Ly DoclD15962 Rev 14 57 142 Interrupt vector mapping STM8L151x4 6 STM8L152x4 6 Table 11 Interrupt mapping continued Wakeu Wakeup Wakeup Wakeup IRQ Source Description from SCH from from Wait from Wait Vector No block P Active halt WFI WFE address mode 1 mode mode mode 18 me Me update OVeIT OW Yes Yes 0x00 8054 trigger break interrupt 20 mud TIME capture Yes Yes 0x00 8058 compare interrupt sil mus EE EEN Yes Yes 0x00 805C trigger break interrupt 22 qima MS capture Yes Yes 0x00 8060 compare interrupt 93 TIMA Update overflow trigger Yes 0x00 8064 COM 24 TIM1 Capture compare 2 S Yes 0x00 8068 25 mu EMP update overflow Yes Yes 0x00 806C trigger interrupt SPI1 TX buffer empty 26 SPI1 RX buffer not empty Yes Yes Yes Yes 0x00 8070 error wakeup interrupt US
23. 0x02 Page 0 and 1 reserved for the UBC and read write protected Page 0 contains only the interrupt vectors 0x03 Page 0 to 2 reserved for UBC memory write protected OxFF Page 0 to 254 reserved for UBC memory write protected Refer to User boot code section in the STM8L15x and STM8L16x reference manual RM0031 OPT2 Reserved IWDG_HW Independent watchdog 0 Independent watchdog activated by software 1 Independent watchdog activated by hardware IWDG HALT Independent window watchdog off on Halt Active halt 0 Independent watchdog continues running in Halt Active halt mode 1 Independent watchdog stopped in Halt Active halt mode OPT1 OPT3 WWDG_HW Window watchdog 0 Window watchdog activated by software 1 Window watchdog activated by hardware WWDG_HALT Window window watchdog reset on Halt Active halt 0 Window watchdog stopped in Halt mode 1 Window watchdog generates a reset when MCU enters Halt mode HSECNT Number of HSE oscillator stabilization clock cycles 0x00 1 clock cycle 0x01 16 clock cycles 0x10 512 clock cycles 0x11 4096 clock cycles OPT4 LSECNT Number of LSE oscillator stabilization clock cycles 0x00 1 clock cycle 0x01 16 clock cycles 0x10 512 clock cycles 0x11 4096 clock cycles Refer to Table 32 LSE oscillator characteristics on page 84 d 60 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Option bytes Table 13 Option byte description c
24. 24 hour week day date month year in BCD binary coded decimal format Correction for 28 29 leap year 30 and 31 day months are made automatically It provides a programmable alarm and programmable periodic interrupts with wakeup from Halt capability e Periodic wakeup time using the 32 768 kHz LSE with the lowest resolution of 61 us is from min 122 us to max 3 9 s With a different resolution the wakeup time can reach 36 hours e Periodic alarms based on the calendar can also be generated from every second to every year 2 DoclD15962 Rev 14 19 142 Functional overview STM8L151x4 6 STM8L152x4 6 3 6 Note 3 7 3 8 3 9 20 142 LCD Liquid crystal display The liquid crystal display drives up to 4 common terminals and up to 28 segment terminals to drive up to 112 pixels e Internal step up converter to guarantee contrast control whatever Vpp e Static 1 2 1 3 1 4 duty supported e Static 1 2 1 3 bias supported e Phase inversion to reduce power consumption and EMI e Up to 4 pixels which can programmed to blink e The LCD controller can operate in Halt mode Unnecessary segments and common pins can be used as general I O pins Memories The medium density STM8L151x4 6 and STM8L152x4 6 devices have the following main features e Upto 2 Kbyte of RAM e The non volatile memory is divided into three arrays Up to 32 Kbyte of medium density embedded Flash program memory 1 Kbyte o
25. 28 PB4 pp1 010 270 PB3 VppA O11 260 PB2 Vrer O12 250PB1 18 14 15 16 17 18 19 20 21 22 2324 DUN DOTrNOTNOT NANO ou uuuiuudaadaadmn 300000000000 MS32629V1 DoclD15962 Rev 14 27 142 Pinout and pin description STM8L151x4 6 STM8L152x4 6 28 142 Figure 8 STM8L152K4 STM8L152K6 32 pin package pinout with LCD cont o ole o TOOOQO Oo O OO DO OD DD Oo 0 0 EE E TT 32 31 30 29 28 27 26 25 NRST PA1 E23 sabor PA2 22 23 3PD6 PA3E 33 2 1PD5 Ad 2 Gp PASE 5 201 PB7 PA6r 6 19 1 PB6 Vest 18C1PB5 y we Maps 9 10 11 12 13 14 15 16 1 PB4 DEN oO e N 2 onaaoammmnmdm TITOO OO O O O gt ai18252b 1 Example given for the UFQFPN32 package DoclD15962 Rev 14 The pinout is the same for the LQFP32 package d STM8L151x4 6 STM8L152x4 6 Pinout and pin description Table 4 Legend abbreviation for table 5 Type l input O output S power supply FT Five volt tolerant Level TT 3 6 V tolerant Output HS high sink source 20 mA Port and control nput float floating wou weak pull up configuration Output T true open drain OD open drain PP push pull Bold X pin state after reset release Reset state Unless otherwise specified the pin state is the same during the reset phase i e under reset and after internal reset release i e at reset state Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description
26. 3 3 15 33 3 45 3 6 Von V ai18223b d DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters Output driving current Subject to general operating conditions for Vpp and T4 unless otherwise specified Table 39 Output driving current high sink ports 19 Symbol Parameter Conditions Min Max Unit Type lio 2 mA 0 45 V Vpp 3 0 V i Guiputiowevalvatage toran iep 10774 MG 0 45 v VoL utput low level voltage for an pin Vnpe 1 8 V m lio 10 mA 07 V e Vpp 3 0 V i E o lio 2 mA Vpp 0 4 T Vopz3ov DD 045 M lip 2 1 mA 2 i j Io 0 Vou Output high level voltage for an I O pin Von 1 8 V Vpp 0 45 V lio 10 mA V 0 7 V Vpp 3 0 V EE 1 The lig current sunk must always respect the absolute maximum rating specified in Table 16 and the sum of lio io ports and control pins must not exceed lyss 2 The lig current sourced must always respect the absolute maximum rating specified in Table 16 and the sum of lio I O ports and control pins must not exceed lypp Table 40 Output driving current true open drain ports Sd Symbol Parameter Conditions Min Max Unit ype lo 3 mA c IO B Vops20V ome c Vo Output low level voltage for an I O pin V o lio 1 mA Q 0 45 Vpp 1 8 V i The lig current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
27. 3 6 V 8 2 Unit kQ 1 2 DoclD15962 Rev 14 32 or 28 pin packages only The DAC channel can be routed either on PB4 PB5 or PB6 using the routing interface I O switch registers 107 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 14 12 bit ADC1 characteristics In the following table data is guaranteed by design not tested in production Table 53 ADC1 characteristics Symbol Parameter Conditions Min Typ Max Unit Vppa Analog supply voltage 1 8 3 6 V Wax Reference supply 2 4 V Nppas 3 6 V 2 4 i VDDA V voltage 1 8 V lt Vopa lt 2 4 V Viena V Vaer Lower reference voltage VssA V Current on the VDDA z S VDDA input pin 1000 1450 yA 700 i i NU m Current on the VREF peak per 400 input pin 450 5 ay HA average Conversion voltage VAIN range 9 S 0 VREF V TA Temperature range 40 125 C i on PFO fast channel Rai External resistance on 509 kQ VAIN on all other channels on PFO fast channel Cape Internal sample and hold 16 pF capacitor on all other channels lt PA DDA gt 0 320 16 MHz Ga ADC sampling clock without zooming frequency lt lt IUDA n 0 320 8 MHz with zooming VAIN on PFO fast 106 MHz channel fconv 12 bit conversion rate V T AIN 0N a other 7 S 4 5 channels 760 Ane External trigger TRIG frequency conv fanc Har External trigger
28. Code giving 0 2 V and Vppa 0 2 V when buffer is OFF For 48 pin packages only For 28 pin and 32 pin packages DAC output buffer must be kept off and no load must be In the following table data is guaranteed by design not tested in production Table 52 DAC output on PB4 PB5 PB6 Symbol Parameter Conditions Typ Max Unit Rp 25 kQ C s50 pF iE 3 2 i DNL Differential non linearity DAGOUT BUerON No load 15 3 DACOUT buffer OFF Ri 25 kO Cis 50 pF o 4 2 INL Integral non linearity DAC OUT BukaroN 12 bit No load 2 4 LSB DACOUT buffer OFF RL 25 kO Cis 50 pF 10 425 Offset Offset error DACOUT buffer ON No load DACOUT buffer OFF 5 zh Offset Offset error at Code 1 DACOUT buffer OFF 1 5 5 R29 KA IR Lanz 0 2 0 5 U 1 U U 2 U Gain error Gain error DACOUT buffer ON No load DACOUT buffer OFF 902 0104 Ri gt 5 kQ CLs 50 pF 12 30 2 bi TUE Total unadjusted error DACOUT Dungi ON js No load 8 12 DACOUT buffer OFF Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023 Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and OxFFF Symbol Rint Parameter Internal resistance between DAC output and PB4 PB5 PB6 output Conditions Max 2 7 V lt Vpp lt 3 6 V 1 4 2 4 V lt Vpp lt 3 6 V 1 6 2 0 V lt Vpp lt 3 6 V 3 2 1 8 V lt Vpp lt
29. Conditions Min Max Unit Master mode 0 8 fsck SP11 clock frequency MHz Tosch Slave mode 0 8 GAN S clock rise and fall Capacitive load C 30 pF 30 f SCK tsunss NSS setup time Slave mode 4x lfevscik wuel NSS hold time Slave mode 80 twscKH o SCK hi Master mode igh and low time 105 145 tw SCKL g fMASTER 8 MHz fsck 4 MHz t 2 Master mode 30 a suMDo Data input setup time tsu Sl Slave mode 3 t 2 Master mode 15 AMI Data input hold time ns this Slave mode 0 taso PG Data output access time Slave mode 3x l fevscik tasso Data output disable time Slave mode 30 huso 2 Data output valid time Slave mode after enable edge 60 a Master mode after enable 2 tuno Data output valid time edge 20 inso Slave mode after enable edge 15 2 Pata output hold time Master mode after enable th mo edge 5 1 Parameters are given by selecting 10 MHz I O output frequency 2 Values based on design simulation and or characterization results and not tested in production 3 Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in Hi Z Ly DoclD15962 Rev 14 97 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 Figure 34 SPI1 timing diagram slave mode and CPHA 0 NSS input
30. DMA1 peripheral address high register me aye C3M1ARH channel 3 0x40 DMA1_C3PARL_ DMA1 peripheral address low register 0x00 399 C3M1ARL channel 3 PR 0x00 5098 Reserved area 1 byte 0x00 5099 DMA1 C3M0ARH DMA1 memory O address high register 0x00 channel 3 0x00 509A DMA1 C3MOARL DMA1 memory 0 address low register 0x00 channel 3 0x00 509B to 0x00 509D Reserved area 3 bytes 0x00 509E SYSCFG RMPCR1 Remapping register 1 0x00 SYSCFG 0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00 42 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name are 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00 0x00 50A3 eae EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00 0x00 50A6 WEE CR1 WFE control register 1 0x00 0x00 50A7 WFE WFE_CR2 WFE control register 2 0x00 0x00 50A8 WFE_CR3 WFE control register 3 0x00 0x00 50A9 to Reserved area 7 bytes 0x00 50AF 0x00 50BO Hay RST CR
31. E3 2 5 600 E 0 2205 e 0 800 S 0 0315 E 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 S 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc s 0 100 5 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits 124 142 DoclD15962 Rev 14 er STM8L151x4 6 STM8L152x4 6 Package information 2 Figure 50 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint l T 000000003 A Us w 050 LI ok C E C CJ 7 30 610 LL n LI 7 30 qmm C C y C l mE WUUUUUULs a 6 10 ba SC di 5V FP V2 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 51 LQFP32 marking example package top view Product identification Standard ST logo Revision code Pin 1 identifier MS37785V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity DoclD15962 Rev 14 125 142 Package information STM8L15
32. Els BJ A0B8 FP V2 1 Dimensions are expressed in millimeters DoclD15962 Rev 14 127 142 Package information STM8L151x4 6 STM8L152x4 6 Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 54 UFQFPN32 marking example package top view Product a identification L l 5 l K 4 Date code x w Standard ST logo Revision code Dot pin 1 MS37786V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity d 128 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information 10 6 2 UFQFPN28 package information Figure 55 UFQFPN28 28 lead 4 x 4 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline PIN 1 IDENTIFIER LASER MARKING AREA 4X c 0 150 gt C0 130X45 PIN 1 CORNER Detail Y 0 1000 0 0500 Detail Z RO 125 T
33. TIM2 active TA 85 C 4 8 5 4 Ta 105 C 7 83 Ta 125 C 11 3 14 5 TA 40 C to 25 CT 235 27 S Ta 55 C 2 42 2 82 all peripherals OFF T4 85 C 3 10 3 71 Ta 105 C 4 36 5 7 LSE g Ta 125 C 720 11 82 768 kHz Ta 40 Cto 25 C 2 46 2 75 Ta 55 C 2 50 2 81 with TIM2 active 2 TA 85 C 3 16 3 82 Ta 105 C 4 51 5 9 TA 125 C 7 28 11 1 No floating I Os 2 Timer 2 clock enabled and counter is running 3 Oscillator bypassed LSEBYP 1 in CLK_ECKCR When configured for external crystal the LSE consumption IDD Lsg must be added Refer to Table 32 76 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Electrical parameters d Figure 16 Typ Ipp LPW vs Vpp LSI clock source IDD LPWL si HA 16 00 14 00 12 00 10 00 8 00 6 00 4 00 2 00 0 00 40 C E 25 C 85 C ee rr 1 8 2 1 2 6 Von V 3 1 3 6 ai18217b DoclD15962 Rev 14 77 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 In the following table data is based on characterization results unless otherwise specified Table 24 Total current consumption and timing in Active halt mode at Vpp 1 65 V to 3 6 V Symbol Parameter Conditions Typ Max Unit Ta 40 Cto25T 09 21 Ta 55 C 1291 3 LCD OFF
34. Table 69 Document revision history continued Date 10 Feb 2012 Revision Changes Features replaced Dynamic consumption with Consumption Table Medium density STM8L 15x pin description updated OD column of NRST PA1 pin Table Interrupt mapping removed tamper 1 tamper 2 and tamper 3 Figure UFQFPN48 package outline replaced Table UFQFPN48 package mechanical data updated title Figure UFQFPN32 32 lead ultra thin fine pitch quad flat no lead package outline 5 x 5 removed the line over A1 Figure UFQFPN28 package outline replaced to improve readability of UFQFPN28 package dimensions A L and L1 Figure Recommended UFQFPN28 footprint dimensions in mm updated title Figure WLCSP28 package outline updated title Table WLCSP28 package mechanical data updated title 02 Mar 2012 Updated Table UFQFPN48 package mechanical data Updated Figure UFQFPN28 package outline Figure Recommended UFQFPN28 footprint dimensions in mm and Table UFQFPN28 package mechanical data Table WLCSP28 package mechanical data Min and Max values removed for e1 e2 e3 e4 F and G dimensions 30 Mar 2012 26 Apr 2012 10 11 Figure SPI1 timing diagram master mode 1 changed SCK signals to output instead of input Figure Medium density STM8L 15x ordering information scheme added Tape amp reel to package section Updated Table WLCSP28 package mechanical data
35. Wait mode in both cases No I O pins toggling Not tested in production Peripherals listed above the Ipp 4 parameter ON TIM1 TIM2 TIM3 TIM4 USART1 SPI1 I2C1 DMA1 WWDG Data based on a differential Ibp measurement between ADC in reset configuration and continuous ADC conversion Data based on a differential Ip measurement between DAC in reset configuration and continuous DAC conversion of Vpp 2 Floating DAC output Data based on a differential Ipp measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2 enabled with static inputs Supply current of internal reference voltage excluded Including supply current of internal reference voltage DoclD15962 Rev 14 81 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 Table 28 Current consumption under external reset Symbol Parameter Conditions Unit IDD RST Supply current under external reset 1 tied to Vop All pins are externally Typ Vop 1 8 V 48 Von 3 V 76 Vop 3 6 V 91 HA 1 All pins except PAO PBO and PB4 are floating under reset PAO PBO and PB4 are configured with pull up under reset 9 3 4 Clock and timing characteristics HSE external clock HSEBYP 1 in CLK ECKCR Subject to general operating conditions for Vpp and Ta Table 29 HSE external clock characteristics Symbol Parameter Conditions Min Typ Max Un
36. in Wait mode by setting the EPM or WAITM bit in the Flash CR1 register 6 Oscillator bypassed HSEBYP 1 in CLK_ECKCR When configured for external crystal the HSE consumption Ibp Hse must be added Refer to Table 31 m Tested in production 8 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for external crystal the LSE consumption Ipp Kse must be added Refer to Table 32 72 142 DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Electrical parameters Figure 14 Typ Ipp wait vs Von fepu 16 MHz 1 IDD WAIT HSI UA 1 8 2 1 2 6 3 1 3 6 Voo V l ai18214b 1 Typical current consumption measured with code executed from Flash memory Ky DoclD15962 Rev 14 73h42 Electrical parameters STM8L151x4 6 STM8L152x4 6 In the following table data is based on characterization results unless otherwise specified Table 22 Total current consumption and timing in Low power run mode at Vpp 1 65 V to 3 6 V Symbol Parameter Conditions Typ Max Nye s Le 5 4 Ta 55 C 57 6 all peripherals OFF Ta 85 68 75 Ta 105 C 92 104 LSI RC osc Ta 125 C 13 4 16 6 at 38 kHz ns Ee gt TA 55 C 6 0 6 3 with TIM2 active Ta 850 72 78 Ta 105C 94 10 7 pana Supply current in Low Ta 125 C 13 8 M power run mode TA 40 C 5 25 56 to 25 C TA255 C
37. modes e Flexible system clock e Ultra safe reset same reset strategy for both STM8L15x and STM32L15xxx including power on reset power down reset brownout reset and programmable voltage detector Features ST ultra low power continuum also lies in feature compatibility e More than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm e Memory density ranging from 4 to 128 Kbyte DoclD15962 Rev 14 13 142 Functional overview STM8L151x4 6 STM8L152x4 6 3 Functional overview Figure 1 Medium density STM8L151x4 6 and STM8L152x4 6 device block diagram BAG 1 16 MH illat s z oscillator _ OSC_OUT Clock VDD18 Power Vop1 1 65V 16 MHz internal RC Hs controller VOLT REG to 3 6V OSC32 IN and E Vss1 08c32 OUTED 32 kHz oscillator gt padapa 38 kHz internal RC peripherals 2 gt RESET NRST Interrupt controller lt gt STM8 Core A POR PDR AR Debug module BOR SWIM SWIM lt gt PVD PVD IN 2channels lt I gt 16 bit Timer 2 lt gt 2 channels 16 bit Timer 3 lt gt 32 Kbyte 3 chan
38. o o a a E O c 3 pun D o function rur own z a 2 lt x Q a zz 21215 0 S IS E OL sS el A I 2 o g gt E us Lu uio OO I a sl Timer 3 break input PA5 T Em Timer 3 external TIM3 ETR 9 TT trigger LCD COM 1 5 15 P4 ep com anci in 9 X X X HS X X Port AS 1 503 input 17 COMP1 INP Comparator 1 positive input ADC1 trigger PA6 ADC1_TRIG TIT LCD COM2 7 6 LCD COM2 ADC1 INO I O s X X X HS X X Port A6 ADC1 input 0 COMP1 INP Comparator 1 positive input 8 PA7 LCD_SEGO S VO FT X X X HS X X Port A7 LCD segment 0 Timer 2 channel 1 PBO TIM2_CH1 TT LCD segment 10 24 13 12 E3 LCD Soo VO 3 X x X HS X X Port BO ADC1 IN18 ADC1_IN18 COMP1_INP Comparator 1 positive input Timer 3 channel 1 PB1 TIM3_CH1 LCD segment 11 25 14 13 G1 LCD SEG112 1 0 IA X X X HS X X Port B1 ADC1 IN17 ADC1 IN17 COMP1 INP Comparator 1 positive input Timer 2 channel 2 PB2 TIM2 CH2 IT LCD segment 12 26 15 14 F2 LCD SEG120 VOlg X X X HS X X Port B2 ADC1 IN16 ADC1 IN16 COMP1 INP Comparator 1 positive input Timer 2 external trigger PB3 TIM2_ETR LCD segment 13 27 LCD SEG182 volh x x X HS x X Port B3 ADC1_IN15 ADC1_IN15 COMP1_INP Comparator 1 positive input d 30 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Pinout and pin description
39. of the devices have an error less than or equal to the value indicated mean 2 gt Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10 Figure 10 Pin loading conditions STM8AL PIN 50 pF MSv37774V1 DoclD15962 Rev 14 63 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 1 5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 17 Figure 11 Pin input voltage STM8S PIN MSv37775V1 9 2 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 15 Voltage characteristics Symbol Ratings Min Max Unit External supply voltage including Vppa Vpp Vss and Vpp3 0 3 4 0 V Input voltage on true open drain pins i PCO and PC1 Meda Von 40 Input voltage on five volt tolerant FT Vin pins PA7 and PEO Vss 0 3 Voo 4 0 V Input voltage on 3 6 V tolerant TT pins Vss 0 3 4 0 Input voltage on any other pin Vss 0 3 4 0 see Absolute maximum VEsD Electrostatic discharge
40. products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 142 142 DoclD15962 Rev 14 d
41. synchronous transfers on 2 lines with a possible bidirectional data line e Master or slave operation selectable by hardware or software e Hardware CRC calculation e Slave master selection input pin SPI1 can be served by the DMA1 Controller PC The 12C bus interface 12C1 provides multi master capability and controls all 12C bus specific sequencing protocol arbitration and timing e Master slave and multi master capability e Standard mode up to 100 kHz and fast speed modes up to 400 kHz e T bit and 10 bit addressing modes e SMBus 2 0 and PMBus support e Hardware CRC calculation C1 can be served by the DMA1 Controller USART The USART interface USART1 allows full duplex asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format It offers a very wide range of baud rates e 1 Mbit s full duplex SCI e SPI1 emulation e High precision baud rate generator e SmartCard emulation e IrDA SIR encoder decoder e Single wire half duplex mode USART1 can be served by the DMA1 Controller Infrared IR interface The medium density STM8L151x4 6 and STM8L152x4 6 devices contain an infrared interface which can be used with an IR LED for remote control functions Two timer output compare channels are used to generate the infrared remote control signals 2 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Functional overview 3 19 d Development suppo
42. to 2 MHz d STM8L151x4 6 STM8L152x4 6 Pinout and pin description 4 1 System configuration options As shown in Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description some alternate functions can be remapped on different I O ports by programming one of the two remapping registers described in the Routing interface RI and system configuration controller section in the STM8L15xxx and STM8L16xxx reference manual RM0031 DoclD15962 Rev 14 37 142 d Memory and register map STM8L151x4 6 STM8L152x4 6 5 Memory and register map 5 1 Memory mapping The memory map is shown in Figure 9 Figure 9 Memory map 0x00 0000 RAM 2 Kbytes 1 including 0x00 07FF Stack 513 bytes 1 0x00 0800 Reserved 0x00 OFFF 0x00 1000 Data EEPROM 0x00 13FF 1 Kbyte 0x00 1400 x00 5000 E Reserved 0x00 5050 ET 0x00 47FF 0x00 5070 Du 0x00 4800 0x00 509E i SYSCFG 0x00 48FF eba byles QOO DAD ITC EXTI 0x00 4900 0x00 50A6 WEE Reserved 0x00 50B0 0x00 4909 ga 5682 0x00 4910 VREFINT Factory CONV RAMS PWR 0x00 4911 TS Factory CONV V90 i CLK 0x00 4912 y 0x00 50D3 SOEN 0x00 4925 Reserved 0x00 50E0 Woe dens E Unique ID Ox00 50F3 BEEP 0x00 4932 0x00 5140 RTG 0x00 4FFF Reserved 0x00 5200 mem 0x00 5000 Dee GPIO and peripheral registers ees 0x00 57FF H USART1 0x00 5800 0x0
43. to achieve the best compromise between low power consumption short startup time and available wakeup sources 2 Wait mode The CPU clock is stopped but selected peripherals keep running An internal or external interrupt event or a Reset can be used to exit the microcontroller from Wait mode WFE or WFI mode Wait consumption refer to Table 21 Low power run mode The CPU and the selected peripherals are running Execution is done from RAM with a low speed oscillator LSI or LSE Flash and data EEPROM are stopped and the voltage regulator is configured in ultra low power mode The microcontroller enters Low power run mode by software and can exit from this mode by software or by a reset All interrupts must be masked They cannot be used to exit the microcontroller from this mode Low power run mode consumption refer to Table 22 Low power wait mode This mode is entered when executing a Wait for event in Low power run mode It is similar to Low power run mode except that the CPU clock is stopped The wakeup from this mode is triggered by a Reset or by an internal or external event peripheral event generated by the timers serial interfaces DMA controller DMA1 comparators and I O ports When the wakeup is triggered by an event the system goes back to Low power run mode All interrupts must be masked They cannot be used to exit the microcontroller from this mode Low power wait mode consumption refer to Table 23 Active halt mo
44. voltage ratings electrical sensitivity on page 115 1 All power Vpp1 Vppo VppA and ground Vss1 Vss2 Vssa pins must always be connected to the external power supply 2 Vum maximum must always be respected Refer to Table 16 for maximum allowed injected current values 64 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Electrical parameters 2 Table 16 Current characteristics Symbol Ratings Max Unit Jupp Total current into Vpp power line source 80 lyss Total current out of Vss ground line sink 80 Output current sunk by IR_TIM pin with high sink LED driver pt 80 mA capability lio Output current sunk by any other I O and control pin 25 Output current sourced by any I Os and control pin 25 Injected current on true open drain pins PCO and PC 5 0 Injected current on five volt tolerant FT pins PA7 and PEO 5 0 IINJ PIN mA Injected current on 3 6 V tolerant TT pins 1 5 0 Injected current on any other pin 2 5 45 Ele Total injected current sum of all UO and control pins 25 Positive injection is not possible on these I Os A negative injection is induced by Viy Vss liny piny must never be exceeded Refer to Table 15 for maximum allowed input voltage values A positive injection is induced by Viy Vpp while a negative injection is induced by Viy Vss ling pin must never be exceeded Refer to Table 15 for maximu
45. 0 45 kQ Cio I O pin capacitance pF op ON gt 90 142 Not tested in production Vpp 3 0 V Ta 40 to 125 C unless otherwise specified Data based on characterization results not tested in production DoclD15962 Rev 14 The max value may be exceeded if negative current is injected on adjacent pins Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested d STM8L151x4 6 STM8L152x4 6 Electrical parameters 6 Rpy pull up equivalent resistor based on a resistive transistor corresponding Ipy current characteristics described in Figure 24 2 Figure 21 Typical Vj and Vj vs Vpp high sink I Os I gt o c c gt 18 2 1 2 6 3 1 3 6 Von V ai18220c Figure 22 Typical Vu and Vj vs Vpp true open drain I Os gt o c o gt 1 8 2 1 2 6 3 1 3 6 Von V ai18221b DoclD15962 Rev 14 91 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 92 142 Figure 23 Typical pull up resistance Rpy vs Vpp With Viy Vss Pull up current uA S o o c 8 2 o L a 5 a 18 2 22 24 26 28 3 32 34 36 Von V ai18222b Figure 24 Typical pull up current ly VS Vpp With Vin Vss 120 100 80 60 40 20 0 18 1 95 21 225 24 255 2 7 285
46. 0 0x00 5410 LCD_RAM4 LCD display memory 4 0x00 0x00 5411 LCD_RAM5 LCD display memory 5 0x00 0x00 5412 aR LCD_RAM6 LCD display memory 6 0x00 0x00 5413 LCD_RAM7 LCD display memory 7 0x00 0x00 5414 LCD_RAM8 LCD display memory 8 0x00 0x00 5415 LCD_RAM9 LCD display memory 9 0x00 0x00 5416 LCD_RAM10 LCD display memory 10 0x00 0x00 5417 LCD_RAM11 LCD display memory 11 0x00 0x00 5418 LCD_RAM12 LCD display memory 12 0x00 0x00 5419 LCD_RAM13 LCD display memory 13 0x00 pers piang Reserved area 22 bytes er DoclD15962 Rev 14 53 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Address Block Register label Register name eae 0x00 5430 Reserved area 1 byte 0x00 0x00 5431 RI ICR1 Timer input capture routing register 1 0x00 0x00 5432 RI ICR2 Timer input capture routing register 2 0x00 0x00 5433 RI IOIR1 I O input register 1 undefined 0x00 5434 RI IOIR2 I O input register 2 undefined 0x00 5435 RI_IOIR3 I O input register 3 undefined 0x00 5436 RI_IOCMR1 UO control mode register 1 0x00 0x00 5437 RI IOCMR2 I O control mode register 2 0x00 0x00 5438 da RI_IOCMR3 I O control mode register 3 0x00 0x00 5439 RI_IOSR1 I O switch register 1 0x00 0x00 543A RI_IOSR2 I O switch register 2 0x00 0x00 543B RI IOSR3 I O switch register 3 0x00 0x00 543C RI IOGCR I O group control register Ox3F 0
47. 0 5250 D Reserved 0x00 5280 sis Coa pada 0x00 52B0 aW A Boot ROM 0x00 52E0 TIM4 0x00 67FF 2 Kbytes Ox00 52FF IRTIM 0x00 6800 0x00 5340 pom 0x00 5380 Bem Reserved 0x00 5400 0x00 7EFF LCD 0x00 7F00 0x00 5430 Ri CPU SWIM Debug ITC 0x00 5440 GONE Registers X00 8000 X 0x00 807F een SE 0x00 8080 Medium density Flash program memory 0x00 FFFF up to 32 Kbytes MS32632V1 1 Table 6 lists the boundary addresses for each memory size The top of the stack is at the RAM end address 2 The VREFINT_Factory_CONV byte represents the LSB of the VrerinT 12 bit ADC conversion result The MSB have a fixed value 0x6 3 The TS_Factory_CONV_V90 byte represents the LSB of the Vg9 12 bit ADC conversion result The MSB 38 142 DocID15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Memory and register map have a fixed value 0x3 4 Refer to Table 9 for an overview of hardware register mapping to Table 8 for details on I O port hardware registers and to Table 10 for information on CPU SWIM debug module controller registers Table 6 Flash and RAM boundary addresses Memory area Size Start address End address RAM 2 Kbyte 0x00 0000 0x00 07FF 16 Kbyte 0x00 8000 0x00 BFFF Flash program memory 32 Kbyte 0x00 8000 0x00 FFFF 5 2 Register map Table 7 Factory conversion registers Address Block Register label Register name neser status 0x00 4910 VREFINT Parton Internal reference voltage fa
48. 0 ITC SPR1 Interrupt Software priority register 1 OxFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 OxFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 OxFF 0x00 7F74 QUSS ITC SPR5 Interrupt Software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt Software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt Software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt Software priority register 8 OxFF 0x00 7F78 to Reserved area 2 byte 0x00 7F79 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 0x00 7F81 to Reserved area 15 byte 0x00 7F8F er DoclD15962 Rev 14 55 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 10 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name oe oxoo7F90 DMBKIRE DMbreakpoint1registerextendedbyte OxFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM Debug module control register 1 0x00 0x00 7F97 DM CR2 DM Debug module control register 2 0x00 0x00 7F98 DM CSR1 DM Debug module control sta
49. 0 pA 10 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for external crystal the LSE consumption Ipp Lse must be added Refer to Table 32 Figure 13 Typ Ipp RUN vs Vpp fcpu 16 MHz 3 00 2 75 T 250 o zm 2 225 2 a a 200 1 75 1 50 1 8 24 2 6 3 1 3 6 Vpp V ai18213b 1 Typical current consumption measured with code executed from RAM d 70 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters In the following table data is based on characterization results unless otherwise specified Table 21 Total current consumption in Wait mode Max T 1 D Symbol Parameter Conditions Typ m 85 105 C 125 C Unit c2 3 4 fopy 125 kHz 0 33 0 39 0 41 0 43 0 45 fopy 1MHz 0 35 0 41 0 44 0 45 0 48 isay fopy 4MHz 0 42 0 51 0 52 0 54 0 58 fopy 8 MHz 0 52 0 57 0 58 0 59 0 62 CPU not fopu 16 MHz 0 68 0 76 0 79 082 983 clocked all peripherals fcru 125 kHz 0 032 0 056 0 068 0 072 0 093 OFF Supply code executed HSE external CPU 1 MHz 0 078 0 121 0 144 0 163 0 197 Gemeng current in from RAM clock foru 4 MHz 0 218 0 26 0 30 0 36 0 40 TA Wait mode with Flash in fepu fuse IDDa mode 6 fepu 8 MHz 0 40 0 52 0 57 0 62 0 66 Vpp from 1 09 1 16 1 65 Vto 3 6 V ou 16 MH
50. 0x00 5208 to Reserved area 8 bytes 0x00 520F 0x00 5210 I2C1 CR1 12C1 control register 1 0x00 0x00 5211 l2C1 CR2 12C1 control register 2 0x00 0x00 5212 l2C1 FREQR I2C1 frequency register 0x00 0x00 5213 l2C1 OARL 12C1 own address register low 0x00 0x00 5214 I2C1 OARH 12C1 own address register high 0x00 0x00 5215 Reserved 1 byte 0x00 5216 I2C1 DR I2C1 data register 0x00 0x00 5217 I2C1 l2C1 SR1 12C1 status register 1 0x00 0x00 5218 l2C1 SR2 I2C1 status register 2 0x00 0x00 5219 l2C1 SR3 12C1 status register 3 0x0x 0x00 521A I2C1 ITR 12C1 interrupt control register 0x00 0x00 521B I2C1 CCRL I2C1 clock control register low 0x00 0x00 521C I2C1 CCRH 12C1 clock control register high 0x00 0x00 521D I2C1 TRISER 12C1 TRISE register 0x02 0x00 521E l2C1 PECH 12C1 packet error checking register 0x00 0x00 521F to Reserved area 17 bytes 0x00 522F 46 142 DoclD15962 Rev 14 er STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name o 0x00 5230 USART1_SR USART1 status register OxCO 0x00 5231 USART1 DR USART1 data register undefined 0x00 5232 USART1 BRR1 USART1 baud rate register 1 0x00 0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00 0x00 5234 USART1 CR1 USART1 control register 1 0x00 0x00 5235 USART1 USART1_CR2 USART1 control register 2 0x00 0x00 5236 USART1
51. 0x4927 the wafer U ID 15 8 0x4928 Y co ordinate on U_ID 23 16 0x4929 the wafer U_ID 31 24 0x492A Wafer number U_ID 39 32 0x492B U_ID 47 40 0x492C U_ID 55 48 0x492D U_ID 63 56 0x492E Lot number U_ID 71 64 0x492F U_ID 79 72 0x4930 U_ID 87 80 0x4931 U_ID 95 88 62 142 DoclD15962 Rev 14 ky STM8L151x4 6 STM8L152x4 6 Electrical parameters 9 9 1 2 Electrical parameters Parameter conditions Unless otherwise specified all voltages are referred to Ves Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and T4 Ta max given by the selected temperature range Data based on characterization results design simulation and or technology characteristics is indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 32 Typical values Unless otherwise specified typical data is based on Ta 25 C Vpp 3 V It is given only as design guidelines and is not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95
52. 151x4 6 STM8L152x4 6 Functional overview Figure 2 Medium density STM8L151x4 6 and STM8L152x4 6 clock tree diagram OSC_IN HSE OSC col HSE OSC OUT 1 16 MHz HSI RC 16 MHz SYSCLK to core and memory gt O to peripherals SYSCLK prescaler 11 2 4 8 16 32 64 128 Peripheral clock enable 15 bit 2 LSE Ps BEEPCLK Lo gt to BEEP LSI RC LSI CLKBEEPSEL 1 0 IWDGCLK 38 kHz gt to IWDG RTCCLK to RTC RTCSEL 3 0 LCD peripheral clock enable 1 bit RTC RTCCLK GE prescaler Fer 2 PU e E to LCD OSC32 IN L TSE osc 1 11 2 4 8 16 32 64 OSC32_OUT 32 768 kHz D LEDCLK en configurable Eco HSI SYSCLK oS peres ESE 1 ES bit 1 2 4 8 16 32 64 12 458 16 32 LSE 1 The HSE clock source can be either an external crystal ceramic resonator or an external source HSE bypass Refer to Section HSE clock in the STM8L15x and STM8L16x reference manual RM0031 2 The LSE clock source can be either an external crystal ceramic resonator or a external source LSE bypass Refer to Section LSE clock in the STM8L15x and STM8L16x reference manual RM0031 Halt ai15366g 3 5 Low power real time clock The real time clock RTC is an independent binary coded decimal BCD timer counter Six byte locations contain the second minute hour 12
53. 15962 Rev 14 1 142 This is information on a product in full production www st com Contents STM8L151x4 6 STM8L152x4 6 Contents 1 Introduction cna aaa dr EEN Ee a 9 2 Description 3c ici x occa cue aie de Rica Eh DNA aie QR Ga e 11 2 1 Device overview 0 lr 12 2 2 Ultra low power continuum sss ee 13 3 Functional overview a d sg ig NIE NIE KEREN RR RAT KANAL ee non 14 3 1 Low power modeS a de ehe Foe poi Repo do ars esas ee 15 3 2 Central processing unit GTM 16 3 2 1 Advanced STM8 Core 2 2 2 16 3 2 2 Interrupt controller 0 BI 16 3 3 Reset and supply management cece eee eens 17 3 3 1 Power supply scheme 17 3 3 2 Power supply supervisor 17 3 3 3 Voltage regulator 17 3 4 Clock management serias er KAAGAD ANG EA 18 3 5 Low power real time clock 19 3 6 LCD Liquid crystal display 20 3 7 MeMONeS 211 Xe ecce ee A ENA ee ha 20 3 8 DMA ia ara bende bees eee eee eee AY 20 3 3 Analog to digital converter 20 3 10 Digital to analog converter DAC 21 3 11 Ultra low power comparators llle 21 3 12 System configuration controller and routing interface 21 do Ne cn E e REESEN 21 3 14 TIMES 0 eet eee 22 3 44 1 TIM1 16 bit advanced control mer 22 3 14 2 16 bit general purpose timers llle 23 3 14 3 8 bitbasictimer llli 23 3 15 Watchdog timers aa nae HAWAKAN Hee a RICE Ee Roa dU SUR e wean 23 3 15 1 Wind
54. 1x4 6 STM8L152x4 6 10 5 UFQFPN32 package information Figure 52 UFQFPN32 32 pin 5 x 5 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline k4 Y A add Je C SEATING PLANE PIN 1 Identifier AOB8_ME_V2 1 Drawing is not to scale d 126 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information 2 Table 65 UFQFPN32 32 pin 5 x 5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 Al 0 000 0 020 0 050 0 0000 0 0008 0 0020 A3 0 152 0 0060 0 180 0 230 0 280 0 0071 0 0091 0 0110 D 4 900 5 000 5 100 0 1929 0 1969 0 2008 D1 3 400 3 500 3 600 0 1339 0 1378 0 1417 D2 3 400 3 500 3 600 0 1339 0 1378 0 1417 E 4 900 5 000 5 100 0 1929 0 1969 0 2008 E1 3 400 3 500 3 600 0 1339 0 1378 0 1417 E2 3 400 3 500 3 600 0 1339 0 1378 0 1417 e 0 500 0 0197 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 ddd 0 080 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 53 UFQFPN32 32 pin 5 x 5 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint a 5 30 gt HOOL LJ 3 80 UOUOUOI E CJ CJ CJ 3 80 UUU
55. 1x4 6 and STM8L152x4 6 devices STM8L151Cx Kx Gx STM8L152Cx Kx microcontrollers with a 16 Kbyte or 32 Kbyte Flash memory density These devices are referred to as medium density devices in the STM8L15x and STM8L16x reference manual RM0031 and in the STM8L Flash programming manual PM0054 For more details on the whole STMicroelectronics ultra low power family please refer to Section 2 2 Ultra low power continuum on page 13 For information on the debug module and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 For information on the STM8 core please refer to the STM8 CPU programming manual PM0044 The medium density devices provide the following benefits e Integrated system Upto 32 Kbyte of medium density embedded Flash program memory 4 Kbyte of data EEPROM Internal high speed and low power low speed RC Embedded reset e Ultra low power consumption 195 uA MHZ 440 uA consumption 0 9 pA with LSI in Active halt mode Clock gated system and optimized power management Capability to execute from RAM for Low power wait mode and Low power run mode e Advanced features Upto 16 MIPS at 16 MHz CPU clock frequency Direct memory access DMA for memory to memory or peripheral to memory access e Short development cycles Application scalability across a common family product architecture with compatible pinout memory map and modula
56. 2 3 2 35 V BOR BOR TH 2 0 010 Rising edge 2 31 2 41 2 44 V Brown out reset threshold 3 Falling edge 245 2 55 2 60 BOR3 BOR TH 2 0 011 Rising edge 2 54 2 66 2 7 V Brown out reset threshold 4 Falling edge 2 68 2 80 2 85 BOR4 Jl BOR TH 2 0 100 Rising edge 2 78 2 90 2 95 Falling edge 1 80 1 84 1 88 Vpvpo PVD threshold 0 Rising edge 1 88 1 94 1 99 Falling edge 1 98 2 04 2 09 Vepvp1 PVD threshold 1 Rising edge 2 08 2 14 2 18 Falling edge 2 2 2 24 2 28 Vpvp2 PVD threshold 2 Rising edge 2 28 2 34 2 38 Falling edge 2 39 2 44 2 48 Vpyp3 PVD threshold 3 V Rising edge 2 47 2 54 2 58 Falling edge 2 57 2 64 2 69 Vpyp4 PVD threshold 4 Rising edge 2 68 2 74 2 79 Falling edge 2 77 2 83 2 88 Vpyps PVD threshold 5 Rising edge 2 87 2 94 2 99 Falling edge 2 97 3 05 3 09 Vpvpe PVD threshold 6 Rising edge 3 08 3 15 3 20 ky DocID15962 Rev 14 67 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 1 Data guaranteed by design not tested in production 2 Data based on characterization results not tested in production 9 3 3 68 142 Figure 12 POR BOR thresholds VDD VDD 3 6 V Operating power supply BOR threshold_0 18V BOR threshold VBORO VPDR O o oO 8 ko E 8 DE o re E i Sg 1 D 1a Internal NRST with without BOR BOR d Time BOR always active BOR activated by user at power up for power down detection ai17033b Supply current characteristics To
57. 2 Initialization and Status register 2 0x00 Du PE RTC Reserved area 2 bytes 0x00 5150 RTC SPRERH Synchronous prescaler register high de 0x00 5151 HTC SPRERL Synchronous prescaler register low Vidal 0x00 5152 RTC_APRER Asynchronous prescaler register ra 0x00 5153 Reserved area 1 byte 0x00 5154 RTC_WUTRH Wakeup timer register high oxFF 0x00 5155 RTC_WUTRL Wakeup timer register low oxFF ose Reserved area 3 bytes 0x00 5159 RTC_WPR Write protection register 0x00 GER E Reserved area 2 bytes 0x00 515C RTC ALRMAR1 Alarm A register 1 0x00 0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00 0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00 0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00 aan Reserved area 160 bytes er DoclD15962 Rev 14 45 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Address Block Register label Register name ean 0x00 5200 SPH CR1 SPI1 control register 1 0x00 0x00 5201 SPI1_CR2 SPI1 control register 2 0x00 0x00 5202 SPI1 ICR SPI1 interrupt control register 0x00 0x00 5203 SPI1 SR SPI status register 0x02 0x00 5204 SR SPI DR SPI1 data register 0x00 0x00 5205 SPI1 CRCPR SPI1 CRC polynomial register 0x07 0x00 5206 SPIt RXCRCR SPI1 Rx CRC register 0x00 0x00 5207 SPI1 TXCRCR SPI1 Tx CRC register 0x00
58. 2 pin 7 x 7 mm low profile quad flat package mechanical data esee ee cae Ree eee ee ne ad ea A ee eed 124 UFQFPN32 32 pin 5 x 5 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 127 UFQFPNZ8 28 lead 4 x 4 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data 129 WLCSP28 28 pin 1 703 x 2 841 mm 0 4 mm pitch wafer level chip scale package mechanical data 133 Thermal characteristics illie 135 Document revision history ee eae 137 2 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Ly Medium density STM8L151x4 6 and STM8L152x4 6 device block diagram 14 Medium density STM8L151x4 6 and STM8L152x4 6 clock tree diagram 19 STM8L151C4 STM8L151C6 48 pin pinout without LCD 26 STM8L151K4 STM8L151K6 32 pin package pinout without LCD 26 STM8L151Gx
59. 28 None Any power of 2 TMe Bol up from 1 to 32768 9 3 14 1 TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e 3 independent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e 1 additional capture compare channel which is not connected to an external I O e Synchronization module to control the timer with external signals e Break input to force timer outputs into a defined state e 3complementary outputs with adjustable dead time e Encoder mode e interrupt capability on various events capture compare overflow break trigger 22 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Functional overview 3 14 2 3 14 3 3 15 3 15 1 3 15 2 3 16 2 16 bit general purpose timers e 16 bit autoreload AR up down counter e 7 bitprescaler adjustable to fixed power of 2 ratios 1 128 e 2 individually configurable capture compare channels e PWM mode e Interrupt capability on various events capture compare overflow break trigger e Synchronization with other timers or external signals external clock res
60. 528C TIM3_CNTRH TIM3 counter high Ox00 0x00 528D TIM3 CNTRL TIM3 counter low 0x00 0x00 528E TIM3_PSCR TIM3 prescaler register 0x00 0x00 528F TIM3 ARRH TIM3 Auto reload register high OxFF 0x00 5290 TIM3_ARRL TIM3 Auto reload register low OxFF 0x00 5291 TIM3_CCR1H TIM3 Capture Compare register 1 high 0x00 0x00 5292 TIM3 CCR1L TIM3 Capture Compare register 1 low 0x00 0x00 5293 TIM3_CCR2H TIM3 Capture Compare register 2 high 0x00 0x00 5294 TIM3 CCR2L TIM3 Capture Compare register 2 low 0x00 0x00 5295 TIM3_BKR TIM3 break register 0x00 0x00 5296 TIM3_OISR TIM3 output idle state register 0x00 oe Reserved area 25 bytes Ky DoclD15962 Rev 14 49 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Address Block Register label Register name Saree 0x00 52B0 TIM1_CR1 TIM1 control register 1 0x00 0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00 0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00 0x00 52B3 TIM1 ETR TIM1 external trigger register 0x00 0x00 52B4 TIM1 DER TIM1 DMA1 request enable register 0x00 0x00 52B5 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 52B6 TIM1 SR1 TIM1 status register 1 0x00 0x00 52B7 TIM1 SR2 TIM1 status register 2 0x00 0x00 52B8 TIM1 EGR TIM1 event generation r
61. 55 C 3 7 83 1 4 duty A internal Ta 85 C 3 9 9 2 Vico 9 Ta 105 C 5 0 14 5 Ta 125 C 6 3 15 2 Supply current during wakeup time from IDD WUFAH Active halt mode 24 mA using HSI Wakeup time from twu usan Active halt mode to 4 7 7 us Run mode using HSI t g Wakeup time from WU LSI AH Active halt mode to S 150 us 9 Run mode using LSI connected No floating I O unless otherwise specified RTC enabled Clock source LSI RTC enabled LCD enabled with external Vi cp 3 V static duty division ratio 256 all pixels active no LCD connected RTC enabled LCD enabled with external Vi cp 1 4 duty 1 3 bias division ratio 64 all pixels active no LCD connected LCD enabled with internal LCD booster V cp 3 V 1 4 duty 1 3 bias division ratio 64 all pixels active no LCD The first word of interrupt routine is fetched 4 CPU cycles after ty Ly ULP 0 or ULP 1 and FWU 1 in the PWR_CSR2 register DoclD15962 Rev 14 Oscillator bypassed LSEBYP 1 in CLK ECKCR When configured for external crystal the LSE consumption Ipp Lsg must be added Refer to Table 32 RTC enabled Clock source LSE Wakeup time until start of interrupt vector fetch 79 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 Table 25 Typical current consumption in Active halt mode RTC clocked by LSE external crystal Symbol Ibon P Parameter Sup
62. 87V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 2 DoclD15962 Rev 14 131 142 Package information STM8L151x4 6 STM8L152x4 6 10 7 WLCSP28 package information Figure 58 WLCSP28 28 pin 1 703 x 2 841 mm 0 4 mm pitch wafer level chip scale package outline bbb Z A1 ball D HR location X Y 7 N 1 o N 7 x Detail A E Notch PEG A aaa T A2 A 4x Wafer back side Bump side Side view gt gt N Been Wee Ge Egi BT Front view Oleee a A N i x 7 Seating plane PCCCWIZXIY 4b 28 igado PCS Detail A rotated by 90 A0AM_ME_V3 1 Drawing is not to scale 132 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Package information 2 Table 67 WLCSP28 28 pin 1 703 x 2 841 mm 0 4 mm pitch wafer level chip scale package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max
63. ART1 transmit data 27 usarTt register empty Yes Yes 0x00 8074 transmission complete interrupt USART1 received data 28 Usagi e29y overrun error Yes Yes 0x00 8078 idle line detected parity error global error interrupt 29 Se 12C1 interrupt Yes Yes Yes Yes 0x00 807C 1 The Low power wait mode is entered when executing a WFE instruction in Low power run mode In WFE mode the interrupt is served if it has been previously enabled After processing the interrupt the processor goes back to WFE mode When the interrupt is configured as a wakeup event the CPU wakes up and resumes processing 2 The interrupt from PVD is logically OR ed with Port E and F interrupts Register EXTI CONF allows to select between Port E and Port F interrupt see External interrupt port select register EXTI CONF in the RM0031 3 The device is woken up from Halt or Active halt mode only when the address received matches the interface address 58 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Option bytes 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated memory block All option bytes can be modified in ICP mode with SWIM by accessing the EEPROM address See Table 12 for details on option byte addresses The option bytes can also be modified on the fly by the application in IA
64. C3 and PC4 in Table Medium density STM8L15x pin description Modified IDWDG_KR reset value in Table General hardware register map Replaced VREF_OUT with VREFINT and TIMx_TRIG with TIMx_ETR Added Table Factory conversion registers Modified reset values for TIM1 DCR1 IWDG KR RTC DR1 RTC_DR2 RTC_SPRERH RTC_SPRERL RTC_APRER RTC_WUTRH and RTC_WUTRL in Table General hardware register map Added notes to certain values in Section Embedded reference voltage and Section Temperature sensor DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Revision history Table 69 Document revision history continued Date Revision Changes Modified OPT1 and OPT4 description in Table Option byte description Updated Section Electrical parameters standard l Os replaced with high sink I Os Updated Run ang Run descriptions in Table LCD characteristics Added Tape amp Reel option to Figure Medium density STM8L 15x ordering information scheme 11 Mar 2011 6 cont d Features updated bullet point concerning capacitive sensing channels Section Low power modes updated Wait mode and Halt mode definitions Section Clock management added kHz to 32 768 in the System clock sources bullet point Section System configuration controller and routing interface replaced last sentence concerning management of charge transfer acquisition sequence Added Section Touchsensing Section Development sup
65. D15962 Rev 14 er STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ree 0x00 52D2 TIM1_DCR2 TIM1 DMA1 control register 2 0x00 0x00 52D3 Ma TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00 0x00 52D4 to Reserved area 12 bytes 0x00 52DF 0x00 52E0 TIM4 CR1 TIM4 control register 1 0x00 0x00 52E1 TIM4 CR2 TIM4 control register 2 0x00 0x00 52E2 TIM4 SMCR TIM4 Slave mode control register 0x00 0x00 52E3 TIM4 DER TIM4 DMA1 request enable register 0x00 0x00 52E4 TIM4 IER TIM4 Interrupt enable register 0x00 0x00 52E5 Lu TIM4 SR1 TIM4 status register 1 0x00 0x00 52E6 TIM4 EGR TIM4 Event generation register 0x00 0x00 52E7 TIM4_CNTR TIM4 counter 0x00 0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00 0x00 52E9 TIM4_ARR TIM4 Auto reload register 0x00 0x00 52EA to Reserved area 21 bytes 0x00 52FE 0x00 52FF IRTIM IR_CR Infrared control register 0x00 0x00 5300 to Reserved area 64 bytes 0x00 533F 0x00 5340 ADC1 CR1 ADC1 configuration register 1 0x00 0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00 0x00 5342 ADC1_CR3 ADC1 configuration register 3 Ox1F 0x00 5343 ADC1_SR ADC1 status register 0x00 0x00 5344 ADC1_DRH ADC1 data register high 0x00 0x00 5345 ADC1 DR
66. DAC right aligned data holding register low 0x00 0x00 538A to 0x00 538B Reserved area 2 bytes 0x00 538C DAC_LDHRH DAC left aligned data holding register high 0x00 0x00 538D DAC_LDHRL DAC left aligned data holding register low 0x00 0x00 538E to 0x00 538F Reserved area 2 bytes 0x00 5390 DAC DHR8 DAC 8 bit data holding register 0x00 0x00 5391 to 0x00 53AB Reserved area 27 bytes 0x00 53AC DAC_DORH DAC data output register high 0x00 0x00 53AD DAC_DORL DAC data output register low 0x00 0x00 53AE to 0x00 53FF Reserved area 82 bytes 52 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ara 0x00 5400 LCD CR1 LCD control register 1 0x00 0x00 5401 LCD_CR2 LCD control register 2 0x00 0x00 5402 LCD_CR3 LCD control register 3 0x00 0x00 5403 LCD_FRQ LCD frequency selection register 0x00 0x00 5404 id LCD PMO LCD Port mask register 0 0x00 0x00 5405 LCD PM1 LCD Port mask register 1 0x00 0x00 5406 LCD PM2 LCD Port mask register 2 0x00 0x00 5407 LCD PMS3 LCD Port mask register 3 0x00 EE Reserved area 4 bytes 0x00 540C LCD_RAMO LCD display memory 0 0x00 0x00 540D LCD RAM1 LCD display memory 1 0x00 0x00 540E LCD_RAM2 LCD display memory 2 0x00 0x00 540F LCD RAM3 LCD display memory 3 0x0
67. I L segment 15 LCD_SEG15 2 TT ADC1 IN13 DAC 18 17 D1 ADC1_IN13 DAC_OUT VOlg X X X HS X X Port B5 output COMP1_INP Comparator 1 positive input Ly DoclD15962 Rev 14 31 142 Pinout and pin description STM8L151x4 6 STM8L152x4 6 Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued Pin number Input Output e Ss t o Ou 0 Z Z oO o bo aj E 2 co Pininame 213 a 5 sg Default alternate JAS Flo 2 5 5 38 E function wih oOo N a x Q an Kz sl sl BO 8 E clo na Gc ei eil OI a 9 16 a E 5 sis ind ira s OO I a sl SPI1 master out slave inj PB6 SP 1_MOSI 30 LCD_SEGt6 vola X X X HS x x Port Be kop Segment 18 ADC1_IN12 COMP1_INP ES T Comparator 1 positive input 4 SPI1 master out EE j TT slave in LCD segment 119 18 F1 ADC1 IN12 COMP1 INP VOlg X X X HS X X Port B6 erc us AD DAC OUT output Comparator positive input SPI1 master in slave out PB7 SPI1_MISO 31 20 19 E1 LCD SEG170 volh x xX X Hs x X Port B7 Nose E ADC1 IN11 COMP1 INP E T Comparator 1 positive input 37 25 21 B1 PCO I2C1 SDA VO FT X X TI PortCO I2C1 data 38 26 22 A1 PC1 I9C1 SCL O FT T PortC1 12C1 clock USARTI receive PC2 USART1_RX TT LCD segment 22 41 27 23 B2 LCD_SEG22 ADC1_IN6 O 3 X X X HS X X
68. L ADC1 data register low 0x00 0x00 5346 ADC1_HTRH ADC1 high threshold register high OxOF 0x00 5347 at ADC1_HTRL ADC1 high threshold register low OxFF 0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00 0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00 0x00 534A ADC1 SQR1 ADC1 channel sequence 1 register 0x00 0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00 0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00 0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00 Ky DoclD15962 Rev 14 51 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Address Block Register label Register name nese status 0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00 0x00 534F rear ADC1_TRIGR2 ADC1 trigger disable 2 0x00 0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00 0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00 0x00 5352 to 0x00 537F Reserved area 46 bytes 0x00 5380 DAC CR1 DAC control register 1 0x00 0x00 5381 DAC CR2 DAC control register 2 0x00 0x00 5382 to 0x00 5383 Reserved area 2 bytes 0x00 5384 DAC SWTRIGR DAC software trigger register 0x00 0x00 5385 DAC SR DAC status register 0x00 0x00 5386 to 0x00 5387 Reserved area 2 bytes 0x00 5388 DAC_RDHRH DAC right oo ae holding register 0x00 0x00 5389 AG DAC RDHRL
69. O o z ES c oja o c ei a OI a 9 16 sol kg c ind ira s OO I a sl Timer 1 channel 3 Timer 3 external PD1 TIM1_CH3 TIM3_ET DCD COM32 TT trigger LCD_COM3 9 G2 ADC1 IN21 COMP2 INP VOlg X X X HS X X Port D1 ADC1 IN21 8 COMP1 INP Comparator 2 positive input Comparator 1 positive input Timer 1 channel 1 PD2 TIM1 CH1 IT LCD segment 8 22 11 10 E4 LCD SEG8 VOlg X X X HS X X Port D2 ADC1 IN20 ADC1 IN20 COMP1 INP Comparator 1 positive input Timer 1 external trigger PD3 TIM1 ETR TT LCD segment 9 23 12 LCD SEG9 ADC1 IN1 I O mi X X X HS X X Port D3 ADC1 IN19 9 COMP1 INP Comparator 1 positive input Timer 1 external trigger roe lu LCD segment 9 LCD SEGS TT ADC1_IN19 Timer 1 111 F3 ADC1 IN19 TIM1 BKIN 1 0 3 X X X HS X X Port D3 break input RTC COMP1_INP calibration Comparator RTC_CALIB nde p 1 positive input Timer 1 channel 2 PD4 TIM1_CH2 TT LCD segment 18 33 21 20 C1 LCD_SEG18 O X X X HS X X Port D4 ADC1_IN10 ADC1_IN10 COMP1_INP Comparator 1 positive input POST cro E 34 22 LCD SEG1909 VO s X X X HS X X Port D5 anc gie Con de ADC1 IN9 COMP1 INP n H 1 positive input Timer 1 break input PD6 TIM1_BKIN LCD segment 20 LCD_SEG20 T ADC1_IN8 RTC 35 23 ADC1 IN8 RTC CALIB 1 0 3 X X X HS X X PortD6 calibration Internal VREFINT voltage reference outpu
70. ON 5 kQ Ro Output impedance DACOUT buffer OFF 8 10 kQ C Capacitive load 50 pF DACOUT buffer ON 0 2 Vppa 0 2 V DAC OUT DAC OUT voltage DACOUT buffer OFF 0 Vrer 1 LSB Settling time full scale for a 12 bit input code transition between tsetting the lowest and the highest input R 25 kQ Cj s 50 pF 7 12 us codes when DAC_OUT reaches the final value 1LSB Max frequency for a correct DAC_OUT 95 change i punte f id when small variation of the input Taie 1 Msps code from code i to i 1LSB Wakeup time from OFF state twaxeup Input code between lowest and RL 25 kQ C 50 pF 9 15 us highest possible codes Power supply rejection ratio to R 5k i E Ea VDDA static DC measurement Laake Cor pg 39 ER Pe A cM e 106 142 Resistive load between DACOUT and GNDA Output on PFO 48 pin package only Capacitive load at DACOUT pin It gives the output excursion of the DAC DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Electrical parameters In the following table data is based on characterization results not tested in production Table 51 DAC accuracy DN a applied Dm P o Difference between two consecutive codes 1 LSB Difference between the value measured at Code 0x800 and the ideal value Vpep 2 Difference between the value measured at Code 0x001 and the ideal value when buffer is ON and from
71. P mode except for the ROP and UBC values which can only be taken into account when they are modified in ICP mode with the SWIM Refer to the STM8L15x Flash programming manual PM0054 and STM8 SWIM and Debug Manual UM0470 for information on SWIM programming procedures Table 12 Option byte addresses Option Option bits Factory Addr Option name byte default No 7 6 5 4 3 2 1 0 setting Read out 0x00 4800 protection OPTO ROP 7 0 OxAA ROP 0x00 4802 UBC User Opry UBCI7 0 0x00 Boot code size 0x00 4807 Reserved 0x00 Independent OPTS3 WWDG WWDG IWDG IWDG 0x00 4808 watchdog 3 0 Reserved HALT HW HALT HW 0x00 option Number of stabilization 0x00 4809 clock cycles for OPT4 Reserved LSECNT 1 0 HSEONTT 1 0 0x00 HSE and LSE oscillators Brownout reset OPT5 BOR 0x00 480A BOR 3 0 Reserved BOR TH ON 0x00 0x00 480B Bootloader 0x00 option bytes pin OPTBL 15 0 Ox00480C OPTBL 15 0 0x00 Ly DoclD15962 Rev 14 59 142 Option bytes STM8L151x4 6 STM8L152x4 6 Table 13 Option byte description Option byte Option description No ROP 7 0 Memory readout protection ROP OPTO OxAA Disable readout protection write access via SWIM protocol Refer to Readout protection section in the STM8L15x and STM8L16x reference manual RM0031 UBC 7 0 Size of the user boot code area 0x00 no UBC 0x01 the UBC contains only the interrupt vectors
72. Port C2 ADC1_IN6 Comparator COMP1_INP VREFINT 1 positive input Internal voltage reference output USART1 transmit PC3 USART1_TX LCD segment 23 LCD_SEG23 TT ADC1_IN5 Comparator 42 28 24 A2l40c1 INS GOMP1 INP X X X HS X X Ports positive input COMP2_INM Comparator 2 negative input USART1 synchronous clock 12C1_SMB Parra ios B Configurable clock 2 TT output LCD segment 24 43 29 25 C2 LCD SEG24Y WO X X X HS X X Port C4 ADC1 IN4 ADC1 IN4 COMP2 INM COMP1 INP Comparator 2 negative input Comparator 1 positive input 32 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Pinout and pin description Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued Pin number Input Output e Ss t o Ou 0 amp al amp 5 SS Default alternate uu ag Pin name e 2 y 213 SE o o a a E O c 3 pun o o function L L A A a 2 x O n E e sl sl BO o z ES c oja o c ei a OI a 9 16 a E 5 sis ind ira s OO I a sl PC5 OSC32 IN LSE oscillator input 44 30 26 A3 SPI1 NSSI 1 0 x x x Hs X X Portes WEIT master slave USART1 Tx select USART1 transmit PC6 OSC32 OUT LSE oscillator output 45 31 27 B3 SPI1 SCH O X X X HS X X Port C6 SPI1 clock USART1 USART1_RX receive LCD segment 25 PC7 LCD SEG250 T ADC1 IN3 Co
73. Reset control register 0x00 0x00 50B1 RST_SR Reset status register 0x01 0x00 50B2 sie PWR CSR1 Power control and status register 1 0x00 0x00 50B3 PWR_CSR2 Power control and status register 2 0x00 0x00 50B4 to Reserved area 12 bytes 0x00 50BF 0x00 50C0 CLK_DIVR Clock master divider register 0x03 0x00 50C1 CLK_CRTCR Clock RTC register 0x00 0x00 50C2 CLK_ICKR Internal clock control register 0x11 0x00 50C3 CLK PCKENR1 Peripheral clock gating register 1 0x00 0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x80 0x00 50C5 CLK_CCOR Configurable clock control register 0x00 0x00 50C6 CLK_ECKR External clock control register 0x00 0x00 50C7 e CLK SCSR System clock status register 0x01 0x00 50C8 CLK SWR System clock switch register 0x01 0x00 50C9 CLK SWCR Clock switch control register Obxxxx0000 0x00 50CA CLK CSSR Clock security system register 0x00 0x00 50CB CLK CBEEPR Clock BEEP register 0x00 0x00 50CC CLK HSICALR HSI calibration register Oxxx 0x00 50CD CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CE CLK HSIUNLCKR HSI unlock register 0x00 0x00 50CF CLK REGCSR Main regulator control status register Obxx11100x Ky DoclD15962 Rev 14 43 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Address Block Register label Register name nese status 0x00 50D0 to Reserved area 3 bytes
74. S at 16 MHz while maintaining the advantages of a CISC architecture with improved code density a 24 bit linear addressing space and an optimized architecture for low power operations The family includes an integrated debug module with a hardware interface SWIM which allows non intrusive In Application debugging and ultra fast Flash programming All medium density STM8L15x microcontrollers feature embedded data EEPROM and low power low voltage single supply program Flash memory They incorporate an extensive range of enhanced I Os and peripherals The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32 bit families This makes any transition to a different family very easy and simplified even more by the use of a common set of development tools Six different packages are proposed from 28 to 48 pins Depending on the device chosen different sets of peripherals are included All STM8L ultra low power products are based on the same architecture with the same memory mapping and a coherent pinout DoclD15962 Rev 14 11 142 Description STM8L151x4 6 STM8L152x4 6 2 1 Device overview Table 2 Medium density STM8L151x4 6 and STM8L152x4 6 low power device features and peripheral counts Features STM8L151Gx STM8L15xKx STM8L15xCx Flash Kbyte 16 32 16 32 16 32 Data EEPROM Kbyte 1 RAM Kbyte 2
75. TM8L15xxx The STM8L and STM32L families allow a continuum of performance peripherals system architecture and features They are all based on STMicroelectronics 0 13 um ultra low leakage process The STM8L151xx and STM8L 152xx are pin to pin compatible with STM8L 101xx devices The STM32L family is pin to pin compatible with the general purpose STM32F family Please refer to STM32L15x documentation for more information on these devices Performance All families incorporate highly energy efficient cores with both Harvard architecture and pipelined execution advanced STM8 core for STM8L families and ARM Cortex M3 core for STM32L family In addition specific care for the design architecture has been taken to optimize the mA DMIPS and mA MHz ratios This allows the ultra low power performance to range from 5 up to 33 3 DMIPs Shared peripherals STM8L151 xx 152xx and STM8L15xxx share identical peripherals which ensure a very easy migration from one family to another e Analog peripherals ADC1 DAC and comparators COMP1 COMP2 e Digital peripherals RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance the STM8L151xx 152xx and STM8L15xxx devices use a common architecture e Same power supply range from 1 8 to 3 6 V down to 1 65 V at power down e Architecture optimized to reach ultra low consumption both in low power modes and Run mode e Fast startup strategy from low power
76. UFQFPN28 package pinout 26 STM8L151G4 STM8L151G6 WLCSP28 package pinout 00000 ue 27 STM8L152C4 STM8L152C6 48 pin pinout with LCD oo 27 STM8L152K4 STM8L152K6 32 pin package pinout with LCD 28 Memory map ute ee EE ha NG ghd OY bode EEN tan eae See e achat 38 Pin loading conditions 0 cece eee 63 Pin input voltage 2 aa eee ace EE AEN AS dE KON eee RR E 64 POR BOR thresholds 68 Typ IDD RUN vs VDD CRU 16 MHZ 0 00 eee 70 Typ IDD Wait vs VDD fCPU 2 GMT 73 Typ IDD LPR vs VDD LSI clock source 75 Typ IDD LPW vs VDD LSI clock source 77 HSE oscillator circuit diagram 2 2 tees 83 LSE oscillator circuit diagram eh 85 Typical HSI frequency vs Vpp 0 2 ce n 86 Typical LSI frequency vs VDD 2 tte eee 87 Typical VIL and VIH vs VDD high sink WOel 91 Typical VIL and VIH vs VDD true open drain I Os 0000 c eee eee 91 Typical pull up resistance Rpy vs Vpp with VIN VSS 0 0 0 0 0c eee eee 92 Typical pull up current lp vs Vpp With VINEVSS ee 92 Typ VOL O VDD 3 0 V high sink porte 94 Typ VOL O VDD 1 8 V high sink porte 94 Typ VOL VDD 3 0 V true open drain ports 000 0 ee eee 94 Typ VOL VDD 1 8 V true open drain ports 0 000 eee 94 Typ VDD VOH O VDD 3 0 V high sink porte 94 Typ VDD VOH O VDD 1 8 V high sink porte 94 Typical NRST pull up resistanc
77. YP AOBO ME V5 1 Drawing is not to scale Table 66 UFQFPN28 28 lead 4 x 4 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 0 500 0 550 0 600 0 0197 0 0217 0 0236 A1 0 000 0 050 0 0000 0 0020 D 3 900 4 000 4 100 0 1535 0 1575 0 1614 D1 2 900 3 000 3 100 0 1142 0 1181 0 1220 E 3 900 4 000 4 100 0 1535 0 1575 0 1614 E1 2 900 3 000 3 100 0 1142 0 1181 0 1220 L 0 300 0 400 0 500 0 0118 0 0157 0 0197 L1 0 250 0 350 0 450 0 0098 0 0138 0 0177 T 0 152 0 0060 0 200 0 250 0 300 0 0079 0 0098 0 0118 e 0 500 0 0197 DoclD15962 Rev 14 129 142 Package information STM8L151x4 6 STM8L152x4 6 1 Values in inches are converted from mm and rounded to 4 decimal digits Figure 56 UFQFPN28 28 lead 4 x 4 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 3 30 _ gt 0 30 AOBO_FP_V2 1 Dimensions are expressed in millimeters d 130 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 57 UFQFPN28 marking example package top view Product a identification gt 1 5 1 G y 3 Revision code Date code Dot pin 1 ww MS377
78. _CR3 USART1 control register 3 0x00 0x00 5237 USART1_CR4 USART1 control register 4 0x00 0x00 5238 USART1 CR5 USART1 control register 5 0x00 0x00 5239 USART1_GTR USART1 guard time register 0x00 0x00 523A USART1_PSCR USART1 prescaler register 0x00 0x00 523B to Reserved area 21 bytes 0x00 524F Ky DoclD15962 Rev 14 47 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Address Block Register label Register name Saree 0x00 5250 TIM2_CR1 TIM2 control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00 0x00 5255 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5256 TIM2 SR1 TIM2 status register 1 0x00 0x00 5257 TIM2 SR2 TIM2 status register 2 0x00 0x00 5258 TIM2 EGR TIM2 event generation register 0x00 0x00 5259 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 525A TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 525B TIM2 TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 525C TIM2 CNTRH TIM2 counter high 0x00 0x00 525D TIM2_CNTRL TIM2 counter low 0x00 0x00 525E TIM2_PSCR TIM2 prescaler register 0x00 0x00 525F TIM2_ARRH TIM2 auto rel
79. a cteristi6S viciado sca cac ca Coe fetal actae C aco aac aod ae RT C e Rc c 100 LCD Characteristics danita rd ee REEL STD S ere le Be eina Re Te PG 102 Reference voltage characteristics 103 DoclD15962 Rev 14 5 142 List of tables STM8L151x4 6 STM8L152x4 6 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 Table 65 Table 66 Table 67 Table 68 Table 69 6 142 TS Characteristics 2 aan a aaa iad rp E rue RR ee a 104 Comparator 1 characteristics 0 0 0 0 00 eens 104 Comparator 2 characteristics cece eens 105 DAG Characteristics eas see eed NEE a ee ey Pe ee oe 106 DAG ACTUA C XT 107 DAC output on DBA DDBRS PG 107 ADC1 characteristics somita a asedii ra tees 108 ADC1 accuracy with VDDA 3 3 V t02 5V cee 110 ADC1 accuracy with VDDA 2 4 V to 3 6V eee 110 ADC1 accuracy with VDDA VREF 1 8 V to 2 4 V nananana 110 Rain Max for fang 16 MHz n 112 dL 114 EMI Gata diia rs aia 115 ESD absolute maximum ratings 0 0 0 c eee eee 115 Electrical sensitivities 2 0 llle el 115 LQFP48 48 pin 7 x 7 mm low profile quad flat package mechanical data aaa ewe ca eet RUE Red e x A ras EE NANA 117 UFQFPN48 48 lead 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical dats 121 LQFP32 3
80. ame Sara 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register OxXX 0x00 500C Port C PC_DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register OxXX 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x00 0x00 5013 PD CR2 Port D control register 2 0x00 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register OxXX 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF_IDR Port F input pin value register OxXX 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 Table 9 General hardware register map ST z 0x00 501E to Reserved area 28 bytes 0x00 5049 0x00 5050 FLASH CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 0x00 5052 eds FLASH PUKR Flash program eet key 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00 0x00 5054 FLASH IAPSR Flash a d status 0x00 40 142 DoclD15962 Rev 14 er
81. aracteristics oooooooooooooooo o 82 9 3 5 Memory characteristics llle 88 9 3 6 I O current injection characteristics cee eee eee 89 9 3 7 I O port pin characteristics 89 DoclD15962 Rev 14 3 142 Contents STM8L151x4 6 STM8L152x4 6 9 3 8 Communication interfaces 97 9 3 9 LCD controller STM8L152xx only a 102 9 3 10 Embedded reference voltage eee 103 9 3 11 Temperature sensor 00002 cee eee 104 9 3 12 Comparator characteristics 104 9 3 13 12 bit DAC characteristics 0 0000 cee eee 106 9 3 14 12 bit ADC1 characteristics 20 0 llle 108 9 3 15 EMC characteristics a 0 0 00 ccc eee 114 10 Package information Adr AN wasn e e eae ee 116 10 1 EOOPAGK a xri haha Se 3 pr de eRe SS eS oo ra dendo 116 10 2 LQFP48 package information 00 c eee eee 116 10 3 UFQFPN48 package information 120 10 4 LQFP32 package information lille 123 10 5 UFQFPN32 package information ee eee eee 126 10 6 UFQFPN28 package information 129 10 7 WLCSP28 package information lille 132 10 8 Thermal characteristics 135 11 Part numbering A nh REESEN a EE e 136 12 Revision history iex dice dace S qw aci RC aee ee DAA OR RC RC Rc e 137 4 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Tabl
82. ccumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 Kbyte level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20 addressing modes e Indexed indirect addressing mode for lookup tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers Interrupt controller The medium density STM8L151x4 6 and STM8L152x4 6 feature a nested vectored interrupt controller e Nested interrupts with 3 software priority levels e 32 interrupt vectors with hardware priority e Up to 40 external interrupt sources on 11 vectors e Trap and reset interrupts 2 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Functional overview 3 3 3 3 1 3 3 2 3 3 3 2 Reset and supply management Power supply scheme The device requires a 1 65 V to 3 6 V operating supply voltage Vpp The external power supply pins must be connected as follows e Vss1 Vpp1 1 8 to 3 6 V
83. citance roughly 7 pF A high Coarasitic value will downgrade conversion accuracy To remedy this fapc should be reduced DoclD15962 Rev 14 111 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 conversion Figure 40 Maximum dynamic current consumption on Ver supply pin during ADC Conversion 12 cycles i Sampling n cycles 4 gt lt l ADC clock l 300pA Table 57 Bam max for fapc 16 MHz 1 Guaranteed by design not tested in production 112 142 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 41 or Figure 42 depending on whether Vppep is connected to Vppa or not Good quality ceramic 10 nF capacitors should be used They should be placed as close as possible to the chip Rain max kohm Ga We Slow channels Fast channels 2 4 V lt VppA lt 3 6 V 1 8 V lt Vppa lt 2 4 V 2 4 V lt Vppa lt 3 3 V 1 8 V lt Vppa lt 24 V 4 0 25 Not allowed Not allowed 0 7 Not allowed 9 0 5625 0 8 Not allowed 2 0 1 0 16 1 2 0 0 8 4 0 3 0 24 1 5 3 0 1 8 6 0 4 5 48 3 6 8 4 0 15 0 10 0 96 6 15 0 10 0 30 0 20 0 192 12 32 0 25 0 50 0 40 0 384 24 50 0 50 0 50 0 50 0 DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Electrical parameters Figure 41 Power supply and re
84. ckage Modified Figure Memory map and added 2 notes Modified Low power run mode in Section Low power modes Added Section Unique ID Modified Table Interrupt mapping added reserved area 11 Dec 2009 3 at address 0x00 8008 Modified OPT4 option bits in Table Option byte addresses Table Option byte description modified OPTO description disable instead of enable and OPT1 description Added OPTBL option bytes Modified Section Electrical parameters Changed title of the document STM8L151x4 STM8L151x6 STM8L152x4 STM8L152x6 Changed pinout Vss1 Vpp1 Vss2 Vpp 2 instead of Vss Von Vssio Vopio Changed packages Changed first page Modified note 1 in Table Medium density STM8L 15x pin description Added note to PA7 PCO PC1 and PEO in Table Medium density STM8L 15x pin description Desplat i Modified Figure Memory map Modified Table WLCSP28 28 pin wafer level chip scale package package mechanical data min and max columns swapped Modified Figure WLCSP28 28 pin wafer level chip scale package package outline A1 ball location Renamed Rm Lm and Cm EXTI CONF replaced with EXTI CONF1 in Table General hardware register map Updated Section Electrical parameters Ly DoclD15962 Rev 14 137 142 Revision history STM8L151x4 6 STM8L152x4 6 138 142 Table 69 Document revision history continued Date 23 Jul 2010 Revision Changes Modified n
85. clD15962 Rev 14 The time between 2 conversions or between ADC ON and the first conversion must be lower than tip E 109 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 In the following three tables data is guaranteed by characterization result not tested in production Table 54 ADC1 accuracy with Vppa 3 3 V to 2 5 V Symbol Parameter Conditions Typ Max Unit fanc 16 MHz 1 1 6 DNL Differential non linearity fapc 8 MHz 1 1 6 fapc 4 MHz 1 1 5 fanc 16 MHz 1 2 2 INL Integral non linearity fapc 8 MHz 1 2 1 8 LSB fApc 4 MHz 1 2 1 7 fanc 16 MHz 2 2 3 0 TUE Total unadjusted error fapc 8 MHz 1 8 2 5 fapc 4 MHz 1 8 2 3 fanc 16 MHz 1 5 2 Offset Offset error fanc 8 MHz 1 1 5 fApc 4 MHz 0 7 1 2 e fanc 16 MHz Gain Gain error fapc 8 MHz 1 1 5 fapc 4 MHz Table 55 ADC1 accuracy with Vppa 2 4 V to 3 6 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 1 7 3 LSB TUE Total unadjusted error 2 4 LSB Offset Offset error 1 2 LSB Gain Gain error 1 5 3 LSB Table 56 ADC1 accuracy with Vppa Vrer 1 8 V to 2 4 V Symbol Parameter Typ Max Unit DNL Differential non linearity 1 2 LSB INL Integral non linearity 2 3 LSB TUE Total unadjusted error 3 5 LSB Offset Offset error 2 3 LSB Gain Gain error 2 3 LSB 110 142 DoclD15962 Rev 14
86. ctory OxXX CONV conversion 0x00 4911 Nay ONV Temperature sensor output voltage OxXX 1 The VREFINT Factory CONV byte represents the 8 LSB of the result of the VREFINT 12 bit ADC conversion performed in factory The MSB have a fixed value Ox6 The 2 MSB have a fixed value 0x3 Table 8 I O port hardware register map The TS_Factory_CONV_V90 byte represents the 8 LSB of the result of the V90 12 bit ADC conversion performed in factory Address Block Register label Register name Wee 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register OxXX 0x00 5002 PortA PA_DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x01 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register OxXX 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 er DoclD15962 Rev 14 39 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 8 I O port hardware register map continued Address Block Register label Register n
87. de CPU and peripheral clocks are stopped except RTC The wakeup can be triggered by RTC interrupts external interrupts or reset Active halt consumption refer to Table 24 and Table 25 Halt mode CPU and peripheral clocks are stopped the device remains powered on The RAM content is preserved The wakeup is triggered by an external interrupt or reset A few peripherals have also a wakeup from Halt capability Switching off the internal reference voltage reduces power consumption Through software configuration itis also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 us Halt consumption refer to Table 26 DoclD15962 Rev 14 15 142 Functional overview STM8L151x4 6 STM8L152x4 6 3 2 3 2 1 3 2 2 16 142 Central processing unit STM8 Advanced STM8 Core The 8 bit STM8 core is designed for code efficiency and performance with an Harvard architecture and a 3 stage pipeline It contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching most instructions e XandY 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit a
88. e Startup time Vpp is stabilized 1 s 1 C C 4 C is approximately equivalent to 2 x crystal Cj 4p 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Ba value Refer to crystal manufacturer for more details 3 Data guaranteed by Design Not tested in production 4 tsuse is the startup time measured from the moment it is enabled by software to a stabilized 33 768 Hz oscillation This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer d DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters Figure 18 LSE oscillator circuit diagram Rm Lse gt Lm CoT Rr Cu Em EE e Been Ee Resonator Consumption o BIEN control sonator C OSCOUT L2 STM8 MSv37776V1 Internal clock sources Subject to general operating conditions for Vpp and Ta High speed internal RC oscillator HSI In the following table data is based on characterization results not tested in production unless otherwise specified Table 33 HSI oscillator characteristics on gt Vpp 3 0 V TA 40 to 125 C unless otherwise specified Tested in production Symbol Parameter Conditions Min Typ Max Unit fugi Frequency V
89. e 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Ly Device SUMMA rera e E a E a a a a a a a 1 Medium density STM8L151x4 6 and STM8L152x4 6 low power device features and peripheral counts e a E E a E aa e e a s 12 Timer feature comparison 2 eee 22 Legend abbreviation for table be 29 Medium density STM8L151x4 6 STM8L152x4 6 pin description 29 Flash and RAM boundary addresses nanana 39 Factory conversion registers ce teens 39 I O port hardware register map 39 General hardware register map 40 CPU SWIM debug module interrupt controller registers 55 Interrupt mapping o erpai aisee e e RR RR hh 57 Option byte addresses 0 cc ea 59 Option byte description n 60 Unique ID registers 96 bits 0 0 BB 62 Voltage characteristics ents 64 Current characteristics 65 Thermal characteristics ritis adre easa daaa EAE A E EEA A E A a a 65 General operating conditions 66 Embedded reset and power control block characteristics
90. e Rpy vs VDD ee eee eee 95 Typical NRST pull up current lgu PSV aerials ee pee hie aes wee NG 96 Recommended NRST pin configuration 0000 eee 96 SPI1 timing diagram slave mode and CPHA 0 0 0 00 eee 98 SPI1 timing diagram slave mode and CPHA 1 A EE 98 SPI1 timing diagram master nU MMC 99 Typical application with I2C bus and timing diagram 1 101 ADC1 accuracy characteristics 2 111 Typical connection diagram using the ADC 2 0 0 0 cee 111 Maximum dynamic current consumption on Vpep supply pin during ADC CONVEISION M 112 Power supply and reference decoupling Vref not connected to Vppa 113 Power supply and reference decoupling VREF connected to VDDA 113 LQFP48 48 pin 7 x 7 mm low profile quad flat package outline 116 LQFP48 48 pin 7 x 7 mm low profile quad flat package recommended footprint lille eee eee 118 LQFP48 marking example package top view 119 UFQFPN48 48 lead 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat DoclD15962 Rev 14 7 42 List of figures STM8L151x4 6 STM8L152x4 6 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 8 142 package outline 2 6 rn 120 UFQFPN48 48 lead 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footpri
91. egister 0x00 0x00 52B9 TIM1 CCMR1 TIM1 Capture Compare mode register 1 0x00 0x00 52BA TIM1 CCMR2 TIM1 Capture Compare mode register 2 0x00 0x00 52BB TIM1_CCMR3 TIM1 Capture Compare mode register 3 0x00 0x00 52BC TIM1_CCMR4 TIM1 Capture Compare mode register 4 0x00 0x00 52BD TIM1 CCER1 TIM1 Capture Compare enable register 1 0x00 0x00 52BE TIM1_CCER2 TIM1 Capture Compare enable register 2 0x00 0x00 52BF TIM1_CNTRH TIM1 counter high 0x00 0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00 0x00 52C1 are TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 52C3 TIM1_ARRH TIM1 Auto reload register high OxFF 0x00 52C4 TIM1_ARRL TIM1 Auto reload register low OxFF 0x00 52C5 TIM1 RCR TIM1 Repetition counter register 0x00 0x00 52C6 TIM1 CCR1H TIM1 Capture Compare register 1 high 0x00 0x00 52C7 TIM1 CCR1L TIM1 Capture Compare register 1 low 0x00 0x00 52C8 TIM1 CCR2H TIM1 Capture Compare register 2 high 0x00 0x00 52C9 TIM1 CCR2L TIM1 Capture Compare register 2 low 0x00 0x00 52CA TIM1 CCR3H TIM1 Capture Compare register 3 high 0x00 0x00 52CB TIM1 CCRS3L TIM1 Capture Compare register 3 low 0x00 0x00 52CC TIM1_CCR4H TIM1 Capture Compare register 4 high 0x00 0x00 52CD TIM1_CCR4L TIM1 Capture Compare register 4 low 0x00 0x00 52CE TIM1_BKR TIM1 break register 0x00 0x00 52CF TIM1_DTR TIM1 dead time register 0x00 0x00 52D0 TIM1 OISR TIM1 output idle state register 0x00 0x00 52D1 TIM1 DCR1 DMA1 control register 1 0x00 50 142 Docl
92. er STM8L151x4 6 STM8L152x4 6 Electrical parameters 2 Figure 38 ADC1 accuracy characteristics V V 1LSB BEF or PPA depending on package IDEAL 1196 4096 cpending on packag NM Xx de 1 Example of an actual transfer curve 7 I 2 The ideal transfer curve 4094 zt 1 3 End point correlation line 4093 TI Er Total Unadjusted Error maximum deviation is ed 1 Er 7 between the actual and the ideal transfer curves 7 i P Eo Offset Error deviation between the first actual 6 PES m 1 transition and the first ideal one 1 i i 1 Eg Gain Error deviation between the last ideal 5 Le transition and the last actual one Eo A e EL Ep Differential Linearity Error maximum deviation 4 i i p i between actual steps and the ideal one 3 1 1 T z 1 E Integral Linearity Error maximum deviation 1 Ba n Ep i between any actual transition and the end point 2 z Lab 1 correlation line 1 MEE d 1 LSBipgar Pil A p E 0 1 2 3 4 5 6 7 4093 4094 4095 4096 Vssa DDA ai14395b Figure 39 Typical connection diagram using the ADC VoD STM8 Sample and hold ADC converter 12 bit converter VT 2 parasitic ZN 0 6V I X ai17090f Refer to Table 53 for the values of Rain and Capc Cparasitic represents the capacitance of the PCB dependent on soldering and PCB layout quality plus the pad capa
93. et trigger and enable 8 bit basic timer The 8 bit timer consists of an 8 bit up auto reload counter driven by a programmable prescaler lt can be used for timebase generation with interrupt generation on timer overflow or for DAC trigger generation Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Window watchdog timer The window watchdog WWDG is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence Independent watchdog timer The independent watchdog peripheral IWDG can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the internal LSI RC clock source and thus stays active even in case of a CPU clock failure Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz DoclD15962 Rev 14 23 142 Functional overview STM8L151x4 6 STM8L152x4 6 3 17 3 17 1 Note 3 17 2 Note 3 17 3 Note 3 18 24 142 Communication interfaces SPI The serial peripheral interface SPI1 provides half full duplex synchronous serial communication with external devices e Maximum speed 8 Mbit s fgysc_K 2 both for master and slave e Full duplex synchronous transfers e Simplex
94. f SWIM input 0 X X9 X lao X X Port AO and output Beep output Infrared Timer output PAOS USART1 CK 9 32 lasa law SWIM BEEP IR TIM 10 8 9 10 At power up the PA1 NRST pin is a reset input pin with pull up To be used as a general purpose pin PA1 it can be configured only as output open drain or push pull not as a general purpose input Refer to Section Configuring NRST PA1 pin as general purpose output in the STM8L15x and STM8L 16x reference manual RM0031 Available on STM8L152xx devices only In the 3 6 V tolerant I Os protection diode to Vpp is not implemented Alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function In the 5 V tolerant I Os protection diode to Vpp is not implemented A pull up is applied to PBO and PB4 during the reset phase These two pins are input floating after reset release In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented Available on STM8L151xx devices only The PAO pin is in input pull up during the reset phase and after reset release High Sink LED driver capability available on PAO Note The slope control of all GPIO pins except true open drain pins can be programmed By 36 142 DoclD15962 Rev 14 default the slope control is limited
95. f data EEPROM Option bytes The EEPROM embeds the error correction code ECC feature It supports the read while write RWW it is possible to execute the code from the program matrix while programming erasing the data matrix The option byte protects part of the Flash program memory from write and readout piracy DMA A 4 channel direct memory access controller DMA1 offers a memory to memory and peripherals from to memory transfer capability The 4 channels are shared between the following IPs with DMA capability ADC1 DAC 12C1 SPI1 USARTI the four Timers Analog to digital converter e 12 bit analog to digital converter ADC1 with 25 channels including 1 fast channel temperature sensor and internal reference voltage e Conversion time down to 1 us with fsyscLK 16 MHz e Programmable resolution e Programmable sampling time e Single and continuous mode of conversion e Scan capability automatic conversion performed on a selected group of analog inputs e Analog watchdog e Triggered by timer DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Functional overview Note 3 10 Note 3 11 3 12 3 13 2 ADC1 can be served by DMA1 Digital to analog converter DAC e 12 bit DAC with output buffer e Synchronized update capability using TIM4 e DMA capability e External triggers for conversion e Input reference voltage Vref for better resolution DAC can be served by DMA1 Ultra low po
96. ference decoupling Vref not connected to VppA External reference 1 uF 10 nF Supply 1 pF 10 nF VSSA VREF ai17031c Figure 42 Power supply and reference decoupling per connected to VppA VREF VDDA Supply 1 uF 10 nF VREF VDDA ai17032c 2 DoclD15962 Rev 14 113 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 15 114 142 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility Based on a simple running application on the product toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical applica
97. fopy 125 kHz 0 43 0 55 0 56 0 58 0 62 Luz 1 MHz 0 60 0 77 0 80 0 82 0 87 HSI R S a fopy 4 MHz 1 11 1 34 1 37 1 39 1 43 OSC fcpy 8MHz 1 90 2 20 2 23 2 31 2 40 i fopy 16 MHz 3 8 4 60 4 75 4 87 4 88 peripherals fopy 125 kHz 0 30 0 36 0 39 0 44 0 47 Supply OFF code i current executed HSE external fcpy 1 MHz 0 40 0 50 0 52 0 55 0 56 DD RUN in Run from Flash clock m i fopy 4 MH mode yen rom fceu fuse CPU z 1 15 1 31 1 40 1 45 1 48 165Vto fopy 8MHz 2 17 233 244 2 56 2 77 3 6 V fcpu 16 MHz 4 0 446 4 52 4 59 4 77 LSI RC osc fcpu fL si 0 110 0 123 0 130 0 140 0 150 LSE ext clock 32 768 fou fLSE 0 100 0 101 0 104 0 119 0 122 kHz 10 1 All peripherals OFF Vpp from 1 65 V to 3 6 V HSI internal RC osc torpu fsyscLk 2 For devices with suffix 6 3 For devices with suffix 7 4 For devices with suffix 3 ky DoclD15962 Rev 14 69 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 CPU executing typical data processing The run from RAM consumption can be approximated with the linear formula Ipp run_from_RAM Freq 90 uA MHz 380 pA 7 Oscillator bypassed HSEBYP 1 in CLK_ECKCR When configured for external crystal the HSE consumption Ibp Hse must be added Refer to Table 31 Tested in production The run from Flash consumption can be approximated with the linear formula Ipp run from Flash Freq 195 nA MHz 44
98. gment 47 PVD IN O 3 X X X HS X X Port E6 26 PVD IN 48 PE7 LCD_SEG27 UO n X X X HS X X Port E7 LCD segment 27 PFO ADC1 IN24 TT 32 DAC OUT Oil X X X HS X X Port FO ADC1_IN24 DAC OUT 13 9 VLCD S LCD booster external capacitor 13 Reserved Reserved Must be tied to Vpp 10 Vpp S Digital power supply 11 VppA Analog supply voltage ai II lv s T _ _ ADC1 and DAC positive voltage REF reference DoclD15962 Rev 14 35 142 Pinout and pin description STM8L151x4 6 STM8L152x4 6 Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued n Pin umber Input Output LQFP48 UFQFPN48 Default alternate Pin nam ame function Type UO level floating wpu Main function after reset LQFP32 UFQFPN32 UFQFPN28 WLCSP28 Ext interrupt High sink source OD PP Digital power supply Analog G4 Vppi VppA Vngr s supply voltage ADC1 positive voltage reference co N I O ground Analog ground voltage 7 6 F4 Vssi Vssa Vngr aa Ba Ka kal EA E ADC1 negative voltage reference 39 Vppe S IOs supply voltage 40 Vss2 s Os ground voltage USART1 synchronous HS clock
99. herals ADC DAC SPI DC USART timers 1 channel for memory to memory April 2015 9 m Datasheet production data E UN LaFe4s UFQFPNA8 ZA UFQFPNS2 5x5 mm 7x7 mm fxcmm LQFP32 mM 7x7 mm UFQFPN28 4x4 mm WLCSP28 12 bit DAC with output buffer 12 bit ADC up to 1 Msps 25 channels T sensor and internal reference voltage 2 ultra low power comparators 1 with fixed threshold and 1 rail to rail Wakeup capability Timers Two 16 bit timers with 2 channels used as IC OC PWM quadrature encoder One 16 bit advanced control timer with 3 channels supporting motor control One 8 bit timer with 7 bit prescaler 2watchdogs 1 Window 1 Independent Beeper timer with 1 2 or 4 kHz frequencies Communication interfaces Synchronous serial interface SPI Fast 12C 400 kHz SMBus and PMBus USART ISO 7816 interface and IrDA Up to 41 I Os all mappable on interrupt vectors Up to 16 capacitive sensing channels supporting touchkey proximity linear touch and rotary touch sensors Development support Faston chip programming and non intrusive debugging with SWIM Bootloader using USART 96 bit unique ID Table 1 Device summary Reference Part number STM8L151xx STM8L151C4 STM8L151C6 STM8L151K4 without LCD STM8L151K6 STM8L151G4 STM8L151G6 STM8L152xx STM8L152C4 STM8L152C6 STM8L152K4 with LCD STM8L152K6 DoclD
100. ication letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity d 122 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information 10 4 LQFP32 package information Figure 49 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE bira sil o ba IF OTTEN 0 25 mm GAUGE PLANE 5V_ME_V2 1 Drawing is not to scale 2 DoclD15962 Rev 14 123 142 Package information STM8L151x4 6 STM8L152x4 6 Table 64 LAFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 S E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835
101. identifier MS37783V1 1 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 2 DoclD15962 Rev 14 119 142 Package information STM8L151x4 6 STM8L152x4 6 10 3 120 142 UFQFPN48 package information Figure 46 UFQFPNAS 48 lead 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline Pin 1 identifier laser marking area A Seating plane D lt __ _ y Exposed pad area uM t E2 Detail Z C 0 500x45 pin1 corner R 0 125 typ OO Z A0B9 ME V3 1 Drawing is not to scale All leads pads should also be soldered to the PCB to improve the lead pad solder joint life There is an exposed die pad on the underside of the UFQFPN package It is recommended to connect and solder this back side pad to PCB ground DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Package information Table 63 UFQFPN48 48 lead 7 x 7 mm 0 5 mm pitch ultra thin fine pitch quad flat package mechanical data
102. ification activity d DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information 10 8 Thermal characteristics The maximum chip junction temperature T Jmax must never exceed the values given in Table 18 General operating conditions on page 66 The maximum chip junction temperature T max in degree Celsius may be calculated using the following equation T ymax TAmax PDmax X ya Where Tamax is the maximum ambient temperature in C Oja is the package junction to ambient thermal resistance in C W PDmax is the sum of Pintmax and Pjjomax PDmax Pintmax Pivomax Pintmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Promax represents the maximum power dissipation on output pins Where PyOmax E Nool 2 Vpp Vou on taking into account the actual Vo lo and Voy lon of the I Os at low and high level in the application Table 68 Thermal characteristics Symbol Parameter Value Unit Gy a oe EE 65 C W A ape e id 32 C W M Mun oo o od 59 C W ja Mee nc en 38 C W T MT cc eno 118 C W Oy icc cine junction ambient 70 C W 1 2 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment DoclD15962 Rev 14 135 142 Part numbering STM8L151x4 6 STM8L152x4 6 11 Part numbering For a list of available options memory package and so on or for further informa
103. ined for ADC output reaching its final value 1 2LSB Comparator characteristics In the following table data is guaranteed by design not tested in production unless otherwise specified Table 48 Comparator 1 characteristics Symbol Parameter Min Typ Max Unit Vppa Analog supply voltage 1 65 3 6 V TA Temperature range 40 125 C Raook Raook value 300 400 500 Riok R4ok value 7 5 10 12 5 VIN Comparator 1 input voltage range 0 6 VDDA VREFINT Internal reference voltage 1 202 1 224 1 242 Y tsTART Comparator startup time 7 10 ta Propagation delay 3 10 E Vottset Comparator offset error E 3 10 mV IcoMP1 Current consumption 7 160 260 nA 1 Based on characterization not tested in production Tested in production at Vpp 3 V 10 mV The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non inverting input set to the reference DoclD15962 Rev 14 Comparator consumption only Internal reference voltage not included 2 STM8L151x4 6 STM8L152x4 6 Electrical parameters 2 In the following table data is guaranteed by design not tested in production Table 49 Comparator 2 characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage E 1 65 3 6 V TA Temperature range 40 125 C Vin Comparator 2 i
104. ion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 31 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fuse a speed external oscillator 1 16 MHz requency Re Feedback resistor 200 kQ c Recommended load capacitance 2 S 20 S pF C 20 pF 2 5 startup fosc 16 MHz 0 7 stabilized 9 loose HSE oscillator power consumption mA C 10 pF 2 5 startup fosc 16 MHz 0 46 stabilized 9 Om Oscillator transconductance S 3 513 E mA V tsuHse Startup time Vpp is stabilized 1 E ms 1 C C C is approximately equivalent to 2 x crystal Cj oap 2 Refer to crystal manufacturer for more details 3 Data guaranteed by Design Not tested in production The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value tsu Hse is the startup time measured from the moment it is enabled by software to a stabilized 16 MHz oscillation This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer 2 Figure 17 HSE oscillator circuit diagram Rm fuse to core gt Lm Co s Rp C Cm x OSCIN io rb ERE e e 9n Resonator Consumption Resonator co
105. it External clock source Just eat 1 16 MHz frequency OSC_IN input pin high level E VHSEH Voltage 0 7 x Vpp Vpp OSC_IN input pin low level VHSEL voltage Vss 0 3 x Vpp OSC_IN input Cj is 2 6 F IHSE capacitance P OSC_IN input leakage ILEAK HSE current Vss lt Vin lt Vpp S e 1 HA Data guaranteed by Design not tested in production LSE external clock LSEBYP 1 in CLK ECKCR Subject to general operating conditions for Vpp and Ta Table 30 LSE external clock characteristics Symbol Parameter Min Typ Max Unit fLSE_ext External clock source frequency 32 768 kHz VisEH OSC32 IN input pin high level voltage 0 7 x Vpp Vpp V Vise OSC32_IN input pin low level voltage Vss 0 3 x Vop Cin LSE OSC32 IN input capacitance s 0 6 pF lLEAK LSE OSC32 IN input leakage current 1 yA 1 Data guaranteed by Design not tested in production 2 Data based on characterization results not tested in production 82 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Electrical parameters HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distort
106. latency 3 5 l fsvscik 108 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Electrical parameters Table 53 ADC1 characteristics continued Symbol Parameter Conditions Min Typ Max Unit VAIN on PFO fast channel 0 43 4 5 E us VDDA lt 2 4 V VAIN on PFO fast EE channel 0 22 4 5 us ts Sampling time 2 4 V Nppas 3 6 V Vain on slow channels 4 5 Vppa lt 2 4 V 0 88 ER Vain on slow channels 4 5 I 24VNopac3 ev 9 dd S 124 ts l fApc teonv 12 bit conversion time 16 MHz 1 4 us Wakeup time from OFF WKUP state S 5 3 us Ta 25 C 10 s Time before a new 6 7 or conversion TANG sa pi Ta 125 C 20 ms t Internal reference refer to ms VREFINT voltage startup time Table 46 1 The current consumption through Vpegp is composed of two parameters one constant max 300 pA one variable max 400 pA only during sampling time 2 first conversion pulses So peak consumption is 300 400 700 yA and average consumption is 300 4 sampling 2 16 x 400 450 pA at 1Msps PD IU BO NO 2 Vngr OF Vppa must be tied to ground Guaranteed by design not tested in production Value obtained for continuous conversion on fast channel The tip_e maximum value is coon the Z revision code of the device Minimum sampling and conversion time is reached for maximum Rext 0 5 kQ Do
107. m allowed input voltage values When several inputs are submitted to a current injection the maximum liy up is the absolute sum of the positive and negative injected currents instantaneous values Table 17 Thermal characteristics Symbol Ratings Value TsTG Storage temperature range 65 to 150 Ty Maximum junction temperature 150 Unit C DoclD15962 Rev 14 65 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 Operating conditions Subject to general operating conditions for Vpp and Ta 9 3 1 General operating conditions Table 18 General operating conditions Symbol Parameter Conditions Min Max Unit fsyseLK O 1 65 V Vpp lt 3 6 V 0 16 MHz Von E paang 1650 36 V ADC and DAC 1 650 3 6 V V Analog operating not used Must be at the same REM voltage ADC or DAC potential as Vpp 1 8 3 6 V used LQFP48 288 UFQFPN48 169 Power dissipation at LQFP32 288 Taz 85 C for suffix 6 devices UFQFPN32 169 UFQFPN28 169 WLCSP28 S 286 Pp mw LQFP48 77 Power dissipation at UFQFPN48 156 Taz 125 C for suffix 3 LQFP32 85 devices and at Taz 105 C for suffix 7 UFQFPN32 E 181 devices UFQFPN28 42 WLCSP28 71 1 65 V lt Vpp lt 3 6 V 6 suffix version 40 85 Ta Temperature range 1 65 V lt Vpp lt 3 6 V 7 suffix version 40 105 C 1 65 V lt Vpp lt 3 6 V 3 suffix version 40 125 40 C lt TA lt 85 C
108. mparator 46 ADC1_IN3 COMP2_INM lOlg X X X HS X X PortC7 negative input COMP1_INP Comparator 1 positive input Timer 3 channel 2 PDO TIMS10 i ADC1 Trigger LCD ADC1 TRIGf TT segment 7 ADC1_IN22 20 8 G3 LCD_SEG7 ADC1_IN2 I O 3 X X X HS X X Pont DO 2 COMP2 INP m input Comparator COMETE positive input Timer 3 channel 2 PDO TIM3_CH2 ADC1 Trigger _ _ ADC1 TRIGO TT Port ADC1 IN22 S ADC1_IN22 COMP2_INP MOX X X BS XD Comparator 2 positive COMP1_INP input Comparator 1 positive input Timer 3 external trigger PD1 TIM3 ETR LCD COM3 LCD COM3 TT ADC1 IN21 1 lapci iN2t COMP2 Weill X X X HS X X PortD1 omparator 2 positive COMP1_INP input Comparator 1 positive input Timer 3 external trigger TIM1 inverted PD1 TIM1 CHSN TIMS Se SEA channel 3 LCD COM3 10 ADC1_IN21 COMP2_INP O 3 X X X HS X X Port D1 Al 8 COMP1 INP omparator 2 positive a input Comparator 1 positive input 2 DoclD15962 Rev 14 33 142 Pinout and pin description STM8L151x4 6 STM8L152x4 6 Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued Pin Ambar Input Output JE Se t o o 0 5 amp al sl 53 Default alternate Lum S Pin name ge 35 313 S oO OIZ a s o E 5 o o function L L A A a 2 x O n E e sl sl B
109. nEFNT VREFINT Factory CONV byte i my Stability of VREFINT over 40 C lt Ta lt temperature 125 C i Si ppm C STABVREFINT Stability of V abiiy OF YREFINT OVOr OC lt TAS50O C 20 mmm temperature Stability of V after 1000 STABVREFINT EE y REFINT S TBD ppm Defined when ADC output reaches its final value 1 2LSB Data guaranteed by Design Not tested in production Tested in production at Vpp 3 V 10 mV To guaranty less than 1 Vpepour deviation a pon gt Measured at Vpp 3 V 10 mV This value takes into account Vpp accuracy and ADC conversion accuracy 2 DoclD15962 Rev 14 103 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 11 9 3 12 104 142 Temperature sensor In the following table data is based on characterization results not tested in production unless otherwise specified Table 47 TS characteristics Symbol Parameter Min Typ Max Unit V425 Sensor reference voltage at 90 C 5 C 0 640 0 660 0 680 V TL Vsenson linearity with temperature S 1 2 C Avg slope Average slope 1 59 1 62 1 65 mV C IDo TEMP Consumption 3 4 6 UA Teranr 9 Temperature sensor startup time i 10 us E ee pali UA when reading the 10 i T 1 Tested in production at Vpp 3 V 10 mV The 8 LSB of the Von ADC conversion result are stored in the TS Factory CONV V90 byte Data guaranteed by design not tested in production Def
110. nels IE 16 bit Timer 1 lt gt program memory 8 bit Timer 4 lt o FH 1 Kbyte data EEPROM o IR TIM G1 r1 Infrared interface x gt 9 ame RE 2 Kbyte RAM o DMA1 5 4 channels lt gt o SEL Port A PA 7 0 SCL SDA SMB lt ID CH SE E E Port B PB 7 0 MOSI MISO Ar 75 8 SCK NSS SPI1 lt lt n pium Port C PC 7 0 9 RX TX CK LT USART1 lt gt 3 XI gt Port D CLE PD 7 0 4 lt x VDDA i Vssa VDDANVSSA psi Port E T gt PE 7 0 ADC1_INx lt Pot Ka Pro VREF 12 bit ADC1 cm VREF Temp sensor Beeper LLL BEEP RTC HIT ALARM CALIB VREFINT out lt Internal reference voltage lt i IWDG 38 kHz clock COMP1_INP COMP2 INP Cal COMP 1 lt COMP2 INM Sane psi WWDG e VREF 12 bit DAC tx LCD driver EV 4x28 SEGx COMx Vico 2 5 V LCD booster to 3 6V MS32627V2 1 Legend ADC Analog to digital converter BOR Brownout reset DMA Direct memory access DAC Digital to analog converter 12C Inter integrated circuit multi master interface 14 142 DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Functional overview IWDG Independent watchdog LCD Liquid crystal display POR PDR Power on reset power down reset RTC Real time clock SPI Serial peripheral interface SWIM Single wire interface module USART Universal synchronous asynchronous receiver transmitter WWDG Window watchdog 3 1 Low power modes The medium density STM8L151x4 6 and STM8L152x4 6 devices support five low power modes
111. nput voltage range 0 VDDA V Fast mode 15 20 tstaRT Comparator startup time Slow mode 20 25 lt iise is as t Propagation delay in slow mode BEY 27V Vpas os e us 3 6 V Pee pus d 0 8 2 ld fast Propagation delay in fast mode 2 7 V Nppa 12 4 3 6 V l Vottset Comparator offset error 4 20 mV e 3 Fast mode 3 5 5 IcoMP urrent consumption H SCH Slow mode 0 5 2 1 Based on characterization not tested in production 2 The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input the non inverting input set to the reference 3 Comparator consumption only Internal reference voltage not included DoclD15962 Rev 14 105 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 13 12 bit DAC characteristics In the following table data is guaranteed by design not tested in production Table 50 DAC characteristics Symbol Parameter Conditions Min Typ Max Unit VDDA Analog supply voltage 1 8 3 6 V VREF Reference supply voltage 1 8 S VDDA VREF 3 3 V no load middle code 130 220 Current consumption on Vggr Ox800 VREF supply VREF 3 3 V no load worst code 220 350 0x000 HA VDDA 3 3 V no load middle code 210 320 Current consumption on Vppa 0x800 VDDA supply Vppa 3 3 V no load worst code lt 320 520 0x000 TA Temperature range 40 125 C RL Resistive load 2 DACOUT buffer
112. nt asnasa 0 ce eee 121 UFQFPNA8 marking example package top view cee eee eee eee 122 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 123 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint tne tee 125 LQFP32 marking example package top view 125 UFQFPN32 32 pin 5 x 5 mm 0 5 mm pitch ultra thin fine pitch quad flat package QUI INS pa cee x NAGA dtes ee a deo x RO ne KANG he a e S AE a dedo 126 UFQFPN32 32 pin 5 x 5 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint 0 0 tees 127 UFQFPN32 marking example package top view 128 UFQFPN238 28 lead 4 x 4 mm 0 5 mm pitch ultra thin fine pitch quad flat package outline 2 6 hh hr 129 UFQFPNO2S8 28 lead 4 x 4 mm 0 5 mm pitch ultra thin fine pitch quad flat package recommended footprint llle 130 UFQFPN28 marking example package top view 131 WLCSP28 28 pin 1 703 x 2 841 mm 0 4 mm pitch wafer level chip scale package outlines s ce kho Rex RUE E KORR I Kex acida Sad ala AE Je al T EE A 132 WLCSP28 marking example package top view 134 Medium density STM8L15x ordering information scheme sssasa annae 136 2 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Introduction 1 Introduction This document describes the features pinout mechanical data and ordering information of the medium density STM8L15
113. ntrol C OSCOUT L2 STM8 MS36490V2 DoclD15962 Rev 14 83 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 84 142 HSE oscillator critical gm formula Imerit 2X TIX fyse x Rm 2C0 C Rm Motional resistance see crystal specification Lm Motional inductance see crystal specification Cm Motional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42 5 C Grounded external capacitance Om gt gt merit LSE crystal ceramic resonator oscillator The LSE clock can be supplied with a 32 768 kHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 32 LSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fige GE external oscillator 32 768 kHz Re Feedback resistor AV 200 mV S 1 2 MQ c Recommended load capacitance 2 F 8 pF 114 yA loose LSE oscillator power consumption PAGE ROME a AT Vpp23V 600 nA Vpp 3 6 V 750 Om Oscillator transconductance 3 S z PAN tsus
114. o o oooooooo 67 Total current consumption in Run mode 69 Total current consumption in Wait mode 71 Total current consumption and timing in Low power run mode at VDD 1 65 V103 6 V La ae ct RR RE ra Mae ea Re AC OR ade lee 74 Total current consumption in Low power wait mode at VDD 1 65 V to 3 6 V 76 Total current consumption and timing in Active halt mode at VDD 1 65 V to 3 6 V 78 Typical current consumption in Active halt mode RTC clocked by LSE external crystal 80 Total current consumption and timing in Halt mode at VDD 1 65 to 3 6 V 80 Peripheral current consumption eae 81 Current consumption under external reset 2l eee 82 HSE external clock characteristics liliis 82 LSE external clock characteristics 82 HSE oscillator characteristics illie 83 LSE oscillator characteristics 0 0 0 0 teen eens 84 HSI oscillator characteristics llle 85 LSI oscillator characteristics 0 0 0 nent eens 86 RAM and hardware registers ete 88 Flash program and data EEPROM memon 000 cee eens 88 I O current injection susceptibility llle 89 I O static characteristics eh 90 Output driving current high sink porte 93 Output driving current true open drain porte 93 Output driving current PAO with high sink LED driver capability 93 NRST pin characteristics 95 SPId1 chiaracterislics uds AA 97 2G char
115. o the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in run mode through a configuration register e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory e System clock sources 4 different clock sources can be used to drive the system clock 1 16 MHz High speed external crystal HSE 16 MHz High speed internal RC oscillator HSI 32 768 kHz Low speed external crystal LSE 38 kHz Low speed internal RC LSI e RTC and LCD clock sources the above four sources can be chosen to clock the RTC and the LCD whatever the system clock e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If a HSE clock failure occurs the system clock is automatically switched to HSI e Configurable main clock output CCO This outputs an external clock for use by the application 2 DoclD15962 Rev 14 STM8L
116. oad register high OxFF 0x00 5260 TIM2_ARRL TIM2 auto reload register low OxFF 0x00 5261 TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5262 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5263 TIM2 CCR2H TIM2 capture compare register 2 high 0x00 0x00 5264 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5265 TIM2 BKR TIM2 break register 0x00 0x00 5266 TIM2 OISR TIM2 output idle state register 0x00 E Reserved area 25 bytes 48 142 DoclD15962 Rev 14 Ky STM8L151x4 6 STM8L152x4 6 Memory and register map Table 9 General hardware register map continued Address Block Register label Register name ree 0x00 5280 TIM3_CR1 TIM3 control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00 0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00 0x00 5286 TIM3 SR1 TIM3 status register 1 0x00 0x00 5287 TIM3_SR2 TIMS status register 2 0x00 0x00 5288 TIM3_EGR TIM3 event generation register 0x00 0x00 5289 TIM3 CCMR1 TIM3 Capture Compare mode register 1 0x00 0x00 528A TIM3_CCMR2 TIM3 Capture Compare mode register 2 0x00 0x00 528B TIM3 TIM3_CCER1 TIM3 Capture Compare enable register 1 0x00 0x00
117. oltage below Vgg or above Vpp for standard pins should be avoided during normal product operation However in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens susceptibility tests are performed on a sample basis during device characterization Functional susceptibility to I O current injection While a simple application is executed on the device the device is stressed by injecting current into the I O pins programmed in floating input mode While current is injected into the I O pin one at a time the device is checked for functional failures The failure is indicated by an out of range parameter ADC error out of spec current injection on adjacent pins or other functional failure for example reset oscillator frequency deviation LCD levels etc The test results are given in the following table Table 37 I O current injection susceptibility Functional susceptibility Symbol Description Negative Positive Unit injection injection Injected current on true open drain pins PCO and 5 40 PC1 lij Injected current on all five volt tolerant FT pins 5 4 0 mA Injected current on all 3 6 V tolerant TT pins 5 0 Injected current on any other pin 5 5 UO port pin characteristics General characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified All unused pins must be kept at a fi
118. ontinued Option byte Option description No BOR_ON 0 Brownout reset off OPT5 1 Brownout reset on BOR_TH 3 1 Brownout reset thresholds Refer to Table 23 for details on the thresholds according to the value of BOR_TH bits OPTBL 15 0 This option is checked by the boot ROM code after reset Depending on OPTBL content of addresses 00 480B 00 480C and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UM0560 bootloader user manual for more details 2 DoclD15962 Rev 14 61 142 Unique ID STM8L151x4 6 STM8L152x4 6 8 Unique ID STM8 devices feature a 96 bit unique device identifier which provides a reference number that is unique for any device and in any context The 96 bits of the identifier can never be altered by the user The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm The unique device identifier is ideally suited e Foruse as serial numbers e For use as security keys to increase the code security in the program memory while using and combining this unique ID with software cryptographic primitives and protocols before programming the internal memory e To activate secure boot processes Table 14 Unique ID registers 96 bits madres iet Unique ID bits 7 6 5 4 3 2 1 0 0x4926 X co ordinate on U ID 7 0
119. ow profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 z 0 0630 A1 0 050 0 150 0 0020 gt 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 e E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 2 5 500 E 0 2165 e 0 500 S 0 0197 E 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 S 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc s 0 080 5 0 0031 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD15962 Rev 14 1171142 Package information STM8L151x4 6 STM8L152x4 6 Figure 44 LQFP48 48 pin 7 x 7 mm low profile quad flat package recommended footprint r JN 1 mmm LO A o y o Y ai14911d 1 Dimensions are expressed in millimeters 2 118 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 45 LQFP48 marking example package top view Product a identification S T M L 1 5 1 Standard ST logo Revision code Pin 1
120. ow watchdog mer 23 3 15 2 Independent watchdog mer 23 2 142 DocID15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Contents 2 A AN 23 3 17 Communication interfaces 24 A A ae oe Se Oe a eee 24 3 152 PO gacewetin decadideiauceaeed galled CR oe creed aw dean 24 KOEHLER 24 3 18 Infrared IR interface 24 3 19 Development support 25 Pinout and pin description 0c eee eee eee 26 4 1 System configuration options 37 Memory and register map 2222 eee eee 38 5 1 Memory mapping a a xac sa AGA par SUN EE E EES 38 5 2 Register map apan ka m RREESNGOR Para A RACE RERO 39 Interrupt vector mapping een iiie 57 Option DV GS iuc cic iia Mec A ca A ub dca da e dae de RC dr 59 Unique ID siii cai e EC ER E E 62 Electrical parameters leeren 63 9 1 Parameter conditions kaaa a ARA aka Kev E Eee RE READS RE RE 63 9 1 1 Minimum and maximum values 63 9 1 2 Typical values eee 63 9 1 3 Typical CUIVES cinto DEe ewm eR P Re e mx VOR EORR 63 9 1 4 Loading Capacitor sss eta ek ENGR EBA RR A NN V EE EE 63 9 1 5 Pin input voltage III 64 9 2 Absolute maximum ratings 2 0 wawa hk REG RR cR Rr RR ERES 64 9 3 Operating conditions s s s eae RR RR RR RR a is 66 9 3 1 General operating conditions 66 9 3 2 Embedded reset and power control block characteristics 67 9 3 3 Supply current characteristics 68 9 3 4 Clock and timing ch
121. parameters Current consumption of on chip peripherals Table 27 Peripheral current consumption Symbol Parameter p Unit d Vpp 3 0 V IDD TIM1 TIM1 supply current 13 IDD TIM2 TIM2 supply current N 8 IDD TIM3 TIM3 supply current N 8 IDD TIMa TIM4 timer supply current 1 3 IDD USART1 USART1 supply current 2 6 yA MHz IDD sP11 SPI1 supply current 2 3 IDD I201 DCH supply current 2 5 IDD DMA1 DMA1 supply current 3 Ipp wwba WWDG supply current 2 IDD ALL Peripherals ON 44 HA MHz IDD ADC1 ADC1 supply current 1500 uA IDD DAC DAC supply current 370 uA Ipp coMP Comparator 1 supply current 0 160 Slow mode 2 lpp coMP2 Comparator 2 supply current Fast mode 5 Power voltage detector and brownout Reset unit supply IDD PVD BOR NU 2 6 curren uA IDD BOR Brownout Reset unit supply current 7 2 4 including LSI supply 0 45 current IDD IDWDG Independent watchdog supply current excluding LSI 0 05 supply current ap o D Ly Data based on a differential Ipp measurement between all peripherals OFF and a timer counter running at 16 MHz The CPU is in Wait mode in both cases No IC OC programmed no I O pins toggling Not tested in production Data based on a differential Ipp measurement between the on chip peripheral in reset configuration and not clocked and the on chip peripheral when clocked and not kept under reset The CPU is in
122. ply current in Active halt mode Condition Typ LSE 1 15 Appi bes LsE 320 1 05 LSE 1 30 Kee LSE 32 9 1 20 LSE 1 45 Keck LsE 329 1 35 Unit pA 1 No floating I O unless otherwise specified 2 Based on measurements on bench with 32 768 kHz external crystal oscillator 3 RTC clock is LSE divided by 32 In the following table data is based on characterization results unless otherwise specified Table 26 Total current consumption and timing in Halt mode at Vpp 1 65 to 3 6 V Symbol Parameter Condition Typ Max Unit Ta 40 C to 25 C 350 14002 TA 255 C 580 2000 Supply current in Halt mode nA IpD Halt Ultra low power ULP bit 1 in TA 85 C 1160 28002 the PWR_CSR2 register Ta 105 2560 67002 Ta 125 C 4 4 130 uA Supply current during wakeup IDD WUHalt time from Halt mode using 2 4 mA HSI Wakeup time from Halt to Run 3 4 S Wu_HSI Halt mode using HSI id P po Wakeup time from Halt mode 3 4 Wu_Lsi Halt to Run mode using LSI lai He Tested in production EEN ieee ULP 0 or ULP 1 and FWU 1 in the PWR_CSR2 register Wakeup time until start of interrupt vector fetch Ta 40 to 125 C no floating I O unless otherwise specified The first word of interrupt routine is fetched 4 CPU cycles after twy 80 142 DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Electrical
123. port updated the Bootloader Table Medium density STM8L 15x pin description added LQFP32 to second column same pinout as UFQFPN32 Timer X trigger replaced by Timer X external trigger added note at the end of this table concerning the slope control of all GPIO pins Table Interrupt mapping merged footnotes 1 and 2 updated some of the source blocks and descriptions Section Option bytes replaced PM0051 by PM0054 and UM0320 by UM0470 Table Option byte description replaced the factory default setting OxAA for OPTO NRST pin updated text above the Figure updated Figure Recommended NRST pin configuration Table TS characteristics removed typ and max values for the parameter Ts temp added min value for same Table Comparator 1 characteristics added typ value for Comparator offset error added footnote 7 Table Comparator 2 characteristics updated tstart t slow ldfast Vottset Icomp2 added footnotes 7 and 3 Table DAC characteristics updated max value for DAC_OUT voltage DACOUT buffer ON Section 12 bit ADC1 characteristics updated Replaced Figure UFQFPN48 7 x 7 mm 0 5 mm pitch package outline and Figure UFQFPN48 7 x 7mm recommended footprint dimensions in mm Figure Medium density STM8L 15x ordering information scheme removed TR Tape Reel 06 Sep 2011 7 2 DoclD15962 Rev 14 139 142 Revision history STM8L151x4 6 STM8L152x4 6 140 142
124. pp 3 0 V 16 E MHz Vpp 3 0 V Ta 25 C EL 1 2 Vpp 3 0 V 0 C lt T lt 55 C 1 5 1 5 Accuracy of HSI Vop 3 0 V 10 C STA lt 70 C 2 x 96 ACCysi oscillator factory Vpp 3 0 V 10 C T4 lt 85 C 2 5 E calibrated Vpp 3 0 V 10 C lt TA lt 125 C 45 1 65 V Vpp lt 3 6 V o 40 C xTA 125 C S 3 a TRIM HSI user trimming Trimming code multiple of 16 a 0 4 0 7 96 step Trimming code multiple of 16 t 1 5 96 HSI oscillator setup 4 Juri time wakeup time SS 8 us HSI oscillator power 4 IDD HSI consumption 100 140 pA The trimming step differs depending on the trimming code It is usually negative on the codes which are multiples of 16 0x00 0x10 0x20 0x30 0xE0 Refer to the AN3101 STM8L15x internal RC oscillator calibration application note for more details 4 Guaranteed by design not tested in production Ly DoclD15962 Rev 14 85 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 Figure 19 Typical HSI frequency vs Vpp HSI frequency MHz a a 13 0 18 1 95 21 225 24 255 2 7 285 3 3 15 33 345 3 6 Voo V ai18218c Low speed internal RC oscillator LSI In the following table data is based on characterization results not tested in production Table 34 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency
125. quently the BOR in Halt mode The device remains under reset when Vpp is below a specified threshold Vpop ppr or Vgor without the need for any external reset circuit The device features an embedded programmable voltage detector PVD that monitors the Vpp Vppa power supply and compares it to the Vpyp threshold This PVD offers 7 different levels between 1 85 V and 3 05 V chosen by software with a step around 200 mV An interrupt can be generated when Vpp Vppa drops below the Vpyp threshold and or when Vpp VppA is higher than the Vpyp threshold The interrupt service routine can then generate a warning message and or put the MCU into a safe state The PVD is enabled by software Voltage regulator The medium density STM8L151x4 6 and STM8L152x4 6 embeds an internal voltage regulator for generating the 1 8 V power supply for the core and peripherals This regulator has two different modes e Main voltage regulator mode MVR for Run Wait for interrupt WEI and Wait for event WFE modes e Low power voltage regulator mode LPVR for Halt Active halt Low power run and Low power wait modes When entering Halt or Active halt modes the system automatically switches from the MVR to the LPVR in order to reduce current consumption DoclD15962 Rev 14 17 42 Functional overview STM8L151x4 6 STM8L152x4 6 3 4 18 142 Clock management The clock controller distributes the system clock SYSCLK coming from different oscillators t
126. r peripherals Wide choice of development tools All devices offer 12 bit ADC DAC two comparators Real time clock three 16 bit timers one 8 bit timer as well as standard communication interface such as SPI I2C and USART A 4x28 segment LCD is available on the medium density STM8L152xx line Table 2 Medium density STM8L151x4 6 and STM8L152x4 6 low power device features and peripheral counts and Section 3 Functional overview give an overview of the complete range of peripherals proposed in this family Figure 1 on page 14 shows the general block diagram of the device family d DoclD15962 Rev 14 9 142 Introduction STM8L151x4 6 STM8L152x4 6 10 142 The medium density STM8L15x microcontroller family is suitable for a wide range of applications Medical and hand held equipment Application control and user interface PC peripherals gaming GPS and sport equipment Alarm systems wired and wireless sensors DoclD15962 Rev 14 d STM8L151x4 6 STM8L152x4 6 Description 2 2 Description The medium density STM8L151x4 6 and STM8L152x4 6 devices are members of the STM8L ultra low power 8 bit family The medium density STM8L15x family operates from 1 8 V to 3 6 V down to 1 65 V at power down and is available in the 40 to 85 C and 40 to 125 C temperature ranges The medium density STM8L15x ultra low power family features the enhanced STM8 CPU core providing increased processing power up to 16 MIP
127. rer O Reserved Must be tied to Vpp MS32628V1 Figure 4 STM8L151K4 STM8L151K6 32 pin package pinout without LCD NRST PA1 gt PA2 f PA3F PA4 F2 DAD PA6 gt Vss1 ES Vpp4 o Ae o RON o must Cl e CH OOOOOOO Dna nn n 32 3130 29 28 27 28 25 24c 3 PD7 234 PD6 zciPD5 211PD4 2041 PB7 tci PB6 101 PB5 gt 171 PB4 9 10 11 12 13 14 15 16 PDO PD1f PD2f PD3 PBOt PB1 PB2t gt PB3 ai18251b Example given for the UFQFPN32 package The pinout is the same for the LQFP32 package Figure 5 STM8L151Gx UFQFPN28 package pinout o9 NN d o N ITO O O O O O pop OC 28 27 26 25 24 23 22 NRST PA1 E 1 21 PA2 2 2 20 PASE 3 19 PA4 E 4 18 DAD dE Vssi Vssa VREF E2 6 Vppi VppA Vggr 8 9 10 11 12 13 14 5808588 51 e ec Co O N DO DO a m D 00000 O 0 ai18250b DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Pinout and pin description 2 Figure 6 STM8L151G4 STM8L151G6 WLCSP28 package pinout 4 3 2 1 gt UJ O el PB4 m PBO nm PB6 O ai17084b Figure 7 STM8L152C4 STM8L152C6 48 pin pinout with LCD Nononorna Aro WWOOOOODO 7 add aLa ASAA DOODOADANDAA 48 47 46 45 44 43 42 41 40 39 38 37 PAO Cie 36 0PD7 NRST PA 1 Oe ssHPD6 PA2 03 34pPD5 PA3 04 330PD4 PA4 05 320PFO PA5 Us 310PB7 PA6 07 300 PB6 PA7 8 9HPB5 Vssi VssaVrer Ca
128. rt Development tools Development tools for the STM8 microcontrollers include e The STice emulation system offering tracing and code profiling e The STVD high level language debugger including C compiler assembler and integrated development environment e The STVP Flash programming software The STMB8 also comes with starter kits evaluation boards and low cost in circuit debugging programming tools Single wire data interface SWIM and debug module The debug module with its single wire data interface SWIM permits non intrusive real time in circuit debugging and fast memory programming The single wire interface is used for direct access to the debugging module and memory programming The interface can be activated in all device operation modes The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals CPU operation can also be monitored in real time by means of shadow registers Bootloader A bootloader is available to reprogram the Flash memory using the USART 1 interface The reference document for the bootloader is UM0560 STM8 bootloader user manual DoclD15962 Rev 14 25 142 Pinout and pin description STM8L151x4 6 STM8L152x4 6 4 26 142 Pinout and pin description Figure 3 STM8L151C4 STM8L151C6 48 pin pinout without LCD PAO Y NRST PA1 D PA2 Y PA3 Y PA4 O PA5 O PAG Y PA7 Y Vss1 VssaVrer D po1 H Vppa O V
129. s low register 0x00 channel 1 Ly DoclD15962 Rev 14 41 142 Memory and register map STM8L151x4 6 STM8L152x4 6 Table 9 General hardware register map continued Reset Address Block Register label Register name status 0x00 5084 Reserved area 1 byte 0x00 5085 DMA1 C1MOARH DMA1 memory O address high register 0x00 channel 1 0x00 5086 DMA1 C1MOARL DMA1 memory 0 address low register 0x00 channel 1 0x00 5087 0x00 5088 Reserved area 2 bytes 0x00 5089 DMA1 C2CR DMA1 channel 2 configuration register 0x00 0x00 508A DMA1 C2SPR DMA1 channel 2 status amp priority register 0x00 0x00 508B DMA1 C2NDTR DMA1 number of data to transfer register 0x00 channel 2 0x00 508C DMA1 C2PARH DMA1 peripheral address high register 0x52 channel 2 0x00 508D DMA1 C2PARL DMA1 peripheral address low register 0x00 channel 2 0x00 508E Reserved area 1 byte 0x00 508F DMA1 C2M0ARH DMA1 memory O address high register 0x00 channel 2 DMA1 0x00 5090 DMA1 C2MOARL DMA1 memory O address low register 0x00 channel 2 0x00 5091 0x00 5092 Reserved area 2 bytes 0x00 5093 DMA1_C3CR DMA1 channel 3 configuration register 0x00 0x00 5094 DMA1_C3SPR DMA1 channel 3 status amp priority register 0x00 0x00 5095 DMA1 C3NDTR DMA1 number of data to transfer register 0x00 channel 3 DMA1_C3PARH_
130. start Start 47 J tsu STA tw STO STA SDA i x i i Start Ge VA X J e n t SDA tr SDA itsu SDA th SDA ia Stop amp h NAN TON GA MO th STA tw SCLH tw SCLL tr SCL ti SCL tsu STO MS32620V2 1 Measurement points are done at CMOS levels 0 3 x Vpp and 0 7 x Vpp DoclD15962 Rev 14 101 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 9 3 9 102 142 LCD controller STM8L152xx only In the following table data is guaranteed by design Not tested in production Table 45 LCD characteristics Symbol Parameter Min Typ Max Unit Vico LCD external voltage S 3 6 V Vicpo LCD internal reference voltage 0 2 6 Vuen LCD internal reference voltage 1 2 7 V Vuen LCD internal reference voltage 2 x 2 8 V Vi cpa3 LCD internal reference voltage 3 2 9 V Vi cp4 LCD internal reference voltage 4 a 3 0 V Vi cps LCD internal reference voltage 5 3 1 V Vi cpe LCD internal reference voltage 6 3 2 V Vi cp7 LCD internal reference voltage 7 3 3 V Cext Vicp external capacitance 0 1 2 uF Supply current at Vpp 1 8 V 3 uA Supply current at Vpp 3V 3 PA Run 2 High value resistive network low drive S 6 6 z MQ RLN 3 Low value resistive network high drive E 360 z kQ V33 Segment Common higher level voltage Vicpx V Voz Segment Common 2 3 level voltage 2 3VLCDx V Vio Segment Common 1 2 level voltage g 1 2Vi cpx e V
131. t COMP1_INP Comparator 1 positive input 34 142 DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Pinout and pin description Table 5 Medium density STM8L151x4 6 STM8L152x4 6 pin description continued Pin numb r Input Output CO N So gt 2 3 zB 33 P E m g Pin name 2 E E E 3 sg Default alternate Oc Zia Flo cel gt gt 5 function S5 E2 Ez zog x Q a Ee 2 2 S 3 O O sS o N O I 2 Io a E 5 sis ralis s OO I a sl Timer 1 inverted PD7 TIM1_CH1N channel 1 LCD segment LCD SEG212 TT 21 ADC1 IN7 RTC 36 24 ADC1_IN7 RTC_ALARM I O 3 X X X HS X X Pont Di alarm Internal voltage VREFINT reference output COMP1_INP Comparator 1 positive input 14 PEOS LCD_SEG1 2 VO FT X X X HS X X Port EO LCD segment 1 Timer 1 inverted 15 een 1 0 n X X X HS X X PortE1 channel 2 LCD B segment 2 Timer 1 inverted PE2 TIM1 CH3N TT 16 wen secs Wiel X X X HS X X Port E2 channel 3 LCD segment 3 17 PES LCD_SEG4 O n X X X HS X X Port E3 LCD segment 4 18 PE4 LCD SEG5 Vol x x X HS x X PortE4 ILCD segment 5 LCD segment 6 PES LCD SEG6 T ADC1 IN23 19 ADC1_IN23 COMP2_INP I O 3 X X X HS X X Port E5 Comparator 2 positive COMP1 INP input Comparator 1 positive input PE6 LCD_SEG26 TT LCD se
132. tal current consumption The MCU is placed under the following conditions All I O pins in input mode with a static value at Vpp or Vss no load All peripherals are disabled except if explicitly mentioned In the following table data is based on characterization results unless otherwise specified Subject to general operating conditions for Vpp and Ta d DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Electrical parameters Table 20 Total current consumption in Run mode Para max Symbol meter Conditions Typ Unit 55 C 85 Cl 105 C 125 ec fcpu 125 kHz 0 39 0 47 0 49 0 52 0 55 fcpy 1MHz 0 48 0 56 0 58 0 61 0 65 HSI RC osc fcpu 4MHz 0 75 0 84 0 86 0 91 0 99 16 MHz e fcepu 8 MHz 1 10 1 20 1 25 1 81 1 40 All fopy 16 MHz 1 85 1 93 2 12 2 2918 2 36 8 peripherals OFF fopy 125 kHz 0 05 0 06 0 09 0 11 0 12 Supply code ent f 1 MH E banis exceed lake saang Ore z 0 18 0 19 0 20 0 22 0 23 ma mod rom RAM clock fcpeu 4MHz 0 55 0 62 0 64 071 0 77 Vopfrom fopuzfuse 2018 MH 1 65 Vto CPU z 0 99 1 20 1 21 1 22 1 24 SST fopy 16 MHz 1 90 2 22 223 2 248 2 288 LSI RC osc tana typ 38 KHz CPU fis 0 040 0 045 0 046 0 048 0 050 LSE external clock fopu fLse 0 035 0 040 0 048 9 0 050 0 062 32 768 kHz
133. th the norm IEC61967 2 which specifies the board and the loading of each pin DoclD15962 Rev 14 Ly STM8L151x4 6 STM8L152x4 6 Electrical parameters 2 Table 59 EMI data e Max vs Ken Monitored h Symbol Parameter Conditions Unit frequency band 16 MHz Vpp 3 6 V 0 1 MHz to 30 MHz 3 Ta 25 C 30 MHz to 130 MHz 9 dBuV SEMI Peak level LQFP32 conforming to 130 MHz to 1 GHz 4 IEC61967 2 SAE EMI Level 2 E 1 Not tested in production Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges a positive then a negative pulse separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin Two models can be simulated human body model and charge device model This test conforms to the JESD22 A114A A115A standard Table 60 ESD absolute maximum ratings Ra Maximum i Symbol Ratings Conditions value Unit Electrostatic discharge voltage VESD HBM human body model 2000 Ta 425 C V V Electrostatic discharge voltage 500 ESD CDM charge device model
134. tion environment and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 58 EMS data Symbol Parameter Conditions paagi Voltage limits to be applied on Vpp 3 3 V Ta 25 C Vresp any I O pin to induce a functional fepy 16 MHz 3B disturbance conforms to IEC 61000 Fast transient voltage burst limits Vpp 3 3 V Ta 2 V to be applied through 100 pF on i BB See Mic EE Using HSI s EFTB Vpp and Vss pins to induce a CPU Es functional disturbance conforms to IEC 61000 Using HSE 2B Electromagnetic interference EMI Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line wi
135. tion on any aspect of this device please contact your nearest ST sales office Figure 60 Medium density STM8L15x ordering information scheme Example STM8 L 151 C 4 U 6 TR Product class STM8 microcontroller Family type L Low power Sub family type 151 Ultra low power 152 Ultra low power with LCD Pin count C 48 pins K 32 pins G 28 pins Program memory size 4 16 Kbyte 6 32 Kbyte Package U UFQFPN T LQFP Y WLCSP Temperature range 3 40 C to 125 C 7 40 C to 105 C 6 40 C to 85 C Delivery TR Tape amp Reel 1 Foralist of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please contact the ST sales office nearest to you 2 136 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Revision history 12 Revision history Table 69 Document revision history Date Revision Changes 06 Aug 2009 1 Initial release Updated peripheral naming throughout document Added Figure STM8L151Cx 48 pin pinout without LCD Added capacitive sensing channels in Features Updated PA7 PCO and PC1 in Table Medium density 10 Sep 2009 2 STM8L 15x pin description Changed CLK and REMAP register names Changed description of WDGHALT Added typical power consumption values in Table 18 to Table 26 Corrected VIH max value Added WLCSP28 pa
136. trode which is protected from direct touch by a dielectric example glass plastic The capacitive variation introduced by a finger or any conductive object is measured using a proven implementation based on a surface charge transfer acquisition principle It consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold In medium density STM8L151x4 6 DoclD15962 Rev 14 21 142 Functional overview STM8L151x4 6 STM8L152x4 6 and STM8L152x4 6 devices the acquisition sequence is managed by software and it involves analog I O groups and the routing interface Reliable touch sensing solutions can be quickly and easily implemented using the free STM8 Touch Sensing Library 3 14 Timers Medium density STM8L151x4 6 and STM8L152x4 6devices contain one advanced control timer TIM1 two 16 bit general purpose timers TIM2 and TIM3 and one 8 bit basic timer TIM4 All the timers can be served by DMA1 Table 3 compares the features of the advanced control general purpose and basic timers Table 3 Timer feature comparison Counter Counter DMAI Capture compare Complementar Timer vesolutiod type Prescaler factor request estat bata ute y yp generation p Any integer Mu from 1 to 65536 ones a 16 bit up down TIM2 P Any power of 2 Yes 2 TIM3 from 1 to 1
137. troduction and Description Modified Table Legend abbreviation for table 5 and Table Medium density STM8L15x pin description for PAO PA1 PBO and PB4 and for reset states in the floating input column Modified Figure Low density STM8L151xx device block diagram Figure Low density STM8L15x clock tree diagram Figure Low power modes and Figure Low power real time clock Modified CLK_PCKENR2 and CLK_HSICALR reset values in Table General hardware register map Modified notes below Figure Memory map Modified PA CR1 reset value Modified reset values for Px_IDR registers Modified Table Voltage characteristics and Table Current characteristics Modified Vi in Table I O static characteristics Modified Table Total current consumption in Wait mode Modified Figure Typical application with I2C bus and timing diagram 1 Modified value in Figure Typical connection diagram using the ADC1 Modified Ry and R in Table LCD characteristics Added graphs in Section Electrical parameters Modified note 3 below Table Reference voltage characteristics Modified note 1 below Table TS characteristics Changed Vgsp cpyw value in Table ESD absolute maximum ratings Updated notes for UFQFPN32 and UFQFPN48 packages 11 Mar 2011 Modified note on true open drain I Os and I O level columns in Table Medium density STM8L 15x pin description Remapping option removed for USART1 TX USART1 RX and USART1_CK on PC2 P
138. tus register 1 0x10 0x00 7F99 DM CSR2 DM Debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF 0x00 7F9B to Reserved area 5 byte 0x00 7F9F 1 Accessible by debug module only 2 56 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Interrupt vector mapping 6 Interrupt vector mapping Table 11 Interrupt mapping Wakeup Wakeup Wakeup Wakeup IRQ Source Description from Halt from from Wait from Wait Vector No block p Active halt WFI WFE address mode 1 mode mode mode RESET Reset Yes Yes Yes Yes 0x00 8000 TRAP Software interrupt S 0x00 8004 0 Reserved 0x00 8008 FLASH end of programing 1 FLASH write attempted to Yes Yes 0x00 800C protected page interrupt DMA1 channels 0 1 half 2 DMA1 0 1 transaction transaction 3 Yes Yes 0x00 8010 complete interrupt DMA1 channels 2 3 half 3 DMA1 2 3 transaction transaction Yes Yes 0x00 8014 complete interrupt me EE Yes Yes Yes Yes 0x00 8018 wakeup EXTI E F External interrupt port E F 5 PVDO PVD interrupt Yes Yes Yes Yes 0x00 801C 6 EXTIB G External interrupt port B G Yes Yes Yes Yes 0x00 8020 7 EXTID H External interrupt port D H Yes Yes Yes Yes 0x00 8024 8 EXTIO External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes
139. ut alternate function characteristics SDA and SCL Table 44 DC characteristics Standard mode 2 1 Gr Fast mode GC Symbol Parameter Unit Min Max Min Max lwscii SCL clock low time 4 7 1 3 S us tw SCLH SCL clock high time 4 0 z 0 6 tsuspa SDA setup time 250 100 thispa SDA data hold time 0 0 900 t SDA SDA and SCL rise time 1000 300 ns t sCL t SPA SDA and SCL fall time 300 300 sc isa START condition hold time 4 0 0 6 Repeated START condition setu us tsu STA dm P 4 7 0 6 tsusto STOP condition setup time 4 0 0 6 us STOP to START condition time bus tw STO STA free 4 7 3 1 3 us Cb Capacitive load for each bus line 400 400 pF 1 fsyscik must be at least equal to 8 MHz to achieve max fast Ke speed 400 kHz 2 Data based on standard DC protocol requirement not tested in production Note For speeds around 200 kHz the achieved speed can have at 5 tolerance For other speed ranges the achieved speed can have at 2 tolerance The above variations depend on the accuracy of the external components used 100 142 DoclD15962 Rev 14 2 STM8L151x4 6 STM8L152x4 6 Electrical parameters 2 Figure 37 Typical application with DC bus and timing diagram VDD VDD 4 7kQ 4 7kO z 1000 a ken SDA 12C BUS 1000 SCL Wi STM8L E Repeated
140. wer comparators The medium density STM8L151x4 6 and STM8L152x4 6 embed two comparators COMP1 and COMP2 sharing the same current bias and voltage reference The voltage reference can be internal or external coming from an I O e One comparator with fixed threshold COMP1 e One comparator rail to rail with fast or slow mode COMP2 The threshold can be one of the following DAC output External I O Internal reference voltage or internal reference voltage sub multiple 1 4 1 2 3 4 The two comparators can be used together to offer a window function They can wake up from Halt mode System configuration controller and routing interface The system configuration controller provides the capability to remap some alternate functions on different I O ports TIM4 and ADC1 DMA channels can also be remapped The highly flexible routing interface allows application software to control the routing of different I Os to the TIM1 timer input captures It also controls the routing of internal analog signals to ADC1 COMP1 COMP2 DAC and the internal reference voltage Vpepinr It also provides a set of registers for efficiently managing the charge transfer acquisition sequence Section 3 13 Touch sensing Touch sensing Medium density STM8L151x4 6 and STM8L152x4 6 devices provide a simple solution for adding capacitive sensing functionality to any application Capacitive sensing technology is able to detect finger presence near an elec
141. x00 543D RI ASCR1 Analog switch register 1 0x00 0x00 543E RI ASCR2 Analog switch register 2 0x00 0x00 543F RI RCR Resistor control register 1 0x00 0x00 5440 COMP CSR1 Comparator control and status register 1 0x00 0x00 5441 COMP CSR2 Comparator control and status register 2 0x00 0x00 5442 COMP COMP_CSR3 Comparator control and status register 3 0x00 0x00 5443 COMP_CSR4 Comparator control and status register 4 0x00 0x00 5444 COMP CSR5 Comparator control and status register 5 0x00 1 These registers are not impacted by a system reset They are reset at power on d 54 142 DoclD15962 Rev 14 STM8L151x4 6 STM8L152x4 6 Memory and register map Table 10 CPU SWIM debug module interrupt controller registers Address Block Register Label Register Name a 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 pet E anu Reserved area 85 byte 0x00 7F60 CFG_GCR Global configuration register 0x00 0x00 7F7
142. xed voltage using the output mode of the I O for example or an external pull up or pull down resistor DoclD15962 Rev 14 89 142 Electrical parameters STM8L151x4 6 STM8L152x4 6 Table 38 I O static characteristics Symbol Vi Parameter Input low level voltage Conditions Input voltage on true open drain pins PCO and PC1 Min Vss 0 3 Typ Max 0 3 x Vop Input voltage on five volt tolerant FT pins PA7 and PEO Vss 0 3 0 3 x Vop Input voltage on 3 6 V tolerant TT pins Vgg 0 3 0 3 x Vop Input voltage on any other pin Vgg 0 3 0 3 x Vpp Unit ViH Input high level voltage 2 Input voltage on true open drain pins PCO and PC1 with Vpp lt 2V Input voltage on true open drain pins PCO and PC1 with Vpp 52v 0 70 x Vop 5 2 5 5 Input voltage on five volt tolerant FT pins PA7 and PEO with Vop lt 2V Input voltage on five volt tolerant FT pins PA7 and PEO Input voltage on 3 6 V tolerant TT pins 0 70 x Vop 5 2 5 5 Input voltage on any other pin 0 70 x Vop Vhys Schmitt trigger voltage hysteresis 9 Os 200 True open drain I Os 200 mV likg Input leakage current 4 VssVinSVpp High sink I Os VsssVinsVpp True open drain I Os VsssVinsVpp PAO with high sink LED driver capability nA Rpy Weak pull up equivalent resistor 2 6 Vin Vss 3
143. z 0 760 1 01 1 05 7 o LSI fopu Ia 0 035 0 044 0 046 0 049 0 054 LSE external clock fopu fLSE 0 032 0 036 0 038 0 044 0 051 32 768 kHz Ly DoclD15962 Rev 14 71 42 Electrical parameters STM8L151x4 6 STM8L152x4 6 Table 21 Total current consumption in Wait mode continued Max SES 1 Symbol Parameter Conditions Typ Se 85 105 C1125 cl Unit o 2 3 4 fcpu 125 kHz 0 38 0 48 0 49 0 50 0 56 fcpu 1 MHz 0 41 0 49 0 51 0 53 0 59 HSI fcpu 4 MHz 0 50 0 57 0 58 0 62 0 66 fcpy 8 MHz 0 60 0 66 0 68 0 72 0 74 f 16 MH E CPU not CPU z 0 79 0 84 0 86 0 87 0 90 clocked fopy 125 kHz 0 06 0 08 0 09 0 10 0 12 Supply all peripherals 6 HSE currentin OFF fcpu 1 MHz 0 10 0 17 0 18 0 19 0 22 IDD wait Wait code executed a mA i Flash clock fcpu 4 MHz 0 24 0 36 0 39 0 41 0 44 mode Pap on fcpu HSE Vpp from fcey 8 MHz 0 50 0 58 0 61 0 62 0 64 1 65 V to 3 6 V fcpu 16 MHz 1 00 1 08 1 14 1 16 1 18 LSI fopu tis 0 055 0 058 0 065 0 073 0 080 LSE a fopu Lse 0 051 0 056 0 060 0 065 0 073 32 768 kHz 1 All peripherals OFF Vpp from 1 65 V to 3 6 V HSI internal RC osc fepy fsysci K 2 For temperature range 6 3 For temperature range 7 4 For temperature range 3 5 Flash is configured in Ippo mode

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