RX62T Group On-chip Flash Memory Reprogramming in Single
Contents
1. 929077 received from master wrdata_buffer with FFh SCI Trs1byte E _ eae ACCEPTABLE command Receive 256 bytes of data from the master write data SCI_Revnbyte E R_FlashWrite E seeeeee Write 256 bytes of data If an error occurs when writing the 256 sroeeen bytes of data perform error handling error No 08 Indicate Eror LED Determine whether writing of the received write size data quantity is finished Programming finished Transmit ACCEPTABLE command 1 byte SCI_Trstbyte E Disable SCIO transmit and receive operation Disable RXI0 ERIO and TXIO interrupts Indicate_Ending LED neocon Normal end processing Figure 16 Flowchart Flash_Update 3 Slave RO1AN0640EJ0102 Rev 1 02 Page 31 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 Indicate_Ending_LED Function a Functional Overview When programing erasing completes successfully the Indicate_Ending LED function indicates a normal end using LEDO to LED3 The function illuminates LEDO to LED3 one at a time in sequence b Arguments None c Return Values None d Flowchart Indicate_Ending LED LEDO on LED1 to LEDS off Wait WAIT_LED LED1 on LEDO LED2 and LEDS off Wait processing using for loop loop count WAIT_LED Wait processing using for l2. RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave SCIO Serial Status Register SCIO SSR Number of Bits 8 Address 0008 8244h Serial communication interface mode SMIF bit in SCIO SCMR 0 Setting Bit Symbol Value Bit Name Function R W b2 TEND Transmit end flag 0 Character transmission in progress R 1 Character transmission finished b4 FER Framing error flag 0 No framing error occurred R W 1 A framing error occurred ae b5 ORER Overrun error flag 0 No overrun error occurred R W 1 An overrun error occurred Notes 1 The FER and ORER bits are handled as read only in this application note Writing to these bits to clear the flags to 0 is not performed 2 Only writing 0 to clear the flag is allowed SCIO Transmit Data Register SCIO TDR Number of Bits 8 Address 0008 8243h Setting Bit Symbol Value Bit Name Function R W b7to Stores transmit data R W bO Note The transmitted data is stored in this field SCIO Receive Data Register SCIO RDR Number of Bits 8 Address 0008 8245h Setting Bit Symbol Value Bit Name _Function R W b7 to Stores receive data R bO 5 Interrupt Control Unit ICU Interrupt Priority Register 80 IPR80 Number of Bits 8 Address 0008 7380h Setting Bit Symbol Value Bit Name Function R W b3 to IPR 3 0 0000 SCIO Interrupt priority level 0000 Level 0 interrupt disabled R W bO setting
3. completion and when an error occurs r_flash_api_rx600 c The Simple Flash API program r_flash_api_rx600 h External reference include file for the Simple Flash API program r_flash_api_rx600_private h External reference include file for the Simple Flash API program r_flash_api_rx600_config h Simple Flash API parameter settings include header file mcu_info h Simple Flash API parameter settings include header file Notes 1 This file is generated automatically by High performance Embedded Workshop In the sample program it has been edited to restore a line in the PowerON_Reset_PC function calling the HardwareSetup function which was originally commented out In the edited version the HardwareSetup function in the main c file is called from the PowerON_Reset_PC function 2 See the Simple Flash API application note for details RO1AN0640EJ0102 Rev 1 02 Page 16 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 2 Function Structure Table 12 lists the functions for the slave device and figure 10 shows the hierarchy of these functions Table 12 Slave Device Functions Function File Name Description PowerON_Reset_PC resetprg c Initial settings function HardwareSetup main c MCU initial settings function main main c Main function Flash_Update main c Data send receive control and error handling cont
4. 02 Page 10 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 4 5 Handshaking Control The slave uses handshaking with the master for communications control The handshaking control used here consists of the slave first receiving a serial communication from the master then performing the processing for the received data and finally returning an ACCEPTABLE command 55h when it is ready to receive the next serial communication The master only starts the next serial communication after it has received an ACCEPTABLE command from the slave 4 4 6 Overrun Error In this application note if an overrun error occurs during slave asynchronous serial communication reception the SCIO SSR ORER bit is set to 1 the slave will perform error handling 4 4 7 Framing Error In this application note if a framing error occurs during slave asynchronous serial communication reception the SCIO SSR FER bit is set to 1 the slave will perform error handling RO1ANO640EJ0102 Rev 1 02 Page 11 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 5 User MAT Write and Erase See the RX600 Simple Flash API application note listed in section 7 Reference Documents for details on the RX600 Simple Flash API used for write and erase in this application note 4 5 1 User MAT Erase Processin
5. 1 00 Sep 27 2011 First edition issued 1 01 Mar 27 2012 4 Table 1 Master Verified Operating Environment evaluation environment updated 11 4 5 3 Changes to the Simple Flash API Changes to the RX600 Simple Flash API are now reflected in this section 4 5 4 Notes on Using Interrupts Added 13 Table 10 Master Section Settings Setting values modified 14 Table 11 Master File Structure RX600 Simple Flash API description modified 15 Table 12 Slave Device Functions Changes to the RX600 Simple Flash API are now reflected in this section 37 Change to the version number of the RX600 Simple Flash API in section 7 Reference Documents and removal of the R01AN0639EJ version number HEW workspace generated with the environment from table 1 1 02 Mar 04 2015 4 Table 1 Optimizing linkage editor added 4 Table 1 Note added 28 Figure 13 Note added 38 6 1 Note added 38 6 3 rom Option added A 1 General Precautions in the Handling of MPU MCU Products The following usage notes are applicable to all MPU MCU products from Renesas For detailed usage notes on the products covered by this document refer to the relevant sections of the document as well as any technical updates that have been issued for the products 1 Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual The input pins of CMOS products are generally in the high impedance state In operation with a
6. B1 1 P71 I O select bit 1 Output port R W b2 B2 1 P72 I O select bit 1 Output port R W b3 B3 1 P73 I O select bit 1 Output port R W Port 3 Data Direction Register P3 DDR Number of Bits 8 Address 0008 C003h Setting Bit Symbol Value Bit Name Function R W b3 B3 1 P33 I O select bit 1 Output port R W Port B Input Buffer Control Register PB ICR Number of Bits 8 Address 0008 C06Bh Setting Bit Symbol Value Bit Name Function R W b1 B1 1 PB1 input buffer control bit 1 PB1 input buffer enabled R W R01AN0640EJ0102 Rev 1 02 Page 21 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 3 Low Power Consumption Module Stop Control Register B MSTPCRB Number of Bits 32 Address 0008 0014h Setting Bit Symbol Value Bit Name Function R W b31 MSTPB31 0 Serial communication 0 SCIO module stop state canceled R W interface 0 module stop setting bit 4 Serial Communications Interface 0 SCIO SCIO Serial Control Register SCIO SCR Number of Bits 8 Address 0008 8242h Serial communication interface mode SMIF bit in SCIO SCMR 0 Setting Bit Symbol Value Bit Name Function R W b1 b0 CKE 1 0 00 Clock enable bits For asynchronous communication R W 00 Internal baud rate generator The SCKO pin is set to be an I O port b2 TEIE 0 Transmit end interrupt 0 TEIO interrupt disabled R W enable bit b4 RE 0 Receive enable bit 0 Serial reception disa
7. LEDO to LEDS off Wait processing using for loop loop count WAIT_LED Wait WAIT_LED Figure 18 Flowchart Indicate_Error_LED Slave RO1AN0640EJ0102 Rev 1 02 Page 33 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 7 SCI_Revlbyte Function a Functional Overview The SCI_Rcvlbyte function performs the reception control for receiving byte of data over SCIO asynchronous serial communication b Arguments None c Return Values Table 17 lists the return values used by this function Table 17 Return Values SCI_Revibyte Function Type Description unsigned char The one byte of receive data from the SCIO asynchronous serial communication d Flowchart SCl_Revibyte Error handling when an overrun error or framing error occurs error No 01 Overrun error or framing error Indicate Eror LED Reception of 1 byte done gt semm Reception of 1 byte finished Clear RXIO interrupt status flag to 0 Read receive data from RDR gt gt Read 1 byte of receive data from RDR of SCIO Return receive data s Send 1 byte of receive data as return value End Figure 19 Flowchart SCl_Rcev1byte Slave RO1AN0640EJ0102 Rev 1 02 Page 34 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface
8. Reprogramming in Single Chip Mode via an UART Interface Slave 4 Flash_Update Function a Functional Overview The Flash_Update function controls reception of communication commands using asynchronous serial communications with the master controls reception of erase block numbers controls reception of the write data size controls reception of the write data controls transmission of the ACCEPTABLE command calls the R_FlashErase function when the user MAT is erased calls the R_FlashWrite function when the user MAT is written calls the Indicate_Ending_ LED function when a user MAT write or erase completes normally and calls the Indicate_Error_LED function when an operation terminates with an error b Arguments None c Return Values None d Flowchart Flash_Update SCI_Trs1byte sees Transmit ACCEPTABLE command 1 byte Receive 1 byte of data from master E ACi Movibyie Goo S ERASE command ERASE command received Noo o o Error handling when the received data is not an ERASE command error No 03 Yes Indicate Eror LED SCI_Trs1byte Pf eee Transmit ACCEPTABLE command 1 byte Receive 1 byte of data from master E se Roun ee erasure block number Check whether erasure block number is NG within range EB02 to EB21 and if out of range perform error handling error OK No 04 Indicate Eror LED Initialize fcu_info Initialize fcu_info RAM variable
9. a ACCEPTABLE command maaan Issue ACCEPTABLE command 1 byte Pe command received Figure 4 Communication Sequence 2 RO1ANO640EJ0102 Rev 1 02 Page 7 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave WRITE command Transmit WRITE command Receive 1 byte of data 1 byte WRITE command received Error processing ACCEPTABLE command Amam Issue ACCEPTABLE command 1 byte ACCEPTABLE command received it Write data size 4 bytes 4 bytes of data Transmit write data size received Write data size check Error processing ACCEPTABLE command m Issue ACCEPTABLE command ACCEPTABLE 1 byte command received Write data Transmit write data 256 bytes of data 256 bytes received Write 256 bytes of received write data to user MAT Write processing check Error processing Write data transmit finished Write data receive finished Figure 5 Communication Sequence 3 RO1AN0640EJ0102 Rev 1 02 Page 8 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave ACCEPTABLE command Issue ACCEPTABLE command es ommand received Normal
10. according to received erasure block number Figure 14 Flowchart Flash_Update 1 Slave R01AN0640EJ0102 Rev 1 02 Page 29 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave I Rrena i OK Erase the erasure block specified by the erasure block data If an error occurs when erasing the erasure block perform error handling error No 05 Indicate_Error_LED sorties Scr Rovioye I WRITE command received No Yes Transmit ACCEPTABLE command 1 byte Receive 1 byte of data from the master WRITE command Error handling when the received data is not an WRITE command error No 06 Indicate_Error_LED __sortrsteve_T TL Sc Roye T EC OK Transmit ACCEPTABLE command 1 byte Receive 4 bytes of data from the master write size data Error handling when the received write data size value is 0 or larger than the size of the specified erase block error No 07 ndate Eror LED Initialize fcu_info Initialize fcu_info RAM variable according to the received write size data Figure 15 Flowchart Flash_Update 2 Slave R01AN0640EJ0102 Rev 1 02 Mar 04 2015 Page 30 of 40 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave Initialize storage buffer for write data Initialize wrdata_buffer
11. bits Interrupt Request Enable Register 1A IER1A Number of Bits 8 Address 0008 721Ah Setting Bit Symbol Value Bit Name Function R W b7 IEN7 0 RXIO Interrupt enable bit 7 0 RXI0 interrupt disabled R W Interrupt Request Enable Register 1B IER1B Number of Bits 8 Address 0008 721Bh Setting Bit Symbol Value Bit Name Function R W bO IENO 0 TXIO Interrupt enable bit 0 0 TXIO interrupt disabled R W RO1AN0640EJ0102 Rev 1 02 Page 24 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave Interrupt Request Register 215 IR215 Number of Bits 8 Address 0008 70D7h Setting Bit Symbol Value Bit Name Function R W bO IR 0 RXIO Interrupt status flag 0 No RXIO interrupt request R W 1 RXIO interrupt request Note Only 0 may be written to this bit to clear the flag Writing 1 is prohibited Interrupt Request Register 216 IR216 Number of Bits 8 Address 0008 70D8h Setting Bit Symbol Value Bit Name Function R W bO IR 0 TXIO Interrupt status flag 0 No TXIO interrupt request R W 1 TXIO interrupt request Note Only 0 may be written to this bit to clear the flag Writing 1 is prohibited RO1AN0640EJ0102 Rev 1 02 Page 25 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 7 Function Specifications The specifications of the slave device functions are as follows 1 PowerON_R
12. command Error No 03 In the ERASE command wait state the command Off Off On On received from the master was not an ERASE command Error No 04 The erasure block data received from the master Off On Off Off specifies a block other than EB02 to EB21 Error No 05 An error occurred in the erase processing forthe erase Off On Off On block Error No 06 In the WRITE command wait state the command Off On On Off received from the master was not an WRITE command Error No 07 The write data size received from the master was 0 or Off On On On a value greater than the block size of the specified erase block Error No 08 An error occurred in the data write processing On Off Off Off RO1ANO640EJ0102 Rev 1 02 Page 14 of 40 Mar 04 2015 RENESAS RX62T Group 49 Section Settings On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave Table 10 shows the section settings for the slave device Table 10 Section Settings of Slave Device FIXEDVECT FFFF FFDOh RO1AN0640EJ0102 Rev 1 02 Mar 04 2015 Section Start Address Description RPFRAM 0000 0000h Area mapped in RAM as the PFRAM section by the ROM support option B_1 0000 1000h Uninitialized data area ALIGN 1 R1 Area mapped in RAM as the D 1 section by the ROM support option B2 Uninitialized data area ALIGN 2 R_2 Area mapped in RAM as the D 2 section by the ROM s
13. end indication or error end indication Figure 1 Specifications R01AN0640EJ0102 Rev 1 02 Page 2 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave Figure 2 shows a hardware configuration diagram of the slave device as used in this application note Asynchronous serial communication Slave Master LEDO LED1 LED2 LED3 Endian switch ee ae switch Reset switch 12 5 MHz crystal resonator TxD0 i A RxDO io 5 0 V RX62T RX62T Note The TxDO and RxDO pins of the slave are pulled up externally Figure 2 Hardware Configuration Diagram of Slave Device RO1AN0640EJ0102 Rev 1 02 Page 3 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 2 Operation Confirmation Environment Table 1 lists the environment required for confirming slave operation Table 1 Slave Operation Confirmation Environment Item Description Device RX62T Group R5F562TAADFP ROM 256 KB RAM 16 KB Board Renesas Starter Kit Under development as of February 21 2012 Power supply voltage 5 0 V Input clock 12 5 MHz ICLK 100 MHz PCLK 50 MHz Operating temperature High performance Room temperature Version 4 09 00 007 Embedded Workshop Toolchain RX Standard Toolchain V 1 2 0 0 Debugger Emulator E1 Emulator Debugger co
14. end processing LU 1 byte Normal end processing Figure 6 Communication Sequence 4 4 4 2 Communication Command Specifications Table 6 lists the specifications of the communication commands sent between the master and slave Table 6 Communication Command Specifications Communication Command Value Description Direction FSTART 10h Command to start programming erasing of the user MAT Master gt slave of the slave ERASE 11h Command to start erasing of the user MAT of the slave Master slave WRITE 12h Command to start programming of the user MAT of the Master gt slave slave ACCEPTABLE 55h Status command used by the slave to inform the master Slave gt master that it is able to receive data from the master R01AN0640EJ0102 Rev 1 02 Page 9 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 4 3 Erasure Block Number After receiving an ERASE command from the master the slave receives byte of erasure block number 1 byte of data defined by a symbolic constant Figure 7 shows the specifications of the erasure block number See section 4 5 1 User MAT Erase Processing for details on the erase block numbers Erasure block number unsigned char type b7 b6 b5 b4 b3 b2 b1 bO In this application note a value corresponding to EB08 is used as the erase block number to write or erase the slave erase block EB08
15. to the erased block EBO8 starting at the start address of that block Note that this application note s specifications call for the program code to be allocated to EB00 and EBO1 and for it not to be erased or overwritten Therefore it is an error for the master to specify EBO0 or EBO1 as an erase block number e Handshaking is used to control communication between the master and slave After processing the data received from the master the slave returns an ACCEPTABLE command 55h to the master The master starts the next serial transfer after receiving the ACCEPTABLE command from the slave e When the slave completes the erase and write processing of the user MAT normally it reports this normal completion using the 4 LEDs connected to the I O ports It also reports the error state if an error occurs during communication with the master or during the write erase processing Figure 1 shows the specifications of the system used in this application note E ame oa Master Asynchronous serial communication After EB08 is Write data On chip RAM erased the received 8 KB ACCEPTABLE write data is written command EB08 to EB08 in 256 byte 55h Write data ata beginning 8 KB rom the start address Programming erasing of slave EB08 starts when the IRQ Unused area switch is pressed 8 KB IRQ switch I O ports LEDx4 I O ports Normal end indication or error end indication Normal
16. 2PENESAS APPLICATION NOTE RX62T Group On chip Flash Memory Reprogramming in Single chip Mode hi aia meh via an UART Interface Slave Mar 04 2015 Introduction This application note describes the write and erase processing for the flash memory user MAT using the erase block number write data size and write data transferred by asynchronous serial communication from an RX62T Group microcontroller R01 AN0639EJ as described in On chip Flash Memory Reprogramming in Single chip Mode via an UART Interface Master See the RX62T Group document On chip Flash Memory Reprogramming in Single chip Mode via an UART Interface Master ROLAN0639EJ for details on the processing used to transfer the erase block number write data size and write data using asynchronous serial communication Note that the erase and write processing for the internal flash memory used here is taken from the RX600 Series Simple Flash API for RX600 application note Rev 2 20 RO1AN0544EU0220 Target Device RX62T Group This program can be used with other RX Family MCUs that have the same I O registers peripheral device control registers as the RX62T Group Check the latest version of the manual for any additions and modifications to functions Careful evaluation is recommended before using this application note Contents Te SPOCIICATIONS cesia eaaa a a eat aaa aaa iaa aaa et aaa lt eine 2 2 Operation Confirmation ENvirOnMent cccc
17. Note A value corresponding to EB02 to EB21 must be specified as the erase block number If a value other than an erase block number is specified the slave will recognize an error and perform error handling Figure 7 Erasure Block Number Specifications 4 4 4 Write Data Size After receiving a WRITE command from the master the slave receives 4 bytes of write data size Figure 8 shows the specifications of the write data size Write data size unsigned long type b31 b30 b29 b28 b27 b26 b25 b24 b23 b22 b21 b20 b19 b18 b17 b16 Z23 SZ22 SZ21 SZ20 SZ19 SZ18 SZ17 SZ16 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO The sample program uses a write size of 8 KB so the write data size value is 0000 2000h Notes 1 The write data size must be greater than zero and less than or equal to the erase block size for the specified erase block If O or a value greater than the erase block size is specified the slave will recognize an error and perform error handling 2 The size of write data transmissions is fixed at 256 bytes Consequently if the write data size specifies a value that is not a multiple of 256 bytes the master transmits write data in units of 256 bytes and then fills in the final unit of write data which is less than 256 bytes with bytes of value FFh as padding to reach a total of 256 bytes which it transmits to the slave Figure 8 Write Data Size Specifications R01AN0640EJ0102 Rev 1
18. RROR_NO_01 ERROR_NO_02 On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave Setting Value Description Functions Used By Data indicating error state Flash_Update Indicate_Error LED ERROR_NO_03 ERROR_NO_04 ERROR_NO_05 ERROR_NO_06 ERROR_NO_07 ERROR_NO_08 WRITE_ADRS_TOP_16K CO N OD 01 BR OG PO H 0Ox00FCO000 Start address of the 16 KB block Flash_Update size area in the write erase address space WRITE_ADRS_TOP_4K 0x00FF8000 Start address of the 4 KB block size area in the write erase address space Mar 04 2015 BLK_SIZE_16K 16 x 1024 The size of each of the blocks in EBO08 to EB21 BLK_SIZE_4K 4 x 1024 The size of each of the blocks in EBOO to EB07 RO1AN0640EJ0102 Rev 1 02 Page 19 of 40 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 4 RAM Variables Table 14 lists the RAM variables used by the slave device Table 14 RAM Variables of Slave Device Variable Type Description wrdata_buffer BUF_SIZE unsigned char Array for storing 256 bytes of write data received from the slave 256 bytes fcu_info ST_FCU_INFO Structure for storing FCU related address information used to program erase the user MAT 28 bytes p_write_buffer unsigned short Address of write data storage area used when programming user MAT 4 bytes p_command_adrs unsigned char FCU command destination addres
19. Slave 8 SCI_Revnbyte Function a Functional Overview The SCI_Rcvnbyte function controls reception of n bytes of data n is the first argument and unsigned short type using asynchronous serial communication by SCIO b Arguments Table 18 lists the arguments used by this function Table 18 Arguments of SCI_Revnbyte Function Arguments Type Description ist argument unsigned short Receive data byte count obtained using asynchronous serial communication by SCIO 2nd argument unsigned char Start address of receive data storage location c Return Values None RO1AN0640EJ0102 Rev 1 02 Page 35 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave d Flowchart SCI_Revnbyte NG Error handling when an overrun _ error or framing error occurs error No 01 Overrun error or framing error OK indicate Eror LED No Reception of 1 byte done Yes Clear RXIO interrupt status flag to 0 Read 1 byte of receive data from RDR of SCIO Read receive data from RDR and store it in the receive data storage location obtained as the second argument Increment the address of the receive data Increment address of receive l maarata storage location obtained as the second data storage location argument Decrement receive data count 1 Decrement the receive data byte count obtained as the first argum
20. acter length bit Only in asynchronous Rw communication mode 0 Transmission and reception with an 8 bit data length b7 CM 0 Communication mode bit 0 Asynchronous mode RW Notes 1 For information on n setting values see the User s Manual listed in 7 Reference Documents 2 Writing to these bits is possible only when the TE and RE bits in SCIO SCR are both cleared to 0 serial transmission and serial reception both disabled SCIO Smart Card Mode Register SCIO SCMR Number of Bits 8 Address 0008 8246h Setting Bit Symbol Value Bit Name Function R W bO SMIF 0 Smart card interface 0 Serial communication interface RW mode select bit mode b3 SDIR 0 Bit order selection bit 0 LSB first transmission reception R W Note Writing to this bit is possible only when the TE and RE bits in SCIO SCR are both cleared to 0 serial transmission and serial reception both disabled SCIO Bit Rate Register SCIO BRR Number of Bits 8 Address 0008 8241h Setting Bit Symbol Value Bit Name Function R W b7 to 00110001 31h Bit rate 31 250 bps RW bO When PCLK is 50 MHz Notes 1 For information on BRR setting values see the User s Manual listed in 7 Reference Documents 2 While this register can be read at any time it can only be written when both the SCIO SCR TE bit and the SCIO SCR RE bits are 0 serial transmission disabled and serial reception disabled RO1AN0640EJ0102 Rev 1 02 Page 23 of 40 Mar 04 2015 RENESAS
21. bled RM 1 1 Serial reception enabled b5 TE 0 Transmit enable bit 0 Serial transmission disabled Rw 1 1 Serial transmission enabled b6 RIE 0 Receive interrupt enable bit 0 RXIO and ERIO interrupts R W disabled 1 1 RXIO and ERIO interrupts enabled b7 TIE 0 Transmit interrupt enable bit 0 TXIO interrupt disabled R W 1 1 TXIO interrupt enabled Notes 1 Writing to these bits is possible only when the TE and RE bits are both cleared to 0 2 A value of 1 may be written to either these bits only when the TE and RE bits are both cleared to 0 Also 0 may be written to both the TE and RE bits after one of them has been set to 1 RO1ANO640EJ0102 Rev 1 02 Page 22 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave SCIO Serial Mode Register SCIO SMR Number of Bits 8 Address 0008 8240h Serial communication interface mode SMIF bit in SCIO SCMR 0 Setting Bit Symbol Value Bit Name Function R W a A Aenea an Tine naoa o b1 b0 CKS 1 0 00 Clock select bit 00 PCLK clock n 0 RW b2 MP 0 Multiprocessor mode bit Only in asynchronous RM communication mode 0 Multiprocessor communication function disabled b3 STOP 0 Stop bits length select bit Only in asynchronous RW communication mode 0 One stop bit b5 PE 0 Parity enable bit Only in asynchronous RW communication mode Transmission 0 No parity bits Reception 0 Reception with no parity b6 CHR 0 Char
22. cccecceceeeeeceeeeeeeeeeeaaeeeeeeeceeeeesaaeeeeaaeseeeeeseeeesaeeseaeeeeaes 4 8 Functions Used ueacsccarinaiirin riaa AENEA TEA A AAT 4 4z Operation niecne enee neg PR Na 5 5 Software DeSCription cccceceseceeececeeeeeeeaeeeeaeeeeeeeecaeeeeaaeseeaaesgaeeeseaeeseaaesgeneeseeeesaesseaaeseeneesseeeaas 16 Ox Usada NOLS creeni E ace dita Pade ces aap eure eters eee E eee See 38 7 Reference DOCUMEMMS ccccccescccceeeeeceeeeeeeceeeeseceeeeeaeeesaaeceaesageaeaesaaecaaesaaeeeeesaeeeeesneeaeeesneeeentnes 39 RO1ANO640EJ0102 Rev 1 02 Page 1 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 1 Specifications e This application note describes writing and erasing the user MAT using an RX62T Group R5F562TAADFP microcontroller in single chip mode e The slave receives the erase block number write data size and write data using asynchronous serial communication from the master and performs the write and erase operations required on the user MAT e The SCI channel 0 SCIO module is used for asynchronous serial communication between the master and the slave e Asynchronous serial communication specifications Bit rate 31 250 bps Data length 8 bits Parity bits none Stop bits 1 bit e In this application note s sample program the slave erases the specified erase block EB08 16 KB and writes the received 8 KB 256 bytes x 32 of write data
23. e of the target erase block RO1AN0640EJ0102 Rev 1 02 Page 20 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 6 I O Registers The I O registers of the slave device used by the sample program are listed below Note that the setting values shown are those used in the sample program and differ from the initial setting values 1 Clock Generation Circuit System Clock Control Register SCKCR Number of Bits 32 Address 0008 0020h Setting Bit Symbol Value Bit Name Function R W b11to PCK 3 0 0001 Peripheral module clock 0001 x 4 R W b8 PCLK select bits PCLK 50 MHz b27 to ICK 3 0 0000 System clock ICLK select 0000 x 8 R W b24 bits ICLK 100 MHz 2 TO Ports Port 7 Data Register P7 DR Number of Bits 8 Address 0008 C027h Setting Bit Symbol Value Bit Name Function R W b1 B1 0 P71 output data storage bit 0 Output data 0 R W 1 1 Output data 1 b2 B2 0 P72 output data storage bit 0 Output data 0 R W 1 1 Output data 1 b3 B3 0 P73 output data storage bit 0 Output data 0 R W 1 1 Output data 1 Port 3 Data Register P3 DR Number of Bits 8 Address 0008 C023h Setting Bit Symbol Value Bit Name Function R W b3 B3 0 P33 output data storage bit 0 Output data 0 R W 1 1 Output data 1 Port 7 Data Direction Register P7 DDR Number of Bits 8 Address 0008 C007h Setting Bit Symbol Value Bit Name Function R W b1
24. ent Repeat the receive operation until the receive data byte count obtained as the first argument reaches 0 The sample program uses a while 0 loop for this purpose l 0 Receive data count End Figure 20 Flowchart SCI_Rcevnbyte Slave RO1AN0640EJ0102 Rev 1 02 Page 36 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 9 SCI_Trsibyte Function a Functional Overview The SCI_Trs1byte function controls transmission of one byte of data using asynchronous serial communication by SCIO b Arguments Table 19 lists the arguments used by this function Table 19 Arguments of SCI_Trsibyte Function Arguments Type Description ist argument unsigned char Transmit data byte count obtained using asynchronous serial communication by SCIO c Return Values None d Flowchart SCI_Trs1byte Write transmit data to TDR Write the 1 byte of transmit data from the 1st argument to TDR of SCIO Wait for transmission of 1 byte of data to finish Figure 21 Flowchart SCI_Trsibyte Slave RO1AN0640EJ0102 Rev 1 02 Page 37 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 6 Usage Notes 6 1 Notes on the Wait Time for a 1 Bit Period for the Bit Rate at SCIO Initialization In this application note the 1 bit period wait time f
25. eset_PC Function a Functional Overview The PowerON_Reset_PC function initializes the stack pointer a pragma entry declaration causes the compiler automatically to generate ISP USP initialization code at the start of the PowerON_Reset_PC function sets INTB set_intb function embedded function initializes FPSW set_fpsw function embedded function initializes the RAM area section _INITSCT function standard library function calls the HardwareSetup function initializes PSW set_psw function embedded function and sets user mode as the processor mode Then it calls the main function b Arguments None c Return Values None d Flowchart PowerON_Reset_PC set_fpsw Use the set_intb embedded function to set the start address of the C VECT section in the INTB register Use the set_fpsw embedded function to initialize the FPSW register Use the _INITSCT standard library function to initialize SLUSS the RAM section HardwareSetup Call the MCU initial settings function Use the set_psw embedded function to initialize the PSW register Set processor mode Set user mode as the processor mode sores Call the main function set psw Joo i Call the brk embedded function BRK instruction Figure 11 Flowchart PowerON_Reset_PC Slave RO1AN0640EJ0102 Rev 1 02 Page 26 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in S
26. ff control of LED 0 on the HardwareSetup evaluation board main Indicate_Ending_ LED Indicate_Error_LED RSK_LED1 PORT7 DR BIT B2 On off control of LED 1 on the HardwareSetup evaluation board main Indicate_Ending_ LED Indicate_Error_LED RSK_LED2 PORT7 DR BIT B3 On off control of LED 2 on the HardwareSetup evaluation board main Indicate_Ending_LED Indicate_Error_LED RSK_LED3 PORT3 DR BIT B3 On off control of LED 3 on the HardwareSetup evaluation board main Indicate_Ending_ LED Indicate_Error_LED RSK_LEDO_DDR PORT7 DDR BIT B1 I O control for LED 0 on the HardwareSetup evaluation board RSK_LED1_DDR PORT7 DDR BIT B2 I O control for LED 1 on the HardwareSetup evaluation board RSK_LED2_DDR PORT7 DDR BIT B3 I O control for LED 2 on the HardwareSetup evaluation board RSK_LED3_DDR PORT3 DDR BIT B3_ I O control for LED 3 on the HardwareSetup evaluation board WAIT_SCI1BIT 1920 Standby time data used after HardwareSetup setting the SCIO BRR register WAIT_LED 2000000 LED illumination interval data for Indicate_Ending_ LED indication of successful completion Indicate_Error_LED of programming erasing of slave user MAT SIZE_WRITE_BLOCK 128 Write size for programming user Flash_Update MAT word units BUF_SIZE 256 Size of write data storage area Flash_Update RxDO_ICR PORTB ICR BIT B1 RxDO input buffer settings HardwareSetup RO1AN0640EJ0102 Rev 1 02 Mar 04 2015 RENESAS Page 18 of 40 RX62T Group Symbolic Constant E
27. g The R_FlashErase function provided by the RX600 Simple Flash API is used for user MAT erase processing Therefore the block numbers for erasing are the same as the values specified to the R_FlashErase function Erase errors are indicated in the return value from the R_FlashErase function 4 5 2 User MAT Write Processing The R_FlashWrite function provided by the RX600 Simple Flash API is used for user MAT write processing Write errors are indicated in the return value from the R_FlashWrite function 4 5 3 Changes to the Simple Flash API The Simple Flash API r_flash_api_rx600_config h file is modified for this application note Table 7 lists the changes to r_flash_api_rx600_config h Table 7 Changes to r_flash_api_rx600_config h Item Changed Place Changed Changes to Simple Flash API settings define IGNORE_LOCK_BITS define COPY_CODE_BY_API define FLASH_API_USE_R_BSP 4 5 4 Notes on Using Interrupts Flash ROM cannot be access during ROM write or erase operations Therefore it is necessary to prevent access to the ROM by interrupts that occur during write or erase operations Although interrupts are not used in this application note this sample program includes code that suppresses interrupts but that code is commented out This sample interrupt suppression code is shown below Holds IPL of processor before flash operation static unsigned char flash_pipl Save current processor IPL flash_
28. ia an UART Interface Slave 7 Reference Documents User s Manual RX62T Group User s Manual Hardware Rev 1 10 The latest version can be downloaded from the Renesas Electronics Web site RX Family User s Manual Software Rev 1 00 The latest version can be downloaded from the Renesas Electronics Web site Development Environment Manual RX Family C C Compiler Package User s Manual Rev 1 01 The latest version can be downloaded from the Renesas Electronics Web site Application Note RX62T Group On chip Flash Memory Reprogramming in Single chip Mode via an UART Interface Slave ROLAN0639EJ The latest information can be downloaded from the Renesas Electronics Web site RX600 Series Simple Flash API for RX600 Rev 2 20 RO1AN0544EU The latest information can be downloaded from the Renesas Electronics Web site Technical Updates The latest information can be downloaded from the Renesas Electronics Web site RO1AN0640EJ0102 Rev 1 02 Page 39 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave Website and Support Renesas Electronics Website http www renesas com Inquiries http www renesas com contact All trademarks and registered trademarks are the property of their respective owners RO1AN0640EJ0102 Rev 1 02 Page 40 of 40 Mar 04 2015 RENESAS Revision History Description Rev Date Page Summary
29. ingle Chip Mode via an UART Interface Slave 2 HardwareSetup Function a Functional Overview The HardwareSetup function makes initial settings to the MCU It makes initial clock settings system clock ICLK and peripheral module clock PCLK initial I O settings for the I O ports P71 P72 P73 and P33 connected to LEDO to LED3 and initial settings to SCIO b Arguments None c Return Values None d Flowchart HardwareSetup System clock ICLK 100 MHz Clock settings Peripheral module clock PCLK 50 MHz e LEDO P71 Initial output high LEDO turning off REFE rd ee e LED1 P72 Initial output high LED1 turning off CEO POI lata VS SENGS LED2 P73 Initial output high LED2 turning off e LED3 P33 Initial output high LED3 turning off Cancel SCIO module stop state e Disable transmit and receive operation Enable PB1 RxDO input pin buffer e Set PCLK clock as clock source of on chip baud rate generator e Set asynchronous mode as communication mode e Set serial communication interface mode as SCIO operating mode e Set the bit rate to 31 250 bps when PCLK 50 MHz e Set the data length to 8 bits e Set no parity bit e Set number of stop bits to 1 e Wait for a 1 bit period at the bit rate e Set the SCIO interrupt priority level to interrupts disabled e Disable TXIO and RXIO interrupts e Clear TXIO and RXIO interrupt status flags SCIO initial sett
30. ings End Figure 12 Flowchart HardwareSetup Slave R01AN0640EJ0102 Rev 1 02 Page 27 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 3 main Function a Functional Overview The main function controls reception of one byte of data from the master calls the Indicate_Error_LED function when an error occurs and calls the user MAT write control program the Flash_Update function in internal RAM b Arguments None c Return Values None d Flowchart main Enable SCIO transmit and receive operation Enable RXI0 ERIO and TXIO interrupts Overrun error or framing error NG Error handling when an overrun error or framing error occurs error No 01 Indicate_Error_LED Reception of 1 byte done Yes Clear RXIO interrupt status flag to 0 Read receive data from RDR Read 1 byte of receive data from RDR of SCIO FSTART No Error handling when the received data is not an command received ieee FSTART command error No 02 Yes Indicate_Error_LED Jump to the user MAT programming erase control Flash_Update E E program Flash_Update function in on chip RAM End Note See 6 3 rom Option for details Figure 13 Flowchart main Slave RO1AN0640EJ0102 Rev 1 02 Page 28 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory
31. ion used here Table 5 Asynchronous Serial Communication Specifications Item Description Channel SCI channel 0 SCIO Communication mode Asynchronous mode Bit rate 31 250 bps PCLK 50 MHz Data length 8 bits Parity bit None Stop bit 1 bit Error Overrun error framing error 4 4 1 Communication Sequence Figures 3 to 6 show the communication sequence between master and slave IRQ switch pressed Yes Issue FSTART command 1 byte of data received m FSTART command received FSTART command y 1 byte Error processing ACCEPTABLE command E 1 byte Issue ACCEPTABLE command ACCEPTABLE command received Figure 3 Communication Sequence 1 R01AN0640EJ0102 Rev 1 02 Page 6 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave ERASE command S 1 byte of data received Issue ERASE command 1 byte Yes No ERASE command received Error processin ACCEPTABLE command Yes aia Issue ACCEPTABLE command 1 byte 1 byte of data received ACCEPTABLE command received Erase block number Transmit erase block number 1 byte Yes NG Erase block number check z Erase the block specified by the received erase block number NG Erase processing check
32. ister Setting O Port State LED State P71 PORT7 DR B1 1 PORT7 DDR B1 1 High level output LEDO Off PORT7 DR B1 0 PORT7 DDR B1 1 Low level output On P72 PORT7 DR B2 1 PORT7 DDR B2 1 High level output LED1 Off PORT7 DR B2 0 PORT7 DDR B2 1 Low level output On P73 PORT7 DR B3 1 PORT7 DDR B3 1 High level output LED2 Off PORT7 DR B3 0 PORT7 DDR B3 1 Low level output On P33 PORT3 DR B3 1 PORT3 DDR B3 1 High level output LED3 Off PORT3 DR B3 0 PORT3 DDR B3 1 Low level output On 4 7 Normal End Processing When programming erasing of the user MAT completes successfully the slave makes a normal end indication by means of four LEDs connected to the device The normal end indication consists of LEDO to LED3 illuminating one after another in a sequence that is repeated multiple times RO1AN0640EJ0102 Rev 1 02 Page 13 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 8 Error Handling Table 9 lists the slave device errors that apply to the sample program Error handling consists of indicating the error state by means of four LEDs connected to the device Table 9 List of Slave Errors LED Indication Error No Description LED3 LED2 LED1 LEDO Error No 01 An overrun or framing error occurred Off Off Off On Error No 02 In the FSTART command wait state the command Off Off On Off received from the master was not an FSTART
33. mponent RX E1 E20 SYSTEM V 1 02 00 Optimizing linkage editor rom option rom D R D_1 R_1 D_2 R_2 PFRAM RPFRAM Note See 6 3 rom Option for details 3 Functions Used e Clock generation circuit e Low Power Consumption e Interrupt control unit e I O ports e Serial Communications Interface e ROM flash memory for code storage For details see the User s Manual listed in 7 Reference Documents RO1ANO640EJ0102 Rev 1 02 Page 4 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 Operation 4 1 Operation Mode Settings In the sample program the slave s mode pins are set to MD1 1 MDO 1 to select single chip mode as the operating mode the ROME bit in system control register 0 SYSCRO is set to 1 to enable the on chip ROM The slave is activated from the user MAT in single chip mode Table 2 lists the slave operating mode settings used in the sample program Table 2 Operating Mode Settings of Slave Device Mode Pin SYSCRO Register MD1 MDO ROME Operating Mode On Chip ROM 1 1 1 Single chip mode Enabled Note The initial setting of the ROME bit in the SYSCRO register is SYSCRO ROME 1 so it is not necessary for the sample program to make settings to the SYSCRO register 4 2 Clock Settings The evaluation board used for this application note includes a 12 5 MHz crystal oscillator Therefore this application no
34. n unused pin in the open circuit state extra electromagnetic noise is induced in the vicinity of LSI an associated shoot through current flows internally and malfunctions occur due to the false recognition of the pin state as an input signal become possible Unused pins should be handled as described under Handling of Unused Pins in the manual 2 Processing at Power on The state of the product is undefined at the moment when power is supplied The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied In a finished product where the reset signal is applied to the external reset pin the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provided for the possible future expansion of functions Do not access these addresses the correct operation of LSI is not guaranteed if they are accessed 4 Clock Signals After applying a reset only release the reset line after the operating clock signal has become stable When switching the clock
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36. oop Wait WAIT_LED loop count WAIT_LED LED2 on LEDO LED1 and LEDS off Wait WAIT_LED LED3 on LEDO to LED2 off Wait WAIT_LED Wait processing using for loop loop count WAIT_LED Wait processing using for loop loop count WAIT_LED Figure 17 Flowchart Indicate_Ending_LED Slave RO1AN0640EJ0102 Rev 1 02 Page 32 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 6 Indicate_Error_LED Function a Functional Overview When an error occurs during programing erasing of the user MAT the Indicate_Error_LED function indicates the error number using LEDO to LED3 The display alternates repeatedly between the error number indication and all LEDs off b Arguments Table 16 lists the arguments used by this function Table 16 Arguments of Indicate_Error_LED Function Arguments Type Description 1st argument unsigned char Error number that occurred during programing erasing of the user MAT Note For information on error numbers see 4 8 Error Handling c Return Values None d Flowchart Indicate_Error LED Display error number 01 to ii abet vat oi ode e For a description of the indications of 08 using LEDO to LED3 LEDO to LEDS see 4 8 Error Handling Wait processing using for loop loop count WAIT_LED Wait WAIT_LED LEDO to LED3 off Turn all of
37. or the bit rate after setting the bit rate register SCIO BRR at SCI initialization is measured using a software timer Since the bit rate for SCIO asynchronous serial communication is 31 250 bps the bit period is calculated as follows The 1 bit period for the 31 250 bps bit rate is 32 us In this application note the 1 bit period wait time for the bit rate is implemented by iterating a while loop with the loop count defined by the WAIT_SCI1BIT symbolic constant If we take the number of cycles to execute one iteration of the while loop to be 5 cycles which can be verified from the assembly language output by the compiler the number of iterations can be calculated as follows while loop run count wait duration cycle count per while loop iteration x ICLK cycle duration Note that the CPU s instruction processing time can differ due to pipelining so the above mentioned number of cycles per while loop iteration 5 cycles is a rough estimate of the instruction processing time In the sample program the wait duration is calculated as 96 us to provide a sufficient margin as follows while loop run count WAIT_SCI1BIT 96 us 5 x 10 ns 1 920 ICLK 100 MHz Therefore the symbolic constant WAIT_ SCI1BIT is defined as 1 920 To use this application note users should either carefully evaluate the CPU instruction execution time or use a timer to measure this time Note The number of cycles value below is for refe
38. pipl get_ipl lf your system is using the interrupt Enable this line Set the processor IPL so that interrupts that access ROM will not occur during ROM program erase operations set_ipl FLASH_READY_IPL If your system is using the interrupt Enable this line Erasure process by using simple API fcu_status R_FlashErase uint8_t target_eb Programming process by using simple API fcu_status R_FlashWrite uint32_t fcu_info p_write_adrs_now uint32_t wrdata_buffer BUF_SIZE Program 256 byte data to the target EB by using simpleAPI call of R_FlashWrite function in simpleAPI Restore processor IPL set_ipl flash_pipl lf your system is using the interrupt Enable this line RO1ANO640EJ0102 Rev 1 02 Page 12 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 6 LED Connections Figure 9 shows the connections of the slave I O ports and LEDO to LED3 5 0 V 5 0 V 5 0 V 5 0 V Figure 9 Slave Device LED Connection Diagram As shown in figure 9 high level output from an I O port P71 P72 P73 or P33 causes the corresponding LED among LEDO to LED3 to turn off and low level output causes the corresponding LED to illuminate Table 8 shows the correspondence between I O port output and LED states Table 8 Slave I O Port Output and LED States O Port Reg
39. rence The actual value will vary according to the conditions of the user s system 6 2 Note on Reprogramming Erasure Block EB00 The erasure block EBOO programming erase address range 0OOFF E000h to OOFF FFFF read address range FFFF E000h to FFFF FFFFh contains areas allocated for fixed vectors FFFF FF80h to FFFF FFFFh ID code protection FFFF FFAOh to FFFF FFAFh etc When EBO0 is programmed erased the above mentioned fixed vector and ID code protection data is erased It is therefore necessary to make fixed vector and ID code protection settings again after erasing EBOO ID code protection is a function that disables programming and erasing by the host ID code protection determinations are made by using a control code and ID code programmed in the ROM For details of ID code protection see the User s Manual listed in 7 Reference Documents 6 3 rom Option The procedure described in this application note uses the rom option of the optimizing linkage editor to relocate the defined symbols in PFRAM ROM section to addresses in RPFRAM RAM section As a result after the Flash_Update function is called the addresses in RAM are used as the run addresses For details of the rom option see RX Family C C Compiler Package User s Manual REJ10J2062 listed in section 7 Reference Documents RO1AN0640EJ0102 Rev 1 02 Page 38 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode v
40. responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information 2 Renesas Electronics has used reasonable care in preparing the information included in this document but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein 3 Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others 4 You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration modification copy or otherwise misappropriation of Renesas Electronics product 5 Renesas Electronics products are classified according to the following two quality grades Standard and High Quality The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below Sta
41. rol functions R_FlashErase r_flash_api_rx600 c User MAT erase control function R_FlashWrite r_flash_api_rx600 c User MAT programming control function Indicate_Ending_LED main c Normal end processing function Indicate_Error_LED main c Error end processing function SCI_Revibyte main c 1 byte data reception function SCI_Revnbyte main c n byte data reception function SCI_Trs1byte main c 1 byte data transmission function PowerON_Reset_PC HardwareSetup Flash_Update R_FlashErase R_FlashWrite Indicate_Ending LED Indicate_Error_LED SCI_Rev1byte SCI_Revnbyte id SCI_Trs1byte Figure 10 Hierarchy of Slave Device Functions RO1AN0640EJ0102 Rev 1 02 Page 17 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 3 Symbolic Constants Table 13 lists the symbolic constants used by the slave device Table 13 Symbolic Constants of Slave Device Symbolic Constant Setting Value Description Functions Used By FSTART 0x10 Programming erase start command main ERASE 0x11 Erase start command Flash_Update WRITE 0x12 Programming start command Flash_Update ACCEPTABLE 0x55 Status command sent to the main master LED_ON 0 Set value used when the LED is on _ Indicate_Ending_LED Indicate_Error_LED LED_OFF 1 Set value used when the LED is off HardwareSetup Indicate_Ending_ LED Indicate_Error_LED RSK_LEDO PORT7 DR BIT B1 On o
42. s programming erase address 4 bytes p_erase_adrs unsigned short Start address of erase target erasure block programming erase address 4 bytes p_write_adrs_top unsigned short Start address of programming target erasure block programming erase address 4 bytes p_write_adrs_end unsigned short End address of programming target erasure block programming erase address 4 bytes p_write_adrs_now unsigned short Programming target address programming erase address 4 bytes eb_block_size unsigned long Block size of the target erase block 4 bytes Note 1 For details on the ST_FCU_INFO type see 5 5 Structures 5 5 Structures Table 15 lists the specifications of the ST_FCU_INFO structure used by the slave device Table 15 ST_FCU_INFO Structure Specifications Member Type Description p_write_buffer unsigned short Address of write data storage area used when programming user MAT p_command_adrs unsigned char FCU command destination address programming erase address p_erase_adrs unsigned short Start address of erase target erasure block programming erase address p_write_adrs_top unsigned short Start address of programming target erasure block programming erase address p_write_adrs_end unsigned short End address of programming target erasure block programming erase address p_write_adrs_ now unsigned short Programming target address programming erase address eb_block_size unsigned long Block siz
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46. signal during program execution wait until the target clock signal has stabilized When the clock signal is generated with an external resonator or from an external oscillator during a reset ensure that the reset line is only released after full stabilization of the clock signal Moreover when switching to a clock signal produced with an external resonator or by an external oscillator while program execution is in progress wait until the target clock signal is stable 5 Differences between Products Before changing from one product to another i e to a product with a different type number confirm that the change will not lead to problems The characteristics of an MPU or MCU in the same group but having a different part number may differ in terms of the internal memory capacity layout pattern and other factors which can affect the ranges of electrical characteristics such as characteristic values operating margins immunity to noise and amount of radiated noise When changing to a product with a different part number implement a system evaluation test for the given product Notice 1 Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no
47. te uses the following settings for the system clock ICLK and the peripheral module clock PCLK 8x 100 MHz and 4x 50 MHz 4 3 Endian Mode Setting The sample program presented in this application note supports both big and little endian mode Table 3 lists the hardware MDE pin endian mode settings of the slave device Note that the master and slave endian settings must match Table 3 Endian Mode Settings of Slave Device Hardware MDE pin Endian 0 Little endian 1 Big endian Table 4 lists the endian settings used in the compiler options Table 4 Endian Mode Settings of Slave Device Compiler Options MCU Option Endian endian little Little endian endian big Big endian Note Set the MDE bit to match the endian mode selected as a compiler option RO1AN0640EJ0102 Rev 1 02 Page 5 of 40 Mar 04 2015 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 4 4 Asynchronous Serial Communication Specifications This application note uses asynchronous serial communication between the master and the slave to receive communication commands FSTART ERASE WRITE the erase block number the write data size and the write data itself Note that the slave transmits the ACCEPTABLE command 55h as a status command for handshaking The used SCIO TxDO and RxD0 pins are each pulled up externally Table 5 shows the specifications of the asynchronous serial communicat
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49. upport option B Uninitialized data area ALIGN 4 R Area mapped in RAM as the D section by the ROM support option SI Interrupt stack area PResetPRG FFFF E000h Program area PowerON_Reset_PC program P Program area PIntPRG Program area interrupt program C_1 FFFF E800h Constant area ALIGN 1 C_2 Constant area ALIGN 2 C Constant area ALIGN 4 C Section initialization table of uninitialized data area relocatable vector area D_1 Initialized data area ALIGN 1 D2 Initialized data area ALIGN 2 D Initialized data area ALIGN 4 W Switch statement branch table area ALIGN 4 PFRAM FFFF FO00h Program area user MAT programming control program Fixed vector area Page 15 of 40 RENESAS RX62T Group On chip Flash Memory Reprogramming in Single Chip Mode via an UART Interface Slave 5 Software Description 5 1 File Structure Table 11 shows the file structure of the slave device In addition to the files listed in table 11 some files generated automatically by High performance Embedded Workshop are used as well Table 11 File Structure of Slave Device File Name Description resetprg c Initial settings main c This program handles the following operations reception and transmission control for communication commands using asynchronous serial communication with the master reception control for the erase block number the write data size and the write data control of LED display at normal
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