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S1D13A04 TECHNICAL MANUAL - Digi-Key

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1. Oscillator MC68K 1 Sue IOVDD _ Y RD x FPDAT 17 0 gt D 17 0 18 bit WEO FPFRAME gt SPS HR TFT A 23 18 i e Decoder W R EE eee Display FPSHIFT CLK __ Decoder gt CS GPIOO _ PS POr y CLS A 17 1 gt AB 17 1 Soe BEY a D 15 0 l4 gt DB 15 0 GPIO3 y SPL LDS gt ABO S1 D1 3A04 UDS gt WE1 AS gt BS R W gt RD WR DTACK ly WAIT CLK gt CLKI RESET gt RESET Figure 3 5 Typical System Diagram MC68K 1 Motorola 16 Bit 68000 Oscillator MC68K 2 BUS y A 31 18 S FCO FC1 gt Decoder M R A FPDAT 17 0 D 17 0 18 bit Decoder gt CS FPFRAME SPS HR TFT A 17 0 gt AB 17 0 OS a Display FPSHIFT ___ D 31 16 l4 gt DB 15 0 S oe GPioo __ Ps es Wee GPIo1 _____ CLS Fae d s GPIO2 ____ REV gt GPIO3 __ SPL R W gt RD WR S1 D1 3A04 SIZ1 gt RD SIZO gt WEO DSACK1 la WAIT CLK gt CLKI RESET gt RESET Figure 3 6 Typical System Diagram MC68K 2 Motorola 32 Bit 68030 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 18 Epson Research and Development Vancouver Design Center
2. Oscillator REDCAP2 BUS IOVDD y BS A 4 bit FPDAT 7 4 ___ pys 0 Single A 21 18 Decoder M R FPSHIFT FPSHIFT rh pos ispla CSn CS p ay A 17 1 gt AB 17 1 cies ad FPFRAME 3 D 15 0 gt DB 15 0 er ERRE a DRDY MOD 3 RW gt RD WR S1 D1 3A04 GPIOO i OE gt RD EBT gt WEO EBO gt WE1 CLK gt CLKI RESET_OUT gt RESET ABO vss Note CSn can be any of CS0 CS4 Figure 3 7 Typical System Diagram Motorola REDCAP2 Bus Oscillator MC68EZ328 MC68VZ328 y 5 Baji IOVDD _ a BUS BSA 8 bit RD WR FPDAT 7 0 D 7 0 Single LCD A 25 18 Decoder gt W R FPSHIFT _ FP SHIFT Display TSX gt OSH FPFRAME FPFRAME gt z FPLINE gt FPLINE A 17 1 gt AB 17 1 id me S1D13A04 a ane LWE p WEO GPIOO i UWE gt WE1 OE RD DTACK 4 WAIT CLKO gt CLKI RESET gt RESET ABO vss Figure 3 8 Typical System Diagram Motorola MC68EZ328 MC68VZ328 DragonBall Bus S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 19 Vancouver Design Center 3 2 USB Interface 1D13A04 USB Socket
3. le VDP sig VNDP a FPFRAME FPLINE DRDY MOD X FPDAT 15 0 Invalid LINE X LINE2 X LINES X LINE4 gt Invalid YX LINE X LINE2 X FPLINE i E DRDY MOD P HDP HNDP y FPSHIFT 3Ts 2Ts 3Ts 3Ts 2Ts 3Ts 3Ts 3Ts 2Ts 3Ts E 3Ts 3Ts 21s 3Ts 3Ts 2Ts 21s 3Ts 3Ts FPDAT15 Invalid 181 01 66 X1 B11 X X1 G635X Invalid FPDAT14 Invalid X 1 81 87 X1 G12X X 1 6630X Invalid X FPDAT13 Invalid X 1 62 X 1 87 X 1 R13X Xt XX ER637Y Invalid X FPDAT12 Invalid 1 R3 X 1 68 X1 B13 X X 1 B637X Invalid X FPDAT7 Invalid 1 B3 X _1 R9 X1 G14X Y XG y 1 G638X Invalid FPDAT6 Invalid 1 64 Y 1 B9 X 1 R15X y X1 R639X Invalid X Y FPDAT5 Invalid 1 R5 X 1 G10X1 B15 X XO Y X 4 B639X_Invalid y FPDAT4 Invalid X 1B5 X 1 R11X1 G16 X y Y NEO invalid y FPDAT11 Invalid X 1 G1 X 1 B6 X 1 R12X Ye 1 R636X Invalid Y FPDAT10 Invalid 1 R2 X 1 G7 YX 1 812X Y YE Y 1 B636X Invalid FPDAT9 Invalid 1 B2 Y 1 R8 Y 1 G13X X X X X1 G637X Invalid X Y FPDAT8 Invalid 1 63 Y 1 88 Y 1 R14Y ya TRE invalid YX FPDAT3 Invalid 1 R4 X 1 G9 X 1 B14 Xx X1 B638X Invalid X X FPDAT2 Invalid 1 84 X1 R10 X 1 G15X X Y 1 G639X Invalid X FPDAT1 Invalid 1 G5 X 1 B10X 1 R16X Ke i R640X Invalid FPDATO Invalid 1 R6 X1 G11 X 1 B16X Ye X1 B640X Invalid Y Notes The duty cycle of FPSHIFT changes in order to proc
4. Epson Research and Development Page 25 Vancouver Design Center Table 5 9 Suggested LUT Values 8 bpp Color Continued Index R G B Index R G B Index R G B jIndex R G B 24 44 00 00 64 00 FF BC A4 BC 00 FF E4 44 FF 44 25 55 00 00 65 00 FF AB A5 AB 00 FF E5 55 FF 55 26 66 00 00 66 00 FF 9A A6 9A 00 FF E6 66 FF 66 27 77 00 00 67 00 FF 89 A7 89 00 FF E7 77 FF 77 28 89 00 00 68 00 FF 77 A8 77 00 FF E8 89 FF 89 29 9A 00 00 69 00 FF 66 A9 66 00 FF E9 9A FF 9A 2A AB 00 00 6A 00 FF 55 AA 55 00 FF EA AB FF AB 2B BC 00 00 6B 00 FF 44 AB 44 00 FF EB BC FF BC 2C CD 00 00 6C 00 FF 33 AC 33 00 FF EC CD FF CD 2D DE 00 00 6D 00 FF 22 AD 22 00 FF ED DE FF DE 2E EF 00 00 6E 00 FF 11 AE 11 00 FF EE EF FF EF 2F FF 00 00 6F 00 FF 00 AF 00 00 FF EF FF FF FF 30 00 00 00 70 00 FF 00 BO 00 00 00 FO 00 00 FF 31 00 11 00 71 11 FF 00 B1 11 00 11 F1 11 11 FF 32 00 22 00 72 22 FF 00 B2 22 00 22 F2 22 22 FF 33 00 33 00 73 33 FF 00 B3 33 00 33 F3 33 33 FF 34 00 44 00 74 44 FF 00 B4 44 00 44 F4 44 44 FF 35 00 55 00 75 55 FF 00 B5 55 00 55 F5 55 55 FF 36 00 66 00 76 66 FF 00 B6 66 00 66 F6 66 66 FF 37 00 77 00 77 77 FF 00 B7 77 00 77 F7 77 77 FF 38 00 89 00 78 89 FF 00 B8 89 00 89 F8 89 89 FF 39 00 9A 00 79 9A FF 00 B9 9A 00 9A F9 9A 9A FF 3A 00 AB 00 7A AB FF 00 BA AB 00 AB FA AB AB FF 3B 00 BC 00 7B BC FF 00 BB BC 00 BC FB BC BC FF 3C 00 CD 00 7C CD FF 00 BC
5. Epson Research and Development Page 61 Vancouver Design Center tl t2 Sync Timing i d FPFRAME Hr lt t3 gt FPLINE t5 pe gate DRDY MOD Data Timing FPLINE t6 7 t7 FPSHIFT FPDAT 7 4 Figure 6 16 Single Monochrome 4 Bit Panel A C Timing Table 6 20 Single Monochrome 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 4 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPDAT 7 4 setup to FPSHIFT falling edge 1 Ts t13 FPDAT 7 4 hold to FPSHIFT falling edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 min t3min HPS t4min 4 Bmin HT 5 t4min HPW 6 min HPS 1 7 min HPS HDP HDPS 2 if negative add t3 pin 8 t14min HDPS HPS t4 min if negative add t3min Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 62 Epson Research and Development Vancouver D
6. USBCLK gt CLKUSB CLKI e o o gt BCLK 22 1 CNF6 REG 04h bits 5 4 o 2 01 MCLK e 3 10 4 11 00 e m 000 O 10 e 2 001 CLKI2 o 11 e 3 010 gt PCLK e E 11 REG 08h bits 1 0 Bs y 8 1xx 00 ji 01 REG 08h bits 6 4 10 gt PWMCLK We REG 70h bits 2 1 Figure 7 1 Clock Selection Note 1 CNF6 must be set at RESET Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 88 Epson Research and Development Vancouver Design Center 7 3 Clocks versus Functions Table 7 6 S1D13A04 Internal Clock Requirements lists the internal clocks required for the following S1D13A04 functions Table 7 6 SIDI3A04 Internal Clock Requirements Funci n Bus Clock Memory Clock Pixel Clock PWM Clock USB Clock BCLK MCLK PCLK PWMCLK USBCLK Register Read Write Required Not Required Not Required Not Required Not Required Memory Read Write Required Required Not Required Not Required Not Required Look Up Table Register 4 i Read Write Required Required Not Required Not Required Not Required Software Power Save Required Not Required Not Required Not Required Not Required LCD Output Required Required Required Not Required Not Required USB Register Read Write Required Not Required Not Required Not Required Required Note IPWMCLK is an optional
7. 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 6 bit Green Data F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 f A a 6 bit Blue Data F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111 8 bit per pixel data from Display Buffer Figure 12 8 8 Bit per pixel Color Mode Data Output Path 16 Bit Per Pixel Color Mode The LUT is bypassed and the color data is directly mapped for this color depth Display Data Formats on page 144 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 151 Vancouver Design Center 13 SwivelView 13 1 Concept Most computer displays are refreshed in landscape orientation from left to right and top to bottom Computer images are stored in the same manner SwivelView is designed to rotate the displayed image on an LCD by 90 180 or 270 in a counter clockwise direction The ro
8. ti t2 P t3 FPDAT 17 01 AO A ALLA a fue A A 1 1 t4 a a t5 t6 GPIO1 7 j CLS A t7 t sce ie a a ru U Ud aac FPLINE N JN LP FPSHIFT RW ce p t10 t11 t12 GPIO1 A a A CLS e t14 GPIOO Y di PS Figure 6 31 160x160 Sharp Direct HR TFT Panel Vertical Timing S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 79 Vancouver Design Center Table 6 28 160x160 Sharp Direct HR TFT Panel Vertical Timing Symbol Parameter Min Typ Max Units t1 Vertical total period 203 264 Lines t2 Vertical display start position 40 Lines t3 Vertical display period 160 Lines t4 Vertical sync pulse width 2 Lines t5 FPFRAME falling edge to GPIO1 alternate timing start 5 Lines t6 GPIO1 alternate timing period 4 Lines t7 FPFRAME falling edge to GPIOO alternate timing start 40 Lines t8 GPIOO alternate timing period 162 Lines t9 GPIO1 first pulse rising edge to FPLINE rising edge 4 Ts note 1 t10 GPIO1 first pulse width 48 Ts t11 GPIO1 first pulse falling edge to second pulse rising edge 40 Ts t12 GPIO1 second pulse width 48 Ts t13 GPIOO falling edge to FPLINE rising edge 4 Ts t14 GPIOO low pulse width 24 Ts 1 Ts pixel clock period Hardware Functional Specification S1D13
9. S1D13A04 interface S1D13A04 TMPR3905 12 CARDIORD gt RDA CARDIOWR gt WEO gt M R CARD1CSL gt WE1 CARD1CSH OV e BS A18 RD WR ENDIAN System RESET RESET Latch NY ALE gt hs gt CS A 12 0 eee gt AB 17 13 AB 12 0 D 31 24 DB 7 0 D 23 16 4 gt DB 15 8 HIOVDD pull up CARD1WAIT WAIT DCLKOUT See text gt CLKI2 gt Clock divider gt oh Oscillator CLKI Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 SIDI3A04 to TMPR3905 12 Direct Connection S1D13A04 X37A G 002 01 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 13 Vancouver Design Center The Generic 2 Host Bus Interface control signals of the S1D13A04 are asynchronous with respect to the S1D13A04 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and CLKI2 The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximu
10. z ee Manufacturer Part No Item Qty Designation Part Value Description Assembly Instructions C1 C11 C15 Ceramic Chip 50V X7R 5 1 25 C21 C28 C30 C32 C35 C48 0 1u 1206 pckg Kemet C1206C104J5RAC 1 C12 10u 10V Tantalum C Size 10 Kemet T491C106K010AS 2 C13 C14 n p 1206 pckg Do not populate Bie 27 A 45 046 Sgu 10V Tantalum D Size 10 Kemet T491D86K010AS Electrolytic Radial Lead NIPPON UNITED CHEMI CON 5 3 SERES 19UF 63X 20 KMF63VB10RM5X11LL Electrolytic Radial Lead NIPPON UNITED CHEMI CON 6 1 Car a 20 KMF35VB56RM5X11LL 7 9 C36 C44 0 22uF Ceramic Chip 50V XTR 5 Kemet C1206C224J5RAC 1206 pckg 8 2 C47 C50 33u 20V Tantalum D Size 10 Kemet T491D33K020AS 9 2 D1 D2 BAV99 eine nigh seco ATICO Rohm BAV99 diode 10 H1 HEADER 20X2 20x2 025 sq shrouded Thomas amp Betts P N 636 4027 or header keyed equivalent 411 1 H2 HEADER 8X2 8x2 025 sq shrouded header Thomas amp Betts P N 636 1627 or keyed equivalent 12 2 H3 H4 HEADER 17X2 17x2 025 sq unshrouded Thomas amp Betts P N 609 3407 or header right angle equivalent 13 5 JP1 JP5 HEADER 3 3x1 1 pitch unshrouded header 14 1 J1 USB Type B Right Angle Type B USB AMP787780 1 Connector 15 1 L1 1uH Inductor RCD MCI 1812 1uH MT 16 1 L2 Ferrite Ferrite Bead Phillips BDS3 3 8 9 4S2 7 1 Q1 fiuetsgos PAP signe transistor SOTAS Motorola MMBT3906LT1 package 18 1 Q2 MMBT2222A NPN transistor SOT 23 pckg
11. MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13A04 Signal Name 2 0V see note 1 P9 D24 COREVDD 3 3V P9 A22 IOVDD A14 see note 2 P6 C20 AB17 A15 see note 2 P6 D20 AB16 A16 see note 2 P6 B24 AB15 A17 see note 2 P6 C24 AB14 A18 see note 2 P6 D23 AB13 A19 see note 2 P6 D22 AB12 A20 see note 2 P6 D19 AB11 A21 see note 2 P6 A19 AB10 A22 see note 2 P6 D28 AB9 A23 see note 2 P6 A28 AB8 A24 see note 2 P6 C27 AB7 A25 see note 2 P6 A26 AB6 A26 see note 2 P6 C26 AB5 A27 see note 2 P6 A25 AB4 A28 see note 2 P6 D26 AB3 A29 see note 2 P6 B25 AB2 A30 see note 2 P6 B19 AB1 A31 see note 2 P6 D17 ABO DO see note 3 P12 A9 D15 D1 see note 3 P12 C9 D14 D2 see note 3 P12 D9 D13 D3 see note 3 P12 A8 D12 D4 see note 3 P12 B8 D11 D5 see note 3 P12 D8 D10 D6 see note 3 P12 B7 D9 D7 see note 3 P12 C7 D8 D8 see note 3 P12 A15 D7 D9 see note 3 P12 C15 D6 Interfacing to the Motorola MPC82x Microprocessor Issue Date 01 10 05 Epson Research and Development Vancouver Design Center Page 17 Table 4 1 List of Connections from MPC821ADS to SIDI3A04 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13A04 Signal Name D10 see note 3 P12 D15 D5 D11 see note 3 P12 A14 D4 D12 see note 3 P12 B14 D3 D13 see note 3 P12 D14 D2 D14 see note 3 P12 B13 D1 D15 see note 3 P12
12. Maximum Number of Colors Shades Max No Of Bo Color Depth bpp Passive Panel TFT Panel pea Dithering On Colors Shades 00000 Reserved 00001 1 bpp 64K 64 64K 64 2 2 00010 2 bpp 64K 64 64K 64 4 4 00011 Reserved 00100 4 bpp 64K 64 64K 64 16 16 00101 00111 Reserved 01000 8 bpp 64K 64 64K 64 256 64 10000 16 bpp 64K 64 64K 64 64K 64 10001 11111 Reserved Power Save Configuration Register REG 14h Default 00000010h Read Write 30 28 PAL 26 17 16 Direct HR TFT GPO Control Power Save Enable 0 bit 7 Vertical Non Display Period Status Read only This is a read only status bit When this bit 0 the LCD panel output is in a Vertical Display Period When this bit 1 the LCD panel output is in a Vertical Non Display Period bit 6 Memory Controller Power Save Status Read only This read only status bit indicates the power save state of the memory controller and must be checked before turning off the MCLK source clock When this bit 0 the memory controller is powered up When this bit 1 the memory controller is powered down and the MCLK source can be turned off Note Memory writes are possible during power save mode because the S1D13A04 dynami cally enables the memory controller for display buffer writes 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 97 Vancouver Design C
13. Figure 3 1 Configuration DIP Switch SW1 Location S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 10 Epson Research and Development Vancouver Design Center The S1D13A04 has seven configuration inputs CONF 6 0 which are read on the rising edge of RESET All S1D13A04 configuration inputs are fully configurable using an eight position DIP switch as described below Table 3 1 Configuration DIP Switch Settings Switch 1D13A04 Value on this pin at rising edge of RESET is used to configure SW1 Signal Closed On 1 Open Off 0 Select host bus interface as follows CNF4 CNF2 CNF1 CNFO Host Bus Interface 1 0 0 0 SH 4 SH 3 interface Big Endian 0 0 0 0 SH 4 SH 3 interface Little Endian 1 0 0 1 MC68K 1 Big Endian 0 0 0 1 Reserved 1 0 1 0 MC68K 2 Big Endian 0 0 1 0 Reserved SW1 5 CNEA 1 0 1 1 Generic 1 Big Endian swi 13 17 CNF 2 0 MI Reserved Generic 2 Little Endian RedCap 2 Big Endian Reserved DragonBall Big Endian Reserved Reserved xo OA OA Be eet oe ee ee oe 220000 20000 Configure GPIO 7 6 and GPIO 4 0 as outputs SW1 4 CNF3 and GPIO5 as an input at power on for use when USB is selected SW1 6 CNF5 WAIT is active high SW1 7 CNF6 CLKI to BCLK Divide ratio 2 1 SW1 8 Disable PCI bridge for non PCI host EA Required settings when used with PCI Bridge FPGA
14. BitBLT Operation BitBLT ration Bits 3 0 it Operatio an Write BitBLT with ROP This operation refers to BitBLTs where data is to be transferred from system memory to display memory re Read BitBLT This operation refers to BitBLTs where data is to be transferred from display memory to system memory do a Move BitBLT in positive direction with ROP This operation is used to transfer data from display memory to display memory de Move BitBLT in negative direction with ROP This operation is used to transfer data from display memory to display memory Transparent Write BitBLT 0100 Like the Write BitBLT this operation is used when transferring data from system memory to display memory the difference is that destination pixels will be left as is when source pixels of a specified color are encountered Transparent Move BitBLT in positive direction 0101 As with the Move BitBLTs this operation is used to transfer data from display memory to display memory The difference is that destination pixels will be left as is when source pixels of a specified color are encountered o Pattern Fill with ROP Fills the specified area of display memory with a repeating pattern stored in display memory Pattern Fill with transparency 0111 As with the Pattern Fill this BitBLT fills a specified area of display memory with a repeating pattern destination pixels will be left as is when source pixels of a specified color are encount
15. Figure 2 1 MCF3307 Memory Read Cycle Figure 2 2 MCF5307 Memory Write Cycle illustrates a typical memory write cycle on the MCF5307 system bus Bco O LJ LJ LI LI LI LI LI TS TA TP A 31 0 X R W SIZ 1 0 TT 1 0 D 31 0 A Valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory Write Cycle 2 1 3 Burst Cycles Burst cycles are very similar to normal cycles except that they occur as a series of four back to back 32 bit memory reads or writes The TIP Transfer In Progress output is asserted continuously through the burst Burst memory cycles are mainly intended to fill Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 010 01 Page 10 Epson Research and Development Vancouver Design Center caches from program or data memory They are typically not used for transfers to or from IO peripheral devices such as the S1D13A04 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not burst capable 2 2 Chip Select Module In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable BWE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Rea
16. S1D13A04 X37A A 001 06 Figure 6 14 Generic STN Panel Timing Revision 6 0 Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Page 59 Vancouver Design Center VT Vertical Total REG 30h bits 9 0 1 lines VPS FPFRAME Pulse Start Position 0 lines because REG 2Ch bits 9 0 0 VPW FPFRAME Pulse Width REG SCh bits 18 16 1 lines VDPS Vertical Display Period Start Position 0 lines because REG 38h bits 9 0 0 VDP Vertical Display Period REG 34h bits 9 0 1 lines HT Horizontal Total REG 20h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 2Ch bits 9 0 1 pixels HPW FPLINE Pulse Width REG 2Ch bits 22 16 1 pixels HDPS Horizontal Display Period Start Position 22 pixels because REG 28h bits 9 0 0 HDP Horizontal Display Period REG 24h bits 6 0 1 x 8 pixels For passive panels the HDP must be a minimum of 32 pixels and must be increased by multiples of 16 HPS must comply with the following formula HPS gt HDP 22 HPS HPW lt HT Panel Type Bits REG OCh bits 1 0 00b STN FPFRAME Pulse Polarity Bit REG 3Ch bit 23 1 active high FPLINE Polarity Bit REG 2Ch bit 23 1 active high MOD is the MOD signal when REG OCh bits 21 16 0 MOD toggles every FPERAME MOD is the MOD signal when REG OCH bits 21 16 n MOD toggles every n FPLINE Hardware Functional
17. ee 142 ON OVERVIEW unta aa dr a oe a eo a a a a Aa 1AZ 9 2 BitBLT Operations 2 a ee 142 10 Frame Rate Calculation 143 11 Display Data Formats lt gt si acon A e de EE e Se 144 12 Look Up Table Architecture 145 12 1 Monochrome Modes s s s e ss os ee ee ee 145 TAZ Golor Modes lt 2 i tl BOERS A a e Bs BE e oe Go ee a ce AA 13 SwivelView n ai a bore Be Dee eR Ee eS eee ees 151 13 1 Concept py ay he By ee ae a OP as a a ee DST 13 2 907 Swivel View M aca ee we A ee ee ee eo DT 13 2 1 Register Programming 0 00 2p eee ee 152 13 3 F8O0 SwivelVaewi M ica Bose Ge ke Sw BO ow a de ee we we we ca SS 13 3 1 Register Programming 2 2 0 00 2 ee ee 153 13 4 207 SwavelView M a sac ai ae oe a a a Re ea oe BO ae hs ve da ee Mas 194 13 4 1 Register Programming 2 2 0 00 ee ee 155 14 Picture in Picture Plus PIP 4 156 TAEL CONCEPT o d arods Sas Boe a A a e a O 14 2 With SwivelView Enabled 0 ee ee LST 14 21 wivel Vie WO aa A a E a pare Saw 157 14 2 2 SwivelView 180 ee 157 14 2 3 Swivel Wiew 2 10 22 8 eS BAM i Bo tt a Ae 158 15 Power Save Mode 2 2 224 44 epee AR eee a ee ee ee ee 159 16 Mechanical Data lt 5 s s s r 2 000 4 AR AA A RA A ee 160 17 Referentes ciar A A
18. Figure 6 30 160x160 Sharp Direct HR TFT Panel Horizontal Timing S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center Table 6 27 160x160 Sharp Direct HR TFT Horizontal Timing Page 77 Symbol Parameter Min Typ Max Units tl FPLINE start position 13 Ts note 1 t2 Horizontal total period 180 220 Ts 13 FPLINE width 2 Ts t4 FPSHIFT period 1 Ts t5 Data setup to FPSHIFT rising edge 0 5 Ts t6 Data hold from FPSHIFT rising edge 0 5 Ts t7 Horizontal display start position 5 Ts t8 Horizontal display period 160 Ts t9 FPLINE rising edge to GPIO3 rising edge 4 Ts t10 GPIO3 pulse width 1 Ts t11 GPIO1 GPIOO pulse width 136 Ts t12 GPIO1 rising edge GPIOO falling edge to FPLINE rise edge 4 Ts t13 GPIO2 toggle edge to FPLINE rise edge 10 Ts 1 Ts pixel clock period 2 ttyp REG 2Ch bits 9 0 1 3 t2typ REG 20h bits 6 0 1 x 8 4 t8typ REG 2Ch bits 22 16 1 5 t7typ REG 28h bits 9 0 5 REG 2Ch bits 9 0 1 6 t8typ REG 24h bits 6 0 1 x 8 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 78 Epson Research and Development Vancouver Design Center
19. 6 1 Overview 6 2 Registers 6 2 1 Power Save Mode Enable 6 2 2 Memory Controller Power Save Status o o 6 3 LCD Power Sequencing 6 4 Enabling Power Save Mode 6 5 Disabling Power Save Mode SWIVeIVIOW ici a a A is 7 1 SwivelView Registers 7 2 Examples 7 3 Limitations 7 3 1 SwivelView 0 and 180 0 00 0000200000004 7 3 2 SwivelView 90 and 270 0 00 00 0 0 0 000008 8 Picture In Picture Plus 0 8 1 Registers 8 2 Picture In Picture Plus Examples 8 2 1 SwivelView 0 Landscape Mode o o 82 24 SWIVEIVIEWDOS o rd a dt de home ean Programming Notes and Examples Issue Date 2002 08 21 Page 3 S1D13A04 X37A G 003 05 Page 4 Epson Research and Development Vancouver Design Center 8 2 3 SwivelView 180 ii a cnet Weta A og r a ee Bee dk Sw oh eae hs 51 8 2 4 SWIvElViEW2 70 ar e a AA Ree A 54 8 3 Limitations A do oh ho Ok od aa bd 57 8 3 1 SwivelView O and 180 qao done i ee 57 8 3 2 SwivelView 90 and 270 norae ie ee ee 57 9 2D BUBLT Engine 0 16 58 as aa a Be a e a a E 58 9 1 Registers 58 9 2 BitBLT ein kag grusu niue Ll a 66 9 2 1 Write BitBLT with ROP o 00 2 0 00000000 67 92 2 Color Expansion BitBLT sess 2 4 arse a ee ae ae A Se ae 70 9 2 3 Color Expansion BitBLT With Transparency 04 74 9 2 4 Solid Fil BitBLT
20. ooa 86 S1D13A04 Internal Clock Requirements o o 88 S1D13A04 Register Mapping e 89 SIDI3A04 Register Set 2 0 e coronas e ee ee ee a 89 MCLK Divide Selecti0M ee 92 PEEK Divide Select o a da be ees 92 PCLK Source Selection oei rande ef Pe Ee Bee bee ee eee aa 93 Panel Data Width Selection 2 2 2 0 00 0000 000202 2 eee 93 Active Panel Resolution Selection 2 2 o o e 94 LCD Panel Type Selection e cei s e eao unni a i ea Ea e i E a a E E A 94 SwivelViewTM Mode Select Options o oo e 95 LCD Bit per pixel Selection 2 2 ee E 96 32 bit Address Increments for Color Depth o ooo o 106 32 bit Address Increments for Color Depth o o o 107 32 bit Address Increments for Color Depth o o o 108 32 bit Address Increments for Color Depth o oo o 109 PWM Clock Divide Select Options o o e o 114 PWMCLK Source Selection e 115 PWMOUT Duty Cycle Select Options o o o e 115 BitBLT FIFO Words Available o 136 BitBLT ROP Code Color Expansion Function Selection o 137 BitBLT Operation Selection o e 138 BitBLT Source Start Address Selection o oo o 139 Power Save Mode Function Summary 0 2 00000000004 159 Hardware Functional Specification
21. ee 114 4 8 16 Bit Per Pixel Display Data Memory Organization 144 1 Bit per pixel Monochrome Mode Data Output Path 145 2 Bit per pixel Monochrome Mode Data Output Path 145 4 Bit per pixel Monochrome Mode Data Output Path 146 8 Bit per pixel Monochrome Mode Data Output Path 146 1 Bit Per Pixel Color Mode Data Output Path o o 147 2 Bit Per Pixel Color Mode Data Output Path o o 148 4 Bit Per Pixel Color Mode Data Output Path o 149 8 Bit per pixel Color Mode Data Output Path o a 150 Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView 152 Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 153 Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView 154 Picture in Picture Plus with SwivelView disabled 156 Picture in Picture Plus with SwivelView 90 enabled 157 Picture in Picture Plus with SwivelView 180 enabled 157 Picture in Picture Plus with SwivelView 270 enabled 158 Mechanical Data PFBGA 121 pin Package o o e 160 Mechanical Data TQFP15 128 pin Package o o 161 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development
22. 0000002020000 74 9 2 5 Move BitBLT in a Positive Direction with ROP 76 9 2 6 Move BitBLT in Negative Direction with ROP 78 9 2 7 Transparent Write BitBLT 2 2 ee ee 79 9 2 8 Transparent Move BitBLT in Positive Direction 82 9 2 9 Pattern Fill BitBLT with ROP o o e e e 84 9 2 10 Pattern Fill BitBLT with Transparency o o e 86 9 2 11 Move BitBLT with Color Expansion e e 88 9 2 12 Transparent Move BitBLT with Color Expansion 89 9 2 13 Read iBUBLD ie i E A A A OO ek a ee e R 89 9 3 S1D13A04 BitBLT Synchronization 92 9 4 S1D13A04 BitBLT Known Limitations 93 9 5 Sample Code 93 10 Programming the USB Controller lt lt 94 10 1 Registers and Interrupts i ha A oh ae AA 94 10 1 1 R gisters n 2 eer dt Be AE SL Se Ph wo ee ed 94 10 112 Interrupts gave ai ke Me a as A Ae eg Bran Be eat BE Roe ede ae 95 10 2 Initialization ur AOA fer SA OP ate fer RA Bok 95 10 231 GPIO Setups 0 earen cece heels Rae bk ee Se Se ta a eee Se 95 10 22 USB Registers snc ee A ee Be oe ee a ed ee ae ee 96 10 3 Data Transfers fad Br ten 97 10 3 1 Receiving Data from the Host the OUT command 97 10 3 2 Sending Data to the Host the IN command 101 10 4 Known Issues 106 10 4 1 EP4 NAK Status not set ova in USB Status Regio P
23. 1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 13 Vancouver Design Center 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 1 Host Bus Interface which is most suitable for direct connection to the Motorola MPC82x microprocessor Generic 1 supports a Chip Select and an individual Read Enable Write Enable for each byte The Generic 1 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13A04 configuration see Section 4 3 S1D13A04 Hardware Configuration on page 18 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping 1D13A04 Pin Names Motorola MPC82x AB 17 0 A 14 31 DB 15 0 D 0 15 WE1 WEO CS CS4 M R A13 CLKI SYSCLK BS Connect to lOypp from the S1D13A04 RD WR OE see note RD OE see note WEO WET WAIT TA RESET System RESET Note The Motorola MPC82x chip select module only handles 16 bit read cycles As the S1D13A04 uses the chip select module to generate CS only 16 bit read cycles are pos sible and both the high and low byte enables can be driven by the MPC82x sign
24. Due to truncation the dimensions of the PIP window may have changed Recalculate the PIP window width and height below PIP Width REG 58h bits 25 16 REG 58h bits 9 0 1 x 32 bpp 1Dh OAh 1 x 32 4 160 pixels PIP Height REG 5Ch bits 25 16 REG 5Ch bits 9 0 1 B3h 3Ch 1 120 lines 3 Determine the PIP display start address The main window image must take up 320 x 240 pixels x bpp 8 9600h bytes If the main window starts at address Oh the PIP window can start at 9600h PIP display start address desired byte address 4 9600h 4 2580h Program the PIP Display Start Address register REG 50h is set to 00002580h 4 Determine the PIP line address offset number of dwords per line image width 32 bpp 160 32 4 20 14h Program the PIP Line Address Offset register REG 54h is set to 00000014h 5 Enable the PIP window Program the PIP Window Enable bit REG 10h bit 19 is set to 1 Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 48 8 2 2 SwivelView 90 Epson Research and Development Vancouver Design Center 90 SwivelView PIP window x end position REG 58h bits 25 16 el PIP window main window panel s origin PIP window x start position REG 58h bits 9 0 PIP window y start position REG 5Ch bits 9 0 PIP window y end po
25. e Epson Research and Development Website www erd epson com Connecting to the Sharp HR TFT Panels 1D13A04 Issue Date 01 10 12 X37A G 011 01 Page 20 6 Sales amp Technical Support 6 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk 6 2 Sharp HR TFT Panel North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de http www sharpmeg com S1D13A04 X37A G 011 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Connecting to the Sharp HR TFT Panels Issue Date 01 10 12 EPSON 1D13A04 LCD USB Com
26. x x BytesPerPixel 10 x 320 x 2 100 x 2 6600 19C8h DestinationAddress Y x ScreenStride X x BytesPerPixel 20 x 320 x 2 200 x 2 13200 3390h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride Display WidthInPixels x BytesPerPixel 640 for 16 bpp Program the BitBLT Source Start Address Register REG 800Ch is set to 19C8h Program the BitBLT Destination Start Address Register REG 8010h is set to 3390h 2 Program the BitBLT Width Register to 9 1 REG 8018h is set to 08h 3 Program the BitBLT Height Register to 101 1 REG 801Ch is set to 64h 100 deci mal 4 Program the BitBLT Operation Register to select the Transparent Move BitBLT in Positive Direction REG 8008h bits 3 0 are set to 05h 5 Program the BitBLT Background Color Register to select blue as the transparent col or REG 8020h is set to 001Fh Full intensity blue in 16 bpp is 001Fh 6 Program the BitBLT Color Format Register to select 16 bpp operations REG 8000h bit 18 is set to 1 7 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 140h REG 8014h is set to 0140h 8 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit O is set to 1 Note The order of register se
27. Cnt gt 0 Copy byte from FIFO to local memory pLocMem REG 4020h Point to next local memory pLocMem Reduce Count Count with a NAK Transfer Done Remaining 0 Since the transfer is over l 3 Yes there is no need for OUT packets to interrupt the local CPU anymore this is optional See 2 5 3 Disable EP3 Interrupt EP3 Interrupt Status REG 4002h amp 08h bit set by NAKs Figure 10 2 Endpoint 3 Data Reception 1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 101 Vancouver Design Center 10 3 2 Sending Data to the Host the IN command Data transfers to the host controller occur when the host issues an IN command The data comes from EndPoint 2 the mailbox or EndPoint 4 the FIFO The data transfer is handled automatically by the S1D13A04 and requires no CPU assistance Data transfers from the S1D13A04 to the host controller are performed by writing the data into either EndPoint 2 mailbox or EndPoint 4 FIFO data registers After writing the data to the registers a control bit indicating that mailbox or FIFO data is valid is set Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 102 Epson Research and Development Vancouver Design Center Endpoint 2 Mailbox Transmit Figure 10 3 shows the logical flow for sen
28. FPSHIFT t12 t13 t FPDAT 7 0 y 2 X Figure 6 24 Single Color 8 Bit Panel A C Timing Format 2 Table 6 24 Single Color 8 Bit Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 2 Ts t9 FPSHIFT period 2 Ts t10 FPSHIFT pulse width low 1 Ts t11 FPSHIFT pulse width high 1 Ts t12 FPDAT 7 0 setup to FPSHIFT falling edge 1 Ts t13 FPDAT 7 0 hold to FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 t2min 13min HPS t4min 4 tBmin HT 5 t4min HPW 6 min HPS 1 7 min HPS HDP HDPS 1 if negative add t3 min 8 tl4min HDPS HPS t4 min if negative add t3 min Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 70 6 4 7 Single Color 16 Bit Panel Timing Epson Research and Development Vancouver Design Center
29. Page 16 Epson Research and Development Vancouver Design Center Oscillator SH 4 BUS y a a ABO x 12 bit vss 3 EPDAT15 p11 ET A 25 18 Decoder M R FPDAT12 m9 D10 Display CSn CS FPDAT 9 0 31 D 9 0 gt AME A 17 1 gt ABLI7A FPFRAME FPFR FPLINE FPLINE gt D 15 0 l gt DB 15 0 2 NEO eog FPSHIFT FPSHIFT DRDY DRDY 3 WE1 gt WE1 a BS gt BS S1 D1 3A04 j RD WR gt RD WR GPIOO RD gt RD RDY l4 WAIT CKIO gt CLKI RESET gt RESET Figure 3 3 Typical System Diagram Hitachi SH 4 Bus Oscillator SH 3 BUS y Alps ABO N R L S 18 bit vss A 25 18 Decoder gt MIRE FPDAT 17 0 p p t7 0 TFT CSni CS FPFRAME FPFRAME Display A 17 1 gt AB 17 1 FPLINE FPLINE 5 D 15 0 La gt DB 15 0 FPSHIFT FPSHIFT WEO gt WEO Baby 2 WE1 gt WE1 gt DRDY 5 BS gt BS S1 D1 3A04 RD WR gt RD WR GPIOO RD gt RD WAIT La WAIT CKIO gt CLKI RESET gt RESET Figure 3 4 Typical System Diagram Hitachi SH 3 Bus S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 17 Vancouver Design Center
30. Release Number bits 15 8 7 6 5 4 3 2 1 0 Release Number LSB REG 403Ah Index 05h Default 00h Read Write Release Number bits 7 0 7 6 5 4 3 2 1 0 bits 15 0 Release Number Bits 15 0 These registers determine the device release number returned in a Get Device Descriptor request Receive FIFO Almost Full Threshold REG 403Ah Index 06h Default 3Ch Read Write n a Receive FIFO Almost Full Threshold bits 5 0 7 6 3 2 bits 5 0 Receive FIFO Almost Full Threshold Bits 5 0 This register determines the threshold at which the receive FIFO almost full status bit is set Note The Receive FIFO Almost Full threshold must be set less than 64 as the FIFO count must rise above the threshold to cause an interrupt Transmit FIFO Almost Empty Threshold REG 403Ah Index 07h Default 04h Read Write Transmit FIFO Almost Empty Threshold bits 5 0 bits 5 0 Transmit FIFO Almost Empty Threshold Bits 5 0 This register determines the threshold at which the transmit FIFO almost empty status bit is set Note The Transmit FIFO Almost Empty threshold must be set greater than zero as the FIFO count must drop below the threshold to cause an interrupt Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 128 Epson Research and Development Vancouver Design Center USB Control REG 403Ah Index 08h Default 01h Read Write USB String na Enable 7 6 5 4 3 2 1 0 bit O
31. S1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 21 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Support or www erd epson com Interfacing to the Motorola MPC82x Microprocessor S1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 22 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM available on the Internet at http www mot com SPS ADC pps _subpgs _documentation 821 821UM html Epson Research and Development Inc D13A04 Hardware Functional Specification Document Number X37A A 001 xx Epson Research and Development Inc SSU 3A04BO0C Rev 1 0 Evaluation Board User Manual Document Number X37A G 004 xx Epson Research and Developme
32. Table 6 24 Single Color 8 Bit Panel A C Timing Format 2 0 Table 6 25 Single Color 16 Bit Panel A C Timing Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Page 7 1D13A04 X37A A 001 06 Page 8 Table 6 26 Table 6 27 Table 6 28 Table 6 29 Table 6 30 Table 6 31 Table 7 1 Table 7 2 Table 7 3 Table 7 4 Table 7 5 Table 7 6 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 8 5 Table 8 6 Table 8 7 Table 8 8 Table 8 9 Table 8 10 Table 8 11 Table 8 12 Table 8 13 Table 8 14 Table 8 15 Table 8 16 Table 8 17 Table 8 18 Table 8 19 Table 8 20 Table 8 21 Table 15 1 1D13A04 X37A A 001 06 Revision 6 0 Epson Research and Development Vancouver Design Center TET ACC MO st vs Yn cea Vind Sb eee eee bo o ee ad 75 160x160 Sharp Direct HR TFT Horizontal Timing 77 160x160 Sharp Direct HR TFT Panel Vertical Timing 79 320x240 Sharp Direct HR TFT Panel Horizontal Timing 81 320x240 Sharp Direct HR TFT Panel Vertical Timing 81 USB Interface Timing s g xis pnt eee eae de es Bg eed dae Gone a eee 83 BCLK Clock Selections bicho ot de Seok bo ae tok See oh 84 MCEK Clock Selection 2 2 ee ee 84 PGLK Clock Selection ocios e ereas bd Mea et oe ee ee a 85 Relationship between MCLK and PCLK oo o 86 PWMCLK Clock Selection
33. The source and the destination areas of the BitBLT may be either rectangular or linear Performing a rectangular to rectangular Move BitBLT creates an exact copy of one portion of video memory at the second location Selecting a rectangular source to linear destination would be used to compactly store an area of displayed video memory into non displayed video memory Later the area could be restored by performing a linear source to rectan gular destination Move BitBLT The Move BitBLT in a Positive Direction with ROP is a self completing operation Once the width height and the source and destination start addresses are setup and the BitBLT is started the BitBLT engine will complete the operation automatically Should the source and destination areas overlap a decision has to be made as to whether to use a Positive or Negative direction so that source data is not overwritten by the move before it is used Refer to Figure 9 1 to see when to make the decision to switch to the Move BitBLT in a Negative direction When the destination area overlaps the original source area and the destination address is greater then the source address use the Move BitBLT in Negative Direction with ROP D S S D Destination Address less than Source Address Destination Address greater than Source Address Use Move BitBLT in Positive Direction Use Move BitBLT in Negative Direction 1D13A04 X37A G 003 05
34. This bit must be set to 1 to enable the USB interface and USB registers See the S D13A04 Programming Notes and Examples document number X37 A G 003 xx for further infor mation on this bit Interrupt Control Enable Register 0 REG 4046h Default 00h Read Write me AAA a These bits enable interrupts from the corresponding bit of the Interrupt Control Status Clear Register 0 0 corresponding interrupt bit disabled masked 1 corresponding interrupt bit enabled Interrupt Control Enable Register 1 REG 4048h Default 00h Read Write se om aE These bits enable interrupts from the corresponding bit of the Interrupt Control Status Clear Register 1 0 corresponding interrupt bit disabled masked 1 corresponding interrupt bit enabled Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 132 Epson Research and Development Vancouver Design Center Interrupt Control Status Clear Register 0 REG 404Ah Default 00h Read Write n a 15 14 13 12 11 10 9 8 n a cd Reserved Reserved Reserved Reserved USBRESET Reserved Connected 7 6 5 4 3 2 1 0 On reads these bits represent the interrupt status for interrupts caused by low to high transitions on the corresponding signals 0 read no low to high event detected on the corresponding signal 1 read low to high event detected on the corresponding signal On writes these bits clear the corresponding interru
35. This register has multiple meanings depending on the BitBLT operation it specifies It can be either e the start address in display memory of the source data for BitBLTs where the source is display memory i e Move BitBLTs e in pattern fill operations the BitBLT Source Start Address determines where in the pattern to begin the BitBLT operation and is defined by the following equation Value programmed to the Source Start Address Register Pattern Base Address Pattern Line Offset Pixel Offset e the data alignment for 16 bpp BitBLTs where the source of BitBLT data is the CPU i e Write BitBLTs The following table shows how Source Start Address Register is defined for 8 and 16 bpp color depths Table 9 4 BitBLT Source Start Address Selection Color Format Pattern Base Address 20 0 Pattern Line Offset 2 0 Pixel Offset 3 0 BitBLT Source Start BitBLT Source Start 8 bpp BitBLT Source Start Address 20 6 Address 5 3 Address 2 0 BitBLT Source Start BitBLT Source Start 16 bpp BitBLT Source Start Address 20 7 Address 6 4 Address 3 0 BitBLT Destination Start Address Register REG 8010h Default 00000000h Read Write BitBLT Destination Start Address bits 20 16 22 21 20 19 18 17 16 BitBLT Destination Start Address bits 15 0 8 7 6 4 3 2 0 BitBLT Destination Start Address This register specifies the initial destination address for BitBLT operations For rectangu lar destinations t
36. e 10 3 2 Host Bus Interface Signals tile A A BOW a cra A 4 VR4102 VR4111 to S1D13A04 Interface o 12 4 1 Hardware Description Dd 3 a ad ar peat een LZ 4 2 S1D13A04 Hardware Configuration ED bs io aS rs LS 4 3 NEC VR4102 VR4111 Configuration 2 2 e 14 5 Software iins A A A E at ee ee 15 Referentes caras aa a a da add la a 16 6 1 DOCUMENTS otra a o ar e Ae a ar tn ete a he e N 6 2 Document Sources e 16 7 Sales and Technical Support 17 7 1 EPSON LCD USB Companion Chips SID13A04 17 7 2 NEC Electronics IMC 2 6 a 4a e er a a a e TY Interfacing to the NEC VR4102 VR4111 Microprocessors S1D13A04 Issue Date 01 10 12 X37A G 007 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the NEC VR4102 VR4111 Microprocessors X37A G 007 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 2 000002 ee eee 10 Table 4 1 Summary of Power On Reset Options 2 o e e e 13 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles o 9 Figure 4 1 Typical Implementation of VR4102 VR4111 to S1D13A04 Interface 12 Interfacing to the NEC VR4102 VR4111 Microprocessors S1D13A0
37. 1 16 bpp 64K color format is selected bit 17 BitBLT Destination Linear Select When this bit 1 the Destination BitBLT is stored as a contiguous linear block of memory When this bit 0 the Destination BitBLT is stored as a rectangular region of memory The BitBLT Memory Address Offset register REG 8014h determines the address offset from the start of one line to the next line bit 16 BitBLT Source Linear Select When this bit 1 the Source BitBLT is stored as a contiguous linear block of memory When this bit 0 the Source BitBLT is stored as a rectangular region of memory The BitBLT Memory Address Offset register REG 8014h determines the address offset from the start of one line to the next line bit 0 BitBLT Enable This bit is write only Setting this bit to 1 begins the 2D BitBLT operation This bit must not be set to 0 while a BitBLT operation is in progress Note To determine the status of a BitBLT operation use the BitBLT Busy Status bit REG 8004h bit 0 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 136 Epson Research and Development Vancouver Design Center BitBLT Status Register aladas Default 00000000h Read Only Number of Used FIFO Entries Number of Free FIFO Entries 0 means full 22 18 17 16 FO BitBLT Full Busy Status Status 0 bits 28 24 Number of Used FIFO Entries Bits 4 0 These bits indicate the minimum number of FIFO e
38. 1 Start Bit Position 1 BitBLT Width 2 The following bits are expanded Word Sent To BitBLT Engine 15 8 7 0 High Byte Low Byte 4 To expand bits 0 15 14 of the word Source Address 0 Start Bit Position 0 BitBLT Width 3 The following bits are expanded Word Sent To BitBLT Engine 15 8 7 0 7 0 7 0 High Byte Low Byte All subsequent WORDS in one BitBLT line are then serially expanded starting at bit 7 of the low byte until the end of the BitBLT line All unused bits in the last WORD are discarded It is extremely important that the exact number of WORDS is provided to the BitBLT engine The number of WORDS is calculated from the following formula This formula is valid for all color depths 8 16 bpp WORDS Sx MOD 16 BitBLTWidth 15 16 x BitBLTHeight where Sx is the X coordinate of the starting pixel in a word aligned monochrome bitmap Monochrome Bitmap Byte 1 Byte 2 Sx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 72 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center Example 10 Color expand a rectangle of 12 x 18 starting at the coordinates Sx 125 Sy 17 using a 320x240 display at a color depth of 8 bpp This example assumes a
39. 2 14 5 SoftWare a eo ae a a ew ee ea a ee ee ee ee A 15 Helerences aa aa hae DAA Aa la G 16 6 1 DOCUMENTS ws ve Ae eae a ee A rt A ne ee ie HG 6 2 Document Sources o 16 7 Sales and Technical Support 17 7 1 EPSON LCD USB Companion Chips SID13A04 2 2 2 2 2 0T7 7 2 Toshiba MIPS TMPR3905 12 Processor a ee ee 17 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13A04 Issue Date 01 10 12 X37A G 002 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X37A G 002 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 000022 ee eee 10 Table 4 1 Summary of Power On Reset Options 0 002 000 00202 eee 14 List of Figures Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle 00 9 Figure 2 2 Toshiba 3905 12 PC Card IO Cycle 2 2 ee 9 Figure 4 1 S1D13A04 to TMPR3905 12 Direct Connection o e 12 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13A04 Issue Date 01 10 12 X37A G 002 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessor
40. MCLK 4 1 The S1D13A04 has Power Save Mode enabled but the clocks CLKI CLKI2 and USBCLK remain active unless specified otherwise 2 CLKI CLKI2 and USBCLK are grounded for the Clocks Removed condition 1D13A04 X37A G 006 01 Power Consumption Issue Date 01 10 29 Epson Research and Development Page 5 Vancouver Design Center The following table provides an example of some 160x160 panels and the effects on power consumption of specific environments The following conditions apply e All tests had an appropriate LCD panel connected to the LCD outputs of the S1D13A04 e All tests were run with a static full color palette display except the test where the 2D BitBLT engine was running e All tests were done using the Generic 1 host bus interface BCLK 33MHz Table 1 2 SIDI3A04 Total Power Consumption for 160x160 panels e Power Consumption mA Test Condition S1D13A04 All COREVpp 2 0V and lOVpp 3 3V Active Power Save Mode Panel Frame Color 1 1 Clocks Resolution Type Rate Clocks MHz Depth CORE IO CORE IO pemoved2 67 CLKI 33 3 MCLK BCLK 4 2 5 0 9 2 2 0 2 0 1 67 CLKI2 3 PCLK 8 2 6 1 1 2 2 0 2 0 1 18 bit 67 USBCLK 48 16 2 8 1 1 2 2 0 2 0 1 MAATEL CLKI 33 3 MCLK BCLK 67 CLKI2 3 PCLK 16 2 6 1 0 4 2 0 1 0 1 160x160 USBCLK grounded 18 bit CLKI 33 3 MCLK BCLK HA TFT 67 CLKI2 3 PCLK 16 12 3 2 4 a
41. Pixel 1 bits 3 0 Programming Notes and Examples Issue Date 2002 08 21 Figure 4 3 Pixel Storage for 4 Bpp in One Byte of Display Buffer At a color depth of 4 bpp each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to 1 Four bit pixels provide 16 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first 16 elements of the green component of the Look Up Table LUT For color panels the 16 colors are derived by indexing into the first 16 positions of the LUT 1D13A04 X37A G 003 05 Page 16 Epson Research and Development Vancouver Design Center 4 5 Memory Organization for 8 Bpp 256 Colors 64 Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 bits 7 0 Figure 4 4 Pixel Storage for 8 Bpp in One Byte of Display Buffer At a color depth of 8 bpp each byte of display buffer represents one pixel on the display At this color depth the read modify write cycles are eliminated making the update of each pixel faster Each byte indexes into one of the 256 positions of the LUT The S1D13A04 LUT supports six bits per primary color This translates into 256K possible colors when color mode is selected Therefore the display has 256 colors available out of a possible
42. The latest software drivers and documentation for the 1D13A04 is available at this website Update Common Controls About 13A04CFG 13A04CFG uses some of the latest common control DLLs On systems using earlier versions of the common controls certain controls may not appear correctly This option updates the Common Controls required for proper operation of 13A04CFG Selecting the About 13A04CFG option from the Help menu displays the about dialog box for 13A04CFG The about dialog box contains version information and the copyright notice for 13A04CFG 13A04CFG Configuration Program S1D13A04 Issue Date 01 10 19 X37A B 001 01 Page 28 Comments 1D13A04 X37A B 001 01 Epson Research and Development Vancouver Design Center On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13A04 i e Selecting TFT or STN on the Panel tab enables disables options specific to the panel type The file panels def is a text file containing operational specifications for several supported and tested panels This file can be edited with any text editor 13A04CFG allows manually altering register values The manual changes may violate memory and LCD timings as specified in the S1D 3A04 Hardware Functional Specifi cation document number X37A A 001 xx If this is done unpredictable results may occur Epson Research and Development Inc does not assume liability
43. VDP Vertical Display Period REG 34h bits 9 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 30h bits 9 0 REG 34h bits 9 0 Lines HDP Horizontal Display Period REG 24h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 20h bits 6 0 1 x 8Ts REG 24h bits 6 0 1 x 8Ts 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 67 Vancouver Design Center Sync Timing y ti t2 FPFRAME t4 e t3 FPLINE l Data Timing FPLINE ja t6a t6b t8 t9 t7a t14 t11 t10 gt 4 gt FPSHIFT p t7b gt FPSHIFT2 e 112 113 112113 FPDAT 7 0 TK X Figure 6 22 Single Color 8 Bit Panel A C Timing Format 1 Table 6 23 Single Color 8 Bit Panel A C Timing Format 1 Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t6a FPSHIFT falling edge to FPLINE rising edge note 6 Ts t6b FPSHIFT2 falling edge to FPLINE rising edge note 7 Ts t a FPSHIFT falling edge to FPLINE falling edge t6a t4 Ts t7b FPSHIFT2 falling edge to FPLINE falling edge t6b t4 Ts t8 FPLINE falling edge to FPSHIFT rising FPSHIF
44. cessor The NEC VR4181A microprocessor is specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the NEC VR4181A Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 008 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4181A 2 1 The NEC VR4181A System Bus 2 1 1 Overview S1D13A04 X37A G 008 01 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4181A offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4181A is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 100MHz VR4110 CPU core which supports the MIPS III and MIPS16 instruction sets The CPU communicates with external devices via an ISA interfac
45. ss hre ae ee 27 About TIADACEG oe s nc eb ee es es Be de we pe Pe 27 Comments ts 4 i de a e te Ate bee ch AD ek Sete Be Ae ek Hee te 4228 13A04CFG Configuration Program 1D13A04 Issue Date 01 10 19 X37A B 001 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Page 5 Vancouver Design Center 13A04CFG 13A04CFG is an interactive Windows program that calculates register values for a user defined S1D13A04 configuration The configuration information can be used to directly alter the operating characteristics of the S1D13A04 utilities or any program built with the Hardware Abstraction Layer HAL library Alternatively the configuration information can be saved in a variety of text file formats for use in other applications S1D13A04 Supported Evaluation Platforms 13A04CFG runs on PC system running Windows 9x ME NT 2000 and can modify Win32 exe files and s9 format files Installation Create a directory for 13A 04cfg exe and copy the files 13A 04cfg exe and panels def to that directory Panels def contains configuration information for a number of panels and must reside in the same directory as 13A 04cfg exe Usage To start 13A04CFG from the Windows desktop click on the My Computer icon and run the program 13a04cfg exe from the installed directory To start 13A04CFG from a Windows c
46. 1 9600h 80 x 120 1 160 x 4 8 4 160 x 4 8 amp 03h 4 1 11999 2EDFh Program the PIP Display Start Address register REG 50h is set to 00002EDFh 3 Determine the PIP line address offset number of dwords per line image width 32 bpp 160 32 4 20 14h Program the PIP Line Address Offset register REG 54h is set to 00000014h 4 Enable the PIP window Program the PIP Window Enable bit REG 10h bit 19 is set to 1 Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 54 Epson Research and Development Vancouver Design Center 8 2 4 SwivelView 270 270 SwivelView e main window PIP window y end position REG 5Ch bits 25 16 A PIP window y start position REG 5Ch bits 9 0 PIP window PIP window x start position in REG 58h bits 9 0 ee PIP window x end position REG 58h bits 25 16 panel s origin Figure 8 5 Picture in Picture Plus with SwivelView 270 enabled SwivelView 270 is a mode in which both the main and PIP windows are rotated 270 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address O and followed by the PIP window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be
47. 1 Big Endian 0 0 0 1 Reserved 1 0 1 0 MC68K 2 Big Endian 0 0 1 0 Reserved CNF4 CNF 2 0 1 0 1 1 Generic 1 Big Endian 0 0 1 1 Generic 1 Little Endian 1 1 0 0 Reserved 0 1 0 0 Generic 2 Little Endian 1 1 0 1 REDCAP2 Big Endian 0 1 0 1 Reserved 1 1 1 0 DragonBall MC68EZ328 MC68VZ328 Big Endian 0 1 1 0 Reserved Xx 1 1 1 Reserved CNF3 Reserved Must be set to 1 ONES WAIT is active high WAIT is active low see note CNF6 CLKI to BCLK divide ratio 2 1 CLKI to BCLK divide ratio 1 1 Note If CNF5 1 the WAIT pin should be tied low using a pull down resistor If CNF5 0 the WAIT pin should be tied high using a pull up resistor If WAIT is not used this pin should be tied either high or low using a pull up or pull down resistor S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center 4 5 Host Bus Interface Pin Mapping Table 4 8 Host Bus Interface Pin Mapping Page 31 to Vos 2 Tf the target MC68K bus is 32 bit then these signals should be connected to D 31 16 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Motorola S1D13A04 Generic 1 Generic 2 Hitachi Motorola Motorola Motorola MC68EZ328 Pin Name SH 3 SH 4 MC68K 1 MC68K 2 REDCAP2 MC68VZ328 DragonBall AB 17 1 A 17 1 A 17 1 A 17 1 A 17 1 A 17 1 A
48. 150kQ USBDETECT VBus m USBPUP Full Speed Device LVDD 1 5kQ e USBDP e b A gt DP A USBDM we gt DM A n 4 NNCD5 6LG de Overvoltage E ae Protection ESD Protection VSS GND Figure 3 9 USB Typical Implementation Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 20 Epson Research and Development Vancouver Design Center 4 Pins 4 1 Pinout Diagram PFBGA 121 pin L 0600000000090 K 00000000000 mm 0600000000009 H 0606000000000 0600000000000 MM 060000000000 E RO E E E ee D 0600000000090 c 0600000000090 B EE 00000000000 Y 0600000000000 1 2 3 4 5 6 7 8 9 10 11 BOTTOM VIEW Figure 4 1 Pinout Diagram PFBGA 121 pin Table 4 1 PFBGA 121 pin Mapping L NC IOVDD DB7 DB3 DBO GPIO7 GPIO3 GPIOO IOVDD COREVDD NC K NC vss DB8 DB4 DBI GPIO6 GPIO2 IRQ DRDY vss NC J NC DB9 DB6 DB5 DB2 NC GPIO1 USBCLK FPFRAME COREVDD NC H DB12 DBt1 DB10 DB13 NC IOVDD GPIO4 NC FPLINE FPSHIFT FPDATO G WAIT DB15 DB14 IOVDD VSS GPIOS FPDAT5 FPDAT1 FPDAT2 FPDAT3 FPDAT4 F RESET VSS RD WR WE1 CLKI NC FPDAT8 FPDAT6 VSS FPDAT7 IOVDD E RDA BS M R CS WEO AB13 TESTEN FPDAT9 FPDAT12 FPDAT11 FPDAT10 D ABO ABI AB2 AB8 AB12 AB17 CNF3 FPDAT13 FPDAT16 FPDAT15 FPDAT14 Cc NC COREVDD AB3 AB6 AB9 AB16 CNF2 CNF5 CNF6 FPDAT17 NC B N
49. Connecting to the Sharp HR TFT Panels Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 Digital Analog Power Supplies The digital power supply VSHD must be connected to a 3 3V supply The analog power supply VSHA must be connected to a 5 0V supply 2 1 3 DC Gate Driver Power Supplies The gate driver high level power supply Vpp and the gate driver logic low power supply Vss have typical values of 15V and 15V respectively These power supplies can be provided by a Linear Technology high efficiency switching regulator LT1172 The two power supplies can be adjusted through their allowable ranges using the potentiometer VRI The gate driver logic high power supply Vcc is defined as Vgg VSHD The typical Voc voltage of 11 7V can be supplied from Vgs using a 3 3V zener diode which provides the necessary voltage change Figure 2 2 Panel Gate Driver DC Power Supplies shows the schematic for Vss Vpp and Vcc roa a aang ie x i i E T 24 gt veomp R2 Tr ae HH ns E Y scHoTtky C4 Y Hb i Figure 2 2 Panel Gate Driver DC Power Supplies Connecting to the Sharp HR TFT Panels 1D13A04 Issue Date 01 10 12 X37A G 011 01 Page 10 Epson Research and Development Vancouver Design Center 2 1 4 AC Gate Driver Power Supplies 1D13A04 X37A G 011 01 The gate drive low level power supply Ve is an AC power suppl
50. Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Page 65 Vancouver Design Center t1 t2 Sync Timing lt A in FPFRAME p t3 FPLINE i t5 Puan DRDY MOD 3 Data Timing FPLINE t6 t8 t9 A t7 FPSHIFT FPDAT 7 4 Figure 6 20 Single Color 4 Bit Panel A C Timing Table 6 22 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 0 5 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width low 0 5 Ts t11 FPSHIFT pulse width high 0 5 Ts t12 FPDAT 7 4 setup to FPSHIFT falling edge 0 5 Ts t13 FPDAT 7 4 hold to FPSHIFT falling edge 0 5 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 min t3min HPS t4min 4 Bmin HT 5 t4min HPW 6 min HPS 1 7 min HPS HDP HDPS 1 5 if negative add t3 min 8 t4min HDPS HPS 4 min 1 if negative add t3 min Hardware Functional Specification S1D13A04 Issue D
51. Motorola MMBT2222A 19 13 R1 R7 R23 R31 R34 R37 15K 5 1206 Resistor 20 8 R8 R14 R16 330K 5 1206 Resistor 21 6 R15 R17 R18 R32 R33 R38 1K 5 1206 Resistor 22 3 R19 R20 R30 100K 5 1206 Resistor 23 1 R21 470 Ohm 5 1206 Resistor 24 1 R22 200K Pot 200K Trim Pot Bourns 3386W 1 204 25 2 R24 R25 20 Ohm 1 1206 Resistor 26 2 R26 R29 301K 1 1206 Resistor 27 1 R27 1 5K 1 1206 Resistor S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Vancouver Design Center Table 9 1 Parts List Page 25 PEEP Manufacturer Part No ltem Qty Designation Part Value Description Assembly Instructions 28 1 R28 150K 1 1206 Resistor 29 1 R39 100K Pot 100K Trim Pot Bourns 3386W 1 104 30 1 SW1 SW DIP 8 Dip Switch 8 Position 31 1 Sw2 SW DIP 4 DIP switch 4 position Do Not Populate 32 1 U1 S1D13A04F0A 121 pin PFBGA 13A04 LCDC Supplied by Epson R amp D A 5V fixed voltage regulator Linear Technology LT1117CST 33 1 U2 LT1117CST 5 SOT 223 5 34 1 U3 ICD2061A Clock Chip Wide SO 16 pckg Cypress ICD2061A 35 1 U4 74AHC04 Inverter SO 14 package TI74AHCO4 TinyLogic UHS inverter Pere 36 2 U5 U6 NC7SZ04 SOT23 5 package Fairchild NC7SZ04 37 2 U7 U8 Test Socket pn deseo DI Screw Sockets for oscillator input machine socket Positive LCD Bias Power Taiyo Yuden Xentek Positive ae f rs RD 0412 Supply P
52. PWMOUT Duty Cycle Select Options PWMOUT Duty Cycle 7 0 PWMOUT Duty Cycle 00h Always Low 01h High for 1 out of 256 clock periods 02h High for 2 out of 256 clock periods FFh High for 255 out of 256 clock periods Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 116 Epson Research and Development Vancouver Design Center Scratch Pad A Register REG 80h Default not applicable Read Write Scratch Pad A bits 31 24 Sater Pad A T 15 0 bits 31 0 Scratch Pad A Bits 31 0 This register contains general purpose read write bits These bits have no effect on hard ware Note The contents of the Scratch Pad A register defaults to an un defined state after initial power up Any data written to this register remains intact when the S1D13A04 is reset as long as the chip is not powered off Scratch Pad B Register REG 84h Default not applicable Read Write Scratch Pad B bits 31 24 a Pad B 7 15 0 bits 31 0 Scratch Pad B Bits 31 0 This register contains general purpose read write bits These bits have no effect on hard ware Note The contents of the Scratch Pad B register defaults to an un defined state after initial power up Any data written to this register remains intact when the S1D13A04 is reset as long as the chip is not powered off Scratch Pad C Register REG 88h Default not applicable Read Write Scratch Pad C bits 31 24 an Pad C a
53. Ro Gp Gof Go Pp Re Gn O Bp 0 Byte 2 Gy G G B44 B B B By Byte 3 R44 R43 R42 Ry R10 6 5 G44 a 3 Panel Display Host Address Display Buffer Figure 11 1 4 8 16 Bit Per Pixel Display Data Memory Organization Note 1 The Host to Display mapping shown here is for a little endian system 2 For 16 bpp format R Gn B represent the red green and blue color components S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 145 Vancouver Design Center 12 Look Up Table Architecture The following figures are intended to show the display data output path only Note When Video Data Invert is enabled the video data is inverted after the Look Up Table 12 1 Monochrome Modes The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome Mode Green Look Up Table 256x6 6 bit Gray Data 00 o 01 a 1 bit per pixel data unused Look Up Table entries from Display Buffer Figure 12 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Green Look Up Table 256x6 ae co 6 bit Gray Data 02 A 10 03 AA 11 FC FD FE FF unused Look Up Table entries 2 bi
54. WE1 UDS DS EBO UWE WAIT WAIT WAIT pel DTACK DSACK1 N A DTACK RESET RESET RESET RESET RESET RESET RESET _OUT RESET Note 1 AO for these busses is not used internally by the S1D13A04 and should be connected to Vos 2 If the target MC68K bus is 32 bit then these signals should be connected to D 31 16 3 These pins are not used in their corresponding host interface mode Systems are responsible for externally connecting them to Host Interface IO Vpp 1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 X37A G 004 02 Epson Research and Development Vancouver Design Center 4 2 CPU Bus Connector Pin Mapping Table 4 2 CPU Bus Connector H3 Pinout sonnector Comments Pin No 1 Connected to DBO of the S1D13A04 2 Connected to DB1 of the S1D13A04 3 Connected to DB2 of the S1D13A04 4 Connected to DB3 of the S1D13A04 5 Ground 6 Ground 7 Connected to DB4 of the S1D13A04 8 Connected to DB5 of the S1D13A04 9 Connected to DB6 of the S1D13A04 10 Connected to DB7 of the S1D13A04 11 Ground 12 Ground 13 Connected to DB8 of the S1D13A04 14 Connected to DB9 of the S1D13A04 15 Connected to DB10 of the S1D13A04 16 Connected to DB11 of the S1D13A04 17 Ground 18 Ground 19 Connected to DB12 of the S1D13A04 20 Connected to DB13 of the S1D13A04 21 Connected to DB14 of the S1D13A04 22 Connected to DB1
55. and 270 SwivelView the X start position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 10h bit 19 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 108 Epson Research and Development Vancouver Design Center PIP Y Positions Register REG 5Ch Default 00000000h Read Write PIP Y End Position bits 9 0 21 Note l The effect of REG 58h through REG 5Ch takes place only after REG 5Ch is written and at the next vertical non display period 2 For host bus interfaces using little endian CNF4 0 a write to bits 31 24 causes the PIP Window Y End Position to take effect For host bus interfaces using big endian CNF4 1 a write to bits 7 0 causes the PIP Window Y End Position to take effect bits 25 16 PIP Window Y End Position Bits 9 0 These bits determine the Y end position of the PIP window in relation to the origin of the panel Due to the S1D13A04 SwivelView feature the Y end position may not be a vertical position value only true in 0 and 180 Swivel View For further information on defining the value of the Y End Position register see Section 14 Picture in Picture Plus PIP on page 156 The register is also incremented differently bas
56. are connected directly to the TMPR3905 12 address bus Since the TMPR3905 12 has a multiplexed address bus the other address inputs A 17 13 must be generated using an external latch controlled by the address latch enable signal ALE The low data byte on the TMPR3905 12 data bus for 16 bit ports is D 31 24 and connects to the S1D13A04 low data byte D 7 0 The high data byte on the TMPR3905 12 data bus for 16 bit ports is D 23 16 and connects to the S1D13A04 high data byte D 15 0 The hardware engineer must ensure that CNF4 selects the proper endian mode upon reset Chip Select CS is driven by external decoding circuitry to select the S1D13A04 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address line A18 allowing system address A18 to select between memory or register accesses WEI is connected to CARD1CSH and is the high byte enable for both read and write cycles WEO is connected to CARDIOWR the write enable signal and must be driven low when the Toshiba TMPR3905 12 is writing data to the S1D13A04 RD is connected to CARDIORD the read enable signal and must be driven low when the Toshiba TMPR3905 12 is reading data from the 1D13A04 WAIT connects to CARDIWAIT and is a signal which is output from the S1D13A04 to the TMPR3905 12 that indicates when data is ready read cycle or accepted wr
57. bpp 128 32 4 16 10h Program the PIP Line Address Offset register REG 54h is set to 0000001 0h Enable the PIP window Program the PIP Window Enable bit REG 10h bit 19 is set to 1 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 57 Vancouver Design Center 8 3 Limitations 8 3 1 SwivelView 0 and 180 The PIP Line Address Offset register REG 54h requires the PIP window image width to be a multiple of 32 bits per pixel If this formula is not satisfied then the PIP Line Address Offset register must be programmed to the next larger value that satisfies the formula 8 3 2 SwivelView 90 and 270 The PIP Line Address Offset register REG 54h requires the PIP window image width to be a multiple of 32 bits per pixel If this formula is not satisfied then the PIP Line Address Offset register must be programmed to the next larger value that satisfies the formula Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 58 Epson Research and Development Vancouver Design Center 9 2D BitBLT Engine BitBLT is an acronym for Bit Block Transfer The 2D BitBLT Engine in the S1D13A04 is designed to increase the speed of the most common GUI operations by off loading work from the CPU reducing traffic on the system bus and freeing the CPU sooner for other tasks BitBLTs require a destination a place to write the display data M
58. g ravinon E o Fy on bg 3s EX a os 2 35 ano ano Hr ano ano ano 3 ano E ano a 310N38 3 an Noa 32 3 3 5 3 Be I 7 83 mm ri ino Ja og mm z Sn BS r 7 on Bg tor ONS I A EAS p 5 E at 5 es 5 nee R as y pa qe a 6 SS sl z o t 5al AAA 7 ae E Toae 83 8s HH Hr 3 a a d m Figure 10 3 SIDI3A04B00C Schematics 3 of 6 S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Page 29 I 1 1 I 1 Wow Too Be TP HO epn Seq lt a gt a qunywawnoog 2aig Si0p8UU0O ESO O L ASH ODDAPOVELNSS anuj ees a T TS sopauuog 8 asn E 0049 901d sold vole 801d zo1d9 10ld9 ool L 02 See ot moe Loot HOSE 6zu eeu L s01d09 gt sogigaasn nr PYZLOHVL ig w E ONO o somo 00m al lor we JAiHSda eve AQ30 De Ns we AWW Wide mE e SK Lnowma y E ivi TVOH 9Vdd3 Awasio Triads Sh Lvadsa mo vrZLOHyL veo a0 POH onno on a fo YAZ we EAZ eve ZAZ zae IAZ iv H ras w BAL evi ZAL evi ENEE YE IVgdi8 EL IVOda8 ZLIVgda8 EL IVOda8 OLAJ
59. the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 010 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The MCF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section is an overview of the operation of the CPU bus in order to establish interface requirements The MCF5307 microprocessor family uses a synchronous address and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 N
60. type the command line argument Where displays copyright and program version information 13A04PLAY Diagnostic Utility Issue Date 01 10 05 Epson Research and Development Page 5 Vancouver Design Center Commands 13A04PLAY Diagnostic Utility Issue Date 01 10 05 The following commands are intended to be used from within the 13A04PLAY program However simple commands can also be executed from the command line e g 13A04play f 0 14000 AB q Note If the host platform is big endian reading writing words and dwords to from the regis ters and display buffer may be incorrect It may be necessary for the user to manually swap the bytes in order to perform the IO correctly For further information on little big endian and the S1D13A04 byte word swapping capabilities see the S D 3A04 Hard ware Functional Specification document number X37A A 001 xx CLKI freq Sets the frequency of CLKI Where freq The desired frequency for CLKI in MHz CLKI2 freq Sets the frequency of CLKI2 Where freq The desired frequency for CLKI2 in MHz D SI16132 startaddr endaddrllen Displays a memory dump from the specified display buffer address range Where 8116132 The unit size 8 bit bytes 16 bit words 32 bit dwords If a unit size is not specified this command uses the unit size from the last Dump command performed If no previous Dump command has been issued the unit size defaults to 8 bit startaddr The st
61. 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Windows CE 3 x USB Driver X37A E 007 01 Issue Date 01 10 19 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 3 0 USB DRIVER The Windows CE v3 0 USB driver for the S1D13A04 LCD USB Companion Chip is a client driver which supports Microsoft ActiveSync 3 1 This driver is intended as reference source code for OEMs developing for the Microsoft Window CE platform and provide a basis for OEMs to develop their own drivers This document and the source code for the Windows CE v3 0 USB driver is updated as appropriate Before beginning any development please check the Epson Research and
62. 1 then wait until REG 8004h bit O returns a 1 1D13A04 X37A G 003 05 Page 82 Epson Research and Development Vancouver Design Center 11 Prior to writing any data to the BitBLT FIFO confirm the BitBLT FIFO is not full REG 8004h bit 4 returns a 0 If the BitBLT FIFO Not Empty Status REG 8004h bit 6 returns a 0 the FIFO is empty Write up to 16 WORDS to the BitBLT data register area If the BitBLT FIFO Not Empty Status REG 8004h bit 6 returns a 1 and the BitBLT FIFO Half Full Status REG 8004h bit 5 returns a 0 then you can write up to 8 WORDS If the BitBLT FIFO Full Status returns a 1 do not write to the BitBLT FIFO until it re turns a 0 The following table summarizes how many words can be written to the BitBLT FIFO Table 9 7 Possible BitBLT FIFO Writes BitBLT Status Register REG 8004h Word Writes FIFO Not Empty Status FIFO Half Full Status FIFO Full Status Available 0 0 16 0 0 8 1 0 less than 8 1 1 0 do not write Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started 9 2 8 Transparent Move BitBLT in Positive Direction S1D13A04 X37A G 003 05 The Transparent Move BitBLT in Positive Direction combines the capabilities of the Move BitBLT with the ability to define a transparent color Use this operation to copy a masked area of display memory to another area in display memory The sourc
63. 1 ns t5 WEn RD setup to next CKIO after BS low 0 ns t6 Falling edge CSn to WAIT driven low 3 10 ns 7 D 15 0 setup to 3rd CKIO rising edge after BS deasserted 4 Tee write cycle t8 Falling edge of RD to D 15 0 driven read cycle 2 12 ns t9 WE RD deasserted to A 16 1 M R RD WR deasserted 0 ns t10 Rising edge of WAIT to BS falling Texio 16 ns t11 WE RD deasserted to CS high 0 ns 112 a rising edge before WAIT deasserted to WEn RD asserted 2 Tab or next cycle t13 Rising edge of WAIT to WE RD deasserted 0 ns t14 Rising edge of CSn to WAIT high impedance 0 5 Tekio t15 D 15 0 hold from WEn deasserted write cycle 2 note 1 ns t16 D 15 0 setup to CKIO falling edge read cycle 12 ns t17 Rising edge of RD to D 15 0 high impedance read cycle 5 ns t18 Cycle Length 4 Tckio 1 The S1D13A04 requires 2ns of write data hold time Hardware Functional Specification S1D13A04 X37A A 001 06 Page 42 6 2 4 Hitachi SH 4 Interface Timing Epson Research and Development Vancouver Design Center A 16 1 M R RD WR MS Tokio t1 t9 a gt queeiememees p t19 Al t2 13 y t10 il t4 t11 lt gt gt t12 le 5 t13 gt gt o WEn RDH MO t15 t6 t14 NL 1 t7 t16 K valid t17 gt t8 t18 gt e a valid 1D13A04 X37A A 001 06 Figure 6 5 Hita
64. 11 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 012 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X37A G 012 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13A04 LCD USB Companion Chip and the Motorola MC68VZ328 Dragonball VZ microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 012 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68VZ328 2 1 The MC68VZ328 System Bus The Motorola MC68VZ328 Dragonball VZ is the third generation in the Dragonball microprocessor family The Dragonball VZ is an integrated controller designed for handheld products It is based upon the FLX68
65. 15 0 bits 31 0 Scratch Pad C Bits 31 0 This register contains general purpose read write bits These bits have no effect on hard ware Note The contents of the Scratch Pad C register defaults to an un defined state after initial power up Any data written to this register remains intact when the S1D13A04 is reset as long as the chip is not powered off S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 117 Vancouver Design Center 8 4 USB Registers Offset 4000h The S1D13A04 USB device occupies a 48 byte local register space which can be accessed by the CPU on the local host interface To access the USB registers 1 A valid USBCLK must be provided 2 The USBCIk Enable bit REG 4000h bit 7 must be set to 1 and the USB Setup bit REG 4000h bit 2 must be set to 1 Both bits should be set together If any of the above conditions are not true the USB registers must not be accessed Control Register REG 4000h Default 00h Read Write n a 15 14 13 2 11 10 9 8 USBCIk Enable Software EOT USB Enable Endpoint 4 Stall Endpoint 3 Stall USB Setup 7 6 5 4 3 2 1 0 bit 7 USBCIKk Enable This bit allows the USBCIk to be enabled disabled allowing the S1D13A04 to save power when the USBCIK is not required This bit should be initially set with the USB Setup bit However it can be disabled re enabled individually When this bit 1 the U
66. 1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Page 11 Vancouver Design Center 3 2 Configuration Jumpers The S5U13A04B00C has five jumper blocks which configure various setting on the board The jumper positions for each function are shown below Table 3 2 Jumper Summary Jumper Function Position 1 2 Position 2 3 No Jumper JP1 CLKI Source i e External oscillator U7 BUSCLK from Header H4 JP2 CLKI2 Source External oscillator U8 JP3 LCD Panel Voltage 3 3V LCDVCC JP4 GPOIO Polarity on H1 Inverted Active Low GPIOO not sent to H1 JP5 GPIOO function select HR TFT PS signal recommended settings JP1 CLKI Source JP1 selects the source for the CLKI input pin Position 1 2 sets the CLKI source to VCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI source to the external oscillator at U7 When no jumper is installed the CLKI source is set to the BUSCLK signal from Header H4 A TEO ETA Ey llo oa VCLKOUT from External BUSCLK from clock synthesizer oscillator U7 Header H4 Figure 3 2 Configuration Jumper JP1 Location S5U13A04B00C Rev 1 0 Evaluation Board User Manual 1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 12 JP2 CLKI2 Source Epson Research and Development Vancouver Design
67. 2 NEC Electronics Inc NEC Electronics Inc U S A Corporate Headquarters 2880 Scott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 10 12 S1D13A04 X37A G 007 01 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the NEC VR4102 VR4111 Microprocessors X37A G 007 01 Issue Date 01 10 12 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the NEC VR4181A Microprocessor Document Number X37A G 008 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document bu
68. 256K colors When a monochrome panel is selected the green component of the LUT is used to determine the intensity The green indices with six bits can resolve 64 gray shades Display memory values gt 64 are truncated Thus a display memory value of 65 1000 0001 displays the same intensity as a display memory value of 1 4 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Red Component Green Component bits 4 0 bits 5 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Green Component bits 2 0 Blue Component bits 4 0 1D13A04 X37A G 003 05 Figure 4 5 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer Ata color depth of 16 bpp the S1D13A04 is capable of displaying 64K 65536 colors The 64K color pixel is divided into three parts five bits for red six bits for green and five bits for blue In this mode the LUT is bypassed and output goes directly into the Frame Rate Modulator Should monochrome mode be chosen at this color depth the output sends the six bits of the green LUT component to the modulator for a total of 64 possible gray shades Note This operation is similar to 8 bpp but it requires twice as much memory for the display Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 17 Vancouver Design Center 5 Look
69. 30h bits 9 0 1 lines VPS FPFRAME Pulse Start Position REG 3Ch bits 9 0 lines VPW FPFRAME Pulse Width REG SCh bits 18 16 1 lines VDPS Vertical Display Period Start Position REG 38h bits 9 0 lines VDP Vertical Display Period REG 34h bits 9 0 1 lines HT Horizontal Total REG 20h bits 6 0 1 x 8 pixels HPS FPLINE Pulse Start Position REG 2Ch bits 9 0 1 pixels HPW FPLINE Pulse Width REG 2Ch bits 22 16 1 pixels HDPS Horizontal Display Period Start Position REG 28h bits 9 0 5 pixels HDP Horizontal Display Period REG 24h bits 6 0 1 x 8 pixels For TFT panels the HDP must be a minimum of 8 pixels and must be increased by multiples of 8 Panel Type Bits REG OCh bits 1 0 01 TFT FPLINE Pulse Polarity Bit REG 2Ch bit 23 0 active low FPFRAME Polarity Bit REG 3Ch bit 23 0 active low S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 73 Vancouver Design Center 6 4 9 9 12 18 Bit TFT Panel Timing VNDP gt gy VDP bid VNDP FPFRAME FPLINE UU L L lI o U L Uo U FPDAT 17 0 LINE240 LINE A LINE480 DRDY A i PA FPLINE HNDP HDP HNDP gt FPSHIFT ass sae LI LJ DRDY FPDAT 17 0 inva OA
70. 89 00 C7 00 77 77 08 55 55 55 48 00 00 89 88 FF 77 00 C8 00 89 89 09 00 00 FF 49 00 00 9A 89 FF 66 00 C9 00 9A 9A 0A 00 FF 00 4A 00 00 AB 8A FF 55 00 CA 00 AB AB 0B 00 FF FF 4B 00 00 BC 8B FF 44 00 CB 00 BC BC 0c FF 00 00 4C 00 00 CD 8C FF 33 00 CC 00 CD CD 0D FF 00 FF 4D 00 00 DE 8D FF 22 00 CD 00 DE DE OE FF FF 00 4E 00 00 EF 8E FF 11 00 CE 00 EF EF OF FF FF FF 4F 00 00 FF 8F FF 00 00 CF 00 FF FF 10 00 00 00 50 00 00 FF 90 FF 00 00 DO FF 00 00 11 11 11 11 51 00 11 FF 91 FF 00 11 D1 FF 11 11 12 22 22 22 52 00 22 FF 92 FF 00 22 D2 FF 22 22 13 33 33 33 53 00 33 FF 93 FF 00 33 D3 FF 33 33 14 44 44 44 54 00 44 FF 94 FF 00 44 D4 FF 44 44 15 55 55 55 55 00 55 FF 95 FF 00 55 D5 FF 55 55 16 66 66 66 56 00 66 FF 96 FF 00 66 D6 FF 66 66 17 77 77 77 57 00 77 FF 97 FF 00 77 D7 FF 77 77 18 89 89 89 58 00 89 FF 98 FF 00 89 D8 FF 89 89 19 9A 9A 9A 59 00 9A FF 99 FF 00 9A D9 FF 9A 9A 1A AB AB AB 5A 00 AB FF 9A FF 00 AB DA FF AB AB 1B BC BC BC 5B 00 BC FF 9B FF 00 BC DB FF BC BC 1C CD CD CD 5C 00 CD FF 9C FF 00 CD DC FF CD CD 1D DE DE DE 5D 00 DE FF 9D FF 00 DE DD FF DE DE 1E EF EF EF 5E 00 EF FF 9E FF 00 EF DE FF EF EF 1F FF FF FF 5F 00 FF FF 9F FF 00 FF DF FF FF FF 20 00 00 00 60 00 FF FF AO FF 00 FF EO 00 FF 00 21 11 00 00 61 00 FF EF Al EF 00 FF E1 11 FF 11 22 22 00 00 62 00 FF DE A2 DE 00 FF E2 22 FF 22 23 33 00 00 63 00 FF CD A3 CD 00 FF E3 33 FF 33 S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21
71. A aig Note DRDY is used to indicate the first pixel Example Timing for 18 bit 320x240 panel VDP VNDP VNDP1 VNDP2 HDP HNDP HNDP1 HNDP2 Figure 6 28 18 Bit TFT Panel Timing Vertical Display Period VDP Lines Vertical Non Display Period VNDP1 VNDP2 VT VDP Lines Vertical Non Display Period 1 VNDP VNDP2 Lines Vertical Non Display Period 2 VDPS VPS Lines if negative add VT Horizontal Display Period HDP Ts Horizontal Non Display Period HNDP1 HNDP2 HT HDP Ts Horizontal Non Display Period 1 HDPS HPS Ts if negative add HT Horizontal Non Display Period 2 HPS HDP HDPS Ts if negative add HT Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 74 Epson Research and Development Vancouver Design Center t1 X t2 lt 4 gt FPFRAME J t3 we UW WW A t4 lt 4 gt FPLINE J p t5 18 t6 t7 E lt p lt gt DRDY J t9 t12 t13 14 t10 t11 gig t ee a ee N t15 gt lt _ gt FPDAT 17 0 invalid 1 i 2 Wi 320 invalid Note DRDY is used to indicate the first pixel Figure 6 29 TFT A C Timing S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Pa
72. C13 DO SRESET P9 D15 RESET SYSCLK P9 C2 CLKI CS4 P6 D13 CS TA P6 B6 to inverter enabled by CS WAIT WEO P6 B15 WE1 WE1 P6 A14 WE0 OE P6 B16 RD WR RD A13 P6 C21 M R P12 A1 P12 B1 P12 A2 P12 B2 GND P12 A3 P12 B3 P12 A4 P12 B4 Vss P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 Note 1 The PCMCIA connector P9 provides 2 0V on D 23 25 and can be used as the source for COREVDD However at 2 0V the S1D13A04 MCLK is has a maximum frequency of 30MHz To increase memory performance MCLK maximum SOMHz an external 2 5V power supply must be connected to COREVDD 2 The bit numbering of the Motorola MPC821 bus signals is reversed from the normal convention e g the most significant address bit is AO the next is Al A2 etc 3 The bit numbering of the Motorola MPC821 data signals is reversed from the normal convention e g the most significant address bit is DO the next is D1 D2 etc Interfacing to the Motorola MPC82x Microprocessor Issue Date 01 10 05 1D13A04 X37A G 009 01 Page 18 Epson Research and Development Vancouver Design Center 4 3 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SID13A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for this implementation of a S1D
73. Corrective Action X00Z P 001 01 There are two software solutions for this occurrence Disable USB Receiver before setting the EP4 FIFO Valid bit The first solution involves disabling the USB receiver to avoid responding to an EP4 IN packet During the time the USB receiver is disabled the EP4 FIFO Valid bit is set When the local CPU is ready to send data on endpoint 4 the steps to follow are 1 Disable the USB differential input receiver REG 4040h bit 6 0 2 Wait a minimum of lus If needed delays may be added 3 Enable the EP4 FIFO Valid bit REG 402Ch bit 5 1 4 Clear the EP4 Interrupt status bit REG 4004h bit 4 1 5 Enable the USB differential input receiver REG 4040h bit 6 1 Note Steps 1 through 5 are time critical and must be performed in less than 6 us Note To comply with EP4 NAK Status not set correctly in USB Status register steps 3 and 4 must be completed within 5 us of each other For further information on EP4 NAK Status not set correctly in USB Status register see the S1D13A0x Programming Notes and Examples document numbers X36A G 003 xx X37A G 003 xx and X40A G 003 xx EP4 FIFO Valid bit set after NAK and before the next IN token The second solution is to wait until immediately after the USB has responded to an IN request with a NAK packet before setting the transmit FIFO valid bit This solution is recommended only for fast processors When the local CPU is ready to send d
74. Design Center 6 3 LCD Power Sequencing 6 3 1 Passive TFT Power On Sequence GPIOO Power Save t1 Mode Enable REG AOh bit 0 t2 LCD Signals It is recommended to use the general purpose lO pin GPIOO to control the LCD bias power The LCD power on sequence is activated by programming the Power Save Mode Enable bit REG 14h bit 4 to 0 LCD Signals include FPDAT 17 0 FRSHIFT FPLINE FPFRAME and DRDY Figure 6 11 Passive TFT Power On Sequence Timing Table 6 17 Passive TFT Power On Sequence Timing Symbol Parameter Min Max Units t1 LCD signals active to LCD bias active Note 1 Note 1 t2 Power Save Mode disabled to LCD signals active 0 1 BCLK 1 t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 55 Vancouver Design Center 6 3 2 Passive TFT Power Off Sequence 4 gt GPIO0 Power Save Mode Enable REG AOh bit 0 t2 LCD Signals It is recommended to use the general purpose IO pin GPIOO to control the LCD bias power The LCD power off sequence is activated by programming the Power Save Mode Enable bit REG 14h bit 4 to 1 L_CD Signals include FPDAT 17 0 FRSHIFT FPLINE FPFRAME and DRDY F
75. Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 2000000002000 0 48 11 Table 4 1 Summary of Power On Reset Options e o 14 Table 4 2 RDFx Parameter Value versus CPU Maximum Frequency 15 List of Figures Figure 2 1 SA 1110 Variable Latency IO Read Cycle o oo 9 Figure 2 2 SA 1110 Variable Latency IO Write Cycle o o o 10 Figure 4 1 Typical Implementation of SA 1110 to S1D13A04 Interface 13 Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13A04 LCD USB Companion Chip and the Intel StrongARM SA 1110 Microprocessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Pl
76. Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Power Consumption X37A G 006 01 Issue Date 01 10 29 Epson Research and Development Page 3 Vancouver Design Center 1 S1D13A04 Power Consumption S1D13A04 power consumption is affected by many system design variables Input clock frequency CLKI CLKI2 the CLKI CLKI2 frequency determines the LCD frame rate CPU performance to memory and other functions the higher the input clock frequency the higher the frame rate performance and power consumption CPU interface the S1D13A04 current consumption depends on the BCLK frequency data width number of toggling pins and other factors the higher the BCLK the higher the CPU performance and power consumption Vpp Voltage level the voltage level affects power consumption the higher the voltage the higher the consumption Display mode the resolution and color depth affect power consumption the higher the resolution color depth the higher the consumption Internal CLK divide internal registers allow the input clock to be divided before going to the internal logic blocks the higher the divide the lower the power consumption There is a power save mode in the S1D13A04 The power consumption is affected by various system design variables e Clock states during the power save mode disabling the clocks during power save mode has substantial power savings Power Consumption 1D13A04 Issue Date
77. EN A 106 10 4 2 Write to EP4 FIFO Valid bit cleared by NAK 2 00 4 107 10 4 3 EP3 Interrupt Status bit set by NAKs aaa a 107 10 4 4 EP2 Valid Bit in USB Status can be erroneously set by firmware 110 S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center 10 4 5 Setting EP4 FIFO Valid bit while NAKing INtoken 110 11 Hardware Abstraction Layer 112 11 1 Introduction oe e e ee 112 11 2 API forthe HAL Library s s cas s osom mo a koa ee 112 11 2 1 Startup Routines 0 si ee 8 QA eh a A ew Ra Ok Re a 113 1132 2 Memory ACCESS ici aa eae BSE eS eR ae hE Sede eed Se 115 11 23 Register ACCESS riada Sats oa eae dat ee sen ae A 116 11 24 Clock SUpport cios a ab he Bae e a Be A A ee 118 1122 5 Miscellaneous ova a Rhee a a a 119 12 Sample Code mini 2 5 Di A es wee eee 121 13 Sales and Technical Support es 122 Programming Notes and Examples Issue Date 2002 08 21 Page 5 1D13A04 X37A G 003 05 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center Table 5 1 Table 5 2 Table 5 3 Table 5 4 Table 5 5 Table 5 6 Table 5 7 Table 5 8 Table 5 9 Ta
78. Endpoint 1 Receive Mailbox Data Register REG 4012h Default 00h Read Only ee EE Mailbox Da bits 7 0 bits 7 0 Endpoint 1 Receive Mailbox Data Bits 7 0 This register is used to read data from one of the receive mailbox registers Data is returned from the register selected by the Endpoint 1 Index Register The eight receive mailbox registers are written by a USB bulk transfer to endpoint 1 and can be used to pass messages from the USB host to the local CPU The format and content of the messages are user defined If enabled USB writes to this register can generate an interrupt Endpoint 2 Index Register REG 4018h Default 00h Read Write a ei 1 bits 2 0 Endpoint 2 Index Register Bits 2 0 This register determines which Endpoint 2 Transmit Mailbox is accessed when the End point 2 Transmit Mailbox Data register is read or written This register is automatically incremented after the Endpoint 2 Transmit Mailbox Data port is read or written This index register wraps around to zero when it reaches the maximum count 7 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 122 Epson Research and Development Vancouver Design Center Endpoint 2 Transmit Mailbox Data Register REG 401Ah Default 00h Read Write n a Endpoint 2 Transmit Mailbox Data bits 7 0 bits 7 0 Endpoint 2 Transmit Mailbox Data Bits 7 0 This register is used to read or write one of the transmit mailbo
79. FPDAT12 Green data signal 23 G3 FPDAT5 Green data signal 24 G4 FPDAT4 Green data signal 25 G5 FPDAT3 _ Green data signal MSB S1D13A04 Connecting to the Sharp HR TFT Panels X37A G 011 01 Issue Date 01 10 12 Epson Research and Development Vancouver Design Center Page 13 Table 2 2 SIDI3A04 to LQ039Q2DS01 Pin Mapping Continued LCDPin LCD Pin S1D13A04 Description Remarks No Name Pin Name P 26 BO FPDAT17 Blue data signal LSB 27 B1 FPDAT16 Blue data signal 28 B2 FPDAT15 Blue data signal 29 B3 FPDAT8 Blue data signal 30 B4 FPDAT7 Blue data signal 31 B5 FPDAT6 Blue data signal MSB or See Section 2 1 External Power 32 VSHD Digital power supply Supplies on page 8 33 DGND Vss Digital ground Ground pin of S1D13A04 34 PS GPIOO Power save signal 35 LP FPLINE _ Data latch signal of source driver 36 DCLK FPSHIFT Data sampling clock signal 37 LBR Selection for horizontal scanning direction Connect to VSHD left right scanning 38 SPR 2 Sampling start signal for right left scanning Right to left scanning not supported See Section 2 1 External Power 39 VSHA Analog power supply Supplies on page 8 40 VO Standard gray scale voltage black See Section 2 1 External Power Supplies on page 8 41 vi Standard gray scale voltage da O Sue OA Supplies on page 8 42 v2 Standard gray scale voltage
80. Figure 9 1 Move BitBLT Usage Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 77 Vancouver Design Center Example 12 Copy a 9 x 101 rectangle at the screen coordinates x 100 y 10 to screen coordinates x 200 y 20 using a 320x240 display at a color depth of 16 bpp 1 Calculate the source and destination addresses upper left corners of the source and destination rectangles using the following formula SourceAddress y X ScreenStride x x BytesPerPixel 10 x 320 x 2 100 x 2 6600 19C8h DestinationAddress y x ScreenStride x x BytesPerPixel 20 x 320 x 2 200 x 2 13200 3390h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride Display WidthInPixels x BytesPerPixel 640 for 16 bpp Program the BitBLT Source Start Address Register REG 800Ch is set to 19C8h Program the BitBLT Destination Start Address Register REG 8010h is set to 3390h 2 Program the BitBLT Width Register to 9 1 REG 8018h is set to 08h 3 Program the BitBLT Height Register to 101 1 REG 801Ch is set to 64h 100 deci mal 4 Program the BitBLT Operation Register to select the Move BitBLT in Positive Direc tion with ROP REG 8008h bits 3 0 are set to 2h 5 Program the BitBLT ROP Code Register to select Destination Source REG 8008h bits 19 16 are set to OCh 6 Program the BitBLT Color Format Select bit for 16 bpp operat
81. For 16 bpp color depths REG 8000h bit 18 1 bits 15 0 are used For 8 bpp color depths REG 8000h bit 18 0 bits 7 0 are used Note For Big Endian implementations see the 1D13A04 Programming Notes and Examples document number X37A G 003 xx BitBLT Foreground Color Register REG 8024h Default 00000000h Read Write n a 3i 30 29 28 27 26 25 24 23 22 21 20 19 18 lz 16 BitBLT Foreground Color bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits 15 0 BitBLT Foreground Color Bits 15 0 This register specifies the BitBLT foreground color for Color Expansion or Solid Fill For 16 bpp color depths REG 8000h bit 18 1 bits 15 0 are used For 8 bpp color depths REG 8000h bit 18 0 bits 7 0 are used Note For Big Endian implementations see the 1D13A04 Programming Notes and Examples document number X37A G 003 xx 8 6 2D Accelerator BitBLT Data Register Descriptions The 2D Accelerator BitBLT data registers decode AB15 ABO and require AB16 1 The BitBLT data registers are 32 bit wide Byte access to the BitBLT data registers is not allowed 2D Accelerator BitBLT Data Memory Mapped Region Register AB16 ABO 10000h 1FFFEh even addresses Read Write BitBLT Data bits 31 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BitBLT Data bits 15 0 bits 15 0 BitBLT Data Bits 15 0 This register specifies the BitBLT data This register is loosely decoded from 10000h to 1FFFEh Hardware Functional Specification
82. Functional Specification document number X37A A 001 for more information regarding the bits in the GPIO Status and Control register Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 96 10 2 2 USB Registers Epson Research and Development Vancouver Design Center The steps described below are typical of the startup of the S1D13A04 USB controller e registers are set to an initial value e the S1D13A04 is connected to a USB host controller e the host controller issues a RESET command e the USB registers are re initialized As initialization for both steps are similar it is recommended that one routine perform the sequence The following table depicts a typical register initialization sequence Table 10 1 USB Controller Initialization Sequence 8 Value Register hex Notes Enable the USB differential input receiver and indicate we are a bulk REG 4040h USBFG INRUT CONTROL a0 transfer self powered device for SOchronous mode use 43h USBPUP must be set to enable the USB interface and registers PESA PIO SPAMS DATA 91 REG 4000h to REG 403Ah cannot be written until this bit is set REG 4000 CONTROL 84 Enable the clocks and USB GPIO pins REG 4024 EP3 RECEIVE FIFO STATUS 1C Clear EP3 status REG 402C USB EP4 TX FIFO STATUS 1C Clear EP4 status REG 4032 USB STATUS 7E Clear EP2 valid bit REG 4004 INTERRUPT ST
83. GPIOO GPIOO is used on the S1D13A04 evaluation board Power Up Time Delay This setting controls the maximum time delay between when the S1D13A04 control signals are turned on and the LCD panel is powered on This setting must be configured according to the specification for the panel being used This value is used by Epson evaluation software designed for the S5U13A04B00C evaluation board Power Down Time Delay This setting controls the minimum time delay between when the LCD panel is powered off and when the S1D13A04 control signals are turned off This setting must be configured according to the specification for the panel being used This value is used by Epson evaluation software designed for the S5U13A04B00C evaluation board 13A04CFG Configuration Program S1D13A04 Issue Date 01 10 19 X37A B 001 01 Page 20 Epson Research and Development Vancouver Design Center Registers Tab 51D13404 Configuration Utility File Help Bm ES General Preferences Clocks Panel Panel Power Registers Direct Decimal Register Name The Registers tab allows viewing and editing of the S1D13A04 register values Scroll up and down the list to view register values which are determined from the configu ration settings of the previous tabs Hovering over a register displays a pop up help box which describes the functionality of the bits in that register Register settings may be changed by double clicking on the registe
84. HR TFT 8 2 1 External Power Supplies a e e 2 ee ee 8 2 1 1 Gray Scale Voltages for Gamma Correction o e 00004 8 2 1 2 Digital Analog Power Supplies e e 9 2 1 3 DC Gate Driver Power Supplies e a eee eee eee 9 2 1 4 AC Gate Driver Power Supplies e e ee eee 10 2 2 HR TFT MOD Signal A ee te A A rach oe eee Byte las e MEL 2 3 S1D13A04 to LQ039Q2DS01 Pin Manome nde e E a a e pis ss AD 3 Connecting to the Sharp LQ031B1DDxx HR TFT lt lt 14 3 1 External Power Supplies 0000 6 a ee ee eee en TA 3 1 1 Gray Scale Voltages for Gamma Correction o e 008 14 3 1 2 Digital Analog Power Supplies o e e o o 15 3 1 3 DC Gate Driver Power Supplies o e e e 15 3 1 4 AC Gate Driver Power Supplies e e o 15 3 2 HR TFT MOD Signal AR E fac A ond Y LO 3 3 S1D13A04 to LQ031B1DDxx Pin Mapping is er ea A Ay oe aa MO Test SottwWate 2 See Sho A LE go Pou ie a Ra aa e Se 18 REIGFENCES n a s a Ae A a a de Pe ee ee ee da 19 Sil Documents aaa aS a D aw et AS ek td ted PR ta ae MO 5 2 Document Sources 5 06 a ee ON A ce ee ee a a 19 6 Technical Support hos isa ada eS ee aS 20 6 1 EPSON LCD USB Companion Chips S1D13A04 2 2 2 2 20 6 2 Sh rp HR TEFT Panel 3 east ar we oe aoe a BR ee ee ew Pe 20 Connecting to the Sha
85. Input Requirements forCLKI2 Table 6 4 Internal Clock Requirements o e e e Table 6 5 Generic 1 Interface TlMINg e Table 6 6 Generic 1 Interface Truth Table for Little Endian Table 6 7 Generic 1 Interface Truth Table for Big Endian Table 6 8 Generic 2 Interface TilMiNB e e Table 6 9 Generic 2 Interface Truth Table for Little Endian Table 6 10 Hitachi SH 3 Interface TiMiN8 o Table 6 11 Hitachi SH 4 Interface TiMiN8 o o Table 6 12 Motorola MC68K H1 Interface TiMiNg o Table 6 13 Motorola MC68K 2 Interface Timing o Table 6 14 Motorola Redcap2 Interface Timing 4 Table 6 15 Motorola Dragonball Interface Timing with DTACK Table 6 16 Motorola Dragonball Interface Timing w o DTACK Table 6 17 Passive TFT Power On Sequence TiMiNg Table 6 18 Passive TFT Power Off Sequence Timing Table 6 19 Panel Timing Parameter Definition and Register Summary Table 6 20 Single Monochrome 4 Bit Panel A C Timing Table 6 21 Single Monochrome 8 Bit Panel A C Timing Table 6 22 Single Color 4 Bit Panel A C TiMiN8 o a Table 6 23 Single Color 8 Bit Panel A C Timing Formatl
86. Issue Date 2003 05 01 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 4 1 Figure 4 2 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 6 6 Figure 6 7 Figure 6 8 Figure 6 9 Figure 6 10 Figure 6 11 Figure 6 12 Figure 6 13 Figure 6 14 Figure 6 15 Figure 6 16 Figure 6 17 Figure 6 18 Figure 6 19 Figure 6 20 Figure 6 21 Figure 6 22 Figure 6 23 Figure 6 24 Figure 6 25 Figure 6 26 Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Vancouver Design Center Page 9 List of Figures Typical System Diagram Generic 1 Bus o o 15 Typical System Diagram Generic 2 Bus o o e 15 Typical System Diagram Hitachi SH 4 Bus oo a 16 Typical System Diagram Hitachi SH 3 Bus oo o 16 Typical System Diagram MC68K 1 Motorola 16 Bit 68000 17 Typical System Diagram MC68K 2 Motorola 32 Bit 68030 17 Typical System Diagram Motorola REDCAP2 Bus 18 Typical System Diagram Motorola MC68EZ328 MC68VZ328 DragonBall Bus 18 USB Typical Implementati0d e 19 Pinout Diagram PFBGA 121 PMM e 20 Pinout Diagram TQFP13 128 pin 2 ee 21 Clock Input Requirements ee 34 Generic 1 Interface Timing 36
87. LCD display no rotation Useful Hex Values 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13A04 Width dword 140 Height dword FO Bpp dword 8 Rotation dword 0 13 From the Build menu select Rebuild Platform to generate a Windows CE image file NK BIN in the project directory x myproject myplatform reldir x86_release nk bin Windows CE 3 x Display Driver Issue Date 01 10 19 S1D13A04 X37A E 006 01 Page 8 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK BIN file is built the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC from a floppy drive a Create a bootable floppy disk b Copy HIMEM SYS to the floppy disk and edit CONFIG SYS on the floppy disk to contain only the following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines loadcepc B 38400 C 1 c nk bin d Search for loadcepc exe in the Windows CE directories and copy loadcepc exe to the bootable floppy disk e Copy NK BIN to ca f Boot the system from the bootable floppy disk 2 To start CEPC from a hard drive a Search for loadcepc exe in the Windows CE directories and copy loadcepc exe to Ca b Edit CONFIG SYS on the hard drive to contain only the
88. Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 10 12 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the Intel StrongARM SA 1110 Microprocessor Document Number X37A G 013 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introduction se 2 re n
89. Number X37A G 004 xx Epson Research and Development Inc S1D13A04 Programming Notes and Examples Document Number X37A G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website www mot com e Epson Research and Development Website www erd epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 012 01 Page 16 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de 7 2 Motorola MC68VZ328 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor 1D13A04 X37A G 012 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287
90. Output Path Revision 6 0 Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Vancouver Design Center 4 Bit Per Pixel Color Page 149 4 bit per pixel data from Image Buffer Red Look Up Table 256x6 Green Look Up Table 256x6 0110 6 bit Red Data 0110 6 bit Green Data 0110 6 bit Blue Data unused Look Up Table entries Figure 12 7 4 Bit Per Pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 2003 05 01 1D13A04 X37A A 001 06 Revision 6 0 Page 150 Epson Research and Development Vancouver Design Center 8 Bit per pixel Color Mode Red Look Up Table 256x6 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 p a 6 bit Red Data F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111
91. Page 49 Symbol Parameter Min Max Unit fcko Bus clock frequency 17 MHz TcKo Bus clock period 1 fcko ns ti A 16 1 R W CSn setup to CKO rising edge 1 ns t2 EB0 EB1 setup to CKO rising edge write 1 ns 3 D 15 0 input setup to 4th CKO rising edge after CSn and EBO or 4 T EB1 asserted low write cycle CKO D 15 0 input hold from 4th CKO rising edge after CSn and EBO or t4 p7 11 ns EB1 asserted low write cycle t5 EB0 EB1 0E setup to CKO rising edge read cycle 1 ns t6a 1st CKO rising edge after CSn EBO or EB1 0E asserted low to 5 T D 15 0 valid for MCLK BCLK read cycle CKO 16b 1st CKO rising edge after CSn EBO or EB1 0E asserted low to 8 T D 15 0 valid for MCLK BCLK 2 read cycle CKO t6c 1st CKO rising edge after CSn EBO or EB1 0E asserted low to 10 T D 15 0 valid for MCLK BCLK 3 read cycle CKO t6d 1st CKO rising edge after CSn EBO or EB1 0E asserted low to 13 T D 15 0 valid for MCLK BCLK 4 read cycle CKO t7 EBO EB1 OE falling edge to D 15 0 driven read cycle 4 11 ns t8 A 16 1 R W CSn hold from CKO rising edge 0 ns t9 EBO EB1 setup to CKO rising edge write cycle 1 ns t10 CKO falling edge to EBO EB1 OE deasserted read 0 ns t11 OE EBO EB1 deasserted to D 15 0 output high impedance read 1 ns t12 Cycle Length note 1 10 10 TcKo 1 The cycle length for the REDCAP interface is fixed 2 The Read and Write 2D BitBLT functio
92. Pattern Display Test Pattern Shutdown S1D13A04 1D13A04 X37A B 001 01 Epson Research and Development Vancouver Design Center When this box is checked the S1D13A04 Lookup Table is programmed as part of the initialization When this box is checked the S1D13A04 display buffer will be cleared set to zeros as part of the initialization Clicking this button initializes the 1D13A04 according to the options selected After initializing the S1D13A04 these further options become available This setting should be used with caution Checking this box will cause setting changes on any tab to immedi ately update the associated register s Checking this box will update the test pattern in the display buffer after every setting change This is useful when fine tuning panel settings as the results of the change are immediately visible Clicking this button causes 13A04CFG to draw a test pattern into display memory The pattern is based on the configured width height rotation and color depth Clicking this button shuts down the S1D13A04 This feature is necessary should a setting change appear to be damaging or harmful to the attached panel 13A04CFG Configuration Program Issue Date 01 10 19 Epson Research and Development Vancouver Design Center 13A04CFG Menus Open Page 23 The following sections describe each of the options in the File and Help menus From the Menu Bar select File then Open
93. REG 8008h Default 00000000h Read Write e eae Ores Bs ar min i L BitBLT ROP Code The BitBLT ROP Code specifies the Raster Operation to be used for Write and Move Bit BLTs In addition for Color Expansion the BitBLT ROP Code bits 2 0 specify the start bit position for Color Expansion BitBLTs Table 9 2 BitBLT ROP Code Color Expansion Function Selection BitBLT ROP Code Bits Boolean Function for Write Boolean Function for Start Bit Position for Color 3 0 BitBLT and Move BitBLT Pattern Fill Expansion 0000 0 Blackness 0 Blackness bit O 0001 S D or S D P D or P D bit 1 0010 S D P D bit 2 0011 S P bit 3 0100 S D P D bit 4 0101 D D bit 5 0110 S D P D bit 6 0111 S D or S D P D or P D bit 7 1000 S D P D bit 0 1001 S D P D bit 1 1010 D D bit 2 1011 S D P D bit 3 1100 S P bit 4 1101 S D P D bit 5 1110 S D P D bit 6 1111 1 Whiteness 1 Whiteness bit 7 Note S Source D Destination P Pattern NOT Logical AND Logical OR Logical XOR Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 62 BitBLT Operation Epson Research and Development Vancouver Design Center The BitBLT Operation selects which BitBLT operation performed The following table lists the available BitBLT operations Table 9 3 BitBLT Operation Selection
94. RESET and defaults to an input after every RESET When this pin is not used for USB it must either be configured as an output using REG 64h or be pulled high or low externally to avoid unnecessary current drain Hardware Functional Specification Issue Date 2003 05 01 1D13A04 X37A A 001 06 Revision 6 0 Page 28 Epson Research and Development Vancouver Design Center Table 4 3 LCD Interface Pin Descriptions PFBGA TQFP15 RESET ee Pin Name Type Ping Ping Cell State Description This pin has multiple functions e USBDETECT e General purpose lO pin 5 GPIO5 GPIO5 IO G6 50 LB3M GPIO5 defaults to a Hi Z state during every RESET and defaults to an input after every RESET When this pin is not used for USB it must either be configured as an output using REG 64h or be pulled high or low externally to avoid unnecessary current drain This pin has multiple functions e USBDM e General purpose IO pin 6 GPIO6 GPIO6 IO K6 49 CUS GPIO6 defaults to a Hi Z state during every RESET and defaults to an input after every RESET When this pin is not used for USB it must either be configured as an output using REG 64h or be pulled high or low externally to avoid unnecessary current drain This pin has multiple functions e USBDP e General purpose lO pin 7 GPIO7 IO L6 48 CUS GPIO7 defaults to a Hi Z state during every RESET and defaults to an i
95. S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 142 Epson Research and Development Vancouver Design Center 9 2D Accelerator BitBLT Engine 9 1 Overview The S1D13A04 is designed with a built in 2D BitBLT engine which increases the perfor mance of Bit Block Transfers BitBLT It supports 8 and 16 bit per pixel color depths The BitBLT engine supports rectangular and linear addressing modes for source and desti nation in a positive direction for all BitBLT operations except the move BitBLT which also supports in a negative direction The BitBLT operations support byte alignment of all types The BitBLT engine has a dedicated BitBLT IO access space This allows the BitBLT engine to support simultaneous BitBLT and host side operations 9 2 BitBLT Operations 1D13A04 The S1D13A04 2D BitBLT engine supports the following BitBLTs For detailed infor mation on using the individual BitBLT operations refer to the S1D13A04 Programming Notes and Examples document number X37A G 003 xx Write BitBLT Move BitBLT Solid Fill BitBLT Pattern Fill BitBLT e Transparent Write BitBLT e Transparent Move BitBLT e Read BitBLT e Color Expansion BitBLT e Move BitBLT with Color Expansion Note For details on the BitBLT registers see Section 8 5 2D Acceleration BitBLT Regis ters Offset 8000h on page 135 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revis
96. Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 98 Epson Research and Development Vancouver Design Center 8 3 4 Look Up Table Registers Look Up Table Write Register REG 18h Default 00000000h Write Only LUT Write Address LUT Red Write Data n a 21 20 19 17 LUT Blue Write Data 5 4 3 Note The S1D13A04 has three 256 position 6 bit wide LUTs one for each of red green and blue see Section 12 Look Up Table Architecture on page 145 Note This is a write only register and returns 00h if read bits 31 24 LUT Write Address Bits 7 0 These bits form a pointer into the Look Up Table LUT which is used to write the LUT Red Green and Blue data When the S1D13A44 is set to a host bus interface using lit tle endian CNF4 0 the RGB data is updated to the LUT with the completion of a write to these bits Note When a value is written to the LUT Write Address Bits the same value is automatically placed in the LUT Read Address Bits REG 1Ch bits 31 24 bits 23 18 LUT Red Write Data Bits 5 0 These bits contains the data to be written to the red component of the Look Up Table The LUT position is controlled by the LUT Write Address bits bits 31 24 bits 15 10 LUT Green Write Data Bits 5 0 These bits contains the data to be written to the green component of the Look Up Table The LUT position is controlled by the LUT Write Address bits bits 31 24 bits 7 2 LUT Blue Writ
97. Tel 02 2717 7360 Fax 02 2712 9164 http Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 10 12 EPSON 1D13A04 LCD USB Companion Chip Connecting to the Sharp HR TFT Panels Document Number X37A G 011 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Connecting to the Sharp HR TFT Panels X37A G 011 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A introd ction 6 su sere tats Sie aS eee se ADA A A aw oe ate 7 2 Connecting to the Sharp LQ039Q2DS01
98. The S1D13A04 HAL includes six register access functions The primary purpose of the register access functions is to demonstrate how to access the S1D13A04 control registers using the C programming language Most programs that need to access the registers will bypass the HAL and access the registers directly Uint8 halReadReg8 UInt32 Index Description Reads and returns the contents of one byte of an S1D13A04 register at the requested off set No S1D13A04 registers are changed Parameters Index 32 bit offset to the register to read Index is zero based from the beginning of register address space e g if Index 04h then the Memory Clock Configuration register will be read and if Index 8000h then the BitBLT Control Register will be read Return Value The value read from the register Use caution in selecting the index and when interpreting values returned from halReadReg8 to ensure the correct meaning is given to the values Changing between big endian and little endian will move relative register offsets S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 117 Vancouver Design Center Ulnt16 halReadReg16 Ulnt32 Index Description Parameters Return Value Reads and returns the contents of one word of an S1D13A04 register at the requested off set No S1D13A04 register are changed Index 32 bit offset to the register to read Index is zero based from th
99. This register should be accessed using a 32 bit write cycle to ensure proper operation If the Look Up Table Write Register is accessed with 8 or 16 bit write it is important to under stand that the LUT data is latched into the LUT only after the completion of the write to the LUT Write Address bits On little endian systems this means a write to bits 31 24 On big endian systems this means a write to bits 7 2 This is a write only register and returns 00h if read Note For further information on the S1D13A04 LUT architecture see the S D13A04 Hard ware Functional Specification document number X37A A 001 xx Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 18 Epson Research and Development Vancouver Design Center 5 1 2 Look Up Table Read Registers Look Up Table Read Register REG 1Ch Default 00000000h Write Only bits 31 24 Read Only LUT Read Address write only LUT Red Read Data 29 28 21 20 19 18 LUT Blue Read Data 5 4 3 This register contains the data returned from the red bits 23 18 green bits 15 10 and blue bits 7 2 components of the Look Up Table LUT Also contained in this register is the LUT Read Address bits 31 24 which forms a pointer to the location in the LUT where the RGB components are read from Reading the LUT is a two step process First the desired index must be set by writing the LUT Read Address bits with the desired index Second the LUT values are re
100. Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 Power PC Memory Read Cycle illustrates a typical memory read cycle on the Power PC system bus SYSCLK E E A 0 31 ee TSIZ 0 1 AT O 3 X post 20000A ANAX Sampled when TA ow Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC82x Microprocessor S1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 Power PC Memory Write Cycle illustrates a typical memory write cycle on the Power PC system bus A 0 31 X RD WR TSIZ 0 1 AT 0 3 T X D 0 31 Valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit tran
101. Up Table LUT This section discusses programming the S1D13A04 Look Up Table LUT Included is a summary of the LUT registers recommendations for color gray shade LUT values and additional programming considerations For a discussion of the LUT architecture refer to the 1D13A04 Hardware Functional Specification document number X37A A 001 xx The S1D13A04 is designed with a LUT consisting of 256 indexed red green blue entries Each LUT entry is six bits wide The color depth bpp determines how many indices are used For example 1 bpp uses the first 2 indices 2 bpp uses the first 4 indices 4 bpp uses the first 16 indices and 8 bpp uses all 256 indices 16 bpp bypasses the LUT In color modes the pixel values stored in the display buffer index directly to an RGB value stored in the LUT In monochrome modes the pixel value indexes into the green component of the LUT and the amount of green at that index controls the intensity 5 1 Registers 5 1 1 Look Up Table Write Register Look Up Table Write Register REG 18h Default 00000000h Write al LUT Write Address LUT Red Write Data 29 LUT Green me Data 1 E i se Wits Da to This register receives the data to be written to the red bits 23 18 green bits 15 10 and blue bits 7 2 components of the Look Up Table LUT Also contained in this register is the LUT Write Address bits 31 24 which forms a pointer to the location in the LUT where the RGB components will be written
102. User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 20 Epson Research and Development Vancouver Design Center 6 5 Adjustable LCD Panel Positive Power Supply Most color passive LCD panels and most single monochrome 640x480 passive LCD panels require a positive power supply to provide between 23V and 40V 45mA Such a power supply VDDH has been provided on the S5U13A04B00C board VDDH can be adjusted using R22 to provide an output voltage from 23V to 40V and is enabled disabled using the S1D13A04 general purpose signal GPIOO active high Note When manually adjusting the voltage set the potentiometer according to the panel s specific power requirements before connecting the panel 6 6 Software Adjustable LCD Backlight Intensity Support Using PWM The S1D13A04 provides Pulse Width Modulation output on PWMOUT PWMOUT can be used to control LCD panels which support PWM control of the backlight inverter The PWMOUT signal is provided on the LCD connector H1 6 7 LCD Panel Support The S1D13A04 directly supports e Single panel single drive passive displays e 4 8 bit monochrome interface e 4 8 16 bit color interface e Active Matrix TFT interface e 9 12 18 bit interface e Direct support for 18 bit Sharp HR TFT LCD or compatible interface All the necessary signals are provided on the 40 pin LCD connector H1 and the 16 pin LCD connector H2 For connection information refer to Table 5 1 LCD Signal Co
103. Vop RD WR BS A gt CS A 17 0 gt AB 17 0 D 15 0 i gt DB 15 0 15K pull up WAIT 4 WAIT 7 CLKI Oscillator CLKI2 Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13A04 X37A G 005 01 Figure 4 1 Typical Implementation of PC Card to SIDI3A04 Interface Interfacing to the PC Card Bus Issue Date 01 10 12 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SIDI3A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for this implementation of a S1D13A04 to PC Card bus interface Table 4 1 Summary of Power On Reset Options S1D13A04 Configuration Input Power On Reset State 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 CNF3 Reserved Must be set to 1 CNF5 WAIT is active high CNF6 CLKI to BCLK divide ratio 2 1 SSS configuration for PC Card bus 4 3 Register Memory Mapping The S1D13A04 is a memory mapped device The S1D13A04 uses two 256K byte blocks which are selected using A18 from the PC Car
104. X Y XO X1 B318X Invalid xo X FPDATS valid 1 B1 YX 1 G4 X 1 87 X Y X X RINV invalid X FPDAT4 nvalid R2 X 1 B4 X 1 67 Y o e Y X X1 G319 Invalid X FPDAT3 maid AR ARA AB X Y XO B19 Invalid X FPDAT2 nvalid 182X 16 Y 18X Y Y X yY ViR invalid y FPDAT1 _ Invalid As X1B5 X68 X X X X Mex Invalid FPDATO vaid E OD O XX X KBX Invalid Notes The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 23 Single Color 8 Bit Panel Timing Format 2 VDP Vertical Display Period REG 34h bits 9 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 30h bits 9 0 REG 34h bits 9 0 Lines HDP Horizontal Display Period REG 24h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 20h bits 6 0 1 x 8Ts REG 24h bits 6 0 1 x 8Ts 1D13A04 Hardware Functional Specification X37A A 001 06 Revision 6 0 Issue Date 2003 05 01 Epson Research and Development Page 69 Vancouver Design Center Sync Timing t i 2 FPFRAME tt lt t3 gt FPLINE o is DRDY MOD Y Data Timing FPLINE t6 4 t8 gt 4 t9 gt t7 t14 tii t10 lt 4 gt gt t _
105. ad Si n Ste eon Supplies on page 8 43 V3 Standard gray scale voltage Bee Secon Slee eave Supplies on page 8 44 V4 Standard gray scale voltage eee Section Ebi eine ag Supplies on page 8 45 V5 Standard gray scale voltage e Section Aih Pipal rowel Supplies on page 8 46 V6 Standard gray scale voltage pee Secon ed A Supplies on page 8 47 V7 Standard gray scale voltage See Secon o IA Supplies on page 8 48 V8 5 Standard gray scale voltage eee Secon loe Supplies on page 8 49 v9 i Standard gray scale voltage white ore Section ety einer ewe Supplies on page 8 50 AGND Vss Analog ground Ground pin of S1D13A04 Connecting to the Sharp HR TFT Panels Issue Date 01 10 12 S1D13A04 X37A G 011 01 Page 14 Epson Research and Development Vancouver Design Center 3 Connecting to the Sharp LQ031B1DDxx HR TFT 3 1 External Power Supplies The S1D13A04 provides all necessary data and control signals to connect to the Sharp LQ031B1DDxx 160x160 HR TFT panel s However it does not provide any of the voltages required for the backlight gray scaling gate driving or for the digital and analog supplies Therefore external supplies must be designed for any device utilizing the LQ031B1DDxx The LQ031B1DDxx 160x160 has the same voltage requirements as the LQ039Q2DS01 320x240 All the circuits used to generate the various voltages for the LQ039Q2DS01 panel also apply to the LQ031B1DDxx panel This section pr
106. an input after every RESET When this pin is used GPIO1 IO J7 56 LB3M for HR TFT it must be configured as an output using REG 64h Otherwise it must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain See Table 4 6 LCD Interface Pin Mapping on page 32 for summary This pin has multiple functions REV for Direct HR TFT e General purpose IO pin 2 GPIO2 GPIO2 defaults to a Hi Z state during every RESET and defaults to an input after every RESET When this pin is used GPIO2 IO K7 55 LB3M for HR TFT it must be configured as an output using REG 64h Otherwise it must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain See Table 4 6 LCD Interface Pin Mapping on page 32 for summary This pin has multiple functions e SPL for Direct HR TFT e General purpose IO pin 3 GPIO3 GPIO3 defaults to a Hi Z state during every RESET and defaults to an input after every RESET When this pin is used GPIO3 lO L7 54 LB3M for HR TFT it must be configured as an output using REG 64h Otherwise it must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain See Table 4 6 LCD Interface Pin Mapping on page 32 for summary This pin has multiple functions e USBPUP e General purpose IO pin 4 GPIO4 GPIO4 10 H7 51 LB3M GPIO4 defaults to a Hi Z state during every
107. and Development Vancouver Design Center BitBLT Memory Address Offset Register REG 8014h Default 00000000h Read Write es er TOS er bits 10 gt bits 10 0 BitBLT Memory Address Offset Bits 10 0 These bits are the display s 11 bit address offset from the starting word of line n to the starting word of line n They are used only for address calculation when the BitBLT is configured as a rectangular region of memory They are not used for the displays BitBLT Width Register REG 8018h Default 00000000h Read Write bits 9 0 BitBLT Width Bits 9 0 A 10 bit register that specifies the BitBLT width in pixels 1 BitBLT width in pixels ContentsOfThisRegister 1 BitBLT Height Register REG 801Ch Default 00000000h Read Write etal o de i bits 9 0 BitBLT Height Bits 9 0 A 10 bit register that specifies the BitBLT height in lines 1 BitBLT height in lines ContentsOfThisRegister 1 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 141 Vancouver Design Center BitBLT Background Color Register REG 8020h Default 00000000h Read Write n a ail 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BitBLT Background Color bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits 15 0 BitBLT Background Color Bits 15 0 This register specifies the BitBLT background color for Color Expansion or key color for Transparent BitBLT
108. and Development Page 3 Vancouver Design Center Table of Contents 1 introduction 5 ses a seers a a Se Sow ee EO ee a a we ie Bate 7 2 Interfacing to the MCF5307 2 ee ee 8 2 1 The MCF5307 System Bus o 8 QV ds SOVERVICW oi a ad a a dio te 8 2 1 2 Normal Non Burst Bus Transactions e 8 213 iBurstEycles oi va lt AAA Ad A te rs ad 9 2 2 Chip SelectsModutl s s sod arsa A a dr apnea 10 3 S1D13A04 Host Bus Interface 0 4 11 3 1 Host Bus Interface Pin Mapping 11 3 2 Host Bus Interface Signals 2 ee 12 4 MCF5307 To S1D13A04 Interface o 13 4 1 Hardware Description a 2 0 0 0 0 002 00 13 4 2 S1D13A04 Hardware Configuration 2 2 2 2 2 14 4 3 Register Memory Mapping 2 2 LS 4 4 MCF5307 Chip Select Configuration 15 5 SOTWalG A a A ae EA 16 Referents ncra a A AR A OW ana a ee Oe Oa mead 17 6 1 Documents 5 ea Ae he Ae aa A wr a a ee a ET 6 2 Document Sources 2 ee ee ee 17 7 Sales and Technical Support 18 7 1 EPSON LCD USB Companion Chips S1D13A04 18 7 2 Motorola MCF5307 Processor 2 2 2 ee eee ee ee ee 18 Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 010 01 Page 4 Epso
109. bias power supply from 14V to 24V Software adjustable backlight intensity support using PWMOUT 4 8 bit 3 3V or 5V single monochrome passive LCD panel support 4 8 16 bit 3 3V or 5V single color passive LCD panel support 9 12 18 bit 3 3V or 5V active matrix TFT LCD panel support Direct interface for 18 bit Epson D TFD LCD panel support Direct interface for 18 bit Sharp HR TFT LCD panel support Programmable clock synthesizer to CLKI and CLKI2 for maximum clock flexibility Connector for USB client support Software initiated power save mode Selectable clock source for CLKI and CLKI2 External oscillator support for CLKI and CLKI2 S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Epson Research and Development Page 9 Vancouver Design Center 3 Installation and Configuration The S5U13A04B00C is designed to support as many platforms as possible The S5U13A04B00C incorporates a DIP switch and five jumpers which allow both the evalu ation board and the S1D13A04 LCD controller to be configured for a specified evaluation platform 3 1 Configuration DIP Switches The S1D13A04 has configuration inputs CNF 6 0 which are read on the rising edge of RESET In order to configure the S1D13A04 for multiple Host Bus Interfaces an eight position DIP switch SW1 is required The following figure shows the location of DIP switch SW1 on the SSU13A04BO00C Co Oe am m DIP Switch SW1 L E e
110. bit would cause the Search command to search 8 words from the starting address data The value s to search the display buffer for Values can be combinations of text or numbers Numbers are assumed to be hexadecimal values unless otherwise specified with the correct suffix binary 1 octal 0 decimal t hexadecimal h For example 101i 101 binary Show Shows a test pattern on the display The test pattern is based on current register settings and may not display correctly if the registers are not configured properly Use this command to display an image during testing After adjusting a register value use the show command to view the effect on the display 13A04PLAY Diagnostic Utility Issue Date 01 10 05 Epson Research and Development Page 9 Vancouver Design Center U index data Reads writes data to the USB register at index If no data is specified the command reads and displays the contents from the USB register at index Where index Index into the USB registers hex data The value to be written to the register Numbers are assumed to be hexadecimal values unless otherwise specified with the correct suffix binary i octal o decimal t hexadecimal h For example 101i 101 binary UA Reads and displays the contents of all the USB registers UX index data This command automates the writes reads into the indexed USB registers located at REG 4038h and REG 403Ah Index represents the value tha
111. bit read 1 1 0 1 valid 8 bit read data on low byte even byte address 1 1 1 0 valid 8 bit read data on high byte odd byte address Table 6 7 Generic 1 Interface Truth Table for Big Endian WEO WE1 RDO RD1 D 15 8 D 7 0 Comments 0 0 1 1 valid valid 16 bit write valid 8 bit write data on low byte odd byte address valid 8 bit write data on high byte even byte address valid valid 16 bit read valid 8 bit read data on low byte odd byte address ajajalo oa 1 1 0 0 1 Olalo al o valid 8 bit read data on high byte even byte address 1 Because AO is not used internally all addresses are seen by the S1D13A04 as even addresses 16 bit word address aligned on even byte addresses Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 S1D13A04 X37A A 001 06 Page 38 Epson Research and Development Vancouver Design Center 6 2 2 Generic 2 Interface Timing e g ISA TBuscLk BUSCLK ti t7 lt gt gt A 16 0 M R BHE n Ss t2 t8 lt _ _ gt CS 14 gl i 19 ig lt gt P E t10 WE RD M o t11 t4 lt _ gt 4 WAIT t6 t12 gt aa D 15 0 write valid j t5 t13 HF D 15 0 read ea as Figure 6 3 Generic 2 Interface Timing S1D13A04 Hardware Functional Specificatio
112. bit to enable chip select The following options were selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits S1D13A04 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by clock cycle from address lines BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below SETA 1 the 1D13A04 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC82x Microprocessor S1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 20 Epson Research and Development Vancouver Design Center 4 6 Test Software The test software to exercise this interface is very simple It configures chip select 4 CS4 on the MPC82x to map the 1D13A04 to an unused 512K byte block of address space and loads the appropriate values into the option register for CS4 Then the software runs a tight loop reading the S1D13A04 Revision Code Register REG OOh This allows monitoring of the bus timing on a logic analyzer The following source code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board Once the program was executed on the ADS a logic an
113. bus interface clock BCLK The BCLK source is always CLKI Specifies the divide ratio for the clock source The divide ratio is applied to the BCLK source to derive BCLK This field shows the actual BCLK frequency used by the configuration process These settings select the clock source and input clock divisor for the internal memory clock MCLK For the best performance MCLK should be set as close to the maximum 50 MHz as possible The MCLK source is always BCLK Specifies the divide ratio for the clock source The divide ratio is applied to the MCLK source to derive MCLK This divide ratio should be left at 1 1 unless the resultant MCLK is greater that SOMHz This field shows the actual MCLK frequency used by the configuration process 13A04CFG Configuration Program Issue Date 01 10 19 Epson Research and Development Page 13 Vancouver Design Center PWMCLK Enable Force High Source Divide Timing Duty Cycle These controls configure various PWMCLK settings The PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel When this box is checked the PWMCLK circuitry is enabled The signal PWMOUT is forced high when this box is checked When not checked PWMOUT will be low if PWM is not enabled or will change state according to the configured values when PWM is enabled Selects the PWMCLK source Possible sources include CLKI CLKI2 MCLK and PCLK Specifi
114. bytes respectively Both signals are driven low by OE when the Motorola MPC82x is reading data from the S1D13A04 WAIT connects to TA and is a signal which is output from the S1D13A04 which indi cates the MPC82x must wait until data is ready read cycle or accepted write cycle on the host bus Since MPC82x accesses to the S1D13A04 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal is not used in this implementation of the MPC82x interface using the Generic 1 Host Bus Interface This pin must be tied high connected to IO Vpp Interfacing to the Motorola MPC82x Microprocessor Issue Date 01 10 05 Epson Research and Development Page 15 Vancouver Design Center 4 MPC82x to S1D13A04 Interface 4 1 Hardware Description The interface between the S1D13A04 and the MPC82x requires no external glue logic The polarity of the WAIT signal must be selected as active high by connecting CNF5 to IO Vpp see Table 4 2 Summary of Power On Reset Options on page 18 BS bus start is not used in this implementation and should be tied high connected to IO Vpp The following diagram shows a typical implementation of the MPC82x to S1D13A04
115. circuitry For this example M R is connected to address line A18 allowing system address A18 to select between memory or register accesses WEO0 connects to LWE the low data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the low byte of a 16 bit device WEI1 connects to UWE the upper data byte write strobe enable of the MC68VZ328 and is asserted when valid data is written to the high byte of a 16 bit device RD connects to OE the read output enable of the MC68VZ328 and is asserted during a read cycle of the MC68VZ328 microprocessor RD WRF is not used for the Dragonball host bus interface and must be tied high to IO Vpp WAIT connects to DTACK and is a signal which is output from the S1D13A04 indi cating the MC68VZ328 must wait until data is ready read cycle or accepted write cycle on the host bus MC68VZ328 accesses to the S1D13A04 may occur asynchro nously to the display update BS is not used for the Dragonball host bus interface and must be tied high to IO Vpp Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 4 MC68VZ328 to S1D13A04 Interface 4 1 Hardware Description The interface between the S1D13A04 and the MC68VZ328 does not requires any external glue logic Chip select module B is used to provide the S1D13A04 with a chip select and A18 is used to select between mem
116. clock see Section 7 1 4 PWMCLK on page 86 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 89 Vancouver Design Center 8 Registers This section discusses how and where to access the 1D13A04 registers It also provides detailed information about the layout and usage of each register 8 1 Register Mapping The S1D13A04 registers are memory mapped When the system decodes the input pins as CS 0 and M R 0 the registers may be accessed The register space is decoded by AB 16 0 and is mapped as follows Table 8 1 SIDI3A04 Register Mapping M R Address Size Function 1 00000h to 28000h 160K bytes SRAM memory 0 0000h to 0088h 136 bytes Configuration registers 0 4000h to 4054h 84 bytes USB registers 0 8000h to 8019h 25 bytes 2D Acceleration Registers 0 10000h to 1FFFEh 65536 bytes 64K bytes 2D Accelerator Data Port 8 2 Register Set The S1D13A04 register set is as follows Table 8 2 SIDI3A04 Register Set Register Pg Register Pg REG 00h Product Information Register 91 REG 04h Memory Clock Configuration Register 92 REG 08h Pixel Clock Configuration Register 92 REG OCh Panel Type amp MOD Rate Register 93 REG 10h Display Settings Register 94 REG 14h Power Save Configuration Register 96 REG 18h Look Up Table Write Register 98 REG 1Ch Look Up Table R
117. co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Page 33 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg S1D13A04 X37A G 004 02 Page 34 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Document Number X37A G 002 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your
118. disable the use of off screen memory edit the file x wince300 platform cepc driv ers display S 1D13A04 sources In SOURCES there is a line which when uncom mented will instruct Windows CE to use off screen display memory if sufficient display memory is available CDEFINES CDEFINES DEnablePreferVmem In the file PROJECT REG under CE 3 0 there is a key called PORepaint search the Windows CE directories for PROJECT REG PORepaint is relevant when the Sus pend state is entered or exited PORepaint can be set to 0 1 or 2 as described below a PORepaint 0 This mode tells Windows CE not to save or restore display memory on sus pend or resume Since display data is not saved and not repainted this is the FASTEST mode Main display data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running Off screen data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running This mode cannot be used if power to the display memory is turned off b PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display data to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is LOST when suspended Therefore off screen memory usage must eith
119. driver configuration as described below in Description of Windows CE Display Driver Issues Description of Windows CE Display Driver Issues The following are some issues to consider when configuring the display driver to work with Windows CE 1 When Windows CE enters the Suspend state power off the LCD controller and dis play memory may lose power depending on how the OEM sets up the system If dis play memory loses power all images stored in display memory are lost If power off power on features are required the OEM has several options e If display memory power is turned off add code to the display driver to save any images in display memory to system memory before power off and add code to restore these images after power on If display memory power is turned off instruct Windows CE to redraw all images upon power on Unfortunately it is not possible to instruct Windows CE to redraw any off screen images such as icons slider bars etc so in this case the OEM must also configure the display driver to never use off screen memory e Ensure that display memory never loses power Windows CE 3 x Display Driver S1D13A04 Issue Date 01 10 19 X37A E 006 01 Page 12 S1D13A04 X37A E 006 01 Epson Research and Development Vancouver Design Center Using off screen display memory significantly improves display performance For ex ample slider bars appear more smooth when using off screen memory To enable or
120. follows represents len or the number of bytes words dwords to be filled Len is based on the unit size For example L8 when the unit size is 16 bit would cause the Fill command to fill 8 words from the starting address data The value s used to fill the display buffer If multiple values are given the pattern repeats through memory Values can be combinations of text or numbers Numbers are assumed to be hexadecimal values unless otherwise specified with the correct suffix binary 1 octal 0 decimal t hexadecimal h For example 101i 101 binary H lines Sets the number of lines of data that are displayed at a time The display is halted after the specified number of lines Setting the number of lines to O disables the halt function and allows the data to continue displaying until all data has been shown This command is useful when large blocks of the display buffer or the contents of the LUT are being viewed Where lines Number of lines that are shown before halting the displayed data decimal value I Initializes the S1D13A04 registers with the default register settings as configured by the utility 13A04CFG To initialize the S1D13A04 with different register values reconfigure 13A04PLAY using 13A04CFG For further information on 13A04CFG see the 13A04CFG User Manual document number X37A B 001 xx Note If the TP command is used before 13 A04PLAY is configured an error message is dis played and no
121. for Slow CPU Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 110 Epson Research and Development Vancouver Design Center 10 4 4 EP2 Valid Bit in USB Status can be erroneously set by firmware Endpoint 2 Valid is the only bit in USB Status which is not written as a Yes CLR bit Therefore the firmware must do a read modify write sequence when clearing other bits in Interrupt Status Register 0 REG 4004h to preserve the state of Endpoint 2 Valid However this read modify write could lead to erroneously setting the EP2 Valid bit if the following sequence occurs with EP2 Valid set True 1 Firmware reads Interrupt Status Register 0 to do a read modify write 2 Data from EP2 is sent to Host PC causing S1D13A04 to clear EP2 Valid 3 Firmware writes modified value to Interrupt Status Register 0 In this case the firmware has set EP2 Valid in Step 3 after it was cleared by the Host PC erroneously validating EP2 for the next IN token from the Host Work Around First the firmware should do the read modify write operation as described above anytime it is modifying bits in USB Status Second when the firmware recognizes an interrupt for EP2 Packet Transmitted it should immediately write a 0 to USB Status Register This will clear the EP2 Valid bit in the unlikely event that it was erroneously set during a read modify write operation 10 4 5 Setting E
122. from the beginning of one display line to the beginning of the next display line in the main window Note that this is a 32 bit address increment Calculate the Line Address Offset as follows REG 44h bits 9 0 display width in pixels 32 bpp Note A virtual display can be created by programming this register with a value greater than the formula requires When a virtual display is created the image width is larger than the display width and the displayed image becomes a window into the larger virtual image 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 105 Vancouver Design Center 8 3 6 Picture in Picture Plus PIP Registers PIP Display Start Address Register REG 50h Default 00000000h Read Write bit 16 PIP Display Start Address bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits 16 0 PIP Display Start Address Bits 16 0 These bits form the 17 bit address for the starting double word of the PIP window Note that this is a double word 32 bit address An entry of 00000h into these registers represents the first double word of display memory an entry of 00001h represents the sec ond double word of the display memory and so on Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 10h bit 19 PIP Line Address Offset Register REG 54h Default 00000000h Read Write 22 21 20 19 18 17 16
123. interface MPC82x 1D13A04 A 14 31 gt AB 17 0 D O 15 y gt DB 15 0 CS4 CS A13 gt M R IO Vop L Bs TA lt WAIT WEO gt WE1 WE1 gt WEO OE gt RD WR gt RD SYSCLK gt CLKI System RESET RESET Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MPC82x to SID13A04 Interface Table 4 1 List of Connections from MPC821ADS to SIDI3A04 on page 16 shows the connections between the pins and signals of the MPC82x and the S1D13A04 Interfacing to the Motorola MPC82x Microprocessor 1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 16 Epson Research and Development Vancouver Design Center Note The interface was designed using a Motorola MPC821 Application Development System ADS The ADS board has 5 volt logic connected to the data bus so the interface included two 74F245 octal buffers on D 0 15 between the ADS and the S1D13A04 In a true 3 volt system no buffering is necessary 4 2 MPC821ADS Evaluation Board Hardware Connections 1D13A04 X37A G 009 01 The following table details the connections between the pins and signals of the MPC821 and the S1D13A04 Table 4 1 List of Connections from MPC821ADS to SIDI3A04
124. line width defined by the line address offset register i e starting at horizontal position 0 A right justified image is one drawn in display memory such that each of the image s lines only use the right most portion of the line width defined by the line address offset register i e starting at a non zero horizontal position which is the virtual width image width 7 3 2 SwivelView 90 and 270 1D13A04 X37A G 003 05 In Swivel View 90 and 270 the Main Window Line Address Offset register REG 44h requires the panel height to be a multiple of 32 bits per pixel If this is not the case then the Main Window Line Address Offset register must be programmed to a longer line which meets this requirement This longer line creates a virtual image whose width is main window line address offset register X 32 bits per pixel In SwivelView 270 this virtual image should be drawn in display memory as left justified and in Swivel View 90 this virtual image should be drawn in display memory as right justified A left justified image is one drawn in display memory such that each of the image s lines only use the left most portion of the line width defined by the line address offset register i e starting at horizontal position 0 A right justified image is one drawn in display memory such that each of the image s lines only use the right most portion of the line width defined by the line address offset register i e starting at a non
125. of frame packet Extended Register Index REG 4038h Default 00h Read Write n a Extended Register Index bits 7 0 bits 7 0 Extended Register Index Bits 7 0 This register selects which extended data register is accessed when the REG 403Ah is read or written Extended Register Data REG 403Ah Default 04h Read Write 15 14 13 12 11 10 9 8 7 6 5 0 Extended Data bits 7 0 4 3 2 1 bits 7 0 Extended Data Bits 7 0 This port provides access to one of the extended data registers The index of the current register is held in REG 4038h Vendor ID MSB REG 403Ah Index 00h Default 04h Read Write Vendor ID bits 15 8 7 6 5 4 3 2 1 0 Vendor ID LSB REG 403Ah Index 01h Default B8h Read Write Vendor ID bits 7 0 7 6 5 4 3 2 1 0 bits 15 0 Vendor ID Bits 15 0 These registers determine the Vendor ID returned in a Get Device Descriptor request 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 127 Vancouver Design Center Product ID MSB REG 403Ah Index 02h Default 88h Read Write Product ID bits 15 8 7 6 5 4 3 2 1 0 Product ID LSB REG 403Ah Index 03h Default 21h Read Write Product ID bits 7 0 7 6 5 4 3 2 1 0 bits 15 0 Product ID Bits 15 0 These registers determine the Product ID returned in a Get Device Descriptor request Release Number MSB REG 403Ah Index 04h Default 01h Read Write
126. on our documentation Please contact us via email at documentation erd epson com Interfacing to the PC Card Bus S1D13A04 Issue Date 01 10 12 X37A G 005 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 archi tecture which address peripherals independently from memory space Bit notation follows the convention used by most microprocessors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further
127. own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X37A G 002 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A IMPOQUCHON a Bae a a ARABIA a a A Sete 7 2 Interfacing to the TMPR3905 12 o 8 2 1 The Toshiba TMPR3905 12 System Bus a a a a a a ee eee ee 8 ZN SONERVIEW rta de a hes Bae aed Ha eat da ts 8 2 12 Card Access Cycles 2 5 endine Gece Roe ow Re a Ee a ee Pe eee aa 8 3 1D13A04 Host Bus Interface ee es 10 3 1 Host Bus Interface Pin Mapping LO 3 2 Host Bus Interface Signals Eur Grete MS ely ard oh tao te Ah 4 Toshiba TMPR3905 12 to S1D13A04 Interface 12 4 1 Hardware Description O 42 S1D13A04 Hardware Configuration ip e ERIE eh wh d ee A 4 3 Memory Mapping and Aliasing
128. owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Wind River WindML v2 0 Display Drivers X37A E 002 01 Issue Date 01 09 28 Epson Research and Development Page 3 Vancouver Design Center Wind River WindML v2 0 DISPLAY DRIVERS The Wind River WindML v2 0 display drivers for the S1D13A04 LCD USB Companion Chip are intended as reference source code for OEMs developing for Wind River s WindML v2 0 The driver package provides support for both 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13A04 Source code modification is required to produces a smaller more efficient driver for mass production The WindML display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13A04CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13A04CFG see the 3A04CFG Configuration Program User Manual document number X37A B 001 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to develop their own drivers for WindML v2 0 These drivers are not backwards compatible with UGL v1 2 For information on UGL v1 2 display drivers contact us via email at erdvdcsw_info erd epson co
129. posi tion is controlled by the LUT Read Address bits bits 31 24 This is a read only register bits 15 10 LUT Green Read Data Bits 5 0 Read Only These bits point to the data from the green component of the Look Up Table The LUT position is controlled by the LUT Read Address bits bits 31 24 This is a read only regis ter bits 7 2 LUT Blue Read Data Bits 5 0 Read Only These bits point to the data from the blue component of the Look Up Table The LUT position is controlled by the LUT Read Address bits bits 31 24 This is a read only regis ter Hardware Functional Specification 1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 100 Epson Research and Development Vancouver Design Center 8 3 5 Display Mode Registers Horizontal Total Register REG 20h Default 00000000h Read Write 16 Horizontal Total bits 6 0 bits 6 0 Horizontal Total Bits 6 0 These bits specify the LCD panel Horizontal Total period in 8 pixel resolution The Hori zontal Total is the sum of the Horizontal Display period and the Horizontal Non Display period Since the maximum Horizontal Total is 1024 pixels the maximum panel resolu tion supported is 800x600 REG 20h bits 6 0 Horizontal Total in number of pixels 8 1 Note l For all panels this register must be programmed such that HDPS HDP lt HT HT HDP 8MCLK 2 For passive panels this register must be programmed such that HPS HPW lt HT 3 See Section
130. s top edge Increasing y moves the top edge downwards in 1 line steps The vertical coordinates start at line 0 Program the PIP Window Y End Position so that PIP Window Y End Position panel height y 1 In SwivelView 270 these bits set the horizontal coordinates x of the PIP window s right edge Increasing x moves the right edge towards the right in steps of 32 bits per pixel see Table 8 3 The horizontal coordinates start at pixel 0 Program the PIP Window Y End Position so that PIP Window Y End Position x 32 bits per pixel Note Truncate the fractional part of the above equation Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 44 PIP Y Start Position 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center The PIP Y Start Position bits determine the vertical start position of the PIP window in 0 and 180 Swivel View orientations These bits determine the horizontal start position in 90 and 270 SwivelView For further information on defining the value of the Y Start Position see Section 8 2 Picture In Picture Plus Examples on page 45 The register also increments differently based on the SwivelView orientation For 0 and 180 SwivelView the Y Start Position is incremented in 1 line increments For 90 and 270 Swivel View the Y Start Position is incremented by Y pixels where Yis relative to the current color dep
131. selected REG OCH bits 1 0 and GPIO3 is configured as an input a read from this bit returns the status of GPIO3 When the Direct HR TFT LCD interface is enabled REG OCh bits 1 0 10 GPIOO outputs the SPL signal automatically and writing to this bit has no effect bit 2 GPIO2 Pin IO Status When the Direct HR TFT LCD interface is not selected REG OCh bits 1 0 and GPIO2 is configured as an output writing a 1 to this bit drives GPIO2 high and writing a 0 to this bit drives GPIO2 low When the Direct HR TFT LCD interface is not selected REG OCh bits 1 0 and GPIO2 is configured as an input a read from this bit returns the status of GPIO2 When the Direct HR TFT LCD interface is enabled REG OCh bits 1 0 10 GPIOO outputs the REV signal automatically and writing to this bit has no effect bit 1 GPIO1 Pin IO Status When the Direct HR TFT LCD interface is not selected REG OCh bits 1 0 and GPIO1 is configured as an output writing a 1 to this bit drives GPIO1 high and writing a 0 to this bit drives GPIO1 low When the Direct HR TFT LCD interface is not selected REG OCh bits 1 0 and GPIO1 is configured as an input a read from this bit returns the status of GPIO1 When the Direct HR TFT LCD interface is enabled REG OCh bits 1 0 10 GPIOO outputs the CLS signal automatically and writing to this bit has no effect bit O GPIOO Pin IO Status When the Direct HR TFT LCD interface is not selected REG O
132. stored in Windows BMP file format and then exits 13A04BMP supports SviwelView 90 180 and 270 hardware rotation of the display image 13A04BMP is designed to operate on a personal computer PC within a 32 bit environment only Windows 9x NT ME 2000 Other embedded platforms are not supported due to the possible lack of system memory or structured file system The 13A04BMP demonstration utility must be configured to work with your hardware configuration The program 13A04CFG can be used to configure 13A04BMP For further information on 13A04CFG refer to the 3AO4CFG Users Manual document number X37A B 001 xx 1D13A04 Supported Evaluation Platforms 13A04BMP supports the following S1D13A04 evaluation platforms e PC with an Intel 80x86 processor running Windows 9x NT ME 2000 Note The 13A04BMP source code may be modified by the OEM to support other evaluation platforms Installation Copy the file 13A04bmp exe to a directory in the path e g PATH C S1D13A04 13A04BMP Demonstration Program 1D13A04 Issue Date 01 10 04 X37A B 003 01 Page 4 Epson Research and Development Vancouver Design Center Usage At the prompt type 13A04bmp bmpfile Where bmpfile Specifies filename of the windows format bmp image to be displayed n Displays the help message Note 13A04BMP displays the bmpfile image and returns to the prompt 13A04BMP Examples To display a bmp image in the main window on an LCD ty
133. the Finish button In the dialog box New Platform Information click the OK button 5 Set the active configuration to Win32 WCE x86 Release a b c S1D13A04 X37A E 006 01 From the Build menu select Set Active Configuration Select MYPLATFORM Win32 WCE x86 Release Click the OK button Windows CE 3 x Display Driver Issue Date 01 10 19 Epson Research and Development Vancouver Design Center Page 5 6 Add the environment variable DDI_S1D13A04 a b d e f From the Platform menu select Settings Select the Environment tab In the Variable box type DDI_S1D13A04 In the Value box type 1 Click the Set button Click the OK button 7 Create a new directory S1D13A04 under x wince300 platform cepc drivers display and copy the S1D13A04 driver source code into this new directory 8 Add the S1D13A04 driver component a b c f From the Platform menu select Insert User Component Set Files of type to All Files Select the file x wince300 platform cepc drivers display S1D13A04 sources Click the OK button In the User Component Target File dialog box select browse and then select the path and the file name of sources as in step c Click the OK button 9 Delete the component ddi_flat a b Windows CE 3 x Display Driver Issue Date 01 10 19 In the Platform win
134. the USB host using bulk or isochronous transfers from endpoint 4 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 124 Epson Research and Development Vancouver Design Center Endpoint 4 Transmit FIFO Count Register REG 402Ah Default 00h Read Only a FIFO Count aS 7 0 bits 7 0 Transmit FIFO Count Bits 7 0 This register returns the number of transmit FIFO entries containing valid entries Values range from 0 empty to 64 full Endpoint 4 Transmit FIFO Status Register REG 402Ch Default 01h Read Write l ETET FIFO Transmit FIFO Transmit FIFO Reserved ET FIFO T FIFO Valid Flush Overflow Full read only Empty read only 0 bit 5 Transmit FIFO Valid If set this bit allows the data in the Transmit FIFO to be read by the next read from the host This bit is automatically cleared by a host read This bit is only used if bit O in USB 403Ah Index OCh is set bit 4 Transmit FIFO Flush Writing to this bit causes the transmit FIFO to be flushed Reading this bit always returns a 0 bit 3 Transmit FIFO Overflow If set this bit indicates that an attempt was made by the local CPU to write to the transmit FIFO when the transmit FIFO was full Writing a 1 clears this bit bit 2 Reserved bit 1 Transmit FIFO Full read only If set this bit indicates that the transmit FIFO is full bit O Transmit FIFO Empty read only If set this bit indicates that the tra
135. the unchanged bits and setting the appropriate bits to 1 One bit pixels provide 2 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first two elements of the green component of the Look Up Table LUT For color panels the 2 colors are derived by indexing into the first 2 positions of the LUT Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 15 Vancouver Design Center 4 3 Memory Organization for Two Bit per pixel 4 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 bits 1 0 bits 1 0 bits 1 0 bits 1 0 Figure 4 2 Pixel Storage for 2 Bpp in One Byte of Display Buffer At a color depth of 2 bpp each byte of display buffer contains four adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the unchanged bits and setting the appropriate bits to 1 Two bit pixels provide 4 gray shades color possibilities For monochrome panels the gray shades are generated by indexing into the first 4 elements of the green component of the Look Up Table LUT For color panels the 4 colors are derived by indexing into the first 4 positions of the LUT 4 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 bits 3 0
136. this implementation of a S1D13A04 to NEC VR4181A interface Table 4 1 Summary of Power On Reset Options S1D13A04 Configuration Input Power On Reset State 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 CNF3 Reserved Must be set to 1 CNF5 WAIT is active high CNF6 CLKI to BCLK divide ratio 2 1 configuration for NEC VR4181A microprocessor Interfacing to the NEC VR4181A Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 008 01 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4181A Configuration S1D13A04 X37A G 008 01 The S1D13A04 is a memory mapped device The S1D13A04 uses two 256K byte blocks which are selected using A18 from the NEC VR4181A A18 is connected to the S1D13A04 M R pin The internal registers occupy the first 256K byte block and the 160K byte display buffer occupies the second 256K byte block When the VR4181A embedded LCD controller is disabled the external LCD controller chip select signal LCDCS decodes either a 64K byte 128K byte 256K byte or 512K byte memory block in the VR4181A external ISA memory The S1D13A04 requires this block of memory to be set to 512K bytes With this configuration the S1D13A04 internal registers starting address is located at physical memory location 133C_0000h and the display buffer is located at memory location 1340_0000h The NEC VR4181A must be configured through its internal regist
137. to display the Open File Dialog Box Look in E s1d13a04 ej wl ex 13404cfg exe 13404play exe File name Files of type All Configurable Files exe s9 idp elf lvb p Y Cancel Zi The Open option allows 13A04CFG to read the configuration information from programs based on the HAL library When 13A04CFG opens a file it scans the file for an identifi cation string and if found reads the configuration information This feature may be used to quickly arrive at a starting point for register configuration The only requirement is that the file being opened must contain a valid 1D13A04 HAL library information block 13A04CFG supports a variety of executable file formats Select the file type s 13A04CFG should display in the Files of Type drop down list and then select the filename from the list and click on the Open button Note 13A04CFG is designed to work with utilities programmed using a given version of the HAL If the configuration structure contained in the executable file differs from the ver sion 13A04CFG expects the Open will fail and an error message is displayed This may happen if the version of 13A04CFG is substantially older or newer than the file being opened 13A04CFG Configuration Program Issue Date 01 10 19 1D13A04 X37A B 001 01 Page 24 Epson Research and Development Vancouver Design Center Save From the Menu Bar select File then Save to initiate the sav
138. to select the Read BitBLT REG 8008h bits 3 0 are set to 1h Program the BitBLT Color Format Select bit for 8 bpp operations REG 8000h bit 18 1s set to 0 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 2 160 A0h REG 8014h is set to OAOh Calculate the number of WORDS the BitBLT engine expects to receive WORDS BLTWidth 1 DestinationPhase 2 xBLTHeight 100 1 0 2 x20 1000 3E8h Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation and wait for the BitBLT engine to start REG 8000h bit 0 is set to 1 then wait until REG 8004h bit O returns a 1 Prior to reading from the BitBLT FIFO confirm the BitBLT FIFO is not empty REG 8004h bit 4 returns a 1 If the BitBLT FIFO Not Empty Status REG 8004h bit 6 returns a 1 and the BitBLT FIFO Half Full Status REG 8004h bit 5 returns a O then you can read up to 8 WORDS If the BitB LT FIFO Full Status returns a 1 read up to 16 WORDS If the BitBLT FIFO Not Empty Status returns a 0 the FIFO is empty do not read from the BitBLT FIFO until it returns a 1 The following table summarizes how many words can be read from the BitBLT FIFO Table 9 8 Possible BitBLT FIFO Reads BitBLT Status Register REG 8004h Word Reads FIFO Not Empty Status FIFO Half Fu
139. zero horizontal position which is the virtual width image width Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 37 Vancouver Design Center 8 Picture In Picture Plus Picture in Picture Plus PIP enables a secondary window or PIP window within the main display window The PIP window may be positioned anywhere within the virtual display and is controlled through the PIP Window control registers REG SOh through REG 5Ch The PIP window retains the same color depth and Swivel View orientation as the main window A PIP window can be used to display temporary items such as a dialog box or to float the display item so that the system doesn t have to exclude the area during screen repaints The following diagram shows an example of a PIP window within a main window 0 SwivelView main window PIP window Figure 8 1 Picture in Picture Plus with SwivelView disabled Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 38 Epson Research and Development Vancouver Design Center 8 1 Registers The following registers control the Picture In Picture Plus feature Display Settings Register REG 1 0h Default 00000000h Read Write Pixel Pixel i g P P Display Dithering Window SwivelView Mode Blank Disable Doubling Doubling Vertical Horiz Enable a 22 19 Bits per pixel Select a
140. 0 Note It is possible to use the same image for both the main window and PIP window To do so set the PIP Line Address Offset register REG 54h to the same value as the Main Window Line Address Offset register REG 44h S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 55 Vancouver Design Center Example 8 In SwivelView 270 program the PIP window registers for a 320x240 panel at 4 bpp with the PIP window positioned at SwivelView 270 co ordinates 60 80 with a width of 120 and a height of 160 1 Determine the value for the PIP Window X Positions and PIP Window Y Positions registers Let the top left corner of the PIP window be x1 y1 and let the bottom right corner be x2 y2 where x2 x1 width 1 and y2 y1 height 1 The PIP Window X Positions register sets the vertical coordinates of the PIP window s top right and bottom left corner The PIP Window Y Positions register sets the horizontal coordinates of the PIP window s top right and bottom left corner The required values are calculated as follows X Start Position panel width y2 1 320 80 160 1 1 80 50h Y Start Position x1 32 bpp 60 32 4 7 5 07h truncated fractional part X End Position panel width y1 1 320 80 1 239 EFh Y End Position x2 32 bpp 60 120 1 32 4 22 375 16h trun
141. 0 1 For SwivelView 90 and 270 PIP Width REG 5Ch bits 25 16 REG 5Ch bits 9 0 1 x 32 bpp PIP Height REG S58h bits 25 16 REG 58h bits 9 0 1 Note Image width can be larger than PIP width or PIP height for Swivel View 90 or 270 number of dwords per line image width 32 bpp Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 40 Epson Research and Development Vancouver Design Center PIP X Positions Register REG 58h Default 00000000h Read Write PIP X End Position bits 9 0 21 PIP X End Position The PIP X End Position bits determine the horizontal end of the PIP window in 0 and 180 SwivelView orientations These bits determine the vertical end position in 90 and 270 Swivel View For further information on defining the value of the X End Position see Section 8 2 Picture In Picture Plus Examples on page 45 This register also increments differently based on the SwivelView orientation For 0 and 180 SwivelView the X End Position is incremented by X pixels where X is relative to the current color depth For 90 and 270 SwivelView the X End Position is incremented in 1 line increments Table 8 1 32 bit Address Increments for PIP X Position in SwivelView 0 and 180 Bits Per Pixel Color Depth Pixel Increment X 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 In SwivelView 0 these bits se
142. 0 gt i ADDRESS VALID nCS4 nWE nOE RDY D 31 0 DATA VALID nCAS 3 0 Figure 2 2 SA 1110 Variable Latency IO Write Cycle 1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the SA 1110 The Generic 2 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on S1D13A04 configuration see Section 4 2 S DI3A04 Hardware Configu ration on page 14 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping S1D13A04 Pin Name SA 1110 AB 17 0 A 17 0 DB 15 0 D 15 0 WE1 nCAS1 M R A18 CS nCS4 CLKI SDCLK2 BS Connect to lOypp from the S1D13A04 RD WR Connect to lO ypp from the S1D13A04 RD nOE WE0 nWE WAIT RDY RESET system RESET Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 12 Epson Research and Development Vancouver
143. 0 1 USBCLK 48 2D BitBLT engine running 18 bit CLKI 33 3 MCLK BCLK HA TFT 67 CLKI2 3 PCLK 16 12 4 1 6 9 gt 0 1 USBCLK 48 USB is active running The S1D13A04 has Power Save Mode enabled but the clocks CLKI CLKI2 and USBCLK remain active unless specified otherwise 2 CLKI CLKI2 and USBCLK are grounded for the Clocks Removed condition This test has the 2D BitBLT engine performing a Move BitBLT which requires a high level of CPU activity and a rapidly updating display This test has the 1D13A04 USB module running a loop back test This result is not applicable See the 16 bpp color depth results for power save mode W Hi Power Consumption S1D13A04 Issue Date 01 10 29 X37A G 006 01 Page 6 Epson Research and Development Vancouver Design Center 2 Summary The system design variables in Section 1 S1D13A04 Power Consumption and in Table 1 1 S1D13A04 Total Power Consumption for 320x240 panels show that S1D13A04 power consumption depends on the specific implementation Active Mode power consumption depends on the desired CPU performance and LCD frame rate whereas power save mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the S1D13A04 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility S1D13A04 Power Consumption X37A G 006 01 Issue Date 01 10
144. 0 devg 4 Unpack the display driver files using the commands gunzip S1D13A04 tar gz tar xvf S1D13A04 tar This unpacks the files into the directory Project gddk_1 0 devg S1D13A04 Configure the Driver The files s1d13A04_16 h and s1d13A04_8 h contain register values required to set the screen resolution color depth bpp display type rotation etc The s1d13A04 h file included with the drivers may not contain applicable values and must be regenerated The configuration program 13A04CFG can be used to build new s1d13A04_16 h and s1d13A04_8 h files Note S1d13A04 h should be created using the configuration utility 13A04CFG For more in formation on 13A04CFG see the 13A04CFG Configuration Program User Manual document number X37A B 001 xx available at www erd epson com Build the Driver The first time the driver is built the following command ensures that all drivers and required libraries are built At the root of the Project source tree type make Note To build drivers for X86 NTO type OSLIST nto CPULIST x86 make Further builds do not require all libraries to be re built To build only the S1D13A04 display driver change to the directory gddk_1 0 devg s1d13A04 and type make QNX Photon v2 0 Display Driver Issue Date 01 10 19 Epson Research and Development Page 5 Vancouver Design Center Installing the Driver The build step produces two library images e lib disputil nto x86 libdisputil so e lib disputil nto
145. 00 5 3 206 4 221 2 4 Parameter RDNx lt 4 0 gt should be set to 0 minimum command precharge time Parameter RRRx lt 2 0 gt should be set to 0 minimum nCSx precharge time The S1D13A04 endian mode is set to little endian To program the SA 1110 for little endian set bit 7 of the control register register 1 to 0 The CLKI signal input to the S1D13A04 from one of the SDCLK 2 1 pins is a deriva tive of the SA 1110 internal processor speed either divide by 2 or 4 The S1D13A04 Generic 2 Host Bus Interface has a maximum BCLK of 50MHz Therefore if the processor clock is higher than 1OOMHz either divide the BCLK input using the S1D13A04 configuration pin CNF6 see Table 4 1 Summary of Power On Reset Options or set SDCLK1 SDCLK2 to CPU clock divided by four using the DRAM Refresh Control Register MDREFR bit 26 1 for SDCLK2 MDREFR bit 22 1 for SDCLK1 Interfacing to the Intel StrongARM SA 1110 Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 16 Epson Research and Development Vancouver Design Center 4 4 Register Memory Mapping The S1D13A04 is a memory mapped device The SA 1110 uses the memory assigned to a chip select nCS4 in this example to map the S1D13A04 internal registers and display buffer The S1D13A04 uses two 256K byte blocks which are selected using A18 from the SA 1110 A18 is connected to the S1D13A04 M R pin The internal registers occupy the first 256K bytes block and
146. 000 microprocessor core and uses a 24 bit address bus and 16 bit data bus The Dragonball VZ is faster than its predecessors and the DRAM controller now supports SDRAM The bus interface consists of all the standard MC68000 bus interface signals except AS plus some new signals intended to simplify the interface to typical memory and peripheral devices The 68000 signals are multiplexed with IrDA SPI and LCD controller signals The MC68000 bus control signals are well documented in the Motorola user manuals and are not be described here The new signals are as follows e Output Enable OE is asserted when a read cycle is in progress It is intended to connect to the output enable control signal of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus They may be directly connected to the write enable inputs of a typical memory device 2 2 Chip Select Module 1D13A04 X37A G 012 01 The MC68VZ328 can generate up to 8 chip select outputs which are organized into four groups A through D Each chip select group has a common base address register and address mask register allowing the base address and block size of the entire group to be set In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s
147. 01 10 29 X37A G 006 01 Page 4 1 1 Conditions Epson Research and Development Vancouver Design Center The following table provides an example of some 320x240 panels and the effects on power consumption of specific environments The following conditions apply e All tests had an appropriate LCD panel connected to the LCD outputs of the S1D13A04 e All tests were run with a static full color palette display e All tests were done using the Generic 1 host bus interface BCLK 33MHz Table 1 1 SIDI3A04 Total Power Consumption for 320x240 panels Test Condition Power Consumption mA All COREVpp 2 0V and IOV pp 3 3V pd Power Save Mode Panel Frame Color 1 1 Clocks Resolution Type Rate Clocks MHz Depth CORE 10 CORE IO Removed 67 CLKI 6 BCLK MCLK 4 1 7 0 7 0 7 0 1 0 1 67 CLKI2 6 PCLK 8 2 1 0 7 0 7 0 1 0 1 Color 8 bit 67 USBCLK 48 16 2 4 0 6 0 7 0 1 0 1 Formata CLKI 6 BCLK 67 CLKI2 6 PCLK 8 1 8 0 6 0 4 0 0 0 1 USBCLK grounded CLKI 33 3 MCLK BCLK 94 CLKI2 grounded 8 4 3 1 3 2 3 0 2 0 1 USBCLK 48 PCLK MCLK 4 320x240 Color 4 bit CLKI 33 3 MCLK BCLK 94 CLKI2 grounded 8 4 0 1 2 2 1 0 1 0 1 USBCLK grounded PCLK MCLK 4 CLKI 33 3 MCLK BCLK 79 CLKI2 grounded 8 37 2 9 2 3 0 2 0 1 USBCLK 48 PCLK MCLK 4 18 bit TFT CLKI 33 3 MCLK BCLK 79 CLKI2 grounded 8 3 5 2 8 2 1 0 1 0 1 USBCLK grounded PCLK
148. 0h Read Write Endpoint 1 Index bits 2 0 i Receive Mailbox Data Register Default 00h Read Only Index Registe Default 00h Transmit Mailbox Data Register Default 00h Endpoint 2 Transmit Mailbox Data bits 7 0 5 4 3 2 Interrupt Polling Interval Register Default FFh Endpoint 2 Interrupt Polling Interval bits 7 0 5 4 3 Receive FIFO Data Register Default 00h Endpoint 3 Receive FIFO Data bit 4 3 Receive FIFO Count Register Default 00h Endpoint 3 Receive FIFO Count bits 7 0 5 4 3 Endpoint 3 Receive FIFO Status Register REG 4024h Default 01h Read Write Receive Receive meree Receive Reserved FIFO FIFO Full eS FIFO Flush Sue Undertlow readonly ead only 1 0 Endpoint 3 Maximum Packet Size Register REG 4026h Default 08h Read Write Endpoint 3 Max Packet Size bits 4 3 Transmit FIFO Data Register Default 00h oint 4 Transmit FIFO Data bits 7 0 4 3 Transmit FIFO Count Register Default 00h Endpoint 4 Transmit FIFO Count bits 7 0 5 4 3 1D13A04 Register Summary X37A R 001 01 Issue Date 01 10 02 Epson Research and Development Page 5 Vancouver Design Center Endpoint 4 Transmit FIFO Status Register REG 402Ch Default 01h Read Write Transmit Transmit Tansmi Transmit q Transmit FIFO Reserved FIFOFul FFO FIFO Valid FIFO Flush Empty Overflow read only read only 3 1 0 En
149. 13A04 Issue Date 01 10 12 X37A G 011 01 Page 12 2 3 S1D13A04 to LQ039Q2DS01 Pin Mapping Epson Research and Development Vancouver Design Center Table 2 2 SIDI3A04 to LQO39Q2DSO01 Pin Mapping LCDPin LCD Pin S1D13A04 Des ribtior Remark No Name Pin Name p Senne 1 VDD Power supply of gate driver high level ane Bag Kowe 2 VCC Power supply of gate driver logic high cc oe Rowe 3 MOD Control signal of gate driver See Section 2 2 RAE MOD Signal on page 11 4 MOD Control signal of gate driver See econ RAE MO Signal on page 11 5 U L Selection for vertical scanning direction Connect to VSHD top bottom scanning 6 SPS FPFRAME Start signal of gate driver 7 CLS GPIO1 Clock signal of gate driver 8 VSS Power supply of gate driver logic low el se ternal Power 9 VEE E Power supply of gate driver low level lero ri BOWS 10 VEE Power supply of gate driver low level nae eae rower 11 VCOM Common electrode driving signal Sea ee EOWer 12 VCOM Common electrode driving signal a hr i Fower 13 SPL GPIO3 Sampling start signal for left right scanning 14 RO FPDAT11 Red data signal LSB 15 R1 FPDAT10 Red data signal 16 R2 FPDAT9 Red data signal 17 R3 FPDAT2 Red data signal 18 R4 FPDAT1 Red data signal 19 R5 FPDATO Red data signal MSB 20 GO FPDAT14 Green data signal LSB 21 G1 FPDAT13 Green data signal 22 G2
150. 13A04 RD MEMRD WE0 MEMWR WAIT IORDY RESET RESET 1D13A04 Interfacing to the NEC VR4181A Microprocessor X37A G 008 01 Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The interface requires the following signals CLKI is a clock input which is required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example SYSCLK from the NEC VR4181A is used for CLKI The address inputs AB 17 0 and the data bus DB 15 0 connect directly to the NEC VR4181A address A 17 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS must be driven low by LCDCS whenever the S1D13A04 is accessed by the VR4181A M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address line A18 allowing system address A18 to select between memory or register accesses WE1 connects to UBE the high byte enable signal from the NEC VR4181A which in conjunction with address bit 0 allows byte steering of read and write operations WEO connects to MEMWR the write enable signal from the NEC VR4181A and must be driven low when the NEC VR4181A is writing data to the S1D13A04 RD connects to MEMRD the read ena
151. 13A04 to Motorola MPC82x microprocessor Table 4 2 Summary of Power On Reset Options S1D13A04 Power On Reset State Configuration Input 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 CNF3 Reserved Must be set to 1 CNF5 WAIT is active low CNF6 CLKI to BCLK divide ratio 2 1 EA configuration for Motorola MPC82x microprocessor 4 4 Register Memory Mapping The DRAM on the MPC821 ADS board extends from address O through 3F FFFFh so the 1D13A04 is addressed starting at 40 0000h The S1D13A04 uses two 256K byte blocks which are selected using A13 from the MPC821 A13 is connected to the S1D13A04 M R pin The internal registers occupy the first 256K byte block and the 160K byte display buffer occupies the second 256K byte block S1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 19 Vancouver Design Center 4 5 MPC82x Chip Select Configuration Chip select 4 is used to control the S1D13A04 The following options are selected in the base address register BR4 e BA 0 16 0000 0000 0100 0000 0 set starting address of S1D13A04 to 40 0000h e AT 0 2 0 ignore address type bits e PS 0 1 1 0 memory port size is 16 bits e PARE 0 disable parity checking e WP 0 disable write protect e MS 0 1 0 0 select General Purpose Chip Select module to control this chip select e V 1 set valid
152. 13A04B00C Rev 1 0 Evaluation Board User Manual 1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the SSU13A04BO0C Rev 1 0 Evaluation Board The board is designed as an evaluation platform for the S1ID13A04 LCD USB Companion Chip This user manual is updated as appropriate Please check the Epson Research and Devel opment Website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 8 2 Features 1D13A04 X37A G 004 02 Epson Research and Development Vancouver Design Center Following are some features of the S5U13A04B00C Rev 1 0 Evaluation Board 121 pin PFBGA S1D13A04 Embedded Memory LCD Controller with 160K bytes of embedded SRAM PCI bus operation through onboard PCI bridge CPU Bus interface header strips for non PCI bus operation Configuration options On board adjustable positive LCD bias power supply from 23V to 40V On board adjustable negative LCD
153. 17 0 DB 7 0 connects D 23 16 the MCF5307 low order byte DB 15 8 connects to D 31 24 the MCF5307 high order byte CNF4 must be set to select big endian mode Chip Select CS must be driven low by CS4 whenever the S1D13A04 is accessed by the Motorola MCF5307 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address line A18 allowing system address A18 to select between memory or register accesses WEO connects to BWEO the low byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the low byte to the S1D13A04 WEIl connects to BWE1 the high byte enable signal from the MCF5307 and must be driven low when the MCF5307 is writing the high byte to the S1D13A04 RD and RD WR are read enables for the low order and high order bytes respectively Both signals are driven low by OE when the Motorola MCF5307 is reading data from the S1D13A04 WAIT connects to TA and is a signal which is output from the S1D13A04 that indi cates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13A04 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the
154. 17 1 A 17 1 ABO Ao AO Ao LDS AO Ao Ao DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 CSH External Decode CSn External Decode CSn CSX M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLKO BS Connected to lO Vpp BS AS AS Connected to lO Vpp RD WR RDig Connectedto pn wry R W R W RW Connectedto IO Vpp IO Vop RD RDO RD RD Gonnecied to sizt OE OE IO Vop WEO WEO WE Weoj Connected to SIZO EB WE IO Vpp WE1 WE1 BHE WE1 UDS DS EBO UWE WAIT aL WAIT WAIT WAIT RDY DTACK DSACK1 N A DTACK RESET RESET RESET RESET RESET RESET RESET OUT RESET Note 1 AO for these busses is not used internally by the S1D13A04 and should be connected S1D13A04 X37A A 001 06 Page 32 4 6 LCD Interface Pin Mapping Table 4 9 LCD Interface Pin Mapping Epson Research and Development Vancouver Design Center acacia Color Passive Panel Color TFT Panel Passive Panel Pin Name Single Direct single Format 1 Format 2 athans HR TFT 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit FPFRAME FPFRAME SPS FPLINE FPLINE LP FPSHIFT FPSHIFT DCLK DRDY MOD FPSHIFT2 MOD DRDY GPO FPDATO DO Do B5 __ Do G3 Do Re R2 R3 R5 R5 FPDAT1 D1 1 R5 D1 R38 D1 G5 3 R1 R2 R4 R4 FPDAT2 D2 2 G4 D2 B2 D2 B4 3 RO R1 R3 R3 F
155. 29 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the NEC VR4102 VR4111 Microprocessors Document Number X37A G 007 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the NEC VR4102 VR4111 Microprocessors X37A G 007 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction lt e area AR A de ee ad ae ae sie aad 7 2 Interfacing to the NEC VR4102 VR4111 saaana 8 2 1 The NEC VR41XX System Bus 2 8 2b ONCRVICW coi dl ks a eo a gare a dn wa 8 2 1 2 LCD Memory Access Cycles o o 9 3 S1D13A04 Host Bus Interface lt lt es 10 3 1 Host Bus Interface Pin Mapping
156. 3 SH 4 MCLK provides the internal clock required to access the embedded SRAM The S1D13A04 is designed with efficient power saving control for clocks clocks are turned off when not used reducing the frequency of MCLK does not necessarily save more power Furthermore reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and so reduces screen update performance For a balance of power saving and performance the MCLK should be configured to have a high enough frequency setting to provide sufficient screen refresh as well as acceptable CPU cycle latency Note The maximum frequency of MCLK is 50MHz 30MHz if running CORE Vpp at 2 0V 10 As MCLK is derived from BCLK when BCLK is greater than 50MHz MCLK must be divided using REG 04h bits 5 4 The Memory Controller Power Save Status bit REG 14h bit 6 must return a 1 before disabling the MCLK source The source clock options for MCLK may be selected as in the following table Table 7 2 MCLK Clock Selection Source Clock Options MCLK Selection BCLK REG 04h bits 5 4 00 BCLK 2 REG 04h bits 5 4 01 BCLK 3 REG 04h bits 5 4 10 BCLK 4 REG 04h bits 5 4 11 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 85 Vancouver Design Center 7 1 3 PCLK Hardware Functional Specification Issue Date 2003 05 01 PCLK is the internal clock used to contr
157. 3 05 Epson Research and Development Vancouver Design Center Example 5 Program the PIP window registers for a 320x240 panel at 4 bpp with the PIP window positioned at 80 60 with a width of 160 and a height of 120 Determine the value for the PIP Window X Positions and PIP Window Y Positions registers Let the top left corner of the PIP window be x1 y1 and let the bottom right corner be x2 y2 where x2 x1 width 1 and y2 y1 height 1 The PIP Window X Positions register sets the horizontal coordinates of the PIP window s top left and bottom right corners The PIP Window Y Positions register sets the vertical coordinates of the PIP window s top left and bottom right corners The required values are calculated as follows X Start Position x1 32 bpp 80 32 4 10 0Ah Y Start Position yl 60 3Ch X End Position x2 32 bpp 80 160 1 32 4 29 875 1Dh truncated fractional part Y End Position y2 60 120 1 179 B3h Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 47 Vancouver Design Center 2 Program the PIP Window X Positions register with the X Start Position in bits 9 0 and the X End Position in bits 25 16 REG 58h is set to 001 DOO0Ah Program the PIP Window Y Positions register with the Y Start Position in bits 9 0 and the Y End Position in bits 25 16 REG 5Ch is set to 00B3003Ch
158. 37A A 001 xx fora complete description of the FPFRAME pulse settings Specifies the delay in lines from the start of the vertical non display period to the leading edge of the FPFRAME pulse Specifies the pulse width in lines of the vertical sync signal FPFRAME 13A04CFG uses a file panels def which contains predefined settings for a number of LCD panels If the file panels def is present in the same directory as 13A 04cfg exe the predefined panels are available in the drop down list If a panel is selected from the list 13A04CFG preconfigures its settings to nominal panel values S1D13A04 X37A B 001 01 Page 18 Epson Research and Development Vancouver Design Center Panel Power Tab 51D13A04 Configuration Utility Power Panel Support Enable Power Up Time Dela GPIO Selection Power Down Time Dela S1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Page 19 Vancouver Design Center The S5U13A04B00C evaluation board is designed to use a GPIO signal to control the LCD bias power The following settings configure panel power support Power Panel Support Enable When this box is checked the LCD bias power to the panel is controlled by the selected GPIO pin When this box is unchecked the LCD bias power must be controlled by the CPU or some other means GPIO Selection This setting selects the GPIO pin used to control the LCD bias power The default is
159. 3A04 X37A G 011 01 Page 18 Epson Research and Development Vancouver Design Center 4 Test Software 1D13A04 X37A G 011 01 Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13A04 test utilities and display drivers are available from your sales support contact see Section 6 Sales amp Technical Support or at www erd epson com Connecting to the Sharp HR TFT Panels Issue Date 01 10 12 Epson Research and Development Page 19 Vancouver Design Center 5 References 5 1 Documents Sharp Electronics Corporation LQO39Q2DSO01 Specification Sharp Electronics Corporation LQ031B1DDxx Specification Epson Research and Development Inc S D13A04 Hardware Functional Specification Document Number X37A A 001 xx Epson Research and Development Inc 7D13A04 Programming Notes and Examples Document Number X37A G 003 xx Epson Research and Development Inc S5UI3A04B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X37A G 004 xx 5 2 Document Sources e Sharp Electronics Corporation Website www sharpmeg com
160. 3A04 16bpp File Note Mode0 h should be created using the configuration utility 13A04CFG For more infor mation on 13A04CFG see the 13A04CFG Configuration Program User Manual docu ment number X37A B 001 xx available at www erd epson com 6 Build the WindML v2 0 library From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get src ugl and type the command make CPU PENTIUM ugl 7 Open the S1D13A04 workspace From the Tornado tool bar select File gt Open Workspace gt Existing gt Browse and select the file x 13A04 8bpp 13A03 wsp or x1113A04116bpp113A04 wsp 8 Add support for single line comments The WindML v2 0 display driver source code uses single line comment notation rather than the ANSI conventional comments To add support for single line comments follow these steps a Inthe Tornado Workspace Views window click on the Builds tab b Expand the 8bpp Builds or 16bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on default and select Properties A Properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that contains g mpent
161. 3A04 LCD USB Companion Chip S5U13A04B00C Rev 1 0 Evaluation Board User Manual Document Number X37A G 004 02 Copyright 2001 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Vancouver Design Center 10 11 12 Table of Contents Introduction 1 we 4 Features ia A Gr A RI A a Installation and Configuration 2 20 2 eee eee ee 3 1 Configuration DIP Switches 3 2 Configuration Jumpers CPU Interface gt lt 30 a ti eh ee A LS 4 1 CPU Interface Pin Mapping 4 2 CPU Bus Connector Pin Mapping LCD Interface Pin Mapping 2 222 eee eee Technical Descripti
162. 3A04CFG window Configure Multiple x Select files to configure Selected files Add gt Add All gt gt lt Remove lt lt Remove All C Show all files Show conf files only m iiit E l C 4s1d13a04 Close TF Preserve physical addresses The left pane lists files available for configuration the right pane lists files that have been selected for configuration Files can be selected by clicking the Add or Add All buttons double clicking any file in the left pane or by dragging the file s from Windows Explorer Selecting Show all files displays all files in the selected directory whereas selecting Show conf files only will display only files that can be configured using 13A04CFG i e exe s9 Checking Preserve Physical Addresses instructs 13A04CFG to use the register and display buffer address values the files were previously configured with Addresses specified in the General Tab are discarded This is useful when configuring several programs for various hardware platforms at the same time For example if configuring PCI MPC and IDP based programs at the same time for a new panel type the physical addresses for each are retained This feature is primarily intended for the test lab where multiple hardware configurations exist and are being tested 13A04CFG Configuration Program S1D13A04 Issue Date 01 10 19 X37A B 001 01 Page 26 Epson Research and Development Vancouver
163. 4 1 In Swivel View 270 program the start address desired byte address PIP height 1 x PIP Stride 4 S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 39 Vancouver Design Center Note Truncate all fractional values before writing to the address registers Note SwivelView 0 and 180 require the PIP width to be a multiple of 32 bits per pixel SwivelView 90 and 270 require the PIP height to be a multiple of 32 bits per pixel If this is not possible refer to Section 8 3 Limitations PIP Line Address Offset Register REG 54h Default 00000000h Read Write 22 21 20 19 18 17 16 PIP Line Address Offset bits 9 0 6 5 4 3 2 1 0 PIP Line Address Offset The PIP Line Address Offset register indicates the number of dwords per line in the PIP window image The image width must be a multiple of 32 bpp If the image width is not such a multiple a slightly larger width must be chosen see Section 8 3 Limitations PIP width and PIP height refer to the PIP dimensions as seen in Swivel View 0 landscape mode Stride is the number of bytes required for one line of the image the offset register represents the stride in DWORD steps PIP Stride image width x bpp 8 For SwivelView 0 and 180 PIP Width REG 58h bits 25 16 REG 58h bits 9 0 1 x 32 bpp PIP Height REG 5Ch bits 25 16 REG 5Ch bits 9
164. 4 Issue Date 01 10 12 X37A G 007 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the NEC VR4102 VR4111 Microprocessors X37A G 007 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13A04 LCD USB Companion Chip and the NEC VR4102 4111 micro processor The NEC VR4102 and VR4111 microprocessors are specifically designed to support an external LCD controller The designs described in this document are presented only as examples of how such inter faces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13A04 Issue Date 01 10 12 X37A G 007 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 VR4111 2 1 The NEC VR41XX System Bus 2 1 1 Overview S1D13A04 X37A G 007 01 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller
165. 4 These panels are e Sharp LQ031B1DDXX 160 x 160 HR TFT panel e Sharp LQ039Q2DS01 320 x 240 HR TFT panel The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Connecting to the Sharp HR TFT Panels 1D13A04 Issue Date 01 10 12 X37A G 011 01 Page 8 Epson Research and Development Vancouver Design Center 2 Connecting to the Sharp LQ039Q2DS01 HR TFT 2 1 External Power Supplies The S1D13A04 provides all necessary data and control signals to connect to the Sharp LQ039Q2DS01 320 x 240 HR TFT panel However it does not provide any of the voltages required for gray scaling gate driving or for the digital and analog supplies Therefore external supplies must be designed for any device utilizing the LQ039Q2DS01 2 1 1 Gray Scale Voltages for Gamma Correction The standard gray scale voltages can be generated using a precise resistor divider network that supplies two sets A and B of nine reference voltages to a National Semiconductor 9 Channel Buffer Amplifier LMC6009 The LMC6009 buffers these nine reference voltages and outputs them to the panel column drivers T
166. 4 480 X 480 e image seen by programmer image refreshed by S1D13A04 image in display buffer Figure 13 2 Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView 13 3 1 Register Programming Enable 180 Swivel View Mode Set Swivel View Mode Select bits REG 10h bits 17 16 to 10 Display Start Address The display refresh circuitry starts at pixel D therefore the Main Window Display Start Address register REG 40h must be programmed with the address of pixel D To calculate the value of the address of pixel D use the following formula assumes 8 bpp color depth REG 40h bits 16 0 image address offset x panel height 1 panel width x bpp 8 4 1 0 480 pixels x 319 pixels 480 pixels x 8 bpp 8 4 1 38399 95FFh Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Epson Research and Development Page 154 Vancouver Design Center Line Address Offset The Main Window Line Address Offset register REG 44h is based on the display width and programmed using the following formula REG 44h bits 9 0 display width in pixels 32 bpp 480 pixels 32 8 bpp 120 78h 13 4 270 SwivelView 270 SwivelView requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 2 1 25PCLK The following figure shows how the programmer s
167. 5 of the S1D13A04 23 Connected to RESET of the S1D13A04 24 Ground 25 Ground 26 Ground 27 12 volt supply 28 12 volt supply 29 Connected to WEO of the S1D13A04 30 Connected to WAIT of the S1D13A04 31 Connected to CS of the S1D13A04 32 Connected to MR of the S1D13A04 33 Connected to WE1 of the S1D13A04 34 Connected to 3 3V S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Page 15 S1D13A04 X37A G 004 02 Page 16 1D13A04 X37A G 004 02 Table 4 3 CPU Bus Connector H4 Pinout Epson Research and Development Vancouver Design Center Connector Comments Pin No 1 Connected to ABO of the S1D13A04 2 Connected to AB1 of the S1D13A04 3 Connected to AB2 of the S1D13A04 4 Connected to AB3 of the S1D13A04 5 Connected to AB4 of the S1D13A04 6 Connected to AB5 of the S1D13A04 7 Connected to AB6 of the S1D13A04 8 Connected to AB7 of the S1D13A04 9 Ground 10 Ground 11 Connected to AB8 of the S1D13A04 12 Connected to AB9 of the S1D13A04 13 Connected to AB10 of the S1D13A04 14 Connected to AB11 of the S1D13A04 15 Connected to AB12 of the S1D13A04 16 Connected to AB13 of the S1D13A04 17 Ground 18 Ground 19 Connected to AB14 of the S1D13A04 20 Connected to AB15 of the S1D13A04 21 Connected to AB16 of the S1D13A04 22 Connected to AB17 of the S1D13A04 23 Not connected 24 Not connected 25 Groun
168. 5307 ColdFire Microprocessor Issue Date 01 10 12 S1D13A04 X37A G 010 01 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SID13A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for this implementation of a S1D13A04 to Motorola MFC5307 microprocessor Table 4 1 Summary of Power On Reset Options S1D13A04 Power On Reset State Configuration Input 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 CNF3 Reserved Must be set to 1 CNF5 WAIT is active low CNF6 CLKI to BCLK divide ratio 2 1 EA configuration for Motorola MFC5307 microprocessor S1D13A04 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X37A G 010 01 Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 4 3 Register Memory Mapping The S1D13A04 uses two 256K byte blocks which are selected using A18 from the MCF5307 A18 is connected to the S1D13A04 M R pin The internal registers occupy the first 256K bytes block and the 160K byte display buffer occupies the second 256K byte block These two blocks of memory are aliased over the entire 2M byte space Note If aliasing is not desirable the up
169. 5U13A04B00C evaluation board is connected to S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 22 Epson Research and Development Vancouver Design Center 7 Clock Synthesizer and Clock Options For maximum flexibility the S5U13A04B00C implements a Cypress ICD2061A Clock Synthesizer MCLKOUT from the clock synthesizer is connected to CLKI2 of the S1D13A04 and VCLKOUT from the clock synthesizer is connected to CLKI of the S1D13A04 A 14 31818MHz crystal Y1 is connected to XTALIN and XTALOUT of the clock synthesizer and provides the reference clock to the clock synthesizer ICD2061A Synthesizer reference 14 31818 MHz gt gt XTALIN MCLKOUT gt CLKI2 VCLKOUT gt CLKI Figure 7 1 Symbolic Clock Synthesizer Connections At power on CLKI2 MCLKOUT is configured to be 40MHz and CLKI VCLKOUT is configured at 25 175MHz Note If a Sharp HR TFT panel is selected the clock synthesizer cannot be programmed and external oscillators must provide the clock signals to CLKI and CLKI2 Jumpers JP1 and JP2 allow selection of external oscillators U7 and U8 as the clock source for both CLKI and CLKI2 For further information see Table 3 2 Jumper Summary on page 11 7 1 Clock Programming 1D13A04 X37A G 004 02 The S1D13A04 utilities automatically program the clock generator If manual programming of the clock generator is required re
170. 6 7 6 5 4 3 2 1 0 1 6 4 3 22 21 20 19 18 17 16 Scratch Pad A bits 15 0 15 1 0 8 T 6 5 4 3 2 il 0 1 6 4 3 22 21 20 19 18 17 16 8 6 5 4 3 2 1 0 1 4 3 22 21 20 19 18 17 16 7 6 5 4 3 2 1 0 Page 4 Epson Research and Development Vancouver Design Center USB REGISTERS Control Register REG 4000h Default 00h Read Write USBClk Software USB Endpoint 4 Endpoint 3 Enable EOT Enable Stall Stall 7 6 5 4 3 2 1 0 USB Setup Reserved Reserved Interrupt Enable Register 0 REG 4002h Default 00h Read Write Suspend Request Interrupt Enable T 6 4 3 2 1 SOF Endpoint4 Endpoint3 Endpoint2 Endpoint 1 Interrupt Reserved Interrupt Interrupt Interrupt Interrupt Enable Enable Enable Enable Enable Interrupt Status Register 0 REG 4004h Default 00h Read Write Suspend Upper Req est SOF Endpoint4 Endpoint3 Endpoint2 Endpoint 1 Interrupt g Interrupt Reserved Interrupt Interrupt Interrupt Interrupt TUP Interrupt Active Status Status Status Status Status Status read only 7 6 4 3 2 1 0 Interrupt Enable Register 1 REG 4006h Default 00h Read Write Transmit FIFO Almost Empty Interrupt Enable 1 0 Receive FIFO Almost Full Interrupt Enable Interrupt Status Register 1 REG 4008h Default 00h Read Write Transmit FIFO Almost Empty Status 1 0 Receive FIFO Almost Full Status Endpoint 1 Index Registe REG 4010h Default 0
171. 6 4 Display Interface on page 56 Horizontal Display Period Register REG 24h Default 00000000h Read Write 19 18 Honora Display Period bits 6 0 4 3 2 1 bits 6 0 Horizontal Display Period Bits 6 0 These bits specify the LCD panel Horizontal Display period in 8 pixel resolution The Horizontal Display period should be less than the Horizontal Total to allow for a sufficient Horizontal Non Display period REG 24h bits 6 0 Horizontal Display Period in number of pixels 8 1 Note For passive panels HDP must be a minimum of 32 pixels and must be increased by mul tiples of 16 For TFT panels HDP must be a minimum of 8 pixels and must be increased by multi ples of 8 Note See Section 6 4 Display Interface on page 56 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 101 Vancouver Design Center Horizontal Display Period Start Position Register REG 28h Default 00000000h Read Write bits 9 0 Horizontal Display Period Start Position Bits 9 0 These bits specify a value used in the calculation of the Horizontal Display Period Start Position in 1 pixel resolution for TFT and direct HR TFT panels For passive LCD panels these bits must be set to 00h which will result in HDPS 22 HDPS REG 28h bits 9 0 22 For TFT panels HDPS is calculated using the following formula HDPS REG 28h bits 9 0 5
172. A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 80 Epson Research and Development Vancouver Design Center 6 4 11 320x240 Sharp Direct HR TFT Panel Timing e g LQ039Q2DS01 FPFRAME SPS t1 FPLINE A a z LP FPLINE LP FPSHIFT ENS EIA CLK t5 t6 GO FPDAT 17 0 for foziosxX X X XD320 t7 t8 t9 t10 GPIO3 SPL Ji GPIO1 CLS t12 P GPIOO PS t13 gt GPIO2 REV Figure 6 32 320x240 Sharp Direct HR TFT Panel Horizontal Timing S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 81 Vancouver Design Center Table 6 29 320x240 Sharp Direct HR TFT Panel Horizontal Timing Symbol Parameter Min Typ Max Units tl FPLINE start position 14 Ts note 1 t2 Horizontal total period 400 440 Ts t3 FPLINE width 1 Ts t4 FPSHIFT period 1 Ts t5 Data setup to FPSHIFT rising edge 0 5 Ts t6 Data hold from FPSHIFT rising edge 0 5 Ts t7 Horizontal display start position 60 Ts t8 Horizontal display period 320 Ts t9 FPLINE rising edge to GPIO3 rising edge 59 Ts t10 GPIO3 pulse width 1 Ts t11 GPIO1 GPIOO pulse width 353 Ts t12 GPIO1 rising edge GPIOO falling edge to FPLINE rise edge 5 Ts t13 GPIO2 toggle edge to FPLINE rise ed
173. AO O M 7 Hono ee oie Gone sivada aves rescind Er S SOA al lor 2 ve xo me ae ae 2 bates ee 0 rivassa elvas 57 yat me EN Eros 3 EN ps Ts aves a en ry E ae e K loulvaas i T T T T I Epson Research and Development Vancouver Design Center 1D13A04 X37A G 004 02 Figure 10 4 SIDI3A04B00C Schematics 4 of 6 S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Vancouver Design Center Epson Research and Development Page 30 a a a a a mor g TOE TEES E o lt gt a pal sewonwouroca sa aaa a i s ods ovoaroveinss sino s ony ales E daa E KLS s masaa s aur s U 1 olsNoou gt AQUI s sanua S 2380 s fasai E 10380 s lt 4 lo elav sS nzo gt nzzo F rezo nzzo mo I so T zo i 10 i neste note n note nzo nazo rezo azo oro 680 869 180 1 R A R n senior Ls usas Ls EEE g re Niki st ne ns ne PI mo S WOHd3 LOneInbyuos y9dd z ea soalrrioda rezo u 1 so L e Sh 10130 l aso 37 00n oma E SUN 2 ase oon vivo E rod ain vom Some 2 F 5 5 5 5555555555552 0525555555555555585 eed eeu ASS 2058 AN b ieu amp amp zvviosoroosaa 251001 osu n si lostlaag st loza lt a fuasau i mag Livin 80 sum aM anos sa 0 nosna T a a i i Figu
174. ATUS 0 FF Clear any pending USB interrupts REG 4010 EP1 INDEX 00 Set EP1 index to zero REG 4018 EP2 INDEX 00 Set EP2 index to zero ext REG 00 VENDOR ID MSB 2 Provide appropriate vendor ID ext REG 01 VENDOR ID LSB 2 ext REG 02 PRODUCT ID MSB 2 Provide appropriate product ID ext Reg 03 PRODUCT ID LSB 2 ext REG OC FIFO CONTROL 01 Enable EP4 FIFO valid transfer mode REG 4002 INT ENABLE 0 OA Enable interrupts for EP1 and EP3 REG 4004 INT STATUS 0 OA Make sure any pending interrupts are cleared INTERRUPT CONTROL REG 4046 ENABLE 0 02 e INTERRUPT CONTROL Enable RESET and endpoints notifications REG 4048 ENABLE 1 01 INTERRUPT CONTROL REC STATUS CLEAR 0 a INTERRUPT CONTROL Clear ALL interrupt status ad STATUS CLEAR 1 ae REG 4000 CONTROL A4 Enable the USB port for use S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 97 Vancouver Design Center The USB controller is ready for operation with the following configuration Endpoint 1 mailbox receive is configured for bulk OUT and Endpoint 2 mailbox transmit is configured for interrupt IN The functionality of these endpoints cannot be altered Endpoint 3 FIFO receive is configured for bulk in and Endpoint 4 FIFO transmit is configured for bulk out Endpoints 3 and 4 may also be configured for isochronous oper ation When the S1D13A04 is connected to a host controller the host will issue a
175. Ah Y Start Position panel height y2 1 240 60 120 1 1 60 3Ch X End Position panel width x1 1 32 bpp 320 80 1 32 4 29 875 1Dh truncated fractional part Y End Position panel height yl 1 240 60 1 179 B3h Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 53 Vancouver Design Center Program the PIP Window X Positions register with the X Start Position in bits 9 0 and the X End Position in bits 25 16 REG 58h is set to 001 DOOOAh Program the PIP Window Y Positions register with the Y Start Position in bits 9 0 and the Y End Position in bits 25 16 REG 5Ch is set to 00B3003Ch Due to truncation the dimensions of the PIP window may have changed Recalculate the PIP window width and height below PIP Width REG 58h bits 25 16 REG 58h bits 9 0 1 x 32 bpp 1Dh OAh 1 x 32 4 160 pixels PIP Height REG 5Ch bits 25 16 REG 5Ch bits 9 0 1 B3h 3Ch 1 120 lines 2 Determine the PIP display start address The main window image must take up 320 x 240 pixels x bpp 8 9600h bytes If the main window starts at address Oh then the PIP window can start at 9600h PIP Stride image width x bpp 8 160x4 8 80 50h PIP display start address desired byte address PIP Stride x PIP height 1 PIP width x bpp 8 4 PIP width x bpp 8 amp 03h 4
176. BitBLT Background Color This register specifies either e the BitBLT background color for Color Expansion or e the key color for Transparent BitBLT For 8 bpp BitBLTs bits 7 0 are used to specify the key color and for 16 bpp BitBLTs bits 15 0 are used BitBLT Foreground Color Register REG 8024h Default 00000000h Read Write n a 3i 30 29 28 27 26 25 24 23 22 21 20 19 18 lz 16 BitBLT Foreground Color bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BitBLT Foreground Color This register specifies the foreground color for Color Expansion or Solid Fill BitBLTs For 8 bpp BitBLTs bits 7 0 are used to specify the color and for 16 bpp BitBLTs bits 15 0 are used 2D Accelerator BitBLT Data Memory Mapped Region Register AB16 ABO 10000h 1FFFEh even addresses Read Write BitBLT Data bits 31 16 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 14 13 12 11 10 9 8 de 6 5 4 3 2 1 0 BitBLT Data bits 15 0 1 BitBLT Data bits This register is used by the local CPU to send data to the BitBLT engine for Write and Color Expansion BitBLTs and is used to read data from the BitBLT engine for Read BitBLTs The register should be treated as any other register it is however loosely decoded from 10000h to 1 FFFEh Note The BitBLT data registers are 32 bits wide but are accessed on WORD boundaries using 16 bit accesses Byte access to the BitBLT data registers is not allowed Note Accesses to this register other than for purposes
177. Bits 20 0 A 21 bit register that specifies the source start address for the BitBLT operation If data is sourced from the CPU then bit 0 is used for byte alignment within a 16 bit word and the other address bits are ignored In pattern fill operation the BitBLT Source Start Address is defined by the following equation Value programmed to the Source Start Address Register Pattern Base Address Pattern Line Offset Pixel Offset The following table shows how Source Start Address Register is defined for 8 and 16 bpp color depths Table 8 21 BitBLT Source Start Address Selection Color Format Pattern Base Address 20 0 Pattern Line Offset 2 0 Pixel Offset 3 0 8 bpp BitBLT Source Start Address 20 6 a a sare P 16 bpp BitBLT Source Start Address 20 7 a pias ra de a Note For further information on the BitBLT Source Start Address register see the D13A04 Programming Notes and Examples document number X37A G 003 xx BitBLT Destination Start Address Register REG 801 0h Default 00000000h Read Write BitBLT Destination Start Address bits 20 16 25 24 23 22 21 20 19 18 17 16 BitBLT Destination Start Address bits 15 0 8 7 6 5 4 3 2 1 0 bits 20 0 BitBLT Destination Start Address Bits 20 0 A 21 bit register that specifies the destination start address for the BitBLT operation Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 140 Epson Research
178. C vss AB5 NC AB10 AB14 CNF1 CNF4 CLKI2 VSS NC A NC COREVDD AB4 AB7 AB11 AB15 CNFO NC PWMOUT IOVDD NC 1 2 3 4 5 6 7 8 9 10 11 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Page 21 64 63 pin 2605 a 9 2 o1 lso lso es e7 se e5 e4 ss ag lso Izo zs 77 z zs z a zef zo eo lee e7 lee 6s COREVDD COREVDD NC NC FPFRAME FPLINE FPSHIFT FPDATO FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 NC VSS IOVDD NC FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT16 FPDAT17 NC NC NC VSS NC S1D13A04 COREVDD 4 2 Pinout Diagram TQFP15 128 Epson Research and Development Vancouver Design Center VSS NC NC DB9 DB10 DB11 DB12 DB13 DB14 DB15 WAIT NC IOVDD CLKI VSS NC RESET RD WR WE1 WEO RD BS M R CS NC ABO AB1 AB2 AB3 NC NC COREVDD 1D13A04 X37A A 001 06 Figure 4 2 Pinout Diagram TOFPIS 128 pin Revision 6 0 f E E P E E E ls o hoji hz 1014 151617 18 10 202122 20 20 25 28 a7 28 2030132 Hardware Functional Specification Issue Date 2003 05 01 Page 22 Epson Research and Development Vancouver Design Center 4 3 Pin Descriptions Key LB2A LB3P LO3 LB3M T1 Hi Z CUS Input Output Bi Directional Input Output Power pin CMOS input LVTTL input LVTTL IO buffer 6mA 6mMA 3 3V Low n
179. CD 00 CD FC CD CD FF 3D 00 DE 00 7D DE FF 00 BD DE 00 DE FD DE DE FF 3E 00 EF 00 7E EF FF 00 BE EF 00 EF FE EF EF FF 3F 00 FF 00 7F FF FF 00 BF FF 00 FF FF FF FF FF 16 bpp color The Look Up Table is bypassed at this color depth therefore programming the LUT is not required Programming Notes and Examples Issue Date 2002 08 21 1D13A04 X37A G 003 05 Page 26 Epson Research and Development Vancouver Design Center 6 Power Save Mode 6 1 Overview 1D13A04 X37A G 003 05 The S1D13A04 is designed for very low power applications During normal operation the internal clocks are dynamically disabled when not required The S1D13A04 design also includes a Power Save Mode to further save power When Power Save Mode is initiated LCD power sequencing is required to ensure the LCD bias power supply is disabled properly For further information on LCD power sequencing see Section 6 3 LCD Power Sequencing on page 28 For Power Save Mode AC Timing see the S D13A04 Hardware Functional Specification document number X37A A 001 xx The S1D13A04 includes a software initiated Power Save Mode Enabling disabling Power Save Mode is controlled using the Power Save Mode Enable bit REG 14h bit 4 While Power Save Mode is enabled the following conditions apply e Registers are accessible USB registers are not accessible e Memory writes are possible e Memory reads are not possible e LCD display is inactive e LCD interface out
180. CEPC_OHCI ohci dll FLATRELEASEDIR Nohci dll NK SH ENDIF usbd dll_ FLATRELEASEDIR usbd dll NK SH usbhid dll _FLATRELEASEDIR usbhid dll NK SH ENDIF IF USB_S1D13A04 Insert this line 13a04usb dll _FLATRELEASEDIR 13a04usb dll NK SH Insert this line ENDIF Insert this line ENDIF 1D13A04 X37A E 007 01 Page 6 Epson Research and Development Vancouver Design Center 10 From the Platform window click the Parameter View Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the WINCE300 tree and click the Hardware Specific Files then double click the PLATFORM REG Insert the following section in the file platform reg to in clude the settings for 13A04USB driver HKEY_LOCAL_MACHINE Drivers BuiltIn 13 AOXUSB DIL 13A04USB dll Prefix COM Tsp Unimodem dll DeviceArrayIndex dword 1 Order dword 2 DeviceType dword 0 FriendlyName S1D13A04 USB DevConfig hex 10 00 00 00 05 00 00 00 10 01 00 00 00 4B 00 00 00 00 08 00 00 00 00 00 00 PhysicalAddress dword 0x08000000 for non cepc environment only IRQ dword 05 for non cepc environment only 11 From the Build menu select Rebuild Platform to generate a Windows CE image file nk bin in the project directory x myproject myplatform reldir x86_release nk bin S1D13A04 Windows CE 3 x USB Driver X37A E 007 01 Issue Date 01 10 19 Epson Research and Development
181. Center Endpoint 3 Receive FIFO Status Register REG 4024h Default 01h Read Write 15 13 Receive FIFO Receive FIFO Receive FIFO Receive FIFO Fun Receive FIFO Flush Overflow Underflow read only Empty read only 4 3 2 1 0 bit 4 Receive FIFO Flush Writing to this bit causes the receive FIFO to be flushed Reading this bit always returns a 0 bit 3 Receive FIFO Overflow If set this bit indicates that an attempt was made by the USB host to write to the receive FIFO when the receive FIFO was full Writing a 1 clears this bit bit 2 Receive FIFO Underflow If set this bit indicates that an attempt was made to read the receive FIFO when the receive FIFO was empty Writing a 1 clears this bit bit 1 Receive FIFO Full If set this bit indicates that the receive FIFO is full bit 0 Receive FIFO Empty If set this bit indicates that the receive FIFO is empty Endpoint 3 Maximum Packet Size Register REG 4026h Default 08h Read Write n a Endpoint 3 Max Packet Size bits 7 0 bits 7 0 Endpoint 3 Max Packet Size Bits 7 0 This register specifies the maximum packet size for endpoint 3 in units of 8 bytes default 64 bytes It can be read by the host through the endpoint 3 descriptor Endpoint 4 Transmit FIFO Data Register REG 4028h Default 00h Write Only Tans FIFO Data bits 7 0 bits 7 0 Transmit FIFO Data Bits 7 0 This register is used by the local CPU to write data to the transmit FIFO The FIFO data is read by
182. Center JP2 selects the source for the CLKI2 input pin Position 1 2 sets the CLKI2 source to MCLKOUT from the Cypress clock synthesizer default setting Position 2 3 sets the CLKI2 source to the external oscillator at U8 E amp Co OS Ross MCLKOUT from External clock synthesizer oscillator U8 Figure 3 3 Configuration Jumper JP2 Location JP3 LCD Panel Voltage JP3 selects the voltage level to the LCD panel Position 1 2 sets the voltage level to 5 0V default setting Position 2 3 sets the voltage level to 3 3V Note When configured for Sharp HR TFT or Epson D TFD panels JP3 and JP5 must be set to position 2 3 J Co OS JP3 gt fl ji 5 LCDVCC 3 3 LCDVCC S1D13A04 X37A G 004 02 Figure 3 4 Configuration Jumper JP3 Location S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Epson Research and Development Page 13 Vancouver Design Center JP4 GPIOO Polarity on H1 JP4 selects the polarity of the GPIOO signal available on the LCD Connector H1 Position 1 2 sends the GPIOO signal directly to H1 default setting Position 2 3 inverts the GPIOO signal before sending it to H1 When no jumper is installed GPIOO is not sent to H1 mm Cx ea Normal Inverted GPIOO not Active High Active Low sent to H1 Figure 3 5 Configurati
183. Ch bits 1 0 and GPIOO is configured as an output writing a 1 to this bit drives GPIOO high and writing a 0 to this bit drives GPIOO low When the Direct HR TFT LCD interface is not selected REG OCHh bits 1 0 and GPIOO is configured as an input a read from this bit returns the status of GPIOO When the Direct HR TFT LCD interface is enabled REG OCh bits 1 0 10 GPIOO outputs the PS signal automatically and writing to this bit has no effect Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 114 Epson Research and Development Vancouver Design Center PWM Clock Configuration Register REG 70h Default 00000000h Read Write 17 16 PWM Clock Divide Select PWMCLK Source o bits 3 0 Select bits 1 0 Enable 0 PWM Clock Enable PWM Clock a PWM Duty Cycle PWMCLK gt Divider gt Modulation E to PWMOUT Clock Source 2 Duty n 256 frequency Clock Source 2 X 256 n PWM Clock Duty Cycle PWM Clock Force High m PWM Clock Divide Select value Figure 8 2 PWM Clock Block Diagram Note For further information on PWMCLK see Section 7 1 4 PWMCLK on page 86 bits 7 4 PWM Clock Divide Select Bits 3 0 The value of these bits represents the power of 2 by which the selected PWM clock source is divided Table 8 15 PWM Cloc
184. Date 2002 08 21 X37A G 003 05 Page 34 Epson Research and Development Vancouver Design Center Example 3 In SwivelView 180 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp 1 Determine the main window display start address The main window is typically placed at the start of display memory which is at display address 0 Main Window Stride image width x bpp 8 320x4 8 160 AOh main window display start address register desired byte address Main Window Stride x panel height 1 panel width x bpp 8 4 panel width x bpp 8 amp 03h 4 1 0 160 x 240 1 320 x 4 8 4 320 x 4 8 amp 03h 4 1 9599 257Fh Program the Main Window Display Start Address register REG 40h is set to 0000257Fh 2 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset register REG 44h is set to 00000028h S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 35 Vancouver Design Center Example 4 In SwivelView 270 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp 1 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 Mai
185. Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 64 6 4 4 Single Color 4 Bit Panel Timing Epson Research and Development Vancouver Design Center VDP VNDP FPFRAME FPLINE fl l ll fl LJ I I fl DRDY MOD y A X FPDAT 7 4 X Invalid LINE1 X LINE2 X LINES X LINE4 XLINE239XLINE240 Invalid LINE1 X LINE2 X FPLINE l a DRDY MOD X HDP HNDP lt 4 gt 5Ts 51s 5Ts 51s 5Ts 5Ts 5Ts 5Ts 5Ts 5Ts 5Ts FPSHIFT AN AAA O O AAA PA II 5Ts 5Ts 51s 5Ts 5Ts 2 5Ts STs 5Ts EPDAT7 maid ARANA XX y Yes Invalid X FPDATe ea E A X Y AE valia gt EPDATS waid ABN XiRayta4y XXX AY Ke2 Invalid XX FPDAT4 Invalid R2X 1 G3X 1 B4X XX yX YY Xi B320X Invalid X Notes FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks Ts Pixel clock iod PCLK 3 Diagram drawn with 2 APLINE vertical blank period Example timing for a 320x240 panel Figure 6 19 Single Color 4 Bit Panel Timing REG 20h bits 6 0 1 x 8Ts REG 24h bits 6 0 1 x 8Ts VDP Vertical Display Period REG 34h bits 9 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 30h bits 9 0 REG 34h bits 9 0 Lines HDP Horizontal Display Period REG 24h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP S1D13A04 X37A A 001 06 Revision 6 0
186. Design Center 3 2 Host Bus Interface Signal Descriptions The S1D13A04 Generic 2 Host Bus Interface requires the following signals S1D13A04 X37A G 013 01 CLKI is a clock input which is required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example it is driven by one of the SA 1110 signals SDCLK1 or SDCLK2 The example implementation in this document uses SDCLK2 For further information see Section 4 3 StrongARM SA 1110 Register Configuration on page 15 The address inputs AB 17 0 and the data bus DB 15 0 connect directly to the SA 1110 address bus A 17 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address line A18 allowing system address A18 to select between memory or register accesses Chip Select CS must be driven low by nCSx where x is the SA 1110 chip select used whenever the S1D13A04 is accessed by the SA 1110 WElH connects to nCAS1 the high byte enable signal from the SA 1110 which in conjunction with address bit O allows byte steering of read and write operations WEO connects to nWE the write enable signal from the SA 1110 and must be driven low when the SA 1110 is writing d
187. Design Center Export After determining the desired configuration Export permits the user to save the register information as a variety of ASCII text file formats The following is a list and description of the currently supported output formats e aC header file for use in writing HAL library based applications e aC header file which lists each register and the value it should be set to e aC header file for use in developing Window CE display drivers e aC header file for use in developing display drivers for other operating systems such as Linux QNX and VxWorks WindML e a comma delimited text file containing an offset a value and a description for each S1D13A04 register e a html based reference guide to the S1D13A04 registers C Header File for 51013404 HAL Based Applications lappefa h C Header File Defining a Map of 51013404 Registers chip h C Header File for 51013404 WinCE Drivers mode h Close C Header File for 51013404 Generic Drivers s1d13a0x h Comma Delimited File Containing Current Configuration s1d13a0x csv 1D13404 Register Quick Reference s1d13a0x html After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Clicking the Preview button uses Notepad or the web browser to display a copy of the file to be saved When the C Header File for S1D13A04 WinCE Drivers option is selecte
188. Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Windows CE 3 x USB Driver S1D13A04 Issue Date 01 10 19 X37A E 007 01 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds Build for CEPC X86 on Windows CE Platform Builder 3 00 using the GUI Interface S1D13A04 X37A E 007 01 1 2 Install Microsoft Windows 2000 Professional or Windows 98 Install Platform Builder 3 00 Start Platform Builder by double clicking on the Microsoft Windows CE Platform Builder icon Create a new project a Select File New b In the dialog box select the Platforms tab c Inthe Platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform set the processor to Win32 WCE x86 d Click the OK button e Inthe WCE Platform Step 1 of 2 dialog box select CEPC f Click the Next button g Inthe WCE Platform Step 2 of 2 dialog box select Maximum OS Maxall h Click the Finish button i Inthe New Platform Information dialog box click the OK button Set the active configuration to Win32 WCE x86 Release a From the Build menu select Set Active Configuration b Select MYPLATFORM Win32 WCE x86 Release c Click the OK button A
189. E PFBGA TQFP15 RESET ae Pin Name Type Pin Ping Cell State Description Input data from the system data bus e For Generic 1 these pins are connected to D 15 0 e For Generic 2 these pins are connected to D 15 0 L5 K5 J5 e For SH 3 SH 4 these pins are connected to D 15 0 L4 K4 J4 e For MC68K 1 these pins are connected to D 15 0 DB 15 0 jo 193 L3 K3 23 29 LB2A Hi Z For MC68K 2 these pins are connected to D 31 16 for J2 H3 H2 35 43 a 32 bit device e g MC68030 or D 15 0 for a 16 bit H1 H4 G3 device e g MC68340 G2 e For REDCAP2 these pins are connected to D 15 0 e For DragonBall these pins are connected to D 15 0 See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary This input pin has multiple functions e For Generic 1 this pin inputs the write enable signal for the lower data byte WEO e For Generic 2 this pin inputs the write enable signal WE e For SH 3 SH 4 this pin inputs the write enable signal for data byte 0 WEO WEO E5 13 LI e For MC68K 1 this pin must be tied to IO Vpp e For MC68K 2 this pin inputs the bus size bit O SIZO e For REDCAP2 this pin inputs the byte enable signal for the D 7 0 data byte EB1 For DragonBall this pin inputs the byte enable signal for the D 7 0 data byte LWE See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary This input pin has multiple functions e For G
190. EMs to do multiple designs with a common code base This document is updated as appropriate Please check the Epson Research and Devel opment website at www erd epson com for the latest revision of this document and source before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 12 Epson Research and Development Vancouver Design Center 2 Identifying the 1D13A04 The S1D13A04 can be identified by reading the value contained in the Product Information Register REG 00h To identify the S1D13A04 follow the steps below 1 Read REG OOh 2 The production version of the S1D13A04 returns a value of 2Cxx282Ch where xx depends on the configuration of the CNF 6 0 pins This value can be broken down into the following 1 The product code for the S1D13A04 is OBh 001011 binary and can be found in bits 7 2 and also in bits 31 26 2 The revision code is Oh 00 binary and can be found in bits 1 0 and again in bits 25 24 3 The display buffer size is 28h 00101000 binary and is contained in bits 15 8 Note The display buffer size is the distinguishing value between the S1D13A03 and the S1D13A04 as they share the same product code and revision code For the correct dis play buffer size for the S1D13A03 see the D 3A03 Hardware Functional Specifica tion
191. EPSON S1D13A04 LCD USB Companion Chip S1D13A04 TECHNICAL MANUAL Document Number X37A Q 001 01 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 TECHNICAL MANUAL X37A Q 001 01 Issue Date 01 10 02 Epson Research and Development Page 3 Vancouver Design Center COMPREHENSIVE SUPPORT TOOLS EPSON provides the designer and manufacturer a complete set of resources and tools for the development of LCD Graphics Systems Documentation Technical manuals Evaluation Demonstration board manual Evaluation Demonstration Board e Assembled and fully tested Graphics Evaluation Demonstration board e Schematic of Evaluation Demonstration board e Parts List e Installation Guide e CPU Independent Software Utilities e Evalua
192. FO will result in a STALL acknowl edge by the S1D13A04 No data will be returned to the USB host bit 3 Endpoint 3 Stall If this bit is set host bulk writes to the receive FIFO will result in a STALL acknowledge by the S1D13A04 Receive data will be discarded bit 2 USB Setup This bit is used by software to select between GPIO and USB functions for multifunction GPIO pins GPIO 7 4 This bit should be set at the same time as the USBClk Enable bit When this bit 1 the USB function is selected When this bit 0 the GPIO function is selected Note The USB Registers must not be accessed when this bit is 0 bit 1 Reserved This bit must be set to 0 bit 0 Reserved This bit must be set to 0 Interrupt Enable Register 0 REG 4002h Default 00h Read Write n a 5 14 13 12 1 10 9 8 Suspend Request SOF Interrupt reserved Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 ma Interrupt Enable Enable Interrupt Enable Interrupt Enable Interrupt Enable Interrupt Enable bit 7 Suspend Request Interrupt Enable When set this bit enables an interrupt to occur when the USB host is requesting the S1D13A04 USB device to enter suspend mode bit 6 SOF Interrupt Enable When set this bit enables an interrupt to occur when a start of frame packet is received by the S1D13A04 bit 5 Reserved This bit must be set to 0 bit 4 Endpoint 4 Interrupt Enable When set this bit enables an interrupt to occur when a USB Endpoint 4 Data Packet has bee
193. Generic 2 Interface Timing 38 Hitachi SH 3 Interface Timing 2 2 ee 40 Hitachi SH 4 Interface Timing 2 2 e 42 Motorola MC68K 1 Interface Timing 00200000004 44 Motorola MC68K 2 Interface Timing 000000000007 46 Motorola Redcap2 Interface Timing 2 02 00 00004 48 Motorola Dragonball Interface Timing with DTACK 50 Motorola Dragonball Interface Timing w o DTACK 52 Passive TFT Power On Sequence Timing 2 002 e 54 Passive TFT Power Off Sequence Timing 2 0008 55 Panel Timing Parameters rms ora a wee de Re ae ee eae 56 Generic STN Panel Timing 58 Single Monochrome 4 Bit Panel Timing 60 Single Monochrome 4 Bit Panel A C Timing 00 0 4 61 Single Monochrome 8 Bit Panel Timing o e 62 Single Monochrome 8 Bit Panel A C TiMiNd8 o 63 Single Color 4 Bit Panel TiMing e 64 Single Color 4 Bit Panel A C Timing e e 65 Single Color 8 Bit Panel Timing Format l o o 66 Single Color 8 Bit Panel A C Timing Format o o 67 Single Color 8 Bit Panel Timing Format2 o o 68 Single Color 8 Bit Panel A C Timing Format2 o oo 69 Single Color 16 Bit Panel Timing e e 70 Single Col
194. HR TFT Panels document number X37A G 011 xx Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 29 Vancouver Design Center 6 4 Enabling Power Save Mode Power Save Mode must be enabled using the following steps 1 Turn off the LCD bias power Note The S5U13A04B00C uses GPIOO to control the LCD bias power supplies Your system design may vary 2 Wait for the LCD bias power supply to discharge The discharge time is based on the discharge rate of the power supply 3 Enable Power Save Mode set REG 14h bit 4 to 1 The S1D13A04 is now in Power Save Mode To further increase power savings PCLK and MCLK can be switched off see steps 4 and 5 4 At this time the LCD pixel clock source may be disabled 5 After the Memory Controller Power Save Status bit REG 14h bit 6 returns a 1 the Memory Clock source may be shut down 6 5 Disabling Power Save Mode Bring the S1D13A04 out of Power Save Mode using the following steps 1 Ifthe Memory Clock source is shut down it must be started 2 If the pixel clock is disabled it must be started 3 Disable Power Save Mode set REG 14h bit 4 to 0 4 Wait for the LCD bias power supply to charge The charge is based on the time re quired for the LCD power supply to reach operating voltage 5 Enable the LCD bias power Note The S5U13A04B00C uses GPIOO to control the LCD bias power supplies Your system design may vary Program
195. Host Bus Interface and should be tied high connected to IO Vpp The following diagram shows a typical implementation of the SA 1110 to S1D13A04 interface SA 1110 S1D13A04 nWE gt WEO nCAS1 gt WE1 nOE gt RD nCS4 gt CSH Pull up To RDY WAIT A18 gt M R System RESET gt RESET A 17 0 gt AB 17 0 D 15 0 4 gt DB 15 0 SDCLK2 gt CLKI lOVpp BS L RD WR Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of SA 1110 to SIDI3A04 Interface Interfacing to the Intel StrongARM SA 1110 Microprocessor Issue Date 01 10 12 1D13A04 X37A G 013 01 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SID13A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for this implementation of a S1D13A04 to SA 1110 interface Table 4 1 Summary of Power On Reset Options 1D13A04 Configuration Input Power On Reset State 1 con
196. IT signal Fixed low latency CPU access times Registers are memory mapped M R input selects between memory and register address space The complete 160k byte display buffer is directly and contiguously available through the 18 bit address bus 2 3 Display Support Single panel single drive passive displays e 4 8 bit monochrome LCD interface e 4 8 16 bit color LCD interface Active Matrix TFT interface e 9 12 18 bit interface Direct support for 18 bit Sharp HR TFT LCD or compatible interface 2 4 Display Modes e 1 2 4 8 16 bit per pixel bpp color depths e Up to 64 gray shades on monochrome passive LCD panels e Up to 64K colors on passive panels e Up to 64K colors on active matrix LCD panels e Example resolutions 320x240 at a color depth of 16 bpp 320x320 at a color depth of 8 bpp 160x160 at a color depth of 16 bpp 2 pages 160x240 at a color depth of 16 bpp 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 13 Vancouver Design Center 2 5 Display Features SwivelView 90 180 270 counter clockwise hardware rotation of display image Virtual display support displays images larger than the panel size through the use of panning and scrolling Picture in Picture Plus PIP displays a variable size window overlaid over back ground image Pixel Doubling independent control of both horizontal an
197. K 3 10 MCLK BCLK 4 12 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 012 01 Page 14 5 Software 1D13A04 X37A G 012 01 Epson Research and Development Vancouver Design Center Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The 1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Support or at www erd epson com Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MC68VZ328 DragonBall VZ Integrated Processor User s Manual Motorola Publication no MC683VZ28UM available on the Internet at http www mot com SPS WIRELESS products MC68VZ328 html Epson Research and Development Inc 1D 13404 Hardware Functional Specification Document Number X37A A 001 xx Epson Research and Development Inc S5U13A04B00C Rev 1 0 Evaluation Board User Manual Document
198. LEFT BLANK S1D13A04 13A04PLAY Diagnostic Utility X37A B 002 01 Issue Date 01 10 05 Epson Research and Development Page 3 Vancouver Design Center 13A04PLAY 13A04PLAY is a diagnostic utility which allows a user to read write all the registers and display buffer of the S1D13A04 Commands are received from the standard input device and messages are sent to the standard output device On Intel platforms the console provides standard input output For most embedded systems the serial device provides these functions Commands can be entered interactively by a user or be executed from a script file Scripting is a powerful feature which allows command sequences to be used repeatedly without re entry 1D13A04 Supported Evaluation Platforms 13A04PLAY is available as an executable for PCs running Windows 9x ME NT 2000 and as C source code which can be modified and recompiled to allow 13A04PLAY to run on other platforms 13A04PLAY Diagnostic Utility S1D13A04 Issue Date 01 10 05 X37A B 002 01 Page 4 Installation Usage 1D13A04 X37A B 002 01 Epson Research and Development Vancouver Design Center PC platform Copy the file 13A04play exe to a directory in the path e g PATH C S1D13A04 Embedded platform Download the program 13A04play to the system PC platform At the prompt type 13A04play Where displays copyright and program version information Embedded platform Execute 13A04play and at the prompt
199. NICAL MANUAL X37A Q 001 01 Issue Date 01 10 02 EPSON GRAPHICS 1D13A04 LCD USB Companion Chip September 2001 The S1D13A04 is an LCD USB solution designed for seamless connection to a wide variety of micro processors The S1D13A04 integrates a USB slave controller and an LCD graphics controller with an embedded 160K byte SRAM display buffer The LCD controller based on the popular S1D13706 supports all standard panel types including the Sharp HR TFT family of products In addition to the S1D13706 feature set the S1D13A04 includes a Hardware Acceleration Engine to greatly improve screen drawing functions The USB controller provides revision 1 1 compliance for applications requiring a USB client This high level of integration provides a low cost low power single chip solution to meet the demands of embedded markets requiring USB client support such as Mobile Communica tions devices and Palm size PCs The S1D13A04 utilizes a guaranteed low latency CPU architecture that provides support for micropro cessors without READY WAIT handshaking signals The 32 bit internal data path write buffer and the Hardware Acceleration Engine provide high performance bandwidth into display memory allowing for fast display updates Direct support for the Sharp HR TFT removes the requirement of an external Timing Control IC Additionally products requiring a rotated display can take advantage of the SwivelView feature which provide
200. Note S Source D Destination P Pattern NOT Logical AND Logical OR Logical XOR Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 1D13A04 X37A A 001 06 Page 138 Epson Research and Development Vancouver Design Center bits 3 0 BitBLT Operation Bits 3 0 Specifies the 2D Operation to be carried out based on the following table Table 8 20 BitBLT Operation Selection BitBLT Operation Bits 3 0 BitBLT Operation 0000 Write BitBLT with ROP 0001 Read BitBLT 0010 Move BitBLT in positive direction with ROP 0011 Move BitBLT in negative direction with ROP 0100 Transparent Write BitBLT 0101 Transparent Move BitBLT in positive direction 0110 Pattern Fill with ROP 0111 Pattern Fill with transparency 1000 Color Expansion 1001 Color Expansion with transparency 1010 Move BitBLT with Color Expansion 1011 Move BitBLT with Color Expansion and transparency 1100 Solid Fill Other combinations Reserved S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 139 Vancouver Design Center BitBLT Source Start Address Register REG 800Ch Default 00000000h Read Write BitBLT Source Start Address bits 20 16 20 19 18 17 16 BitBLT Source Start Address bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits 20 0 BitBLT Source Start Address
201. Note This register must be programmed such that the following formula is valid HDPS HDP lt HT FPLINE Register REG 2Ch Default 00000000h Read Write PRONE FPLINE Pulse Width bits 6 0 Polarity 23 22 21 20 19 18 FPLINE Pulse Start Position bits 9 0 7 6 5 4 3 2 bit 23 FPLINE Pulse Polarity This bit selects the polarity of the horizontal sync signal For passive panels this bit must be set to 1 For TFT panels this bit is set according to the horizontal sync signal of the panel typically FPLINE or LP When this bit 0 the horizontal sync signal is active low When this bit 1 the horizontal sync signal is active high bits 22 16 FPLINE Pulse Width Bits 6 0 These bits specify the width of the panel horizontal sync signal in 1 pixel resolution The horizontal sync signal is typically FPLINE or LP depending on the panel type REG 2Ch bits 22 16 FPLINE Pulse Width in number of pixels 1 Note For passive panels these bits must be programmed such that the following formula is valid HPW HPS lt HT Note See Section 6 4 Display Interface on page 56 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 102 Epson Research and Development Vancouver Design Center bits 9 0 FPLINE Pulse Start Position Bits 9 0 These bits specify the start position of the horizontal sync signal in 1 pixel resolution FPLINE Pulse Start Position in pixels REG 2Ch bi
202. On receipt of the interrupt the local CPU examines the masked interrupt status registers REG 404Eh and REG 4050h to determine the source of the interrupt If the interrupt came from bit O of the Negative Interrupt Masked Status register REG 4050h the next step is to examine REG 4004 to determine the exact cause of the interrupt Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 98 Epson Research and Development Vancouver Design Center Endpoint 1 Mailbox Receive If the cause of the interrupt is determined to be EndPoint 1 REG 4004h bit 1 1 then the data is read from the EndPoint 1 data register REG 4012h The following figure shows the procedure for the CPU to read the mailbox register EP1 Receive Clear EP1 Index Register REG 4010h 00h Initialize local index Idx 0 Read byte from EP 1 Receive Mailbox Data pBuffer REG 4012h Increment the local index ldx Read another byte from the mailbox Idx lt 8 Clear EP1 interrupt status REG 4004h 20h Figure 10 1 Endpoint 1 Data Reception Note In this diagram reference is made to two pseudo variables Idx is an integer used as a loop counter pBuffer is a pointer to eight bytes of memory to store the EP1 data 1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 99 Vancouver Design Cente
203. P4 FIFO Valid bit while NAKing IN token Bit 5 of REG 402Ch indicates to the S1D13A04 controller when data in the endpoint 4 FIFO is ready to be transferred to the host computer Changing the state of this bit at certain times may generate an error When the S1D13A04 USB controller receives an endpoint 4 IN request and endpoint 4 is not ready to transmit data REG 402Ch bit 5 0 the response is a NAK packet If endpoint 4 is toggled to a ready to transmit state just before a NAK response packet is sent the controller may erroneously send a zero length packet instead When this happens the data toggle state will be incorrectly set for the next endpoint 4 data transmit The following timing diagram shows the error occurring in section 3 7 Y Host to Device IN EP4 Token PKT IN EP4 Token PKT IN EP4 Token PKT Device to Host NAK RPLY_ DATA PKT RPLY ZERO Length PKT CPU Write to EP4_VALID 1 o 1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 111 Vancouver Design Center This unexpected occurrence of a zero length packet may cause file system handling errors for some operating systems Work Around There are two software solutions for this occurrence Disable USB Receiver before setting the EP4 FIFO Valid bit The first solution involves disabling the USB receiver to avoid responding to an EP4 IN packet During the
204. PCI Bus Support The S1D13A04 does not have on chip PCI bus interface support The S1D13A04B00C uses the PCI Bridge FPGA to support the PCI bus 6 2 Direct Host Bus Interface Support The SSUI3A04BO00C is specifically designed to work using the PCI Bridge FPGA in a standard PCI bus environment However the S1D13A04 directly supports many other host bus interfaces Connectors H3 and H4 provide the necessary IO pins to interface to these host buses For further information on the host bus interfaces supported see CPU Interface on page 14 Note The PCI Bridge FPGA must be disabled using SW1 8 in order for direct host bus inter face to operate properly 6 3 S1D13A04 Embedded Memory The S1D13A04 has 160K bytes of embedded SRAM The 160K byte display buffer address space is directly and contiguously available through the 18 bit address bus 6 4 Adjustable LCD Panel Negative Power Supply Most monochrome passive LCD panels require a negative power supply to provide between 14V and 24V 1 45mA Such a power supply VLCD has been provided on the SSU13A04BO00C board VLCD can be adjusted using potentiometer R39 to provide an output voltage from 14V to 24V and is enabled disabled using the S1D13A04 general purpose signal GPIOO active high Note When manually adjusting the voltage set the potentiometer according to the panel s specific power requirements before connecting the panel S5U13A04B00C Rev 1 0 Evaluation Board
205. PDAT12 25 D12 R3 GO G2 G2 FPDAT13 27 D13 G2 G1 G1 FPDAT14 29 D14 B1 GO GO FPDAT15 31 D15 R1 BO B2 B2 FPDAT16 4 B1 B1 FPDAT17 6 BO BO FPSHIFT 33 FPSHIFT CLK DRDY 35 amp 38 MOD FPSHIFT2 MOD DRDY GPO FPLINE 37 FPLINE LP FPFRAME 39 FPFRAME SPS GND 2 s 20 GND PWMOUT 28 PWMOUT VLCD 30 Adjustable 24V to 14V negative LCD bias VCC 32 LCDVCC 3 3V or 5V 12V 34 12V VDDH 36 Adjustable 23V to 40V positive LCD bias DISPLAY 40 GPIOO for controlling on board LCD bias power supply on off PS Note These pin mappings use signal names commonly used for each panel type however signal names may differ between panel manufacturers The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT For further FPDATxx to LCD interface mapping see S1D13A04 Hardware Functional Specification document number X37A A 001 xx 2 DISPLAY can be disconnected from GPIOO using JP5 2 3 position and inverted on H1 setting JP4 to 2 3 can be 3 When the Direct HR TFT interface is selected DRDY becomes a general purpose output GPO controllable using the Direct HR TFT LCD Interface GPO Control bit REG 14h bit 0 This GPO can be used to control the HR TFT MOD signal if required For further information see the S1D13A04 Hardware Functional Specification document number X37A A 001 xx S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28
206. PDAT3 D3 3 B3 S D3 G2 5 D3 R4 3 G2 G3 G5 G5 FPDAT4 DO D4 DO R2 D4 R3 D4 R2 5 D8 B5 3 G1 G2 G4 G4 FPDAT5 D1 D5 D1 B1 D5 G2 8 D5 B1 D9 R5 Go G1 G3 G3 FPDAT6 D2 D6 D2 G1y Bn D6 G1 D10 G4 3 B2 B3 B5 B5 FPDAT7 D3 D7 D3 R1 gt D7 R1 D7 R1 gt D171 B35 Bi B2 B4 B4 FPDAT8 D4 G3 3 BO B1 B3 B3 FPDAT9 D5 B2 RO R2 R2 FPDAT10 D6 R2 Ri Ri FPDAT11 D7 G1 RO RO FPDAT12 D12 R3 GO G2 G2 FPDAT13 D13 G2 G1 G1 FPDAT14 D14 B1 GO GO FPDAT15 D15 R1 BO B2 B2 FPDAT16 B1 B1 FPDAT17 BO BO GPIOO GPIOO PS GPIO1 GPIO1 CLS GPIO2 GPIO2 REV GPIO3 GPIO3 SPL Note GPIO pins default to inputs at reset and require special configuration using REG 64h when the Direct HR TFT interface is desired 2 When the Direct HR TFT interface is selected REG OCh bits 1 0 10 DRDY becomes a general purpose output GPO controllable using the Direct HR TFT LCD Interface GPO Control bit REG 14h bit 0 This GPO can be used to control the HR TFT MOD signal if required For further information see the bit description for REG 14h bit 0 3 These pin mappings use signal names commonly used for each panel type however signal names may differ between panel manufacturers The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT For further FPDATxx to LCD interface mapping see Section 6 4 Display Interface on page 56
207. PIP Line Address Offset bits 9 0 6 5 4 3 2 1 0 bits 9 0 PIP Window Line Address Offset Bits 9 0 These bits are the LCD display s 10 bit address offset from the starting double word of line n to the starting double word of line n 1 for the PIP window Note that this is a 32 bit address increment Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 10h bit 19 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 106 Epson Research and Development Vancouver Design Center PIP X Positions Register REG 58h Default 00000000h Read Write PIP X End Position bits 9 0 21 Note The effect of REG 58h through REG SCh takes place only after REG 5Ch is written and at the next vertical non display period bits 25 16 PIP Window X End Position Bits 9 0 These bits determine the X end position of the PIP window in relation to the origin of the panel Due to the S1D13A04 SwivelView feature the X end position may not be a horizontal position value only true in 0 and 180 Swivel View For further information on defining the value of the X End Position register see Section 14 Picture in Picture Plus PIP on page 156 The register is also incremented differently based on the Swivel View orientation For 0 and 180 SwivelView the X end position is incremented by x pixels where x is relative to the current color depth Tab
208. PU independent allowing use of the driver for several Windows CE Platform Builder supported platforms The file s1dflat cpp will require editing for the correct values of PhysicalPortAddr Physical VmemA ddr etc The sample code defaults to a 320x240 8 bit color passive LCD panel in Swivel View 0 mode landscape with a color depth of 8 bpp To support other settings use 13A04CFG EXE to generate a proper MODEO H file For further information refer to the 13A04CFG Configuration Program User Manual document number X37A B 001 XX By default the 13A04CFG program assumes PCI addressing for the SSU13A04B00C evaluation board This means that the display driver will automatically locate the S1D13A04 by scanning the PCI bus currently only supported for the CEPC platform If you select the address option Other and fill in your own custom addresses for the registers and video memory then the display driver will not scan the PCI bus and will use the specific addresses you have chosen If you are running the display driver on hardware other than the S5U13A04B00C evalu ation board you must ensure that your hardware provides the correct clock frequencies for CLKI and CLKI2 13A04CFG defaults to SOMHz for both CLKI and CLKI2 On the evaluation board the display driver will correctly program the clock chip to support the CLKI and CLKI2 frequencies On customer hardware you must ensure that the clocks you provide to all clock inputs match the se
209. Page 11 Vancouver Design Center 1 Introduction 1 1 Scope This is the Hardware Functional Specification for the S1D13A04 LCD USB Companion Chip Included in this document are timing diagrams AC and DC characteristics register descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers This document is updated as appropriate Please check for the latest revision of this document before beginning any development The latest revision can be downloaded at www erd epson com We appreciate your comments on our documentation Please contact us via email at documentation erd epson com 1 2 Overview Description The S1D13A04 is an LCD USB solution designed for seamless connection to a wide variety of microprocessors The S1D13A04 integrates a USB slave controller and an LCD graphics controller with an embedded 160K byte SRAM display buffer The LCD controller based on the popular S1D13706 supports all standard panel types including the Sharp HR TFT family of products In addition to the S1D13706 feature set the S1D13A04 includes a Hardware Acceleration Engine to greatly improve screen drawing functions The USB controller provides revision 1 1 compliance for applications requiring a USB client This high level of integration provides a low cost low power single chip solution to meet the demands of embedded markets requiring USB client support such as Mobile Co
210. Polarity FPLINE Polarity FPFRAME Polarity Panel Dimensions 13A04CFG Configuration Program Issue Date 01 10 19 Page 15 Selects the panel data width Panel data width is the number of bits of data transferred to the LCD panel on each clock cycle and shouldn t be confused with color depth which determines the number of displayed colors When a passive panel type is selected the available options are 4 8 and 16 bit When an active panel type TFT HR TFT is selected the available options are 9 12 and 18 bit Selects between a monochrome or color panel Allows selection of the polarity for the FPLINE and FPRAME pulses Note Selecting the wrong pulse polarity may damage the panel Selects the polarity of the FPLINE pulse Refer to the panel specification for the correct polarity of the FPLINE pulse Selects the polarity of the FPFRAME pulse Refer to the panel specification for the correct polarity of the FPFRAME pulse These fields specify the panel width and height A number of common widths and height are available in the selection boxes If the width height of your panel is not listed enter the actual panel dimensions into the edit field For passive panels manually entered pixel widths must be a minimum of 32 pixels and can be increased by multiples of 16 For TFT panels manually entered pixel widths must be a minimum of 8 pixels and can be increased by multiples of 8 If a value is entered that d
211. Power 32 VSHD Digital power supply Supplies on page 14 33 DGND Vss Digital ground Ground pin of S1D13A04 34 PS GPIOO Power save signal 35 LP FPLINE Data latch signal of source driver 36 DCLK FPSHIFT Data sampling clock signal 37 LBR Selection for horizontal scanning direction Connect to VSHD left right scanning 38 SPR Sampling start signal for right left scanning Right to left scanning not supported See Section 3 1 External Power 39 VSHA Analog power supply Supplies on page 14 40 VO Standard gray scale voltage black 36 Sea on 3 1 External Rower Supplies on page 14 41 vi gt Standard gray scale voltage ace ore Ones Skea ener Supplies on page 14 42 V2 Standard gray scale voltage ore oo ony tices elmer One Supplies on page 14 43 V3 Standard gray scale voltage ore occ Ona i Forna ERWEE Supplies on page 14 44 V4 Standard gray scale voltage ace Sedi ono eee One Supplies on page 14 45 V5 gt Standard gray scale voltage oe eee MS Supplies on page 14 46 V6 Standard gray scale voltage i cal Met ON Supplies on page 14 47 V7 Standard gray scale voltage See Seel Ones onal One Supplies on page 14 48 V8 gt Standard gray scale voltage a PaA a A evel Supplies on page 14 49 v9 Standard gray scale voltage white e meel ne e E rer one Supplies on page 14 50 AGND Vss Analog ground Ground pin of S1D13A04 Connecting to the Sharp HR TFT Panels Issue Date 01 10 12 1D1
212. R or SPACE moves to the next memory location if data is specified the previous memory location is updated if no data is specified no change is made moves to the previous memory location Q or exits MODIFY mode c6 99 X 8116132 index data Reads writes data to the register at index If no data is specified the register is read and the contents are displayed Where 8116132 The unit size 8 bit bytes 16 bit words 32 bit dwords If a unit size is not specified this command uses the unit size from the last X command performed If no previous X command has been issued the unit size defaults to 8 bit index Index into the registers hex data The value to be written to the register Numbers are assumed to be hexadecimal values unless otherwise specified with the correct suffix binary i octal 0 decimal t hexadecimal h For example 101i 101 binary XA Reads and displays the contents of all the S1D13A04 registers 2 Displays the help screen The help screen contains a summary of all available commands 1D13A04 13A04PLAY Diagnostic Utility X37A B 002 01 Issue Date 01 10 05 Epson Research and Development Page 11 Vancouver Design Center 13A04PLAY Example 1 Configure 13A04PLAY using the utility 13A04CFG For further information on 13A04CFG see the 13A04CFG User Manual document number X37A B 001 xx 2 Type 13A04PLAY to start the program 3 Type for help 4 Typei to i
213. RESET command to the S1D13A04 In response to the RESET the S1D13A04 clears all USB registers in the range REG 4000h to REG 403Ah The client software must respond to the reset and reprogram the USB registers A host controller may issue a RESET at any time during operation After the S1D13A04 receives the RESET and re initializes the registers the host controller starts the USB SETUP phase The SETUP sequence is handled entirely by the S1D13A04 USB controller After the setup is complete the S1D13A3 is ready to begin transferring data Note Prior to initializing the registers host controller accesses are responded to with NAKs After being configured host controller accesses will be handled in the normal way Note A Vendor ID can be obtained through the USB Implementers Forum at http www usb org 10 3 Data Transfers The S1D13A04 USB requires very little local CPU assistance during data transfers For the most part data transfers from the host involve reading a FIFO data register when notified of that the transfer is complete or writing a FIFO register and setting a ready bit to send data to the host The following sections expand on the data transfer mechanism 10 3 1 Receiving Data from the Host the OUT command Data transferred from the host to the S1D13A04 is directed to either EndPoint 1 the mailbox or EndPoint 3 the FIFO When the data packet has been successfully received the S1D13A04 generates an interrupt
214. S Ya hie 84 7 1 Clock Descriptions 2 2 ee 84 Wala BEER ES A A Ne a as de E 84 P22 MCEK a a RA eee AR Ano ele ata G 84 dd PEER srs es i ORS a A A A nh hoe 38 8 85 TALA PWMCEK 0 ir a a A eg es ene 86 HAS USBEEK 40d e tai PE Oa taa eek ad 86 dize Clock Selection s os 4 4 a a ns dace a Be ok ra ST 7 3 Clocks versus Functions e 8 3 REGISICRS ct A A e AD A e A 89 8 1 RegisterMapping 2 ee 89 8 2 Register Set emir sed ee e 8D 8 3 LCD Register Descriptions Offset 0h 91 8 3 1 Read Only Configuration Registers 2 2 20 0 2 0 2 0000004 91 8 3 2 Clock Configuration Registers 2 2 0 0 e e 0000004 92 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 5 Vancouver Design Center 8 3 3 Panel Configuration Registers 2 2 0 0 00 00000000 ee eee 93 8 3 4 Look Up Table Registers 0 0 0 00 0000000000 0004 98 8 3 5 Display Mode Registers a 100 8 3 6 Picture in Picture Plus PIP Registers o o 105 8 3 7 Miscellaneous Registers o a 110 8 4 USB Registers Offset 4000h e o fon nds LAF 8 5 2D Acceleration BitBLT Registers Offset 8000h 2 2 135 8 6 2D Accelerator BitBLT Data Register Descriptions 2 2 141 9 2D Accelerator BitBLT Engine
215. S ore A amp Goa A A Geet 7 2 Interfacing to the StrongARM SA 1110 BUS 2 eee ee ee es 8 2 1 The StrongARM SA 1110 System Bus 2 2 8 2 1 1 StrongARM SA 1110 Overview 0 0 000 0000 eee ee ee 8 2 1 2 Variable Latency IO Access Overview 2 2 2 2 a 8 2 1 3 Wariable Latency IO Access Cycles 2 2 0 0 0 002 eee ee eee 9 3 S1D13A04 Host Bus Interface 11 3 1 Host Bus Interface Pin Mapping e 11 3 2 Host Bus Interface Signal Descriptions 2 2 2 12 4 StrongARM SA 1110 to S1D13A04 Interface 13 4 1 Hardware Description 2 0 020 ee ee 13 4 2 S1D13A04 Hardware Configuration 2 2 2 14 4 3 StrongARM SA 1110 Register Configuration 15 4 4 Register Memory Mapping 16 S ftWare sore E a cae ee A et ee a e a ee 17 Referenc s ic ice ech a a a AA ee a 18 6 1 Documents s i a ee be Ah roth ge a SA ok Go eee nd ote eh ee Bee te ds ES 6 2 Document Sources 1 ee ee ee ee 18 7 Sales and Technical Support ee et 19 7 1 EPSON LCD USB Companion Chips SID13A04 2 2 2 2 19 7 2 Intel StrongARM SA 1110 Processor 2 2 2 19 Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 4 Epson Research and Development Vancouver
216. S1D13A04 X37A G 004 02 Page 18 Epson Research and Development Vancouver Design Center Table 5 2 Extended LCD Signal Connector H2 a onocnrome Color Passive Panel Color TFT Panel assive Panel Pin Connector i 3 Name Pin No Single m a 3 Others bias USB 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit GPIoo 1 GPIOO PS GPIOO GPIO1 3 GPIO1 CLS GPIO1 GPI02 5 GPIO2 REV GPIO2 GPIO3 7 GPIO3 SPL GPIO3 GPIO4 9 GPIO4 USBPUP GPIO5 11 GPIO5 BET GPIO6 13 GPIO6 USBDM GP107 15 GPIO7 USBDP 2 4 6 8 10 SND 12 14 16 GND Note 1 When Switch SW1 4 is open CNF3 0 at RESET GPIO 7 6 and GPIO 4 0 are set as outputs at O low state and GPIOS is set as an input at power on RESET for use when USB is selected If SW1 4 is closed then GPIO 7 0 are set as inputs upon power on RESET 2 If the Direct HR TFT interface is selected REG O0Ch bits 1 0 10 GPIO 3 0 are used for the Direct HR TFT interface GPIO 7 4 remain available for USB support or as GPIOs 3 If USB support is enabled REG 4000h bit 7 1 GPIO 7 4 are used by the USB interface GPIO 3 0 remain available for Direct HR TFT interface support or as GPIOs S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Page 19 Vancouver Design Center 6 Technical Description 6 1
217. S1D13A04 Hardware Functional Specification X37A A 001 06 Revision 6 0 Issue Date 2003 05 01 Epson Research and Development Vancouver Design Center Page 33 5 D C Characteristics Note When applying Supply Voltages to the S1D13A04 Core Vpp must be applied to the chip before or simultaneously with IO Vpp or damage to the chip may result Table 5 1 Absolute Maximum Ratings Symbol Parameter Rating Units Core Vpp Supply Voltage Vss 0 3 to 3 0 V IO Vpp Supply Voltage Vss 0 3 to 4 0 V Vin Input Voltage Vss 0 3 to lO Vpp 0 5 V Vout Output Voltage Vss 0 3 to IO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C TsoL Solder Temperature Time 260 for 10 sec max at lead C Table 5 2 Recommended Operating Conditions Symbol Parameter Condition Min Typ Max Units Vss 0V 1 8 note 1 2 0 note 1 2 2 note 1 V Core Vpp Supply Voltage Vss 0V 2 25 2 5 2 75 V IO Vop Supply Voltage Vss 0V 3 0 3 3 3 6 V VIN Input Voltage Vss 10 Yoo if Vss CORE Vpp Topr Operating Temperature 40 25 85 C 1 When Core Vpp is 2 0V 10 the MCLK must be less than or equal to 30MHz MCLK lt 30MHz Table 5 3 Electrical Characteristics for VDD 3 3V typical Symbol Parameter Condition Min Typ Max Units lobos Quiescent Current Quiescent Conditions 170 uA liz Input Leakage Current 1 1 uA loz Ou
218. SB driver is independent of the S1D13A04 Windows CE v3 x display driver but may be run together with S1D13A04 display driver For information on the S1D13A04 CE Display Driver see the Windows CE 3 x Display Driver document number X37A E 006 xx e At this time the driver has been tested on the x86 CPUs and has been run with Platform Builder v3 00 S1D13A04 Windows CE 3 x USB Driver X37A E 007 01 Issue Date 01 10 19 EPSON S1D13XXX 32 Bit Windows Device Driver Installation Guide Document No X00A E 003 04 Copyright 1999 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32 Bit Windows Device Driver Installation Guide X00A E 003 04 Issue Date 01 04 17 Epson Research and Development Page 3 Vancouver Design Center S1D13XXX 32 Bit Windows De
219. SBClk is enabled When this bit 0 the USBCIk is disabled Note The USB Registers must not be accessed when this bit is 0 bit 6 Software EOT This bit determines the response to an IN request to Endpoint 4 when the transmit FIFO is empty If this bit is asserted the S1D13A04 responds to an IN request to Endpoint 4 with an ACK and a zero length packet if the FIFO is empty If this bit is not asserted the S1D13A04 responds to an IN request from Endpoint 4 with an NAK if the FIFO is empty indicating that it expects to transmit more data This bit is automatically cleared when the S1D13A04 responds to the host with a zero length packet when the FIFO is empty bit 5 USB Enable Any device or configuration descriptor reads from the host will be acknowledged with a NAK until this bit is set This allows time for the local CPU to set up the interrupt polling register maximum packet size registers and other configuration registers e g Product ID and Vendor ID before the host reads the descriptors Note As the device and configuration descriptors cannot be read by the host until the USB Enable bit is set the device enumeration process will not complete and the device will not be recognized on the USB Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 118 Epson Research and Development Vancouver Design Center bit 4 Endpoint 4 Stall If this bit is set host bulk reads from the transmit FI
220. Save Mode Operating Voltage COREypp 2 0 10 or 2 5 10 volts e lOypp 3 0 10 volts Clock Source Three independent clock inputs including dedicated USB clock single clock possible if USB not required Flexible clock source selection and divides Package 121 pin PFBGA e 128 pin TQFP15 Integrated USB Features e USB Client Revision 1 1 Compliant Integrated LCD Controller Features 1 2 4 8 16 bit per pixel bpp support Up to 64 gray shades on monochrome passive panels Up to 64K colors on passive active matrix panels Single panel single drive passive displays 4 8 bit monochrome LCD interface e 4 8 16 bit color passive LCD interface 9 12 18 bit Active matrix TFT interface 18 bit Direct HR TFT interface SwivelView hardware rotation by 90 180 270 Picture in Picture Plus displays a variable size window overlaid over background image Pixel Doubling horizontal and vertical resolutions can be doubled without any additional memory Software video invert Typical resolutions supported 320x240 16 bpp 320x320 8 bpp 160x160 16 bpp 2 pages 160x240 16 bpp 2D BitBLT Engine Write BLT Transparent Write BLT Move BLT Transparent Move BLT Solid Fill BLT Read BLT Pattern Fill Color Expansion BLT Move BLT with Color Expansion CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS S1D13A04 Technical Manual e Palm OS Hardware Abstractio
221. Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 60 6 4 2 Single Monochrome 4 Bit Panel Timing Epson Research and Development Vancouver Design Center VDP VNDP dl FPFRAME FPLINE f fl fl ll l DRDY MOD Y sl Y FPDAT 7 4 Y Invalid LINE1 X LINE2 X LINES X LINE4 X XLINE239XLINE240X Invalid LINE X LINE2 Y FPLINE M o DRDY MOD ae HDP HNDP 4 4 gt FPSHIFT FPDAT7 Invalid X 11 X15 X A X X 1317X Invalid x FPDAT6 Invalid 12 Y 16 Y Ll X X IR Invalid FPDAT5 Invalid 13 17 X e X X 1319X Invalid Y FPDAT4 Invalid 14 X18 X A X 320 Invalid Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel VDP Vertical Display Period REG 34h bits 9 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 30h bits 9 0 REG 34h bits 9 0 Lines HDP Horizontal Display Period REG 24h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 20h bits 6 0 1 x 8Ts REG 24h bits 6 0 1 x 8Ts 1D13A04 X37A A 001 06 Revision 6 0 Figure 6 15 Single Monochrome 4 Bit Panel Timing Hardware Functional Specification Issue Date 2003 05 01
222. Sta wav ozay be Ga ano zar aw szav ne PRS 9 wea ey 8300 asa E gt gt 13501 neet rza 07 szav ano F POE zov szav gt ozv ot BN ono szav zy ez ee z oy sees rea EE onA aaauas38 prx es 4038 ano yr an ano Fx 9 mk mo ome TX ano susu E gt gt tase aanas aanuassy Hx Z INSYd aansasa Hx cansas3y ou Px MINSA canessas FX AUN ns PE ___ rani vont PE ast want E a ase no ooa oal au x ONO SL Fe xon nait Neh aau Hx 18104 mos rene gt lossa e K loelav gug I T Epson Research and Development Vancouver Design Center Figure 10 6 SIDI3A04B00C Schematics 6 of 6 1D13A04 X37A G 004 02 S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Page 32 11 Board Layout Epson Research and Development Vancouver Design Center z u4 seo X u5 ENERGY EPSON gt SAVING C24 C27 ce C44 R36 240 R37 u17 C37 c4 L HE PE EEN SEKO EPSON CORP S5U13A03 4 5B00C REV 1 0 2001 Figure 11 1 SsUI3A04B00C Board Layout 1D13A04 X37A G 004 02 S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Epson Research and Development Vancouver Design Center 12 Sales and Technical Support 12 1 Epson Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson
223. T2 falling edge t14 2 Ts t9 FPSHIFT2 FPSHIFT period 4 6 Ts t10 FPSHIFT2 FPSHIFT pulse width low 2 Ts t11 FPSHIFT2 FPSHIFT pulse width high 2 Ts t12 FPDAT 7 0 setup to FPSHIFT2 FPSHIFT falling edge 1 Ts t13 FPDAT 7 0 hold from FPSHIFT2 FPSHIFT falling edge 1 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 min t3min HPS t4min 4 Bmin HT 5 t4min HPW 6 t6amin HPS HDP HDPS if negative add t3min 7 t6Dmin HPS HDP HDPS 2 if negative add t3 pin 8 t4min HDPS HPS t4 min if negative add t3 pin Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 68 Epson Research and Development Vancouver Design Center 6 4 6 Single Color 8 Bit Panel Timing Format 2 le VDP ste VNDP A FPFRAME gt FPLINE __l l I ery call I I fl I DRDY MOD ke X FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 X XLINE239XLINE240 Invalid LINE1 X LINE2 X FPLINE ae DRDY MOD X HDP HNDP lt gt FP S HIFT 2Ts Ts 2Ts 2Ts Ts 2Ts 2Ts Ts 2Ts m Ts Ts Ts Ts Ts Ts Ts ___ Se a FPDAT7 nvalid RX 183 Y 1 66 Y Y X Y Xay maid YEY FPDAT6 maid a ar
224. TMPR3905 12 Specification Epson Research and Development Inc S D13A04 Hardware Functional Specification Document Number X37A A 001 xx e Epson Research and Development Inc S5UI3A04B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X37A G 004 xx e Epson Research and Development Inc S1IDI3A04 Programming Notes and Examples Document Number X37A G 003 xx 6 2 Document Sources e Toshiba America Electrical Components Website www toshiba com taec e Epson Research and Development Website www erd epson com 1D13A04 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X37A G 002 01 Issue Date 01 10 12 Epson Research and Development Page 17 Vancouver Design Center 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de 7 2 T
225. Threshold bits 5 0 n a Transmit FIFO Almost Empty Threshold bits 5 0 a 3 2 1 4 3 2 1 Contro Maximum Power Consumption 403Ah efault 01h Read Write REG 403Ah Index 09h Default FAh Read Write USB String Maximum Current bits 7 0 Enable 4 3 Reserved REG Default 00h Read Write REG 403Ah Default 00h Read Write EP2 Data EP1 Data Toggle Toggle 5 3 2 0 va 6 5 4 3 2 1 0 Default 00h Read Write Transmit FIFO Valid Mode 0 USBFC Input Control Register REG 4040h Default ODh Read Write USCMPEN Reserved Reserved ISO WAKEUP Reserved Reserved 6 5 4 3 2 1 0 Reserved REG 4042h Default 1Dh Read Only Reserved Reserved Reserved Reserved Reserved 2 Register Summary S1D13A04 Issue Date 01 10 02 X37A R 001 01 Page 6 Epson Research and Development Vancouver Design Center S1D13A04 Register Summary X37A R 001 01 Issue Date 01 10 02 Epson Research and Development Page 7 Vancouver Design Center 2D ACCELERATION BitBLT REGISTERS Color z Source Dest Linear 3 Format Select Linear Select Select 18 17 16 BitBLT Enable WO 0 Number of Free FIFO Entries 0 means full Number of Used FIFO Entries 26 25 20 19 18 17 FIFO Not FIFO Half FIFO Full ey Empty Full Status usy Status 6 5 4 0 BitBLT ROP Code bits 3 0 18 17 BitBLT Operation bits 3 0 2 1
226. USB String Enable When set this bit allows the default Vendor and Product ID String Descriptors to be returned to the host When this bit is cleared the string index values in the Device Descriptor are set to zero Maximum Power Consumption REG 403Ah Index 09h Default FAh Read Write Maximum Current bits 7 0 7 6 5 4 3 2 1 0 bits 7 0 Maximum Current Bits 7 0 The amount of current drawn by the peripheral from the USB port in increments of 2 mA The S1D13A04 reports this value to the host controller in the configuration descriptor The default and maximum value is 500 mA FAh 2 mA In order to comply with the USB specification the following formula must apply REG 403Ah index 09h lt FAh Packet Control REG 403Ah Index 0Ah Default 00h Read Write a Ga a li Ga anny ma 7 6 5 4 3 2 1 0 bit 7 EP4 Data Toggle Bit Contains the value of the Data Toggle bit to be sent in response to the next IN token to endpoint 4 from the USB host Note When a write is made to this bit the value cannot be read back before a minimum of 12 USBCLK bit 6 EP3 Data Toggle Bit Contains the value of the Data Toggle bit expected in the next DATA packet to endpoint 3 from the USB host Note When a write is made to this bit the value cannot be read back before a minimum of 12 USBCLK 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 129 Vancouv
227. Vancouver Design Center Page 7 Installation and Execution from CEPC Environment Once the nk bin file is built the CEPC environment can be started by booting either from a floppy step 1 or a hard drive step 2 configured with a Windows 9x operating system Both methods are described below 1 To start CEPC by booting from a floppy drive a b Create a bootable floppy disk Copy himem sys to the floppy disk and edit config sys on the floppy disk to con tain only the following line device a himem sys Edit autoexec bat on the floppy disk to contain the following line loadcepc B 38400 C 1 c nk bin Search for loadcepc exe in your Windows CE directories and copy the file to the bootable floppy disk Copy nk bin to c Boot the system from the bootable floppy disk 2 To start CEPC by booting from a hard drive d e Search for loadcepc exe in the Windows CE directories and copy the file to C Edit config sys on the hard drive to contain only the following line device c himem sys Edit autoexec bat on the hard drive to contain the following line loadcepc B 38400 C 1 c nk bin Copy nk bin to C Boot the system 3 Install Windows 2000 Professional on a host machine 4 Install ActiveSync 3 1 on the host machine 5 Install the included weeusbsh sys on the host machine by following the procedures below a Unzip the file wceusbsh zip to a directory on your hard drive b Find the fi
228. View Select Bit 1 Select Bit 0 Orientation 0 0 0 normal 0 1 90 1 0 180 1 1 270 1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 31 Vancouver Design Center Main Window Display Start Address Register REG 40h Default 00000000h Read Write bit 16 Main Window Display Start Address The Main Window Display Start Address register represents a DWORD address which points to the start of the main window image in the display buffer An address of 0 is the start of the display buffer For the following Swivel View mode descriptions the desired byte address is the starting display address for the main window image In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address panel height x bpp 8 4 panel height x bpp 8 amp 03h 4 1 In SwivelView 180 program the start address desired byte address Main Window Stride x panel height 1 panel width x bpp 8 4 panel width x bpp 8 amp 03h 4 1 In Swivel View 270 program the start address desired byte address panel width 1 x Main Window Stride 4 Note Truncate all fractional values before writing to the address registers Note SwivelView 0 and 180 require the panel width to be a multiple of 32 bits per pixel Swivel View 90 and 270 require the pan
229. WE deasserted to reasserted TeLko 7 D 15 0 valid to fourth CLKO rising edge where CSX 0 and UWE 4 TORG 0 or LWE 0 write cycle t8 D 15 0 hold from UWE LWE rising edge write cycle 2 ns t9 DTACK falling edge to D 15 0 valid read cycle Telko 4 ns t10 CSX rising edge to D 15 0 high impedance read cycle 6 ns t11 CSX rising edge to DTACK rising edge 9 ns t12 CLKO rising edge to DTACK high impedance 9 ns t13 Cycle Length 5 TeLKo 1 The MC68VZ328 has a maximum clock frequency of 33MHz The MC68EZ328 has a maximum clock frequency of 16MHz Hardware Functional Specification S1D13A04 X37A A 001 06 Page 52 Epson Research and Development Vancouver Design Center 6 2 9 Motorola Dragonball Interface Timing w o DTACK e g MC68EZ328 MC68VZ328 F CLKO CLKO t1 pa 5 A i6 1 HD EE t1 u gt id CSX x t1 ls t5 UWE LWE write A t1 _ e Be o OE read 12 i t5 D 15 0 write K valid i p t4 d t3 lt D 15 0 read valid Figure 6 10 Motorola Dragonball Interface Timing w o DTACK S1D13A04 X37A A 001 06 Revision 6 0 Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Vancouver Design Center Table 6 16 Motorola Dragonball Interface Timing w o DTACK Page 53 Symbol Parameter Min Max Unit foLko Bus clock fr
230. Windows 95 OSR2 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Windows will detect the card as a new PCI Device and launch the UPDATE DEVICE DRIVER wizard If The Driver is on Floppy Disk 3 4 5 6 Place the disk into drive A and click NEXT Windows will find the EPSON PCI Bridge Card Click FINISH to install the driver Windows will ask you to restart the system If The Driver is not on Floppy Disk 3 4 10 11 12 13 14 15 16 17 Click NEXT Windows will search the floppy drive and fail Windows will attempt to load the new hardware as a Standard VGA Card Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE Select NO for Windows to DETECT NEW HARDWARE Click NEXT Select OTHER DEVICES from HARDWARE TYPE and Click NEXT Click HAVE DISK Specify the location of the driver and click OK Click OK EPSON PCI Bridge Card will appear in the list Click NEXT Windows will install the driver Click FINISH Windows will ask you to restart the system Windows will re detect the card and ask you to restart the system S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards Install the evaluation board in
231. Y End Position see Section 8 2 Picture In Picture Plus Examples on page 45 The register also increments differently based on the SwivelView orientation For 0 and 180 SwivelView the Y End Position is incremented in 1 line increments For 90 and 270 SwivelView the Y End Position is incremented by Y pixels where Y is relative to the current color depth Table 8 3 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment Y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 16 bpp 2 S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 43 Vancouver Design Center In SwivelView 0 these bits set the vertical coordinates y of the PIP windows s bottom edge Increasing y moves the bottom edge downwards in 1 line steps The vertical coordi nates start at line 0 Program the PIP Window Y End Position so that PIP Window Y End Position y In Swivel View 90 these bits set the horizontal coordinates x of the PIP window s left edge Increasing x moves the left edge towards the right in steps of 32 bits per pixel see Table 8 3 The horizontal coordinates start at pixel 0 Program the PIP Window Y End Position so that PIP Window Y End Position panel height x 1 32 bits per pixel Note Truncate the fractional part of the above equation In SwivelView 180 these bits set the vertical coordinates y of the PIP window
232. a format is packed pixel Packed pixel data may be envisioned as a stream of pixels In this stream pixels are packed adjacent to each other If a pixel requires four bits then it is located in the four most signif icant bits of a byte The pixel to the immediate right on the display occupies the lower four bits of the same byte The next two pixels to the immediate right are located in the following byte etc 4 1 Display Buffer Location The S1D13A04 display buffer is 160K bytes of embedded SRAM The display buffer is memory mapped and is accessible directly by software The memory block location assigned to the S1D13A04 display buffer varies with each individual hardware platform For further information on the display buffer see the S D13A04 Hardware Functional Specification document number X37A A 001 xx For further information on the S1D13A04 Evaluation Board see the SSU 3A04B00C Evaluation Board Rev 1 0 User Manual document number X37A G 004 xx 4 2 Memory Organization for One Bit per pixel 2 Colors Gray Shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 1D13A04 X37A G 003 05 Figure 4 1 Pixel Storage for 1 Bpp in One Byte of Display Buffer At a color depth of 1 bpp each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out
233. ace on page 56 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 104 Epson Research and Development Vancouver Design Center bits 9 0 FPFRAME Pulse Start Position Bits 9 0 These bits specify the start position of the vertical sync signal in 1 line resolution For passive panels these bits must be set to 00h For TFT panels VDPS is calculated using the following formula VPS REG 3Ch bits 9 0 Note See Section 6 4 Display Interface on page 56 Main Window Display Start Address Register REG 40h Default 00000000h Read Write bit 16 bits 16 0 Main Window Display Start Address Bits 16 0 This register specifies the starting address in DWORDS for the LCD image in the display buffer for the main window Note that this is a double word 32 bit address An entry of 00000h into these registers represents the first double word of display memory an entry of 00001h represents the sec ond double word of the display memory and so on Calculate the Display Start Address as follows REG 40h bits 16 0 image address 4 valid only for SwivelView 0 Note For information on setting this register for other Swivel View orientations see Section 13 Swivel View on page 151 Main Window Line Address Offset Register REG 44h Default 00000000h Read Write bits 9 0 Main Window Line Address Offset Bits 9 0 This register specifies the offset in DWORDS
234. ace Timing e g MC68030 46 6 2 7 Motorola REDCAP2 Interface Timing o e 48 6 2 8 Motorola Dragonball Interface Timing with DTACK e g MC68EZ328 MC68VZ328 50 6 2 9 Motorola Dragonball Interface Timing w o DTACK e g MC68EZ328 MC68VZ328 52 6 3 LCD Power Sequencing oop dce c d c oe S dde c DA 6 3 1 Passive TFT Power On Sequence a 54 6 3 2 Passive TFT Power Off Sequence a 55 6 3 3 Direct HR TFT Interface Power On Off Sequence 0 55 6 4 Display Interface s u a an a g a a aaa a a e a a E a a 56 64 1 Generic STN Panel Timing cos ioeo iaai e a ee a d aa Y 58 6 4 2 Single Monochrome 4 Bit Panel Timing 60 6 4 3 Single Monochrome 8 Bit Panel Timing 62 6 4 4 Single Color 4 Bit Panel Timing _ a 64 6 4 5 Single Color 8 Bit Panel Timing Format 1 00 66 6 4 6 Single Color 8 Bit Panel Timing Format 2 68 6 4 7 Single Color 16 Bit Panel Timing o 0000 0 70 6 4 8 Generic TFT Panel Timing e 72 6 4 9 9 12 18 Bit TFT Panel Timing 00 0000 00 73 6 4 10 160x160 Sharp Direct HR TFT Panel Timing e g LQ031B1DDxx 76 6 4 11 320x240 Sharp Direct HR TFT Panel Timing e g LQ039Q2DS01 80 65 USB Timings aaraa a a a a O A er IO T UGIOCKS o UA EA A GAS AE A
235. address block Each chip select may also be individ ually programmed to control an 8 or 16 bit device Lastly each chip select can either generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally using the standard MC68000 DTACK signal Chip select groups A and B are used to control ROM SRAM and Flash memory devices and have a block size of 128K bytes to 16M bytes Chip select AO is active immediately after reset and is a global chip select so it is typically used to control a boot EPROM device AO ceases to decode globally once its chip select registers are programmed Groups C and D are special in that they can also control DRAM interfaces These last two groups have block size of 32K bytes to 4M bytes Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 10 12 Epson Research and Development Vancouver Design Center 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a Dragonball Host Bus Interface which directly supports the Motorola MC68VZ328 micro processor Page 9 The Dragonball Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13A04 configuration see Section 4 2 S1D13A04 Hardware Configuration on page 12 3 1 Host Bus Interface Pin Map
236. age This results in 64 gray shades 5 2 2 Color Modes 1D13A04 X37A G 003 05 In color display modes the number of LUT entries used is determined by the color depth For each color depth a table of sample LUT values is provided These LUT values are a standardized set of colors used by the Epson S1D13A04 utility programs Note These LUT values carry eight bits of significance The S1D13A04 LUT uses only the six MSB The 2 LSB are ignored 1 bpp color When the S1D13A04 is configured for 1 bpp color mode the first 2 entries in the LUT are used The remaining indices of the LUT are unused Table 5 6 Suggested LUT Values for I bpp Color Index Red Green Blue 00 00 00 00 01 FF FF FF 02 FF sk Indicates unused entries in the LUT 2 bpp color When the S1D13A04 is configured for 2 bpp color mode the first 4 entries in the LUT are used The remaining indices of the LUT are unused Table 5 7 Suggested LUT Values for 2 bpp Color Index Red Green Blue sk Indicates unused entries in the LUT Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 23 Vancouver Design Center 4 bpp color When the S1D13A04 is configured for 4 bpp color mode the first 16 entries in the LUT are used The remaining indices of the LUT are unused The following table shows LUT values that simulate those of a VGA operating in 16 color mode Table 5 8 S
237. age 9 and Figure 2 2 Panel Gate Driver DC Power Supplies on page 9 for details on generating Vss Vpp and Vcc 3 1 4 AC Gate Driver Power Supplies See Section 2 1 4 AC Gate Driver Power Supplies on page 10 and Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 for details on generating V gg and Vcom If the Sharp IR3E203 is used to generate the gray scale voltages the COM signal can be connected to the input of the F2C02E MOSFET instead of the buffered REV signal 3 2 HR TFT MOD Signal See Section 2 2 HR TFT MOD Signal on page 11 for details on controlling the MOD signal through software Connecting to the Sharp HR TFT Panels 1D13A04 Issue Date 01 10 12 X37A G 011 01 Page 16 3 3 S1D13A04 to LQ031B1DDxx Pin Mapping Epson Research and Development Vancouver Design Center Table 3 1 SIDI3A04 to LOO3IBIDDxx Pin Mapping LCD Pin LCD Pin S1D13A04 Description Remark No Name Pin Name P emarss 1 VDD Power supply of gate driver high level eA en Power 2 VCC Power supply of gate driver logic high es O il 3 MOD Control signal of gate driver econ 2 A MOD signal on page 15 4 MOD Control signal of gate driver area REMO sign on page 15 5 U L 5 Selection for vertical scanning direction Connect to VSHD top bottom scanning 6 SPS FPFRAME Start signal of gate driver 7 CLS GPIO1 Clock signal o
238. al CPU sets EP4 FIFO Valid in Endpoint 4 FIFO Status Register REG 402Ch the S1D13A04 will erroneously clear the EP4 valid bit if the S1ID13A04 is concurrently sending a NAK handshake in response to a previous IN token to EP4 Work Around The work around is in the EP4 Packet Transmitted interrupt routine It requires the interrupt routine to know whether the recently queued packet was a zero length packet or not so that must be stored as a bit when the packet was loaded into the FIFO On entry to the EP4 Packet Transmitted interrupt routine For a non zero length Packet Check the FIFO count If it is non zero this error occurred In that case set FIFO Valid again clear the interrupt status bit and exit the interrupt routine For a zero length Packet Check the Software EOT bit in Control Register REG 4000h If it is set the FIFO Valid write failed In that case set FIFO Valid again clear the interrupt status bit and exit the interrupt routine 10 4 3 EP3 Interrupt Status bit set by NAKs When receiving Bulk OUT packets from a Host PC the S1D13A04 Endpoint 3 Interrupt Status interrupt typically is used to notify the peripheral firmware that a packet has been received This bit also serves as the Receive FIFO Valid bit so additional packets addressed to Endpoint 3 are NAKed until this status bit is cleared Once cleared however it may become set by another packet which is NAKed by the 1D13A04 causin
239. al OE Interfacing to the Motorola MPC82x Microprocessor 1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 14 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals 1D13A04 X37A G 009 01 CLKI is a clock input which is required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example SYSCLK from the Motorola MPC82x is used for CLKI The address inputs AB 17 0 and the data bus DB 15 0 connect directly to the MPC82x address A 14 31 and data bus D 0 15 respectively CNF4 must be set to select big endian mode Chip Select CS must be driven low by CS4 whenever the S1D13A04 is accessed by the Motorola MPC82x M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address line A13 allowing system address A13 to select between memory or register accesses WEO connects to WE1 the low byte enable signal from the MPC82x and must be driven low when the MPC82x is writing the low byte to the S1ID13A04 WEIl connects to WEO the high byte enable signal from the MPC82x and must be driven low when the MPC82x is writing the high byte to the S1D13A04 RD and RD WRi are read enables for the low order and high order
240. ale Si acs A ee wae 162 18 Sales and Technical Support lt lt ee ee es 163 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center List of Tables Table 4 1 PFBGA 121 pin Mapping 0 0000 Table 4 2 Host Interface Pin Descriptions o o e Table 4 3 LCD Interface Pin Descriptions o e Table 4 4 Clock Input Pin Descriptions o o e e Table 4 5 Miscellaneous Pin Descriptions o o Table 4 6 Power And Ground Pin Descriptions o o o Table 4 7 Summary of Power On Reset Opti0MS o e Table 4 8 Host Bus Interface Pin Mapping o e e Table 4 9 LCD Interface Pin Mapping e o o Table 5 1 Absolute Maximum Ratings e o Table 5 2 Recommended Operating Conditions o o e Table 5 3 Electrical Characteristics for VDD 3 3V typical Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide gt 1 Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 Table 6 3 Clock
241. alues for 4 Bpp Gray Shade Unused entries S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center 8 bpp gray shade Page 21 When configured for 8 bpp gray shade mode the green component of all 256 LUT entries may be used However this results in redundant values where each of the 256 pixel values can only be mapped into 1 of 64 gray shades Table 5 5 Suggested LUT Values for 8 Bpp Gray Shade Index Red Green o X O O O O O NIN O ES a O E AOS i ae jee 1 EN ERA CIA REN Blue Index gt O gt O A CO CO CG w w CO w CO GC w w w CG Y NI PL N DDN NN PS PY PY PY PS PY PO PO oj T m O ius CO N O O A Co N ojl T m o ius CO CO N O OI BY Co N o ma mn Unused entries Programming Notes and Examples Issue Date 2002 08 21 Red Green O amp gt al al zi sis o Co A ol O P O Q O O O mn O Blue S1D13A04 X37A G 003 05 Page 22 Epson Research and Development Vancouver Design Center 16 bpp gray shade The Look Up Table is bypassed at this color depth therefore programming the LUT is not required As with 8 bpp there are limitations to the colors which can be displayed In this mode the six bits of green are used to set the absolute intensity of the im
242. alyzer was used to verify operation of the interface hardware It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set up so that the S1D13A04 memory block is tagged as non cacheable to ensure that accesses to the S1D13A04 occurs in proper order and also to ensure that the MPC821 does not attempt to cache any data read from or written to the S1D13A04 or its display buffer The source code for this test routine is as follows BR4 equ 120 CS4 base register OR4 equ 124 CS4 option register MemStart equ 44 0000 address of S1D13A04 display buffer RevCodeReg qu 40 0000 address of Revision Code Register Start mfspr rl IMMR get base address of internal registers andis rl CL ASEEEE clear lower 16 bits to 0 andis r2 r0 0 clear r2 oris r2 r2 MemStart write base address ori r2 r2 0801 port size 16 bits select GPCM enable stw r2 BR4 r1 write value to base register andis r2 r0 0 clear r2 oris r2 r2 ffc0 address mask use upper 10 bits ori r2 r2 0708 normal CS negation delay CS clock inhibit burst stw r2 OR4 r1 write to option register andis r1 r0 0 clear rl oris r1 r1 MemStart point rl to start of S1D13A04 mem space Loop lbz r0 RevCodeReg r1 read revision code into rl b Loop branch forever end Note MPC8BUG does not support comments or symbolic equates These have been added for clarity only
243. ancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 EPSON Errata No X00Z P 001 01 Device S1D13A03 S1D13A04 S1D13A05 Description Setting EP4 FIFO Valid bit while NAKing an IN token Bit 5 of REG 402Ch indicates to the S1ID13A0x controller when data in the endpoint 4 FIFO is ready to be transferred to the host computer Changing the state of this bit at certain times may generate an error When the S1D13A0x USB controller receives an endpoint 4 IN request and endpoint 4 is not ready to transmit data REG 402Ch bit 5 0 the response is a NAK packet If endpoint 4 is toggled to a ready to transmit state just before a NAK response packet is sent the controller may erroneously send a zero length packet instead When this happens the data toggle state will be incorrectly set for the next endpoint 4 data transmit The following timing diagram shows the error occurring in section 3 2 aad 3 7 E f Host to Device INEP4 Token PKT _ _ _ IN EPA Token PKT IN EP4 Token PKT Device to Host _ NAK RPLY _ DATA PKT RPLY ZERO Length PKT CPU Write to EP4_VALID 1 N a B i This unexpected occurrence of a zero length packet may cause file system handling errors for some operating systems Page 2 Epson Research and Development Vancouver Design Center
244. and Development Vancouver Design Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SID13A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for this implementation of a S1D13A04 to Motorola MC68VZ328 microprocessor Table 4 1 Summary of Power On Reset Options S1D13A04 Power On Reset State Configuration Input 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 CNF3 Reserved Must be set to 1 CNF5 WAIT is active low CNF6 CLKI to BCLK divide ratio 2 1 EA configuration for Motorola MC68VZ328 microprocessor S1D13A04 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X37A G 012 01 Issue Date 01 10 12 Epson Research and Development Page 13 Vancouver Design Center 4 2 1 Register Memory Mapping The S1D13A04 requires two 256K byte segments in memory for the display buffer and its internal registers To accommodate this block size 1t is preferable but not required to use one of the chip selects from groups A or B Groups A and B can have a size range of 128K bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes Therefore any chip select other than CSAO would be suitable for the S1D13A04 interface In the example interfac
245. and Development Page 11 Vancouver Design Center Width dword 140 Height dword FO Bpp dword 8 Rotation dword 0 Note that all dword values are in hexadecimal therefore 140h 320 and FOh 240 When the display driver starts 1t will read these values in the registry and attempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the first mode table in your list A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that controls these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request Resource Management Issues The Windows CE 3 0 OEM must deal with certain display driver issues relevant to Windows CE 3 0 These issues require the OEM balance factors such as system vs display memory utilization video performance and power off capabilities The section Simple Display Driver Configuration on page 13 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display
246. and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 illustrates a typical memory access read cycle on the PC Card bus A 25 0 Eee ADDRESS VALID CE1 CE2 OE WAIT D 15 0 Hi Z DATA VALID ae Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle Figure 2 2 illustrates a typical memory access write cycle on the PC Card bus A 25 a ADDRESS VALID CE1 CE2 OE WAIT Hi Z ae Hi Z 2050 DATA VALID l Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the PC Card Bus S1D13A04 Issue Date 01 10 12 X37A G 005 01 Page 10 Epson Research and Development 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the PC Card bus Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte Vancouver Design Center The Generic 2 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13A04 configuration see Se
247. anging between big and little endian will move relative register offsets Use caution in interpreting the index and values to write to registers using the halWriteReg8 function to ensure that register are programmed correctly Nothing Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 118 Epson Research and Development Vancouver Design Center void halWriteReg16 Ulnt32 Index Ulnt16 Value Description Writes a 16 bit value to the S1D13A04 register at the requested offset Parameters Index 32 bit byte offset to the register to write Index is zero based from the beginning of register address space e g if Index 04h then the Memory Clock Configuration register will be written to and if Index 8000h then the BitBLT Control Register will be written to Value The word value to write to the register Return Value Nothing Changing between big and little endian will move relative register offsets Use caution in interpreting the index and values to write to registers using the halWriteReg8 function to ensure that register are programmed correctly void halWriteReg32 Ulnt32 Index Ulnt32 Value Description Writes a 32 bit value dword to the register at the requested offset Parameters Index 32 bit byte offset to the register to write Index is zero based from the beginning of register address space e g if Index 04h then the Memory Clock Configuration register will be written to and i
248. arting address to read data from Specifying a period uses the same starting address as the last Dump command performed Specifying a startaddr of two periods will back the start address by the size of len endaddrllen Determines how many units to continue dumping the contents of the display buffer A number without a prefix represents a physical ending address If an L prefix is used the number that follows represents len which is the number of bytes words dwords to be dumped Len is based on the unit size For example L8 when the unit size is 16 bit would cause the Dump command to dump 8 words from the starting address S1D13A04 X37A B 002 01 Page 6 1D13A04 X37A B 002 01 Epson Research and Development Vancouver Design Center F 8116132 startaddr endaddrllen data1 data2 data3 Fills a specified address range in the display buffer Where 8116132 The unit size 8 bit bytes 16 bit words 32 bit dwords If a unit size is not specified this command uses the unit size from the last Fill command performed If no previous Fill command has been issued the unit size defaults to 8 bit startaddr The starting address to begin filling at Specifying a period uses the same starting address as the last Fill command performed endaddrllen Determines how many units to fill the display buffer with A number without a prefix represents a physical ending address If a L prefix is used the number that
249. ata on endpoint 4 it must first detect that a NAK packet has been sent This is done by reading the EP4 Interrupt Status bit REG 4004h bit 4 If the EP4 FIFO Valid bit was not set the EP4 Interrupt Status bit is set only if a NAK packet has been sent When the local CPU detects the NAK it must immediately set the EP4 FIFO Valid bit before responding to the next IN token After filling the EP4 FIFO the steps to follow before setting the EP4 FIFO Valid bit are 1 Clear the EP4 Interrupt Status bit REG 4004h bit 4 2 Read the EP4 Interrupt Status bit REG 4004h bit 4 until it is set 3 Set the EP4 FIFO Valid bit REG 402Ch bit 5 1 Note The setting of the EP4 FIFO Valid bit is time critical The EP4 FIFO Valid bit must be set within 3 us after the EP4 Interrupt Status has been set internally by the S1D13A0x Errata No X00Z P 001 01 Issue Date 2002 08 22 EPSON 1D13A04 LCD USB Companion Chip Programming Notes and Examples Document Number X37A G 003 05 Copyright 2001 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may
250. ata to the S1D13A04 RD connects to nOE the read enable signal from the SA 1110 and must be driven low when the SA 1110 is reading data from the S1D13A04 WAIT connects to RDY and is a signal output from the S1D13A04 that indicates the SA 1110 must wait until data is ready read cycle or accepted write cycle on the host bus Since SA 1110 accesses to the S1D13A04 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Start BS and RD WR signals are not used for this Host Bus Interface and should be tied high connected to IOVpp The RESET active low input of the S1D13A04 may be connected to the system RESET Interfacing to the Intel StrongARM SA 1110 Microprocessor Issue Date 01 10 12 Epson Research and Development Vancouver Design Center 4 StrongARM SA 1110 to S1D13A04 Interface 4 1 Hardware Description Page 13 The SA 1110 microprocessor provides a variable latency I O interface that can be used to support an external LCD controller By using the Generic 2 Host Bus Interface no glue logic is required to interface the S1D13A04 and the SA 1110 A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2
251. ate 2003 05 01 Revision 6 0 X37A A 001 06 Page 66 Epson Research and Development Vancouver Design Center 6 4 5 Single Color 8 Bit Panel Timing Format 1 r VDP r VNDP FPFRAME ay FPLINE l fl f f fl fl fiaa f f f f fl FPDAT 7 0 X Invalid LINE1 X LINE2 X LINES X LINE4 XLINE239 XLINE240 Invalid LINE1 X LINE2 X FPLINE HDP HNDP 4 gt lt gt ES 2Ts 2T 2T 4T 2T 2Ts 2Ts 2Ts 2Ts s FPSHIFT ICAA f e 2Ts 4Ts 2Ts 2Ts ATs 2Ts 4Ts 2 s 2Ts 4Ts 2Ts 2Ts 4Ts 2Ts 2Ts 4Ts 2Ts de FPSHIFT2 2Ts 2Ts 4Ts 2Ts 2Ts 2Ts 2Ts 2Ts FPDAT7 nvalid 1 R1 DA 1 66 X hair PI Pe a Y Y TA invalid FPDAT6 inaid AMERO XO OOOO mata YX FPDAT5 Invalid Mrs wea ver Y va kmay ras CAE 3 X X valid FPDAT4 invalid Mae Vea SY Oe iS NOA maid y FPDAT3 Invalid May ra ar ES Y X Invalid FPDAT2 Invalid rr ras ro a rors fer ed SS Y ene Invalid FPDAT1 Invalid DOE OE AS XX fa Invalid FPDATO Invalid DOE a APA XX an invalid Notes The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FRSHIFT FPSHIFT2 rising edges Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 6 21 Single Color 8 Bit Panel Timing Format 1
252. ax 089 14005 110 http www epson electronics de 7 2 Intel StrongARM SA 1110 Processor INTEL Intel Customer Support ICS for StrongARM 800 628 8686 Website for StrongARM Processor http developer intel com design strong Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Intel StrongARM SA 1110 Microprocessor Issue Date 01 10 12 1D13A04 X37A G 013 01 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12
253. being left untouched Bits set to one are expanded to the foreground color Use this BitBLT operation to overlay text onto any background while leaving the background intact Refer to the Color Expansion BitBLT for sample calculations and keep the following points in mind e Program the BitBLT operation bits REG 8008h bits 3 0 to 09h instead of 08h e Setting a background color REG 8020h is not required 9 2 4 Solid Fill BitBLT 1D13A04 X37A G 003 05 The Solid Fill BitBLT fills a rectangular area of the display buffer with a solid color This operation is used to paint large screen areas or to set areas of the display buffer to a given value This BitBLT operation is self completing After setting the width height destination start position and foreground color the BitBLT engine is started When the region of display memory is filled with the given color the BitBLT engine will automatically stop Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 75 Vancouver Design Center Example 11 Fill a red 9 x 301 rectangle at the screen coordinates x 100 y 10 us ing a 320x240 display at a color depth of 16 bpp 1 Calculate the destination address upper left corner of the destination rectangle using the following formula DestinationAddress y X ScreenStride x x BytesPerPixel 10 x 320 x 2 100 x 2 6600 19C8h where BytesPerPixel 1 for 8 bpp BytesPerP
254. bit CPU instructions are required The data is not directly written to read from the display buffer It is written to read from the BitBLT FIFO through the 64K byte BitBLT aperture specified at the address of REG 10000h The 16 word FIFO can be written to only when not full and can be read from only when not empty Failing to monitor the FIFO status can result in a BitBLT FIFO overflow or underflow While the FIFO is being written to by the CPU it is also being emptied by the S1D13A04 If the S1D13A04 empties the FIFO faster than the CPU can fill it it may not be possible to cause an overflow underflow In these cases performance can be improved by not monitoring the FIFO status However this is very much platform dependent and must be determined for each system Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 67 Vancouver Design Center 9 2 1 Write BitBLT with ROP Write BitBLTs increase the speed of transferring data from system memory to the display buffer The Write BitBLT with ROP accepts data from the CPU and writes it into display memory This BitBLT is typically used to copy a bitmap image from system memory to the display buffer Write BitBLTs support 16 ROPs the most frequently used being ROP OCh Copy Source to Destination Write BitBLTs support both rectangular and linear destinations Using a linear destination it is possible to move an image to off screen memory in a compact forma
255. ble 7 1 Table 8 1 Table 8 2 Table 8 3 Table 8 4 Table 9 1 Table 9 2 Table 9 3 Table 9 4 Table 9 5 Table 9 6 Table 9 7 Table 9 8 Table 10 1 Table 11 1 Programming Notes and Examples Issue Date 2002 08 21 List of Tables Look Up Table Configurations 0 0 0 0000000000 0004 18 Suggested LUT Values for 1 Bpp Gray Shade o o 19 Suggested LUT Values for 4 Bpp Gray Shade o o 19 Suggested LUT Values for 4 Bpp Gray Shade o ee 20 Suggested LUT Values for 8 Bpp Gray Shade o o 21 Suggested LUT Values for 1 bpp Color o oo o 22 Suggested LUT Values for 2 bpp Color o ooo e 22 Suggested LUT Values for 4 bpp Color 2 2 2 0 0 222200000084 23 Suggested LUT Values 8 bpp Color oo o o e 24 SwivelView Mode Select Bits 2 2 20 0 00 00 0000 0000000 30 32 bit Address Increments for PIP X Position in SwivelView 0 and 180 40 32 bit Address Increments for Color Depth o o e 41 32 bit Address Increments for Color Depth o o o 42 32 bit Address Increments for Color Depth oo o 44 BitBLT FIFO Words Available o o e 60 BitBLT ROP Code Color Expansion Function Selection 61 BitBLT Operation Selection o o 62 BitBLT Source Start Add
256. ble signal from the NEC VR4181A and must be driven low when the NEC VR4181A is reading data from the S1D13A04 WAIT connects to IORDY and is a signal which is output from the S1D13A04 which indicates the NEC VR4181A must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4181A accesses to the S1D13A04 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the NEC VR4181A interface using the Generic 2 Host Bus Interface These pins must be tied high connected to IO Vpp Interfacing to the NEC VR4181A Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 008 01 Page 12 4 VR4181A to S1D13A04 Interface 4 1 Hardware Description Epson Research and Development Vancouver Design Center The NEC VR4181A microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 Host Bus Interface no glue logic is required to interface the S1D13A04 to the NEC VR4181A A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle MEMCS 16 of the NEC VR4181A is
257. bled will drastically impact display driver performance and should only be used to track down failures in the BLT operations This option should be disabled unless doing BLT debugging A second variable which will affect the finished display driver is the register configurations contained in the mode file The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13A04CFG EXE The display driver comes with one example MODE table e MODEO H LCD 8 bit STN color 320x240 8bpp 70Hz By default only MODEO H is used by the display driver New mode tables can be created using the 13A04CFG program Edit the include section of MODE H to add the new mode table If you only support a single mode table you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13A04 Windows CE 3 x Display Driver Issue Date 01 10 19 Epson Research
258. c by OEMs For further information on 13A04CFG see the 13A04CFG Configuration Program User Manual document number X37A B 001 xx Note The QNX display drivers are provided as reference source code only They are intend ed to provide a basis for OEMs to develop their own drivers for QNX Photon v2 0 This document and the source code for the QNX display drivers are updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com QNX Photon v2 0 Display Driver S1D13A04 Issue Date 01 10 19 X37A E 005 01 Page 4 Epson Research and Development Vancouver Design Center Building the Photon v2 0 Display Driver 1D13A04 X37A E 005 01 The following steps build the Photon v2 0 display driver and integrate it into the QNX operating system These instructions assume the QNX developer environment is correctly installed and the developer is familiar with building for the QNX operating system Unpack the Graphics Driver Development Kit Archive 1 Install the QNX ddk package using the Package Manager utility For information about the Drivers Development Kit contact QNX directly 2 Once the ddk package is installed copy the directory tree usr scr gddk_v1 0 into the Project directory 3 Change directory to Project gddk_1
259. cally placed at the start of display memory which is at display address 0 main window display start address register desired byte address 4 0 Program the Main Window Display Start Address register REG 40h is set to 00000000h S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 33 Vancouver Design Center 2 Determine the main window line address offset number of dwords per line image width 32 bpp 320 32 4 40 28h Program the Main Window Line Address Offset register REG 44h is set to 00000028h Example 2 In SwivelView 90 mode program the main window registers for a 320x240 panel at a color depth of 4 bpp 1 Determine the main window display start address The main window is typically placed at the start of display memory which is at dis play address 0 main window display start address register desired byte address panel height x bpp 8 4 panel height x bpp 8 amp 03h 4 1 0 240 x 4 8 4 240 x 4 8 amp 03h 4 1 29 1Dh Program the Main Window Display Start Address register REG 40h is set to 0000001Dh 2 Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset register REG 44h is set to 0000001Eh Programming Notes and Examples S1D13A04 Issue
260. cated fractional part Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 56 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center Program the PIP Window X Positions register with the X Start Position in bits 9 0 and the X End Position in bits 25 16 REG 58h is set to OOEFOOSOh Program the PIP Window Y Positions register with the Y Start Position in bits 9 0 and the Y End Position in bits 25 16 REG 5Ch is set to 00160007h Due to truncation the dimensions of the PIP window may have changed Recalculate the PIP window width and height below PIP Width REG 5Ch bits 25 16 REG S5Ch bits 9 0 1 x 32 bpp 16h 07h 1 x 32 4 128 pixels note that this is different from the desired width PIP Height REG 58h bits 25 16 REG 58h bits 9 0 1 EFh 50h 1 160 lines Determine the PIP display start address The main window image must take up 320 x 240 pixels x bpp 8 9600h bytes If the main window starts at address Oh then the PIP window can start at 9600h PIP Stride image width x bpp 8 128x4 8 64 40h PIP display start address desired byte address PIP height 1 x PIP Stride 4 9600h 160 1 x 64 4 12144 2F70h Program the PIP Display Start Address register REG 50h is set to 00002F70h Determine the PIP line address offset number of dwords per line image width 32
261. ce for the CLKI2 input of the S1D13A04 may be used The address inputs AB 17 0 and the data bus DB 15 0 connect directly to the PC Card address A 17 0 and data bus D 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address line A18 allowing system address A18 to select between memory or register accesses WE 1 connects to CE2 the high byte chip select signal from the PC Card interface which in conjunction with address bit 0 allows byte steering of read and write opera tions WEO connects to WE the write enable signal form the PC Card bus and must be driven low when the PC Card bus is writing data to the S1D13A04 RD connects to OE the read enable signal from the PC Card bus and must be driven low when the PC Card bus is reading data from the S1D13A04 WAIT is a signal output from the S1D13A04 that indicates the PC Card bus must wait until data is ready read cycle or accepted write cycle on the host bus Since PC Card bus accesses to the S1D13A04 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or display buffer T
262. ces described in this document do not attempt to support burst cycles 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Ya clock cycle The CSNT bit causes chip select and WE to be negated 1 2 clock cycle earlier than normal The TRLX relaxed timing bit inserts an additional one clock delay between assertion of the address bus and chip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit inserts an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted or the peripheral can terminate the bus cycle itself by as
263. ch pixel from the pattern is the first pixel in the destination rectangle the pattern start phase This allows seamless redrawing of any part of the screen using the pattern fill Example 16 Fill a 100 x 150 rectangle at the screen coordinates x 10 y 20 with the pattern in off screen memory at offset 27000h using a 320x240 dis play at a color depth of 8 bpp The first pixel upper left corner of the rectangle is the pattern pixel at x 3 y 4 1 Calculate the destination address upper left corner of the destination rectangle using the formula DestinationAddress y X ScreenStride x x BytesPerPixel 20 x 320 10 x 1 6410 190Ah where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixels 320 for 8 bpp Program the BitBLT Destination Start Address Register REG 8010h is set to 190Ah Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 85 Vancouver Design Center 2 Calculate the source address This is the address of the pixel in the pattern that is the origin of the destination fill area The pattern begins at offset 156K but the first pattern pixel is at x 3 y 4 Therefore an offset within the pattern itself must be calculated SourceAddress PatternOffset StartPatternY x 8 x BytesPerPixel StartPatternX x BytesPerPixel 156K 4x8x1 3x1 156K 35 159779 27023h where Byt
264. chi SH 4 Interface Timing Revision 6 0 Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Page 43 Vancouver Design Center Table 6 11 Hitachi SH 4 Interface Timing Symbol Parameter Min Max Unit fcKlo Bus clock frequency 66 MHz Tckio Bus clock period 1Ackio ns t1 A 16 1 M R RD WR setup to CKIO 1 ns t2 BS setup 1 ns t3 BS hold 5 ns t4 CSn setup 1 ns t5 WEn RD setup to 2nd CKIO rising edge after BS low 0 ns t6 Falling edge CSn to RDY driven high 3 10 ns 7 D 15 0 setup to 3rd CKIO rising edge after BS deasserted 4 Tens write cycle t8 Falling edge RD to D 15 0 driven read cycle 2 12 ns t9 WE RD deasserted to A 16 1 M R RD WR deasserted 0 ns t10 RDY falling edge to BS falling Texto 11 ns t11 WE RD deasserted to CS high 0 ns 112 D rising edge before RDY deasserted to WEn RD asserted 2 Toad or next cycle t13 RDY falling edge to WE RD deasserted 0 ns t14 Rising edge CSn to RDY rising edge 3 10 ns t15 CKIO falling edge to RDY tristate 3 ns t16 D 15 0 hold from WEn deasserted write cycle 3 ns t17 D 15 0 setup to CKIO falling edge read cycle 12 ns t18 Rising edge of RD to D 15 0 high impedance read cycle 1 4 ns t19 Cycle Length 4 Tckio Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 44 6 2 5 Motorola MC68K 1 Interfac
265. cles the SA 1110 starts sampling the data ready input RDY Samples are taken every half memory cycle until three consecutive samples at the rising edge falling edge and following rising edge of the memory clock indicate that the IO device is ready for data transfer Read data is latched one half memory cycle after the third successful sample on falling edge Then nOE or nWE is deasserted on the next rising edge and the address may change on the subsequent falling edge Prior to a subsequent data cycle nOE or nWE remains deasserted for RDN 1 memory cycles The chip select and byte selects nCAS 1 0 for 16 bit data transfers remain asserted for one memory cycle after the final nOE or nWE deassertion of the burst The SA 1110 is capable of burst cycles during which the chip select remains low while the read or write command is asserted precharged and reasserted repeatedly Figure 2 1 illustrates a typical variable latency IO access read cycle on the SA 1110 bus A 25 0 ADDRESS VALID nCS4 nOE nWE RDY D 31 0 nCAS 3 0 K X DATA VALID Figure 2 1 SA 1110 Variable Latency IO Read Cycle Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 illustrates a typical variable latency IO access write cycle on the SA 1110 bus A 25
266. config pcPentium config h with the file x 13A04 8bpp File config h or x 13A04 16bpp File config h The new con fig h file removes networking components and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build aboot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as the image 4 Create a bootable disk in drive A From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get config pcPentium and type mkboot a bootrom_uncmp S1D13A04 Wind River WindML v2 0 Display Drivers X37A E 002 01 Issue Date 01 09 28 Epson Research and Development Page 5 Vancouver Design Center 5 If necessary generate a new mode0 h configuration file The file mode0 h contains the register values required to set the screen resolution col or depth bpp display type rotation etc The mode0 h file included with the drivers may not contain applicable values and must be regenerated The configuration pro gram 13A04CFG can be used to build a new mode0 h file If building for 8 bpp place the new mode0 h file in the directory x 13A04 8bpp File If building for 16 bpp place the new mode0 h file in x 1
267. connected to LCDCS to signal that the S1D13A04 is capable of 16 bit transfers BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to IO Vpp The diagram below shows a typical implementation of the VR4181A to S1D13A04 interface NEC VR4181A 1D13A04 MEMWR gt WEO UBE gt WE1 MEMRD RD A18 M R LCDCS hg gt CS Pull up IORDY l WAIT MEMCS16 lt _ System RESET RESET H A 17 0 gt AB 17 0 D 15 0 e gt DB 15 0 SYSCLK gt CLKI lOVpp o BS RD WR Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of VR4181A to SLDI3A04 Interface 1D13A04 X37A G 008 01 Interfacing to the NEC VR4181A Microprocessor Issue Date 01 10 12 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SIDI3A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for
268. contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center b Q N Table of Contents Introduction 1 we uu Identifying the S1D13A04 2 2 2 ee et INItIAlIZATION o 02 po tec ke aS edie Sank ee eo ees Gd Memory Models i gana ec Gk Bee a alk ee wea a a 4 1 Display Buffer Location i 4 2 Memory Organization for One Bit per ad e Colors Gray Shades 4 3 Memory Organization for Two Bit per pixel 4 Colors Gray Shades 4 4 Memory Organization for Four Bit per pixel 16 Colors Gray Shades 4 5 Memory Organization for 8 Bpp 256 Colors 64 Gray Shades 4 6 Memory Organization for 16 Bpp 65536 Colors 64 Gray Shades Look Up Table LUT o 5 1 Registers 5 1 1 Look Up Table Write ee tar Goa Ee Bo ae Ge Wh ae Be a te eB at 5 1 2 Look Up Table Read Registers 00 4 5 2 Look Up Table Organization 5 2 1 Gray Shade Mode Si ar ie alah thn Oa aie BE A E aes NE ae ee 5222 COIE Modest 00 ta eesti Se ue eee YR ee ds Sette oie Aaa de es Power Save Mode 0 0 lt lt ee ee
269. controlled GPIO pins from the S1D13A04 see Figure 2 4 HR TFT Power On Off Sequence Timing t1 t2 lt M gt e GPIOx VSHD power 13 t4 GPIOy other power t5 i GPO MOD Power Save Mode Enable REG AOH bit 0 l t8 t7 Acti J LCD Signals SNS It is recommended to use one of the general purpose IO pins GPIO 6 4 to control the digital power supply VSHD It is recommended to use one of the general purpose lO pins GPIO 6 4 to control the other power supplies required by the HR TFT panel The S1D13A04 LCD power on off sequence is activated by programming the Power Save Mode Enable bit REG AOh bit O LCD Signals include FPDAT 17 0 FPSHIFT FPLINE FPFRAME and GPIO 3 0 Figure 2 4 HR TFT Power On Off Sequence Timing Table 2 1 HR TFT Power On Off Sequence Timing Symbol Parameter Min Max Units t1 LCD Power VSHD active to Power Save Mode disabled 0 ns t2 LCD signals low to LCD Power VSHD inactive 0 ns t3 Power Save Mode disabled to LCD Power other active 0 ns t4 LCD Power other inactive to Power Save Mode enabled 0 ns t5 LCD Power other active to MOD active 2 FRAME t6 MOD inactive to LCD Power other inactive 0 ns t7 Power Save Mode disabled to LCD signals active 20 ns t8 Power Save Mode enabled to LCD signals low 20 ns Connecting to the Sharp HR TFT Panels S1D
270. ct 6 Panel Data Width SW Video Invert Dithering Disable MOD Rate 19 18 17 16 Direct HR TFT n a Panel Type Res Select 3 2 al 0 SwivelView Mode Select Bits per pixel Select actual value 1 2 4 8 16 bpp Direct HR TFT GPO Control 0 LUT Green 13 LUT Green 13 Register Summary Issue Date 01 10 02 Write Data 12 LUT Read Address write only Read Data 12 LUT Red Write Data LUT Blue Write Data 10 9 8 LUT Red Read Data LUT Blue Read Data 10 8 n a 17 16 a il 0 S1D13A04 X37A R 001 01 Page 2 Epson Research and Development Vancouver Design Center DISPLAY MODE REGISTERS n a n a Horizontal Total bits 6 0 n a n a Horizontal Display Period bits 6 0 n a Horizontal Display Period Start Position bits 9 0 FPLINE Polarity FPLINE Pulse Width bits 6 0 5 31 3 27 20 19 18 5 n a 14 13 12 1 10 0 29 28 26 n a FPLINE Pulse Start Position bits 14 13 12 i 10 9 5 4 n a 14 13 12 il 10 il i n a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Vertical Total bits 9 0 15 1 9 8 7 6 5 4 3 2 1 0 n a Vertical Display Period bits 9 0 3 FPFRAME a FPFRAME Pulse Width Polarity bits 2 0 FPFRAME Pulse Start Position bits 9 0 AAA n a 31 30 29 28 27 26 25 3 21 20 19 18 17 24 2 22 Main Window Display Start Address bits 15 0 9 8 7 6 5 4 3 2 1 n a 15 14 13 12 11 10 1 30 29 28 27 26 n a Vertical Di
271. ction 4 2 S1D13A04 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping 1D13A04 Pin Names PC Card PCMCIA AB 17 0 A 17 0 DB 15 0 D 15 0 WE1 CE2 CS External Decode M R A18 CLKI see note BS Connect to lOypp from the S1D13A04 RD WR Connect to lOypp from the S1D13A04 RD OE WEO WE WAIT WAIT RESET Inverted RESET Note Although a clock is not directly supplied by the PC Card interface one is required by the S1D13A04 Generic 2 Host Bus Interface For an example of how this can be accom plished see the discussion on CLKI in Section 3 2 Host Bus Interface Signals on page 11 S1D13A04 X37A G 005 01 Interfacing to the PC Card Bus Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The S1D13A04 Generic 2 Host Bus Interface requires the following signals from the PC Card bus Interfacing to the PC Card Bus Issue Date 01 10 12 CLKI is a clock input which is required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock Since the PC Card signalling is independent of any clock CLKI can come from any oscillator already implemented For example the sour
272. ctual value 1 2 4 8 or 16 bpp 3 2 1 Select PIP Window Enable The PIP Window Enable bit enables a PIP window within the main window The loca tion of the PIP window within the landscape window is determined by the PIP X Posi tion register REG 58h and PIP Y Position register REG 5Ch The PIP window has its own Display Start Address register REG 50h and Line Address Offset register REG 54h The PIP window shares the same color depth and Swivel View orientation as the main window PIP Display Start Address Register REG 50h Default 00000000h Read Write n a bit 16 26 25 24 23 22 16 PIP Display Start Address bits 15 0 10 9 8 7 6 0 PIP Display Start Address The PIP Display Start Address register is a DWORD which represents an address that points to the start of the PIP window image in the display buffer An address of 0 is the start of the display buffer For the following PIP descriptions the desired byte address is the starting display address for the PIP window image In SwivelView 0 program the start address desired byte address 4 In SwivelView 90 program the start address desired byte address PIP width x bpp 8 4 PIP width x bpp 8 amp 03h 4 1 In Swivel View 180 program the start address desired byte address PIP Stride x PIP height 1 PIP width x bpp 8 4 PIP width x bpp 8 amp 03h
273. d 26 Ground 27 5 volt supply 28 5 volt supply 29 Connected to RD WR of the S1D13A04 30 Connected to BS of the S1D13A04 31 Connected to BUSCLK of the S1D13A04 32 Connected to RD of the S1D13A04 33 Not connected 34 Not connected S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Epson Research and Development Page 17 Vancouver Design Center 5 LCD Interface Pin Mapping Table 5 1 LCD Signal Connector H1 Monochrome Passive Panel Color Passive Panel Color TFT Panel Pin Name Connector Single Sharp Pin No Single Pomar Fond Others HR TFT 4 bit 8 bit 4 bit 8 bit 8 bit 16 Bit 9 bit 12 bit 18 bit 18 bit FPDATO 1 DO Do B5 Do G3 DO R6 R2 R3 R5 R5 FPDAT1 3 D1 D1 R5 D1 R3 D1 G5 R1 R2 R4 R4 FPDAT2 5 D2 D2 G4 D2 B2 D2 B4 RO R1 R3 R3 FPDAT3 7 D3 D3 B3 D3 G2 D3 R4 G2 G3 G5 G5 FPDAT4 9 DO D4 Do R2 D4 R3 D4 R2 Da B5 G1 G2 G4 G4 FPDAT5 11 D1 D5 D1 B1 D5 G2 D5 B1 D9 R5 GO G1 G3 G3 FPDAT6 13 D2 D6 D2 G1 D6 B1 De Gt D10 G4 B2 B3 B5 B5 FPDAT7 15 D3 D7 D3 R1 D7 R1 D7 R1 D11 B3 B1 B2 B4 B4 FPDAT8 17 D4 G3 BO B1 B3 B3 FPDAT9 19 D5 B2 RO R2 R2 FPDAT10 21 D6 R2 R1 R1 FPDAT11 23 D7 G1 RO RO F
274. d Control Register REG 64h Default 20000000h Read Write GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIOO Input Input Input Input Input Input Input Input GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIOO Enable Enable Enable Enable Enable Enable Enable Enable Conf a Config Config Config Config Config Config Config 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TA GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIOO Status Status Status Status Status Status Status Status 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note The GPIO pins default as inputs after power up and must be configured using the bits in this register Note For information on GPIO pin mapping when the direct HR TFT LCD interface is se lected see Table 4 9 LCD Interface Pin Mapping on page 32 bits 31 24 GPIO 7 0 Pin Input Enable bits These bits are used to enable the input function of each GPIO pin They must be changed to a 1 after power on reset to enable the input function of the corresponding GPIO pin default is 0 Note The default for GPIOS Pin Input Enable is 1 bits 23 16 GPIO 7 0 Pin IO Configuration When this bit 0 default the corresponding GPIO pin is configured as an input pin When this bit 1 the corresponding GPIO pin is configured as an output pin Note The input function of each GPIO pin must be enabled using the GPIO 7 0 Pin Input En able bi
275. d Write R W signal which is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each has a unique fixed offset from a common programmable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for e port size 8 16 32 bit e up to 15 wait states or external acknowledge e address space type e burst or non burst cycle support e write protect Figure 2 3 Chip Select Module Outputs Timing illustrates a typical cycle for a memory mapped device using the GPCM of the Power PC ox LL pod l CS 7 0 BE BWE 3 0 aD OE 1D13A04 X37A G 010 01 Figure 2 3 Chip Select Module Outputs Timing Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 10 12 Epson Research and Development Vancouver Design Center 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 1 Host Bus Interface which is most suitable for direct connection to the Motorola MFC5307 m
276. d as the export type additional options are available and can be selected by clicking on the Options button The options dialog appears as Export Options Ed Cancel Cursor C Software Cursor No Cursor Cursor Support selects the type of cursor support enabled in the header file Mode Number selects the mode number for use in the header file SW Acceleration enables software BitBLT acceleration gt M Software Acceleration paetae o M Hardware Accelertion HW Acceleration 5 enables hardware BitBLT acceleration Mode number 0 E in the header file S1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Page 27 Vancouver Design Center Enable Tooltips Tooltip Delay ERD on the Web Tooltips provide useful information about many of the items on the configuration tabs Placing the mouse pointer over nearly any item on any tab generates a popup window containing helpful advice and hints To enable disable tooltips check uncheck the Tooltips option form the Help menu Note Tooltips are enabled by default This option sets the length of time the cursor must be left over an item before its associated tooltip is displayed This Help menu item is actually a hotlink to the Epson Research and Development website Selecting Help then ERD on the Web starts the default web browser and points it to the ERD product web site
277. d bus A18 is connected to the 1D13A04 M R pin The internal registers occupy the first 256K byte block and the 160K byte display buffer occupies the second 256K byte block The PC Card socket provides 64M bytes of memory address space However the S1D13A04 only needs a 512K byte block of memory to accommodate its 160K byte display buffer and register set For this reason only address bits A 18 0 are used while A 25 19 are ignored The S1D13A04 s memory and registers are aliased every 512K bytes in the 64M byte PC Card memory address space Note If aliasing is not desirable the upper addresses must be fully decoded Interfacing to the PC Card Bus S1D13A04 Issue Date 01 10 12 X37A G 005 01 Page 14 5 Software 1D13A04 X37A G 005 01 Epson Research and Development Vancouver Design Center Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The 1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Support or www erd epson com Interfacing to the PC Card Bus Is
278. d vertical pixel doubling e example usage 160x160 8 bpp can be expanded to 320x320 8 bpp without any addi tional memory Double Buffering Multi pages provides smooth animation and instantaneous screen updates 2 6 Clock Source e Three independent clock inputs CLKI CLKI2 and USBCLK Flexible clock source selection e internal Bus Clock BCLK selected from CLKI or CLKI 2 CNF6 e internal Memory Clock MCLK selected from BCLK or BCLK divide ratio REG 04h e internal Pixel Clock PCLK selected from CLKI CLKI2 MCLK or BCLK PCLK can also be divided down from source REG 08h Single clock input possible if USB support not required 2 7 USB Device USB Client revision 1 1 compliant Dedicated clock input USBCLK 2 8 2D Acceleration e 2D BitBLT engine including Write BitBLT Transparent Write BitBLT Move BitBLT Transparent Move BitBLT Solid Fill BitBLT Read BitBLT Pattern Fill BitBLT Color Expansion BitBLT Move BitBLT with Color Expansion Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 14 2 9 Miscellaneous 1D13A04 X37A A 001 06 Software Video Invert Software initiated Power Save mode General Purpose Input Output pins are available IO Operates at 3 3 volts 10 Core operates at 2 0 volts 10 or 2 5 volts 10 121 pin PFBGA package 128 pin TQFP15 package Revision 6 0 Epson Research and Development Vancouver Design C
279. dd the environment variable USB_S1D13A04 a From the Platform menu select Settings b Select the Environment tab c In the Variable box type USB_S1D13A04 d Inthe Value box type 1 e Click the Set button f Click the OK button Windows CE 3 x USB Driver Issue Date 01 10 19 Epson Research and Development Vancouver Design Center Page 5 7 Create a new directory 13A04USB under x wince300 platform cepc drivers and copy the 13A04USB driver source code into this new directory 8 Add the 13A04USB driver component a b c f From the Platform menu select Insert User Component Set Files of type to All Files Select the file x wince300 platform cepc drivers 13A04USB sources Click the OK button In the User Component Target File dialog box select browse and then select the path filename of the file sources Click the OK button 9 From the Platform window click the Parameter View Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and then click the Hardware Specific Files and then double click the PLATFORM BIB Edit the file platform bib and make the following two changes Windows CE 3 x USB Driver Issue Date 01 10 19 Find the section shown below and insert the line as marked IF IMGUSB IF CEPC_UHCI uhci dll S FLATRELEASEDIR uhci dll NK SH ENDIF IF
280. demarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the PC Card Bus X37A G 005 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introduction se ra ras Gy Blais A AAA A Re ee A ee Be 7 2 Interfacing tothe PC CardBus 002 2c eee ee ee 8 2 1 ThePCCardSystemBus 2 2 2 2 8 Z PCCard OVenviews secs ak a Soe ae ks oe ees Fae aed a Loa ya 8 2 1 2 Memory Access Cycles o o e 8 3 S1D13A04 Host Bus Interface o 10 3 1 Host Bus Interface Pin Mapping e 10 3 2 Host Bus Interface Signals o oo a so ao s eee 11 4 PC Card to S1D13A04 Interface o n 12 4 1 Hardware Connections a ee ee 1 4 2 S1D13A04 Hardware Configuration 13 4 3 Register Memory Mapping 2 13 5 SOTMWANG od E A A a el E Se E 14 Helerences aaa A DAA adi la A 15 6 1 DOCUMENTS wie ario a e at e a ay oe et de AO 6 2 Document Sources a a a ee ee ee ee ee ee IS 7 Sales and Technical Support 16 7 1 EPSON LCD USB Companion Chips SID13A04 16 7 2 PC Card Standard e 16 Interfacing to the PC Card Bus S1D13A04 Issue Date 01 10 12 X37A G 005 01 Page 4 Epson Research a
281. dge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge t6 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 3 Ts t9 FPSHIFT period 5 Ts t10 FPSHIFT pulse width low 2 Ts t11 FPSHIFT pulse width high 2 Ts t12 FPDAT 15 0 setup to FPSHIFT rising edge 2 Ts t13 FPDAT 15 0 hold to FPSHIFT rising edge 2 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 min t8min HPS t4min 4 18min HT 5 t4min HPW 6 min HPS 1 7 min HPS HDP HDPS 2 if negative add t3 pin 8 tl4min HDPS HPS t4 min if negative add t3min Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 72 Epson Research and Development Vancouver Design Center 6 4 8 Generic TFT Panel Timing VT 1 Frame 4 gt lt VPS yy VPW FPFRAME VDPS VDP FPLINE M P dl L L L L E e DRDY FPDAT 17 0 A HT 1 Line lt gt HPS PW eg FPLINE FPSHIFT DRDY HDPS HDP 4 diel gt FPDAT 17 0 invalid KOX a a SS invalid Figure 6 27 Generic TFT Panel Timing VT Vertical Total REG
282. ding data to the host controller using EndPoint 2 the mailbox EP2 Transmit ion 10 4 4 11 Clear EP2 valid bi _ 82 Section 10 4 4 on page 110 REG 4032h 0 Clear EP2 index register REG 401 8h 0 Initialize local count Idx 0 Copy byte to EP2 data Copy another byte REG 401Ah pBuffer Idx lt 8 Yes Increment pointer pBuffer Clear EP2 interrupt status EP2 will now respond to REG 4004h 04h IN packets with data Set EP2 valid instead of NAKs REG 4032h 01h Figure 10 3 EndPoint 2 Data Transmission Note In this diagram reference is made to two pseudo variables Idx is an integer used as a loop counter pBuffer is a pointer to eight bytes of memory to send to the host Endpoint 4 Data Transmit Transferring data to the host controller using the FIFO controller has additional overhead as this routine must run tests to ensure error free data transmission 1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 103 Vancouver Design Center EP4 Transmit Determine size of packet PktSize min Remain FIFOSIZE Enqueue ZeroLengthPacket REG 4000h 40h Need to send ZLP PktSize 0 Initialize local Count Count 0 Copy another byte to FIFO Count lt PktSize Copy byte
283. document number X36A A 001 xx S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 13 Vancouver Design Center 3 Initialization This section describes how to initialize the S1D13A04 Sample code for performing initial ization of the S1D13A04 is provided in the file init13A04 c which is available on the internet at www erd epson com 1D13A04 initialization can be broken into the following steps 1 Set all registers to initial values The values are obtained by using the s1d13A04 h file that is exported by the 13A04CFG EXE configuration utility For more information on 13A04CFG see the 13A04CFG User Manual document number X37A B 001 xx 2 Program the Look Up Table LUT with color values For details on programming the LUT see Section 5 Look Up Table LUT on page 17 3 Clear the display buffer If the system implementation uses a clock chip instead of a fixed oscillator refer to the HAL Hardware Abstraction Layer sample code available on the internet at www erd epson com For example the Epson S5U13A04B00C evaluation board uses a Cypress clock chip Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 14 Epson Research and Development Vancouver Design Center 4 Memory Models The S1D13A04 contains a display buffer of 160K bytes and supports color depths of 1 2 4 8 and 16 bit per pixel For each color depth the dat
284. dow select the ComponentView tab Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree Right click on the ddi_flat component Select Delete From the File menu select Save Workspace 1D13A04 X37A E 006 01 Page 6 1D13A04 X37A E 006 01 Epson Research and Development Vancouver Design Center 10 From the Platform window click the ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking the sign at the root of the tree Expand the the WINCE300 tree and then click on Hardware Specific Files and then double click PLATFORM BIB Edit the file the PLATFORM BIB file and make the following two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13A04 ddi dll FLATRELEASEDIRAS1D13A04 d1l NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF DDI_S1D13A04 Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT653X IF CEPC_DDI_VGASBPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATT ddi dll _FLATRELEASEDIR ddi_flat dll NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Windows6 CE 3 x Display Driver Issue Date 01 10 19 Epson Research and Development Page 7 Vancouver Design Center 11 12 Modify MODEO H The file MODEO H located in x wince300 platform cepc drivers dis play S 1D13A04 contains the register values req
285. dpoint 4 Maximum Packet Size Register REG 402Eh Default 08h Read Write Endpoint 4 Max Packet Size bits 4 3 Revision Register REG 4030h Di Chip Revision bits 7 0 4 3 Status Register 4032h Read Write USB USB USB USB USB USB Endpoint4 Endpoint4 Endpoint4 Endpoint3 Endpoint3 Endpoint3 STALL NAK ACK STALL NAK ACK 7 6 5 4 3 2 1 0 Suspend Control Endpoint 2 Valid Frame Counter MSB Register REG 4034h Default 00h Read Only Frame Counter bits 10 8 1 Frame Counter LSB Register REG 4036h Default 00h Read Only Frame Counter bits 7 0 4 3 Extended Register Index REG 4038h D Extended Register Index bits 7 4 3 Extended Register Data REG 403Ah D Extended Register Data bits 7 0 4 3 Vendor ID MSB Vendor ID L REG 403Ah Index Default 04h Read Write REG 403Ah Default B8h Read Write Vendor ID bits 15 8 Vendor ID bits 7 0 4 3 4 3 uct ID MSB Product ID LSB 403Ah Index efault 88h Read Write REG 403Ah Index Default 21h Read Write Product ID bits 15 8 Product ID bits 7 0 4 3 4 3 Release Number MSB Release Nu REG 403Ah Index 04h efault 01h Read Write REG 403Ah Default 00h Read Write Release Number bits 15 8 Release Number bits 7 0 4 3 4 3 Receive FIFO Almost Full Threshold Transmit FIFO Almost Empty Threshold REG 403Ah Index 06h Default 3Ch Read Write REG 403Ah Index 07h Default 04h Read Write n a Receive FIFO Almost Full
286. dth and programmed using the following formula REG 44h bits 9 0 display width in pixels 32 bpp 320 pixels 32 8 bpp 80 50h Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 156 Epson Research and Development Vancouver Design Center 14 Picture in Picture Plus PIP 14 1 Concept Picture in Picture Plus PIP enables a secondary window or PIP window within the main display window The PIP window may be positioned anywhere within the virtual display and is controlled through the PIP Window control registers REG 50h through REG 5Ch The PIP window retains the same color depth and SwivelView orientation as the main window The following diagram shows an example of a PIP window within a main window and the registers used to position it o iaw TM 0 SwivelView PIP window y start position panel s origin REG 5Ch bits 9 0 PIP window y end position REG 5Ch bits 25 16 main window PIP window gt PIP window x start position PIP window x end position REG 58h bits 9 0 REG 58h bits 25 16 Figure 14 1 Picture in Picture Plus with SwivelView disabled S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 157 Vancouver Design Center 14 2 With SwivelView Enabled 14 2 1 SwivelView 90 90 SwivelView pan
287. e While the VR4181A has an embedded LCD controller this internal controller can be disabled to provide direct support for an external LCD controller through its external ISA bus A 64 to 512K byte block of memory is assigned to the external LCD controller with a dedicated chip select signal LCDCS Word or byte accesses are controlled by the system high byte signal UBE Interfacing to the NEC VR4181A Microprocessor Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Signals The S1D13A04 requires an addressing range of 256K bytes When the VR4181A external LCD controller chip select signal is programmed to a window of that size the S1D13A04 resides in the VR4181A physical address range of 133C 0000h to 133F FFFFh This range is part of the external ISA memory space The following signals are required to access an external LCD controller All signals obey ISA signalling rules A 16 0 is the address bus UBE is the high byte enable active low LCDCS is the chip select for the S1D13A04 active low D 15 0 is the data bus MEMRD is the read command active low MEMWR is the write command active low MEMCS16 is the acknowledge for 16 bit peripheral capability active low IORDY is the ready signal from 1D13A04 SYSCLK is the prescalable bus clock optional Once an address in the LCD block of memory is accessed the LCD chip select LCDCS is drive
288. e chip select CSB1 controls the 1D13A04 A 512K byte address space is used by setting the SIZ bits of Chip Select Register B FFFFF116h to 512k bytes The S1D13A04 internal registers occupy the first 256K byte block and the 160K byte display buffer is located in the second 256K byte block A18 from the MC68VZ328 is used to select between these two 256K byte blocks 4 2 2 MC68VZ328 Chip Select and Pin Configuration The chip select used to map the S1D13A04 in this example CSB 1 must have its RO Read Only bit set to 0 its BSW Bus Data Width set to 1 for a 16 bit bus and the WS Wait states bits should be set to 111b to allow the S1D13A04 to terminate bus cycles externally with DTACK The DTACK pin function must be enabled with Register FFFFF433 Port G Select Register bit 0 If Chip Select Group B is used as the chip select module for the 1D13A04 SRAM timing must be enabled by setting the Chip Select Control Register 1 FFFFF10Ah SR16 bit Ob Early cycle detection for static memory must be disabled by setting the Chip Select Control Register 2 FFFFF10Ch ECDS bit Ob If DTACK is not used then the WS bits should be set to either 4 6 10 or 12 software wait states depending on the divide ratio between the S1D13A04 MCLK and BCLK The WS bits should be set as follows Table 4 2 WS Bit Programming 1D13A04 MCLK to BCLK Divide Ratio WS Bits wait states MCLK BCLK 4 MCLK BCLK 2 6 MCLK BCL
289. e 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1IADACEG iret a SE oe ee eee be ee ee a eh et an ee et ee ae ge wee ee de 5 S1D13A04 Supported Evaluation Platforms 5 Installation 29 USAZE Ms a e erg te aed 5 13A04CFG Configuration Tabs A General Lab 44 2d sr A eo bot a a e italia dad 6 Preferences Tab a ur a it ds A Whew Aa Sar bela tas bs 8 ClocksilabDiz 2 da tt ETE da Sai De E ee ann ang Sie a ten rd es Bh es 2 10 Panel Tab it fathead ts see fe aah Ae ct ages hy eae ee ala Senet BANS he aa 14 Panel Power Lab cra tiny Aramid ae atk a Sie Bead A Sie Sad Dn 18 Registers ab n ari bd Rael Oe ae he She A a ae 20 Direct Tabi geet da eld Ae di Ne ge hale a Relat Be cabelas ae Ne Nae pl ori hea 21 13A04CFG Menus 23 Opein Bee ng Ges Se eae cg edi EA ea a Ser Sea heater ate Win Beebo e 23 SAVE ardent ta Tad Get sob Ag etal ab Aes a da eta dA ee 24 SV SI hs Min WAAL iat Se then eta ace ao hey tide aS iy Gon da Ath si 24 Configure Multiple occiso be eb ee kee eee 25 PROG fh ine dd e UA we ARE NEE e I as died ek da Ne bdo NA a 26 Enable Tooltips 2 iria Ea A Sew oar a he are Bes a 27 Tooltip Delay se ce ee ean t ee he ee ee ee ee 27 ERD on the Web o 2 45 43 es Geo ne bre a ey ee Sad Sa De Rt near e 27 Update Common Controls
290. e 4 Windows 2000 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards 9 Install the evaluation board in the computer and boot the computer Windows will detect the new hardware as a new PCI Device and bring up the FOUND NEW HARDWARE dialog box Click NEXT The New Hardware Wizard will bring up the dialog box to search for a suitable driver Click NEXT When Windows does not find the driver it will allow you to specify the location of it Type the driver location or select BROWSE to find it Click NEXT Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card Select this file and click OPEN Windows then shows the path to the file Click OK 10 Click NEXT 11 Click FINISH All ISA Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD REMOVE HARDWARE click NEXT Select ADD TROUBLESHOOT A DEVICE and click NEXT Windows 2000 will attempt to detect any new plug and play device and fail The CHOOSE HARDWARE DEVICE dialog box appears Select ADD NEW HARDWARE and click NEXT Select NO IWANT TO SELECT FROM A LIST and click NEXT Select OTHER DEVICE from the list and click NEXT Click HAVE DISK Specify the location of the driver files select the SID13XXX INF file and click OPEN Click OK S1D13XXX 32 Bit Windows Device Driver Installation G
291. e 91 Vancouver Design Center 8 3 LCD Register Descriptions Offset 0h Unless specified otherwise all register bits are set to 0 during power on 8 3 1 Read Only Configuration Registers Product Information Register REG 00h Default 2Cxx282Ch Read Only Product Code bits 5 0 a ae CNF 6 0 Status 31 30 29 28 27 26 25 24 23 22 21 20 19 17 16 Display Buffer Size bits 7 0 Product Code bits 5 0 e 13 12 11 10 5 4 1 0 bits 31 26 Product Code These read only bits indicate the product code The product code is 001011 OBh bits 25 24 Revision Code These are read only bits that indicates the revision code The revision code is 00 bits 22 16 CNF 6 0 Status These read only status bits return the status of the configuration pins CNF 6 0 CNF 6 0 are latched at the rising edge of RESET For a functional description of each configura tion bit CNF 6 0 see Section 4 4 Summary of Configuration Options on page 30 Note CNF3 Status bit 19 always reads back a 1 The CNF3 pin is reserved and must be set to 1 bits 15 8 Display Buffer Size Bits 7 0 This is a read only register that indicates the size of the SRAM display buffer measured in 4K byte increments The 1D13A04 display buffer is 160K bytes and therefore this regis ter returns a value of 40 28h Value of this register display buffer size 4K bytes 160K bytes 4K bytes 40 28h bits 7 2 Product Code These read only bits indicate the product code The prod
292. e BitBLT Width the last WORD may contain only one pixel In this case it is always in the low byte The number of WORD writes the BitBLT engine expects for 8 bpp color depths is shown in the following formula WORDS BitBLTWidth 1 SourcePhase 2 x BitBLTHeight Once the Transparent Write BitBLT begins the BitBLT engine remains active until all pixels have been written The BitBLT engine requires this number of WORDS to be sent from the local CPU before it ends the Transparent Write BitBLT operation Note The BitBLT engine counts WORD writes made to the BitBLT register This does not imply only 16 bit CPU instructions are acceptable If a system is able to separate one DWORD write into two WORD writes and the CPU writes the low word before the high word then 32 bit CPU instructions are acceptable Otherwise 16 bit CPU instruc tions are required Example 14 Write 100 x 20 pixels at the screen coordinates x 25 y 38 using a 320x240 display at a color depth of 8 bpp Transparent color is high in tensity blue assume LUT Index 124 1 Calculate the destination address upper left corner of the screen BitBLT rectangle using the formula DestinationAddress y X ScreenStride x x BytesPerPixel 38 x 320 25 x 1 12185 2F99h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixel 320 for 8 bpp Program the BitBLT Destination Start Address Regi
293. e Data Bits 5 0 These bits contains the data to be written to the blue component of the Look Up Table The LUT position is controlled by the LUT Write Address bits bits 31 24 When the S1D13A04 is set to a host bus interface using big endian CNF4 1 the RGB data is updated to the LUT with the completion of a write to these bits S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 99 Vancouver Design Center Look Up Table Read Register REG 1Ch Default 00000000h Write Only bits 31 24 Read Only LUT Read Address write only LUT Red Read Data n a 9 8 25 24 23 22 20 19 18 i 16 31 30 2 2 27 26 21 LUT Green Read Data n a LUT Blue Read Data n a 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note The S1D13A04 has three 256 position 6 bit wide LUTs one for each of red green and blue see Section 12 Look Up Table Architecture on page 145 bits 31 24 LUT Read Address Bits 7 0 Write Only This register forms a pointer into the Look Up Table LUT which is used to read LUT data Red data is read from bits 23 18 green data from bits 15 10 and blue data from bits 7 2 Note If a write to the LUT Write Address Bits REG 18h bits 31 24 is made the LUT Read Address bits are automatically updated with the same value bits 23 18 LUT Red Read Data Bits 5 0 Read Only These bits point to the data from the red component of the Look Up Table The LUT
294. e S1D13A04 and reads the registers Note after a semicolon all characters on a line are ignored Initialize the S1D13A04 i Read all registers xa 13A04PLAY Diagnostic Utility Issue Date 01 10 05 EPSON S1D13A04 LCD USB Companion Chip 13A04BMP Demonstration Program Document Number X37A B 003 01 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 13A04BMP Demonstration Program X37A B 003 01 Issue Date 01 10 04 Epson Research and Development Page 3 Vancouver Design Center 13A04BMP 13A04BMP is a demonstration utility used to show the S1D13A04 display capabilities by rendering bitmap images on the display device The program displays a bitmap
295. e Timing e g MC68000 Epson Research and Development Vancouver Design Center D 15 0 read 7 CLK CLK t 4 A 16 1 R W M R MD p t13 i hatte t4 l CS j t AS gt wo o t1 le ome t6 gt i UDS LDS AQ t7 AY t2 t8 EE DTACK t9 gt t1 D 15 0 write valid t12 t11 S1D13A04 X37A A 001 06 Figure 6 6 Motorola MC68K 1 Interface Timing Revision 6 0 Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Vancouver Design Center Table 6 12 Motorola MC68K I1 Interface Timing Page 45 Symbol Parameter Min Max Unit foLk Bus clock frequency 66 MHz Tok Bus clock period T foLk ns u Alt 6 1 M R R W and CS and AS and UDS LDS setup to ng first CLK rising edge t2 CS and AS asserted to DTACK driven 3 10 ns t3 UDS 0 or LDS 0 to D 15 0 driven read cycle 10 ns t4 A 16 1 M R R W and CS hold from AS rising edge ns t5 DTACK falling edge to UDS LDS rising edge ns t6 UDS LDS deasserted high to reasserted low 1 Telk t7 CLK rising edge to DTACK high impedance Telk 2 ns t8 AS rising edge to DTACK rising edge 3 11 ns 19 D 15 0 valid to 4th CLK rising edge where CS 0 AS 0 and 4 1 either UDS 0 or LDS 0 write cycle CLK t10 D 15 0 hold from UDS LDS fallin
296. e Windows CE v3 0 driver is updated as appro priate Before beginning any development please check the Epson Research and Devel opment Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Windows6 CE 3 x Display Driver S1D13A04 Issue Date 01 10 19 X37A E 006 01 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following section describes how to build the Windows CE display driver for Windows CE Platform Builder 3 00 using the GUI interface Build for CEPC X86 on Windows CE Platform Builder 3 00 using the GUI Interface 1 Install Microsoft Windows 2000 Professional or Windows NT Workstation version 4 0 with Service Pack 5 or later 2 Install Platform Builder 3 00 3 Start Platform Builder by double clicking on the Microsoft Windows CE Platform Builder icon 4 Create a new project a b C i Select File New In the dialog box select the Platforms tab In the platforms dialog box select WCE Platform set a location for the project such as x myproject set the platform name such as myplatform and set the processor to Win32 WCE x86 Click the OK button In the dialog box WCE Platform Step 1 of 2 select CEPC Click the Next button In the dialog box WCE Platform Step 2 of 2 select Maximum OS Maxall Click
297. e action The Save menu option allows a fast save of the configuration information to a file that was opened with the Open menu option Note This option is only available once a file has been opened Save As From the Menu Bar select File then Save As to display the Save As Dialog Box Save in sid13a04 E al c 13a03play exe 13404cfg exe File name Save as type EXE Files y Cancel Save as is very similar to Save except a dialog box is displayed allowing the user to name the file before saving Using this technique a tester can configure a number of files differing only in configuration information and name e g BMP60Hz EXE BMP72Hz EXE BMP75Hz EXE where only the frame rate changes in each of these files Note When Save As is selected then an exact duplicate of the file as opened by the Open option is created containing the new configuration information S1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Page 25 Vancouver Design Center Configure Multiple After determining the desired configuration Configure Multiple allows the information to be saved into one or more executable files built with the HAL library From the Menu Bar select File then Configure Multiple to display the Configure Multiple Dialog Box This dialog box is also displayed when a file s is dragged onto the 1
298. e and the destination areas of the BitBLT may be either rectangular or linear Performing a rectangular to rectangular Move BitBLT creates an exact copy of one portion of video memory at the second location Selecting a rectangular source to linear destination would be used to compactly store an area of displayed video memory into non displayed video memory Later the area could be restored by performing a linear source to rectan gular destination Move BitBLT The transparent color is not copied during this operation whatever pixel color existed in the destination will be there when the BitBLT completes This allows fast display of non rectangular images For example consider a source bitmap having a red circle on a blue background By selecting the blue color as the transparent color and using the Transparent Move BitBLT on the whole rectangle the effect is a BitBLT of the red circle only Note The Transparent Move BitBLT is supported only in a positive direction Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 83 Vancouver Design Center Example 15 Copy a 9 x 101 rectangle at the screen coordinates x 100 y 10 to Screen coordinates X 200 Y 20 using a 320x240 display at a color depth of 16 bpp Transparent color is blue 1 Calculate the source and destination addresses upper left corners of the source and destination rectangles using the formula SourceAddress y X ScreenStride
299. e beginning of register address space e g if Index 04h then the Memory Clock Configuration register will be read and if Index 8000h then the BitBLT Control Register will be read The word value read from the register Use caution in determining the index and interpreting the values returned from halReadReg160 to ensure the correct meaning is given to the values Changing between big and little endian will move relative register offsets resulting in different values Ulnt16 halReadReg32 Ulnt32 Index Description Parameters Return Value Reads and returns the dword value of an S1D13A04 register at the requested offset No S1D13A04 register are changed Index 32 bit offset to the register to read Index is zero based from the beginning of register address space e g if Index 04h then the Memory Clock Configuration register will be read and if Index 8000h then the BitBLT Control Register will be read The dword value read from the register void halWriteReg8 Ulnt32 Index Ulnt8 Value Description Parameters Return Value Writes an 8 bit value to the register at the requested offset Index 32 bit offset to the register to write Index is zero based from the beginning of register address space e g if Index 04h then the Memory Clock Configuration register will be written to and if Index 8000h then the BitBLT Control Register will be written to Value The byte value to write to the register Ch
300. e clearing the EP3 Packet Received bit in Interrupt Status Register 0 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center For a Fast CPU Page 109 A CPU which can clear the Interrupt Status Register 0 bit within 10 msec after the S1D13A04 asserts the IRQ signal requires no extra code to prevent the potential cycling In this case the CPU is fast enough to clear a NAKed packet s Interrupt Status Register 0 bit before another packet can be received For a Slow CPU A CPU which can t meet the timing requirements for a fast CPU above will require some additional firmware to eliminate the potential for this cycle After successfully receiving a packet on Endpoint 3 and emptying received data out of the FIFO the firmware should follow the flow in the following figure Part of Endpoint 3 Interrupt Service Routine after FIFO has been emptied Clear USB Status Register ACK and NAK bits 1 and 2 Set Timout calculate for 50 ms Read USB Status Register Note Each cycle of this loop should take less than 10 ms No Vv Decrement Timeout Clear Endpoint 3 Interrupt Status in Timeout 0 Clear USB Endpoint 3 NAK in USB Status No Yes Interrupt Status gt Register bit 2 Register 0 bit 3 Figure 10 7 Endpoint 3 Program Flow
301. e display buffer occupies the second 256K byte block The registers occupy the range Oh through 3FFFFh while the on chip display memory occupies the range 40000h through 68000h Demultiplexed address lines A 25 19 are ignored Therefore the S1D13A04 is aliased at 256K byte intervals over the 64M byte PC Card slot 1 memory space Note If aliasing is undesirable additional decoding circuitry must be added S1D13A04 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X37A G 002 01 Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Support or www erd epson com Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors 1D13A04 Issue Date 01 10 12 X37A G 002 01 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Toshiba America Electrical Components Inc
302. e high Source cu y lt PWMCLK Source Diva 111 PWMCLK Divide imma MESME PANCUR DUW Cycle oF C lt 4 MCLK Source lt MCLK Divide m Diagnostics The Clocks tab simplifies the selection of input clock frequencies and the sources of internal clocking signals For further information regarding clocking and clock sources refer to the S1D13A04 Hardware Functional Specification document number X37A A 001 xx The CLKI and CLKI2 frequencies represent clock values the system provides to the S1D13A04 It is the responsibility of the system designer to ensure that the correct clock frequencies are supplied to the S1D13A04 Note Changing clock values may modify or invalidate Panel settings Confirm all settings on the Panel tab after modifying any clock settings 1D13A04 X37A B 001 01 13A04CFG Configuration Program Issue Date 01 10 19 Epson Research and Development Vancouver Design Center Page 11 The S1D13A04 may use one or two clock sources Two clock sources allow greater flexi bility in the selection of display type and memory speed CLKI Timing Actual CLKI2 Timing Actual PCLK Source Divide Timing 13A04CFG Configuration Program Issue Date 01 10 19 This setting determines the frequency of CLKI Set this value by selecting a preset frequency from the drop down list or entering the desired frequency MHz in the edit box This field displays the actual val
303. e not available when the S1D13A04 is config ured for the Redcap or Dragonball without DTACK host bus interfaces e A BitBLT operation cannot be terminated once it has been started 9 5 Sample Code Sample code demonstrating how to program the S1D13A04 BitBLT engine is provided in the file A04sample zip This file is available on the internet at www erd epson com Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 94 Epson Research and Development Vancouver Design Center 10 Programming the USB Controller USB Universal Serial Bus is an external bus designed to ease the connection and use of peripheral devices USB incorporates a host client architecture in which the host initiates all data transactions and the client either receives or supplies data to the host USB offers the following features to the end user e Single plug type for all peripheral devices e Support for up to 127 simultaneous devices e Speeds up to 12 Megabits per second e hot plugging peripherals The S1D13A04 USB controller supports revision 1 1 of the USB specification The S1D13A04 USB controller handles many common USB tasks without requiring local processor intervention For example setup and data transfers are handled automatically by the S1D13A04 controller The controller notifies the local CPU through an interrupt when data is ready to be read from the FIFO or when data has been transmitted to the host Th
304. e output enable OB e For DragonBall this pin inputs the output enable OB See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary 1D13A04 X37A A 001 06 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 25 Vancouver Design Center Table 4 2 Host Interface Pin Descriptions A PFBGA TQFP15 RESET gt i Pin Name Type Pin Ping Cell State Description During a data transfer this output pin is driven active to force the system to insert wait states It is driven inactive to indicate the completion of a data transfer WAIT is released to the high impedance state after the data transfer is complete Its active polarity is configurable See Table 4 7 Summary of Power On Reset Options on page 30 e For Generic 1 this pin outputs the wait signal WAIT e For Generic 2 this pin outputs the wait signal WAIT e For SH 3 mode this pin outputs the wait request signal WAIT e For SH 4 mode this pin outputs the device ready signal RDY e For MC68K 1 this pin outputs the data transfer WAIT IO G1 22 LB2A Hi Z acknowledge signal DTACK e For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 e For REDCAP2 this pin is unused Hi Z e For DragonBall this pin outputs the data transfer acknowledge signal DTACK See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summar
305. e up 320 x 240 pixels x bpp 8 9600h bytes If the main window starts at address Oh then the PIP window can start at 9600h PIP display start address desired byte address PIP width x bpp 8 4 PIP width x bpp 8 amp 03h 4 1 9600h 128 x 4 8 4 128 x 4 8 amp 03h 4 1 9615 258Fh Program the PIP Display Start Address register REG 5Oh is set to 0000258Fh Determine the PIP line address offset number of dwords per line image width 32 bpp 128 32 4 16 10h Program the PIP Line Address Offset register REG 54h is set to 0000001 0h Enable the PIP window Program the PIP Window Enable bit REG 10h bit 19 is set to 1 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 51 Vancouver Design Center 8 2 3 SwivelView 180 180 SwivelView E PIP window x end position REG 58h bits 25 16 PIP window x start position REG 58h bits 9 0 4 PIP window x main window PIP window y end position l a N REG 58h bits 25 16 IP window y start position panel s origin REG 5Ch bits 9 0 Figure 8 4 Picture in Picture Plus with SwivelView 180 enabled SwivelView 180 is a mode in which both the main and PIP windows are rotated 180 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main
306. e value to be written to display memory Count The number of times to repeat Value in memory By including a count or loop value this function can efficiently fill display memory Return Value Nothing Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 116 Epson Research and Development Vancouver Design Center void halWriteDisplay16 UInt32 Offset Ulnt16 Value Ulnt32 Count Description Writes a word into display memory at the requested offset Parameters Offset a 32 bit byte offset to the byte to be written to display memory To prevent system slowdowns and possibly memory faults Offset should be a word multiple Value the word value to be written to display memory Count the number of times to repeat the Value in memory By including a count or loop value this function can efficiently fill display memory Return Value Nothing void halWriteDisplay32 Ulnt32 Offset Ulnt32 Value Ulnt32 Count Description Writes a dword into display memory at the requested offset Parameters Offset A 32 bit byte offset to the byte to be written to display memory To prevent system slowdowns and possibly memory faults Offset should be a dword multiple Value The dword value to be written to display memory Count The number of times to repeat the Value in memory By including a count or loop value this function can efficiently fill display memory Return Value Nothing 11 2 3 Register Access
307. ead Register 99 REG 20h Horizontal Total Register 100 REG 24h Horizontal Display Period Register 100 REG 28h Horizontal Display Period Start Position Register 101 REG 2Ch FPLINE Register 101 REG 30h Vertical Total Register 102 REG 34h Vertical Display Period Register 102 REG 38h Vertical Display Period Start Position Register 103 REG 3Ch FPFRAME Register 103 REG 40h Main Window Display Start Address Register 104 REG 44h Main Window Line Address Offset Register 104 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 90 Epson Research and Development Vancouver Design Center Table 8 2 SIDI3A04 Register Set Register Pg Register Pg gt icture i cture Plus Registers REG 50h PIP Window Display Start Address Register 105 REG 54h PIP Window Line Address Offset Register 105 REG 58h PIP Window X Positions Register 106 REG 5Ch PIP Window Y Positions Register 108 REG 60h Special Purpose Register 110 REG 64h GPIO Status and Control Register 112 REG 70h PWM Clock Configuration Register 114 REG 74h PWMOUT Duty Cycle Register 115 REG 80h Scratch Pad A Register 116 REG 84h Scratch Pad B Register 116 REG 88h Scratch Pad C Register 116 AE NS AAA REG 4000h Control Register 117 REG 4002h Interrupt Enable Register O 118 REG 4004h Interrupt Status Register 0 119 REG 4006h Int
308. ease check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the StrongARM SA 1110 Bus 2 1 The StrongARM SA 1110 System Bus The StrongARM SA 1110 microprocessor is a highly integrated communications micro processor that incorporates a 32 bit StrongARM RISC processor core The SA 1110 is ideally suited to interface to the S1D13A04 LCD controller and provides a high perfor mance power efficient solution for embedded systems 2 1 1 StrongARM SA 1110 Overview The SA 1110 system bus can access both variable latency IO and memory devices The SA 1110 uses a 26 bit address bus and a 32 bit data bus which can be used to access 16 bit devices A chip select module with six chip select signals each accessing 64M bytes of memory allows selection of external devices Only chip selects 3 through 5 nCS 5 3 may be used to select variable latency devices which use RDY to extend access cycles These chip selects are individually programmed in the SA 1110 memory configuration registers and can be configured for either a 16 or 32 bit data bus Byte steering is impleme
309. ected by the HAL Parameters ErrMsg When halGetLastError returns ErrMsg will point to the textual error message If ErrMsg is NULL then only the error code will be returned MaxSize Maximum number of bytes including the final O that can be placed in the string pointed to by ErrMsg Return Value The numerical value of the internal error number HALEXTERN void hallnitLUT void Description To standardize the appearance of test and validation programs it was decided the HAL would have the ability to set the lookup table to uniform values The routine cracks the color depth and display type to determine which LUT values to use and proceeds to write the LUT entries Parameters None Return Value Nothing S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 121 Vancouver Design Center 12 Sample Code Example source code demonstrating programming the S1D13A04 using the HAL library is available on the internet at www erd epson com Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 122 13 Sales and Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 htt
310. ects to receive is calculated as follows WORDS WordsOneLine x 18 2x18 36 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation and wait for the BitBLT Engine to start REG 8000h bit O is set to 1 then wait until REG 8004h bit O returns a 1 S1D13A04 X37A G 003 05 Page 74 Epson Research and Development Vancouver Design Center 14 Prior to writing all WORDS to the BitBLT FIFO confirm the BitBLT FIFO is not full REG 8004h bit 4 returns a 0 One WORD expands into 16 pixels which fills all 16 FIFO words in 16 bpp or 8 FIFO words in 8 bpp The following table summarizes how many words can be written to the BitBLT FIFO Table 9 6 Possible BitBLT FIFO Writes BitBLT Status Register REG 8004h 8 bpp Word 16 bpp Word FIFO Not Empty Status FIFO Half Full Status FIFO Full Status Writes Available Writes Available 0 0 0 2 1 1 0 0 1 1 1 i 7 7 0 do not write 9 Aono wate Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started 9 2 3 Color Expansion BitBLT With Transparency This BitBLT operation is virtually identical to the Color Expand BitBLT the difference is in how background bits are handled Bits in the source bitmap which are set to zero result in the destination pixel
311. ed 32 bit data is reversed Note This bit is only used when the S1D13A04 is configured for Big Endian CNF4 1 at RESET If configured for Little Endian CNF4 0 this bit has no effect 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 111 Vancouver Design Center bit 5 Display Data Byte Swap The display pipe fetches 32 bit of data from the display buffer This bit enables byte 0 and byte 1 to be swapped and byte 2 and byte 3 to be swapped before sending them to the LCD display If the Display Data Word Swap bit is also enabled then the byte order of the fetched 32 bit data is reversed Note This bit is only used when the S1D13A04 is configured for Big Endian CNF4 1 at RESET If configured for Little Endian CNF4 0 this bit has no effect byte 0 N 32 bit display data byte 1 gt from display buffer Data To LUT byte 2 gt Serialization Pp gt byte 3 lt lt 4 gt Byte Swap Word Swap Figure 8 1 Display Data Byte Word Swap bit 2 Latch Byte Select When this bit 1 REG 5Ch is latched in reverse order When this bit 0 there is no hardware effect Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 112 Epson Research and Development Vancouver Design Center GPIO Status an
312. ed on the Swivel View orientation For 0 and 180 SwivelView the Y end position is incremented in 1 line increments For 90 and 270 Swivel View the Y end position is incremented by y pixels where y is relative to the current color depth Table 8 13 32 bit Address Increments for Color Depth Color Depth Pixel Increment y 1 bpp 32 2 bpp 16 4 bpp 8 bpp 4 16 bpp 2 Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 10h bit 19 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center bits 9 0 PIP Window Y Start Position Bits 9 0 Page 109 These bits determine the Y start position of the PIP window in relation to the origin of the panel Due to the S1D13A04 SwivelView feature the Y start position may not be a vertical position value only true in 0 and 180 Swivel View For further information on defining the value of the Y Start Position register see Section 14 Picture in Picture Plus PIP on page 156 The register is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the Y start position is incremented in 1 line increments For 90 and 270 SwivelView the Y start
313. edCap Register Address C Hitachi SH 3 LCEVB Register address hex PCI bus Display Buffer A p isplay Buffer Address Display buffer address hex PCI bus NOTE The decoding of the 13404 physical addresses depends on your particular hardware implementation The selection of Platform Types above reflect only one of many possible implementations for each platform Display Data Byte Swap use Support fi Additional features Y Enable USB support Enable display data byte swap Y Enable clock chip support FT Enable BitBLT data byte swap Clock Chip Support M r Diagnostics BitBLT Data Byte Swap The General tab contains settings that define the S1D13A04 operating environment Decode Addresses Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer address fields The values used for each evalu ation platform are examples of possible implementa tions as used by the Epson S3U13A04B00C evaluation board If your hardware implementation differs from the addresses used select the User Defined option and enter the correct values for Register address and Display buffer address 1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Vancouver Design Center Note Page 7 When Epson S5U13A04B00B B00C Evaluation Board is selected the register and display buffe
314. eee wh wha ce ei ee A EA a ea we 15 Helerences iaa A DAA aia la G 16 6 1 DOCUMENTS se trar eanas a ar ee a rt A a e e HG 6 2 Document Sources 2 o 16 T Technical S pport esa A A a A A eee 17 7 1 EPSON LCD USB Companion Chips SID13A04 17 7 2 NEC Electronics Inc 0 1 ee 17 Interfacing to the NEC VR4181A Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 008 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Interfacing to the NEC VR4181A Microprocessor X37A G 008 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 2 000002 ee eee 10 Table 4 1 Summary of Power On Reset Options 2 o e e e 13 List of Figures Figure 4 1 Typical Implementation of VR4181A to 1D13A04 Interface 12 Interfacing to the NEC VR4181A Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 008 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Interfacing to the NEC VR4181A Microprocessor X37A G 008 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13A04 LCD USB Companion Chip and the NEC VR4181A micropro
315. ees a 320x480 portrait image and how the image is being displayed The application image is written to the S1D13A04 in the following sense A B C D The display is refreshed by the S1D13A04 in the following sense C A D B physical memory start address A B o ivelVi O di Q SwivelView E 2 window 5 5 display start address ss al panel origin 25 2 w C D M a 480 5 320 image seen by programmer image refreshed by S1D13A04 image in display buffer Figure 13 3 Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Epson Research and Development Page 155 Vancouver Design Center 13 4 1 Register Programming Enable 270 Swivel View Mode Set Swivel View Mode Select bits REG 10h bits 17 16 to 11 Display Start Address The display refresh circuitry starts at pixel C therefore the Main Window Display Start Address register REG 40h must be programmed with the address of pixel C To calculate the value of the address of pixel C use the following formula assumes 8 bpp color depth REG 40h bits 16 0 image address panel width 1 x offset x bpp 8 4 0 480 pixels 1 x 320 pixels x 8 bpp 8 4 38320 95BOh Line Address Offset The Main Window Line Address Offset register REG 44h is based on the display wi
316. el height to be a multiple of 32 bits per pix el If this is not possible refer to Section 7 3 Limitations Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 32 Epson Research and Development Vancouver Design Center Main Window Line Address Offset Register REG 44h Default 00000000h Read Write 17 16 Main Window Line Address Offset The Main Window Line Address Offset register indicates the number of dwords per line in the main window image For SwivelView 0 and 180 the image width must be at least the panel width For SwivelView 90 and 270 the image width must be at least the panel height In addition the image width must be a multiple of 32 bpp If the image width is not such a multiple a slightly larger width must be chosen see Section 7 3 Limitations Panel width and panel height refer to the physical panel dimensions in pixels Stride is the number of bytes required for one line of the image the offset register represents the stride in DWORD steps Main Window Stride image width x bpp 8 Note Image width can be larger than panel width or panel height for Swivel View 90 or 270 number of dwords per line image width 32 bpp 7 2 Examples Example 1 In SwivelView 0 normal mode program the main window registers for a 320x240 panel at a color depth of 4 bpp 1 Determine the main window display start address The main window is typi
317. el s origin NN de eae PIP window x start position PIP window x end position I REG 58h bits 9 0 REG 58h bits 25 16 al PIP window PIP window y start position REG 5Ch bits 9 0 Ds PIP window y end position a Paks REG 5Ch bits 25 16 main window Figure 14 2 Picture in Picture Plus with SwivelView 90 enabled 14 2 2 SwivelView 180 180 SwivelView o PIP window x end position ee 7 REG 58h bits 25 16 PIP window x start position REG 58h bits 9 0 4 PIP window main window PIP window y end position PA a 7 REG 5Ch bits 25 16 IP window y start position panel s origin REG 5Ch bits 9 0 Figure 14 3 Picture in Picture Plus with SwivelView 180 enabled Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 158 Epson Research and Development Vancouver Design Center 14 2 3 SwivelView 270 270 SwivelView te main window PIP window y end position REG 5Ch bits 25 16 A PIP window y start position ae REG 5Ch bits 9 0 PIP window PIP window x start position Spee REG 58h bits 9 0 A E PIP window x end position REG 58h bits 25 16 panel s origin Figure 14 4 Picture in Picture Plus with Swivel View 270 enabled S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Re
318. elationship between the frequency of MCLK and PCLK that must be maintained Table 7 4 Relationship between MCLK and PCLK SwivelView Orientation Color Depth bpp MCLK to PCLK Relationship 16 fuck 2 fpcLk 8 fuck 2 fpcLk 2 SwivelView 0 and 180 4 mcLk 2 trcLk 4 2 fuck 2 fpcLk 8 1 fuck 2 froLk 16 SwivelView 90 and 270 16 8 4 2 1 mcLk 2 1 25fPcLK 7 1 4 PWMCLK PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel The source clock options for PWMCLK may be selected as in the following table Table 7 5 PWMCLK Clock Selection Source Clock Options PWMCLK Selection CLKI REG 70h bits 2 1 00 CLKI2 REG 70h bits 2 1 01 MCLK REG 70h bits 2 1 10 PCLK REG 70h bits 2 1 11 For further information on controlling PWMCLK see PWM Clock Configuration Register on page 114 7 1 5 USBCLK CLKUSB is an internal clock derived from USBCLK and should be fixed at 48 MHz USBCLK must be active to access the USB Registers Hardware Functional Specification S1D13A04 X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 87 Vancouver Design Center 7 2 Clock Selection The following diagram provides a logical representation of the S1D13A04 internal clocks
319. eneric 1 this pin inputs the write enable signal for the upper data byte WE1 e For Generic 2 this pin inputs the byte enable signal for the high data byte BHE e For SH 3 SH 4 this pin inputs the write enable signal for data byte 1 WE1 WE1 FA 14 T E a 1 this pin inputs the upper data strobe e For MC68K 2 this pin inputs the data strobe DS e For REDCAP2 this pin inputs the byte enable signal for the D 15 8 data byte EBO e For DragonBall this pin inputs the byte enable signal for the D 15 8 data byte UWE See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary Chip select input See Table 4 8 Host Bus Interface Pin CS l E4 9 CI ul elos Mapping on page 31 for summary Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 24 Epson Research and Development Vancouver Design Center Table 4 2 Host Interface Pin Descriptions Pin Name Type PFBGA Pin TQFP15 Pin Cell RESET State Description M R E3 10 LI This input pin is used to select between the display buffer and register address spaces of the S1D13A04 M R is set high to access the display buffer and low to access the registers See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary BS E2 11 LI This input pin has multiple functions e For Generic 1 this pi
320. enter Hardware Functional Specification Issue Date 2003 05 01 Epson Research and Development Page 15 Vancouver Design Center 3 Typical System Implementation Diagrams 3 1 Typical System Diagrams Oscillator Generic 1 BUS IOVDD BS ABO d 16 bit a FPDAT 15 0 gt D 15 0 Single A 27 18 Decoder M Ri FPFRAME FPFRAME LCD Display CSn mice FPLINE gt FPLINE g A 17 1 gt AB 17 1 FPSHIFT FPSHIFT D 15 0 DB 15 0 DRDY g S1D13A04 ae a WEO gt WEO i WE1 gt WEI GPIOO RDO gt RD RD1 gt RD WR WAIT Le WAIT BUSCLK gt CLKI RESET gt RESET Figure 3 1 Typical System Diagram Generic 1 Bus Oscillator P Generic 2 BUS IOVDD y BS x 9 bit RD WR bi FPDAT 8 0 gt D 8 0 TFT A 27 18 Decoder gt WR FPFRAME FPFRAME Display CSn 5 OSH FPLINE FPLINE 5 A 17 0 gt AB 17 0 FPSHIFT gt FPSHIFT Y D 15 0 e gt DB 15 0 DRDY gt DRDY a WEA gt WEO S1 D1 3A04 i BHE gt WEI GPIOO RD gt RD WAIT Le WAIT BUSCLK gt CLKI RESET gt RESET Figure 3 2 Typical System Diagram Generic 2 Bus Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0
321. enter bit 4 Power Save Mode Enable When this bit 1 the software initiated power save mode is enabled When this bit 0 the software initiated power save mode is disabled At reset this bit is set to 1 For a summary of Power Save Mode see Section 15 Power Save Mode on page 159 Note Memory writes are possible during power save mode because the S1D13A04 dynami cally enables the memory controller for display buffer writes Power Considerations The S1D13A04 may experience higher than normal Quiescent Current immediately after applying power To prevent this condition the following start up sequence must be followed 1 Power up Reset the S1D13A04 2 Initialize all registers 3 Disable power save mode set REG 14h bit 4 to 0 Note By default Power Save Mode is enabled equal to 1 after power up Reset If it is desir able necessary to remain in power save mode for any length of time after power up Re set the above described condition can be prevented by performing a R W access to the embedded memory bit 0 Direct HR TFT LCD Interface GPO Control This bit is for HR TFT panels only For all other panel types this bit has no effect When the direct HR TFT LCD interface is selected REG OCh bits 1 0 10 the DRDY pin becomes a general purpose output GPO This GPO can be used to control the HR TFT MOD signal When this bit 0 DRDY GPO is forced low When this bit 1 DRDY GPO is forced high Hardware Functional
322. epths of 1 bit per pixel or Swivel View 90 270 modes bit 24 Pixel Doubling Horizontal Enable This bit controls the pixel doubling feature for the horizontal dimension or width of the panel i e 160 pixel wide data doubled to 320 pixel wide panel When this bit 1 pixel doubling in the horizontal dimension width is enabled When this bit 0 there is no hardware effect Note Pixel Doubling is not designed to support color depths of 1 bit per pixel or Swivel View 90 270 modes 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 95 Vancouver Design Center bit 23 Display Blank When this bit 0 the LCD display pipeline is enabled When this bit 1 the LCD display pipeline is disabled and all LCD data outputs are forced to zero i e the screen is blanked bit 22 Dithering Disable When this bit 0 dithering on the passive LCD panel is enabled allowing a maximum of 64K colors 2 8 or 64 gray shades in 1 2 4 8 bpp mode In 16bpp mode only 64K colors 216 can also be achieved When this bit 1 dithering on the passive LCD panel is disabled allowing a maximum of 4096 colors 212 or 16 gray shades The dithering algorithm provides more shades of each primary color Note For a summary of the results of dithering for each color depth see Table 8 10 LCD Bit per pixel Selection on page 96 bit 20 Software Video Invert When thi
323. equency 33 note 1 MHz Tciko Bus clock period Yciko ME u A 16 1 and CSX and UWE LWE and OE setup to CLKO 4 je rising edge 2 D 15 0 valid to 4th CLK rising edge where CSX 0 and UWE 4 T 0 or LWE 0 write cycle CLKO t3 CSX and OE asserted low to D 15 0 driven read cycle 11 ns t4a 1st CLKO rising edge after CSX and OE asserted to D 15 0 5 T valid for MCLK BCLK read cycle PERS t4b 1st CLKO rising edge after CSX and OE asserted to D 15 0 8 T valid for MCLK BCLK 2 read cycle CERO fae 1st CLKO rising edge after CSX and OE asserted to D 15 0 10 7 valid for MCLK BCLK 3 read cycle see note 2 CEKO tad 1st CLKO rising edge after CSX and OE asserted to D 15 0 13 T valid for MCLK BCLK 4 read cycle see note 2 CLKO A 16 1 and UWE LWE and OE and D 15 0 write hold from t5 Pii 0 ns CSX rising edge t6 CSX rising edge to D 15 0 high impedance 6 ns t7 Cycle Length 9 TeLko 1 The MC68VZ328 has a maximum clock frequency of 33MHz The MC68EZ328 has a maximum clock frequency of 16MHz ON Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 The MC68EZ328 does not support the MCLK BCLK 3 and MCLK BCLK 4 options The cycle length for the Dragonball w o DTACK interface is fixed The Read and Write 2D BitBLT functions are not available when using the Dragonball w o DTACK interface S1D13A04 X37A A 001 06 Page 54 Epson Research and Development Vancouver
324. er Design Center bit 5 EP2 Data Toggle Bit Contains the value of the Data Toggle bit to be sent in response to the next IN token to endpoint 2 from the USB host Note When a write is made to this bit the value cannot be read back before a minimum of 12 USBCLK bit 4 EP1 Data Toggle Bit Contains the value of the Data Toggle bit expected in the next DATA packet to endpoint 1 from the USB host Note When a write is made to this bit the value cannot be read back before a minimum of 12 USBCLK bit 3 Reserved This bit must be set to 0 bit 2 Reserved This bit must be set to 0 bit 0 Reserved This bit must be set to 0 Reserved REG 403Ah Index OBh Default 00h Read Write n a Reserved K 6 5 4 3 2 1 0 bit 0 Reserved This bit must be set to 0 FIFO Control REG 403Ah Index OCh Default 00h Read Write Transmit FIFO na Valid Mode 7 6 5 4 3 2 1 0 bit O Transmit FIFO Valid Mode When set this bit causes a NAK response to a host read request from the transmit FIFO EP4 unless the FIFO Valid bit in register EP4STAT is set When this bit is cleared any data waiting in the transmit FIFO will be sent in response to a host read request and the FIFO Valid bit is ignored Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 130 Epson Research and Development Vancouver Design Center USBFC Input Control Register REG 4040h 15 Default ODh Read W
325. er be disabled in the display driver i e EnablePreferVmem not defined in SOURCES file or new OEM specific code must be added to the display driver to save off screen data to system memory when the system is suspended and restored when resumed If off screen data is used provided that the OEM has provided code to save off screen data when the system suspends additional code must be added to the display driver s surface allocation routine to prevent the display driver from allocating the main memory save region in display memory When WinCE OS attempts to allocate a buffer to save the main display data WinCE OS marks the allocation request as preferring display memory We believe this is incorrect Code must be added to prevent this specific allocation from being allocated in display memory it MUST be allocated from system mem ory Since the main display data is copied to system memory on suspend and then simply copied back on resume this mode is FAST but not as fast as mode 0 Windows CE 3 x Display Driver Issue Date 01 10 19 Epson Research and Development Page 13 Vancouver Design Center c PORepaint 2 e This mode tells WinCE to not save the main display data on suspend and causes WinCE to REPAINT the main display on resume e This mode is used if display memory power is going to be turned off when the system is suspended and there is not enough system memory to save the im age e Any off screen data in di
326. erated when the Receive FIFO Almost Full status bit is set Note The Receive FIFO Almost Full threshold must be set less than 64 as the FIFO count must rise above the threshold to cause an interrupt Interrupt Status Register 1 REG 4008h Default 00h Read Write ETS FIFO Almost Empty Status 1 0 Receive FIFO Almost Full Status bit 1 Transmit FIFO Almost Empty Status This bit is set when the number of bytes in the Transmit FIFO is equal to the Transmit FIFO Almost Empty Threshold and another byte is sent to the USB bus from the FIFO Writing a 1 clears this bit bit O Receive FIFO Almost Full Status This bit is set when the number of bytes in the Receive FIFO is equal to the Receive FIFO Almost Full Threshold and another byte is received from the USB bus into the FIFO Writing a 1 clears this bit S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 121 Vancouver Design Center Endpoint 1 Index Register REG 4010h Default 00h Read Write Endpoint 1 nas bits 2 0 RO 6 5 2 1 0 bits 2 0 Endpoint 1 Index Register Bits 2 0 This register determines which Endpoint 1 Receive Mailbox is accessed when the End point 1 Receive Mailbox Data register is read This register is automatically incremented after the Endpoint 1 Receive Mailbox Data register is read This index register wraps around to zero when it reaches the maximum count 7
327. ered Color Expansion 1000 This BitBLT expands the bits of the source data into full pixels at the destination If a source bit is O the destination pixel will be background color and if the source bit is 1 the destination pixel will be of foreground color The source data for Color Expansion BitBLTs is always system memory Color Expansion with transparency 1001 Like the Color Expansion BitBLT this operations expands each bit of the source data to occupy a full destination pixel The difference is that destination pixels corresponding to source bits of O will be left as is The data source is system memory Move BitBLT with Color Expansion 1010 This BitBLT works the same as the Color Expansion BitBLT however the source of the BitBLT is display memory Move BitBLT with Color Expansion and transparency 1011 This BitBLT works the same as the Color Expansion with Transparency BitBLT however the source of the BitBLT is display memory Solid Fill BitBLT 1100 Use this BitBLT to fill a given area with one solid color Other Reserved combinations S1D13A04 X37A G 003 05 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 63 Vancouver Design Center BitBLT Source Start Address Register REG 800Ch Default 00000000h Read Write BitBLT Source Start Address bits 20 16 20 19 18 17 16 BitBLT Source Start Address bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BitBLT Source Start Address
328. errupt Enable Register 1 120 REG 4008h Interrupt Status Register 1 120 REG 4010h Endpoint 1 Index Register 121 REG 4012h Endpoint 1 Receive Mailbox Data Register 121 REG 4018h Endpoint 2 Index Register 121 REG 401Ah Endpoint 2 Transmit Mailbox Data Register 122 REG 401Ch Endpoint 2 Interrupt Polling Interval Register 122 REG 4020h Endpoint 3 Receive FIFO Data Register 122 REG 4022h Endpoint 3 Receive FIFO Count Register 122 REG 4024h Endpoint 3 Receive FIFO Status Register 123 REG 4026h Endpoint 3 Maximum Packet Size Register 123 REG 4028h Endpoint 4 Transmit FIFO Data Register 123 REG 402Ah Endpoint 4 Transmit FIFO Count Register 124 REG 402Ch Endpoint 4 Transmit FIFO Status Register 124 REG 402Eh Endpoint 4 Maximum Packet Size Register 124 REG 4030h Endpoint 4 Maximum Packet Size Register 124 REG 4032h USB Status Register 125 REG 4034h Frame Counter MSB Register 126 REG 4036h Frame Counter LSB Register 126 REG 4038h Extended Register Index 126 REG 403Ah Extended Register Data 126 REG 403Ah Index 00h Vendor ID MSB 126 REG 403Ah Index 01h Vendor ID LSB 126 REG 403Ah Index 02h Product ID MSB 127 REG 403Ah Index 03h Product ID LSB 127 REG 403Ah Index 04h Release Number MSB 127 REG 403Ah Index 05h Release Number LSB 127 REG 403Ah Index 06h Receive FIFO Almost Full Threshold 127 REG 403Ah Index 07h Transmit FIFO Almost Empty Threshold 127 REG 403Ah Index 08h USB Control 128 REG 403Ah Index 09h Maximum Power Consu
329. ers to map the S1D13A04 to the external LCD controller space The following register values must be set e Register LCDGPMD at address 0B00_032Eh must be set as follows e Bit 7 must be set to 1 to disable the internal LCD controller and enable the external LCD controller interface Disabling the internal LCD controller also maps pin SHCLK to LCDCS and pin LOCLK to MEMCS16 e Bits 1 0 must be set to 11b to reserve 512Kbytes of memory address range 133C_0000h to 1343_FFFFh for the external LCD controller e Register GPMD2REG at address 0B00_0304h must be set as follows e Bits 9 8 GP20MD 1 0 must be set to 11 b to map pin GPIO20 to UBE e Bits 5 4 GP18MDT 1 0 must be set to 01 b to map pin GPIO18 to IORDY Interfacing to the NEC VR4181A Microprocessor Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Supp
330. es the divide ratio for the clock source The divide ratio is applied to the PWMCLK source to derive PWMCLK Note After this divide is applied PWMCLK is further divided by 256 to achieve the final PWMCLK frequency This field shows the actual PWMCLK frequency used by the configuration process Selects the number of cycles that PWMOUT is high out of 256 clock periods 13A04CFG Configuration Program Issue Date 01 10 19 S1D13A04 X37A B 001 01 Page 14 Panel Tab Epson Research and Development Vancouver Design Center FPLINE FPFRAME Polarit Polarit Predefined Panels The S1D13A04 supports many panel types This tab allows configuration of most panel related settings such as dimensions type and timings Panel Type Format 2 1D13A04 X37A B 001 01 Selects between passive STN active TFT and reflective HR TFT panel types Some options may change or become unavailable when the STN TFT HR TFT setting is changed Re confirm all settings on this tab after the Panel Type is changed Selects color STN panel data format 2 This option only applies to 8 bit color STN panels See the S D13A04 Hardware Functional Specification document number X37A A 001 xx for description of format 1 format 2 data formats Most new panels use the format 2 data format 13A04CFG Configuration Program Issue Date 01 10 19 Epson Research and Development Vancouver Design Center Data Width Panel Color
331. esPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp Program the BitBLT Source Start Address Register REG 800Ch is set to 27023h 3 Program the BitBLT Width Register to 100 1 REG 8018h is set to 63h 99 deci mal 4 Program the BitBLT Height Register to 150 1 REG 801Ch is set to 95h 149 deci mal 5 Program the BitBLT Operation Register to select the Pattern Fill with ROP REG 8008h bits 3 0 are set to 6h 6 Program the BitBLT ROP Code Register to select Destination Source REG 8008h bits 19 16 are set to OCh 7 Program the BitBLT Color Format Select bit for 8 bpp operations REG 8000h bit 18 1s set to 0 8 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 2 160 AOh REG 8014h is set to OOAOh 9 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit 0 is set to 1 Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 86 Epson Research and Development Vancouver Design Center 9 2 10 Pattern Fill BitBLT with Transparency 1D13A04 X37A G 003 05 This operation is very similar to the Pattern Fill BitBLT with the difference being t
332. esearch and Development Page 137 Vancouver Design Center bit 0 BitBLT Busy Status This bit is a read only status bit When this bit 1 the BitBLT operation is in progress When this bit 0 the BitBLT operation is complete Note During a BitBLT Read operation the BitBLT engine does not attempt to keep the FIFO full If the FIFO becomes full the BitBLT operation stops temporarily as data is read out of the FIFO The BitBLT will restart only when less than 14 values remain in the FIFO BitBLT Command Register REG 8008h Default 00000000h Read Write ieee Ta a bits 19 16 BitBLT Raster Operation Code Color Expansion Bits 3 0 ROP Code for Write BitBLT and Move BitBLT Bits 2 0 also specify the start bit position for Color Expansion Table 8 19 BitBLT ROP Code Color Expansion Function Selection BitBLT ROP Code Bits Boolean Function for Write Boolean Function for Start Bit Position for Color 3 0 BitBLT and Move BitBLT Pattern Fill Expansion 0000 0 Blackness 0 Blackness bit O 0001 S D or S D lt P Dor P D bit 1 0010 S D P D bit 2 0011 S P bit 3 0100 S D P D bit 4 0101 D D bit 5 0110 S D P D bit 6 0111 S Dor S D lt P D or P D bit 7 1000 S D P D bit O 1001 S D P D bit 1 1010 D D bit 2 1011 S D P D bit 3 1100 S P bit 4 1101 D P D bit 5 1110 D P D bit 6 1111 1 Whiteness 1 Whiteness bit 7
333. eseniptions lt a bas de Ry Be a b ae 22 sel Host Interfaces a at eek Sh cag te ae ee AA e A 22 43 2 CCD Interface eoa aaua wales as tS kno a eh sah at wh nee Se ee cd Se we Me ey dd a ek T 26 413 3 Clock Input ota a is Re ee A aS a Gr eS oo 29 Aid Miscellaneous esa A a ee eee kee go Bee Ree a a 29 4 3 PowerAnd Ground oea cic wea Bea dal de bso ble ae caine ek Ais ae dda es be Ss 29 4 44 Summary of Configuration Options 30 4 5 Host Bus Interface Pin Mapping 2 2 31 4 6 LCD Interface Pin Mapping 32 D C Characteristics ica ze te saat a A a a eee eka 33 A C Characteristics lt da a ax A Ad de ARA A da da 34 6 1 Clock Timmg e e ee eb ee we a a a A CTE Input Clocks ts sect y a a A BS e ot a a AA seed 34 61 27 Internal Clocks wiar r nA a A Ew A ee aE e E Be a 35 6 2 CPU Interface Timing 36 6 2 1 Generic 1 Interface Timing e g Epson EOC33 o o ooo 36 6 2 2 Generic 2 Interface Timing e g ISA o oo o 38 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 4 Epson Research and Development Vancouver Design Center 6 2 3 Hitachi SH 3 Interface Timing e e 40 6 2 4 Hitachi SH 4 Interface Timing 000 0000 42 6 2 5 Motorola MC68K 1 Interface Timing e g MC68000 44 6 2 6 Motorola MC68K 2 Interf
334. esign Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 uses CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SIDI3A04 Hardware Functional Specification document number X37A A 001 xx The following table shows the configuration required for this implementation of a S1D13A04 to NEC VR4102 4111 interface Table 4 1 Summary of Power On Reset Options S1D13A04 Configuration Input Power On Reset State 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 Reserved Must be set to 1 CNF5 WAIT is active high CNF6 CLKI to BCLK divide ratio 2 1 SS configuration for NEC VR4102 VR4111 microprocessor Interfacing to the NEC VR4102 VR4111 Microprocessors S1D13A04 Issue Date 01 10 12 X37A G 007 01 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4102 VR4111 Configuration S1D13A04 X37A G 007 01 The NEC VR4102 4111 provides the internal address decoding necessary to map an external LCD controller Physical address 0A00_0000h to OAFF_FFFFh 16M bytes is reserved for an external LCD controller by the NEC VR4102 4111 The S1D13A04 is a memory mapped device The S1D13A04 uses two 256K byte blocks which are selected using ADD18 from the NEC VR4102 4111 ADD18 is connected to the S1D13A04 M R pin The internal registers occupy the first 256K byte block and t
335. esign Center 6 4 3 Single Monochrome 8 Bit Panel Timing VDP VNDP FPFRAME a FPLINE l f l ML Jl fl f l f DRDY MOD X q FPDAT 7 0 X Invalid LINE1 XLINE2 X LINES X LINE4 X XLINE479XLINE480X Invalid X LINE1 X LINE2 Y FPLINE bi E DRDY MOD DE HDP HNDP la la gt FPSHIFT o FPDAT7 invalid X14 X19 X A E E 1 633 Invalid FPDAT6 Invalid 12 X 1 10 y y 1 634 Invalid X FPDAT5 Invalid ANO ee OO maia X FPDAT4 Invalid X t4 YX 112 Y A Y Y Y 1636X Invalid FPDAT3 Invalid 15 Y 113 ES YY 1 637 Invalid FPDAT2 Invalid X 16 X 114 x Keay 1 638X invalid FPDAT1 invalid 47 X 1 45 Y X TY 1639X Invalid X FPDATO invalid 18 X 1 16 AS XX 1640X Invalid X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 17 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 34h bits 9 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 30h bits 9 0 REG 34h bits 9 0 Lines HDP Horizontal Display Period REG 24h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 20h bits 6 0 1 x 8Ts REG 24h bits 6 0 1 x 8Ts 1D13A04 Hardware Functional Speci
336. esponding interrupt status bit unchanged 1 write corresponding interrupt status bit cleared to zero These bits must always be cleared via a write to this register before first use This will ensure that any changes on input pins during system initialization do not generate erroneous interrupts The interrupt bits are used as follows bit 6 USB Host Disconnected Indicates the USB device is disconnected from a USB host bit 5 Reserved Must be set to 0 bit 4 Device Configured Indicates the USB device has been configured by the USB host bit 3 Reserved Must be set to 0 bit 2 Reserved Must be set to 0 bit 1 Reserved Must be set to 0 bit 0 INT Indicates an interrupt request originating from within the USB registers REG 4000h to REG 403 Ah Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 134 Epson Research and Development Vancouver Design Center Interrupt Control Masked Status Register 0 REG 404Eh Default 00h Read Only 4 USB Host AAA a These read only bits represent the logical AND of the corresponding Interrupt Control Status Clear Register 0 REG 404Ah and the Interrupt Control Enable Register 0 REG 4046h Interrupt Control Masked Status Register 1 REG 4050h Default 00h Read Only 14 12 USB Host Device These read only bits represent the logical AND of the corresponding Interrupt Control Status Clear Register 1 REG 404Ch and the Interrupt Con
337. ess 16 pixels in 3 FPSHIFT rising clocks Ts Pixel clock period PCLK Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 6 25 Single Color 16 Bit Panel Timing VDP Vertical Display Period REG 34h bits 9 0 1 Lines VNDP Vertical Non Display Period VT VDP REG 30h bits 9 0 REG 34h bits 9 0 Lines HDP Horizontal Display Period REG 24h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period HT HDP REG 20h bits 6 0 1 x 8Ts REG 24h bits 6 0 1 x 8Ts S1D13A04 X37A A 001 06 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 71 Vancouver Design Center t2 Sync Timing lt ti dl lt FPFRAME 4 lt 4 t3 gt FPLINE t5 Lens DRDY MOD Data Timing FPLINE t6 4 t8 gt 4 t9 gt t7 t14 tii t10 lt 4 gt 4 gt gt FPSHIFT t12 t13 FPDAT 15 0 1 X Figure 6 26 Single Color 16 Bit Panel A C Timing Table 6 25 Single Color 16 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling e
338. etVersionInfo const char szProgName const char szDesc const char szVersion char szRetStr int nLength Description This routine creates a standardized startup banner by merging program and HAL specific information The newly formulated string is returned to the calling program for display The final formatted string will resemble 13A04PROGRAM Internal test and diagnostic program Build 1234 HAL 1234 Copyright c 2000 2001 Epson Research and Development Inc All Rights Reserved Parameters szProgName Pointer to an ASCIIZ string containing the name of the program e g PROGRAM szDesc Pointer to an ASCIIZ string containing a description of what this program is intended to do e g Internal test and diagnostic program szVersion Pointer to an ASCIIZ string containing the build info for this program This should be the revision info string as updated by VSS e g Revision 30 szRetStr Pointer to a buffer into which the product and version information will be formatted into nLength Total number of bytes in the string pointed to by szRetStr This function will write nLength or fewer bytes to the buffer pointed to by szRetStr Return Value Nothing Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 120 Epson Research and Development Vancouver Design Center int halGetLastError char ErrMsg int MaxSize Description This routine retrieves the last error det
339. even address 1 0 0 1 valid 8 bit read at odd address Note Generic 2 interface only supports Little Endian mode Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 40 Epson Research and Development Vancouver Design Center 6 2 3 Hitachi SH 3 Interface Timing Tckio CKIO t1 t9 lt gt A 16 1 M R RD WR MO C p t18 R BS X sy t4 t11 PES AS CSn A t12 le t5 t13 y E WEn RD MO t6 t14 WAIT t7 t15 D 15 0 write valid t8 t17 gt D 15 0 read valid Figure 6 4 Hitachi SH 3 Interface Timing Note For this interface the following formula must apply MCLK BCLK lt 33MHz If a BCLK greater than 33MHz is desired MCLK must be divided such that MCLK is not greater than 33MHz see REG 04h bits 5 4 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 41 Vancouver Design Center Table 6 10 Hitachi SH 3 Interface Timing Symbol Parameter Min Max Unit fcKlo Bus clock frequency 66 MHz Tckio Bus clock period 1Ackio ns t1 A 16 1 RD WR setup to CKIO 1 ns t2 BS setup 1 ns t3 BS hold 5 ns t4 CSn setup
340. f Index 8000h then the BitBLT Control Register will be written to Value The dword value to write to the register Return Value Nothing 11 2 4 Clock Support To maximize flexibility S1D13A04 evaluation boards include a programmable clock The following HAL routines provide support for the programmable clock Boolean halSetClock Ulnt32 ClkiFreq Ulnt32 Clki2Freq Description This routine program the ICD2061A programmable clock generator to the specified fre quency Parameters ClkiFreq The desired frequency in Hz for CLKI Clki2Freq The desired frequency in Hz for CLKI2 dwFrequencyThe desired frequency in Hz Return Value TRUE non zero if the function was successful in setting the clock FALSE zero if there was an error detected while trying to set the clock If additional error information is required call halGetLastError S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 119 Vancouver Design Center UInt32 halGetClock CLOCKSELECT Clock Description Returns the frequency of the clock input identified by Clock Parameters Clock Indicates which clock to read This value can be CLKI or CLKI2 Return Value The frequency in Hz of the requested clock 11 2 5 Miscellaneous The miscellaneous function are an assortment of routines determined to be beneficial to a number of programs and hence warranted being included in the HAL void halG
341. f gate driver 8 VSS Power supply of gate driver logic low PEN a power 9 VEE Power supply of gate driver low level o olla FOWE 10 VEE Power supply of gate driver low level P a Power 11 VCOM z Common electrode driving signal See Section oh einer Powe Supplies on page 14 12 VCOM Common electrode driving signal See Section A Externa Power Supplies on page 14 13 SPL GPIO3 Sampling start signal for left right scanning 14 RO FPDAT11 Red data signal LSB 15 R1 FPDAT10 Red data signal 16 R2 FPDAT9 _ Red data signal 17 R3 FPDAT2 Red data signal 18 R4 FPDAT1 Red data signal 19 R5 FPDATO Red data signal MSB 20 GO FPDAT14 Green data signal LSB 21 G1 FPDAT13 Green data signal 22 G2 FPDAT12 Green data signal 23 G3 FPDAT5 Green data signal 24 G4 FPDAT4 Green data signal 25 G5 FPDAT3 Green data signal MSB S1D13A04 Connecting to the Sharp HR TFT Panels X37A G 011 01 Issue Date 01 10 12 Epson Research and Development Vancouver Design Center Page 17 Table 3 1 SIDI3A04 to LQ031BI1DDxx Pin Mapping Continued LCDPin LCD Pin S1D13A04 Description Remarks No Name Pin Name P 26 BO FPDAT17 Blue data signal LSB 27 B1 FPDAT16 Blue data signal 28 B2 FPDAT15 Blue data signal 29 B3 FPDAT8 Blue data signal 30 B4 FPDAT7 _ Blue data signal 31 B5 FPDAT6 Blue data signal MSB e See Section 3 1 External
342. fer to the source code for the S1D13A04 utilities available on the internet at www erd epson com For further information on programming the clock generator refer to the Cypress ICD2061A specification Note When CLKI and CLKI2 are programmed to multiples of each other e g CLKI 20MHz CLKI2 40MHz the clock output signals from the Cypress clock generator may jitter Refer to the Cypress ICD2061A specification for details To avoid this problem set CLKI and CLKI2 to different frequencies and use the S1D13A04 internal clock divides to obtain the lower frequencies S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Epson Research and Development Page 23 Vancouver Design Center 8 References 8 1 Documents e Epson Research and Development Inc D13A04 Hardware Functional Specification document number X37A A 001 xx Epson Research and Development Inc S1D13A04 Programming Notes and Examples document number X37A G 003 xx e Cypress Semiconductor Corporation ICD2061A Data Sheet 8 2 Document Sources e Epson Research and Development http www erd epson com e Cypress Semiconductor Corporation Website http www cypress com S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 24 9 Parts List Table 9 1 Parts List Epson Research and Development Vancouver Design Center
343. ffected by the initial ization Any or all of the initialization steps may be bypassed according to values contained in the Flags parameter This allows for conditional run time changes to the initialization Flags contains initialization specific information The default action of the HAL is to per form all initialization steps Flags contain specific instructions for bypassing certain ini tialization steps The values for Flags are fDONT_RESET The first step of the initialization process is to perform a software Setting this flag bypasses the software reset fDONT_SET_CLOCKS Setting this flag causes initialization to skip programming the ICD2061A clock generator Normally the clock on the S5U13A04B00C is programmed to configured values during initialization fDONT_INIT_REGS Bypass register initialization Normally the init process sets the register values to a known state Setting this flag bypasses this step fDONT_INIT_LUT Bypass look up table initialization fDONT_CLEAR_MEM The final step of the initialization process is to clear video display memory Setting this flag will bypass this step TRUE non zero if the initialization was successful FALSE zero if the HAL was unable to initialize the SID13A04 If additional error information is required call halGetLastError Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 115 Vancouver Design Center 11 2 2 Memory Access T
344. ffer is byte swapped This box should be checked when the display color depth is 16 bpp on a Big Endian platform When this box is checked word data sent to read from the 2D BitBLT memory is byte swapped This box should be checked when using the 2D BitBLT functions on a Big Endian platform S1D13A04 X37A B 001 01 Page 8 Epson Research and Development Vancouver Design Center Preferences Tab 1D13A04 X37A B 001 01 51D13404 Configuration Utility The Preference tab contains settings pertaining to the initial display state During runtime these settings may be changed S1D Controller 13A04CFG is designed to support the S1ID13A03 and the 1D13A04 When a controller is selected 13A04CFG determines the maximum panel dimensions based on the video memory display buffer size Some S1D13A04 configurations may not be possible for the S1D13A03 due to memory limitations Pixel Doubling These settings allow the Pixel Doubling feature to be configured independently in the horizontal and vertical dimensions Pixel doubling causes each pixel of display data to be extended to two pixels This feature can be useful for using existing software on larger panels Horizontal When this box is checked pixel doubling in the horizontal direction is enabled Note that the S1D13A04 does not support horizontal pixel doubling at a color depth of 1 bpp 13A04CFG Configuration Program Issue Date 01 10 19 Epson Research and Development Vanc
345. fication X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 63 Vancouver Design Center t1 t2 Sync Timing Bic bie FPFRAME t4 t3 gt FPLINE ff Zag ili DRDY MOD Data Timing FPLINE I t6 E t7 FPSHIFT FPDAT 7 0 Wa Figure 6 18 Single Monochrome 8 Bit Panel A C Timing Table 6 21 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units ti FPFRAME setup to FPLINE falling edge note 2 Ts note 1 t2 FPFRAME hold from FPLINE falling edge note 3 Ts t3 FPLINE period note 4 Ts t4 FPLINE pulse width note 5 Ts t5 MOD transition to FPLINE rising edge note 6 Ts t6 FPSHIFT falling edge to FPLINE rising edge note 7 Ts t7 FPSHIFT falling edge to FPLINE falling edge 16 t4 Ts t8 FPLINE falling edge to FPSHIFT falling edge t14 4 Ts t9 FPSHIFT period 8 Ts t10 FPSHIFT pulse width low 4 Ts t11 FPSHIFT pulse width high 4 Ts t12 FPDAT 7 0 setup to FPSHIFT falling edge 4 Ts t13 FPDAT 7 0 hold to FPSHIFT falling edge 4 Ts t14 FPLINE falling edge to FPSHIFT rising edge note 8 Ts 1 Ts pixel clock period 2 tl min HPS t4min 3 t2min 13min HPS t4min 4 tBmin HT 5 t4min HPW 6 min HPS 1 7 min HPS HDP HDPS 4 if negative add t3 min 8 tl4min HDPS HPS t4 min if negative add t3 min Hardware Functional Specification S1D13A04 Issue
346. following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines loadcepc B 38400 C 1 c nk bin d Copy NK BIN to ca e Boot the system S1D13A04 Windows CE 3 x Display Driver X37A E 006 01 Issue Date 01 10 19 Epson Research and Development Page 9 Vancouver Design Center Configuration There are several issues to consider when configuring the display driver The issues cover debugging support register initialization values and memory allocation Each of these issues is discussed in the following sections Compile Switches There are several switches specific to the S1D13A04 display driver which affect the display driver The switches are added or removed from the compile switches in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default to 2 11 The S1D13A04 display driver may test against this option to support different WinCE version specific features EnablePreferVmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable this option if your off screen video memory is limited ENABLE_CLOCK_CHIP This option is used to enable support for the ICD2061A clock generator This clock chip
347. for any damage done to the display device as a result of configuration errors Yellow diagnostic warnings are designed to draw attention to important errors in the configuration and should be corrected before saving the configuration 13A04CFG can be configured by making a copy of the file 13 A04cfg exe and config uring the copy It is not possible to configure the original while it is running The newly saved information becomes the default configuration for that copy of 13A04cfg exe 13A04CFG Configuration Program Issue Date 01 10 19 EPSON S1D13A04 LCD USB Companion Chip 13A04PLAY Diagnostic Utility Document Number X37A B 002 01 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE
348. four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 22 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers S1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA
349. from your sales support contact see Section 7 Sales and Technical Support or www erd epson com Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13A04 Issue Date 01 10 12 X37A G 007 01 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents NEC Electronics Inc VR4102 VR4111 64 32 bit Microprocessor Preliminary User s Manual Epson Research and Development Inc 1D13A04 Hardware Functional Specification document number X37A A 001 xx Epson Research and Development Inc S5UI3A04B00C Rev 1 0 Evaluation Board User Manual document number X37A G 004 xx Epson Research and Development Inc S D13A04 Programming Notes and Examples document number X37A G 003 xx 6 2 Document Sources NEC Electronics Inc Website www necel com e Epson Research and Development Website www erd epson com 1D13A04 Interfacing to the NEC VR4102 VR4111 Microprocessors X37A G 007 01 Issue Date 01 10 12 Epson Research and Development Page 17 Vancouver Design Center 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk 7
350. further action is taken 13A04PLAY Diagnostic Utility Issue Date 01 10 05 Epson Research and Development Page 7 Vancouver Design Center L index red green blue Reads writes the red green and blue Look Up Table LUT components If the red green and blue components are not specified the LUT for the given index is read and the RGB values are displayed Where index Index into the LUT hex red Red component of the LUT hex green Green component of the LUT hex blue Blue component of the LUT hex Note Only bits 7 2 of each color are used in the LUT The least significant two bits of the col ors are discarded For example the command L 0 1 2 3 will set each RGB component of LUT index 0 to 0 as the values 1 2 an 3 use only the least significant bits LA Reads and displays all LUT values M bpp Sets the color depth bpp If no color depth is provided information about the current settings are displayed Where bpp Color depth to be set 1 2 4 8 16 bpp Note This command reads and interprets the S1D13A04 control registers To function cor rectly the registers must have been initialized using the T command Q Quits the program R SI16132 addr1 addr2 addr3 Reads the display buffer at the address locations given Where 8116132 The unit size 8 bit bytes 16 bit words 32 bit dwords If a unit size is not specified this command uses the unit size from the last Read command perfor
351. g edge write cycle 4 ns t11 UDS LDS rising edge to D 15 0 high impedance read cycle 2 ns 112 D 15 0 valid setup time to 2nd CLK falling edge after DTACK goes 10 pe low read cycle t13 Cycle Length 7 ToLk Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 46 Epson Research and Development Vancouver Design Center 6 2 6 Motorola MC68K 2 Interface Timing e g MC68030 Telk LE gt CLK ti altl p tS A 16 1 M R R W SIZ 1 0 BN f p t16 i t1 Bd cs X T t1 t7 gt 18 AS t1 E 9 DS ML t10 d t2 t11 DSACK1 AA A A tle t13 D 31 16 write valid 3 d 45 0191 16 ca es vais Figure 6 7 Motorola MC68K 2 Interface Timing 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 47 Vancouver Design Center Table 6 13 Motorola MC68K 2 Interface Timing Symbol Parameter Min Max Unit tex Bus clock frequency 50 MHz Tok Bus clock period T foLk ns u Alt 6 0 M R R W SIZ 1 0 and CS and ASH and DS setup to ng first CLK rising edge t2 CS and AS asserted low to DSACK1 driven 3 10 ns t3 A 1 0 R W SIZ 1 0 DS asserted to D 15 0 driven 8 ns t4 A 16 1 M R R W SIZ 1 0 ho
352. g messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the USB driver as they will significantly impact the performance of the USB driver S1D13A04 Windows CE 3 x USB Driver X37A E 007 01 Issue Date 01 10 19 Epson Research and Development Page 9 Vancouver Design Center Address and IRQ Modifications e The USB driver is CPU independent and it can be used on other platforms that support USB under Windows CE Platform Builder 3 0 If this driver is to support non cepc plat forms the file project reg requires editing to set the correct values of PhysicalAd dress and IRQ e The variables DEFAULT_PHYSICAL_ADDRESS and DEFAULT_IRQ in the file 13a0xhw h must be changed to reflect the values required by each implementation e If the entries of PhysicalAddress and IRQ are removed from the project reg file the USB driver uses the values of DEFAULT_PHYSICAL_ADDRESS and DEFAULT_IRQ contained in the file 13a0xhw h Windows CE 3 x USB Driver S1D13A04 Issue Date 01 10 19 X37A E 007 01 Page 10 Epson Research and Development Vancouver Design Center Comments e S5U13A04B00C Evaluation Board must be configured to enable USB support This includes configuration changes to the dip switch and confirming that the proper USBCIk is available on U13 See the SSUI3A04BO0C Rev 1 0 Evaluation Board User Manual document number X37A G 004 xx e This U
353. g the Receive FIFO to become Valid again The Host PC may immediately attempt to re transmit the NAKed packet The firmware should be written to prevent a cycle in which the FIFO is Valid each time that the Host PC sends an OUT packet The following rules govern the 1D13A04 s behavior regarding packets received on Endpoint 3 Rule A At the end of a received OUT token to EP3 and before the data is received the S1D13A04 decides to NAK the packet if the EP3 Interrupt Status bit is set and will therefore throw away data received Rule B At the end of a received packet including one which is NAKed the 1D13A04 sets the EP3 Interrupt Status bit Rule C Local firmware should clear the EP3 Interrupt Status bit after reading all bytes out of the EP3 Receive FIFO Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 108 Epson Research and Development Vancouver Design Center The following figure shows how a repeating cycle of NAKed OUT packets may occur Host Device IRQ OUT Data0 pkt OUT Data pkt OUT Datat pkt ACK NAK NAK A A A 2 S1D13A04 X37A G 003 05 Figure 10 6 Firmware Looping Continuously on Received OUT packets At Point 1 the EP3 Interrupt activates because a packet has been received In response the firmware reads the bytes out of
354. ge 11 Ts 1 Ts pixel clock period 2 ttyp REG 2Ch bits 9 0 1 3 t2typ REG 20h bits 6 0 1 x 8 4 t8typ REG 2Ch bits 22 16 1 5 Utyp REG 28h bits 9 0 5 REG 2Ch bits 9 0 1 6 t8typ REG 24h bits 6 0 1 x 8 4 tl t3 t2 FPDATII7 0 Y Y Y Y Y Levon N E A AXA A A LI 14 PONES FPFRAME e SPS Figure 6 33 320x240 Sharp Direct HR TFT Panel Vertical Timing Table 6 30 320x240 Sharp Direct HR TFT Panel Vertical Timing Symbol Parameter Min Typ Max Units tl Vertical total period 245 330 Lines t2 Vertical display start position 4 Lines t3 Vertical display period 240 Lines t4 Vertical sync pulse width 2 Lines Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 82 Epson Research and Development Vancouver Design Center 6 5 USB Timing Data Signal Rise and Fall Time Rise Time Fall Time 4 f ane oy e 90 20 Differential Data Lines Full Speed 4 to 20ns at C 50pF Figure 6 34 Data Signal Rise and Fall Time TpeRion A Crossover___ 1 A A Points AAA Differential Ya Ta Y A ae Data Lines l l X Consecutive Transitions gt N T penon tTn Paired i Transitions i N T peront Ture Figu
355. ge 75 Vancouver Design Center Table 6 26 TFT A C Timing Symbol Parameter Min Typ Max Units tl FPFRAME cycle time VT Lines t2 FPFRAME pulse width low VPW Lines t3 FPFRAME falling edge to FPLINE falling edge phase difference HPS Ts note 1 t4 FPLINE cycle time HT Ts t5 FPLINE pulse width low HPW Ts t6 FPLINE Falling edge to DRDY active note 2 250 Ts t7 DRDY pulse width HDP Ts t8 DRDY falling edge to FPLINE falling edge note 3 Ts t9 FPSHIFT period 1 Ts t10 FPSHIFT pulse width high 0 5 Ts t11 FPSHIFT pulse width low 0 5 Ts t12 FPLINE setup to FPSHIFT falling edge 0 5 Ts t13 DRDY to FPSHIFT falling edge setup time 0 5 Ts t14 DRDY hold from FPSHIFT falling edge 0 5 Ts t15 Data setup to FPSHIFT falling edge 0 5 Ts t16 Data hold from FPSHIFT falling edge 0 5 Ts 1 Ts pixel clock period 2 t6min HDPS HPS if negative add HT 3 t8min HPS HDP HDPS if negative add HT Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 76 Epson Research and Development Vancouver Design Center 6 4 10 160x160 Sharp Direct HR TFT Panel Timing e g LQ031B1DDxx FPFRAME SPS t1 FPLINE AN Eo ie on LP A Di t2 gt 13 FPLINE CE t4 a AAA ERA CLK t5 16 lt FPDAT 17 0 Dri p2X oX X X Xbis0 lt gt gt GPIO3 SPL GPIO1 CLS t12 GPIOO PS t13 GPIO2 REV
356. gister REG 8010h is set to 2F99h 2 Program the BitBLT Width Register to 100 1 REG 8018h is set to 63h 99 deci mal 3 Program the BitBLT Height Register to 20 1 REG 801Ch is set to 13h 19 deci mal 4 Program the Source Phase in the BitBLT Source Start Address Register In this exam ple the data is WORD aligned so the source phase is 0 REG 800Ch is set to 00h 5 Program the BitBLT Operation Register to select the Write BitBLT with ROP REG 8008h bits 3 0 are set to Oh 6 Program the BitBLT ROP Code Register to select Destination Source REG 8008h bits 19 16 are set to OCh 7 Program the BitBLT Color Format Select bit for 8 bpp operations REG 8000h bit 18 is set to 0 8 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BLTMemoryOffset DisplayWidthInPixels BytesPerPixel 320 2 A0h REG 8014h is set to AOh Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 69 Vancouver Design Center 9 Calculate the number of WORDS the BitBLT engine expects to receive WORDS BLTWidth 1 SourcePhase 2 x BLTHeight 100 1 2 x 20 1000 3E8h 10 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation and wait for the BitBLT engine to start REG 8000h bit 0 is set to 1 then wait until REG 8004h bi
357. h is most suitable for connection to the Toshiba 3 1 Host Bus Interface Pin Mapping 1D13A04 X37A G 002 01 TMPR3905 12 microprocessor Vancouver Design Center The Generic 2 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After releasing reset the bus interface signals assume their selected configuration For details on the S1D13A04 configuration see Section 4 2 S1D13A04 Hardware Configuration on page 14 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping 1D13A04 Pin Names Toshiba TMPR3905 12 AB 17 0 External Decode DB 15 8 D 23 16 DB 7 0 D 31 24 WE1 External Decode CS External Decode M R External Decode CLKI DCLKOUT BS Connect to lOypp from the S1D13A04 RD WR Connect to lOypp from the S1D13A04 RD CARDIORD WEO CARDIOWR WAIT CARD1WAIT RESET system RESET Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For example DCLKOUT from the Toshiba TMPR3905 12 The address inputs AB 12 0
358. hase more efficient code would simply write the low byte of the SourceAddress into REG 800Ch directly not needing to test for an odd even address Note that in 16 bpp color depths the Source address is guaranteed to be even 6 Program the BitBLT Operation Register to select the Color Expand BitBLT REG 8008h bits 3 0 are set to 8h Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 73 Vancouver Design Center 7 10 11 12 13 Programming Notes and Examples Issue Date 2002 08 21 Program the Color Expansion Register The formula for this example is as follows Color Expansion 7 Sx MOD 8 7 125 MOD 8 7 5 2 REG 8008h is set to 2h Program the Background Color Register to the background color REG 8020h is set to 7Ch 124 decimal Program the Foreground Color Register to the foreground color REG 8024h is set to 86h 134 decimal Program the BitBLT Color Format Register for 8 bpp operation REG 8000h bit 18 is set to 0 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 2 A0h REG 8014h is set to AOh Calculate the number of WORDS the BitBLT engine expects to receive First the number of WORDS in one BitBLT line must be calculated as follows WordsOneLine 125 MOD 16 12 15 16 13 12 15 16 40 16 2 Therefore the total WORDS the BitBLT engine exp
359. hat one color can be specified to be transparent Whenever the Transparent color is encountered in the pattern data the destination is left as is This operation is useful to create hatched or striped patterns where the original image shows through the hatching The requirements for this BitBLT are the same as for the Pattern Fill BitBLT the only change in programming is that the BitBLT Operation field of REG 8008h must be set to 07h and the BitBLT Background color register REG 8020h must be set to the desired color Example 17 Fill a 100 x 150 rectangle at the screen coordinates x 10 y 20 with the pattern in off screen memory at offset 27000h using a 320x240 dis play at a color depth of 8 bpp The first pixel upper left corner of the rectangle is the pattern pixel at x 3 y 4 Transparent color is blue as sumes LUT index 1 1 Calculate the destination address upper left corner of destination rectangle using the formula DestinationAddress y X ScreenStride x x BytesPerPixel 20 x 320 10 x 1 6410 190Ah where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixels 320 for 8 bpp Program the BitBLT Destination Start Address Register REG 8010h is set to 190Ah 2 Calculate the source address This is the address of the pixel in the pattern that is the origin of the destination fill area The pattern begins at offset 1M but the first patter
360. he 160K byte display buffer occupies the second 256K byte block The starting address of the S1D13A04 internal registers is located at 0A00_0000h and the starting address of the display buffer is located at 0A04_0000h These blocks are aliased over the entire 16M byte address space Note If aliasing is not desirable the upper addresses must be fully decoded The NEC VR4102 VR4111 has a 16 bit internal register named BCUCNTREG2 located at 0B00_0002h It must be set to the value of 0001h which indicates that LCD controller accesses use a non inverting data bus The 16 bit internal register named BCUCNTREGI located at OB00_0000h must have bit D 13 USA LCD bit set to 0 This reserves 16M bytes from 0A00_0000h to OAFF_FFFFh for use by the LCD controller and not as ISA bus memory space Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13A04 test utilities and display drivers are available
361. he A B inputs allow the two sets of reference voltages to be alternated compensating for asymmetrical gamma character istics during row inversion This input is controlled by the S1D13A04 output signal REV which toggles every time a horizontal sync signal is sent to the panel The REV signal is also used to generate the highest gray scale voltage VO or black by buffering REV and shifting its maximum level to the maximum gray scale voltage CON_POWER CON_POWER is supplied by a National Semiconductor micropower Voltage Regulator LP2951 Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation shows the schematic for gray scale voltage generation 4 oon_Power AN ALSK 1 1 i FHE AIA A2B 7 RRAK MOVIE A Lg BIT AGA AA AZ 1 E A BB BES zB EB ee ga SS BR Rig Y R LSG lt 4 E VA ALSK 1 1 RIN ALSK Ml y 1 b RN ALSK 10 El zz Sj 88 29 222 g 382 1 ne A1B a pores gt gt con_Power LAR RI AL ad H BARANA BIRA FO ALE 5 LIRNA 7 LR AL 4 E 520 RABO at p lt AT 220uF 25v Rev X lt h 178K PR gt gt vo N S N D1 N G I P S P G 74A0T04 Fanctos F2002E CON Power gt 1D13A04 X37A G 011 01 Figure 2 1 Sharp LO03902D5801 Gray Scale Voltage VO V9 Generation
362. he PIP Window Y Positions register sets the horizon tal coordinates of the PIP window s top right and bottom left corners The required values are calculated as follows X Start Position yl 80 50h Y Start Position panel height x2 1 32 bpp 240 60 120 1 1 32 4 7 5 07h truncated fractional part X End Position y2 80 160 1 239 EFh Y End Position panel height x1 1 32 bpp 240 60 1 32 4 22 375 16h truncated fractional part Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 50 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center Program the PIP Window X Positions register with the X Start Position in bits 9 0 and the X End Position in bits 25 16 REG 58h is set to OOEFOOSOh Program the PIP Window Y Positions register with the Y Start Position in bits 9 0 and the Y End Position in bits 25 16 REG 5Ch is set to 00160007h Due to truncation the dimensions of the PIP window may have changed Recalculate the PIP window width and height below PIP Width REG SCh bits 25 16 REG SCh bits 9 0 1 x 32 bpp 16h 07h 1 x 32 4 128 pixels note that this is different from the desired width PIP Height REG 58h bits 25 16 REG 58h bits 9 0 1 EFh 50h 1 160 lines Determine the PIP display start address The main window image must tak
363. he S1D13A04 HAL includes six memory access functions The primary purpose of the memory access functions is to demonstrate how to access display memory using the C programming language Most programs that need to access memory will bypass the HAL and access memory directly Uint8 halReadDisplay8 Ulnt32 Offset Description Reads and returns the value of one byte of display memory Parameters Offset A 32 bit offset to the byte to be read from display memory Return Value The value of the byte at the requested offset Ulnt16 halReadDisplay16 UInt32 Offset Description Reads and returns the value of one word of display memory Parameters Offset A 32 bit byte offset to the word to be read from display memory To prevent system slowdowns and possibly memory faults Offset should be a word multiple Return Value The value of the word at the requested offset Uint32 halReadDisplay32 UInt32 Offset Description Reads and returns the value of one dword of display memory Parameters Offset A 32 bit byte offset to the dword to be read from display memory To prevent system slowdowns and possibly memory faults Offset should be a dword multiple Return Value The value of the dword at the requested offset void halWriteDisplay8 Ulnt32 Offset Ulnt8 Value Ulnt32 Count Description Writes a byte into display memory at the requested address Parameters Offset A 32 bit byte offset to the byte to be written to display memory Value The byt
364. he WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the PC Card bus using the Generic 2 Host Bus Interface These pins must be tied high connected to IO Vpp The RESET active low input of the S1D13A04 may be connected to the PC Card RESET active high using an inverter 1D13A04 X37A G 005 01 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to S1D13A04 Interface 4 1 Hardware Connections The S1D13A04 is interfaced to the PC Card bus with a minimal amount of glue logic In this implementation the address inputs AB 17 0 and data bus DB 15 0 connect directly to the CPU address A 17 0 and data bus D 15 0 The PC Card interface does not provide a bus clock so one must be supplied for the S1D13A04 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI2 BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to IO Vpp The following diagram shows a typical implementation of the PC Card to 1D13A04 interface PC Card Bus S1D13A04 OE gt RD WE gt WEO A18 gt M R CE1 CE2 e gt WE1 RESET D gt o gt RESETH 10
365. he destination address is updated to point to the beginning of the next row of a rectangular area The offset to the start of the next row is contained in the BitBLT Memory Address Offset register REG 8014h S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 59 Vancouver Design Center Source Linear Select BitBLT Enable When the end of a row is reached and destination linear is selected the destination address is updated to the next available memory offset The result is data which is jammed together with one row immediately following the next in display memory This is useful when it is desired to compactly save a rectangular area into off screen memory When this bit 0 the BitBLT destination is stored as a rectangular region of memory When this bit 1 the BitBLT destination is stored as a contiguous linear block of mem ory The Source Linear Select bit determines how the source address pointer is updated when the BitBLT reaches the end of a row When the end of a row is reached and rectangular is selected the source address is updated to point to the beginning of the next row of a rectangular area The offset to the start of the next row is contained in the BitBLT Memory Address Offset register REG 8014h When the end of a row is reached and source linear is selected the source address is updated to the next available memory offset The result is data which
366. he read enable RD or write enable WR signals are driven low for the appropriate cycle LCDRDY is driven low by the S1D13A04 to insert wait states into the cycle The system high byte enable is driven low for 16 bit transfers and high for 8 bit transfers Figure 2 1 NEC VR4102 VR4111 Read Write Cycles shows the read and write cycles to the LCD Controller Interface TCLK A RU 7 NUS ZF wy ADD 25 0 x VALID x SHB x x LCDCS WR RD D 15 0 write x VALID D 15 0 Hi Z read gt VALID Hi Z LCDRDY Figure 2 1 NEC VR4102 VR4111 Read Write Cycles Interfacing to the NEC VR4102 VR4111 Microprocessors S1D13A04 Issue Date 01 10 12 X37A G 007 01 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the NEC VR4102 4111 microprocessor Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte 3 1 Host Bus Interface Pin Mapping 1D13A04 X37A G 007 01 The Generic 2 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13A04 configurat
367. his address represents the upper left corner of the BitBLT rectangle If the operation is a Move BitBLT in a Negative Direction these bits define the address of the lower right corner of the rectangle Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 64 Epson Research and Development Vancouver Design Center BitBLT Memory Address Offset Register REG 8014h Default 00000000h Read Write es er ae er bits 10 gt BitBLT Memory Address Offset This register specifies the 11 bit address offset from the starting word of line n to the start ing word of line n The offset value is only used for address calculation when the BitBLT is configured as rectangular BitBLT Width Register REG 8018h Default 00000000h Read Write BitBLT Width This register specifies the width of a BitBLT in pixels 1 BitBLT width in pixels REG 8018h 1 BitBLT Height Register REG 801Ch Default 00000000h Read Write A a de i BitBLT Height This register specifies the height of the BitBLT in lines 1 BitBLT height in lines REG 801Ch 1 S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 65 Vancouver Design Center BitBLT Background Color Register REG 8020h Default 00000000h Read Write n a ail 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BitBLT Background Color bits 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
368. host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode and must be tied high to IO Vpp Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 10 12 Epson Research and Development Vancouver Design Center 4 MCF5307 To S1D13A04 Interface 4 1 Hardware Description Page 13 The interface between the S1D13A04 and the MCF5307 requires no external glue logic The polarity of the WAIT signal must be selected as active high by connecting CNF5 to IO Vpp see Table 4 1 Summary of Power On Reset Options on page 14 The following diagram shows a typical implementation of the MCF5307 to S1D13A04 interface MCF5307 1D13A04 A 17 0 AB 17 0 D 23 16 gt DB 7 0 D 31 24 gt DB 15 8 A18 gt M R CS4 gt CS lOVpp BS TA WAIT BWE1 p WE1 BWEO WEOH OE RD WR gt RD BCLKO CLKI System RESET p RESET Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MCF3307 to SIDI3A04 Interface Interfacing to the Motorola MCF
369. icroprocessor Generic 1 supports a Chip Select and an individual Read Enable Write Enable for each byte 3 1 Host Bus Interface Pin Mapping Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 10 12 Page 11 The Generic 1 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13A04 configuration see Section 4 2 S1D13A04 Hardware Configuration on page 14 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping 1D13A04 Pin Names Motorola MCF5307 AB 17 0 A 17 0 DB 15 0 D 31 16 WE1 BWE1 CS CS4 M R A18 CLKI BCLKO BS Connect to lOypp from the S1D13A04 RD WR OE RD OE WEO BWEO WAIT TA RESET system RESET 1D13A04 X37A G 010 01 Page 12 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals 1D13A04 X37A G 010 01 CLKI is a clock input which is required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example BCLKO from the Motorola MCF5307 is used for CLKI The address inputs AB 17 0 connect directly to the MCF5307 address bus A
370. ign Center bits 1 0 PCLK Source Select Bits 1 0 These bits determine the source of the Pixel Clock PCLK Table 8 5 PCLK Source Selection PCLK Source Select Bits PCLK Source 00 MCLK 01 BCLK 10 CLKI 11 CLKI2 8 3 3 Panel Configuration Registers Panel Type amp MOD Rate Register REG OCH Default 00000000h Read Write MOD Rate bits 5 0 17 Panel Color Direct Data Mono Panel Type Format Panel bits 1 0 Select Select bits 21 16 MOD Rate Bits 5 0 These bits are for passive LCD panels only When these bits are all 0 the MOD output signal DRDY toggles every FPFRAME For a non zero value n the MOD output signal DRDY toggles every n FPLINE bit 7 Panel Data Format Select When this bit 0 8 bit single color passive LCD panel data format 1 is selected For AC timing see Section 6 4 5 Single Color 8 Bit Panel Timing Format 1 on page 66 When this bit 1 8 bit single color passive LCD panel data format 2 is selected For AC timing see Section 6 4 6 Single Color 8 Bit Panel Timing Format 2 on page 68 bit 6 Color Mono Panel Select When this bit 0 a monochrome LCD panel is selected When this bit 1 a color LCD panel is selected bits 5 4 Panel Data Width Bits 1 0 These bits select the data width size of the LCD panel Table 8 6 Panel Data Width Selection Panel Data Width Bits 1 0 Passive ae Width Active Panel Data Wid
371. igure 6 12 Passive TFT Power Off Sequence Timing Table 6 18 Passive IFT Power Off Sequence Timing Symbol Parameter Min Max Units ti LCD bias deactivated to LCD signals inactive Note 1 Note 1 t2 Power Save Mode enabled to LCD signals low 0 1 BCLK 1 tl is controlled by software and must be determined from the bias power supply delay requirements of the panel connected 6 3 3 Direct HR TFT Interface Power On Off Sequence For Direct HR TFT Interface Power On Off sequence information see Connecting to the Sharp HR TFT Panels document number X37A G 011 xx Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 S1D13A04 X37A A 001 06 Page 56 Epson Research and Development Vancouver Design Center 6 4 Display Interface The timing parameters required to drive a flat panel display are shown below Timing details for each supported panel type are provided in the remainder of this section HT HDPS HPS HPW VDPS VPW VT Figure 6 13 Panel Timing Parameters 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 57 Vancouver Design Center Table 6 19 Panel Timing Parameter Definition and Register Summary Symbol Description Derived From Units HT Horizontal Total REG 20h bits 6 0 1 x 8 HDP Horizontal Dis
372. information on these topics refer to Section 6 References on page 15 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO ac cess cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles S1D13A04 X37A G 005 01 A data transfer is initiated when the memory address is placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high
373. inum logo is a trademark of Palm Computing Inc 3Com or its subsidiaries Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners DESIGNED FOR TT COMPUTING PLATFORM Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg VDC aa X37A C 001 04 04 EPSON S1D13A04 LCD USB Companion Chip Hardware Functional Specification Document Number X37A A 001 06 Status Revision 6 0 Issue Date 2003 05 01 Copyright O 2001 2003 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respec
374. ion see Section 4 2 S1D13A04 Hardware Configuration on page 13 The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping O NEC VR4102 4111 AB 17 0 ADD 17 0 DB 15 0 DAT 15 0 WE1 SHB CS LCDCS M R ADD18 CLKI BUSCLK BS Connect to lOypp from the S1D13A04 RD WR Connect to lOypp from the S1D13A04 RD RD WEO WR LCDRDY WAIT RESET system RESET Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 3 2 Host Bus Interface Signals The Host Bus Interface requires the following signals CLKI is a clock input which is required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example BUSCLK from the NEC VR4102 4111 is used for CLKI The address inputs AB 17 0 and the data bus DB 15 0 connect directly to the NEC VR4102 4111 address bus ADD 17 0 and data bus DAT 15 0 respectively CNF4 must be set to select little endian mode Chip Select CS must be driven low by LCDCS whenever the S1D13A04 is accessed by the VR4102 4111 M R memory register selects between memory or register accesses This signal is generated by the external address decode circuitry For this example M R is connected to address
375. ion 6 0 Epson Research and Development Page 143 Vancouver Design Center 10 Frame Rate Calculation The following formula is used to calculate the display frame rate fPcLK HT x VT FrameRate Where fpcLK PClk frequency Hz HT Horizontal Total REG 20h bits 6 0 1 x 8 Pixels VT Vertical Total REG 30h bits 9 0 1 Lines Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 144 Epson Research and Development Vancouver Design Center 11 Display Data Formats The following diagrams show the display mode data formats for a little endian system 1 bpp Byte 0 Byte 1 Ph RGB value from LUT Index A Byte 2 Host Address Panel Display 2 bpp PoP P2 P3P4P5P6P7 P RGB value from LUT Index Ap Bn Host Address Panel Display 4 bpp PoP P2 P3P4P5P6P7 P RGB value from LUT Index An Bn Cp Dn Host Address Panel Display PoP1P2P3P4P5P6P7 Byte 0 Byte 1 Pa RGB value from LUT Index Byte 2 An Bn Ch Dp En Fh Gh Hn Host Address Display Memory Panel Display 16 bpp ae bit 7 so RGB bit 0 Go Go Go Bo Bo Bp Bo By Byte 0 a o o o a E a y Bypasses LUT Byte 1 Ro Ro Ro Ro
376. ions e Shift Clock e CLK for Direct HR TFT See Table 4 6 LCD Interface Pin Mapping on page 32 for summary DRDY K9 60 LO3 This output pin has multiple functions e Display enable DRDY for TFT panels e 2nd shift clock FPSHIFT2 for passive LCD with Format 1 interface e LCD backplane bias signal MOD for all other LCD panels e General Purpose Output See Table 4 6 LCD Interface Pin Mapping on page 32 for summary GPIOO L8 57 LB3M This pin has multiple functions e PS for Direct HR TFT e General purpose lO pin 0 GPIOO GPIOO defaults to a Hi Z state during every RESET and defaults to an input after every RESET When this pin is used for HR TFT it must be configured as an output using REG 64h Otherwise it must either be configured as an output or be pulled high or low externally to avoid unnecessary current drain See Table 4 6 LCD Interface Pin Mapping on page 32 for summary 1D13A04 X37A A 001 06 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center Page 27 Table 4 3 LCD Interface Pin Descriptions 3 PFBGA TQFP15 RESET Pree Pin Name Type Ping Pin Cell State Description This pin has multiple functions e CLS for Direct HR TFT e General purpose IO pin 1 GPIO1 GPIO1 defaults to a Hi Z state during every RESET and defaults to
377. ions REG 8000h bit 18 is set to 1 7 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 140h REG 8014h is set to 0140h Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 78 Epson Research and Development Vancouver Design Center 8 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit 0 is set to 1 Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started 9 2 6 Move BitBLT in Negative Direction with ROP 1D13A04 X37A G 003 05 The Move BitBLT in Negative Direction with ROP is similar to the Move BitBLT in Positive direction Use this BitBLT operation when the source and destination BitBLT areas overlap and the destination address is greater then the source address Refer to Figure 9 1 on page 76 to see when to make the decision to switch to the Move BitBLT ina Positive direction When using the Move BitBLT in Negative Direction it is necessary to calculate the addresses of the last pixels as opposed to the first pixels This means calculating the addresses of the lower right corners as opposed to the upper left corners Example 13 Copy a 9 x 101 rectangle at the screen coordinates x 100 y 10 to screen c
378. is used on the S3U13A04B00C evaluation board The S1D13A04 display drivers can program the clock chip to support the frequencies required in the MODE tables If you are not using the S3U13A04B00C evaluation board you should disable this option EpsonMessages This debugging option enables the display of EPSON specific debug messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the display driver as they will significantly impact the performance of the display driver DEBUG_MONITOR This option enables the use of the debug monitor The debug monitor can be invoked when the display driver is first loaded and can be used to view registers and perform a few debugging tasks The debug monitor is still under development and is UNTESTED Windows6 CE 3 x Display Driver S1D13A04 Issue Date 01 10 19 X37A E 006 01 Page 10 MonoPanel DEBUG_BLT Mode File S1D13A04 X37A E 006 01 Epson Research and Development Vancouver Design Center This option should remain disabled unless you are performing specific debugging tasks that require the debug monitor This option is intended for the support of monochrome panels only The option causes palette colors to be grayscaled for correct display on a mono panel For use with color panels this option should not be enabled This option enables special BLT debugging messages on the debugging serial port This option when ena
379. is section demonstrates how to program and use the S1D13A04 USB controller Topics covered include e Basic concepts such as registers and interrupts e Initialization and data transfers S1D13A04 USB known issues 10 1 Registers and Interrupts 10 1 1 Registers S1D13A04 X37A G 003 05 Configuration interrupt notification and data transfers are all done using the S1D13A04 USB registers The USB registers are located 4000h bytes past the beginning of S1D13A04 address space and should be written read using 16 bit accesses On most systems the start of S1D13A04 address space is fixed by the system design The S1D13A04 evaluation board uses a PCI interface thus the start of S1D13A04 address space may vary from one session to the next Example code is written using a pointer to the USB registers pUSB The USB examples do not show how to obtain the register address For a description of how to get the register address when using the S5U13A04B00C evaluation board refer to the function hal AcquireController in Section 11 Hardware Abstraction Layer on page 112 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 95 Vancouver Design Center 10 1 2 Interrupts The S1D13A04 uses an interrupt to notify the local CPU when a USB event which requires servicing occurs Events such as USB reset and data transfer notifications generate inter rupts It is beyond the scope of this document
380. ision 6 0 Epson Research and Development Page 147 Vancouver Design Center 16 Bit Per Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth Display Data Formats on page 144 12 2 Color Modes 1 Bit Per Pixel Color Red Look Up Table 256x6 00 0 01 1 6 bit Red Data Green Look Up Table 256x6 00 01 6 bit Green Data Blue Look Up Table 256x6 00 01 6 bit Blue Data FC FD FE FF 1 re data from Image Buffer C unused Look Up Table entries Figure 12 5 I Bit Per Pixel Color Mode Data Output Path Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 148 2 Bit Per Pixel Color Epson Research and Development Vancouver Design Center 2 pre pixel data from Image Buffer Red Look Up Table 256x6 6 bit Red Data 6 bit Green Data 6 bit Blue Data unused Look Up Table entries 1D13A04 X37A A 001 06 Figure 12 6 2 Bit Per Pixel Color Mode Data
381. ite cycle on the host bus Since host CPU accesses to the S1D13A04 may occur asynchro nously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the Toshiba TMPR3905 12 using the Generic 2 Host Bus Interface These pins must be tied high connected to IO Vpp Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors 1D13A04 Issue Date 01 10 12 X37A G 002 01 Page 12 Epson Research and Development Vancouver Design Center 4 Toshiba TMPR3905 12 to S1D13A04 Interface 4 1 Hardware Description In this implementation the S1D13A04 occupies the TMPR3905 12 PC Card slot 1 IO address space IO address space closely matches the timing parameters for the S1D13A04 Generic 2 Host Bus Interface The address bus of the TMPR3905 12 PC Card interface is multiplexed and must be demul tiplexed using an advanced CMOS latch e g 74AHC373 BS bus start and RD WR are not used in this implementation and should be tied high connected to IO Vpp A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram demonstrates a typical implementation of the TMPR3905 12 to
382. ites This ability does not increase power consumption 2GPIOS can be accessed and if configured as outputs can be changed After reset the S1D13A04 is always in Power Save Mode Software must initialize the chip i e programs all registers and then clear the Power Save Mode Enable bit For further details see the register description for REG 14h bit 4 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 160 Epson Research and Development Vancouver Design Center 16 Mechanical Data 0 30 10 0 15 0 1max Dl TOP VIEW SIDE VIEW 05max 60000900 10 0LEECOTT 0000000 c n eco O O O O O O O O O O gt UO Tm w QTE G A T OO OO OO ee OO O O OO ee O O OO ee 12 3 4 5 6 7 8 9 10 11 BOTTOM VIEW All dimensions in mm Figure 16 1 Mechanical Data PFBGA 121 pin Package 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center Page 161 16 0 0 4 14 0 0 1 64 14 0 0 1 16 0 0 4 0 125 6 635 1 2 max _ gt gt All dimensions in mm 0 5 0 2 gt t 0 10 a a 1 0 Figure 16 2 Mechanical Data TQFP15 128 pin Package Hardware Functional Specification Issue Date 2003 05 01 S1D13A04 X37A A 001 06 Revisi
383. ium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details Wind River WindML v2 0 Display Drivers S1D13A04 Issue Date 01 09 28 X37A E 002 01 Page 6 1D13A04 X37A E 002 01 10 11 Epson Research and Development Vancouver Design Center Compile the VxWorks image Select the Builds tab in the Tornado Workspace Views window Right click on Sbpp files or 16bpp files and select Dependencies Click on OK to regenerate project file dependencies for All Project files Right click on Sbpp files or 16bpp files and select ReBuild All vxWorks to build VxWorks Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13A04 8bpp default vx Works or x 13A04 16bpp default vx Works to the bootable disk created in step 4 Start the VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGL demo program automatically Wind River WindML v2 0 Display Drivers Issue Date 01 09 28 EPSON S1D13A04 LCD USB Companion Chip QNX Photon v2 0 Display Driver Document Number X37A E 005 01 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may n
384. ivel View 13 2 1 Register Programming Enable 90 SwivelView Mode Set SwivelView Mode Select bits REG 10h bits 17 16 to 01 Display Start Address The display refresh circuitry starts at pixel B therefore the Main Window Display Start Address register REG 40h must be programmed with the address of pixel B To calculate the value of the address of pixel B use the following formula assumes 8 bpp color depth REG 40h bits 16 0 image address panel height x bpp 8 4 1 0 320 pixels x 8 bpp 8 4 1 79 4Fh Line Address Offset The Main Window Line Address Offset register REG 44h is based on the display width and programmed using the following formula REG 44h bits 9 0 display width in pixels 32 bpp 320 pixels 32 8 bpp 80 50h Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Epson Research and Development Page 153 Vancouver Design Center 13 3 180 SwivelView The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed The application image is written to the S1D13A04 in the following sense A B C D The display is refreshed by the S1D13A04 in the following sense D C B A physical memory display start address start address panel origin A B a 8 SwivelView o MOPUIM 5 i N N window o M INAJ AIMS ra C D g Vv
385. ixel 2 for 16 bpp ScreenStride Display WidthInPixels x BytesPerPixel 640 for 16 bpp Program the BitBLT Destination Start Address Register REG 8010h is set to 19C8h 2 Program the BitBLT Width Register to 9 1 REG 8018h is set to 08h 3 Program the BitBLT Height Register to 301 1 REG 801Ch is set to 12Ch 300 dec imal 4 Program the BitBLT Foreground Color Register REG 8024h is set to F800h Full in tensity red in 16 bpp is F800h 5 Program the BitBLT Operation Register to select Solid Fill REG 8008h bits 3 0 are set to OCh 6 Program the BitBLT Color Format Register for 16 bpp operations REG 8000h bit 18 is set to 1 7 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 140h REG 8014h is set to 0140h 8 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit 0 is set to 1 Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 76 Epson Research and Development Vancouver Design Center 9 2 5 Move BitBLT in a Positive Direction with ROP The Move BitBLT is used to copy one area of display memory to another area in display memory
386. iz E Bo g 3 I sir ld a z 2 3 F 3H a s e2 e ler g 3 o E 19 3 Bot 14 wok 85 3 3 8 o 9 8 2 m 15 5 8 s E J 8 Ir 5 aa A 33 5 5 E 3 3 El x HHI g ae g a 222 o 8 B ES E a a E q 3 3 E E 4 3 Ei 3 2 ee a do Ji Zo pl o mi s 4 g Ek a gg 3 Le E El a S E o E 2 o z El a E 38 ec 29 E ap SE gy EE 28 8 25 25 I w LTHM17CSTS vout u 3 2 gt 1 5 y 6 4 1 1 14 p uz 14 vcc GND gt Test Socket us 14 vcc ND Test Socket T 10H VIN co ou 15 ao 15 GPO 4 rH 14 318T8MHz c13 p so cre ou 5y O ji c19 osu E Figure 10 2 SIDI3A04B00C Schematics 2 of 6 S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 28 Epson Research and Development Vancouver Design Center y le al a J 5 el Hr 3 g Z g D gt l fg 3 y le g g jE a 5 la la 3 8S E go 3 E al z g 5 8 2 gt Q Q Ba Ba ES lan la 25 883 oe 4 lr 1 38 33 3 f 3 a Bn 36 28 383 z Je 3 lI Er 35 Ba ga 883 E Y s 5 T E ly de RS 3 E RoN s E BS S rv j 1no oa
387. k Divide Select Options PWM Clock Divide Select Bits 3 0 PWM Clock Divide Amount Oh 1 th 2 2h 4 3h 8 4h 16 5h 32 6h 64 7h 128 8h 256 9h 512 Ah 1024 Bh 2048 Ch 4096 Dh 8192 Eh 16384 Fh 32768 Note This divided clock is further divided by 256 before it is output at PWMOUT 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 115 Vancouver Design Center bit 3 PWM Clock Force High When this bit 0 the PWMOUT pin function is controlled by the PWM Clock enable bit When this bit 1 the PWMOUT pin is forced to high bit 1 PWMCLK Source Select Bits 1 0 These bits determine the source of PWMCLK Table 8 16 PWMCLK Source Selection PWMCLK Source Select Bits PWMCLK Source 00 CLKI 01 CLKI2 10 BCLK 11 PCLK Note For further information on the PWMCLK source select see Section 7 2 Clock Selec tion on page 87 bit 0 PWM Clock Enable When this bit 0 PWMOUT output acts as a general purpose output pin controllable by bit 3 of REG 70h When this bit 1 the PWM Clock circuitry is enabled Note The PWM Clock circuitry is disabled when Power Save Mode is enabled PWMOUT Duty Cycle Register REG 74h Default 00000000h Read Write 21 20 19 18 17 PWMOUT Duty Cycle bits 7 0 5 4 3 2 1 bits 7 0 PWMOUT Duty Cycle Bits 7 0 This register determines the duty cycle of the PWMOUT output Table 8 17
388. kground color The intended use of this BitBLT operation is to increase the speed of writing text to display memory As with the Write BitBLT all data sent to the BitBLT engine must be WORD 16 bit writes The BitBLT engine expands first the low byte then the high byte starting at bit 7 of each byte The start byte of the first WORD to be expanded and the start bit position within this byte must be specified The start byte position is selected by setting source address bit 0 to 0 to start expanding the low byte or 1 to start expanding the high byte Partially masked color expansion BitBLTs can be used when drawing a portion of a pattern i e a portion of a character on the screen The following examples illustrate how one WORD is expanded using the Color Expansion BitBLT 1 To expand bits 0 1 of the word Source Address 0 Start Bit Position 1 BitBLT Width 2 The following bits are expanded Word Sent To BitBLT Engine 15 8 7 0 7 0 7 0 High Byte Low Byte 2 To expand bits 0 15 of the word entire word Source Address 0 Start Bit Position 7 bit seven of the low byte BitBLT Width 16 The following bits are expanded Word Sent To BitBLT Engine High Byte Low Byte S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 71 Vancouver Design Center 3 To expand bits 8 9 of the word Source Address
389. lView disabled o 45 Picture in Picture Plus with SwivelView 90 enabled o 48 Picture in Picture Plus with SwivelView 180 enabled 51 Picture in Picture Plus with SwivelView 270 enabled 54 Move BitBLT Usage ica ER a ee A 76 Endpoint 1 Data Re ception p sss Me a a RA a 98 Endpoint 3 Data Reception e 100 EndPoint 2 Data Transmission 2 2 2 00 000 e eee ees 102 Endpoint 4 Data Transmission oaa ee 103 Endpoint 4 Interrupt Handling 0 00 0000 000004 105 Firmware Looping Continuously on Received OUT packets 108 Endpoint 3 Program Flow for Slow CPU o o o e 109 S1D13A04 X37A G 003 05 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 11 Vancouver Design Center 1 Introduction This guide discusses programming issues and provides examples for the main features of the S1D13A04 such as SwivelView Picture in Picture Plus and the BitBLT engine The example source code referenced in this guide is available on the web at www erd epson com This guide also introduces the Hardware Abstraction Layer HAL which is designed to simplify the programming of the S1D13A04 Most S1D13xxx products have HAL support thus allowing O
390. latency software can monitor this bit prior to a BitBLT read burst operation The following table shows the number of words available in the BitBLT FIFO under dif ferent status conditions Table 9 1 BitBLT FIFO Words Available BitBLT FIFO Full BitBLT FIFO Half BitBLT FIFO Not Number of Words Status Full Status Empty Status available in BitBLT REG 8004h Bit 4 REG 8004h Bit 5 REG 8004h Bit 6 FIFO 0 0 0 0 0 0 1 1 to 6 0 1 1 7 to 14 1 1 1 15to 16 BitBLT FIFO Half Full Status This is a read only status bit When this bit 1 the BitBLT FIFO is half full or greater than half full When this bit 0 the BitBLT FIFO is less than half full BitBLT FIFO Full Status This is a read only status bit When this bit 1 the BitBLT FIFO is full When this bit 0 the BitBLT FIFO is not full BitBLT Busy Status This bit is a read only status bit When this bit 1 the BitBLT operation is in progress When this bit 0 the BitBLT oper ation is complete S1D13A04 X37A G 003 05 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 61 Vancouver Design Center Note During a BitBLT Read operation the BitBLT engine does not attempt to keep the FIFO full If the FIFO becomes full the BitBLT operation stops temporarily as data is read out of the FIFO The BitBLT will restart only when less than 14 values remain in the FIFO BitBLT Command Register
391. ld from AS rising edge 0 ns 5 pte A 1 0 SIZ 1 0 deasserted to R W A 1 0 SIZ 1 0 asserted y Terk or next cycle t6 CS hold from AS rising edge 0 ns t7 DS rising edge to AS rising edge 0 ns t8 AS setup to CLK rising edge 1 ns t9 DSACK1 falling edge to DS rising edge 0 ns t10 CLK rising edge to DSACK1 high impedance Telk 2 ns t11 AS rising edge to DSACK1 rising edge 3 9 ns 112 D 15 0 setup to 4th CLK rising edge after CS 0 AS 0 and 4 T UDS 0 or LDS 0 CLK t13 D 15 0 hold from A 1 0 R W SIZ 1 0 write cycle 1 ns t14 DSACK1 falling edge to D 15 0 valid read cycle 3 ns t15 DS rising edge to D 15 0 high impedance read cycle 2 7 ns t16 Cycle Length 6 Tek Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 48 Epson Research and Development Vancouver Design Center 6 2 7 Motorola REDCAP2 Interface Timing Teko CKO t1 t8 A 16 1 R W CS IB a t12 pl t9 pala EBO EB1 write t3 t4 4 gt gt D 15 0 write valid lt gt EBo EB1 OE read 4 7K t6 t11 D 15 0 read valid Figure 6 8 Motorola Redcap2 Interface Timing S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center Table 6 14 Motorola Redcap2 Interface Timing
392. le 8 11 32 bit Address Increments for Color Depth Color Depth Pixel Increment x 1 bpp 32 2 bpp 16 4 bpp 8 bpp 4 16 bpp 2 For 90 and 270 SwivelView the X end position is incremented in 1 line increments Depending on the color depth some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 10h bit 19 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 107 Vancouver Design Center bits 9 0 PIP Window X Start Position Bits 9 0 These bits determine the X start position of the PIP window in relation to the origin of the panel Due to the S1D13A04 SwivelView feature the X start position may not be a horizontal position value only true in 0 and 180 SwivelView For further information on defining the value of the X Start Position register see Section 14 Picture in Picture Plus PIP on page 156 The register is also incremented differently based on the SwivelView orientation For 0 and 180 SwivelView the X start position is incremented by x pixels where x is relative to the current color depth Table 8 12 32 bit Address Increments for Color Depth Color Depth Pixel Increment x 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 For 90
393. le wceusbsh inf c Right click the WCEUSBSH INF file icon d Select Install Windows CE 3 x USB Driver Issue Date 01 10 19 1D13A04 X37A E 007 01 Page 8 Compile Switches 10 11 12 13 14 Epson Research and Development Vancouver Design Center Connect a USB cable from the USB device S5U13A04BO0C board to the USB host machine Boot the Windows CE machine from a floppy created in step 1 or from the hard drive created in step 2 From the Windows CE desktop click the Start button click Run click Browse Find the file repllog exe by default it resides in windows and select it Click the OK button The ActiveSync window on the host desktop is automatically in voked and the New Partnership window is opened automatically This window prompts Would you like to set up a partnership Click the No button Click the Next button The Microsoft ActiveSync Window is opened automatically and should display Guest connected Click the Explore button from the Microsoft ActiveSync window File transfers are now possible through the USB cable There are switches specific to the S1D13A04 USB driver which affect the USB driver These switches are added or removed from the compile switches in the file sources CEPC This option must be set for the CEPC platform and removed for all other platforms EPSONMESSAGES This debugging option enables the display of EPSON specific debu
394. left edge towards the right in steps of 32 bits per pixel see Table 8 4 The horizontal coordinates start at pixel 0 Program the PIP Window Y Start Position so that PIP Window Y Start Position x 32 bits per pixel Note Truncate the fractional part of the above equation 8 2 Picture In Picture Plus Examples 8 2 1 SwivelView 0 Landscape Mode o iaw I M 0 SwivelView PIP window y start position panel s origin REG 5Ch bits 9 0 PIP window y end position REG 5Ch bits 25 16 main window PIP window gt PIP window x start position PIP window x end position REG 58h bits 9 0 REG 58h bits 25 16 Figure 8 2 Picture in Picture Plus with SwivelView disabled SwivelView 0 or landscape is a mode in which both the main and PIP window are non rotated The images for each window are typically placed consecutively with the main window image starting at address O and followed by the PIP window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and PIP window To do so set the PIP Line Address Offset register REG 54h to the same value as the Main Window Line Address Offset register REG 44h S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Page 46 1D13A04 X37A G 00
395. line ADD 18 allowing system address ADD18 to select between memory or register accesses WE 1 connects to SHB the high byte enable signal from the NEC VR4102 4111 which in conjunction with address bit 0 allows byte steering of read and write opera tions WEO connects to WR the write enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is writing data to the S1D13A04 RD connects to RD the read enable signal from the NEC VR4102 4111 and must be driven low when the VR4102 4111 is reading data from the 1D13A04 WAIT connects to LCDRDY and is a signal output from the S1D13A04 that indicates the VR4102 VR4111 must wait until data is ready read cycle or accepted write cycle on the host bus Since VR4102 VR4111 accesses to the S1D13A04 may occur asyn chronously to the display update it is possible that contention may occur in accessing the S1D13A04 internal registers and or display buffer The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS and Read Write RD WR signals are not used in this implemen tation of the NEC VR4102 4111 interface using the Generic 2 Host Bus Interface These pins must be tied high connected to IO Vpp Interfacing to the NEC VR4102 VR4111 Microprocessors 1D13A04 Issue Date 01 10 12 X37A G 007 01 Page 12 4 VR4102 VR4111 to S1D13A04 Interface 4 1 Hardware Description Eps
396. ll Microprocessor X37A G 012 xx Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 xx S1D13A04 Register Summary X37A R 001 xx Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center 18 Sales and Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Hardware Functional Specification Issue Date 2003 05 01 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de Revision 6 0 Page 163 Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg S1D13A04 X37A A 001 06 Page 164 Epson Research and Development V
397. ll Status FIFO Full Status Available 0 0 0 0 do not read up to 8 1 1 1 0 0 1 0 8 1 1 16 Note The sequence of register initialization is irrelevant as long as all required registers are programmed before the BitBLT is started Programming Notes and Examples Issue Date 2002 08 21 1D13A04 X37A G 003 05 Page 92 Epson Research and Development Vancouver Design Center 9 3 S1D13A04 BitBLT Synchronization A BitBLT operation can only be started if the BitBLT engine is not busy servicing another BitBLT Before a new operation is started software must confirm the BitBLT Busy Status bit REG 8004h bit 0 is set to zero The status of this bit can either be tested after each BitBLT operation or before each BitBLT operation Testing the BitBLT Status After Testing the BitBLT Active Status after starting a new BitBLT is simpler and less prone to errors To test after each BitBLT operation perform the following 1 Program and start the BitBLT engine 2 Wait for the current BitBLT operation to finish Poll the BitBLT Busy Status bit REG 8004h bit 0 until it returns a 0 3 Continue with program execution Testing the BitBLT Status Before Testing the BitBLT Active Status before starting a new BitBLT results in better perfor mance as both CPU and BitBLT engine can be running at the same time This is most useful for BitBLTs that are self completing once started they don t re
398. lowing it to communicate with its many peripheral units The address bus is multiplexed A 12 0 using an address latch signal ALE which controls the driving of the address onto the address bus The full 26 bit address bus A 25 0 is generated to devices not capable of receiving a multiplexed address using external latches controlled by ALE The TMPR3905 12 provides two revision 2 01 compliant PC Card slots The 16 bit PC Card slots provide a 26 bit multiplexed address and additional control signals which allow access to three 64M byte address ranges IO memory and attribute space The signal CARDREG selects memory space when high and attribute or IO space when low Memory and attribute space are accessed using the write and read enable signals WE and RD When CARDREG is low card IO space is accessed using separate write CARDIOWR and read CARDIORD control signals 2 1 2 Card Access Cycles S1D13A04 X37A G 002 01 A data transfer is initiated when the address is placed on the PC Card bus and one or both of the card enable signals CARD1CSL and CARD1CSH are driven low CARDREG is inactive for memory and IO cycles If only CARDI1CSL is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on the PC Card data bus lines D 7 0 If only CARD 1CSH is driven low an odd byte transfer occurs on PC Card data lines D 15 8 If both CARDICSL and CARD1CSH are driven low a 16 bi
399. m This document and the source code for the WindML display drivers is updated as appro priate Please check the Epson Research and Development website at www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Wind River WindML v2 0 Display Drivers S1D13A04 Issue Date 01 09 28 X37A E 002 01 Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2 0 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo program These instructions assume that Wind River s Tornado platform is already installed Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the WindML display driver into it From a command prompt or GUI interface create a new directory e g x113A04 Unzip the file 13A04windml zip to the newly created working directory The files will be unzipped to the directories x 13A04 8bpp and x 13A04 16bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target
400. m S1D13A04 clock frequencies The S1D13A04 also has internal clock dividers providing additional flexibility Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13A04 Issue Date 01 10 12 X37A G 002 01 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13A04 Hardware Configuration The S1D13A04 latches CNF6 through CNFO to allow selection of the bus mode and other configuration data on the rising edge of RESET For details on configuration refer to the SID13A04 Hardware Functional Specification document number X37A A 001 xx The table below shows the configuration settings important to the Generic 2 host bus interface used by the Toshiba TMPR3905 12 Table 4 1 Summary of Power On Reset Options S1D13A04 Configuration Input Power On Reset State 1 connected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 Reserved Must be set to 1 CNF5 WAIT is active high CNF6 CLKI to BCLK divide ratio 2 1 EA configuration for Toshiba TMPR3905 3912 microprocessor 4 3 Memory Mapping and Aliasing In this implementation the TMPR3905 12 control signal CARDREG is ignored This means that the S1D13A04 takes up the entire PC Card slot 1 The S1D13A04 is a memory mapped device and uses two 256K byte blocks which are selected using A18 from the TMPR3905 12 A18 is connected to the S1D13A04 M R pin The internal registers occupy the first 256K byte block and the 160K byt
401. mW H C F d0x0 0x0 Where W is the configured width of the display H is the configured height of the display C is the color depth in bpp either 8 or 16 F is the configured frame rate This command starts the bench utility which will initialize the driver as the secondary display and exercise the drivers main functions If the display appears satisfactory restart QNX Photon and the restart will result in the S1D13A04 display driver becoming the primary display device e To restore the display driver to the default comment out changes made to the trap file crt NODE QNX Photon v2 0 Display Driver Issue Date 01 10 19 EPSON 1D13A04 LCD USB Companion Chip Windows CE 3 x Display Driver Document Number X37A E 006 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of thei
402. med If no previous Read command has been issued the unit size defaults to 8 bit addr The address to read data from Multiple addresses can be given 13A04PLAY Diagnostic Utility S1D13A04 Issue Date 01 10 05 X37A B 002 01 Page 8 1D13A04 X37A B 002 01 Epson Research and Development Vancouver Design Center Run scriptfile This command opens the file scriptfile and executes each line as if it were typed from the command prompt For more information on scriptfiles see Section Script Files on page 12 Where scriptfile The file containing 13A04PLAY commands S SI16132 startaddr endaddrllen datal data2 data3 data4 Search the display buffer for the given data Where 8116132 The unit size 8 bit bytes 16 bit words 32 bit dwords If a unit size is not specified this command uses the unit size from the last Search command performed If no previous Search command has been issued the unit size defaults to 8 bit startaddr The starting address to begin the search from Specifying a period uses the same starting address as the last Search command performed endaddrllen Determines how many units of the display buffer will be searched through A number without a prefix represents a physical ending address If a L prefix is used the number that follows represents len or the number of bytes words dwords to be searched through Len is based on the unit size For example L8 when the unit size is 16
403. ming BitBLT at 16 bpp color depth the number of WORDS to be sent is the same as the number of pixels to be transferred as each pixel is one WORD wide The number of WORD writes the BitBLT engine expects is calculated using the following formula Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 90 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center WORDS Pixels BitBLTWidth x BitBLTHeight When the color depth is 8 bpp the formula must take into consideration that the BitBLT engine accepts only WORD accesses and pixels are only one BYTE This may lead to a different number of WORD transfers than there are pixels to transfer The number of WORD accesses is dependant on the position of the first pixel within the first WORD of each destination row Is the pixel stored in the low byte or the high byte of the WORD Read BitBLT phase is determined as follows Destination phase is 0 when the first pixel is in the low byte and the second pixel is in the high byte of the WORD When the destination phase is 0 bit O of the Destination Start Address Register is 0 The destination phase is 1 if the first pixel of each destination row is contained in the high byte of the WORD the contents of the low byte are ignored When the destination phase is 1 bit O of the Destination Start Address Register is set Depending on the destination phase and the BitBLT width the last WORD may contain
404. ming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 30 Epson Research and Development Vancouver Design Center 7 SwivelView Most computer displays operate in landscape mode In landscape mode the display is typically wider than it is high For example a display size of 320x240 is 320 pixels wide and 240 lines high Swivel View rotates the display image counter clockwise in ninety degree increments Rotating the image on a 320x240 display by 90 or 270 degrees yields a display that is now 240 pixels wide and 320 lines high The S1D13A04 provides hardware support for SwivelView in all color depths 1 2 4 8 and 16 bpp For further details on the SwivelView feature see the S D 3A04 Hardware Functional Specification document number X37A A 001 xx 7 1 SwivelView Registers These are the registers which control the Swivel View feature Display Settings Register REG 1 0h Default 00000000h Read Write Pixel Pixel P P Doubling Doubling ped Gee Window SwivelView Mode Select Vertical Horiz Enable 25 22 19 Bits per pixel Select actual value 1 2 4 8 or 16 bpp 3 2 1 SwivelView Mode Select The SwivelView modes are selected using the Swivel View Mode Select Bits 1 0 bits 17 16 The combinations of these bits provide the following rotations Table 7 1 SwivelView Mode Select Bits SwivelView Mode SwivelView Mode Swivel
405. mmunications devices and Palm size PCs The S1D13A04 utilizes a guaranteed low latency CPU architecture that provides support for microprocessors without READ Y WAIT handshaking signals The 32 bit internal data path write buffer and the Hardware Acceleration Engine provide high performance bandwidth into display memory allowing for fast display updates Direct support for the Sharp HR TFT removes the requirement of an external Timing Control IC Additionally products requiring a rotated display can take advantage of the Swivel View feature which provides hardware rotation of the display memory transparent to the software application The S1D13A04 also provides support for Picture in Picture Plus a variable size Overlay window The S1D13A04 with its integrated USB client provides impressive support for Palm os handhelds However its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 12 Epson Research and Development Vancouver Design Center 2 Features 2 1 Integrated Frame Buffer e Embedded 160k byte SRAM display buffer 2 2 CPU Interface e Direct support of the following interfaces Generic MPU bus interface with programmable ready WAIT Hitachi SH 4 SH 3 Motorola M68K Motorola MC68EZ328 MC68VZ328 DragonBall Motorola REDCAP2 no WA
406. monochrome WORD aligned bitmap of dimensions 300 x 600 with the origin at an address A The color expanded rectangle will be displayed at the screen coordinates X 20 Y 30 The foreground color corresponds to the LUT entry at index 134 the background color to index 124 1 First we need to calculate the address of the WORD within the monochrome bitmap containing the pixel x 125 y 17 SourceAddress BitmapOrigin y x SourceStride x 8 A Sy x SourceStride Sx 8 A 17 x 38 125 8 A 646 15 A 661 where SourceStride BitmapWidth 15 16 300 15 16 19 WORDS per line 38 BYTES per line 2 Calculate the destination address upper left corner of the screen BitBLT rectangle using the following formula DestinationAddress Y x ScreenStride X x BytesPerPixel 30 x 320 20 x 1 9620 2594h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixel 320 for 8 bpp Program the BitBLT Destination Start Address Register REG 8010h is set to 2594h 3 Program the BitBLT Width Register to 12 1 REG 8018h is set to OBh 11 decimal 4 Program the BitBLT Height Register to 18 1 REG 801Ch is set to 11h 17 deci mal 5 Program the Source Phase in the BitBLT Source Start Address Register In this exam ple the source address equals A 661 odd so REG 800Ch is set to 1 Since only bit O flags the source p
407. mory Devices Timing 20 000002 eee eee 12 Figure 4 1 Typical Implementation of MPC82x to S1D13A04 Interface 15 Interfacing to the Motorola MPC82x Microprocessor S1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13A04 LCD USB Companion Chip and the Motorola MPC82x micropro cessor The designs described in this document are presented only as examples of how such inter faces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola MPC82x Microprocessor S1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC82x 2 1 The MPC8xx System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an over
408. mption 128 REG 403Ah Index OAh Packet Control 128 REG 403Ah Index 0Bh Reserved 129 REG 403Ah Index 0Ch FIFO Control 129 REG 4040h USBFC Input Control Register 130 REG 4042h Reserved 130 REG 4044h Pin Input Status Pin Output Data Register 131 REG 4046h Interrupt Control Enable Register 0 131 REG 4048h Interrupt Control Enable Register 1 131 REG 404Ah Interrupt Control Status Clear Register O 132 REG 404Ch Interrupt Control Status Clear Register 1 133 REG 404Eh Interrupt Control Masked Status Register 0 134 REG 4050h Interrupt Control Masked Status Register 1 134 REG 4052h USB Software Reset Register 134 REG 4054h USB Wait State Register 134 2D Acceleration B BLT Register Descriptions Offset 8000h REG 8000h BitBLT Control Register 135 REG 8004h BitBLT Status Register 136 REG 8008h BitBLT Command Register 137 REG 800Ch BitBLT Source Start Address Register 139 REG 8010h BitBLT Destination Start Address Register 139 REG 8014h BitBLT Memory Address Offset Register 140 REG 8018h BitBLT Width Register 140 REG 801Ch BitBLT Height Register 140 REG 8020h BitBLT Background Color Register 141 REG 8024h BitBLT Foreground Color Register 141 2D Acceleration BIEBLT Data Register Descriptions Offset 10000h AB16 ABO 10000h 1FFFEh 2D Accelerator BitBLT Data Memory Mapped Region Register 141 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Pag
409. n X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Center Table 6 8 Generic 2 Interface Timing Page 39 Symbol Parameter Min Max Unit feuscik Bus clock frequency 50 MHz TBuscik Bus clock period 1 ABuscLk ns u A 1 6 0 M R BHE setup to first BUSCLK rising edge where CS 9 ae 0 and either RD 0 or WE 0 t2 CS setup to BUSCLK rising edge 9 ns t3 RD WE setup to BUSCLK rising edge 1 ns t4 RD or WE state change to WAIT driven low 1 10 ns t5 RD falling edge to D 15 0 driven read cycle 2 10 ns t6 D 15 0 setup to 4th rising BUSCLK edge after CS 0 and WE 0 1 TBUSCLK t7 A 16 0 M R BHE and CS hold from RD WE rising edge 0 ns t8 CS deasserted to reasserted 0 ns t9 WAIT rising edge to RD WE rising edge 0 ns t10 WE RD deasserted to reasserted 1 TBUSCLK t11 Rising edge of either RD or WE to WAIT high impedance 0 5 TBUSCLK t12 D 15 0 hold from WE rising edge write cycle 2 ns t13 D 15 0 hold from RD rising edge read cycle ns t14 Cycle Length 6 TBUSCLK Table 6 9 Generic 2 Interface Truth Table for Little Endian WEA RD BHE AO D 15 8 D 7 0 Comments 0 1 0 0 valid valid 16 bit write 0 1 1 0 valid 8 bit write at even address 0 1 0 1 valid z 8 bit write at odd address 1 0 0 0 valid valid 16 bit read 1 0 1 0 valid 8 bit read at
410. n pixel is at x 3 y 4 Therefore an offset within the pattern itself must be calculated SourceAddress PatternOffset StartPatternY x 8 x BytesPerPixel StartPatternX x BytesPerPixel 156K 4x8x1 4 3x 1 156K 35 159779 27023h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp Program the BitBLT Source Start Address Register REG 800Ch is set to 27023h 3 Program the BitBLT Width Register to 100 1 REG 8018h is set to 63h 99 deci mal Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 87 Vancouver Design Center Program the BitBLT Height Register to 150 1 REG 801Ch is set to 95h 149 deci mal Program the BitBLT Operation Register to select the Pattern Fill BitBLT with Trans parency REG 8008h bits 3 0 are set to 7h Program the BitBLT Background Color Register to select transparent color This ex ample uses blue LUT index 1 as the transparent color REG 8020h is set to 01h Program the BitBLT Color Format Select bit for 8 bpp operations REG 8000h bit 18 is set to 0 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 2 160 AOh REG 8014h is set to AOh Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit 0 is
411. n Layer e S5U13A04 Evaluation Boards Windows CE Display Driver e VXWorks Tornado Display CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Driver North America Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk Europe Riesstrasse 15 Tel 089 14005 0 Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Epson Europe Electronics GmbH 80992 Munich Germany Fax 089 14005 110 http Avwww epson electronics de Copyright O 2000 2001 Epson Research and Development Inc All rights reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Palm Computing is a registered trademark and the Palm OS platform Plat
412. n Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X37A G 010 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 000000 00000048 11 Table 4 1 Summary of Power On Reset Options o o 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle 2 2 o e e 9 Figure 2 2 MCF5307 Memory Write Cycle o o e ee ee 9 Figure 2 3 Chip Select Module Outputs TlMidg8_ e 10 Figure 4 1 Typical Implementation of MCF5307 to S1ID13A04 Interface 13 Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 010 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X37A G 010 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13A04 LCD USB Companion Chip and the Motorola MCF5307 Coldfire Processor The designs described in this document are presented only as examples of how such inter faces might be implemented This application note is updated as appropriate Please check
413. n Window Stride image width x bpp 8 240x4 8 120 78h main window display start address register desired byte address panel width 1 x Main Window Stride 4 0 320 1 x 120 4 9570 2562h Program the Main Window Display Start Address register REG 40h is set to 00002562h 2 Determine the main window line address offset number of dwords per line image width 32 bpp 240 32 4 30 1Eh Program the Main Window Line Address Offset register REG 44h is set to 0000001Eh Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 36 7 3 Limitations Epson Research and Development Vancouver Design Center 7 3 1 SwivelView 0 and 180 In SwivelView 0 and 180 the Main Window Line Address Offset register REG 44h requires the panel width to be a multiple of 32 bits per pixel If this is not the case then the Main Window Line Address Offset register must be programmed to a longer line which meets this requirement This longer line creates a virtual image where the width is main window line address offset register X 32 bits per pixel In SwivelView 0 this virtual image should be drawn in display memory as left justified and in SwivelView 180 this virtual image should be drawn in display memory as right justified A left justified image is one drawn in display memory such that each of the image s lines only use the left most portion of the
414. n a BitBLT Source Start Address bits 20 16 BitBLT Source Start Address bits 1 A eee ee BitBLT Destination Start Address bits 15 0 BitBLT Memory Address Offset bits 10 0 11 BitBLT Width bits 9 0 10 BitBLT Height bits 9 0 10 BitBLT Background Color bits 15 0 BitBLT Foreground Color bits 15 BitBLT Data bits 31 16 BitBLT Data bits 15 0 Register Summary Cn ee a bie Issue Date 01 10 02 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Register Summary X37A R 001 01 Issue Date 01 10 02 EPSON S1D13A04 LCD USB Companion Chip 13A04CFG Configuration Program Document Number X37A B 001 01 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Pag
415. n electronics de Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pe card com S1D13A04 X37A G 005 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http Awww epson com sg Interfacing to the PC Card Bus Issue Date 01 10 12 EPSON 1D13A04 LCD USB Companion Chip Power Consumption Document Number X37A G 006 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and
416. n low The read or write enable signals FMEMRD or MEMWR are driven low for the appropriate cycle and IORDY is driven low by the S1D13A04 to insert wait states into the cycle The high byte enable UBE is driven low for 16 bit transfers and high for 8 bit transfers Interfacing to the NEC VR4181A Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 008 01 Epson Research and Development Page 10 Vancouver Design Center 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 2 Host Bus Interface which is most suitable for direct connection to the NEC VR4181A microprocessor Generic 2 supports an external Chip Select shared Read Write Enable for high byte and individual Read Write Enable for low byte The Generic 2 Host Bus Interface is selected by the S1D13A04 on the rising edge of RESET After RESET is released the bus interface signals assume their selected config uration For details on the S1D13A04 configuration see Section 4 2 S1D13A04 Hardware Configuration on page 13 3 1 Host Bus Interface Pin Mapping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping cla ake NEC VR4181A AB 17 0 A 17 0 DB 15 0 D 15 0 WE1 UBE CS LCDCS M R A18 CLKI SYSCLK BS Connect to lOypp from the S1D13A04 RD WR Connect to lOypp from the S1D
417. n must be tied to IO Vpp e For Generic 2 this pin must be tied to IO Vpp e For SH 3 SH 4 this pin inputs the bus start signal BS e For MC68K 1 this pin inputs the address strobe AS e For MC68K 2 this pin inputs the address strobe AS e For REDCAP2 this pin must be tied to lO Vpp e For DragonBall this pin must be tied to lO Vpp See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary RD WR F3 15 LI This input pin has multiple functions e For Generic 1 this pin inputs the read command for the upper data byte RD1 e For Generic 2 this pin must be tied to IO Vpp For SH 3 SH 4 this pin inputs the RD WR signal The S1D13A04 needs this signal for early decode of the bus cycle e For MC68K 1 this pin inputs the R W signal e For MC68K 2 this pin inputs the R W signal e For REDCAP2 this pin inputs the R W signal e For DragonBall this pin must be tied to IO Vpp See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary RD El 12 LI This input pin has multiple functions e For Generic 1 this pin inputs the read command for the lower data byte RDO e For Generic 2 this pin inputs the read command RD e For SH 3 SH 4 this pin inputs the read signal RD e For MC68K 1 this pin must be tied to lO Vpp e For MC68K 2 this pin inputs the bus size bit 1 SIZ1 e For REDCAP2 this pin inputs th
418. n sent by the 1D13A04 bit 3 Endpoint 3 Interrupt Enable When set this bit enables an interrupt to occur when a USB Endpoint 3 Data Packet has been received by the S1D13A04 bit 2 Endpoint 2 Interrupt Enable When set this bit enables an interrupt to occur when the USB Endpoint 2 Transmit Mail box registers have been read by the USB host 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 119 Vancouver Design Center bit 1 Endpoint 1 Interrupt Enable When set this bit enables an interrupt to occur when the USB Endpoint 1 Receive Mail box registers have been written to by the USB host Interrupt Status Register 0 REG 4004h Default 00h Read Write 8 Upper Interrupt Active read only 7 6 5 4 3 2 1 0 Suspend Request SOF Interrupt Reserved Endpoint 4 Endpoint 3 Endpoint 2 Endpoint 1 Interrupt Status Status Interrupt Status Interrupt Status Interrupt Status Interrupt Status bit 7 Suspend Request Interrupt Status This bit indicates when a suspend request has been received by the S1D13A04 Writing a 1 clears this bit bit 6 SOF Interrupt Status This bit indicates when a start of frame packet has been received by the S1D13A04 Writ ing a 1 clears this bit bit 5 Reserved This bit must be set to 0 bit 4 Endpoint 4 Interrupt Status This bit indicates when a USB Endpoint 4 Data packet has been sent by the S1D13A04 Writing a 1 clea
419. nals 2 2 ee we 10 4 MC68VZ328 to S1D13A04 Interface o eee eee 11 4 1 Hardware Description a eee ee 11 4 2 S1D13A04 Hardware Configuration 2 2 2 ee ee 12 4 2 1 Register Memory Mapping osaa aaa 13 4 2 2 MC68VZ328 Chip Select and Pin Configuration oaoa a 13 5 Software foe 5 Ace ee A E be a We a 14 References ara a a a a ee BR a es a a a ee we 15 6 1 Doctiments sr Ao Ace a ee A sy ae See BE LE a Me HS 6 2 Document Sources 2 0 0 a 0 2 ee ee ee ee ee ee AS 7 Sales and Technical Support ee 16 7 1 EPSON LCD USB Companion Chips SID13A04 2 2 2 2 2 16 72 Motorola MC68VZ328 Processor 2 2 ee ee ee ee 16 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 012 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X37A G 012 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 002 eee ee eee 9 Table 4 1 Summary of Power On Reset Options 2 00000 20000 12 Table 4 2 WS Bit Programming 0 00000 a A a a a ee a ea 13 List of Figures Figure 4 1 Typical Implementation of MC68VZ328 to S1D13A04 Interface
420. nd Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the PC Card Bus X37A G 005 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 2 0 00022 ee eee 10 Table 4 1 Summary of Power On Reset Options o o 0 002 000 002 eee 13 List of Figures Figure 2 1 PC Card Read Cycler oia ge Ware a ha es a ee ek 9 Fig re 2 2 PC Card Write Cycle es 208 dy So ae OS Be a RG ee Bare da 9 Figure 4 1 Typical Implementation of PC Card to S1D13A04 Interface 12 Interfacing to the PC Card Bus S1D13A04 Issue Date 01 10 12 X37A G 005 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the PC Card Bus X37A G 005 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13A04 LCD USB Companion Chip and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such inter faces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments
421. nd it is the responsibility of the CPU to provide the required amount of data When performing BitBLTs at 16 bpp color depth the number of WORDS to be sent is the same as the number of pixels as each pixel is one WORD wide The number of WORD writes the BitBLT engine expects is calculated using the following formula Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 80 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center WORDS Pixels BitBLTWidth x BitBLTHeight When the color depth is 8 bpp the formula must take into consideration that the BitBLT engine accepts only WORD accesses and each pixel is one BYTE This may lead to a different number of WORD transfers than there are pixels to transfer The number of WORD accesses is dependant on the position of the first pixel within the first WORD of each row Is the pixel stored in the low byte or the high byte of the WORD This aspect of the BitBLT is called phase and is determined as follows Source phase is 0 when the first pixel is in the low byte and the second pixel is in the high byte of the WORD When the source phase is 0 bit O of the Source Start Address Register is 0 The Source Phase is 1 if the first pixel of each row is contained in the high byte of the WORD the contents of the low byte are ignored When the source phase is 1 bit 0 of the Source Start Address Register is set Depending on the Source Phase and th
422. nected to IO Vpp 0 connected to Vss CNF4 CNF 2 0 CNF3 Reserved Must be set to 1 CNF5 WAIT is active high CNF6 CLKI to BCLK divide ratio 2 1 EA configuration for SA 1110 microprocessor S1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 4 3 StrongARM SA 1110 Register Configuration The SA 1110 requires configuration of several of its internal registers to interface to the S1D13A04 Generic 2 Host Bus Interface The Static Memory Control Registers MSC 2 0 are read write registers containing control bits for configuring static memory or variable latency IO devices These regis ters correspond to chip select pairs nCS 5 4 nCS 3 2 and nCS 1 0 respectively Each of the three registers contains two identical CNFG fields one for each chip select within the pair Since only nCS 5 3 controls variable latency IO devices MSC2 and MSC1 should be programmed based on the chip select used Parameter RTx lt 1 0 gt should be set to 01b selects variable latency IO mode Parameter RBWx should be set to 1 selects 16 bit bus width Parameter RDFx lt 4 0 gt should be set according to the maximum desired CPU frequency as indicated in the table below Table 4 2 RDFx Parameter Value versus CPU Maximum Frequency CPU Frequency MHz RDFx 57 3 85 9 1 88 5 143 2 2 147 5 2
423. nitialize the registers 5 Type xa to display the contents of the registers 6 Type x 80 to read register 80h 7 Type x 80 10 to write 10h to register 80h 8 Type f 0 ffff aa to fill the first 10000h bytes of the display buffer with AAh 9 Type d 0 ff to read the first 100h bytes of the display buffer 10 Type show to display a test pattern 11 Type m to display current mode information 12 Type m 2 to set the color depth to 2 bpp 13 Type show to display a test pattern 14 Type q to exit the program 13A04PLAY Diagnostic Utility S1D13A04 Issue Date 01 10 05 X37A B 002 01 Page 12 Script Files 1D13A04 X37A B 002 01 Epson Research and Development Vancouver Design Center 13A04PLAY can be controlled by a script file This is useful when e there is no display to monitor command keystroke accuracy various registers must be quickly changed to view results A script file is an ASCII text file with one 13AO04PLAY command per line Script files can be executed from within 13A04PLAY using the Run command e g run dumpregs scr Alternately the script file can be executed from the OS command prompt On a PC platform a typical script command line might be 13A04PLAY run dumpregs scr gt results This causes the file dumpregs scr to be interpreted as commands by 13A04PLAY and the results to be redirected to the file results Example 1 Create a script file that reads all registers This file initializes th
424. nnector H1 on page 17 and Table 5 2 Extended LCD Signal Connector H2 on page 18 6 7 1 Direct LCD Connector The direct LCD Connector H1 provides all LCD panel signals required for Active Matrix TFT and Passive LCD panels These signals are buffered to either a 3 3V level or a5 0V level depending on the setting of JP3 See Table 3 2 Jumper Summary on page 11 S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Page 21 Vancouver Design Center 6 7 2 Extended LCD Connector The S1D13A04 directly supports Sharp 18 bit HR TFT and compatible panels The extended LCD connector H2 provides the extra signals required to support these panels The signals on this connector are provided directly from the S1D13A04 without any buffering and are 3 3V signals 6 8 USB Support The S1D13A04 USB controller provides a Revision 1 1 compliant USB client The S1D13A04 acts as a USB device and connects to an upstream hub or USB host through connector J1 on the S5Ul13A04B00C evaluation board Clamping diodes have been added to protect the USB bus from ESD and shorting 6 8 1 USB IRQ Support The S1D13A04 supports interrupts through output pin IRQ This interrupt can be used to support interrupts from the USB client of the S1D13A04 The S5U13A04B00C evaluation board supports this capability by connecting IRQ to the PCI interrupt INTA of the PCI slot that the S
425. not used for that display mode S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 19 Vancouver Design Center 5 2 1 Gray Shade Modes Gray shade monochrome modes are defined by the Color Mono Panel Select bit REG OCh bit 6 When this bit is set to 0 the value output to the panel is derived solely from the green component of the LUT For each gray shade a table of sample LUT values is provided These LUT values are a standardized set of intensities used by the Epson S1D13A04 utility programs Note These LUT values carry eight bits of significance The 1D13A04 LUT uses only the six MSB The 2 LSB are ignored 1 bpp gray shade The 1 bpp gray shade mode uses the green component of the first 2 LUT entries The remaining indices of the LUT are unused Table 5 2 Suggested LUT Values for 1 Bpp Gray Shade Es Unused entries 2 bpp gray shade The 2 bpp gray shade mode uses the green component of the first 4 LUT entries The remaining indices of the LUT are unused Table 5 3 Suggested LUT Values for 4 Bpp Gray Shade EE Unused entries Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 20 Epson Research and Development Vancouver Design Center 4 bpp gray shade The 4 bpp gray shade mode uses the green component of the first 16 LUT entries The remaining indices of the LUT are unused Table 5 4 Suggested LUT V
426. nput after every RESET When this pin is not used for USB it must either be configured as an output using REG 64h or be pulled high or low externally to avoid unnecessary current drain This output pin is the IRQ pin for USB When IRQ is activated IRQ O K8 58 LO3 0 an active high pulse is generated and stays high until the IRQ is serviced by software at REG 404Ah or REG 404Ch This pin has multiple functions PWMOUT O A9 100 LO3 0 e PWM Clock output e General purpose output S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 29 Vancouver Design Center 4 3 3 Clock Input Table 4 4 Clock Input Pin Descriptions PFBGA TQFP15 RESET nee Pin Name Type Pin Pin Cell State Description CLKI FS 19 Cl Typically used as input clock source for bus clock and memory clock CLKI2 B9 99 Cl Typically used as input clock source for pixel clock USBCLK J8 59 Ll Typically used as input clock source for USB 4 3 4 Miscellaneous Table 4 5 Miscellaneous Pin Descriptions PFBGA TQFP15 RESET i Pin Name Type Ping Pin Cell State Description These inputs are used to configure the S1D13A04 see Table C9 C8 B8 4 7 Summary of Power On Reset Options on page 30 CNF 6 0 D7 C7 B 102 108 Cl Note These pins are used for configuration of the 7 A7 1D13A04 and must be connected direc
427. ns are not available when using the REDCAP interface Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 50 Epson Research and Development Vancouver Design Center 6 2 8 Motorola Dragonball Interface Timing with DTACK e g MC68EZ328 MC68VZ328 Terko CLKO ti t4 G a m B Ap16 1 MIND paar tl 13 5 gt CSX DES N ity e BE ale us UWE LWE write g Oo t1 a JE f OE read y t7 t8 D 15 0 write Valid t2 9 p t10 D 15 0 read Valid i t12 t3 t11 T DTACK cis l Figure 6 9 Motorola Dragonball Interface Timing with DTACK S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 51 Vancouver Design Center Table 6 15 Motorola Dragonball Interface Timing with DTACK Symbol Parameter Min Max Unit foLKo Clock frequency 33 note 1 MHz Toko Clock period 1 foLko ns t1 A 16 1 CSX UWE LWE OE setup to CLKO rising edge 1 ns t2 CSX and OE asserted low to D 15 0 driven read cycle 11 ns t3 CSX asserted low to DTACK driven 11 ns t4 A 16 1 hold from CSX rising edge 0 ns t5 DTACK falling edge to UWE LWE and CSX rising edge 0 ns t6 UWE L
428. nsmit FIFO is empty Endpoint 4 Maximum Packet Size Register REG 402Eh Default 08h Read Write 12 11 did 4 Max Packet Size bits 7 0 bits 7 0 Endpoint 4 Max Packet Size Bits 7 0 This register specifies the maximum packet size for endpoint 4 in units of 8 bytes default 64 bytes It can be read by the host through the endpoint 4 descriptor 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 125 Vancouver Design Center Revision Register REG 4030h Default 01h Read Only n a Chip Revision bits 7 0 bits 7 0 Chip Revision Bits 7 0 This register returns current silicon revision number of the USB client USB Status Register REG 4032h Default 00h Read Write n a 15 14 13 12 11 10 9 8 USB Endpoint 4 USB Endpoint 4 USB Endpoint 4 USB Endpoint 3 USB Endpoint 3 USB Endpoint 3 Suspend Control STALL NAK ACK STALL NAK ACK Endpoint 2 Valid 7 6 5 4 3 2 1 0 bit 7 Suspend Control If set this bit indicates that there is a pending suspend request Writing a 1 clears this bit and causes the S1D13A04 USB device to enter suspended mode bit 6 USB Endpoint 4 STALL The last USB IN token could not be serviced because the endpoint was stalled REG 4000h bit 4 set and was acknowledged with a STALL Writing a 1 clears this bit bit 5 USB Endpoint 4 NAK The last USB packet transmitted IN packet encountered a FIFO underrun condition and
429. nt Inc S1D13A04 Programming Notes and Examples Document Number X37A G 003 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website www mot com e Epson Research and Development Website www erd epson com 1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 23 Vancouver Design Center 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Europe Epson Hong Kong Ltd Epson Europe Electronics GmbH 20 F Harbour Centre Riesstrasse 15 25 Harbour Road 80992 Munich Germany Wanchai Hong Kong Tel 089 14005 0 Tel 2585 4600 Fax 089 14005 110 Fax 2827 4346 http www epson electronics de http www epson com hk 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com t
430. nted using the four signals nCAS 3 0 Each signal selects a byte on the 32 bit data bus For example nCASO selects bits D 7 0 and nCAS3 selects bits D 31 24 For a 16 bit data bus only nCAS 1 0 are used with nCASO selecting the low byte and nCAS1 selecting the high byte The SA 1110 can be configured to support little or big endian mode 2 1 2 Variable Latency lO Access Overview A data transfer is initiated when a memory address is placed on the SA 1110 system bus and a chip select signal nCS 5 3 is driven low If all byte enable signals nCAS 3 0 are driven low then a 32 bit transfer takes place If only nCAS 1 0 are driven low then a word transfer takes place through a 16 bit bus interface If only one byte enable is driven low then a byte transfer takes place on the respective data lines During a read cycle the output enable signal nOE is driven low A write cycle is specified by driving nOE high and driving the write enable signal nWE low The cycle can be lengthened by driving RDY high for the time needed to complete the cycle S1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center 2 1 3 Variable Latency lO Access Cycles The first nOE assertion occurs two memory cycles after the assertion of chip select nCS3 nCS4 or nCS5 Two memory cycles prior to the end of minimum nOE or nWE assertion RDF 1 memory cy
431. nter and to access S1D13A04 registers On Win32 systems the returned offsets correspond to a linear addresses within the callers address space Return Value TRUE non zero if the routine is able to locate an S1D13A04 pMem will contain the offset to the first byte of display memory pRegs will contain the address of the first 13A04 control register FALSE zero if an S1D13A04 is not located pMem and pRegs will be undefined If additional error information is required call halGetLastError Note 1 This routine must be called before any other HAL routine is called 2 For programs written for the S1D13A04 evaluation board an application may call this routine to obtain pointers to the registers and display memory and then perform all S1D13A04 accesses directly 3 This routine does not modify 1D13A04 registers or memory Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 114 Epson Research and Development Vancouver Design Center Boolean hallnitController UInt32 Flags Description Parameters Return Value S1D13A04 X37A G 003 05 This routine performs the initialization portion of the startup sequence Initialization of the S1D13A04 evaluation board consists of several steps Program the ICD2061A clock generator Set the initial state of the control Set the LUT to its default value Clear video memory All display memory and nearly every control register can or will be a
432. ntries currently in use there may be more values in internal pipeline stages Number of Free FIFO Entries Bits 4 0 These bits indicate the number of empty FIFO entries available If these bits return a 0 the FIFO is full BitBLT FIFO Not Empty Status This is a read only status bit When this bit 0 the BitBLT FIFO is empty When this bit 1 the BitBLT FiFO has at least one data To reduce system memory read latency software can monitor this bit prior to a BitBLT read burst operation bits 20 16 bit 6 The following table shows the number of words available in BitBLT FIFO under different status conditions Table 8 18 BitBLT FIFO Words Available bit 5 bit 4 1D13A04 X37A A 001 06 BitBLT FIFO Full Status REG 8004h Bit 4 BitBLT FIFO Half Full Status REG 8004h Bit 5 BitBLT FIFO Not Empty Status REG 8004h Bit 6 Number of Words available in BitBLT FIFO 0 0 0 0 1to6 710 14 0 0 1 0 1 1 1 1 1 15 to 16 BitBLT FIFO Half Full Status This is a read only status bit When this bit 1 the BitBLT FIFO is half full or greater than half full When this bit 0 the BitBLT FIFO is less than half full BitBLT FIFO Full Status This is a read only status bit When this bit 1 the BitBLT FIFO is full When this bit 0 the BitBLT FIFO is not full Revision 6 0 Hardware Functional Specification Issue Date 2003 05 01 Epson R
433. o read the packet then the last packet must be loaded into the FIFO REG 402Ah 0 LP actually sent No REG 4000h b6 0 The last packet was not successfully transmitted Yes EP4 ACK No REG 4032h b4 1 Advance pointer to next packet pBuffer FIFOSIZE Reduce remaining transfer size Remain FIFOSIZE n No Y Set Transmit FIFO Valid REG 402Ch 20h Clear EP4 interrupt status REG 4004h 10h Final packet of transfer was successfully transmitted EP4 Data Transmission Last packet Y short or ZLP gt Disable EP4 interrupt REG 4002h amp 10h Remain lt FIFOSIZE Clear EP4 interrupt status REG 4004h 10h No _ 1The last packet was a full packet i Advance to end of buffer pBuffer Remain Reduce remaining count to 0 Remain 0 This block is shown as a cleanup step It is not required Figure 10 5 Endpoint 4 Interrupt Handling Programming Notes and Examples Issue Date 2002 08 21 1D13A04 X37A G 003 05 Page 106 Epson Research and Development Vancouver Design Center Note In the diagram the variables pBuffer is a pointer to the local memory buffer containing the data to be transferred to the host controller Remain is an integer tracking the number of bytes still to be sent 10 4 Known Issues This section presents known iss
434. oes not meet these requirements 13A04CFG rounds up the value to the next allowable width The changed value is reported in the diagnostics portion of the window 1D13A04 X37A B 001 01 Page 16 Display Total Display Start Frame Rate Pixel Clock 1D13A04 X37A B 001 01 Epson Research and Development Vancouver Design Center It is recommended that the automatically generated Display Total values be used However manual adjustment may be used to improve the quality of the displayed image by fine tuning the horizontal and vertical display totals The display total equals the display period plus the non display period Refer to S1D13A04 Hardware Functional Specification document number X37A A 001 xx for a complete description of the Display Total settings Note If the horizontal or vertical display totals are set too small 13A04CFG will display a yellow warning message in the diagnostics portion of the window It is recommended that the automatically generated Display Start values be used However manual adjustment may be used to improve the quality of the displayed image by fine tuning the horizontal and vertical display start positions Refer to S1D13A04 Hardware Functional Specifi cation document number X37A A 001 xx fora complete description of the Display Start settings Note If the horizontal or vertical display start values are set to values that violate the S1D13A04 Hardware Functional Specificati
435. of a BitBLT operation may cause the 13A04 to stop responding and the system to hang Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 66 Epson Research and Development Vancouver Design Center 9 2 BitBLT Descriptions 1D13A04 X37A G 003 05 The S1D13A04 supports 13 fundamental BitBLT operations Write BitBLT with ROP Read BitBLT Move BitBLT in positive direction with ROP Move BitBLT in negative direction with ROP Transparent Write BitBLT Transparent Move BitBLT in positive direction Pattern Fill with ROP Pattern Fill with Transparency Color Expansion Color Expansion with Transparency Move BitBLT with Color Expansion Move BitBLT with Color Expansion and Transparency Solid Fill Most of the 13 operations are self completing This means once the BitBLT operation begins it completes without further assistance from the local CPU No data transfers are required to or from the local CPU Five BitBLT operations Write BitBLT with ROP Transparent Write BitBLT Color Expansion Color Expansion with Transparency Read BitBLT require data to be written to read from the BitBLT engine This data must be trans ferred one word 16 bits at a time This does not imply only 16 bit CPU instructions are acceptable If a system is able to separate one DWORD write into two WORD writes and the CPU writes the low word before the high word then 32 bit CPU instructions are acceptable Otherwise 16
436. of black and background color of white 1 Calculate the destination and source addresses upper left corner of the destination and source rectangles using the formula DestinationAddress y x ScreenStride x x BytesPerPixel 20 x 320 x 2 200 x 2 13200 3390h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride Display WidthInPixels x BytesPerPixels 640 for 16 bpp Source Address 156K 27000h Program the BitBLT Destination Start Address Register REG 8010h is set to 3390h Program the BitBLT Source Start Address Register REG 800Ch is set to 27000h 2 Program the BitBLT Width Register to 9 1 REG 8018h is set to 08h 3 Program the BitBLT Height Register to 16 1 REG 801Ch is set to OFh 4 Program the BitBLT ROP Code Color Expansion Register REG 8008h bits 19 16 are set to 7h 5 Program the BitBLT Operation Register to select the Move BitBLT with Color Ex pansion REG 8008h bits 3 0 are set to OBh 6 Program the BitBLT Foreground Color Register to select black in 16 bpp black 0000h REG 8024h is set to 0000h Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 89 Vancouver Design Center 7 Program the BitBLT Background Color Register to select white in 16 bpp white FFFFh REG 8024h is set to FFFFh 8 Program the BitBLT Color Format Select bit for 16 bpp operations REG 8000h bit 18 is set to 1 9 P
437. ogram the PIP Window X End Position so that PIP Window X End Position panel width y 1 The PIP X Start Position bits determine the horizontal position of the start of the PIP window in 0 and 180 SwivelView orientations These bits determine the vertical start position in 90 and 270 SwivelView For further information on defining the value of the X Start Position see Section 8 2 Picture In Picture Plus Examples on page 45 The register also increments differently based on the SwivelView orientation For 0 and 180 Swivel View the X Start Position is incremented by X pixels where X is relative to the current color depth For 90 and 270 SwivelView the X Start Position is incremented in 1 line increments Table 8 2 32 bit Address Increments for Color Depth Bits per pixel Color Depth Pixel Increment X 1 bpp 32 2 bpp 16 4 bpp 8 bpp 4 16 bpp 2 In SwivelView 0 these bits set the horizontal coordinates x of the PIP windows s left edge Increasing x moves the left edge towards the right in steps of 32 bits per pixel see Table 8 2 The horizontal coordinates start at pixel 0 Program the PIP Window X Start Position so that PIP Window X Start Position x 32 bits per pixel Note Truncate the fractional part of the above equation Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 42 Epson Research and Development Vancouve
438. oise LVTTL IO buffer 6mA 6mMA 3 3V Low noise LVTTL Output buffer 3mA 3mAO3 3V Low noise LVTTL IO buffer with input mask 8mA 3mMA 3 3V Test mode control input with pull down resistor typical value of 50KQ at 3 3V High Impedance Custom Cell Type LVTTL is Low Voltage TTL see Section 5 D C Characteristics on page 33 4 3 1 Host Interface Table 4 2 Host Interface Pin Descriptions i PFBGA TQFP15 RESET a Pin Name Type Pin Pin Cell State Description This input pin has multiple functions e For Generic 1 this pin is not used and should be connected to VSS e For Generic 2 this pin inputs system address bit O AO e For SH 3 SH 4 this pin is not used and should be connected to VSS e For MC68K 1 this pin inputs the lower data strobe ABO l D1 7 LI LDS e For MC68K 2 this pin inputs system address bit O AO e For REDCAP2 this pin is not used and should be connected to VSS e For DragonBall this pin is not used and should be connected to VSS See Table 4 8 Host Bus Interface Pin Mapping on page 31 for summary C6 A6 B6 E6 D5 A5 B5 C5 D4 6 AB 17 1 l Ad C4 B3 111 116 Cl System address bus bits 17 1 A3 C3 D 118 125 3 D2 D6 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 23 Vancouver Design Center Table 4 2 Host Interface Pin Descriptions
439. ol the panel It should be chosen to match the optimum frame rate of the panel See Section 10 Frame Rate Calculation on page 143 for details on the relationship between PCLK and frame rate Some flexibility is possible in the selection of PCLK Firstly panels typically have a range of permissible frame rates Secondly it may be possible to choose a higher PCLK frequency and tailor the horizontal non display period to bring down the frame rate to its optimal value The source clock options for PCLK may be selected as in the following table Table 7 3 PCLK Clock Selection Source Clock Options PCLK Selection MCLK REG 08h bits 7 0 00h MCLK 2 REG 08h bits 7 0 10h MCLK 3 REG 08h bits 7 0 20h MCLK 4 REG 08h bits 7 0 30h MCLK 8 REG 08h bits 7 0 40h BCLK REG 08h bits 7 0 01h BCLK 2 REG 08h bits 7 0 11h BCLK 3 REG 08h bits 7 0 21h BCLK 4 REG 08h bits 7 0 31h BCLK 8 REG 08h bits 7 0 41h CLKI REG 08h bits 7 0 02h CLKI 2 REG 08h bits 7 0 12h CLKI 3 REG 08h bits 7 0 22h CLKI 4 REG 08h bits 7 0 32h CLKI 8 REG 08h bits 7 0 42h CLKI2 REG 08h bits 7 0 03h CLKI2 2 REG 08h bits 7 0 13h CLKI2 3 REG 08h bits 7 0 23h CLKI2 4 RREG 08h bits 7 0 33h CLKI2 8 REG 08h bits 7 0 43h Revision 6 0 1D13A04 X37A A 001 06 Epson Research and Development Page 86 Vancouver Design Center There is a r
440. oller for display buffer writes Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 28 Epson Research and Development Vancouver Design Center 6 3 LCD Power Sequencing 1D13A04 X37A G 003 05 The S1D13A04 requires LCD power sequencing the process of powering on and powering off the LCD panel LCD power sequencing allows the LCD bias voltage to discharge prior to shutting down the LCD signals preventing long term damage to the panel and avoiding unsightly lines at power on power off Proper LCD power sequencing for power off requires a delay from the time the LCD power is disabled to the time the LCD signals are shut down Power on requires the LCD signals to be active prior to applying power to the LCD This time interval depends on the LCD bias power supply design For example the LCD bias power supply on the S5U13A04B00C Evaluation Board requires 0 5 seconds to fully discharge Other power supply designs may vary This section assumes the LCD bias power is controlled through GPIOO The 1D13A04 GPIO pins are multi use pins and may not be available in all system designs For further information on the availability of GPIO pins see the D13A04 Hardware Functional Specification document number X37A A 001 xx Note This section discusses LCD power sequencing for passive and TFT non HR TFT pan els only For further information on LCD power sequencing the HR TFT see Connect ing to the Sharp
441. ommand prompt change to the directory 13A 04cfg exe was installed to and type the command 13A 04cfg The basic procedure for using 13A04CFG is 1 Start 13A04CFG as described above 2 Open an existing file to serve as a starting reference point this step is optional 3 Modify the configuration For specific information on editing the configuration see 13A04CFG Configuration Tabs on page 6 4 Save the new configuration The configuration information can be saved in two ways as an ASCII text file or by modifying an executable image on disk Several ASCII text file formats are supported Most are formatted C header files used to build display drivers or standalone applications Utility files based on the Hardware Abstraction Layer HAL can be modified directly by 13A04CFG 13A04CFG Configuration Program S1D13A04 Issue Date 01 10 19 X37A B 001 01 Page 6 Epson Research and Development Vancouver Design Center 13A04CFG Configuration Tabs 13A04CFG displays a series of tabs which can be selected at the top of the main window Each tab allows the configuration of a specific aspect of S1D13A04 operation The following sections describe the purpose and use of each of the tabs General Tab gt 1D13A04 Configuration Utility File Help Memory mapped locations Decode Addresses _ HI addresses Epson 55U13404B00B B00C Motorola IDP68000 C User Defined Motorola IDP68030 Motorola DragonBall Motorola DSP56654 R
442. on 2 2 0 ee eee ee ee es 6 1 PCI Bus Support Sr 6 2 Direct Host Bus Interface Support 6 3 S1D13A04 Embedded Memory En 6 4 Adjustable LCD Panel Negative Power Supply 6 5 Adjustable LCD Panel Positive Power Supply 6 6 Software Adjustable LCD Backlight Intensity Support Using F PWM 6 7 LCD Panel Support 6 7 1 Direct LCD Connector 0 0 0 0 0 008 6 7 2 Extended LCD Connector 0 0 00 000 6 8 USB Support 6 8 1 USBIRQSupport 0 2 e Clock Synthesizer and Clock Options 7 1 Clock Programming RETErENCOS irei AA He ee A ee oe i ee ee A 8 1 Documents 8 2 Document Sources Parts LIST ii a poe eee oa a dick Sy ten a ae See A Ay RO a ve Schematics 0 un ica pede ndo ia a As Board Layout lt lt sa s tacna A A A AA a a ae Sales and Technical Support 2 2 0 2 eee eee ee 12 1 Epson Companion Chips S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 Page 3 S1D13A04 X37A G 004 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 02 Issue Date 02 01 28 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Configuration DIP Switch Settings o o e e 10 Table 3 2 JumperSummary 2 2 00 0 i e e E a i ee 11 Table 4 1 CPU Inte
443. on 13A04CFG will display a yellow warning message in the diagnostics portion of the window The Frame Rate in Hz is calculated and displayed based on the current settings as selected on the various tabs If the resulting Frame Rate is not acceptable adjust the settings to change the frame rate Panel dimensions are fixed therefore frame rate can only be adjusted by changing either the PCLK frequency or display total values Select the desired Pixel Clock in MHz from the drop down list The range of frequencies displayed is dependent on the PCLK source and divide settings as selected on the Clocks tab 13A04CFG Configuration Program Issue Date 01 10 19 Epson Research and Development Vancouver Design Center HRTC FPLINE pixels Start pos Pulse Width VRTC FPFRAME lines Start pos Pulse width Predefined Panels 13A04CFG Configuration Program Issue Date 01 10 19 Page 17 These settings allow fine tuning of the TFT line pulse parameters Refer to S1D 3A04 Hardware Functional Specification document number X37A A 001 xx for a complete description of the FPLINE pulse settings Specifies the delay in pixels from the start of the horizontal non display period to the leading edge of the FPLINE pulse Specifies the width in pixels of the horizontal sync signal FPLINE These settings allow fine tuning of the frame pulse parameters Refer to S1D 3A04 Hardware Functional Specification document number X
444. on 6 0 Page 162 Epson Research and Development Vancouver Design Center 17 References The following documents contain additional information related to the S1D13A04 Document numbers are listed in parenthesis after the document name All documents can be found at the Epson Research and Development Website at www erd epson com 1D13A04 X37A A 001 06 13A04CFG Configuration Utility Users Manual X37A B 001 xx 13A04PLAY Diagnostic Utility Users Manual X37A B 002 xx 13A04BMP Demonstration Program User Manual X37A B 003 xx S1D13A04 Product Brief X37A C 001 xx S1D13A04 Wind River WindML v2 0 Display Drivers X37A E 002 xx S1D13A04 Linux Console Driver X37A E 004 xx S1D13A04 QNX Photon v2 0 Display Drivers X37A E 005 xx S1D13A04 Windows CE v3 x Display Drivers X37A E 006 xx Interfacing to the Toshiba TMPR3905 3912 Microprocessor X37A G 002 xx S1D13A04 Programming Notes And Examples X37A G 003 xx S5U13A04B00C Rev 1 0 Evaluation Board User Manual X37A G 004 xx Interfacing to the PC Card Bus X37A G 005 xx S1D13A04 Power Consumption X37A G 006 xx Interfacing to the NEC VR4102 VR4111 Microprocessors X37A G 007 xx Interfacing to the NEC VR4181 Microprocessor X37A G 008 xx Interfacing to the Motorola MPC821 Microprocessor X37A G 009 xx Interfacing to the Motorola MCF5307 Coldfire Microprocessors X37A G 010 xx Connecting to the Sharp HR TFT Panels X37A G 011 xx Interfacing to the Motorola MC68VZ328 Dragonba
445. on Jumper JP4 Location JP5 GPIOO Selection JP5 selects the function of the GPIOO signal Position 1 2 GPIOO used to control the LCD bias power supplies for STN panels Position 2 3 GPIOO used as the PS signal when the S1D13A04 is configured for HR TFT panel type Co Coes JP5 S BB i GPIOO HR TFT PS signal Figure 3 6 Configuration Jumper JP5 Location S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Epson Research and Development Page 14 Vancouver Design Center 4 CPU Interface 4 1 CPU Interface Pin Mapping Table 4 1 CPU Interface Pin Mapping Motorola A Hitachi Motorola Motorola Motorola MC68EZ328 1D13A04 Pin Name Generic 1 Generic 2 lt a SH 4 MC68K 1 MC68K 2 REDCAP2 MC68VZ328 DragonBall AB 17 1 A 17 1 A 17 1 A 17 1 A 17 1 A 17 1 A 17 1 A 17 1 ABO Ao AO Ao LDS AO Ao Ao DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 CS External Decode CSn External Decode CSn CSX M R External Decode CLKI BUSCLK BUSCLK CKIO CLK CLK CLK CLK BS Connected to HIOVpp BS AS AS Connected to HIOVpp Connected a Connected to RD WR RD1 i HIOVp 3 ROWRE R W R W RW HlOVpp3 Connected aE RD RDO RD RD to HIOVpp SIZ1 OE OE Connected Ej E WEO WEO WE WEO to HIOVpp SIZO EB1 LWE WE1 WE1 BHE
446. on Research and Development Vancouver Design Center The NEC VR4102 VR4111 microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 Host Bus Interface no glue logic is required to interface the S1D13A04 and the NEC VR4102 VR4111 A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle BS bus start and RD WR are not used by the Generic 2 Host Bus Interface and should be tied high connected to IO Vpp The following diagram shows a typical implementation of the VR4102 VR4111 to S1D13A04 interface NEC VR4102 VR4111 S1D13A04 WR gt WEO SHB gt WE1 RD gt RDA LCDCS P gt CS ull up To LCDRDY WAIT ADD18 gt M R System RESET gt RESET ADD 17 0 gt AB 17 0 DAT 15 0 e gt DB 15 0 BUSCLK gt CLKI lOVpp BS RD WR Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of VR4102 VR4111 to SIDI3A04 Interface 1D13A04 X37A G 007 01 Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 13 Vancouver D
447. only one pixel In this case it is always in the low byte The number of WORD writes the BitBLT engine expects for 8 bpp color depths is shown in the following formula WORDS BitBLTWidth 1 DestinationPhase 2 x BitBLTHeight The BitBLT engine requires this number of WORDS to be sent from the local CPU before it will end the Write BitBLT operation Example 19 Read 100 x 20 pixels at the screen coordinates x 25 y 38 and save to system memory Assume a display of 320x240 at a color depth of 8 bpp 1 Calculate the source address upper left corner of the screen BitBLT rectangle using the formula SourceAddress y X ScreenStride x x BytesPerPixel 38 x 320 25 x 1 12185 2F99h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixels 320 for 8 bpp Program the BitBLT Source Start Address Register REG 800Ch is set to 2F99h 2 Program the BitBLT Width Register to 100 1 REG 8018h is set to 63h 99 deci mal 3 Program the BitBLT Height Register to 20 1 REG 801Ch is set to 13h 19 deci mal Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 91 Vancouver Design Center 10 Program the Destination Phase in the BitBLT Destination Start Address Register In this example the data is WORD aligned so the destination phase is 0 REG 8010h is set to 00h Program the BitBLT Operation
448. oordinates X 105 Y 20 using a 320x240 display at a color depth of 16 bpp In the following example the coordinates of the source and destination rectangles inten tionally overlap 1 Calculate the source and destination addresses lower right corners of the source and destination rectangles using the following formula SourceAddress y Height 1 x ScreenStride x Width 1 x BytesPerPixel 10 101 1 x 320 x 2 100 9 1 x 2 70616 113D8h DestinationAddress Y Height 1 x ScreenStride X Width 1 x BytesPerPixel 20 101 1 x 320 x 2 105 9 1 x 2 77026 12CE2h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixel 640 for 16 bpp Program the BitBLT Source Start Address Register REG 800Ch is set to 113D8h Program the BitBLT Destination Start Address Register REG 8010h is set to 12CE2h Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 79 Vancouver Design Center 2 Program the BitBLT Width Register to 9 1 REG 8018h is set to 08h 3 Program the BitBLT Height Register to 101 1 REG 801Ch is set to 64h 100 deci mal 4 Program the BitBLT Operation Register to select the Move BitBLT in Negative Di rection with ROP REG 8008 bits 3 0 are set to 3h 5 Program the BitBLT ROP Code Register to select Destination Source REG 8008h bi
449. or 16 Bit Panel A C Timing o e 71 S1D13A04 Revision 6 0 X37A A 001 06 Page 10 Figure 6 27 Figure 6 28 Figure 6 29 Figure 6 30 Figure 6 31 Figure 6 32 Figure 6 33 Figure 6 34 Figure 6 35 Figure 6 36 Figure 6 37 Figure 7 1 Figure 8 1 Figure 8 2 Figure 11 1 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 12 6 Figure 12 7 Figure 12 8 Figure 13 1 Figure 13 2 Figure 13 3 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 16 1 Figure 16 2 1D13A04 X37A A 001 06 Epson Research and Development Vancouver Design Center Generic TFT Panel Timing 18 Bit TFT Panel Timing 2 2 0 0 00 2 0 00000000000 73 TET A Ce Timing cc hee gis glint God ae a San a Gages ay ges ee ed te Eek red ays 74 160x160 Sharp Direct HR TFT Panel Horizontal Timing 76 160x160 Sharp Direct HR TFT Panel Vertical Timing 78 320x240 Sharp Direct HR TFT Panel Horizontal Timing 80 320x240 Sharp Direct HR TFT Panel Vertical Timing 81 Data Signal Rise and Fall Time 2 2 2 ee ee 82 Differential Data Jitter sasa iea ee 82 Differential to EOP Transition Skew and EOP Width 82 Receiver Jitter Tolerance ci orein ee 83 Clock Select iveco Us ate a Big E eel eG Gree 87 Display Data Byte Word Swap 2 2 2 111 PWM Clock Block Diagram
450. ormal Non Burst Bus Transactions S1D13A04 X37A G 010 01 A data transfer is initiated by the bus master by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e R W set high for read cycles and low for write cycles e TT 1 0 Transfer Type Signals provides more detail on the type of transfer being attempted e TIP Transfer In Progress asserts whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 MCF5307 Memory Read Cycle illustrates a typical memory read cycle on the MCF5307 system bus sexo dv LJ LI LJ LI LI LU LI TS TA TIP aB XX X Rw XX SIZ 1 0 TT 1 0 X Dero SORKIN KKK Sample when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts
451. ort or www erd epson com Interfacing to the NEC VR4181A Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 008 01 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e NEC Electronics Inc NEC VR4181A Target Specification Revision 0 5 9 11 98 Epson Research and Development Inc S D13A04 Hardware Functional Specification document number X37A A 001 xx e Epson Research and Development Inc S5UI3A04B00C Rev 1 0 Evaluation Board User Manual document number X37A G 004 xx Epson Research and Development Inc S1IDI13A04 Programming Notes and Examples document number X37A G 003 xx 6 2 Document Sources e NEC Electronics Inc Website www necel com e Epson Research and Development Website www erd epson com S1D13A04 Interfacing to the NEC VR4181A Microprocessor X37A G 008 01 Issue Date 01 10 12 Epson Research and Development Page 17 Vancouver Design Center 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk 7 2 NEC Electronics Inc NEC Electronics Inc U S A Corporate Headquarters 2880 Sc
452. ory and register accesses In this example the DTACK signal is made available for the S1D13A04 Alternately the S1D13A04 can guarantee a maximum cycle length that the Dragonball VZ handles by inserting software wait states see Section 4 2 2 MC68VZ328 Chip Select and Pin Configuration on page 13 A single resistor is used to speed up the rise time of the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68VZ328 to S1D13A04 using the Dragonball host bus interface For further information on the Dragonball Host Bus interface and AC Timing refer to the S D13A04 Hardware Functional Specification document number X37A A 001 xx MC68VZ328 S1D13A04 A 17 0 gt AB 17 0 D 15 0 gt DB 15 0 CSB1 gt CSH A18 gt M R IO V IO Vpp ZBP T BS 1K RD WR DTACK WAIT UWE gt WE1 LWE WEO OE RD CLKO CLKI System RESET gt p RESET Note When connecting the S1D13A04 RESET pin the system designer should be aware of all conditions that may reset the S1D13A04 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MC68VZ328 to SIDI3A04 Interface Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 012 01 Page 12 Epson Research
453. oshiba MIPS TMPR3905 12 Processor http www toshiba com taec nonflash indexproducts html Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 10 12 S1D13A04 X37A G 002 01 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors X37A G 002 01 Issue Date 01 10 12 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the PC Card Bus Document Number X37A G 005 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other tra
454. ost BitBLTs have a source of data for the BitBLT and many also incorporate a pattern The pattern source and destination operands are combined using logical AND OR XOR and NOT operations The combining process is called a Raster Operation ROP and results in the final pixel data to be written to the destination address The S1D13A04 2D BitBLT engine supports a total of sixteen ROPs and works at 8 bpp and 16 bpp color depths This section describes the BitBLT registers and provides some sample BitBLT operations 9 1 Registers The S1D13A04 BitBLT registers are located 8000h bytes from the start of S1D13A04 address space The registers are labelled according to their byte offset as REG 8000h through REG 8024h The following is a description of all BitBLT registers BitBLT Control Register REG 8000h Default 00000000h Read Write Color Dest Source Format Linear Linear Select Select Select 18 17 16 Color Format Select The Color Format Select bit indicates to the BitBLT engine what color depth to assume for the BitBLT operation The BitBLT engine uses this information to set the step size for internal counters When this bit 0 8 bpp is selected and when this bit 1 16 bpp is selected Destination Linear Select The Destination Linear Select bit determines how the BitBLT destination address pointer is updated when the BitBLT reaches the end of a row When the end of a row is reached and rectangular is selected t
455. ot modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 QNX Photon v2 0 Display Driver X37A E 005 01 Issue Date 01 10 19 Epson Research and Development Page 3 Vancouver Design Center QNX Photon v2 0 Display Driver The Photon v2 0 display driver for the S1D13A04 LCD USB Companion Chip is intended as reference source code for OEMs developing for QNX platforms The driver package provides support for 8 and 16 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13A04 Source code modification is required to provide a smaller driver for mass production The current revision of the driver is designed for use with either QNX RTP or QNX4 from the latest product CD Dec 99 The Photon v2 0 display driver is designed around a common configuration include file called S1D13A04 h which is generated by the configuration utility 13 A04CFG This design allows for easy customization of display type clocks decode addresses rotation et
456. ott Blvd Santa Clara CA 95050 8062 USA Tel 800 366 9782 Fax 800 729 9288 http www necel com North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the NEC VR4181A Microprocessor Issue Date 01 10 12 S1D13A04 X37A G 008 01 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Interfacing to the NEC VR4181A Microprocessor X37A G 008 01 Issue Date 01 10 12 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the Motorola MPC82x Microprocessor Document Number X37A G 009 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document E
457. ouver Design Center Vertical Panel Invert Configuration Description Color Depth Panel Swivel View Advanced Display Start Address Display Stride 13A04CFG Configuration Program Issue Date 01 10 19 Page 9 When this box is checked pixel doubling in the vertical direction is enabled Note that the S1D13A04 does not support vertical pixel doubling at a color depth of 1 bpp The S1D13A04 can invert the display data going to the LCD panel When this box is checked video data is inverted Display data is inverted after the Look Up Table which means colors are truly inverted This field allows the user to enter a description for a particular configuration This field is saved in the HAL information and is displayed when a HAL based utility is run Sets the initial color depth on the LCD panel If there is insufficient display buffer for the selected width and height then a warning is displayed in the diagnostic area The S1D13A04 SwivelView feature is capable of rotating the image displayed on an LCD panel 90 180 or 270 in a counter clockwise direction This setting determines the initial orientation of the panel These settings allow fine tuning of the start address and stride The start address defines the offset into the display buffer video memory of the pixel which will be displayed in the top left corner of the panel Stride defines the number of bytes required to step from the first pixel on one r
458. ouver Design Center Vertical Display Period Start Position Register REG 38h Default 00000000h Read Write bits 9 0 Vertical Display Period Start Position Bits 9 0 These bits specify the Vertical Display Period Start Position for panels in 1 line resolution For passive LCD panels these bits must be set to 00h For TFT panels VDPS is calculated using the following formula VDPS REG 38h bits 9 0 Note This register must be programmed such that the following formula is valid VDPS VDP lt VT 2See Section 6 4 Display Interface on page 56 FPFRAME Register REG 8Ch Default 00000000h Read Write FPFRAME FPFRAME Pulse Width na Polarity n a bits 2 0 23 22 21 20 19 18 17 16 FPFRAME Pulse Start Position bits 9 0 7 6 5 4 3 2 1 0 bit 23 FPFRAME Pulse Polarity This bit selects the polarity of the vertical sync signal For passive panels this bit must be set to 1 For TFT panels this bit is set according to the horizontal sync signal of the panel typically FPFRAME SPS or DY When this bit 0 the vertical sync signal is active low When this bit 1 the vertical sync signal is active high bits 18 16 FPFRAME Pulse Width Bits 2 0 These bits specify the width of the panel vertical sync signal in 1 line resolution The ver tical sync signal is typically FPFRAME SPS or DY depending on the panel type REG 3Ch bits 18 16 FPFRAME Pulse Width in number of lines 1 Note See Section 6 4 Display Interf
459. ovides additional circuits for generating some of these voltages 3 1 1 Gray Scale Voltages for Gamma Correction The standard gray scale voltages can be generated using a precise resistor divider network as described in Section 2 1 1 Gray Scale Voltages for Gamma Correction on page 8 Alternately they can be generated using a Sharp gray scale IC The Sharp IR3E203 elimi nates the large resistor network used to provide the 10 gray scale voltages and combines their function into a single IC The S1D13A04 output signal REV is used to alternate the gray scale voltages and connects to the SW input of the IR3E203 IC The COM signal is used in generating the gate driver panel AC voltage Vcom and is explained in Section 3 1 4 AC Gate Driver Power Supplies on page 15 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation shows the circuit that generates the gray scale voltages using the Sharp IR3E203 IC SHARP IR3E203 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation S1D13A04 Connecting to the Sharp HR TFT Panels X37A G 011 01 Issue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 3 1 2 Digital Analog Power Supplies The digital power supply VSHD must be connected to a 3 3V supply The analog power supply VSHA must be connected to a 5 0V supply 3 1 3 DC Gate Driver Power Supplies See Section 2 1 3 DC Gate Driver Power Supplies on p
460. ow to the first pixel on the next row i e 160 pixel wide display at 16 bpp requires 320 bytes per horizontal row This option sets the start address for the main window of the panel Typically the start address is set to zero This option sets the stride for the main window of the panel To set the stride equal to the size of the display select the auto box To increase the stride uncheck the auto box and enter the desired stride Note The stride value must be greater than or equal to the number of bytes required by one line of display memory 1D13A04 X37A B 001 01 Page 10 Clocks Tab gt 51D13A04 Configuration Utility File Help General Preferences ft si Panel Panel Power CLK CLKI MHz PCLK y Timing 50 000 Source feki J Actual 49 999 MHz Divide Auto y Timing 6 250 M owe JE CLKI2 MHz iming 6 250 MHz gt Timing 50 000 BULK Actual 49 999 MHz eee ESA gt E y a NOTE Selection Timing 50 000 MHz Divide witraffect the BCLK Divide allowable choices for MCLK panel frame rates After XA O making changes make Source BCLK sure to go to Panel ida i j section for the change to o 11 take effect Timing 50 000 MHz egisters Direct Epson Research and Development Vancouver Design Center PWMCLK Force High I Enable Forc
461. ower Supply RD 0412 Negative LCD Bias Power Taiyo Yuden Xentek Negative 33 1 me EPNOQI Supply Power Supply EPNOO1 40 1 U11 Nozaroa T nyLogic HST inverter SOT23 Fairchild NC7ST04 5 package 41 1 U12 LT1118CST 2 5 2 5V fixed volt reg SOT 223 near vere reas 3 3V fixed volt reg 3 Lead Linear Technology LT1117CM 42 1 U13 LT1117CM 3 3 PlasticDD 33 43 3 U14 U16 74HCT244 Buffer SO 20 package TI74HCT244 44 4 U17 EPF6016TC14 144 pin TQFP FLEX6000 Altera EPF6016TC144 2 4 2 FPGA 45 1 U18 EPC1441PC8 8 pin DIP pckg OTP EPROM Altera EPC1441PC8 socketed 46 1 U19 74HCT125 Buffer SO 14 package TI74HCT125 47 1 Y1 14 31818MHz PEREN es Fox HC EOX FoxS 143 20 14 31818MHz 48 1 Y2 48MHz Osc SMD 48MHz oscillator Epson SG 615PH 48 000MHz 4 pin narrow DIP screw 49 1 U18 Socket machine socket Socket for U18 50 5 JP1 JP5 Shunts Jumper Shunts 51 1 Z1 PCI Bracket POI bracket with slotTor USB Hansen Industries Type B connector Use to Assemble PCI bracket 52 2 Z2 Screw Screw pan head 4 40 x 1 4 onto PCB board S5U13A04B00C Rev 1 0 Evaluation Board User Manual Issue Date 02 01 28 1D13A04 X37A G 004 02 Vancouver Design Center Epson Research and Development Page 26 10 Schematics T T E wa
462. p Awww epson com hk 1D13A04 X37A G 003 05 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epson electronics de Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology 8 Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center READ ONLY CONFIGURATION REGISTERS Product Code Revision Code Display Buffer Size 12 11 PANEL CONFIGURATION REGISTERS Panel Data Format Select 7 Pixel Doubling Horiz Pixel Doubling Vertical Display Blank VNDP Status RO LOOK UP TABLE REGISTERS LUT Write Address CNF 6 4 Status Product Code 5 4 MCLK Divide Select 5 4 21 20 Page 1 Reserved CNF 2 0 Status Revision Code 1 0 18 17 Reserved 19 18 17 16 PCLK Divide Select a PCLK Source Select 5 4 3 1 Color Mono Panel Sele
463. panion Chip Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Document Number X37A G 012 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor X37A G 012 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A INTFOQUCIION era a ey Sale a Bate NOA aes a ee eR ae Bal Bie 7 2 Interfacing to the MC68VZ328 8 2 1 The MC68VZ328 System Bus ee ee 8 2 2 Chip Select Module 2 E a ee 8 3 S1D13A04 Host Bus Interface 9 3 1 Host Bus Interface Pin Mapping 2 00 2 9 3 2 Host Bus Interface Sig
464. pe the following 13A04bmp bmpfile bmp Note To display a bmpfile using SwivelView configure 13A04bmp exe for the selected SwivelView mode using the configuration program 13A04CFG For further information on 13A04CFG see the 3A04CFG User Manual document number X37A B 001 xx Comments e 13A04BMP displays only Windows BMP format images e A 24 bit true color bitmap is displayed at a color depth of 16 bit per pixel e Only the green component of the image is seen on a monochrome panel e 13A04BMP does not perform any image translations The image to display must be the desired dimensions and color depth S1D13A04 13A04BMP Demonstration Program X37A B 003 01 Issue Date 01 10 04 EPSON 1D13A04 LCD USB Companion Chip Wind River WindML v2 0 Display Drivers Document Number X37A E 002 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective
465. per addresses must be fully decoded 4 4 MCF5307 Chip Select Configuration Chip Selects 0 and 1 have programmable block sizes from 64K bytes through 2G bytes However these chip selects would normally be needed to control system RAM and ROM Therefore one of the IO chip selects CS2 through CS7 is required to address the entire address space of the S1D13A04 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the S1D13A04 The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write protect e AM 0 enable alternate bus master access to the S1D13A04 e C I 1 disable CPU space access to the 1D13A04 e SC 1 disable Supervisor Code space access to the S1D13A04 e SD 0 enable Supervisor Data space access to the S1D13A04 e UC 1 disable User Code space access to the S1D13A04 e UD 0 enable User Data space access to the S1D13A04 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Inte
466. ping The following table shows the functions of each Host Bus Interface signal Table 3 1 Host Bus Interface Pin Mapping 1D13A04 Pin Names Motorola MC68VZ328 AB 17 0 A 17 0 DB 15 0 D 15 0 WE1 UWE CS CSx M R External Decode CLKI CLKO BS Connect to lOypp from the S1D13A04 RD WR Connect to IO ypp from the S1D13A04 RD OE WEO LWE WAIT DTACK RESET System RESET Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor Issue Date 01 10 12 S1D13A04 X37A G 012 01 Page 10 Epson Research and Development Vancouver Design Center 3 2 Host Bus Interface Signals 1D13A04 X37A G 012 01 The Host Bus Interface requires the following signals CLKI is a clock input required by the S1D13A04 Host Bus Interface as a source for its internal bus and memory clocks This clock is typically driven by the host CPU system clock For this example CLKO from the Motorola MC68VZ328 is used for CLKI The address inputs AB 17 0 and the data bus DB 15 0 connect directly to the MC68VZ328 address A 17 0 and data bus D 15 0 respectively CNF4 must be set to one to select big endian mode Chip Select CS must be driven low by one of the Dragonball VZ chip select outputs from the chip select module whenever the S1D13A04 is accessed by the MC68VZ328 M R memory register selects between memory or register accesses This signal is generated by the external address decode
467. play Period REG 24h bits 6 0 1 x 8 Er For STN panels REG 28h bits 9 0 22 HDP H Display P P T S orizontal Display Period Start Position For TFT panels REG 28h bits 9 0 5 s HPS FPLINE Pulse Start Position REG 2Ch bits 9 0 1 HPW FPLINE Pulse Width REG 2Ch bits 22 16 1 VT Vertical Total REG 30h bits 9 0 1 VDP Vertical Display Period REG 34h bits 9 0 1 VDPS Vertical Display Period Start Position REG 38h bits 9 0 Lines HT VPS FPFRAME Pulse Start Position REG 2Ch bits 9 0 VPW FPFRAME Pulse Width REG SCh bits 18 16 1 1 For passive panels the HDP must be a minimum of 32 pixels and must be increased by multiples of 16 For TFT panels the HDP must be a minimum of 8 pixels and must be increased by multiples of 8 2 The following formulas must be valid for all panel timings HDPS HDP lt HT VDPS VDP lt VT Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 Revision 6 0 X37A A 001 06 Page 58 6 4 1 Generic STN Panel Timing Epson Research and Development Vancouver Design Center VT 1 Frame VPW FPFRAME ee FPLINE MOD DRDY FPDAT 17 0 Lf HT 1 Line HPS HPW FPLINE FPSHIFT 1P CLK MOD DRDY HDPS a FPDAT 17 0 HOCE
468. pment Inc S1D13A04 Programming Notes and Examples document number X37A G 003 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Inc Website www mot com e Epson Research and Development Website www erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 010 01 Page 18 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor 1D13A04 X37A G 010 01 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan
469. position is incremented by y pixels where y is relative to the current color depth Table 8 14 32 bit Address Increments for Color Depth Color Depth Pixel Increment y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 Depending on the color depth some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels Note These bits have no effect unless the PIP Window Enable bit is set to 1 REG 10h bit 19 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 S1D13A04 X37A A 001 06 Page 110 Epson Research and Development Vancouver Design Center 8 3 7 Miscellaneous Registers Special Purpose Register REG 60h Default 00000000h Read Write n a Reserved 27 26 Latch Byte Select bits 23 16 Reserved These bits must be set to 0 bit 7 2D Byte Swap This bit enables the word data sent to read from the 2D BitBLT port to be swapped byte O and byte 1 are swapped Note This bit is only used when the S1D13A04 is configured for Big Endian CNF4 1 at RESET If configured for Little Endian CNF4 0 this bit has no effect bit 6 Display Data Word Swap The display pipe fetches 32 bits of data from the display buffer This bit enables the lower 16 bit word and the upper 16 bit word to be swapped before sending them to the LCD dis play If the Display Data Byte Swap bit is also enabled then the byte order of the fetch
470. pson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction secs ak A A ee ee a a A ate 7 2 Interfacing to the MPC82x 2 2 aaa 8 2 1 The MPC8xxSystemBus 2 005 2 ee 8 2 2 MPC8xx Bus Overview d h a ela E a aa a a e al 8 2 2 1 Normal Non Burst Bus Transactions el 9 222 Burst Cy CES onire al A A ae Ay wg IA ghee e tye 10 2 3 Memory Controller Module E E A 2 3 1 General Purpose Chip Select Module le GPCM E AR Ati 11 2 3 2 User Programmable Machine UPM o o e 12 3 S1D13A04 Host Bus Interface lt lt es 13 3 1 Host Bus Interface Pin Mapping 13 3 2 Host Bus Interface Signals 2 a a a eee 14 4 MPC82x to S1D13A04 Interface o 15 4 1 Hardware Description Ls Ae ee US 42 MPC821ADS Eval
471. pt status bit 0 write corresponding interrupt status bit unchanged 1 write corresponding interrupt status bit cleared to zero These bits must always be cleared via a write to this register before first use This will ensure that any changes on input pins during system initialization do not generate erroneous interrupts The interrupt bits are used as follows bit 6 USB Host Connected Indicates the USB device is connected to a USB host bit 5 Reserved Must be set to 0 bit 4 Reserved Must be set to 0 bit 3 Reserved Must be set to 0 bit 2 Reserved Must be set to 0 bit 1 USBRESET Indicates the USB device is reset using the RESET pin or using the USB port reset bit O Reserved Must be set to 0 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 133 Vancouver Design Center Interrupt Control Status Clear Register 1 REG 404Ch Default 00h Read Write n a 15 14 13 12 11 10 9 8 USB Host Device n a Disconnected Reserved Configured Reserved Reserved Reserved INT X 6 5 4 3 2 1 0 On reads these bits represent the interrupt status for interrupts caused by high to low transitions on the corresponding signals 0 read no high to low event detected on the corresponding signal 1 read high to low event detected on the corresponding signal On writes these bits clear the corresponding interrupt status bit O write corr
472. puts are forced low Note Memory writes are possible during power save mode because the S1D13A04 dynami cally enables the memory controller for display buffer writes Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 27 Vancouver Design Center 6 2 Registers 6 2 1 Power Save Mode Enable Power Save Configuration Register REG 14h Default 00000010h Read Write 28 2 26 Power Save Mode Enable Control 0 The Power Save Mode Enable bit initiates Power Save Mode when set to 1 Setting the bit to O disables Power Save Mode and returns the S1D13A04 to normal mode At reset this bit is set to 1 Note Enabling disabling Power Save Mode requires proper LCD Power Sequencing See Sec tion 6 3 LCD Power Sequencing on page 28 6 2 2 Memory Controller Power Save Status Power Save Configuration Register REG 14h Default 00000010h Read Write 28 27 26 16 Power Direct Save HR TFT Mode GPO Enable Control 0 The Memory Controller Power Save Status bit is a read only status bit which indicates the power save state of the S1D13A04 SRAM interface When this bit returns a 1 the SRAM interface is powered down and the memory clock source may be disabled When this bit returns a 0 the SRAM interface is active This bit returns a O after a chip reset Note Memory writes are possible during power save mode because the S1D13A04 dynami cally enables the memory contr
473. quire any CPU assis tance While the BitBLT engine is busy the CPU can do other tasks To test before each BitBLT operation perform the following 1 Wait for the current BitBLT operation to finish Poll the BitBLT Busy Status bit REG 8004h bit 0 until it returns a 0 2 Program and start the new BitBLT operation 3 Continue with program execution CPU and BitBLT engine work independently This approach can pose problems when mixing CPU and BitBLT access to the display buffer For example if the CPU writes a pixel while the BitBLT engine is running and the CPU writes a pixel before the BitBLT finishes the pixel may be overwritten by the BitBLT To avoid this scenario always assure no BitBLT is in progress before accessing the display buffer with the CPU or don t use the CPU to access the display buffer at all S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 93 Vancouver Design Center 9 4 S1D13A04 BitBLT Known Limitations The S1D13A04 BitBLT engine has the following limitations e The 2D Accelerator Data Memory Mapped register must not be accessed except during BitBLT operations Read from the register only during Read BitBLT operations and write to the register only during Write and Color Expand BitBLTs Accessing the register at any other time may result in S1D13A04 stopping to respond and the system to freeze e The Read and Write BitBLT operations ar
474. r Endpoint 3 FIFO Receive If the cause of the interrupt is determined to be EndPoint 3 REG 4004h bit 3 1b then the host controller has sent data to EndPoint 3 Figure 10 2 shows the procedure for reading data from EndPoint 3 An EndPoint 3 interrupt is generated when the number of bytes in the receive FIFO equal the value in the Receive FIFO Almost Full Threshold register REG 403Ah Index 06h The default value is sixty bytes On systems where bulk transfers are used the default value for the receive FIFO threshold should be satisfactory Systems with slow processors high interrupt service latency or configured for isochronous operation may have to decrease this value to allow the CPU time to begin reading data before the data transfer overflows the FIFO Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 100 Epson Research and Development Vancouver Design Center EP3 Receive Did EP3 ACK EP3 NAK REG 4032h b2 1 Flush EP3 FIFO REG 4024h 10h S1D13A04 responded to the OUT packet No S1D13A04 detected a transaction error and did not respond to the OUT packet REG 4032h b1 1 S1D13A04 successfully received a packet E Determine transfer size Count min Remaining REG 4022h Reduce size of remaining transfer Remaining Count Copy another byte from FIFO No
475. r Table 6 5 Generic 1 Interface Timing Page 37 Symbol Parameter Min Max Unit fotk Bus clock frequency 50 MHz Tok Bus clock period T foLk ns u Alt 6 1 M R setup to first CLK rising edge where CS 0 and 9 ae either RDO RD1 0 or WEO WE1 0 t2 CS setup to CLK rising edge 9 ns t3 RDO RD1 WEO WE1 setup to CLK rising edge 1 ns t4 RDO RD1 or WEO WE1 state change to WAIT driven low 1 10 ns t5 RDO RD1 falling edge to D 15 0 driven read cycle 2 10 ns t6 D 15 0 setup to 4th rising CLK edge after CS 0 and WEO y Teix WE1 0 7 A 16 1 M R and CS hold from RDO RD1 WEO WE1 rising 0 me edge t8 CS deasserted to reasserted 0 ns t9 WAIT rising edge to RDO RD1 WEO WE1 rising edge 0 ns t10 WE0 WE1 RDO RD1 deasserted to reasserted 1 Tek 11 Rising edge of either RDO RD1 or WEO WE1 to WAIT high 05 Tae impedance t12 D 15 0 hold from WEO WE1 rising edge write cycle 2 ns t13 D 15 0 hold from RDO RD1 rising edge read cycle 1 ns t14 Cycle Length 5 Tok Table 6 6 Generic 1 Interface Truth Table for Little Endian WEO WE1 RDO RD1 D 15 8 D 7 0 Comments 0 0 1 1 valid valid 16 bit write 0 1 1 1 valid 8 bit write data on low byte even byte address 1 0 1 1 valid 8 bit write data on high byte odd byte address 1 1 0 0 valid valid 16
476. r Data Jitter Tolerance to Note 4 Figure 6 37 18 5 0 18 5 ae Next Transition Receiver Data Jitter Tolerance for Ture Paired Transitions Note 4 Figure 6 37 9 0 9 ns EOP Width at Receiver TEOPR1 Must reject as EOP Note 4 Figure 6 36 40 ns EOP Width at Receiver E TeoPR2 Must accept as EOP Note 4 Figure 6 36 80 ns 1 Measured from 10 to 90 of the data signal 2 The rising and falling edges should be smoothly transitioning monotonic 3 Timing difference between the differential data signals 4 Measured at crossover point of differential data signals 5 20 Qis placed in series to meet this USB specification The actual driver output impedance is 15 Q Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 84 7 Clocks Epson Research and Development Vancouver Design Center 7 1 Clock Descriptions 7 1 1 BCLK 7 1 2 MCLK S1D13A04 X37A A 001 06 BCLK is an internal clock derived from CLKI BCLK can be a divided version 1 2 of CLKI CLKI is typically derived from the host CPU bus clock The source clock options for BCLK may be selected as in the following table Table 7 1 BCLK Clock Selection Source Clock Options BCLK Selection CLKI CNF6 0 CLKI 2 CNF6 1 Note For synchronous bus interfaces it is recommended that BCLK be set the same as the CPU bus clock not a divided version of CLKD e g SH
477. r Design Center In SwivelView 90 these bits set the vertical coordinates y of the PIP window s top edge Increasing y moves the top edge downward in 1 line steps The vertical coordinates start at line 0 Program the PIP Window X Start Position so that PIP Window X Start Position y In Swivel View 180 these bits set the horizontal coordinates x of the PIP window s right edge Increasing x moves the right edge towards the right in steps of 32 bits per pixel see Table 8 2 The horizontal coordinates start at pixel 0 Program the PIP Window X Start Position so that PIP Window X Start Position panel width x 1 32 bits per pixel Note Truncate the fractional part of the above equation In SwivelView 270 these bits set the vertical coordinates y of the PIP window s bottom edge Increasing y moves the bottom edge downwards in 1 line steps The vertical coordi nates start at line 0 Program the PIP Window X Start Position so that PIP Window X Start Position panel width y 1 PIP Y Positions Register REG 5Ch Default 00000000h Read Write n a PIP Y End Position bits 9 0 21 PIP Y End Position The PIP Y End Position bits determine the vertical end position of the PIP window in 0 and 180 SwivelView orientations These bits determine the horizontal end position in 90 and 270 Swivel View For further information on defining the value of the
478. r addresses are blanked because the evaluation board uses the PCI interface and the decode addresses are determined by the system BIOS during boot up Register Address Display Buffer Address USB Support Clock Chip Support Display Data Byte Swap BitBLT Data Byte Swap 13A04CFG Configuration Program Issue Date 01 10 19 The physical address of the start of register decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected The physical address of the start of display buffer decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected The S1D13A04 contains a USB client controller If this box is checked chip initialization will configure GPIO 7 4 for use by the USB controller For further information on the S1D13A04 USB implementation see the S D13A04 Hardware Functional Specification document number X37A A 001 xx The S5U13A04B00C evaluation board implements a Cypress ICD2061A Clock Synthesizer which can be used to generate CLKI and CLKI2 When this box is checked GPIO 3 1 are reserved for Clock Synthesizer support Selecting a HR TFT panel will disable this feature as the HR TFT requires GPIO 3 0 Note that this feature is only available when using the S5U13A04B00C When this box is checked the word data from the display bu
479. r in the listing Manual changes to the registers are not checked for errors so cautionis warranted when directly editing these values It is strongly recommended that the D13A04 Hardware Functional Specification document number X37A A 001 xx be referred to before making any manual register settings Note Manually entered values may be changed by 13A04CFG if further configuration chang es are made on other tabs In this case the user is notified S1D13A04 13A04CFG Configuration Program X37A B 001 01 Issue Date 01 10 19 Epson Research and Development Page 21 Vancouver Design Center Direct Tab gt 1D13A04 Configuration Utility File Help General Preferences Clocks Panel Panel Power Registers Direct Program Di i H GEk CH Direct access to physical chip Write Settings r itiali i _ _ _ _ _ _ _ fh diana Fj Hons a Initialization l d di nalloption 7 ES Registers 5 4 Program clock chip Ja esettinas to physical ohie tameaatey Pattern iiitialize gt 4 Initialize registers I Show test pattem after eyen setting change Lookup Table V _Initialize lookup table Clear Video JW Clear video memory ss Memory Display lest Patten Pattern Shutdown Initialize 1D13404 SHUT DEW SIDII S1D13A04 Initialize _ S1D13A04 The settings on this tab allow direct access to the physical chip using the evaluation board All the cu
480. r respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Windows CE 3 x Display Driver X37A E 006 01 Issue Date 01 10 19 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 3 0 DISPLAY DRIVER Windows CE v3 0 display driver for the S1D13A04 LCD USB Companion Chip is intended as reference source code for OEMs developing for the Microsoft Window CE platform The driver supports 4 8 and 16 bit per pixel color depths in landscape mode no rotation and 8 and 16 bit per pixel color depths in SwivelView 90 degree 180 degree and 270 degree modes The source code is written for portability and contains functionality for most features of the S1D13A04 Source code modification is required to provide a smaller driver for mass production The Windows CE v3 0 display driver is designed around a common configuration include file called mode0 h which is generated by the configuration utility 13A04CFG This design allows for easy customization of display type clocks decode addresses rotation etc by OEMs For further information on 13A04CFG see the 13A04CFG Configuration Program User Manual document number X37A B 001 xx Note The Windows CE display driver is provided as reference source code only They are intended to provide a basis for OEMs to develop their own drivers for Microsoft Win dows CE v3 0 This document and the source code for th
481. re 10 5 SIDI3A04B00C Schematics 5 of 6 S5U13A04B00C Rev 1 0 Evaluation Board User Manual S1D13A04 Issue Date 02 01 28 X37A G 004 02 Page 31 I 1 IS TOE Fe ROO TPES ze war a aqumyiwaumog_ azs Siopeuuoo sng IS04 0 4 ABH DOOFOVELNSS Em zs o nor neo Mor ne 90 vo FT o a Ez 2 p 3 ne osuo Jo osisauoHe RT OSISZLLOHPL p7 J 4 N gen vein Se Mis rs fet Ast L E T lt K our si Ast as LF ro Od 10d HAD 19038 bo nest neet nest aN ome oun FX E E z say oay E k T ano zav H on eet Sov ene Ny Le a saw rae oy OW NEE sav E Say av nevee Za ps sav 0380 gt gt waa ano sav _ olay ano Ff agd clay da Lo y TOW an stay Er uw play nee PX A 9 ma stay 1380 stay e z nee uva FE K uve aosa szi 9 Mauas gt gt HUu3s an E Wanda ob ager 088 FE 9 uuaa gt gt Raia anoos x 1001 never PS ano waois LE K 018 9 asi sasaa ano Pe nee sa EE XK ros 9 saou FA ano Fe ano sanves FE gt gt awws 9 ao kE 42380 nee Le a En za nec stv HE ay stav ano ae
482. re 6 35 Differential Data Jitter T Crossover picnic 4 Point Extended 4 Crossover AN lt Point wes ee Differential Ns AE a y Data Lines EN Diff Data to SEO Skew 9 gt geo EOP Width T copy N Tperion peop gt Receiver EOP Width T toppi Teopao Figure 6 36 Differential to EOP Transition Skew and EOP Width S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 83 Vancouver Design Center eer ot ed EL PERIOD A Differential Data Lines xe gt Ta A Consecutive 4 Transitions N T T A PERIOD JRI aired Transitions N Tperion Ture Figure 6 37 Receiver Jitter Tolerance Table 6 31 USB Interface Timing Symbol Parameter Conditions Waveform Min Typ Max Unit USBrrea USB Clock Frequency 48 MHz TrerioD USB Clock Period Figure 6 34 ee USBrrEg T y 4 20 ns R Rise amp Fall Times SL Pe Figure 6 34 Tr Notes 1 2 4 20 TREM Rise Fall time matching Tp Tp Figure 6 34 90 110 Vers Output Signal Crossover Voltage 1 3 2 0 V ZDRV Driver Output Resistance Steady State Drive 2gNote 5 44 Q TDRATE Data Rate 11 97 12 12 03 Mbs Tk A Figure 6 35 3 5 0 3 5 ns Tonia peer reer Nena Figure 6 35 4 0 0 4 0 ns These Differential to EOP Transition Note 4 Figure 6 36 2 0 5 de Skew TeoPT Source EOP Width Note 4 Figure 6 36 160 167 175 ns Tini Receive
483. ress Selection o o o e 63 Possible BitBLT FIFO Writes o e e 69 Possible BitBLT FIFO Writes o ee ee ee 74 Possible BitBLT FIFO Writes a e 0 ee ee 82 Possible BitBLT FIFO Reads 2 0 2 0 000000 0000000045 91 USB Controller Initialization Sequence o ee ee 96 HAL Library APD rs ease agen Pal ee ee Sas le GR ee org a 112 Page 7 1D13A04 X37A G 003 05 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 8 5 Figure 9 1 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Programming Notes and Examples Issue Date 2002 08 21 Page 9 List of Figures Pixel Storage for 1 Bpp in One Byte of Display Buffer 14 Pixel Storage for 2 Bpp in One Byte of Display Buffer 15 Pixel Storage for 4 Bpp in One Byte of Display Buffer 15 Pixel Storage for 8 Bpp in One Byte of Display Buffer 16 Pixel Storage for 16 Bpp in Two Bytes of Display Buffer 16 Picture in Picture Plus with SwivelView disabled o o 37 Picture in Picture Plus with Swive
484. rface Pin Mapping 0 002 000 0002 eee eee 14 Table 4 2 CPU Bus Connector H3 Pinout 2 ee 15 Table 4 3 CPU Bus Connector H4 Pinout 2 ee ee 16 Table 5 1 LCD Signal Connector HD oo o e 17 Table 5 2 Extended LCD Signal Connector H2 o e 18 Pable 9 Parts List e pca a Boe a RS A eh A IA e Daa 24 List of Figures Figure 3 1 Configuration DIP Switch SW1 Location o o e 9 Figure 3 2 Configuration Jumper JP1 Location oo e e 11 Figure 3 3 Configuration Jumper JP2 Location 0 000000 0000004 12 Figure 3 4 Configuration Jumper JP3 Location o o e e 12 Figure 3 5 Configuration Jumper JP4 Location o o e e 13 Figure 3 6 Configuration Jumper JP5 Location o oo e 13 Figure 7 1 Symbolic Clock Synthesizer Connections 0 o 22 Figure 10 1 S1D13A04BO00C Schematics 1 of 6 0 0 000200000000 26 Figure 10 2 SID13A04B00C Schematics 2 of 6 2 2 0 2 0 000 ee o 27 Figure 10 3 SID13A04B00C Schematics 3 of 6 2 0 ee ee 28 Figure 10 4 SID13A04B00C Schematics 40f6 0 0 0000002 ee ee ee 29 Figure 10 5 SID13A04B00C Schematics Sof 6 a aaa aa eee eee 30 Figure 10 6 SID13A04B00C Schematics 60f 6 0 0 2 0000 eee eee 31 Figure 11 1 S5U13A04B00C Board Layout 0 0 0 0 00000000 32 S5U
485. rfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13A04 Issue Date 01 10 12 X37A G 010 01 Page 16 5 Software 1D13A04 X37A G 010 01 Epson Research and Development Vancouver Design Center Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The 1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Support or www erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 10 12 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM available on the Internet at http www mot com SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc D13A04 Hardware Functional Specification document number X37A A 001 xx Epson Research and Development Inc S5U13A04B00C Rev 1 0 Evaluation Board User Manual document number X37A G 004 xx Epson Research and Develo
486. rite n a 14 13 12 11 10 9 8 MPEN Reserved Reserved ISO WAKEUP Reserved Reserved 6 5 4 3 2 1 0 n a USC 7 bit 6 bits 5 bits 4 bit 3 bit 2 bit 1 bit O Reserved REG 4042h These bits control inputs to the USB module USCMPEN This bit controls the USB differential input receiver 0 differential input receiver disabled 1 differential input receiver enabled Reserved This bit must be set to 0 Reserved This bit must be set to 0 ISO This bits selects between isochronous and bulk transfer modes for the FIFOs Endpoint 3 and Endpoint 4 0 Isochronous transfer mode 1 Bulk transfer mode WAKEUP This active low bit initiates a USB remote wake up 0 initiate USB remote wake up 1 no action Reserved This bit must be set to 0 Reserved This bit must be set to 0 1D13A04 X37A A 001 06 Hardware Functional Specification Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 131 Vancouver Design Center Pin Input Status Pin Output Data Register REG 4044h Default depends on USB input pin state Read Write USBDETECT Input Pin Status read only 1 0 USBPUP Output Pin Status These bits can generate interrupts bit 1 USBDETECT Input Pin Status This read only bit indicates the status of the USBDETECT input pin after a steady state period of 0 5 seconds bit 0 USBPUP Output Pin Status This bit controls the state of the USBPUP output pin
487. rocessor Advanced Developer s Manual Order Number 278240 001 Epson Research and Development Inc S D13A04 Hardware Functional Specification Document Number X37A A 001 xx Epson Research and Development Inc S1D13A04 Programming Notes and Examples Document Number X37A G 003 xx Epson Research and Development Inc S5UI3A04B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X37A G 004 xx 6 2 Document Sources e Intel Developers Website http developer intel com e Intel Literature contact 1 800 548 4725 Epson Research and Development Website www erd epson com S1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 19 Vancouver Design Center 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 F
488. rogram the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 140h REG 8014h is set to 0140h 10 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit 0 is set to 1 Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started 9 2 12 Transparent Move BitBLT with Color Expansion The Transparent Move BitBLT with Color Expansion is virtually identical to the Move BitBLT with Color Expansion This operation expands bits set to one in the source bitmap to the foreground color Bits set to zero in the source bitmap leave the corresponding desti nation pixel as is Setup and use this operation is exactly as with the Move BitBLT with Color Expansion 9 2 13 Read BitBLT This Read BitBLT increases the speed of transferring data from the video memory to system memory This BitBLT complements the Write BitBLT and is typically used to save a part of the display buffer to the system memory Once the Read BitBLT begins the BitBLT engine remains active until all the pixels have been read During a Read BitBLT operation the BitBLT engine expects to send a particular number of WORDs to the CPU and it is the responsibility of the CPU to read the required amount of data When perfor
489. rp HR TFT Panels S1D13A04 Issue Date 01 10 12 X37A G 011 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Connecting to the Sharp HR TFT Panels X37A G 011 01 Issue Date 01 10 12 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 HR TFT Power On Off Sequence Timing ooo 11 Table 2 2 S1D13A04 to LQ039Q2DSO1 Pin Mapping o e 12 Table 3 1 S1D13A04 to LQ031B1DDxx Pin Mapping o e e 16 List of Figures Figure 2 1 Sharp LQ039Q2DS01 Gray Scale Voltage VO V9 Generation 8 Figure 2 2 Panel Gate Driver DC Power Supplies o o e e 9 Figure 2 3 Panel Gate Driver AC Power Supplies o o e 10 Figure 2 4 HR TFT Power On Off Sequence Timing e 11 Figure 3 1 Sharp LQ031B1DDxx Gray Scale Voltage VO V9 Generation 14 Connecting to the Sharp HR TFT Panels S1D13A04 Issue Date 01 10 12 X37A G 011 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Connecting to the Sharp HR TFT Panels X37A G 011 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to connect to the Sharp HR TFT panels directly supported by the S1D13A0
490. rrent configuration settings are used when the chip is initialized To prevent possible damage to the LCD panel press the SHUTDOWN 51013404 button if the panel does not appear to be functioning correctly after initialization If the Write settings to physical chip immediately option is selected use EXTREME CAUTION when changing panel or clock settings Diagnostics This tab allows the user to directly interact with the S1D13A04 configuration process The effect of register changes on the displayed image can be observed before writing any configuration files Fine tuning adjustments may be made to achieve the best possible image on the panel Using this tab requires that a SSU13A04BO0C evaluation board is installed in the computer and a panel is attached Initialization These settings define which actions will be carried out when the Initialize S1D13A04 button is clicked Program Clock Chip The S5U13A04B00C evaluation board design includes a clock chip which can provide the signals for CLKI and CLKI2 Checking this box will include programming the clock chip as part of the S1D13A04 initialization Initialize Registers When this box is checked the S1D13A04 registers will be programmed to their configured values as part of the initialization 13A04CFG Configuration Program 1D13A04 Issue Date 01 10 19 X37A B 001 01 Page 22 Initialize Lookup Table Clear Video Memory Initialize S1D13A04 Additional Options Write Settings Show Test
491. rs this bit bit 3 Endpoint 3 Interrupt Status Receive FIFO Valid This bit indicates when a USB Endpoint 3 Data packet has been received by the S1D13A04 No more packets to endpoint 3 will be accepted until this bit is cleared Writ ing a 1 clears this bit bit 2 Endpoint 2 Interrupt Status This bit indicates when the USB Endpoint 2 Mailbox registers have been read by the USB host Writing a 1 clears this bit bit 1 Endpoint 1 Interrupt Status Receive Mailbox Valid This bit indicates when the USB Endpoint 1 Mailbox registers have been written to by the USB host Writing a 1 clears this bit bitO Upper Interrupt Active read only At least one interrupt status bit is set in register REG 4008h Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 120 Epson Research and Development Vancouver Design Center Interrupt Enable Register 1 REG 4006h Default 00h Read Write 15 13 Transmit FIFO Receive FIFO Almost Empty Almost Full Interrupt Enable Interrupt Enable 1 0 bit 1 Transmit FIFO Almost Empty Interrupt Enable When set this bit enables an interrupt to be generated when the Transmit FIFO Almost Empty status bit is set Note The Transmit FIFO Almost Empty threshold must be set greater than zero as the FIFO count must drop below the threshold to cause an interrupt bit 0 Receive FIFO Almost Full Interrupt Enable When set this bit enables an interrupt to be gen
492. s Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 35 Vancouver Design Center Table 6 2 Clock Input Requirements for CLKI when CLKI to BCLK divide 1 Symbol Parameter Min Max Units fosc Input Clock Frequency CLKI 66 MHz Osc Input Clock period CLKI Tose ns town Input Clock Pulse Width High CLKI 3 ns tow Input Clock Pulse Width Low CLKI 3 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 ns Note Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements Table 6 3 Clock Input Requirements for CLKI2 Symbol Parameter Min Max Units fosc Input Clock Frequency CLKI2 66 MHz Osc Input Clock period CLKI2 Tose ns town Input Clock Pulse Width High CLKI2 3 ns towL Input Clock Pulse Width Low CLKI2 3 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 ns Note Maximum internal requirements for clocks derived from CLKI2 must be considered when determining
493. s X37A G 002 01 Issue Date 01 10 12 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13A04 USB LCD Companion Chip and the Toshiba MIPS TMPR3905 3912 processors The designs described in this document are presented only as examples of how such interfaces might be implemented This application note is updated as appropriate Please check the Epson Research and Development website at www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors 1D13A04 Issue Date 01 10 12 X37A G 002 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TMPR3905 12 2 1 The Toshiba TMPR3905 12 System Bus 2 1 1 Overview The TMPR39XX family of processors features a high speed system bus typical of modern MIPS RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements The TMPR3905 12 is a highly integrated controller developed for handheld products The microprocessor is based on the R3900 MIPS RISC processor core The TMPR3905 12 implements an external 26 bit address bus and a 32 bit data bus al
494. s bit 0 video data is normal When this bit 1 video data is inverted Note Video data is inverted after the Look Up Table bit 19 PIP Window Enable This bit enables a PIP window within the main window The location of the PIP win dow within the landscape window is determined by the PIP X Position register REG 58h and PIP Y Position register REG 5Ch The PIP window has its own Dis play Start Address register REG 50h and Memory Address Offset register REG 54h The PIP window shares the same color depth and Swivel View orientation as the main window When this bit 1 the PIP window is enabled When this bit 0 the PIP window is disabled bit 17 16 SwivelView Mode Select Bits 1 0 These bits select different Swivel View orientations Table 8 9 SwivelView Mode Select Options SwivelView Mode Select Bits SwivelView Orientation 00 0 Normal 01 90 10 180 11 270 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 96 Epson Research and Development Vancouver Design Center bits 4 0 Bit per pixel Select Bits 4 0 These bits select the color depth bit per pixel for the displayed data for both the main window and the PIP window if active 1 2 4 and 8 bpp modes use the 18 bit LUT allowing maximum 64K colors 16 bpp mode bypasses the LUT allowing only 64K colors Table 8 10 LCD Bit per pixel Selection
495. s hardware rotation of the display memory transparent to the software application The S1D13A04 also provides support for Picture in Picture Plus a variable size Overlay window The S1D13A04 with its integrated USB client provides impressive support for Palm OS handhelds However its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications E FEATURES e Embedded 160KB Display Buffer e USB Client Revision 1 1 compliant e Low Operating Voltage e SwivelView 90 180 270 hardware de e Low latency CPU interface rotation of displayed image e Direct support for multiple CPU types e Picture in Picture Plus l e Programmable resolutions and color depths e Pixel Doubling e Passive LCD support e Hardware Acceleration Engine e Active Matrix LCD support e Software Initiated Power Save Mode e Direct Sharp HR TFT support e Software Video Invert e 121 pin PFBGA or TQFP15 128 pin package E SYSTEM BLOCK DIAGRAM USB Data and XX Control Signals S1 D1 3A04 LCD Panel t X37A C 001 04 1 W DESCRIPTION CPU Interface e Fixed low latency CPU access times Direct support for Hitachi SH 4 SH 3 Motorola M68xxx REDCAP2 DragonBall ColdFire MPU bus interface with programmable READY Memory Interface Embedded 160K byte SRAM display buffer Power Down Modes Software Initiated Power
496. serting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC82x Microprocessor S1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 12 Epson Research and Development Vancouver Design Center Figure 2 3 GPCM Memory Devices Timing illustrates a typical cycle for a memory mapped device using the GPCM of the Power PC aoe 3 LI LI LJ LI LI LI LI LI A O 31 III IIS Figure 2 3 GPCM Memory Devices Timing 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the S1D13A04 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM
497. set to 1 Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 88 Epson Research and Development Vancouver Design Center 9 2 11 Move BitBLT with Color Expansion 1D13A04 X37A G 003 05 The Move BitBLT with Color Expansion takes a monochrome bitmap as the source and color expands it into the destination All bits set to one in the source are expanded to desti nation pixels of the selected foreground color All bits set to zero in the source are expanded to pixels of the selected background color The Move BitBLT with Color Expansion is used to accelerate text drawing A monochrome bitmap of a font in off screen video memory occupies very little space and takes advantage of the hardware acceleration Since the foreground and background colors are programmable text of any color can be created The Move BitBLT with Color Expansion can move data from one rectangular area to another or either the source or destination may be specified to be linear Storing rectangular display data in linear format in off screen memory results in a tremendous space saving Example 18 Color expand a 9 x 16 rectangle using the pattern in off screen memory at 27000h and move it to the screen coordinates x 200 y 20 Assume a 320x240 display at a color depth of 16 bpp Foreground color
498. sets the LUT to uniform values for color mono panels at all color depths S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 113 Vancouver Design Center 11 2 1 Startup Routines There are two routines dedicated to startup and initializing the S1D13A04 Typically these two functions are the first two HAL routines a program will call The startup routines locate the S1D13A04 controller and initialize HAL data structures As the name suggests the initialization routine prepares the S1D13A04 for use Splitting the startup functionality allows programs to start and locate the S1D13A04 but delay or possibly never initialize the controller Boolean halAcquireController Ulnt32 pMem Ulnt32 pReg Description This routine initializes data structures and initiates the link between the application soft ware and the hardware When the S1D13A04 HAL is used this routine must be the first HAL function called On PCI platforms the routine attempts to load the S1D13xxx driver If the driver loads successfully then a check is made for the existence of an S1D13A04 Parameters pMem Pointer to an unsigned 32 bit integer which will receive the offset to the first byte of display memory The offset may be cast to a pointer to access display memory pReg Pointer to an unsigned 32 bit integer which will receive the offset to the first byte of register space The offset may be cast to a poi
499. sfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data lines DO through D15 are used and address line A31 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 Do not increment address bits A28 and A29 between successive transfers the addressed device must increment these address bits internally S1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA and the processor reverts to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the S1D13A04 therefore the interfa
500. sition REG 5Ch bits 25 16 Figure 8 3 Picture in Picture Plus with SwivelView 90 enabled SwivelView 90 is a mode in which both the main and PIP windows are rotated 90 counter clockwise when shown on the panel The images for each window are typically placed consecutively with the main window image starting at address O and followed by the PIP window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and PIP window To do so set the PIP Line Address Offset register REG 54h to the same value as the Main Window Line Address Offset register REG 44h S1D13A04 X37A G 003 05 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 49 Vancouver Design Center Example 6 In SwivelView 90 program the PIP window registers for a 320x240 panel at 4 bpp with the PIP window positioned at SwivelView 90 coor dinates 60 80 with a width of 120 and a height of 160 1 Determine the value for the PIP Window X Positions and PIP Window Y Positions registers Let the top left corner of the PIP window be x1 y1 and let the bottom right corner be x2 y2 where x2 x1 width 1 and y2 y1 height 1 The PIP Window X Positions register sets the vertical coordinates of the PIP window s top right and bottom left corners T
501. splay Period Start Position bits 9 0 15 14 13 12 11 10 6 5 4 3 1 30 29 28 27 26 n a 15 14 13 12 11 10 15 14 13 12 11 10 n a n a Main Window Line Address Offset bits 9 0 0 S1D13A04 Register Summary X37A R 001 01 Issue Date 01 10 02 Epson Research and Development Page 3 Vancouver Design Center PICTURE IN PICTURE PLUS PIP REGISTERS 22 PIP Window Display Start Address bits 15 0 9 8 7 6 3 PIP Window Line Address Offset bits 9 0 5 4 3 1 30 29 28 27 26 n a n a PIP Window X End Position bits 9 0 n a PIP Window X Start Position bits 9 0 Si n a n a 15 14 13 12 14 10 PIP Window Y End Position bits 9 0 25 24 23 22 21 20 19 18 17 16 PIP Window Y Start Position bits 9 0 5 4 MISCELLANEOUS REGISTERS Display Display Data Word Data Byte Swap Swap 6 5 2 Latch Byte Select GPIO3 Input Enable PWM Clock Divide Select PWM Clock PWMCLK Source Select bits 3 0 Force High bits 1 0 3 a 31 0 29 28 27 26 25 2 n a PWMOUT Duty Cycle bits 7 0 2 2 7 2 3 1 3 Scratch Pad A bits 31 24 3 2 1 0 29 28 27 2 25 2 4 13 12 11 1 9 Scratch Pad B bits 31 24 3 30 29 28 27 2 25 2 Scratch Pad B bits 15 0 15 14 13 12 11 10 9 Scratch Pad C bits 31 24 3 30 29 28 27 26 25 2 Scratch Pad C bits 15 0 15 14 13 12 wi 10 9 8 Register Summary S1D13A04 Issue Date 01 10 02 X37A R 001 01 ni 4 3 22 21 20 19 18 17 1
502. splay memory is LOST and since there is insuffi cient system memory to save display data off screen memory usage MUST be disabled e When the system is resumed WinCE instructs all running applications to re paint themselves This is the SLOWEST of the three modes Simple Display Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 Windows CE 3 x Display Driver Issue Date 01 10 19 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S 1D13A04 sources and change the line CDEFINES CDEFINES DEnablePreferVmem to CDEFINES CDEFINES DEnablePreferVmem This step causes the system to redraw the main display upon power on This step is only required if display memory loses power when Windows CE is shut down If dis play memory is kept powered up set the S1D13A04 in powersave mode then the display data will be maintained and this step can be skipped Search for the file PROJECT REG in your Windows CE directories and inside PROJECT REG find the key PORepaint Change PORepaint as follows PORepaint dword 2 S1D13A04 X37A E 006 01 Page 14 Comments S1D13A04 X37A E 006 01 Epson Research and Development Vancouver Design Center The display driver is C
503. st immediately set the EP4 FIFO Valid bit before responding to the next IN token After filling the EP4 FIFO the steps to follow before setting the EP4 FIFO Valid bit are 1 Clear the EP4 Interrupt Status bit REG 4004h bit 4 2 Read the EP4 Interrupt Status bit REG 4004h bit 4 until it is set 3 Set the EP4 FIFO Valid bit REG 402Ch bit 5 1 The setting of the EP4 FIFO Valid bit is time critical The EP4 FIFO Valid bit must be set within 3 us after the EP4 Interrupt Status has been set internally by the S1D13A04 Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 112 Epson Research and Development Vancouver Design Center 11 Hardware Abstraction Layer 11 1 Introduction The S1D13A04 Hardware Abstraction Layer HAL is a collection of routines intended to simplify the programming for the S5U13A04B00C evaluation board Programmers can use the HAL to assist in rapid software prototyping for the S5Ul13A04B00C evaluation board The HAL routines are divided into discrete functional blocks The functions for startup and clock control offer specific support for the S5U13A04B00C evaluation board while other routines demonstrate memory and register access techniques For a complete list see Table 11 1 HAL Library APT 11 2 API for the HAL Library The following table lists the functions provided by the S1D13A04 HAL library Table 11 1 HAL Library API Function Description Star
504. ster REG 8010h is set to 2F99h Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Page 81 Vancouver Design Center 10 Programming Notes and Examples Issue Date 2002 08 21 Program the BitBLT Width Register to 100 1 REG 8018h is set to 63h 99 deci mal Program the BitBLT Height Register to 20 1 REG 801Ch is set to 13h 19 deci mal Program the Source Phase in the BitBLT Source Start Address Register In this exam ple the data is WORD aligned so the source phase is 0 REG 800Ch is set to 00h Program the BitBLT Operation Register to select Transparent Write BitBLT REG 8008h bits 3 0 are set to 4h Program the BitBLT Background Color Register to select transparent color REG 8020h is set to 7Ch 124 decimal Program the BitBLT Color Format Select bit for 8 bpp operations REG 8000h bit 18 is set to 0 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 2 160 AOh REG 8014h is set to OAOh Calculate the number of WORDS the BitBLT engine expects to receive WORDS BLTWidth 1 SourcePhase 2 x BLTHeight 100 1 0 2 x20 1000 3E8h Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation and wait for the BitBLT engine to start REG 8000h bit 0 is set to
505. sue Date 01 10 12 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents PC Card PCMCIA Standard March 1997 Epson Research and Development Inc S D13A04 Hardware Functional Specification document number X37A A 001 xx Epson Research and Development Inc S5U13A04B00C Rev 1 0 Evaluation Board User Manual document number X37A G 004 xx Epson Research and Development Inc S1D13A04 Programming Notes and Examples Document Number X37A G 003 xx 6 2 Document Sources e PC Card Website www pc card com Epson Research and Development Website www erd epson com Interfacing to the PC Card Bus S1D13A04 Issue Date 01 10 12 X37A G 005 01 Page 16 7 Sales and Technical Support 7 1 EPSON LCD USB Companion Chips S1D13A04 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http Awww epson com hk 7 2 PC Card Standard PCMCIA North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http www epso
506. support and Windows CE based embedded consumer applications in mind the VR4102 VR4111 offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR series microprocessor is designed around the RISC architecture developed by MIPS The VR4102 microprocessor is designed around the 66MHz VR4100 CPU core and the VR4111 is designed around the 80 100MHz VR4110 core These microprocessors support 64 bit processing The CPU communicates with the Bus Control Unit BCU through its internal SysAD bus The BCU in turn communicates with external devices with 1ts ADD and DATA busses which can be dynamically sized for 16 or 32 bit operation The NEC VR4102 VR4111 can directly support an external LCD controller through a dedicated bus interface Specific control signals are assigned for an external LCD controller in order to provide an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller with its own chip select and ready signals available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 VR4111 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low T
507. t for later restoration using a Move BitBLT During a Write BitBLT operation the BitBLT engine expects to receive a particular number of WORDs and it is the responsibility of the CPU to provide the required amount of data When performing BitBLT at 16 bpp color depth the number of WORDS to be sent is the same as the number of pixels to be transferred as each pixel is one WORD wide The number of WORD writes the BitBLT engine expects is calculated using the following formula WORDS Pixels BitBLTWidth x BitBLTHeight When the color depth is 8 bpp the formula must take into consideration that the BitBLT engine accepts only WORD accesses and each pixel is one BYTE This may lead to a different number of WORD transfers than there are pixels to transfer The number of WORD accesses is dependant on the position of the first pixel within the first WORD of each row Is the pixel stored in the low byte or the high byte of the WORD This aspect of the BitBLT is called phase and is determined as follows Source phase is 0 when the first pixel is in the low byte and the second pixel is in the high byte of the WORD When the source phase is 0 bit 0 of the Source Start Address Register is 0 The Source Phase is 1 if the first pixel of each row is contained in the high byte of the WORD the contents of the low byte are ignored When the source phase is 1 bit 0 of the Source Start Address Register is set Depending on the Source Phase and the BitBLT Wid
508. t O returns a 1 11 Prior to writing any data to the BitBLT FIFO confirm the BitBLT FIFO is not full REG 8004h bit 4 returns a 0 If the BitBLT FIFO Not Empty Status REG 8004h bit 6 returns a 0 the FIFO is empty Write up to 16 WORDS to the BitBLT data register area If the BitBLT FIFO Not Empty Status REG 8004h bit 6 returns a 1 and the BitBLT FIFO Half Full Status REG 8004h bit 5 returns a 0 then you can write up to 8 WORDS If the BitBLT FIFO Full Status returns a 1 do not write to the BitBLT FIFO until it re turns a 0 The following table summarizes how many words can be written to the BitBLT FIFO Table 9 5 Possible BitBLT FIFO Writes BitBLT Status Register REG 8004h Word Writes FIFO Not Empty Status FIFO Half Full Status FIFO Full Status Available 0 0 0 16 1 0 0 8 1 1 0 up to 8 1 1 1 0 do not write Note The sequence of register initialization is irrelevant as long as all required registers are programmed before the BitBLT is started Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 70 Epson Research and Development Vancouver Design Center 9 2 2 Color Expansion BitBLT Similar to the Write BitBLT the Color Expansion BitBLT requires the CPU to feed data to the BitBLT data register It differs in that bits set to one in the source data becomes a complete pixel of foreground color Source bits set to zero are converted to a pixel of bac
509. t only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Interfacing to the NEC VR4181A Microprocessor X37A G 008 01 Issue Date 01 10 12 Epson Research and Development Page 3 Vancouver Design Center Table of Contents A Introduction ara ana deb ans a Boat a ed GO A a a A Sette 7 2 Interfacing to the NEC VR4181A 2 2 ee 8 2 1 The NEC VR4181A System BUS o 8 Ze ONCRVIEW ceca ds a e A A da e de 8 2 1 2 LCD Memory Access Signals o o 9 3 S1D13A04 Host Bus Interface o 10 3 1 Host Bus Interface Pin Mapping 10 3 2 Host Bus Interface Signals oos a so ao s ee A 4 VR4181A to S1D13A04 Interface ee 12 4 1 Hardware Description a a a ee ee 1 4 2 1D13A04 Hardware Configuration 13 4 3 NEC VR4181A Configuration 2 a a eee ee 14 5 SOUMWAIG i i sue ee
510. t per pixel data from Display Buffer Figure 12 2 2 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 146 Epson Research and Development Vancouver Design Center 4 Bit per pixel Monochrome Mode Green Look Up Table 256x6 00 0000 01 0001 02 0010 03 m 0011 04 m 0100 05 0101 06 m 0110 bi 07 0111 6 bit Gray Data k 08 1000 09 1001 0A 1010 0B 1011 0C 1100 0D 1101 OE 1110 OF 1111 FC FD FE FF 4 bit per pixel data from Display Buffer unused Look Up Table entries Figure 12 3 4 Bit per pixel Monochrome Mode Data Output Path 8 Bit per pixel Monochrome Mode Green Look Up Table 256x6 00 0000 0000 01 L 0000 0001 02 L 00000010 03 L 00000011 04 L 00000100 05 L 00000101 06 __ 9000 0110 07 L 00000111 E 6 bit Gray Data gt F8 1111 1000 F9 14111 1001 FA 111 1010 FB 1111 1011 FC 1111 1100 FD c 11111101 FE c 1111 1110 FF c 11111111 8 bit per pixel data from Display Buffer Figure 12 4 8 Bit per pixel Monochrome Mode Data Output Path S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Rev
511. t the horizontal coordinates x of the PIP window s right edge Increasing x moves the right edge towards the right in steps of 32 bits per pixel see Table 8 1 The horizontal coordinates start at pixel 0 Program the PIP Window X End Position so that PIP Window X End Position x 32 bits per pixel Note Truncate the fractional part of the above equation In Swivel View 90 these bits set the vertical coordinates y of the PIP window s bottom edge Increasing y moves the bottom edge downward in line steps The vertical coordi nates start at line 0 Program the PIP Window X End Position so that PIP Window X End Position y S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 41 Vancouver Design Center PIP X Start Position In Swivel View 180 these bits set the horizontal coordinates x of the PIP windows left edge Increasing x moves the left edge towards the right in steps of 32 bits per pixel see Table 8 1 The horizontal coordinates start at pixel 0 Program the PIP Window X End Position so that PIP Window X End Position panel width x 1 32 bits per pixel Note Truncate the fractional part of the above equation In SwivelView 270 these bits set the vertical coordinates y of the PIP window s top edge Increasing y moves the top edge downwards in 1 line steps The vertical coordinates start at line 0 Pr
512. t word transfer takes place on D 15 0 During a read cycle either RD or CARDIORD is driven low depending on whether a memory or IO cycle is specified A write cycle is specified by driving WE memory cycle or CARDIOWR IO cycle low The cycle can be lengthened by driving CARD1WAIT low for the time required to complete the cycle Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors Issue Date 01 10 12 Epson Research and Development Page 9 Vancouver Design Center Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle illustrates a typical memory attribute cycle on the Toshiba 3905 12 PC Card bus S X ALE a x D 31 16 Y CARD1CSL CARD1CSH RD WE CARD1WAIT Figure 2 1 Toshiba 3905 12 PC Card Memory Attribute Cycle Figure 2 2 Toshiba 3905 12 PC Card IO Cycle illustrates a typical IO cycle on the Toshiba 3905 12 PC Card bus A 25 0 x ALE IN D 31 16 Y CARD1CSL CARD1CSH CARDIORD CARDIOWR CARD1WAIT CARDREG Figure 2 2 Toshiba 3905 12 PC Card IO Cycle Interfacing to the Toshiba MIPS TMPR3905 3912 Microprocessors S1D13A04 X37A G 002 01 Issue Date 01 10 12 Page 10 Epson Research and Development 3 S1D13A04 Host Bus Interface The S1D13A04 directly supports multiple processors The S1D13A04 implements a 16 bit Generic 2 Host Bus Interface whic
513. t would be written into REG 4038h if separate operations were done to access the index and data registers If no data is specified the command reads and displays the contents of the specified extended USB register Where index Index into USB registers at REG 403Ah hex data The value to be written to the indexed data register Numbers are assumed to be hexadecimal values unless otherwise specified with the correct suffix binary i octal o decimal t hexadecimal h For example 101i 101 binary 13A04PLAY Diagnostic Utility S1D13A04 Issue Date 01 10 05 X37A B 002 01 Page 10 Epson Research and Development Vancouver Design Center WI SI16132 startaddr data1 data2 data3 data4 Writes the given data sequence to the display buffer starting at startaddr location Where 8116132 The unit size 8 bit bytes 16 bit words 32 bit dwords If a unit size is not specified this command uses the unit size from the last Write command performed If no previous Write command has been issued the unit size defaults to 8 bit startaddr The starting address to write data to Specifying a period uses the same starting address as the last Write command performed data Values to write to the display buffer If no data is given then this function enters MODIFY mode This mode prompts the user with the address and it s current data While in this mode the user can type any of the following new values in hex ENTE
514. tation is done in hardware and is transparent to the user for all display buffer reads and writes By processing the rotation in hardware Swivel View offers a performance advantage over software rotation of the displayed image The image is not actually rotated in the display buffer since there is no address translation during CPU read write The image is rotated during display refresh Note The Pixel Doubling feature of the S1D13A04 is not available in 90 and 270 Swivel View rotations 13 2 90 SwivelView 90 SwivelView requires the Memory Clock MCLK to be at least 1 25 times the frequency of the Pixel Clock PCLK i e MCLK 2 1 25PCLK The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed The application image is written to the S1D13A04 in the following sense A B C D The display is refreshed by the S1D13A04 in the following sense B D A C Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Epson Research and Development Page 152 Vancouver Design Center physical memory start address A B E SwivelView a z a window display start address gt E Q panel origin 9 E S E lt s o C D M 4 480 5 320 image seen by programmer image refreshed by S1D13A04 image in display buffer Figure 13 1 Relationship Between The Screen Image and the Image Refreshed in 90 Sw
515. th Table 8 4 32 bit Address Increments for Color Depth Bits Per Pixel Color Depth Pixel Increment Y 1 bpp 32 2 bpp 16 4 bpp 8 8 bpp 4 16 bpp 2 In SwivelView 0 these bits set the vertical coordinates y of the PIP windows s top edge Increasing y moves the top edge downwards in line steps The vertical coordinates start at line 0 Program the PIP Window Y Start Position so that PIP Window Y Start Position y In Swivel View 90 these bits set the horizontal coordinates x of the PIP window s right edge Increasing x moves the right edge towards the right in steps of 32 bits per pixel see Table 8 4 The horizontal coordinates start at pixel 0 Program the PIP Window Y Start Position so that PIP Window Y Start Position panel height x 1 32 bits per pixel Note Truncate the fractional part of the above equation In SwivelView 180 these bits set the vertical coordinates y of the PIP window s bottom edge Increasing y moves the bottom edge downwards in 1 line steps The vertical coordi nates start at line 0 Program the PIP Window Y Start Position so that PIP Window Y Start Position panel height y 1 Programming Notes and Examples Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center Page 45 In Swivel View 270 these bits set the horizontal coordinates x of the PIP window s left edge Increasing x moves the
516. th the last WORD may contain only one pixel In this case it is always in the low byte The number of WORD writes the BitBLT engine expects for 8 bpp color depths is shown in the following formula WORDS BitBLTWidth 1 SourcePhase 2 x BitBLTHeight The BitBLT engine requires this number of WORDS to be sent from the local CPU before it will end the Write BitBLT operation Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 68 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center Note The BitBLT engine counts WORD writes made to the BitBLT register space This does not imply only 16 bit CPU instructions are acceptable If a system is able to separate one DWORD write into two WORD writes and the CPU writes the low word before the high word then 32 bit CPU instructions are acceptable Otherwise 16 bit CPU instruc tions are required Example 9 Write a 100 x 20 rectangle at the screen coordinates x 25 y 38 using a 320x240 display at a color depth of 8 bpp 1 Calculate the destination address upper left corner of the screen BitBLT rectangle using the following formula DestinationAddress y X ScreenStride x x BytesPerPixel 38 x 320 25 x 1 12185 2F99h where BytesPerPixel 1 for 8 bpp BytesPerPixel 2 for 16 bpp ScreenStride DisplayWidthInPixels x BytesPerPixel 320 for 8 bpp Program the BitBLT Destination Start Address Re
517. th Size 00 4 bit 9 bit 01 8 bit 12 bit 10 16 bit 18 bit 11 Reserved Reserved Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 94 Epson Research and Development Vancouver Design Center bit 3 Direct HR TFT Resolution Select This bit selects one of two panel resolutions when the Direct HR TFT interface is selected This bit has no effect for other panel types Table 8 7 Active Panel Resolution Selection Direct HR TFT Resolution Select Bit HR TFT Resolution 0 160x160 1 320x240 bits 1 0 Panel Type Bits 1 0 These bits select the panel type Table 8 8 LCD Panel Type Selection Panel Type Bits 1 0 Panel Type 00 STN 01 TFT 10 Direct HR TFT 11 Reserved Display Settings Register REG 1 0h Default 00000000h Read Write Pixel Pixel i y PIP Doubling Doubling aed raat Window SwivelView Mode Select Vertical Horiz Enable 25 22 19 Bits per pixel Select actual value 1 2 4 8 or 16 bpp 3 2 1 bit 25 Pixel Doubling Vertical Enable This bit controls the pixel doubling feature for the vertical dimension or height of the panel i e 160 pixel high data doubled to 320 pixel high panel When this bit 1 pixel doubling in the vertical dimension height is enabled When this bit 0 there is no hardware effect Note Pixel Doubling is not designed to support color d
518. the 160K byte display buffer occupies the second 256K byte block Each variable latency IO chip select is assigned 128M Bytes of address space Therefore if nCS4 is used the S1D13A04 registers will be located at 4000 0000h and the display buffer will be located at 4004 0000h These blocks are aliased over the entire 128M byte address space Note If aliasing is not desirable the upper addresses must be fully decoded 1D13A04 Interfacing to the Intel StrongARM SA 1110 Microprocessor X37A G 013 01 Issue Date 01 10 12 Epson Research and Development Page 17 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13A04 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13A04CFG see document number X37A B 001 xx or by directly modifying the source The display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13A04 test utilities and display drivers are available from your sales support contact see Section 7 Sales and Technical Support or www erd epson com Interfacing to the Intel StrongARM SA 1110 Microprocessor S1D13A04 Issue Date 01 10 12 X37A G 013 01 Page 18 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents Intel Corporation StrongARM SA 1110 Microp
519. the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES and click NEXT Click Have Disk Specify the location of the driver files and click OK Click Next Click Finish Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 Ze Install the evaluation board in the computer and boot the computer Windows will detect the card Select DRIVER FROM DISK PROVIDED BY MANUFACTURER Click OK Specify a path to the location of the driver files Click OK Windows will find the S1D13XXX INF file Click OK Click OK and Windows will install the driver S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 8 Epson Research and Development Vancouver Design Center All ISA Bus Evaluation Cards X00A E 003 04 10 11 12 13 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES from the HARDWARE TYPES list Click HAVE DISK Specify the location of the driver files and click OK Select the file S1D13XXX INF and click OK Click OK The EPSON PCI Bridge Card should be selected in the list window Click NEXT Click NEXT Click Finish S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 EPSON 1D1
520. the frequency of CLKI2 See Section 6 1 2 Internal Clocks on page 35 for internal clock requirements 6 1 2 Internal Clocks Table 6 4 Internal Clock Requirements Symbol Parameter Min Max Units fBcLK Bus Clock frequency 66 MHz fMcLK Memory Clock frequency note T 2 MHz foot Pixel Clock frequency 50 MHz fowMCLK PWM Clock frequency 66 MHz 1 When COREVDD 2 0V 10 fycLk max 30MHz 2 MCLK is derived from BCLK therefore when BCLK is greater than 50MHz MCLK must be divided using REG 04h bits 5 4 Note For further information on internal clocks refer to Section 7 Clocks on page 84 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 36 Epson Research and Development Vancouver Design Center 6 2 CPU Interface Timing 6 2 1 Generic 1 Interface Timing e g Epson EOC33 P Terk CLK t 17 gt e A 16 1 M R Wi ee t2 t8 4 CS L E E 5 13 19 lt gt P E t10 WEO WE1 RDO RD1 I WAIT S t6 t12 A gt ni D 15 0 write al valid t5 t13 gt gt D 15 0 read es Figure 6 2 Generic 1 Interface Timing 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Vancouver Design Cente
521. the packet and clears the interrupt at Point 2 A second packet is already being received at Point 2 and the S1D13A04 has already decided to NAK this packet due to Rule A At point 3 the S1D13A04 has NAKed the packet and asserts the Interrupt status bit Again the local firmware responds to the interrupt and seeing it is only a NAK interrupt clears the interrupt condition at Point 4 However the Host PC has begun to retry the second packet already so the packet will again get NAKed due to Rule B This cycle could continue until something changes the flow of OUT packets for instance an SOF at the beginning of the next frame or packet traffic directed at another device or endpoint Work Around The normal program flow for a packet which the S1D13A04 NAKs is as follows 1 S1D13A04 asserts IRQ after NAKing a received packet on EP3 2 Local CPU is interrupted enters interrupt routine 3 Local CPU reads Interrupt Status Register 0 REG 4004h and sees EP3 Packet Re ceived interrupt bit 4 Local CPU reads USB Status Register REG 4032h and sees NAK bit set 5 Local CPU clears Interrupt Status Register 0 REG 4004h EP3 Packet Status in terrupt bit 6 Local CPU clears USB Status Register REG 4032 NAK bit The technique for avoiding this potential pitfall depends on the speed of the peripheral CPU The critical timing parameter is the time from the S1D13A04 asserting IRQ to the firmwar
522. time the USB receiver is disabled the EP4 FIFO Valid bit is set When the local CPU is ready to send data on endpoint 4 the steps to follow are 2 Disable the USB differential input receiver REG 4040h bit 6 0 3 Wait a minimum of Ips If needed delays may be added 4 Enable the EP4 FIFO Valid bit REG 402Ch bit 5 1 5 Clear the EP4 Interrupt status bit REG 4004h bit 4 1 6 Enable the USB differential input receiver REG 4040h bit 6 1 Note Steps 1 through 5 are time critical and must be performed in less than 6 us Note To comply with EP4 NAK Status not set correctly in USB Status register steps 3 and 4 must be completed within 5 us of each other For further information on EP4 NAK Status not set correctly in USB Status register see Section 10 4 1 EP4 NAK Status not set correctly in USB Status Register EP4 FIFO Valid bit set after NAK and before the next IN token The second solution is to wait until immediately after the USB has responded to an IN request with a NAK packet before setting the transmit FIFO valid bit This solution is recommended only for fast processors When the local CPU is ready to send data on endpoint 4 it must first detect that a NAK packet has been sent This is done by reading the EP4 Interrupt Status bit REG 4004h bit 4 If the EP4 FIFO Valid bit was not set the EP4 Interrupt Status bit is set only ifa NAK packet has been sent When the local CPU detects the NAK it mu
523. tion Software e Display Drivers Application Engineering Support EPSON offers the following services through their Sales and Marketing Network e Sales Technical Support e Customer Training e Design Assistance Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg TECHNICAL MANUAL Issue Date 01 10 02 S1D13A04 X37A Q 001 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 TECH
524. tive owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction 4 racial ew a Aaa la ee a ee a 11 EI PSCOPC SS Bc Am es Hoge A ote AA A te cs ty eee eee oll 1 2 Overview Description s ste 2 a e a ee ee 11 2 Featul s o sr e Geeta Sher Ss eA le Ss VES ee a ee SG 12 2 1 Integrated Frame Buffer 2 2 eee 12 2 2 CPU Interface 2 3 ts tena a ie Be ab ee a oe GS a ee Bie Ge a te a ae VA 2 3 Display Support s su aoa us ah ph aoa amp hoa la a a aoada ee e 12 2 4 Display Modes 0 2 ne oda ee ee ee we 1D 20 Display Features a anar s Ca May enced ak ee oa BO Uk oat a Gs ee A ee oa a lS 26 gt Clock Source 4 io amp AS A A ed a Ba ps a oe TS 23 NUSB Devices ra 2 A eee EE ee se ke MS 2 8 2D ACCOlEFA LION sa 3 0 Gi ee ae a hehe UB HE a e o Be US a Oe es Ee Ue Baca a AD 2 9 gt Miscellaneous v se m ke a Ate Be oe Se aw Awe aa ae ew a A LA 3 Typical System Implementation Diagrams 2 00282 ee eae 15 3 1 Typical System Diagrams 15 3 2 USB Interface 2 08 05 sk ad Be a Ge gE AS ee he a Ge a a ae a LO 4 1 Pinout Diagram PFBGA 121 pin 2 2 aaa 20 4 2 Pinout Diagram TQFP15 128 pin a a eee 21 4 3 gt Pin D
525. tly to IO Vpp or Vss Test Enable input used for production test only has type 1 TESTEN E7 109 T1 pull down resistor with a typical value of 50KQ at 3 3V Note This pin must not be connected 4 3 5 Power And Ground Table 4 6 Power And Ground Pin Descriptions PFBGA TQFP15 RESET Pin Name Type Ping Pin Cell State Description L2 G4 20 33 IOVDD P H6 L9 46 61 P 610 Vpp pins A10 F11 80 97 A2 C2 1 64 65 2 double bonded Core Vpp pins on TQFP package PORED P litio dio 128 4 Core Vpp pins on PFBGA package B2 F2 18 32 K2 G5 45 62 VSS P F9 B10 K 79 96 P 7 Vgs pins 10 127 Hardware Functional Specification 1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 30 Epson Research and Development Vancouver Design Center 4 4 Summary of Configuration Options These pins are used for configuration of the S1D13A04 and must be connected directly to IOVpp or Vss The state of CNF 6 0 are latched on the rising edge of RESET Changing state at any other time has no effect Table 4 7 Summary of Power On Reset Options S1D13A04 Power On Reset State Configuration Input 1 connected to IO Vpp 0 connected to Vss Select host bus interface as follows CNF4 CNF2 CNF1 CNFO Host Bus 0 0 0 SH 4 SH 3 interface Big Endian y 0 0 0 0 SH 4 SH 3 interface Little Endian 1 0 0 1 MC68K
526. to EP4 FIFO REG 4028h Buffer Yes Reference next position pBuffer a No y Clear USB EP4 ACK REG 4032 10h See Section 10 4 1 on page 106 EP4 IRQ status l must be cleared within 5 us of EP4 transmit FIFO valid Set EP4 IRQ enable REG 4002h 10h Set Transmit FIFO valid REG 402Ch 20h Clear EP4 IRQ Status REG 4004h 10h Figure 10 4 Endpoint 4 Data Transmission Note In this example there are three variables PktSize is an integer containing the number of bytes to transfer in this packet Count is an integer used for local loop control pBuffer is a pointer to an array of at least FIFOSIZE bytes Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 104 Epson Research and Development Vancouver Design Center To ensure the host controller receives the packet error free an interrupt handler for EndPoint 4 must be configured and the flow control as shown in the following diagram must be implemented 1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Vancouver Design Center Page 105 EP4 Int Handler acket actually sent EP4 Int Handler is called after the host controller reads or fails to read a packet If the host controller successfully read the last packet then the next packet can be loaded into the FIFO If the host controller failed t
527. to explain how to setup and configure the interrupt system for the variety of platforms the S1D13A04 supports The examples and flowcharts assume there is one interrupt handling routine which will determine the cause of the interrupt and call the appropriate handler function It is assumed the user understands the mechanics and architecture of their system well enough setup a routine which will receive an interrupt notification and determine the cause of the interrupt 10 2 Initialization 10 2 1 GPIO Setup Initialization describes the process of setting the registers state to enable the USB controller for use There are two cases where the USB registers need to be initialized When the system is powered up and the registers need to be prepared for first use The second time the registers need to be initialized is after receiving a RESET request from the host controller Refer to Section 10 2 2 USB Registers on page 96 for an example of the register initial ization sequence The S1D13A04 shares four lines between GPIO and USB use Before any accesses are made to the USB section the GPIO lines must be configured To set the GPIO lines write the binary value 0010xxxx 1101xxxx 00000000 xxxxxxxx 2xDx00xxh to REG 64h the GPIO Status and Control register Note X s represent a don t care state Depending on other system configuration i e panel technology certain don t care bits may have to be set also See the D 3A04 Hard ware
528. tput Leakage Current 1 1 uA VDD min VoH High Level Output Voltage lon 3mA Type 1 Vpp 0 4 V 6mA Type 2 VDD min VoL Low Level Output Voltage lo 3mA Type 1 0 4 V 6mA Type 2 Vin High Level Input Voltage LVTTL Level Vpp max 2 0 V Vi Low Level Input Voltage LVTTL Level Vpp min 0 8 V Rpp Pull Down Resistance Vin Vpp 20 50 120 kQ Ci Input Pin Capacitance 10 pF Co Output Pin Capacitance 10 pF Cio Bi Directional Pin Capacitance 10 pF Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 34 Epson Research and Development Vancouver Design Center 6 A C Characteristics Conditions IO Vpp 3 3V 10 Ta 40 C to 85 C Trise and Tfay for all inputs must be lt 5 nsec 10 90 CL 50pF Bus MPU Interface C OpF LCD Panel Interface 6 1 Clock Timing 6 1 1 Input Clocks Clock Input Waveform PWH Mb tw gt 90 Vin Vi 10 tp A M o ti lt Tosc gt Figure 6 1 Clock Input Requirements Table 6 1 Clock Input Requirements for CLKI when CLKI to BCLK divide gt 1 Symbol Parameter Min Max Units fosc Input Clock Frequency CLKI 100 MHz Osc Input Clock period CLKI Wosc ns town Input Clock Pulse Width High CLKI 4 5 ns towL Input Clock Pulse Width Low CLKI 4 5 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 n
529. trieved by reading from the Look Up Table Read Register Bits 31 24 are write only and will return 00h if read Note For further information on the S1D13A04 LUT architecture see the S D13A04 Hard ware Functional Specification document number X37A A 001 xx 5 2 Look Up Table Organization e The Look Up Table treats the value of a pixel as an index into an array For example a pixel value of zero would point to the first LUT entry whereas a pixel value of seven would point to the eighth LUT entry e The value contained in each LUT entry represents the intensity of the given color or gray shade This intensity can range in value from 0 to 3Fh e The S1D13A04 Look Up Table is linear This means increasing the LUT entry number results in a brighter color or gray shade For example a LUT entry of FCh in the red bank results in bright red output while a LUT entry of 1Ch results in dull red Table 5 1 Look Up Table Configurations Color Depth Look Up Table Indices Used Effective Gray RED GREEN BLUE Shades Colors 1 bpp gray 2 2 gray shades 2 bpp gray 4 4 gray shades 4 bpp gray 16 16 gray shades 8 bpp gray 64 64 gray shades 16 bpp gray 64 gray shades 1 bpp color 2 2 2 2 colors 2 bpp color 4 4 4 4 colors 4 bpp color 16 16 16 16 colors 8 bpp color 256 256 256 256 colors 16 bpp color e es 65536 colors e Indicates the Look Up Table is
530. trol Enable Register 1 REG 4048h USB Software Reset Register REG 4052h Default 00h Write Only USB Sofware Fase Code IT bits 7 0 5 4 3 2 bits 7 0 USB Software Reset Bits 7 0 Write Only When the specific code of 10100100b is written to these bits the USB module of the S1D13A04 is reset Use of the above code avoids the possibility of accidently resetting the USB USB Wait State Register REG 4054h Default 00h Read Write 058 Wait State bits 1 s 0 bits 1 0 USB Wait State Bits 1 0 This register controls the number of wait states the S1D13A04 uses for its internal USB support For all bus interfaces supported by the S1D13A04 these bits must be set to 01 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 135 Vancouver Design Center 8 5 2D Acceleration BitBLT Registers Offset 8000h These registers control the S1D13A04 2D Acceleration engine For detailed BitBLT programming instructions see the D13A04 Programming Notes and Examples document number X37A G 003 xx BitBLT Control Register REG 8000h Default 00000000h Read Write Color Dest Source Format Linear Linear Select Select Select 18 17 16 BitBLT Enable WO 0 bit 18 BitBLT Color Format Select This bit selects the color format that the 2D operation is applied to When this bit 0 8 bpp 256 color format is selected When this bit
531. ts bits 31 24 before the input configuration takes effect bit 7 GPIO7 Pin IO Status When GPIO7 is configured as an output writing a 1 to this bit drives GPIO7 high and writing a 0 to this bit drives GPIO7 low When GPIO7 is configured as an input a read from this bit returns the status of GPIO7 bit 6 GPIO6 Pin IO Status When GPIO6 is configured as an output writing a 1 to this bit drives GPIO6 high and writing a 0 to this bit drives GPIO6 low When GPIO6 is configured as an input a read from this bit returns the status of GPIO6 bit 5 GPIOS Pin IO Status When GPIOS is configured as an output writing a 1 to this bit drives GPIOS high and writing a 0 to this bit drives GPIOS low When GPIOS is configured as an input a read from this bit returns the status of GPIOS 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 113 Vancouver Design Center bit 4 GPIO4 Pin IO Status When GPIO4 is configured as an output writing a 1 to this bit drives GPIO4 high and writing a O to this bit drives GPIO4 low When GPIO4 is configured as an input a read from this bit returns the status of GPIO4 bit 3 GPIO3 Pin IO Status When the Direct HR TFT LCD interface is not selected REG OCH bits 1 0 and GPIO3 is configured as an output writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low When the Direct HR TFT LCD interface is not
532. ts 19 16 are set to OCh 6 Program the BitBLT Color Format Select bit for 16 bpp operations REG 8000h bit 18 is set to 1 7 Program the BitBLT Memory Offset Register to the ScreenStride in WORDS BltMemoryOffset ScreenStride 2 320 140h REG 8014h is set to 0140h 8 Program the BitBLT Destination Source Linear Select bits for a rectangular BitBLT BitBLT Destination Linear Select 0 BitBLT Source Linear Select 0 Start the BitBLT operation REG 8000h bit 0 is set to 1 Note The sequence of register setup is irrelevant as long as all required registers are pro grammed before the BitBLT is started 9 2 7 Transparent Write BitBLT Transparent Write BitBLTs are similar to the Write BitBLT with ROP with two differ ences first a specified color in the source data leaves the destination pixel untouched and second ROPs are not supported This operation is used to copy a bitmap image from system memory to the display buffer with one color marked as transparent Pixels of the transparent color are not transferred This allows fast display of non rectangular or masked images For example consider a source bitmap having a red circle on a blue background By selecting the blue as the trans parent color and using the Transparent Write BitBLT on the whole rectangle the effect is a BitBLT of the red circle only During a Transparent Write BitBLT operation the BitBLT engine expects to receive a particular number of WORDs a
533. ts 9 0 1 Note For passive panels these bits must be programmed such that the following formula is valid HPW HPS lt HT Note See Section 6 4 Display Interface on page 56 Vertical Total Register REG 30h Default 00000000h Read Write VERE Total bits 9 0 bits 9 0 Vertical Total Bits 9 0 These bits specify the LCD panel Vertical Total period in 1 line resolution The Vertical Total is the sum of the Vertical Display Period and the Vertical Non Display Period The maximum Vertical Total is 1024 lines REG 30h bits 9 0 Vertical Total in number of lines 1 Note This register must be programmed such that the following formula is valid VDPS VDP lt VT 2 See Section 6 4 Display Interface on page 56 Vertical Display Period Register REG 34h Default 00000000h Read Write lene a ei ie bits 9 0 Vertical Display Period Bits 9 0 These bits specify the LCD panel Vertical Display period in 1 line resolution The Vertical Display period should be less than the Vertical Total to allow for a sufficient Vertical Non Display period REG 34h bits 9 0 Vertical Display Period in number of lines 1 Note This register must be programmed such that the following formula is valid VDPS VDP lt VT 2See Section 6 4 Display Interface on page 56 S1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 103 Vanc
534. ttings you chose in the Clocks tab of the 13A04CFG program For more information on setting the clocks see the 13A04CFG User Manual document number X37A B 001 xx If you run the S1D13A04 with a single clock source make sure your clock sources for PCLK BCLK and MCLK are correctly set to use the correct clock input source Also ensure that you enable the clock dividers as required for different display hardware If you are using 13A04CFG EXE to produce multiple MODE tables make sure you change the Mode Number setting for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number For more information on setting the mode number see the 3A04CFG User Manual document number X37A B 001 xx The 13A04CFG program assumes you are using the S3U13A04B00C evaluation board and defaults the Panel Power control to GPIOO 13A04CFG allows you to change the GPIO pin used to control panel power or to disable the use of GPIO pins altogether If this is changed from the default your driver will no longer be able to control panel power on the S5U13A04B00C evaluation board and your panel may not be powered up correctly At this time the driver has been tested on the x86 CPUs and have been run with Plat form Builder v3 00 Windows CE 3 x Display Driver Issue Date 01 10 19 EPSON 1D13A04 LCD USB Companion Chip Windows CE 3 x USB Driver Document Number X37A E 007
535. tup This routine loads the driver required to access the S1D13A04 locates the and returns the address of halAcquireController the controller Initializes the controller for use This includes setting the programmable clock and initializing registers as haliniteontroller well as setting the lookup table and clearing video memory Memory Access halReadDisplay8 Reads one byte from display memory halReadDisplay16 Reads one word from display memory halReadDisplay32 Reads one double word from display memory halWriteDisplay8 Writes one byte to display memory halWriteDisplay16 Writes on word to display memory halWriteDisplay32 Writes on double word to display memory Register Access halReadReg8 Reads one byte from a control register halReadReg16 Reads one word from a control register halReadReg32 Reads one dword from a control register halWriteReg8 Writes one byte to a control register halWriteReg16 Writes one word to a control register halWriteReg32 Writes one dword to a control registers Clock Support halSetClock Programs the ICD2061A Programmable Clock Generator halGetClock Returns the frequency of the requested ICD2061A clock Miscellaneous halGetVersionInfo Returns a standardized startup banner message halGetLastError Returns the numerical value of the last error and optionally an ASCII string describing the error hallnitLUT This routine
536. tup is irrelevant as long as all relevant registers are programmed before the BitBLT is initiated Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 84 Epson Research and Development Vancouver Design Center 9 2 9 Pattern Fill BitBLT with ROP 1D13A04 X37A G 003 05 The Pattern Fill BitBLT with ROP fills a specified area of display memory with a pattern The pattern is repeated until the fill area is completely filled The fill pattern is limited to an eight by eight pixel array and must be loaded to off screen video memory before starting the BitBLT The pattern can be logically combined with the destination using any of the 16 ROP codes but typically the copy pattern ROP is used ROP code OCh A pattern is defined to be an array of 8x8 pixels and the pattern data must be stored in consecutive bytes of display memory 64 consecutive bytes for 8 bpp color depths and 128 bytes for 16 bpp color depths For 8 bpp color depths the pattern must begin on a 64 byte boundary for 16 bpp color depths the pattern must begin on a 128 byte boundary This operation is self completing Once the parameters have been entered and the BitBLT started the BitBLT engine will fill all of the specified memory with the pattern To fill an area using the pattern BitBLT the BitBLT engine requires the location of the pattern the destination rectangle position and size and the ROP code The BitBLT engine also needs to know whi
537. uation Board Hardware Connections 16 4 3 S1D13A04 Hardware Configuration e 18 4 4 Register Memory Mapping 2 18 4 5 MPC82x Chip Select Configuration 19 4 6 TestSoftware 2 aai a Aea aa a a ee ee ee 20 SoftWare ais bo ea OL Pe eee ee ne Rare ele 21 References oos as Se A ae ee ee Ae re A DE a 22 6 1 Documents 2 5 8038 SA ee hoe RO ey Ee A ee ea ED 6 2 DocumentSources s s aps e 2 piad a ee ee 22 7 Sales and Technical Support ee 23 7 1 EPSON LCD USB Companion Chips SID13A04 23 7 2 Motorola MPC821 Processor 2 a a aa eee 23 Interfacing to the Motorola MPC82x Microprocessor 1D13A04 Issue Date 01 10 05 X37A G 009 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 00 02000020008 13 Table 4 1 List of Connections from MPC821ADS to SID13A04 o o o ooo 16 Table 4 2 Summary of Power On Reset Options 0 000002 2 2 eee 18 List of Figures Figure 2 1 PowerPC Memory Read Cycle 0 2 0 0 0 00000000084 9 Figure 2 2 PowerPC Memory Write Cycle o o 0000000000000 10 Figure 2 3 GPCM Me
538. uct code is 001011 OBh bits 1 0 Revision Code These are read only bits that indicates the revision code The revision code is 00 Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 92 Epson Research and Development Vancouver Design Center 8 3 2 Clock Configuration Registers Memory Clock Configuration Register REG 04h Default 00000000h Read Write n a 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MCLK Divide Ne Select bits 1 0 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bits 5 4 MCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Memory Clock MCLK from the Bus Clock BCLK Table 8 3 MCLK Divide Selection MCLK Divide Select Bits BCLK to MCLK Frequency Ratio 00 1 1 01 2 1 10 3 1 11 4 1 bit O Reserved This bit must be set to 0 Pixel Clock Configuration Register REG 08h Default 00000000h Read Write SLR oa bits 6 4 PCLK Divide Select Bits 1 0 These bits determine the divide used to generate the Pixel Clock PCLK from the Pixel Clock Source Table 8 4 PCLK Divide Selection PCLK Divide Select Bits PCLK Source to PCLK Frequency Ratio 000 1 1 001 2 1 010 3 1 011 4 1 100 8 1 101 111 Reserved 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 93 Vancouver Des
539. ue of the CLKI frequency If Enable clock chip support is selected on the General Tab then this value may differ slightly from the value entered in the timing control This setting determines the frequency of CLKI2 Set this value by selecting a preset frequency from the drop down list or entering the desired frequency MHz in the edit box This field displays the actual value of the CLKI2 frequency If Enable clock chip support is selected on the General Tab then this value may differ slightly from the value entered in the timing control These settings select the clock source and divisor for the internal pixel clock PCLK Selects the PCLK source Possible sources include CLKI CLKI2 BCLK or MCLK Note that BCLK and MCLK may be previously divided from CLKI or CLKI2 Specifies the divide ratio for the clock source The divide ratio is applied to the PCLK source to derive PCLK Selecting Auto for the divisor allows the configu ration program to calculate the best clock divisor Unless a very specific clocking is being specified it is best to leave this setting on Auto This field shows the actual PCLK used by the configu ration process 1D13A04 X37A B 001 01 Page 12 BCLK Source Divide Timing MCLK Source Divide Timing 1D13A04 X37A B 001 01 Epson Research and Development Vancouver Design Center These settings select the clock source and divisor for the internal
540. ues with USB transfers when using the S1D13A04 USB controller 10 4 1 EP4 NAK Status not set correctly in USB Status Register The EP4 NAK status bit is not set in the USB Status Register REG4032h when the S1D13A04 responds to an IN request on EP4 with a NAK As a result a local CPU receiving an EP4 Packet Transmitted interrupt may mistakenly believe a bus error occurred in the most recently transmitted packet Work Around Disable the EP4 Packet Transmitted interrupt when no data is queued for transmission to the local CPU The basic flow is In Chip Initialization Code Do not enable EP4 Packet Transmitted bit in Interrupt Enable Register 0 REG 4002h When Local Side Wishes to Send Data 1 Put data to transmit in FIFO 2 Enable EP4 Packet Transmitted bit in Interrupt Enable Register 0 3 Set FIFO Valid if using FIFO Valid Mode TRUE See Section 10 4 2 on page 107 for more information on setting the FIFO Valid 4 Clear EP4 Packet Transmitted status bit in Interrupt Status Register 0 REG 4004 Note Step 4 is time critical It must be performed within 5 us after Step 3 In Packet Transmitted Interrupt Routine Disable EP4 Packet Transmitted bit in Interrupt Enable Register 0 S1D13A04 Programming Notes and Examples X37A G 003 05 Issue Date 2002 08 21 Epson Research and Development Page 107 Vancouver Design Center 10 4 2 Write to EP4 FIFO Valid bit cleared by NAK After the loc
541. uggested LUT Values for 4 bpp Color Index Red Green Blue 00 00 00 00 01 00 00 AA 02 00 AA 00 03 00 AA AA 04 AA 00 00 05 AA 00 AA 06 AA AA 00 07 AA AA AA 08 00 00 00 09 00 00 FF 0A 00 FF 00 0B 00 FF FF 0C FF 00 00 OD FF 00 FF OE FF FF 00 OF FF FF FF 10 FF iF Indicates unused entries in the LUT Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 24 8 bpp color Epson Research and Development Vancouver Design Center When the S1D13A04 is configured for 8 bpp color mode all 256 entries in the LUT are used The S1D13A04 LUT has six bits 64 intensities of intensity control per primary color which is the same as a standard VGA RAMDAC The following table shows LUT values that simulate the VGA default color palette Table 5 9 Suggested LUT Values 8 bpp Color Index R G B Index R G B Index R G B Index R G B 00 00 00 00 40 00 00 00 80 FF FF 00 CO 00 00 00 01 00 00 AA 41 00 00 11 81 FF EF 00 C1 00 11 11 02 00 AA 00 42 00 00 22 82 FF DE 00 C2 00 22 22 03 00 AA AA 43 00 00 33 83 FF CD 00 C3 00 33 33 04 AA 00 00 44 00 00 44 84 FF BC 00 C4 00 44 44 05 AA 00 AA 45 00 00 55 85 FF AB 00 C5 00 55 55 06 AA AA 00 46 00 00 66 86 FF 9A 00 C6 00 66 66 07 AA AA AA 47 00 00 77 87 FF
542. uide Issue Date 01 04 17 Epson Research and Development Page 5 Vancouver Design Center Windows 98 ME All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Windows will detect the new hardware as a new PCI Device and bring up the ADD NEW HARDWARE dialog box 3 Click NEXT 4 Windows will look for the driver When Windows does not find the driver it will al low you to specify the location of it Type the driver location or select BROWSE to find it 5 Click NEXT 6 Windows will open the installation file and show the option EPSON PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Goto the CONTROL PANEL and double click on ADD NEW HARDWARE to launch the ADD NEW HARDWARE WIZARD Click NEXT 3 Windows will attempt to detect any new plug and play device and fail Click NEXT 4 Windows will ask you to let it detect the hardware or allow you to select from a list Select NO I WANT TO SELECT THE HARDWARE FROM A LIST and click NEXT 5 From the list select OTHER DEVICES and click NEXT 6 Click HAVE DISK and type the path to the driver files or select browse to find the driver 7 Click OK 8 The driver will be identified as EPSON PCI Bridge Card Click NEXT 9 Click FINISH S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 6
543. uired to set the screen resolution col or depth bpp display type display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the console driver If the default does not match the configura tion you are building for then MODEO H will have to be regenerated with the correct information Use the program 13A04CFG to generate the header file For information on how to use 13A04CKG refer to the 13A04CFG Configuration Program User Manual docu ment number X37A B 001 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header File for S1D13A04 WinCE Driver option Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the original con figuration file From the Platform window click the ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking the sign at the root of the tree Expand the the WINCE300 tree and click on Hardware Specific Files then double click PLAT FORM REG Edit the file PLATFORM REG to match the screen resolution color depth and rotation information in MODEO H For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp and a SwivelView mode of 0 landscape Default for EPSON Display Driver 320x240 at 8 bits pixel
544. vice Driver Installation Guide This manual describes the installation of the Windows 9x ME NT 4 0 2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards The file SID13XXX VXD is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x ME The file SID13XXX SYS is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows NT 4 0 2000 The file S1ID13XXX INF is the install script For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Video Controller S1D13xxx Display Type N A BIOS N A DOS Program No Dos Version N A Windows Program Yes Windows 9x ME NT 4 0 2000 device driver Windows DOS Box N A Windows Full Screen N A 0S 2 N A Installation Windows NT Version 4 0 All evaluation boards require the driver to be installed as follows 1 2 Install the evaluation board in the computer and boot the computer Copy the files SID13XXX INF and S1D13XXX SYS to a directory on a local hard drive Right click your mouse on the file S1D13XXX INF and select INSTALL from the menu Windows will install the device driver and ask you to restart S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Pag
545. view of the operation of the CPU bus in order to establish interface requirements 2 2 MPC8xx Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the
546. vision 6 0 Epson Research and Development Page 159 Vancouver Design Center 15 Power Save Mode A software initiated Power Save Mode is incorporated into the S1D13A04 to accommodate the need for power reduction in the hand held devices market This mode is enable via the Power Save Mode Enable bit REG 14h bit 4 Software Power Save Mode saves power by powering down the control signals and stopping display refresh accesses to the display buffer For programming information on disabling the clocks see the S D13A04 Programming Notes and Examples document number X37A G 003 xx Table 15 1 Power Save Mode Function Summary Software Power Save Normal IO Access Possible Yes Yes Memory Writes Possible Yes Yes Memory Reads Possible No Yes Look Up Table Registers Access Possible Yes Yes USB Registers Access Possible No Yes Display Active No Yes LCD I F Outputs Forced Low Active PWMCLK Stopped Active Access Possible for GPIO pins configured for HR TFT Forced Low Active Access Possible for GPIO Pins configured as GPIOs Yes Yes USB Running No Yes Note 1 When power save mode is enabled the memory controller is powered down and the status of the memory controller is indicated by the Memory Controller Power Save Sta tus bit REG 14h bit 6 However memory writes are possible during power save mode because the S1D13A04 dynamically enables the memory controller for display buffer wr
547. w Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to the Motorola MPC82x Microprocessor Issue Date 01 10 05 S1D13A04 X37A G 009 01 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MPC82x Microprocessor X37A G 009 01 Issue Date 01 10 05 EPSON 1D13A04 LCD USB Companion Chip Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X37A G 010 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK 1D13A04 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X37A G 010 01 Issue Date 01 10 12 Epson Research
548. was acknowledged with a NAK Writing a 1 clears this bit bit 4 USB Endpoint 4 ACK The last USB packet transmitted IN packet was successfully acknowledged with an ACK from the USB host Writing a 1 clears this bit bit 3 USB Endpoint 3 STALL The last USB packet received OUT packet could not be accepted because the endpoint was stalled REG 4000h bit 3 set and was acknowledged with a STALL Writing a 1 clears this bit bit 2 USB Endpoint 3 NAK The last USB packet received OUT packet could not be accepted and was acknowledged with a NAK Writing a 1 clears this bit bit 1 USB Endpoint 3 ACK The last USB packet received OUT packet was successfully acknowledged with an ACK Writing a 1 clears this bit bitO Endpoint 2 Valid When this bit is set the 8 byte endpoint 2 mailbox registers have been written by the local CPU but not yet read by the USB host The local CPU should not write into these registers while this bit is set Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 126 Epson Research and Development Vancouver Design Center Frame Counter MSB Register REG 4034h Default 00h Read Only 15 18 9 8 n a Frame Counter bits 10 8 Uh 5 1 0 Frame Counter LSB Register REG 4036h Default 00h Read Only 15 18 Frame Counter bits 7 0 7 6 5 4 3 2 1 0 bits 10 0 Frame Counter Bits 10 0 This register contains the frame counter from the most recent start
549. was jammed together with one row immediately following the next in display memory can now be expanded back to a rectangular area When this bit 0 the BitBLT source is stored as a rectangular region of memory When this bit 1 the BitBLT source is stored as a contiguous linear block of memory This bit is write only Setting this bit to 1 begins the 2D BitBLT operation This bit must not be set to 0 while a BitBLT operation is in progress Note To determine the status of a BitBLT operation use the BitBLT Busy Status bit REG 8004h bit 0 Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 60 Epson Research and Development Vancouver Design Center BitBLT Status Register andes Default 00000000h Read Only Number of Used FIFO Entries Number of Free FIFO Entries 0 means full 22 18 17 16 FO Full Status BitBLT Busy Status 0 Number of Used FIFO Entries This is a read only status This field indicates the minimum number of FIFO entries currently in use there may be more in the internal pipeline If these bits return a 0 the FIFO is empty Number of Free FIFO Entries This is a read only status bit This field indicates the number of empty FIFO entries available If these bits return a 0 the FIFO is full FIFO Not Empty This is a read only status bit When this bit 0 the BitBLT FIFO is empty When this bit 1 the BitBLT FiFO has at least one data To reduce system
550. window image starting at address O and followed by the PIP window image In addition both images must start at addresses which are dword aligned the last two bits of the starting address must be 0 Note It is possible to use the same image for both the main window and PIP window To do so set the PIP Line Address Offset register REG 54h to the same value as the Main Window Line Address Offset register REG 44h Programming Notes and Examples S1D13A04 Issue Date 2002 08 21 X37A G 003 05 Page 52 1D13A04 X37A G 003 05 Epson Research and Development Vancouver Design Center Example 7 In SwivelView 180 program the PIP window registers for a 320x240 panel at 4 bpp with the PIP window positioned at SwivelView 180 co ordinates 80 60 with a width of 160 and a height of 120 1 Determine the value for the PIP Window X Positions and PIP Window Y Positions registers Let the top left corner of the PIP window be x1 y1 and let the bottom right corner be x2 y2 where x2 x1 width 1 and y2 y1 height 1 The PIP Window X Positions register sets the horizontal coordinates of the PIP window s bottom right and top left corner The PIP Window Y Positions register sets the verti cal coordinates of the PIP window s bottom right and top left corner The required values are calculated as follows X Start Position panel width x2 1 32 bpp 320 80 160 1 1 32 4 10 0
551. x registers The register being accessed is selected by the Endpoint 2 Index register The eight Transmit Mailbox registers are written by the local CPU and are read by a USB transfer from endpoint 2 The format and content of the messages are user defined If enabled USB reads from this reg ister can generate an interrupt Endpoint 2 Interrupt Polling Interval Register REG 401Ch Default FFh Read Write n a 15 14 13 12 11 10 9 8 Interrupt Polling Interval bits 7 0 7 6 5 4 3 2 1 0 bits 7 0 Interrupt Polling Interval Bits 7 0 This register specifies the Endpoint 2 interrupt polling interval in milliseconds It can be read by the host through the endpoint 2 descriptor Endpoint 3 Receive FIFO Data Register REG 4020h Default 00h Read Only n a Endpoint 3 Receive FIFO Data bits 7 0 bits7 0 Endpoint 3 Receive FIFO Data Bits 7 0 This register is used by the local CPU to read USB receive FIFO data The FIFO data is written by the USB host using bulk or isochronous transfers to endpoint 3 Endpoint 3 Receive FIFO Count Register REG 4022h Default 00h Read Only n a Receive FIFO Count bits 7 0 bits 7 0 Receive FIFO Count Bits 7 0 This register returns the number of receive FIFO entries containing valid entries Values range from 0 empty to 64 full 1D13A04 Hardware Functional Specification X37A A 001 06 Issue Date 2003 05 01 Revision 6 0 Epson Research and Development Page 123 Vancouver Design
552. x86 libffb so For the loader to locate them the files need to be renamed and copied to the lib directory 1 Rename libdisputil so to libdisputil so 1 and libffb so to libffb so 1 2 Copy the files new files libdisputil so 1 and libffb so 1 to the directory usr lib 3 Copy the file devg S1D13A04 so to the lib dll directory Note To locate the file devg S1D13A04 so watch the output of the true command during the makefile build Modify the trap file graphics modes in the etc system config directory by inserting the following lines at the top of the file io graphics dldevg S1D13A04 s0 gWxHxC I0 d0x0 0x0 640 480 8 Epson io graphics dldevg S1D13A04 so gWxHxC I0 d0x0 0x0 640 480 16 Epson Where W is the configured width of the display H is the configured height of the display C is the color depth in bpp either 8 or 16 QNX Photon v2 0 Display Driver S1D13A04 Issue Date 01 10 19 X37A E 005 01 Page 6 Comments 1D13A04 X37A E 005 01 Epson Research and Development Vancouver Design Center Run the Driver Note For the remaining steps the S3U13A04B00C evaluation board must be installed on the test platform It is recommended that the driver be verified before starting ONX with the S1D13A04 as the primary display To verify the driver type the following command at the root of the Project source tree gddk_1 0 directory util bench nto x86 0 devg bench dldevg S 1D13A04 nto x86 dll devg S 1D13A04 so
553. y Note This pin should be tied to the inactive voltage level as selected by CNF5 using a pull up or pull down resistor If CNF5 1 the WAIT pin should be tied low using a pull down resistor If CNF5 0 the WAIT pin should be tied high using a pull up resistor If WAIT is not used this pin should be tied either high or low using a pull up or pull down resistor Active low input to set all internal registers to the default state RESET El 16 e and to force all signals to their inactive states Hardware Functional Specification S1D13A04 Issue Date 2003 05 01 X37A A 001 06 Revision 6 0 Page 26 4 3 2 LCD Interface Epson Research and Development Vancouver Design Center Table 4 3 LCD Interface Pin Descriptions Pin Name Type PFBGA Pin TQFP15 Pin Cell RESET State Description FPDAT 17 0 C10 D9 D 10 D 11 D 8 E9 E10 E11 E8 F 7 F10 F8 G7 G11 G 10 G9 G8 H11 71 77 82 92 LB3P Panel Data bits 17 0 FPFRAME J9 68 LB3P This output pin has multiple functions e Frame Pulse e SPS for Direct HR TFT See Table 4 6 LCD Interface Pin Mapping on page 32 for summary FPLINE H9 69 LB3P This output pin has multiple functions e Line Pulse e LP for Direct HR TFT See Table 4 6 LCD Interface Pin Mapping on page 32 for summary FPSHIFT H10 70 LB3P This output pin has multiple funct
554. y TOE EZ TODO FEST sq lt gt a soquay uounoog 928 MS did vooarovetais 0 i ney Sooavovernss Em saM a300 ZZZZZZ SSA anao PPO OOO ss 2 Te anoo SSA nro no nro no nro no aset pT Pt mmo SSA 80 10 90 0 zo 19 mr anon SSA anon SSA nzo 7 amon PH mon nasar y OTOH um Y mM or es ae AEE O 4 4 Hnos away oN mam nam N oan am ON Wau Was 458 458 A K Hen E ee 59 89 37 sie gD 90100 or vOldD A DES oogsn zoo zono LN gg nowa pro no en E losia eT zo sisa 10149 visa ds noes Cus yore 25 OEE y lio Sad oe ey A O asa ziga a ss 1180 pO ms orga ga vives 680 e os 80 280 Livada 980 dla MS 91 1W0d4 sea noo Y stivads veo tvaad ead Or 94ND L1VOda zaa ul E Sano ziavaas 180 111vad 080 se 7 EJNO OL 1W0da us z SANO 61v0dW4 a LAND 81v0d4 la ONO 21W0d4 pz suvads wy 008 uy my wy ty muaa vemo Qesst Lesat esos Lessel Lost Lesat nod Lvgd3 zuvadd Luvads ouwad nets 94No sano vano EJNO zano Figure 10 1 SIDIS3A04B0O0C Schematics 1 of 6 S5U13A04B00C Rev 1 0 Evaluation Board User Manual 1D13A04 Issue Date 02 01 28 X37A G 004 02 Epson Research and Development Page 27 Vancouver Design Center y FS 5l x fal 3 3 E A g si El o 53 5 lo E 3 4 e 3 So loa E g lo i 2 El gi 8 22 gt 3 g
555. y with a DC offset voltage offset typically 9 0V The AC component is the common electrode driving signal Vcom which has a voltage of 2 5V Veco must be alternated every horizontal period and every vertical period The S1D13A04 output signal REV accomplishes this function and generates the alternating Vcom signal which is superimposed onto Vpr Figure 2 3 Panel Gate Driver AC Power Supplies on page 10 shows the schematic for generating Vcom and VER c1 vik u2 22uF 16V TEE f rev gt NG N D2 ma PS P D1 225 4 ry 180 P f vss VEE GF cer pe ae PR a gt Y Foe 15K 5 Y Ra 27K 5 al cz AR 22uF 16v y As 12K 5 vat Esa a L gt pveou 100K Ranen Re a 225 1 a2 08 NP o1uFS R7 120K 5 Figure 2 3 Panel Gate Driver AC Power Supplies Connecting to the Sharp HR TFT Panels Issue Date 01 10 12 Epson Research and Development Page 11 Vancouver Design Center 2 2 HR TFT MOD Signal The HR TFT panel uses an input signal MOD to control the power on sequencing of the panel This HR TFT signal should not be confused with the S1D13A04 signal DRDY referred to as MOD for passive panels To power on the HR TFT panel MOD must be held low until the power supply has been turned on for more than two FRAMES To power off the HR TFT panel MOD must be forced low before the power supply is turned off This sequencing requires two software

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