PCF8591 8-bit A/D and D/A converter
Contents
1. C BUS D PCF8591 8 bit A D and D A converter Rev 7 27 June 2013 Product data sheet 1 General description The PCF8591 is a single chip single supply low power 8 bit CMOS data acquisition device with four analog inputs one analog output and a serial I C bus interface Three address pins AO A1 and A2 are used for programming the hardware address allowing the use of up to eight devices connected to the C bus without additional hardware Address control and data to and from the device are transferred serially via the two line bidirectional I C bus The functions of the device include analog input multiplexing on chip track and hold function 8 bit analog to digital conversion and an 8 bit digital to analog conversion The maximum conversion rate is given by the maximum speed of the I2C bus 2 Features and benefits 3 Applications Single power supply Operating supply voltage 2 5 V to 6 0 V Low standby current Serial input and output via 1 C bus I2C address selection by 3 hardware address pins Max sampling rate given by I2C bus speed 4 analog inputs configurable as single ended or differential inputs Auto incremented channel selection Analog voltage range from Vss to Vpp On chip track and hold circuit 8 bit successive approximation A D conversion Multiplying DAC with one analog output Supply monitoring Reference setting Analog control loops NXP Semiconductors PC2. Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 19 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus logo is a trademark of NXP B V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 28 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 21 Tables Table 1 Ordering information 00 2 Table 2 Ordering options 00 eee 2 Table 3 Marking codes 00 eee ee eee 2 Table 4 Pin description 0 000e ee eaee 4 Table 5 12C slave address byte 13 Table 6 R W bit description 13 Table 7 Limiting values 0 eee eee 16 Table 8 Characteristics 00000 e eee 17 Table 9 D A characteristics 0 18 Table 10 A D characteristics 0 18 Table 11 Dynamic characteristics 20 Table 12 SnPb eutectic process from J STD 020D 24 Table 13 Lead
3. us tup pat data hold time 0 us tvp pat data valid time 3 4 us tsu sto set up time for STOP condition 4 0 us 1 A detailed description of the 12C bus specification with applications is given in Ref 11 UM10204 START BIT 7 BIT 6 BITO ACKNOWLEDGE STOP PROTOCOL CONDITION MSB A6 LSB A CONDITION S A7 R W P tSU STA tLow tHIGH a 1 sci SCL SDA tHD STA tSU DAT tHD DAT tvD DAT tsu sTo mbd820 Fig 21 1 C bus timing diagram rise and fall times refer to Vi and Vip PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 20 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 15 Package outline DIP16 plastic dual in line package 16 leads 300 mil SOT38 4 lt seating plane i no 0 5 10mm scale DIMENSIONS inch dimensions are derived from the original mm dimensions A Ay A2 1 1 z UNIT max mid max b by b2 c D EM e ey L Me My w ee 1 73 0 53 1 25 0 36 19 50 6 48 3 60 8 25 10 0 an 0 51 ka 1 30 0 38 0 85 0 23 18 55 6 20 ai S 3 05 7 80 8 3 0 254 0 76 0 068 0 021 0 049 0 014 0 77 0 26 0 14 0 32 0 39 inches Oe
4. NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 16 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 14 Characteristics 14 1 Static characteristics Table 8 Characteristics Vpop 2 5 V to 6 0 V Vss 0 Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Supply Vop supply voltage 2 5 lbp supply current standby V Vss or Vpp no load 1 operating fsck 100 kHz AOUT off 125 AOUT active 0 45 Vpor power on reset 01 0 8 voltage Digital in and outputs SCL SDA AO A1 A2 Vit LOW level input 0 voltage Vin HIGH level input 0 7xVpp voltage IL leakage current Vi Vss to Vpp AO A1 A2 250 SCL SDA 1 Ci input capacitance lot LOW level output VoL 0 4 V 3 0 current Reference voltage inputs Viet reference voltage Vref gt VaGND 2 Vss 1 6 VAGND voltage on pin AGND Vret gt VaGno 2 Vss lu input leakage current 250 Rret reference resistance pins Vaer and AGND 100 Oscillator OSC EXT lu input leakage current fosc oscillator frequency 0 75 Max 6 0 250 1 0 2 0 0 3 x Vpp 250 1 Vpp Vpp 0 8 250 250 1 25 Unit uA uA mA nA uA pF mA nA kQ nA MHz 1 The power on reset circuit resets the I2C bus logic when Vpp is less than Vpop V ett VAGND 2 A further extension of the range is possible if the following conditions are fulfill
5. This allows the internal oscillator to run continuously by this means preventing conversion errors resulting from oscillator start up delay The analog output enable flag can be reset at other times to reduce quiescent power consumption The selection of a non existing input channel results in the highest available channel number being allocated Therefore if the auto increment flag is set the next selected channel is always channel 0 The most significant bits of both nibbles are reserved for possible future functions and must be set to logic 0 After a Power On Reset POR condition all bits of the control register are reset to logic 0 The D A converter and the oscillator are disabled for power saving The analog output is switched to a high impedance state All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 5 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter MSB LSB P TxD DoT a oros cr gas A D CHANNEL NUMBER 00 channel 0 01 channel 1 10 channel 2 11 channel 3 AUTO INCREMENT FLAG active if 1 ANALOG INPUT PROGRAMMING 00 four single ended inputs AINO channel 0 AIN1 channel 1 AIN2 channel 2 AIN3 channel 3 three differential inputs AINO 0 channel 0 RINI P channel 1 AIN2 AIN3 10 single ended and differential mixed AINO channel 0 AIN1 channel 1 AIN
6. e A slave receiver which is addressed must generate an acknowledge after the reception of each byte e Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter e The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse set up and hold times must be considered A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition Acknowledgement on the I2C bus is shown in Figure 14 data output by transmitter NAA A AA J a _______ data output by receiver SCL from ca co ae co master Ls S START condition Fig 14 Acknowledgement on the I2C bus not acknowledge iN 7 acknowledge 4 S N clock pulse for acknowledgement mbc602 9 5 I C bus protocol After a START condition the 12C slave address has to be sent to the PCF8591 device PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 12 of 31 NXP Semiconductors PCF8591 PCF8591 8 bit A D and D
7. full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 19 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of an
8. 0 02 NaS 0 051 0 015 0 033 0 009 0 73 0 24 es ee 0 12 0 31 0 33 il 0 03 Note 1 Plastic or metal protrusions of 0 25 mm 0 01 inch maximum per side are not included REFERENCES OUTLINE EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 95 0444 SOT38 4 E 03 02 13 Fig 22 DIP16 plastic dual in line package 16 leads 300 mil PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 21 of 31 PCF8591 NXP Semiconductors 8 bit A D and D A converter S016 plastic small outline package 16 leads body width 7 5 mm SOT162 1 i of A As u i eo f H Lp pin 1 index lt gt detail X 0 5 DESS AE e S a ol C A scale DIMENSIONS inch dimensions are derived from the original mm dimensions UNIT A A1 A2 A3 max 0 3 10 5 7 6 2 65 os 0 29 10 1 7 4 0 41 0 30 inches 0 1 0 01 0 40 0 29 bp c DM EM e He Note 1 Plastic or metal protrusions of 0 15 mm 0 006 inch maximum per side are not included OUTLINE REFERENCES EUROPEAN PROJECTION a VERSION IEC JEDEC JEITA SOT162 1 075E03 MS 013
9. 11 Bit transfer START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy A HIGH to LOW transition of the data line while the clock is HIGH is defined as the START condition S A LOW to HIGH transition of the data line while the clock is HIGH is defined as the STOP condition P see Figure 12 econo fee ia i nE Ss ba SDA i d i SDA pa I I oe I oe SCL l i i SCL S IP ee Pe START condition STOP condition mbc622 Fig 12 Definition of START and STOP conditions System configuration A device generating a message is a transmitter a device receiving a message is a receiver The device that controls the message is the master and the devices which are controlled by the master are the slaves see Figure 13 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 11 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter MASTER SLAVE MASTER MASTER TRANSMITTER oes TRANSMITTER ee alee TRANSMITTER RECEIVER RECEIVER RECEIVER SDA SCL mga807 Fig 13 System configuration 9 4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited Each byte of 8 bits is followed by an acknowledge cycle
10. 80h The protocol of an l2C bus read cycle is shown in Section 9 The maximum A D conversion rate is given by the actual speed of the I C bus HEX code FE Visb VREF VAGND 256 254 255 Vain VAGND gt Visb mbl830 Fig 9 A D conversion characteristics of single ended inputs All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 9 of 31 NXP Semiconductors PCF8591 PCF8591 8 5 8 6 8 bit A D and D A converter HEX CODE 127 VAIN VAIN 128 127 a 5 Visb VREF VAGND 256 Visb 80 mbl831 Fig 10 A D conversion characteristics of differential inputs Reference voltage For the D A and A D conversion either a stable external voltage reference or the supply voltage must be applied to the resistor divider chain pins Vref and AGND The AGND pin has to be connected to the system analog ground It may have a DC off set with reference to Vss A low frequency can be applied to the Vger and AGND pins This allows the use of the D A converter as a one quadrant multiplier see Section 10 and Figure 6 The A D converter can also be used as a one or two quadrant analog divider The analog input voltage is divided by the reference voltage The result is converted to a binary code In th
11. AOUT is shown in Figure 6 The waveforms of a D A conversion sequence are shown in Figure 7 DAC out VREF R256 R255 R3 DECODER R2 R1 AGND aaa 008025 Fig 5 DAC resistor divider chain MSB LSB DAC data or oso oe oro VAOUT VVREF VAGND J vi V V ___ _ Di x 2 jj VDD AOUT VAGND 356 2 A V VREF ae a a a yon a a en A a wee VAGND Vss eae Ae a 00 01 02 03 04 FE FF DAC hex aaa 008027 Fig 6 DAC data and DC conversion characteristics PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 7 of 31 PCF8591 8 bit A D and D A converter NXP Semiconductors protocol ADDRESS ofa CONTROL BYTE DATA BYTE 1 DATA BYTE 2 a VAUVA AUAA JUUA JUUA JUVA 1 2 8 9 1 9 1 9 1 VaouT high impedance state of previous value held previous value held in DAC register in DAC register value of data byter time aaa 008037 Fig 7 D A conversion sequence 8 4 A D conversion The A D converter uses the successive approximation conversion technique The on chip D A converter and a high gain comparator are used temporarily during an A D conversion cycle An A D conversion cycle is always started after sending a valid read mode address to a PCF85
12. E rer Fig 23 S016 plastic small outline package 16 leads body width 7 5 mm All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved PCF8591 Product data sheet Rev 7 27 June 2013 22 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 16 Soldering of SMD packages 16 1 16 2 This text provides a very brief insight into a complex technology A more in depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards PCBs to form electrical circuits The soldered joint provides both the mechanical and the electrical connection There is no single soldering method that is ideal for all IC packages Wave soldering is often preferred when through hole and Surface Mount Devices SMDs are mixed on one printed wiring board however it is not suitable for fine pitch SMDs Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder The wave soldering process is suitable for the following e Through hole components e Leaded o
13. 1 D A output D A output impedance impedance Q Q 400 400 300 300 200 200 100 100 0 0 Oh 2h 4h 6h 8h OAh BOh COh DOh EOh FOh FFh hex input code hex input code a Output impedance near negative power rail b Output impedance near positive power rail Tamb Tamb 27 x C 27 x C Fig 20 Output impedance of analog output buffer near power rails PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 19 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 14 4 Dynamic characteristics Table 11 Dynamic characteristics All timing characteristics are valid within the operating supply voltage and ambient temperature range and reference to Vi and Vj with an input voltage swing of Vss to Vpp Symbol Parameter Min Typ Max Unit I2C bus timing see Figure 21 i fscL SCL clock frequency 100 kHz tsp pulse width of spikes that must be 100 ns suppressed by the input filter tBUF bus free time between a STOP and START 4 7 us condition tsu sta Set up time for a repeated START condition 4 7 us tuo sta hold time repeated START condition 4 0 us tLow LOW period of the SCL clock 4 7 us tHIGH HIGH period of the SCL clock 4 0 us tr rise time of both SDA and SCL signals 1 0 us tr fall time of both SDA and SCL signals 0 3 us tsu pat data set up time 250
14. 2 Lf channel 2 AIN3 11 two differential inputs AINO channel 2 PD channel 0 AIN1 AIN2 PD channel 1 AIN3 ANALOG OUTPUT ENABLE FLAG analog output active if 1 aaa 008019 Fig 4 Control byte 8 3 D A conversion The third byte sent to a PCF8591 device is stored in the DAC data register and is converted to the corresponding analog voltage using the on chip D A converter This D A converter consists of a resistor divider chain connected to the external reference voltage with 256 taps and selection switches The tap decoder switches one of these taps to the DAC output line see Figure 5 The analog output voltage is buffered by an auto zeroed unity gain amplifier Setting the analog output enable flag of the control register switches this buffer amp on or off In the active state the output voltage is held until a further data byte is sent The on chip D A converter is also used for successive approximation A D conversion In order to release the DAC for an A D conversion cycle the unity gain amplifier is equipped with a track and hold circuit This circuit holds the output voltage while executing the A D conversion PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 6 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter The formula for the output voltage supplied to the analog output
15. 3 27 of 31 NXP Semiconductors PCF8591 Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s 20 Contact information 8 bit A D and D A converter own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications
16. 91 device The A D conversion cycle is triggered at the trailing edge of the acknowledge clock pulse and is executed while transmitting the result of the previous conversion see Figure 8 protocol ADDRESS DATA BYTE 0 DATA BYTE 1 DATA BYTE 2 VAL SAV AS EILIAN JAALA JTA 1 2 8 9 1 9 1 9 1 4 L sampling byte 1 conversion of byte 1 4 sampling byte 2 conversion of byte 2 4 L sampling byte 3 conversion of byte 3 transmission of previously transmission of byte 1 transmission of byte 2 mblg29 Fig 8 converted byte A D conversion sequence PCF8591 Once a conversion cycle is triggered an input voltage sample of the selected channel is stored on the chip and is converted to the corresponding 8 bit binary code Samples picked up from differential inputs are converted to an 8 bit two s complement code see Figure 9 and Figure 10 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 8 of 31 NXP Semiconductors PCF8591 PCF8591 8 bit A D and D A converter The conversion result is stored in the ADC data register and awaits transmission If the auto increment flag is set the next channel is selected The first byte transmitted in a read cycle contains the conversion result code of the previous read cycle After a POR condition the first byte read is
17. A converter Eight different 1 C bus slave addresses can be used to address the PCF8591 see Table 5 Table 5 1 C slave address byte Slave address Bit 7 6 5 4 3 2 1 0 MSB LSB slave address 1 0 0 1 A2 A1 AO RW The least significant bit of the slave address byte is bit RW see Table 6 Table 6 R W bit description R W Description 0 write data 1 read data Bit 1 to bit 3 of the slave address are defined by connecting the input pins AO to A2 to either Vgg logic 0 or Vpp logic 1 Therefore eight instances of PCF8591 can be distinguished on the same 2C bus acknowledge acknowledge acknowledge from PCF8591 from PCF8591 from PCF8591 N O0toM data bytes mbl833 Fig 15 Bus protocol for write mode D A conversion acknowledge acknowledge no acknowledge from PCF8591 from master ADDRESS 1 DATA BYTE LAST DATA BYTE ae N 0 to M data bytes mbl834 Fig 16 Bus protocol for read mode A D conversion All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 13 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 10 Application design in information Inputs must be connected to Vss or Vpp when not in use Analog inputs may also be connected to AGND or Vref In order to prevent excessive ground and supply noise and to minimize crosstalk of
18. ER HOLD APPROXIMATION AIN3 REGISTER LOGIC SAMPLE AOUT AND VREF HOLD AGND mbl821 Fig 1 Block diagram of PCF8591 7 Pinning information 7 1 Pinning Wz AINO 1 16 VDD AINO 4 16 Vpp AIN1 2 15 AOUT AIN1 2 15 AOUT AIN2 3 14 VREF AIN2 3 14 VREF AIN3 4 13 AGND AIN3 4 13 AGND PCF8591P _ PCF8591T Ao 5 12 EXT Ao 5 12 EXT A1 6 11 OSC A1 6 11 OSC A2 7 10 SCL A2 7 10 SCL Vss 8 9 SDA Vss 8 9 SDA aaa 008007 aaa 008008 Top view For mechanical details see Top view For mechanical details see Figure 22 on page 21 Figure 23 on page 22 Fig 2 Pin configuration for PCF8591P Fig 3 Pin configuration for PCF8591T PCF8591 DIP16 S016 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 3 of 31 NXP Semiconductors PCF8591 7 2 Pin description 8 bit A D and D A converter Table 4 Pin description Symbol Pin Description AINO 1 analog inputs A D converter AIN1 2 AIN2 3 AIN3 4 AO 5 hardware slave address Al 6 A2 7 Vss 8 ground supply voltage SDA 9 l2C bus serial data input and output SCL 10 I2C bus serial clock input OSC 11 oscillator input output EXT 12 external internal switch for oscillator input AGND 13 analog ground supply VREF 14 voltage reference input AOUT 15 analog output D A converter Vpop 16 supply voltage PCF8591 All information provi
19. F8591 4 Ordering information 8 bit A D and D A converter Table 1 Ordering information Type number Package Name Description Version PCF8591P DIP16 plastic dual in line package 16 leads SOT38 4 300 mil PCF8591T S016 plastic small outline package 16 leads SOT162 1 body width 7 5 mm 4 1 Ordering options Table 2 Ordering options Product type number Sales item 12NC Orderable part IC Delivery form number revision PCF8591P 933768130112 PCF8591P 112 1 tube PCF8591T 2 935276541512 PCF8591T 2 512 1 tube dry pack 935276541518 PCF8591T 2 518 1 tape and reel dry pack 13 inch 5 Marking Table 3 Marking codes Type number Marking code PCF8591P PCF8591P PCF8591T PCF8591T PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 2 of 31 NXP Semiconductors PCF8591 6 Block diagram 8 bit A D and D A converter SCL SDA Ho INTERFACE A1 PCF8591 STATUS DAC DATA ADC DATA A2 REGISTER REGISTER REGISTER EXT li VDD POWER ON Vss RESET CONTROL LOGIC osc OSCILLATOR AINO AIN1 ANALOGUE SANES SUCCESSIVE AIN2 MULTIPLEX
20. all times Studies have shown that small packages reach higher temperatures during reflow soldering see Figure 24 PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 24 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter maximum peak temperature MSL limit damage level temperature minimum peak temperature minimum soldering temperature peak temperature time 001aac844 MSL Moisture Sensitivity Level Fig 24 Temperature profiles for large and small components For further information on temperature profiles refer to Application Note AN10365 Surface mount reflow soldering description 17 References 1 AN10365 Surface mount reflow soldering description 2 AN10853 ESD and EMC sensitivity of IC 3 IEC 60134 Rating systems for electronic tubes and valves and analogous semiconductor devices 4 IEC 61340 5 Protection of electronic devices from electrostatic phenomena 5 IPC JEDEC J STD 020D Moisture Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices 6 JESD22 A114 Electrostatic Discharge ESD Sensitivity Testing Human Body Model HBM 7 JESD22 A115 Electrostatic Discharge ESD Sensitivity Testing Machine Model MM 8 JESD78 IC Latch Up Test 9 JESD625 A Re
21. alues Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 201
22. ded in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 4 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 8 Functional description PCF8591 8 1 8 2 Addressing Each PCF8591 device in an C bus system is activated by sending a valid address to the device The address consists of a fixed part and a programmable part The programmable part must be set according to the address pins AO A1 and A2 The address is always sent as the first byte after the start condition in the 1 C bus protocol The last bit of the address byte is the read write bit which sets the direction of the following data transfer see Table 5 on page 13 Figure 15 on page 13 and Figure 16 on page 13 Control byte The second byte sent to a PCF8591 device is stored in its control register and is required to control the device function The upper nibble of the control register is used for enabling the analog output and for programming the analog inputs as single ended or differential inputs The lower nibble selects one of the analog input channels defined by the upper nibble see Figure 4 If the auto increment flag is set the channel number is incremented automatically after each A D conversion If the auto increment mode is desired in applications where the internal oscillator is used the analog output enable flag must be set in the control byte bit 6
23. ed 7 2 gt 0 8V Vogt V re AGND Vpp a gt 0 4V PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 17 of 31 NXP Semiconductors PCF8591 14 2 D A characteristics Table 9 D A characteristics 8 bit A D and D A converter Voo 5 0 V Vss 0 Vper 5 0 V Vagnp 0 V R 10 KQ C 100 pF Tamp 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Analog output Voa analog output voltage no resistive load Vss Vpp V RL 10kQ Vss 0 9xVpp V ILo output leakage current AOUT disabled 250 nA Accuracy Eo offset error Tamb 25 C 50 mV EL linearity error 5 1 5 LSB Eg gain error no resistive load 5 z ts DAC DAC settling time to 1 2 LSB full scale 90 us fo DAc DAC conversion 11 1 kHz frequency SNRR supply noise rejection f 100 Hz 40 dB ratio Vppn 0 1 x Vpp 14 3 A D characteristics Table 10 A D characteristics Voo 5 0 V Vss 0 Veer 5 0 V Vagnp 0 V Rs 10 kQ Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Analog inputs Via analog input voltage Vss ILIA analog input leakage current Cia analog input E capacitance Ciait differential input capacitance Viise single ended input measuring range VAGND voltage Vi aif differential input measuring range Vps v
24. ee 27 DisclaimerS 0 0200 cece eee eee 27 19 4 20 21 22 23 Trademarks 0 0 ccc eee eee 28 Contact information 0 28 Table ii iii sevice eee eee nae eee 29 Figures aerem tee eae eed aaa eean 30 ContentSie ic scee eek sie cba EAEE reese 31 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2013 For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com All rights reserved Date of release 27 June 2013 Document identifier PCF8591
25. free process from J STD 020D 24 Table 14 Revision history 00200 00s 26 PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 29 of 31 NXP Semiconductors PCF8591 22 Figures 8 bit A D and D A converter Fig 1 Fig 2 Fig 3 Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 Fig 22 Fig 23 Fig 24 PCF8591 Block diagram of PCF8591 3 Pin configuration for PCF8591P DIP16 3 Pin configuration for PCF8591T S016 3 Control byte a an eee 6 DAC resistor divider chain 7 DAC data and DC conversion characteristics 7 D A conversion sequence 0 8 A D conversion sequence 5 8 A D conversion characteristics of single ended INDUIS i Ose eee Pee onaeies Hb thas eelak eas 9 A D conversion characteristics of differential INDUS aa i wet ete ae iy eee 10 Bit transfer 0 2 02 eee 11 Definition of START and STOP conditions 11 System configuration 0000 ee 12 Acknowledgement on the I2C bus 12 Bus protocol for write mode D A conversion 13 Bus protocol for read mode A D conversion 13 Application diagram 00 eee eee 14 Device pr
26. is application the reference voltage must be kept stable during the conversion cycle Oscillator An on chip oscillator generates the clock signal required for the A D conversion cycle and for refreshing the auto zeroed buffer amplifier When using this oscillator the EXT pin must be connected to Vss The oscillator frequency is available at the OSC pin If the EXT pin is connected to Vpp the oscillator output OSC is switched to a high impedance state allowing to feed an external clock signal to OSC All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 10 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 9 Characteristics of the 12C bus PCF8591 9 1 9 2 9 3 The I C bus is for bidirectional two line communication between different ICs or modules The two lines are a Serial DAta line SDA and a Serial CLock line SCL Both lines must be connected to a positive supply via a pull up resistor Data transfer may be initiated only when the bus is not busy Bit transfer One data bit is transferred during each clock pulse The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time are interpreted as a control signal see Figure 11 om ft Xt ctf data line change stable of data data valid allowed mbc621 Fig
27. nal description 00000 5 Addressing 00 00 eee eee eee 5 Control byte 0 cee eee eee eee 5 D A conversion 00002 0c eee 6 A D conversion 2002000e eae 8 Reference voltage 2 0 eee 10 Oscillators o oo hehe hae dad areas 10 Characteristics of the I C bus 11 Bit transfer 020000 eee eee 11 START and STOP conditions 11 System configuration 11 Acknowledge 20 eee eee 12 2C bus protocol 0 6 cece cece eee ee 12 Application design in information 14 Internal Circuitry 2 00 0 c eee eee 15 Safety notes 02 s cdswicid seetsinetnns 15 Limiting values 000 e eee eee 16 Characteristics 00 0e cece eens 17 Static characteristics 00 17 D A characteristics 0000 18 A D characteristics 00 18 Dynamic characteristics 20 Package outline 0c eee eee eee 21 Soldering of SMD packages 23 Introduction to soldering 23 Wave and reflow soldering 23 Wave soldering 20 eee eee 23 Reflow soldering 0e eee eee 24 References 00 cece eee e eee ees 25 Revision history 00 eee e eee nee 26 Legal information 0 0eeeeeee 27 Data sheet status 0 27 Definitions 00000 eee e
28. nductors PCF8591 8 bit A D and D A converter 16 4 Reflow soldering Key characteristics in reflow soldering are e Lead free versus SnPb soldering note that a lead free reflow process usually leads to higher minimum peak temperatures See Figure 24 than a SnPb process thus reducing the process window e Solder paste printing issues including smearing release and adjusting the process window for a mix of large and small components on one board e Reflow temperature profile this profile includes preheat reflow in which the board is heated to the peak temperature and cooling down It is imperative that the peak temperature is high enough for the solder to make reliable solder joints a solder paste characteristic In addition the peak temperature must be low enough that the packages and or boards are not damaged The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12 SnPb eutectic process from J STD 020D Package thickness mm Package reflow temperature C Volume mm lt 350 2 350 lt 25 235 220 gt 25 220 220 Table 13 Lead free process from J STD 020D Package thickness mm Package reflow temperature C Volume mm3 lt 350 350 to 2000 gt 2000 lt 1 6 260 260 260 1 6 to 2 5 260 250 245 gt 2 5 250 245 245 Moisture sensitivity precautions as indicated on the packing must be respected at
29. oltage Ves Vrer VAGND 2 Accuracy Eo offset error Tamb 25 C EL linearity error Eg gain error small signal AV 16 LSB CMRR common mode rejection ratio PCF8591 All information provided in this document is subject to legal disclaimers Typ 60 Max Unit Vin V 100 nA x pF 2 pF VREF V Ves 7 2 20 mV 1 5 LSB 1 5 dB NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 18 of 31 NXP Semiconductors PCF8591 Table 10 A D characteristics continued Voo 5 0 V Vss 0 Vper 5 0 V Vagnp 0 V Rs 10 kQ Tamp 40 C to 85 C unless otherwise specified 8 bit A D and D A converter Symbol Parameter Conditions Min Typ Max Unit SNRR supply noise rejection f 100 Hz 40 dB ratio Vppn 0 1 x Vpp teonv conversion time 90 us fs sampling frequency 11 1 kHz 200 aaa 008043 160 aaa 008049 IDD IDD uA HA 160 120 120 40 C 80 HOT OO 85 C 80 40 40 0 0 2 3 4 6 2 3 4 6 Voo V Voo V a internal oscillator Tamb 27 C b External oscillator Fig 19 Operating supply current as a function of supply voltage analog output disabled 500 aaa 008050 500 aaa 00805
30. otection diagram 15 Operating supply current as a function of supply voltage analog output disabled 19 Output impedance of analog output buffer near power railS 2000 000 00 19 12C bus timing diagram rise and fall times refer to Vi and Vi ee eee 20 DIP 16 plastic dual in line package 16 leads BOO WMD aeaa Wie a a dces Bo ag Oe andres de aves KR 21 S016 plastic small outline package 16 leads body width 7 5mm 2000 2000 22 Temperature profiles for large and small COMPONCMIUS ciasne me died hed cen fe 25 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 30 of 31 NXP Semiconductors PCF8591 23 Contents 8 bit A D and D A converter NoaoaPR BOND Bare oNN ip pata 2 0000 DO D o o o HOM PON O anona OnRwWD OH 14 1 14 2 14 3 14 4 15 16 16 1 16 2 16 3 16 4 17 18 19 19 1 19 2 19 3 General description 0000e00s 1 Features and benefits 00000eees 1 Applications 0 0 00 cece eee eee 1 Ordering information 0 0 2005 2 Ordering options 00e ee eee 2 Marking 00 e eee e eee eee eee 2 Block diagram 00 c scence eee eee 3 Pinning information 00ee ee eee 3 PINNING 220 epea Rie a aes ide SEV eee 3 PIN GeSCIIPLON 2 2 eee ence oe eee eee 4 Functio
31. pplications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting v
32. quirements for Handling Electrostatic Discharge Sensitive ESDS Devices 10 SNV FA 01 02 Marking Formats Integrated Circuits 11 UM10204 2C bus specification and user manual 12 UM10569 Store and transport requirements PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 25 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 18 Revision history Table 14 Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8591 v 7 20130627 Product data sheet PCF8591 v 6 Modifications e The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors e Legal texts have been adapted to the new company name where appropriate PCF8591 v 6 20030127 Product data sheet PCF8591 v 5 PCF8591 v 5 20011213 Product data sheet PCF8591 v 4 PCF8591 v 4 19980702 Product data sheet PCF8591 v 3 PCF8591 v 3 19970402 Product data sheet PCF8591 v 2 PCF8591 v 2 19910901 Product data sheet PCF8591 v 1 PCF8591 v 1 19860627 Product data sheet PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 26 of 31 NXP Semiconductors PCF8591 19 Legal information 8 bit A D and D A converter 19 1 Da
33. r leadless SMDs which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered Packages with solder balls and some leadless packages which have solder lands underneath the body cannot be wave soldered Also leaded SMDs with leads having a pitch smaller than 0 6 mm cannot be wave soldered due to an increased probability of bridging The reflow soldering process involves applying solder paste to a board followed by component placement and exposure to a temperature profile Leaded packages packages with solder balls and leadless packages are all reflow solderable Key characteristics in both wave and reflow soldering are e Board specifications including the board finish solder masks and vias e Package footprints including solder thieves and orientation e The moisture sensitivity level of the packages e Package placement e Inspection and repair e Lead free soldering versus SnPb soldering 16 3 Wave soldering PCF8591 Key characteristics in wave soldering are e Process issues such as application of adhesive and flux clinching of leads board transport the solder wave parameters and the time during which components are exposed to the wave e Solder bath specifications including temperature and impurities All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 23 of 31 NXP Semico
34. ta sheet status Document status J 2 Product status 3 Definition Objective short data sheet Development Preliminary short data sheet Qualification Product short data sheet Production This document contains data from the objective specification for product development This document contains data from the preliminary specification This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 19 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and
35. the digital to analog signal paths the printed circuit board layout must be very carefully designed Supply lines common to a PCF8591 device and noisy digital circuits and ground loops should be avoided Decoupling capacitors gt 10 uF are recommended for power supply and reference voltage inputs pcF8591 OSC SCL AOUT VREF AGND EXT PCF8591 ty SCL SDA VDD MASTER TRANSMITTER 4 7 ANALOGUE GROUND 717 vy 2 7 DIGITAL GROUND IEC bus mbl839 Fig 17 Application diagram PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 14 of 31 NXP Semiconductors PCF8591 11 Internal circuitry 8 bit A D and D A converter PCF8591 substrate AINO AIN1 AIN2 AIN3 AO Al A2 Vss aaa 008073 Fig 18 Device protection diagram VDD AOUT VREF AGND EXT OSC SCL SDA 12 Safety notes CAUTION A AisA This device is sensitive to ElectroStatic Discharge ESD Observe precautions for handling electrostatic sensitive devices Such precautions are described in the ANSI ESD S20 20 IEC ST 61340 5 JESD625 A or equi
36. valent standards PCF8591 All information provided in this document is subject to legal disclaimers NXP B V 2013 All rights reserved Product data sheet Rev 7 27 June 2013 15 of 31 NXP Semiconductors PCF8591 8 bit A D and D A converter 13 Limiting values Table 7 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpp supply voltage 0 5 8 0 V VI input voltage any input 0 5 Vpop 0 5 V l input current 10 mA lo output current 20 mA Ipp supply current 50 mA Iss ground supply current 50 mA Prot total power dissipation per package 300 mW P out power dissipation per 100 mW output Vesp electrostatic HBM H 3000 V discharge voltage MM 2 300 y liu latch up current BI 200 mA Tamb ambient temperature operating device 40 85 C Tstg storage temperature 4 65 150 C 1 Pass level Human Body Model HBM according to Ref 6 JESD22 A114 2 Pass level Machine Model MM according to Ref 7 JESD22 A115 3 Pass level latch up testing according to Ref 8 JESD78 at maximum ambient temperature Tambimax 4 According to the store and transport requirements see Ref 12 UM10569 the devices have to be stored at a temperature of 8 C to 45 C and a humidity of 25 to 75 PCF8591 All information provided in this document is subject to legal disclaimers
37. y products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof PCF8591 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications A
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