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ST ST10F167 Data Sheet

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1. m Us mi Write c yole EET D15 D8 Data Out D7 DO i atio 3e ta ty at top WR A WRL WRH ic 1 mt 1 lis o E M teto WO NN ls Figure 23 External memory cycle demultiplexed bus no read write delay extended ALE 70 78 42 1701 03 y DATA SHEET ST10F167 20 5 9 CLKOUT and READY VDD 5 V 15 Vss 0 V T 40 to 85 G C for PORTO PORT1 Port 4 ALE RD WR BHE CLKOUT 100 pF C for Port 6 CS 100 pF Max CPU Clock 20 MHz Variable CPU Clock 1 2TCL 1 to 20 MHz Parameter Symbol Unit min max min max CLKOUT cycle time by CC 50 50 2TCL 2TCL ns CLKOUT high time ts CC 20 TCL 5 ns CLKOUT low time ts CC 15 TCL 10 ns CLKOUT rise time t CC 5 5 ns CLKOUT fall time ts CC 10 10 ns CLKOUT rising edge to ta CC 5 t 10 ta 5 t 10 t ns ALE falling edge Synchronous READY ts SR 30 30 ns setup time to CLKOUT Synchronous READY tss SR 0 0 ns hold time after CLKOUT Asynchronous READY t4 SR 65 2TCL 15 ns low time Asynchronous READY tss SR 15 15 ns setup time Asynchronous READY Lo SR 0 0 ns hold time Async READY hold time tg SR 0 0 t 0 TCL 25 ns after RD WR high De 2ta te t 2ta de multiplexed Bus 2 2 2 Notes 1 Table 24 CLKOUT and READY These timings are given for test purpo
2. 65 2059 OLKOUT and READY Rma Ro REESE or 71 20 5 10 External Bus Arbitration 73 21 Package Mechanical Data 76 22 Ordering Information 76 23 Revision History 77 77 42 1701 03 3 78 DATA SHEET ST10F167 1 Introduction The ST10F167 is a new derivative of the ST Microelectronics 16 bit single chip CMOS microcontrollers It combines high CPU performance with high peripheral functionality and enhanced l O capabilities It also provides on chip high speed RAM and clock generation via PLL Vpp Vss XTAL1 Port 0 XTAL2 16 bit RSTIN Port 1 RSTOUT 16 bit V Port 2 AREF 16 bit VAGND ST10F167 Port 3 NMI 15 bit EA Port 4 READY PN ALE Port 6 MU 8 bit RD WR WRL C EU 7 Port 5 16 bit C Port 8 8 bit Figure 1 Logic symbol 4 78 42 1701 03 y DATA SHEET ST10F167 Pin Data 2 OO i O LO SF CO QN mr Q O OO i CO LO st CO QI Q O 00 i XO LO st CO l Q O 00 i CO L0 SF CO acmcaoeoeoooooooo00oco0o0 0200000000000 0000 00O i i T T i CTN SSA g OLL ch 6dV I HOd 8 LLL im OLQv ZHOd 9 cl OL LLQV HOd o ELL 69h 2LOv rHOd 4 Fl 89h ELAY S HOd E SII 19h vLdW 9 HOd 4 911 99 n SLOV L HOd B ZEL S9 p 0V O lld d gll 9H LW LTbd Bett 69h cV lt ld d 021 con EV E lld d 121 L9 b PWY Md a cal 09H GWG lld d ezi 6s h 9W 9 1ld d velt 89 n
3. ST10F167 Input l p Symbol Pin LU O Function PORT1 1 0 PORT consists of the two 8 bit bidirectional I O ports P1L and P1L 0 118 P1H Itis bit wise programmable for input or output via direction P1L 7 125 bits For a pin configured as input the output driver is put into P1H 0 128 high impedance state PORT1 is used as the 16 bit address P1H 7 135 bus A in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode The following PORT1 pins also serve for alternate functions 132 P1H 4 CC24I0 CAPCOM2 CC24 Capture Input 133 P1H 5 CC251I0 CAPCOM CC25 Capture Input 134 P1H 6 CC26I0 CAPCOM2 CC26 Capture Input 135 P1H 7 CC27I0 CAPCOM2 CC27 Capture Input XTAL1 138 XTAL1 _ Input to the oscillator amplifier and input to the inter nal clock generator XTAL2 137 O XTAL2 Output of the oscillator amplifier circuit To clock the device from an external source drive XTAL1 while leaving XTAL2 unconnected Minimum and maximum high low and rise fall times specified in the AC Characteristics must be observed RSTIN 140 Reset Input with Schmitt Trigger characteristics A low level at this pin for a specified duration while the oscillator is running re sets the ST10F167 An internal pullup resistor permits pow er on reset using only a capacitor connected to Vas RSTOUT 141 O Internal Reset Indication Output This pin is set to a low level when the part is exe
4. DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value P6 b FFCCh E6h Port 6 Register 8 bits 00h P7 b FFDOh E8h Port 7 Register 8 bits 00h P8 b FFD4h EAh Port 8 Register 8 bits 00h PECCO FECOh 60h PEC Channel 0 Control Register 0000h PECC1 FEC2h 61h PEC Channel 1 Control Register 0000h PECC2 FEC4h 62h PEC Channel 2 Control Register 0000h PECC3 FEC6h 63h PEC Channel 3 Control Register 0000h PECC4 FEC8h 64h PEC Channel 4 Control Register 0000h PECC5 FECAh 65h PEC Channel 5 Control Register 0000h PECC6 FECCh 66h PEC Channel 6 Control Register 0000h PECC7 FECEh 67h PEC Channel 7 Control Register 0000h PICON F1C4hE E2h Port Input Threshold Control Register 0000h PPO FO38hE 1Ch PWM Module Period Register 0 0000h PP1 FOSAhE 1Dh PWM Module Period Register 1 0000h PP2 FOSChE 1Eh PWM Module Period Register 2 0000h PP3 FOSEhE 1Fh PWM Module Period Register 3 0000h PSW b FF10h 88h CPU Program Status Word 0000h PTO FO30hE 18h PWM Module Up Down Counter 0 0000h PT1 FO32hE 19h PWM Module Up Down Counter 1 0000h PT2 FO34hE 1Ah PWM Module Up Down Counter 2 0000h PT3 FO36hE 1Bh PWM Module Up Down Counter 3 0000h PWO FE30h 18h PWM Module Pulse Width Register 0 0000h PW1 FE32h 19h PWM Module Pulse Width Register 1 0000h PW2 FE34h 1Ah PWM Module Pulse Width Register 2 0000h PW3 FE36h 1Bh PWM Module Pulse
5. BUS D15 D8 lt Bataln_ gt gt gt D7 DO i i i 1 ab mui NET c 1 1 li 3 T he m lio i leg n i ww te RdCSx 1 AY 26 A A 9 Write s i gt i b D7 DO Pn R WR et meto R WRL WRH i m dd m lu log WrCSx Ne A 1 l 48 Figure 21 External memory cycle demultiplexed bus with read write delay extended ALE 68 78 42 1701 03 ST DATA SHEET ST10F167 ALE A23 A16 i A15 A0 m Address BHE h Read Cycle E ia lis BUS l D15 D8 lt Desain gt gt gt D7 DO i I gt EN tes ERE MEC ly RdCSx NU 1 A MEE fg Write SD ab a D15 D8 gt K___Datdout X D7 DO to i WR a io RL WRH i i ff MEL iti hs me metso i WrCSx NC Fa Lo Figure 22 External memory cycle demultiplexed bus no read write delay normal ALE iy 42 1701 03 69 78 DATA SHEET ST10F167 A tie eo be l A23 A16 m Wr lion ae A15 A0 f na Address A BHE re 1 1 1 1 1 te 1 1 tos 1 E 1 1 1 tz Read Cycle Pa NUE SSN lt Datan gt gt gt BUS D15 D8 D7 DO gt Lt D 51 1 i i RS a 47 1 RdCSx i W
6. YZ High Performance CPU O 16 bit CPU with 4 stage pipeline O 100ns instruction cycle time at 20MHz CPU clock O 500ns multiplication 16 16 bit O ius division 32 16 bit O Enhanced boolean bit manipulation facilities O Additional instructions to support HLL and operating systems O Single cycle context switching support Memory organization O 2K bytes on chip internal RAM O 2K bytes on chip Extension RAM O 128K bytes on chip FLASH memory O FLASH with 4 independently erasable banks Fast and flexible bus O Programmable external bus characteristics for different address ranges O 8 Bit or 16 Bit external data bus O Multiplexed or de multiplexed external address data buses O Five programmable chip select signals O Hold and hold acknowledge bus arbitration support Fail safe protection O Programmable watchdog timer On chip CAN 2 0B Interface On chip bootstrap loader Interrupt O 8 channel PEC for single cycle interrupt driven data transfer O 16 priority level interrupt system with 56 sources sample rate down to 50ns Timers O Two multi functional general purpose timer units with 5 timers O Two 16 bit capture compare units 42 1701 03 ST10F 167 16 bit MCU with 128KByte FLASH memory DATA SHEET CPU Core Interna Interrupt Controller osc y 2 FLASH v m o A CAPCOM1 1 E Up t o E el e a
7. ns with RW delay to RD WR low time t CC 65 to 3TCL 10 ns no RW delay lc RD to valid data in t SR 5 ate 2TCL 45 ns with RW delay to RD to valid data in tw SR 55 le 3TCL 20 ns no RW delay lc ALE low to valid data in tis SR 40 3TCL 35 ns ta to ta to Address to valid data in tz SR 60 4TCL 40 ns 2t4 to 2ta to Data hold after RD ts SR 0 0 ns rising edge Data float after RD rising tx SR 35 te 2TCL 15 ns edge with RW delay ti Data float after RD rising t SR 15 t TCL 10 ns edge no RW delay te Data valid to WR t CC 15 4 te 2TCL 35 ns fc Data hold after WR t CC 15 te TCL 10 tr ns Table 23 Demultiplexed bus characteristics yy 42 1701 03 65 78 DATA SHEET ST10F167 Max CPU Clock Variable CPU Clock Parameter Symbol 20 MHz 1 2TCL 1 to 20 MHz Unit min max min max ALE rising edge after RD t CC 10 te 10 ns WR t Address hold after RD WR t CC 2 5 tr 2 5 tp ns ALE falling edge to CS ls OG 5 f 10 t 5 ty 10 t ns CS low to Valid Data In to SR 45 3TCL 30 ns to 2t4 lo 2ta CS hold after RD WR tay CC 10 4 te TCL 15 4 tr ns ALE falling edge to RdCS ta CC 20 t TCL 5 ta ns WrCS with RW delay ALE falling edge to RdCS t CC 5 ty 5 ta ns WrCS no RW delay RdCS to Valid Da
8. 56000 6 3 7 0 0006 00074 38400 1 7 4 3 000Fy 0010y 38400 8 5 1 4 0009 000A 19200 1 7 1 4 001Fy 00204 19200 3 3 1 4 0014 0015 9600 0 2 1 4 0040y 0041 9600 0 9 1 4 002A 002B y 4800 0 2 0 6 00814 00824 4800 0 9 0 2 00554 0056 yy 2400 0 2 0 2 01034 0104 2400 0 4 0 2 OOACy 00AD 1200 0 2 0 0 02074 02084 1200 0 1 0 2 015Ay 015By 600 0 1 0 0 04105 0411 600 0 1 0 1 02B5 02B6 76 40 49 0 4 1FFFy 1FFF4 75 0 0 0 0 15B2y 15B3y 50 1 7 1 7 1FFFy 1FFFy Table 12 Commonly used baud rates by reload value and deviation errors 34 78 42 1701 03 y DATA SHEET ST10F167 Note The deviation errors givenin the table above are rounded Using a baudrate crystal will provide correct baudrates without deviation errors For synchronous operation the Baud rate generator provides a clockwith 4 times the rate of the established Baud rate 14 2 High speed synchronous serial channel SSC The High Speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the ST10F167 and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication The serial clock signal can be generated by the SSC itself master mode or be received from an external master slave
9. The next external bus cycle may start here 72 78 42 1701 03 y DATA SHEET ST10F167 20 5 10 External Bus Arbitration vpo 5 V 596 Vss 0 V T 40 to 85 C C for PORTO PORT1 Port 4 ALE RD WR BHE CLKOUT 100 pF C for Port 6 CS 2 100 pF Max CPU Clock Variable CPU Clock min max min max HOLD input setup time ts SR 35 35 ns to CLKOUT CLKOUT to HLDA high t CC 20 20 ns or BREO low delay CLKOUT to HLDA Iow t CC 20 20 ns or BREO high delay CSx release ta CC 20 20 ns CSx drive tes CC 5 25 5 25 ns Other signals release le CC 20 20 ns Other signals drive t7 CC 5 25 5 25 ns Table 25 External bus arbitration iy 42 1701 03 73 78 DATA SHEET ST10F167 e U Cy CLKOUT Vp E HOLD 77 HLDA iE 1 gt JM ER BREQ 2 tea 3 On Pe ESOO a oe ea ee tee re m O OI 1 Figure 25 External bus arbitration releasing the bus Notes 1 The ST10F167 will complete the currently running bus cycle before granting bus access 2 This is the first possibility for BREQ to get active 3 The CS outputs will be resistive high pullup after t 74 78 42 1701 03 57 DATA SHEET ST10F167 P cur N Y NA NAU YY N 1 tty EN z L Other Signal TT C Figure 26 External bus arbitration regaining the bus Notes 1 This isthe last chance
10. The parameters listed in the Electrical Characteristics tables represent the characteristics of the ST10F167 and its demands on the system Where the ST10F167 logic provides signals with their respective timing characteristics the symbol CC for Controller Characteristics is included in the Symbol column Where the external system must provide signals with their respective timing characteristics to the ST10F167 the symbol SR for System Requirement is included in the Symbol column 48 78 42 1701 03 DATA SHEET ST10F167 20 3 DC Characteristics Voo 5 V 15 Vss 0 fopy 20MHz Reset active T 40 to 85 C Limit Values Parameter Symbol Unit Test Condition min max Input low voltage TTL V SR 0 5 0 2 Vpp V 7 0 1 Input low voltage Vis SR 0 5 2 0 V Special Threshold Input high voltage all except Vw SR 0 2 Vpp Vpp 0 5 V m RSTIN and XTAL1 TTL 0 9 Input high voltage RSTIN Vw SR 0 6 Vpp Vpp 0 5 V Input high voltage XTAL1 Vino SR 0 7 Vpp Vpp 0 5 V Input high voltage Vws SR 0 8 Vpp Vpp 0 5 V Special Threshold 0 2 Input Hysteresis HYS 400 mV Special Threshold Output low voltage Vo CC 0 45 V lou 2 4 mA PORTO PORT1 Port 4 ALE RD WR BHE CLKOUT RSTOUT Output low voltage Vo CC 0 45 V lou 1 6 mA all other outputs Output high voltage Von CC 0 9 Vpp V lou 500 u
11. 0 Since only word values can be written to FCR care must be taken that FWM SET is not cleared inadvertently Therefore for any command written to FCR exceptfor the return to the Flash standard mode FWMSET must be set to 1 Reset condition of FWMSET is 0 b14 b10 These bits are reserved for future development they must be written to 0 b9 b8 BEO 1 Select the Flash memory bank to be erased The physical addresses of Bank erase select bank 0 depends on the which Flash memory map has been chosen In Flash operating modes other than the erasing mode these bits are not significant At reset BE1 0 are set to 00 b7 WOWW Word double word write Determines the word width used for programming operations 16 bit WDWW 0 or 32 bit WDWW 1 In Flash operation modes other than the programming mode this bit is not significant At reset WDWW is set to 0 b6 b5 CKCTLO 1 Flash Timer Clock Control Control the width TPRG of the programming or erase pulses applied to the Flash memory cells during the operation TPRG varies in an inverse ratio to the clock frequency To avoid putting the Flash memory under crit ical stress conditions the width of one single programming or erase pulse and the programming or erase time must not exceed defined values Thus the maximum number of programming or erase attempts depends on the system clock frequency RESET state 00 b
12. 77 42 1701 03 33 78 DATA SHEET ST10F167 After each reset and also during normal operation the ADC automatically performs calibration cycles This automatic self calibration constantly adjusts the converter to the changing operating conditions e g temperature and compensates process variations These calibration cycles are part of the conversion cycle and do not affect the normal operation of the A D converter 14 Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces An Asynchronous Synchronous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC 14 1 ASCO ASCO supports full duplex asynchronous communication up to 625 KBaud and half duplex synchronous communication up to 2 5 Mbaud 2 20MHz system clock The SSC allows half duplex synchronous communication up to 5 Mbaud 20MHz system clock For asynchronous operation the Baud rate generator provides a clock with 16 times the rate of the established Baud rate The table below lists various commonly used baud rates together with the reguired reload values and the deviation errors compared to the intended baudrate SOBRS 0 fopy 20MHz SOBRS 1 fopy 20MHz ae Deviation Error Reload Value my ate Deviation Error Reload Value 625000 0 0 0000 416666 0 0 0000 56000 1 5 7 0 OOOA 000B
13. AND word byte operands 2 4 OR B Bitwise OR word byte operands 2 4 XOR B Bitwise XOR word byte operands 2 4 BCLR Clear direct bit 2 BSET Set direct bit 2 BMOV N Move negated direct bit to direct bit 4 BAND BOR BXOR AND OR XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH L Bitwise modify masked high low byte of bit addressable 4 direct word memory with immediate data CMP B Compare word byte operands 214 CMPD1 2 Compare word data to GPR and decrement GPR by 1 2 2 4 CMPI1 2 Compare word data to GPR and increment GPR by 1 2 2 4 PRIOR Determine number of shift cycles to normalize direct 2 word GPR and siore result in direct word GPR SHL SHR Shift left right direct word GPR 2 ROL ROR Rotate left right direct word GPR 2 Table 15 Instruction set summary 38 78 42 1701 03 1571 DATA SHEET ST10F167 Mnemonic Description Bytes ASHR Arithmetic sign bit shift right direct word GPR 2 MOV B Move word byte data 2 4 MOVBS Move byte operand to word operand with sign extension 2 4 MOVBZ Move byte operand to word operand with zero extension 2 4 JMPA JMPI JMPR Jump absolute indirect relative if condition is met 4 JMPS Jump absolute to a code segment 4 J N B Jump relative if direct bit is not set 4 JBC Jump relative and clear bit if direct bit is set 4 JNBS Jump relative and set bit if direct bit is not
14. OI299 2d OILOO F ed OI009 0 cd aga SSA anaeL srNV SE Sd anarv vENV VEL Sd NIS L ELNV E L Sd NI9L ZLNY Z L Sd anast LENV EE Sd GD39L0VINV OF Sd GN9V A ELMAN Figure 2 Pin out 5 78 42 1701 03 ST10F167 DATA SHEET Symbol Pin Input l Output O Function P6 0 1 8 P6 7 1 0 Port 6 is an 8 bit bidirectional I O port It is bit wise programma ble for input or output via direction bits For a pin configured as input the output driver is put into high impedance state Port 6 outputs can be configured as push pull or open drain drivers The following Port 6 pins also serve for alternate functions P6 0 CS0 Chip Select 0 Output P6 4 CS4 Chip Select 4 Output P6 5 HOLD External Master Hold Request Input P6 6 HLDA Hold Acknowledge Output P6 7 BREQ Bus Request Output P8 0 9 16 P8 7 16 1 0 1 0 Port 8 is an 8 bit bidirectional I O port It is bit wise programma ble for input or output via direction bits For a pin configured as input the output driver is put into high impedance state Port 8 outputs can be configured as push pull or open drain drivers The input threshold of Port 8 is selectable TTL or special The following Port 8 pins also serve for alternate functions P8 0 CC16lO CAPCOM 2 CC16 Cap In Comp Out P8 7 CC23IO CAPCOMe2 CC23 Cap In Comp Out P7 0 19 26 P7 7 19 22 23 26 1 0 1 0 1 0 Port 7 is an 8 bit bidirectional I O
15. Port 7 Direction Control Register 00h DP8 b FFD6h EBh Port 8 Direction Control Register 00h DPPO FEOOh 00h CPU Data Page Pointer 0 Register 10 bits 0000h DPP1 FEO2h O1h CPU Data Page Pointer 1 Register 10 bits 0001h DPP2 FEO4h 02h CPU Data Page Pointer 2 Register 10 bits 0002h DPP3 FEO6h 03h CPU Data Page Pointer 3 Register 10 bits 0003h EXICON b FiCOhE Eoh External Interrupt Control Register 0000h MDC FFOEh 87h CPU Multiply Divide Control Register 0000h MDH FEOCh 06h CPU Multiply Divide Register High Word 0000h MDL FEOEh 07h CPU Multiply Divide Register Low Word 0000h ODP2 b F1C2hE Eth Port 2 Open Drain Control Register 0000h ODP3 b FIC6hE E3h Port 3 Open Drain Control Register 0000h ODP6 b FICEhE E7h Port 6 Open Drain Control Register 00h ODP7 b F1D2hE E9h Port 7 Open Drain Control Register 00h ODP8 b FiD6hE EBh Port 8 Open Drain Control Register 00h ONES FF1Eh 8Fh Constant Value 1 s Register read only FFFFh POL b FFOOh 80h Port 0 Low Register Lower half of PORTO 00h POH b FFO2h 81h Port 0 High Register Upper half of PORTO 00h P1L b FFO4h 82h Port 1 Low Register Lower half of PORT1 00h P1H b FFO6h 83h Port 1 High Register Upper half of PORT1 00h P2 b FFCOh EOh Port 2 Register 0000h P3 b FFC4h E2h Port 3 Register 0000h P4 b FFC8h E4h Port 4 Register 8 bits 00h P5 b FFA2h D1h Port 5 Register read only XXXXh Table 16 Special function registers listed by name 44 78 42 1701 03 1571
16. Timer 5 Register 0000h T5CON b FF46h A3h GPT2 Timer 5 Control Register 0000h T5IC b FF66h B3h GPT2 Timer 5 Interrupt Control Register 0000h T6 FE48h 24h GPT2 Timer 6 Register 0000h T6CON b FF48h A4h GPT2 Timer 6 Control Register 0000h T6IC b FF68h B4h GPT2 Timer 6 Interrupt Control Register 0000h T FO50hE 28h CAPCOM Timer 7 Register 0000h T78CON b FF20h 90h CAPCOM Timer 7 and 8 Control Register 0000h T7IC b F17AhE BEh CAPCOM Timer 7 Interrupt Control Register 0000h T7REL FO54hE 2Ah CAPCOM Timer 7 Reload Register 0000h T8 FO52hE 29h CAPCOM Timer 8 Register 0000h T8IC b F17ChE BFh CAPCOM Timer 8 Interrupt Control Register 0000h T8REL FO56hE 2Bh CAPCOM Timer 8 Reload Register 0000h TFR b FFACh D6h Trap Flag Register 0000h WDT FEAEh 57h Watchdog Timer Register read only 0000h WDTCON FFAEh D7h Watchdog Timer Control Register 000Xh XPOIC b F186hE C3h CAN Module Interrupt Control Register 0000h XP1IC b F18bEhE C7h X Peripheral 1 Interrupt Control Register 0000h XP2IC b F196hE CBh X Peripheral 2 Interrupt Control Register 0000h XP3IC b F19EhE CFh PLL Interrupt Control Register 0000h ZEROS b FF1Ch 8Eh Constant Value 0 s Register read only 0000h Table 16 Special function registers listed by name Notes 1 The system configuration is selected during reset 2 3 Bit WDTR indicates a watchdog timer triggered reset The Interrupt Control Registers XPnlC control interrupt requests from integrated X Bus p
17. Tole X 1 3 87100 24 1 nsec fcopy 20MHz This is especially important for bus cycles using waitstates and e g for the operation of timers serial interfaces etc For all slower operations and longer periods e g pulse train generation or measurement lower baudrates etc the deviation caused by the PLL jitter is negligible 56 78 42 1701 03 ST DATA SHEET ST10F167 This approximated formula is valid for Max jitter 9 1 N 40 and 10MHZ lt fopy lt 20MHz 4 34 T br Figure 14 Approximated maximum PLL jitter 20 5 5 External clock drive XTAL1 Vpp 5 V 15 Vss 0 V T 40 to 85 Direct Drive 1 1 PLL 1 4 Parameter Symbol Unit min max min max Oscillator period tos SR 50 1 1000 200 333 ns High time t SR 25 6 ns Low time t SR 25 6 ns Rise time t SR 10 10 ns Fall time UuSR 10 10 ns Table 20 External clock drive XTAL1 Notes 1 Theoretical minimum The real minimum value depends on the duty cycle of the input clock signal yy 42 1701 03 57 78 DATA SHEET ST10F167 tosc Figure 15 External clock drive XTAL1 20 5 6 Memory cycle variables The timing tables below use three variables which are derived from the BUSCONXx registers and represent the special characteristics of the programmed memory cycle The following table describes how these variables are to be computed Description
18. advantagesof both RISC and CISC processors and an advanced peripheral subsystem The following block diagram gives an overview of the different on chip components and the high bandwidth intemal bus structure of the ST10F167 16 32 Internal E 16 CPU Core RAM 16 Watcha Interrupt Controller 16 CAN rr E RD ee E E Aa 1 D o o F S I 221 Q 2 O gt e o oo o e z o O N t5 a o a t ot e lt lt lt o o E N O O a o BRG BRG Port 6 Port 5 Port 3 Port 7 Port 8 the Lis Hs Hs Figure 3 Block diagram 12 78 42 1701 03 y DATA SHEET ST10F167 4 Memory Organization The memory space of the ST10F167 is configured in a Von Neumann architecture Code memory data memory registers and l O ports are organized within the same linear address space of 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable The ST10F167 provides 128KBytes of on chip flash memory 2 KBytes of on chip Internal RAM stores user defi ned variables forthe system stack general purpose register banks and even for code A register bank can consist of up to 16 wordwide RO to R15 and or bytewide RLO RHO RL7 RH7 so called General Purpose Registers GPRs 1024 bytes 2 512 bytes of the address space are reserved for the Special
19. in WDTREL Each time itis serviced by the application software the high byte of the watchdog timer is reloaded The table below shows the watchdog timer range for 20MHz CPU clock Some numbers are rounded to 3 significant digits Pr ler for f Reload value escaler for fcpy in WDTREL 2 WDTIN 0 128 WDTIN 1 FFy 25 6 us 1 64 ms 00y 6 55 ms 419 ms Table 14 Watchdog timer range Note For security rewrite WDTCON each time before the watchdog timer is serviced ii 42 1701 03 37 78 ST10F167 DATA SHEET 17 Instruction Set The table below lists the instruction set of the ST10F167 More detailed information such as address modes instruction operation parameters for conditional execution of instructions opcodes and a detailed description of each instruction can be found in the ST10 Family Programming Manual Mnemonic Description Bytes ADD B Add word byte operands 2 4 ADDC B Add word byte operands with Carry 2 4 SUB B Subtract word byte operands 2 4 SUBC B Subtract word byte operands with Carry 2 4 MUL U Un Signed multiply direct GPR by direct GPR 16 16 bit 2 DIV U Un Signed divide register MDL by direct GPR 16 16 bit 2 DIVL U Un Signed long divide reg MD by direct GPR 32 16 bit 2 CPL B Complement direct word byte GPR 2 NEG B Negate direct word byte GPR 2 AND B Bitwise
20. indirect addressing modes can be used for reading the FLASH memory All programming or erase operations are controlled via a 16 bit register the FCR The FCR is not an SFR or GPR To prevent inadvertent writing to the FLASH memory the FCR is locked and inactive during the standard operation mode The FLASH memory writing mode must be entered before a valid access to the FCR is provided This is done via a special key code instruction seguence The FCR is virtually mapped into the active address space of the Flash memory It can only be accessed with direct 16 bit mem addressing modes Since the FCR is neither byte nor bit addressable only word operand instructions can be used for FCR accesses By default the FCR can be accessed with any even address from 000000h to 07FFFEh and 018000h to 02FFFEh If the first 32K byte Block of the FLASH memory is mapped to segment 1 the corresponding even FCR addresses are 010000h to 017FFEh Note that DPP referencing and DPP contents must be considered for FCR accesses If an FCR access is attempted via an odd address an illegal operand access hardware trap will occur FCR Flash Control Register Reset Condition 0000h Read LT 42 1701 03 15 78 ST10F167 DATA SHEET Bit number amp name Description b15 FWMSET Flash Writing Mode Set This bit is setto 1 automatically once the Flash writing mode is entered To exit from the Flash writing mode FWMSET must be set to
21. lt lo gt lal S y qi o o a o a en E 7 o o o x xt 9 BRG BR I P 5 P 3 i P 7 P 8 A D converter O 16 channel 10 bit 9 7us conversion time Clock Generation O On chip PLL O Direct clock input Up to 111 General Purpose I O Lines Programmable threshold hysteresis Idle and power down modes O Idle current lt 70mA O Power down supply current lt 100LA 4 Channel PWM Unit Serial channels Synchronous asynch serial channel O High speed synchronous channel Electrical characteristics Power 5 volt 10 Development support C Compilers Macro Assembler Packages Emulators Evaluation Boards HLL Debuggers Simulators Logic Analyzer Disassemblers Programming Boards Package option 144 Pin PQFP Package 10 September 98 DATA SHEET ST10F167 Table of Contents 1 Introduction 4 2 PinData 5 3 Functional Description 12 4 Memory Organization 13 5 Flash Memory 14 5 1 Flash programming and erasing 15 5 2 Flash Control Register FCR 15 5 2 Flash memory Secure See eae oe See ee mamme me 18 6 External Bus Controller 20 7 Central Processing Unit CPU 21 8 Interrupt System 22 9 Capture compare CAPCOM Units 26 10 General
22. mode Data width shift direction clock polarity and phase are programmable This allows communication with SPI compatible devices Transmission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability allowing baud rate generation independent from the timers SSCBR is the dual function Baud Rate Generator Reload register The table below lists some possible baud rates against the reguired reload values and the resulting bit times fora 20MHz CPU clock Baud Rate Bit Time Reload Value Reserved use a reload value gt 0 00004 5 MBaud 200 ns 0001 y 3 3 MBaud 303 ns 0002y 2 5 MBaud 400 ns 00034 2 MBaud 500 ns 00044 1 MBaud 1 us 0009 100 KBaud 10 us 0063 10 KBaud 100 us 03E7 y 1 KBaud 1 ms 270Fy 152 6 Baud 6 6 ms FFFF y Table 13 Synchronous baud rate and reload values yy 42 1701 03 35 78 DATA SHEET ST10F167 15 Can Module The integrated CAN Module performs the autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active The on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers The module provides full CAN functionality for up to 15 message objects Message object 15 may be co
23. tc 2TCL 45 ns with RW delay to RD to valid data in ts SR 55 3TCL 20 ns no RW delay lc ALE low to valid data in tie SR 40 t to 3TCL 35 ns ta fc Address to valid data in t SR 60 4TCL 40 ns Pty ty 2ta tc Data hold after RD ts SR 0 0 ns rising edge Data float after RD tig SR 35 tr 2TCL 15 4tr ns Data valid to WR t SR 15 tc 2TCL 35 ns t tc Data hold after WR is 06 35 te 2TCL 15 ns tr ALE rising edge after RD t CC 35 t 2TCL 15 ns WR tr Address hold after RD WR ty CC 35 t 2TCL 15 t ns ALE falling edge to CS tss GC 5 ta 10 ta 5 ta 10 t4 ns CS low to Valid Data In t SR 45 3TCL 30 ns to 2ta to 2ty Table 22 Multiplexed bus characteristics yy 42 1701 03 59 78 DATA SHEET ST10F167 Max CPU Clock Variable CPU Clock Parameter Symbol 20 MHz 1 2TCL 1 to 20 MHz Unit min max min max CS hold after RD WR Lo CC 60 tp 3TCL 15 tp ns ALE fall edge to RdCS t CC 20 t4 TCL 5 ta ns WrCS with RW delay ALE fall edge to RdCS t CC 5 t 5 t ns WrCS no RW delay Address float after RACS t CC 0 0 ns WrCS with RW delay Address float after RACS t CC 25 TCL ns WrCS no RW delay RdCS to Valid Data In te SR 15 t 2TCL 35 ns with RW delay to RdCS to Valid Data In t SR 50 tc 3TC
24. the microcontroller Any of these interrupt reguests can be programmed to being serviced by the Interrupt Controller or bythe Peripheral Event Controller PEC In a standard interrupt service program execution is suspended and a branch to the interrupt vector table is performed For a PEC service just one cycle is stolen from the current CPU activity A PEC service is a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source or the destination pointer An individual PEC transfer counter is decremented for each PEC service except for the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the corresponding source related vector location PEC services are suited to for example the transmission or reception of blocks of data The ST10F167 has 8 PEC channels each of which offers fast interrupt driven data transfer capabilities A separate control register which contains an interrupt request flag an interrupt enable fl ag and an interrupt priority bitfield exists for each of the possible interrupt sources Via its related register each source can be programmed to one of sixteen interrupt priority levels Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service reguest Forthe standard interrupt processing each of the possible interrupt sources has a dedicated vector location Fast
25. 0h to O2FFFFh For flexibility the first 32K bytes of the FLASH memory may be remapped to segment 1 010000h to 017FFFh during initialization This allows the interrupt vectors to be programmed from the external memory while retaining the common routines and constants that are progammed into the FLASH memory Bank Addresses Segment 0 Size bytes 0 000000h to 07FFFh and 018000h to 01BFFFh 48K 1 01C000h to 027FFFh 48K 2 028000h to 02DFFFh 24K 3 02E000h to 02FFFFh 8K Table 2 Flash memory bank addresses 14 78 42 1701 03 y DATA SHEET ST10F167 5 1 Flash programming and erasing The FLASH memory is programmedusing the PRESTO F ProgramWrite algorithm Erasure of the FLASH memory is performed in the program mode using the PRESTOF Erase algorithm Timing of the Write Erase cycles is automatically generated by a programmable timer and completion is indicated by a fl ag A second flag indicates that the V voltage was correct for the whole programming cycle This guarantees that a good write erase operation has been carried out Parameter Units Min Typical Max Word Programming Time usec 12 8 12 8 1250 Bank Erasing Time sec 0 5 30 Endurance cycles 1000 Flash Vpp volts 11 4 12 6 Table 3 Flash Parameters 5 2 Flash Control Register FCR In the standard operation mode the FLASH memory can be accessed in the same way as the normal mask programmable on chip ROM All appropriate direct and
26. 10 CC10IR CC10IE CC10INT 00 0068h 1Ah CAPCOM Register 11 CC11IR CC11IE CC11INT 00 006Ch 1Bh CAPCOM Register 12 CC121R CC42IE CC12INT 00 0070h 1Ch CAPCOM Register 13 CC13IR CC13IE CC13INT 00 0074h 1Dh CAPCOM Register 14 CC14IR CC14IE CC14INT 00 0078h 1Eh CAPCOM Register 15 CC15IR CC15IE CC15INT 00 007Ch 1Fh CAPCOM Register 16 CC16IR CC16IE CC16INT 00 00COh 30h CAPCOM Register 17 CC17IR CC17IE CC17INT 00 00C4h 31h CAPCOM Register 18 CC18IR CC18IE CC18INT 00 00C8h 32h CAPCOM Register 19 CC19IR CC19IE CC19INT 00 00CCh 33h CAPCOM Register 20 CC20IR CC20IE CC20INT 00 00DOh 34h CAPCOM Register 21 CC21IR CC21IE CC21INT 00 00D4h 35h CAPCOM Register 22 CC221R CC22IE CC22INT 00 00D8h 36h CAPCOM Register 23 CC23IR CC23IE CC23INT 00 00DCh 37h CAPCOM Register 24 CC24IR CC2AIE CC24INT 00 00EOh 38h CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E4h 39h CAPCOM Register 26 CC26IR CC26IE CC26INT 00 00E8h 3Ah CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00ECh 3Bh CAPCOM Register 28 CC28IR CC28IE CC28INT 00 00EOh 3Ch CAPCOM Register 29 CC29IR CC29IE CC29INT 00 0110h 44h CAPCOM Register 30 CC30IR CC30IE CC30INT 00 0114h 45h Table 5 List of interrupt sources 1571 42 1701 03 23 78 DATA SHEET ST10F167 Source of Interrupt or Reguest Enable Interrupt Vector Trap PEC Service Reguest Flag Flag Vector Location Number CAPCOM Register 31 CC31IR CC31IE CC31INT 00 0118h 46h CAPCOM Timer 0 TOI
27. 10F167 A23 A16 A15 A8 BHE Read Cycle 1 1 tis iets Write Cycle Figure 18 External memory cycle multiplexed bus no read write delay normal ALE 42 1701 03 63 78 ST10F167 DATA SHEET ALE A23 A16 A15 A8 BHE Read Cycle BUS Address el e me t tts 3 tty la lig a Sy Write Cycle ind los gt T r t lo mal n l5 T ha T 1 3 64 78 Figure 19 External memory cycle multiplexed bus no read write delay extended ALE 42 1701 03 DATA SHEET ST10F167 20 5 8 Demultiplexed Bus VDD 5V X596 Vas 0 V Ta 40 to 85 C C for PORTO PORT1 Port 4 ALE RD WR BHE CLKOUT 100 pF C for Port 6 CS 100 pF ALE cycle time 4 TCL 2t t tr 100 ns at 20 MHz CPU clock without waitstates Max CPU Clock Variable CPU Clock Parameter Symbol 20 MHz 1 2TCL 1 to 20 MHz Unit min max min max ALE high time th CC 15 t TCL 10 t4 ns Address setup to ALE tg CC 0 t x TCL 25 ta ns ALE falling edge to RD tg CC 15 t TCL 10 ns WR with RW delay t ALE falling edge to RD tg CC 10 t 10 ta ns WR no RW delay RD WR low time tip CC 25 te 2TCL 25
28. 11ms 26 2ms 52 4ms 105ms 210ms 419ms 839ms 1 68s Table 9 GPT2 timer input freguencies resolution and period yy 42 1701 03 29 78 DATA SHEET ST10F167 V x T2EUD U D GPT1 Timer T2 EE Interrupt Request CPU Clock on n 3 10 T2 Y T2IN ry Mode Reload Control Capture CPU Clock Si GPT1 Timer T3 T3OT Control En PON T3IN F Capture Reload Interrupt J gt Mode T4IN Request CPU Clock 2 n 3 10 2 n 3 10 GPT1 Timer T4 gene Interrupt Fl J t U D Control Figure 7 Block diagram of GPT1 TSEUD _ CPU Cl 9 Jun DOOR pnn 2 9 GPT Ti T5 Interrupt MN mer Request Interrupt CAPIN Request Interrupt Request T6IN T6 Fu CPU Clock Mode GPT2 Timer T6 T6OUT y 2 Control E U D to CAPCOM puc ee Timers Figure 8 Block diagram of GPT2 30 78 42 1701 03 DATA SHEET ST10F167 11 PWM Module The Pulse Width Modulation unit can generate up to four PWM output signals using edge aligned or centre aligned PWM In addition the PWM module can generate PWM burst signals and single shot outputs The table below shows the PWM frequencies for different resolutions The level of the output signals is selectable and the PWM module can generate interrupt requests Mode 0 Resolution 8 bit 10 bit 12 bit 14 bit 16 bit CPU Clock 1 50ns 7813KHz 19 53
29. 24 CC27 to indicate the occurrence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the valuein a capture compare register specific actions will be taken based on the selected compare mode 26 78 42 1701 03 y DATA SHEET ST10F167 Compare Modes Function Mode 0 Interrupt only compare mode several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match several compare events per timer period are possible Mode 2 Interrupt only compare mode only one compare interrupt per timer period is generated Mode 3 Pin set 1 on match pin reset 0 on compare time overflow only one compare event per timer period is generated Double Two registers operate on one pin pin toggles on each compare match Register Mo
30. 4 VPPRIV Vee Revelation bit Read only bit reflects the state of the Vpp voltage in the Flash writing mode If VPPRIV is set to 0 this indicates that Vp is below the thresh old necessary for reliable programming The normal reaction to this indi cation is to check the Vpp power supply and to then repeat the intended operation If the Vpp voltage is above a sufficient margin VPPRIV will be set to 1 The reset state of the VPPRIV bit depends on the state of the external Vpp voltage at the Vpp pin 16 78 Table 4 Flash control register bit definition 42 1701 03 1571 DATA SHEET ST10F167 Bit number amp name Description b3 FCVPP Flash Vpp control bit Read only bit indicates that the V voltage fell below the valid threshold value during a Flash programming or erase operation lf FCVPP is set to 1 after such an operation has finished it can mean that the operation was not successful The Vpp power supply should be checked and the operation repeated If FCVPP is set to 0 no critical discontinuity in Vpp occurred At reset FCVPP is set to 0 b2 FBUSY Flash busy bit Read only bit indicates that a Flash programming or erase operation is in progress FBUSY is set to 1 by hardware as soon as the programming or erase command is given At reset FBUSY is set to 0 Note that this bit position is also occupied by the write only bit RPROT b2 RPROT Protection enab
31. 4NILMd d Sel E Sh Q0A d gel de oc b SSA B ZZL T gS n 8WO HId D 821 poh 6V L Hld 9 621 es h OLY Z HLd 4 0EI E ch LlWE HId LEL 09 IS OlpZOO ZLW Hld 5 ZEL os d OISZOO ELW S HId 9 eel 6b p Ol9202 V1V 9 HId a pel 8t h OIZ299 S1W Z HLd 9 SEL Iva adn g 9 l op B ZWLX a 781 gp p VIVLIX 0 884 vn SSA o 6EL ern NIISH E 0pL eva 1NOLSY S Ht lr A TAN o er orn SSA m pl O een 90A E yl 8 p Zen ap X nm E zz av x 00o 9m OLIO x qu o OO o ok 299000846 d g amp gesreo AORERDQEZ SReosou o BE LLLLLLIZ bSunsScS Ce LAW A wit MANDATO a y 0 7 5 00 I O 2022222220 2 Q Ma 500 cO e 09 C9 YG ecnonoeonooeocoeonu lt ccrcc gt e gt oenononooonono gt gt gt eeo n0o0o0o0 R 0 O O O O O O O O P6 0 CS0 P6 1 CS1 P6 2 CS2 P6 3 CS3 P6 4 CS4 P6 5 HOLD P6 6 HLDA P6 7 BREO P8 0 CC16 P8 1 CC17 P8 2 CC18 P8 3 CC19 P8 4 CC20 P8 5 CC21 P8 6 CC22 P8 7 CC23 P5 0 ANO P7 0 POUTO P7 1 POUT1 P7 2 POUT2 P7 3 POUT3 P7 4 CC2810 P7 5 CC2910 P7 6 CC3010 P7 7 CC3110 P5 1 AN1 P5 2 AN2 P5 3 AN3 P5 4 AN4 P5 5 AN5 P5 6 AN6 P5 7 AN7 P5 8 AN8 P5 9 AN9 ada SSA NIp1 S Ed GnaeL t d LNOEL E Ed NldVO c d 1f1O91 L d NIO L O Ed NIZL NIZX3 OIS LOO S E 2d NI9X3 Olt LOO v Led NISX3 OI LO9 E L 2d NIVX3 Olc LO9 c Fed NI X3OILLOO LE ed NIZX30101909 01 2d NILX3 OI609 6 2d NIOX3 01899 8 cd aa SSA Ol ZO9 ed OI909 9 cd OISOO S dd OIvOO r Zd Ol 092 cd
32. 701 03 25 78 DATA SHEET ST10F167 9 Capture compare CAPCOM Units The CAPCOM units support generation and control of timing seguences on up to 32 channels It has a maximum resolution of 400 ns at 20MHz CPU clock The CAPCOM units are typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PMW Digital to Analog D A conversion software timing or time recording relative to external events Four 16 bit timers TO T1 T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several pre scaled values of the internal system clock or may be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific reguirements In addition external count inputs for CAPCOM timers TO and T7 allow event scheduling for the capture compare registers relative to external events Both of the two capture compare register arrays contain 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer TO or T1 T7 or T8 respectively and programmed for capture or compare function Each register has one port pin associated with it which serves as an input pin for triggering the capture function or as an output pin except for CC
33. A PORTO PORT1 Port 4 ALE RD 2 4 lou 2 2 4 mA WR BHE CLKOUT RSTOUT Output high voltage Von CC SV V lou 250 uA all other outputs 2 4 lon 1 6 mA Input leakage current Port 5 loz CC 1 HA 0 45V lt Vin lt Voo Input leakage current all other loz CC 1 HA 0 45V lt Vin lt Vpp Overload current lov SR 5 mA 5 8 RSTIN pullup resistor Rast CC 50 250 kQ Read Write inactive current ME 40 uA Vour 2 4 V Read Write active current our 9 500 uA Vour Vols ALE inactive current 4 lALEL 2 30 uA Vour VoLmax Table 17 DC characteristics 1571 42 1701 03 49 78 DATA SHEET ST10F167 Limit Values Parameter Symbol Unit Test Condition min max ALE active current ERO 500 uA Vour 2 4 V Port 6 inactive current 4 E 2 40 uA Vour 2 4 V Port 6 active current mE 500 uA Voor Voir PORTO configuration current IPOH 2 10 uA Vin Vitimin IPoL 3 100 uA Vin Vitmax XTAL1 input current lL CC 20 uA 0 V Vin lt Vpp Pin capacitance 5 Cig CC 10 pF f 1MHz digital inputs outputs Ty 25 T Power supply current loc 120 mA RSTIN V 9 fcpu fcpu in MHz 9 Idle mode supply current lip 40 mA RSTIN Vi 2 fopu fcpu in MHz 9 Power down mode supply current Ipp 100 uA Vop 5 25 V A Vpp Read Current Ippn 200 uA Vpp lt Vop Vpp Write Current Ippw s 50 mA at 20MHz 32 Bit progr
34. APCOM Register 20 Interrupt Control Register 0000h CC21 FE6Ah 35h CAPCOM Register 21 0000h CC21IC b F16AhE B5h CAPCOM Register 21 Interrupt Control Register 0000h CC22 FE6Ch 36h CAPCOM Register 22 0000h Table 16 Special function registers listed by name 42 78 42 1701 03 1571 DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value CC22lC b F16ChE B6h CAPCOM Register 22 Interrupt Control Register 0000h CC23 FE6Eh 37h CAPCOM Register 23 0000h CC23IlC b F16EhE B7h CAPCOM Register 23 Interrupt Control Register 0000h CC24 FE70h 38h CAPCOM Register 24 0000h CC24lC b F170hE B8h CAPCOM Register 24 Interrupt Control Register 0000h CC25 FE72h 39h CAPCOM Register 25 0000h CC25IC b F172hE B9h CAPCOM Register 25 Interrupt Control Register 0000h CC26 FE74h 3Ah CAPCOM Register 26 0000h CC26IC b F174hE BAh CAPCOM Register 26 Interrupt Control Register 0000h CC27 FE76h 3Bh CAPCOM Register 27 0000h CC27IC b F176hE BBh CAPCOM Register 27 Interrupt Control Register 0000h CC28 FE78h 3Ch CAPCOM Register 28 0000h CC28IC b F178hE BCh CAPCOM Register 28 Interrupt Control Register 0000h CC29 FE7Ah 3Dh CAPCOM Register 29 0000h CC29IC b F184hE C2h CAPCOM Register 29 Interrupt Control Register 0000h CC30 FE7Ch 3Eh CAPCOM Register 30 0000h CC30lC b F18ChE C6h CAPCOM Register 30 Interrupt Control Register 0000h CC31
35. FE7Eh 3Fh CAPCOM Register 31 0000h CC31IC b F194hE CAh CAPCOM Register 31 Interrupt Control Register 0000h CCMO b FF52h A9h CAPCOM Mode Control Register 0 0000h CCM1 b FF54h AAh CAPCOM Mode Control Register 1 0000h CCM2 b FF56h ABh CAPCOM Mode Control Register 2 0000h CCM3 b FF58h ACh CAPCOM Mode Control Register 3 0000h CCM4 b FF22h 91h CAPCOM Mode Control Register 4 0000h CCM5 b FF24h 92h CAPCOM Mode Control Register 5 0000h CCM6 b FF26h 93h CAPCOM Mode Control Register 6 0000h CCM7 b FF28h 94h CAPCOM Mode Control Register 7 0000h CP FE10h 08h CPU Context Pointer Register FCOOh CRIC b FF6Ah B5h GPT2 CAPREL Interrupt Control Register 0000h CSP FEO8h 04h CPU Code Segment Pointer Register read only 0000h DPOL b F100hE 80h POL Direction Control Register 00h Table 16 Special function registers listed by name 1571 42 1701 03 43 78 DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value DPOH b F102hE 8th POH Direction Control Register 00h DP1L b F104hE 82h P1L Direction Control Register 00h DP1H b F106hE 83h P1H Direction Control Register 00h DP2 b FFC2h E1h Port 2 Direction Control Register 0000h DP3 b FFC6h E3h Port 3 Direction Control Register 0000h DP4 b FFCAh E5h Port 4 Direction Control Register 00h DP6 b FFCEh E7h Port 6 Direction Control Register 00h DP7 b FFD2h E9h
36. Function Register areas SFR space and ESFR space SFRs are wordwide registers which are used for controlling and monitoring functions of the different on chip units Unused SFR addresses are reserved for other future members of the ST10 family 2 KBytes of on chip Extension RAM XRAM are provided to store user data user stacks or code The XRAM is accessed like external memory and cannot be used forthe system stack or register banks and is not bit addressable The XRAM allows 16 bit accesses with maximum speed In order to meet the needs of designs where more memory is required than is provided on chip up to 16 MBytes of external RAM and or ROM can be connected to the microcontroller iy 42 1701 03 13 78 DATA SHEET ST10F167 5 Flash Memory The ST10F167 provides 128KBytes of on chip electrically erasable and re programmalle Flash EPROM The flash memory is organized in 32 bit wide blocks Double word instructions can be fetched in one machine cycle The flash memory can be used for both code and data storage It is into four banks of sizes 8K 24K 48K and 48Kbytes Each of these banks can be erased independently This prevents unnecessary re programming of the whole flash memory when only a partial re programming is required The first 32K bytes of the FLASH memory are located in segment 0 Oh to 007FFFh during reset and include the reset and interrupt vectors The rest of the FLASH memory is mapped in segments 1 and 2 01800
37. KHz 4 883KHz 1 221KHz 0 305KHz CPU Clock 64 3 2ns 1 221KHz 305 2 Hz 76 29Hz 19 07Hz 4 768Hz Mode 1 Resolution 8 bit 10 bit 12 bit 14 bit 16 bit CPU Clock 1 50ns 39 06KHz 9 766KHz 2 441KHz 610 4Hz 152 6Hz CPU Clock 64 3 2ns 610 4Hz 152 6 Hz 38 15Hz 9 537Hz OHz Table 10 PWM unit frequencies and resolution at 20MHz CPU clock Up Down Clear Control Output Control Write Control rr mni Control Run o e POUTK Enable pour 1 MC801948 Figure 9 Block diagram of PWM module LT 42 1701 03 31 78 DATA SHEET ST10F167 12 Parallel Ports The ST10F167 provides up to 111 I O lines which are organized into eight input output ports and one input port All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of three I O ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs The input threshold of Port 2 Port 3 Port 7 and Port 8 is selectable TTL or CMOS like The special CMOS like input threshold reduces noise sensitivity due to the input hysteresis The input threshold may be selected individually for each byte of the respective ports All port lines h
38. L 25 ns no RW delay lc RdCS WrCS Low Time tia CC 40 t 2TCL 10 ns with RW delay lc RdCS WrCS Low Time t CC 65 t 3TCL 10 ns no RW delay to Data valid to WrCS to CC 35 4 tc 2TCL 15 ns to Data hold after RACS ts SR 0 0 ns Data float after RACS tb SR 30 tr 21TCL 20 tr ns Address hold after t CC 30 t 2TCL 20 tr ns RdCS WrCS Data hold after WrCS tss CC 30 tp 2TCL 20 tp ns 60 78 42 1701 03 Table 22 Multiplexed bus characteristics DATA SHEET ST10F167 lo or li ls n ALE A23 A16 ug ti7 gt i mety A15 A8 E Address BHE Ll gt H tt ea Read Cycle alis A aus METAL t i inet ta tH i leo 14 l48 Mo lm lu et WrCSx Ne A te Figure 16 External memory cycle multiplexed bus with read write delay normal ALE iy 42 1701 03 61 78 DATA SHEET ST10F167 A23 A16 A15 A8 BHE ee to Read Cycle i i etg sus XK Address Y an gt to NE r kaf Write Cycle i bs BUS Address Data Out TN i le 9 it ts tm ilo Figure 17 External memory cycle multiplexed bus with read write delay extended ALE 62 78 42 1701 03 ST DATA SHEET ST
39. Purpose Timer GPT Unit 28 10 1 GPT1 eee ee ee 28 10 2 GPT2 ee ee eee 29 11 PWM Module 31 12 Parallel Ports 32 13 A D Converter 33 14 Serial Channels 34 14 1 ASCO 34 14 2 High speed synchronous serial channel SSC 35 2 78 42 1701 03 DATA SHEET ST10F167 15 Can Module 36 16 Watchdog Timer 37 17 Instruction Set 38 18 Bootstrap Loader 40 19 Special Function Registers 40 20 Electrical Characteristics 48 20 1 Absolute maximum ratings 48 20 2 Parameter interpretation 48 20 3 DC Characteristics 49 20 4 A D Converter Characteristics 52 20 5 AC Characteristics 54 20 5 1 Test waveforms 54 20 5 2 Definition of internal timing 54 20 5 3 Direct Drive 55 20 5 4 Phase locked loop 56 20 5 5 External clock drive XTAL1 57 20 5 6 Memory cycle variables 58 20 5 7 Multiplexed Bus 58 20 5 8 Demultiplexed Bus
40. R TOIE TOINT 00 0080h 20h CAPCOM Timer 1 T1IR THE T1INT 00 0084h 21h CAPCOM Timer 7 T7IR T7IE T7INT 00 00F4h 3Dh CAPCOM Timer 8 T8IR T8IE T8INT 00 00F8h 3Eh GPT1 Timer 2 T2IR T2IE T2INT 00 0088h 22h GPT1 Timer 3 T3IR TSIE T3INT 00 008Ch 23h GPT1 Timer 4 TAIR TAIE TAINT 00 0090h 24h GPT2 Timer 5 T5IR T5IE T5INT 00 0094h 25h GPT2 Timer 6 T6IR T6IE T6INT 00 0098h 26h GPT2 CAPREL Register CRIR CRIE CRINT 00 009Ch 27h A D Conversion Complete ADCIR ADCIE ADCINT 00 00A0h 28h A D Overrun Error ADEIR ADEIE ADEINT 00 00A4h 29h ASCO Transmit SOTIR SOTIE SOTINT 00 00A8h 2Ah ASCO Transmit Buffer SOTBIR SOTBIE SOTBINT 00 011Ch 47h ASCO Receive SORIR SORIE SORINT 00 00ACh 2Bh ASCO Error SOEIR SOEIE SOEINT 00 00BOh 2Ch SSC Transmit SCTIR SCTIE SCTINT 00 00B4h 2Dh SSC Receive SCRIR SCRIE SCRINT 00 00B8h 2Eh SSC Error SCEIR SCEIE SCEINT 00 00BCh 2Fh PWM Channel 0 3 PWMIR PWMIE PWMINT 00 00FCh 3Fh CAN Interface XPOIR XPOIE XPOINT 00 0100h 40h X Peripheral Node XP1IR XP1IE XP1INT 00 0104h 41h X Peripheral Node XP2IR XP2IE XP2INT 00 0108h 42h PLL Unlock XP3IR XP3IE XP3INT 00 010Ch 43h Table 5 List of interrupt sources Note Two X Peripheral nodes can accept interrupt requests from integrated X Bus peripherals Nodes where no X Peripherals are connected may be used to generate software controlled interrupt requests by setting the respective XPnIR bit 24 78 42 1701 03 y DATA SHEET ST10F167 The ST10F167 identifies and to processes exception
41. Register 0000h SSCTB FOBOhE 58h SSC Transmit Buffer write only 0000h SSCTIC b FF72h B9h SSC Transmit Interrupt Control Register 0000h STKOV FE14h OAh CPU Stack Overflow Pointer Register FA00h STKUN FE16h OBh CPU Stack Underflow Pointer Register FCOOh SYSCON b FF12h 89h CPU System Configuration Register OxxOh TO FE50h 28h CAPCOM Timer O Register 0000h TO1CON b FF50h A8h CAPCOM Timer 0 and Timer 1 Control Register 0000h TOIC b FF9Ch CEh CAPCOM Timer 0 Interrupt Control Register 0000h TOREL FE54h 2Ah CAPCOM Timer 0 Reload Register 0000h T1 FE52h 29h CAPCOM Timer 1 Register 0000h T1IC b FF9Eh CFh CAPCOM Timer 1 Interrupt Control Register 0000h T1REL FE56h 2Bh CAPCOM Timer 1 Reload Register 0000h T2 FE40h 20h GPT1 Timer 2 Register 0000h T2CON b FF40h AOh GPT1 Timer 2 Control Register 0000h T21C b FF60h BOh GPT1 Timer 2 Interrupt Control Register 0000h T3 FE42h 21h GPT1 Timer 3 Register 0000h T3CON b FF42h A1h GPT1 Timer 3 Control Register 0000h T3IC b FF62h Bih GPT1 Timer 3 Interrupt Control Register 0000h Table 16 Special function registers listed by name 46 78 42 1701 03 1571 DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value T4 FE44h 22h GPT1 Timer 4 Register 0000h T4CON b FF44h A2h GPT1 Timer 4 Control Register 0000h T4IC b FF64h B2h GPT1 Timer 4 Interrupt Control Register 0000h T5 FE46h 23h GPT2
42. ST10F167 Program Selected Bank to 0000 Program FCR Register Initialize Address Pointers FAIL Set PCOUNT O Erase Selected Bank Wait until Erase Time Elapsed Vpp PCOUNT ENmax pennant ay Ergse Verify Mode Read Operation DatazFFFFh YES Disable Flash Erase Operations PCOUNT PCOUNT 1 Increment Address Pointers Pulse Width TPRG lt 20 ms TPRG ENmax lt 30 sl VR02057B Figure 5 PRESTO F erase algorithm yy 42 1701 03 19 78 DATA SHEET ST10F167 6 External Bus Controller All of the external memory accesses are performed by the on chip External Bus Controller EBC It can be programmed either to single chip mode when no external memory is required orto one of four different external memory access modes e 16 18 20 24 bit Addresses 16 bit Data Demultiplexed e 16 18 20 24 bit Addresses 16 bit Data Multiplexed e 16 18 20 24 bit Addresses 8 bit Data Multiplexed e 16 18 20 24 bit Addresses 8 bit Data Demultiplexed In the demultiplexed bus modes addresses are output on PORT1 and data is input output on PORTO In the multiplexed bus modes both addresses and data use PORTO for input output Important timing characteristics of the external bus interface Memory Cycle Time Memory Tri State Time Length of ALE and Read Write Delay have been made programmaHe This gives the choice of a wide range of differenttypes of memo
43. Symbol Values ALE Extension ta TCL lt ALECTL gt Memory Cycle Time Waitstates tc 2TCL 15 lt MCTC gt Memory Tristate Time tr 2TCL 1 lt MTTC gt Table 21 Memory cycle variables 20 5 7 Multiplexed Bus Vpp 5 V 2596 Vss 0 V T 40 to 85 C C for PORTO PORT Port 4 ALE RD WR BHE CLKOUT 100 pF C for Port 6 CS 100 pF ALE cycle time 6 TCL 2t t t 150 ns at 20 MHz CPU clock without waitstates Max CPU Clock Variable CPU Clock Parameter Symbol 20 MHz 1 2TCL 1 to 20 MHz Unit min max min max ALE high time ts CC 15 t TCL 10 ta ns Address setup to ALE ts CC Ot TCL 25 t ns Address hold after ALE t CC 15 t4 TCL 10 t ns Table 22 Multiplexed bus characteristics 58 78 42 1701 03 ST DATA SHEET ST10F167 Max CPU Clock Variable CPU Clock Parameter Symbol 20 MHz 1 2TCL 1 to 20 MHz Unit min max min max ALE falling edge to RD tg CC 15 t4 TCL 10 ta ns WR with RW delay ALE falling edge to RD tg CC 10 ta 10 t ns WR no RW delay Address floatafter RD WR ty CC 5 5 ns with RW delay Address floatafter RD WR t44 CC E 30 TCL 4 5 ns no RW delay RD WR low time t CC 25 tc 2TCL 25 ns with RW delay to RD WR low time t4 CC 65 tc 3TCL 10 ns no RW delay lc RD to valid data in ta SR 5 4
44. The count direction up down for each timer is programmale by software or may additionally be altered dynamically by an external signal on a port pin TxEUD Concatenation of the timers is supported by the output toggle latch T6OTL of timer T6 which changes its state on each timer overflow underflow The state of this latch may be used to clock timer T5 or it may be output on a port pin T6OUT The overflows underflows of timer T6 can additionally be used to clock the CAPCOM timers TO or T1 and to cause a reload from the CAPREL register The CAPREL register may capture the contents of timer T5 based on an external signal transition on the corresponding port pin CAPIN and timer T5 may optionally be cleared after the capture procedure This allows absolute time differences to be measured or pulse multiplication to be performed without software overhead Table 9 GPT2 timer input frequencies resolution and period lists the timer input frequencies resolution and periods for each pre scaler option at 25 MHz CPU clock This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode fcpu 20MHz Timer Input Selection T5l T6l 000g 001g lo10g JOt1g 1008 101g 1108 111g Pre scaler factor 4 8 16 32 64 128 256 512 Input Frequency 5 25 1 25 625 313 156 78 1 39 1 MHz MHz MHz kHz kHz kHz kHz kHz Resolution 200ns 400ns 800ns 1 60us 3 20us 6 40us 12 8us 25 6us Period 13
45. Width Register 3 0000h PWMCONODb FF30h 98h PWM Module Control Register 0 0000h PWMCON 1b FF32h 99h PWM Module Control Register 1 0000h PWMIC b F17EhE BFh PWM Module Interrupt Control Register 0000h RPOH b F108hE 84h System Startup Configuration Register Rd only XXh SOBG FEB4h 5Ah Serial Channel 0 Baud Rate Generator Reload Reg 0000h SOCON b FFBOh D8h Serial Channel 0 Control Register 0000h Table 16 Special function registers listed by name 1571 42 1701 03 45 78 DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value SOEIC b FF70h B8h Serial Channel 0 Error Interrupt Control Register 0000h SORBUF FEB2h 59h Serial Channel 0 Receive Buffer Register read only XXh SORIC b FF6Eh B7h Serial Channel 0 Receive Interrupt Control Register 0000h SOTBIC b F19ChE CEh Serial Channel 0 Transmit Buffer Interrupt Control 0000h Register SOTBUF FEBOh 58h Serial Channel 0 Transmit Buffer Register write only 00h SOTIC b FF6Ch B6h Serial Channel 0 Transmit Interrupt Control Register 0000h SP FE12h 09h CPU System Stack Pointer Register FCOOh SSCBR FOB4hE 5Ah SSC Baudrate Register 0000h SSCCON b FFB2h D9h SSC Control Register 0000h SSCEIC b FF76h BBh SSC Error Interrupt Control Register 0000h SSCRB FOB2hE 59h SSC Receive Buffer read only XXXXh SSCRIC b FF74h BAh SSC Receive Interrupt Control
46. amming Vpp 12V Vpp during Write Read Vpp 11 4 12 6 V Table 17 DC characteristics Notes 1 This specification is not valid for outputs which are switched to open drain mode In this case the respective output will float and the voltage results from the external circuitry 2 The maximum current may be drawn while the respective signal line remains inactive 3 The minimum current must be drawn in order to drive the respective signal line active 4 This specification is only valid during Reset or during Hold or Adapt mode Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled 5 Not 100 tested guaranteed by design characterization 6 The supply current is a function of the operating frequency This dependency is illustrated in the figure below These parameters are tested at Vppmax and 20 MHz CPU clock with all outputs disconnect ed and all inputs at Vi or Vip 7 This parameter is tested including leakage currents All inputs including pins configured as inputs at O V to 0 1 V or at Vpp 0 1 V to Vpp Vggr 0 V all outputs including pins con figured as outputs disconnected 8 Overload conditions occur if the standard operating conditions are exceeded i e the voltage 50 78 on any pin exceeds the specified range i e Voy gt Vpp 0 5V or Voy lt Vsg 0 5V The ab 42 1701 03 LT DATA SHEET ST10F167 solute sum of input overload currents on all port pins may n
47. an be configured as push pull or open drain drivers The input threshold of Port 2 is selectable TTL or special The following Port 2 pins also serve for alternate functions 47 1 0 P2 0 CCOIO CAPCOM CCO Cap In Comp Out 54 1 0 P2 7 CC7IO CAPCOM CC7 Cap In Comp Out 57 1 0 P2 8 CC8lO CAPCOM CC8 Cap In Comp Out EXOIN Fast External Interrupt O Input 64 1 0 P2 15 CC15I0 CAPCOM CC15 Cap In Comp Out EXTIN Fast External Interrupt 7 Input T7IN CAPCOM2 Timer T7 Count Input Table 1 Pin description 42 1701 03 7 78 DATA SHEET ST10F167 Input l p Symbol Pin a 0 Function P3 0 65 70 1 0 Port 3 is a 15 bit P3 14 is missing bidirectional I O port It is P3 13 73 80 1 0 bit wise programmable for input or output via direction bits For P3 15 81 1 0 a pin configured as input the output driver is put into high im pedance state Port 3 outputs can be configured as push pull or open drain drivers The input threshold of Port 3 is selectable TTL or special The following Port 3 pins also serve for alternate functions 65 P3 0 TOIN CAPCOM Timer TO Count Input 66 O P3 1 T6OUT GPT2 Timer T6 Toggle Latch Output 67 P3 2 CAPIN GPT2 Register CAPREL Capture Input 68 O P3 3 T3OUT GPT1 Timer T3 Toggle Latch Output 69 P3 4 T3EUD GPT1 Timer T3 Ext Up Down Ctrl Input 70 P3 5 T4IN GPT1 Timer T4 Input for Count Gate Reload Capture 73 P3 6 T3IN GPT1 Timer T3 Count Gate Input 74 P3 7 T2IN GPT1 Timer T2 I
48. ave programmahe alternate input or output functions associated with them PORTO and PORT1 may be used as address and data lines when accessing external memory while Port 4 outputs the additional segment address bits A23 19 17 A16 in systems where segmentation is enabled to access more than 64KBytes of memory Port 2 Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM units and or with the outputs of the PWM module Port 6 provides optional bus arbitration signals BREQ HLDA HOLD and chip select signals Port 3 includes alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT Port 5 is used for the analog input channels to the A D converter or timer control signals All port lines that are not used for these alternate functions may be used as general purpose I O lines 32 78 42 1701 03 y DATA SHEET ST10F167 13 A D Converter A 10 bit A D converter with 16 multiplexed input channels and a sample and hold circuit has been integratedon chip for analog signal measurement It uses a successive approximation method The sample time for loading the capacitors and conversion time is programmable and can be modified for the external circuitry Overrun error detection protection is provided through the conversion result register ADDAT When the result of a previous conversion has not been read from the result register at the ti
49. been optimized for speed branches in 2 cycles a 16 X 16 bit multiplication in 5 cycles and a 32 16 bit division in 10 cycles The Jump Cache pipeline optimization reduces the execution time of repeatedly performed jumps in a loop from 2 cycles to 1 cycle The CPU includes an actual register context This consists of up to 16 wordwide GPRs which are physically allocated within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space For easy parameter passing a register bank may overlap others A system stack of up to 2048 bytes is provided as a storage for temporary data The system stack is allocated in the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access forthe detection of a stack overflow or underflow yy 42 1701 03 21 78 DATA SHEET ST10F167 8 Interrupt System With an interrupt response time from 250ns to 600ns in the case of intemal program execution the ST10F167 reacts guickly to the occurrence of non deterministic events The architecture of the ST10F167 supports several mechanisms for fast and flexible response to service reguests that can be generated from various sources internal or external to
50. cuting either a hardware a software or a watchdog timer reset RSTOUT remains low until the EINIT end of initialization instruction is executed NMI 142 Non Maskable Interrupt Input A high to low transition at this pin causes the CPU to vector to the NMI trap routine When the PWRDN power down instruction is executed the NMI pin must be low in order to force the ST10F167 to go into power down mode If NMI is high when PWRDN is executed the part will continue to run in normal mode If not used pin NMI should be pulled high externally V AREF 37 Reference voltage for the A D converter V AGND 38 Reference ground for the A D converter Table 1 Pin description 10 78 42 1701 03 y DATA SHEET ST10F167 Input l Symbol Pin Output O Function Vpp 84 Flash programming voltage This pin accepts the programming voltage for the on chip flash EPROM of the ST10F167 Vop 46 82 E Digital Supply Voltage for internal circuitry 136 5 V during normal operation and idle mode 2 5 V during power down mode 17 56 Digital Supply Voltage for port drivers 72 98 5 V during normal operation and idle mode 109 126 144 Vss 45 83 Digital Ground for internal circuitry 139 18 55 Digital Ground for port drivers 71 94 110 127 143 Table 1 Pin description 42 1701 03 11 78 DATA SHEET ST10F167 3 Functional Description The architecture of the ST10F167 combines
51. de several compare events per timer period are possible Table 6 Compare modes The input freguencies fr for Tx are determined as a function of the CPU clocks The formulas are detailed in the user manual The timer input freguencies resolution and periods which result from the selected pre scaler option in Txl when using a 20MHz CPU clock are listed in the table below The numbers for the timer periods are based on a reload value of 00005 Note that some numbers may be rounded to 3 significant figures fcpu 20MHz Timer Input Selection Txl 0005 001g 010g 011g 100g 101g 110g 111g Pre scaler foricpy 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 313 156 78 1 39 1 19 5 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400ns 800ns 1 60us 3 20us 6 40us 12 8us 25 6us 51 2us Period 26 2ms 52 4ms 105ms 210ms 419ms 839ms 1 68s 3 36s Table 7 CAPCOM timer input frequencies resolution and periods 42 1701 03 27 78 DATA SHEET ST10F167 10 General Purpose Timer GPT Unit The GPT unit is a flexible multifunctional timer counter structure It may be used for many different time related tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication The GPT unit incorporates five 16 bit timers which are organized in two separate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different
52. e ripherals Nodes where no X Peripherals are connected may be used to generate software controlled interrupt requests by setting the respective XPnIR bit 42 1701 03 47 78 DATA SHEET ST10F167 20 Electrical Characteristics 20 1 Absolute maximum ratings Ambient temperature under bias TA ST10F167 sses 40to 85 9C Storage temperature T5 Ts GG GG GO dd GG RE PX aureo Fe 5 to 4150 C Voltage on Vpp pins with respect to ground Vsg sssse 0 5 to 46 5 V Voltage on any pin with respect to ground Vag ssee 0 3to Vpp 0 3 V Input current on any pin during overload condition 10 to 10 mA Absolute sum of all input currents during overload condition 1100 mA POWer CISS QUOI srta 1 5W Note Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed Exposure to absolute maximum rating conditions for extended periods may affect device reliability During overload conditions V y gt Vpp or Viy Vss the voltage on pins With respect to ground Vss must not exceed the values defined by the Absolute Maximum Ratings 20 2 Parameter interpretation
53. er onto web e Preliminary Data becomes Data Sheet The differences between rev 2 and rev 1 are as follows GPT1 timer input freguencies resolution and periods on page 28 Table added GPT2 timer input freguencies resolution and period on page 29 Table added PWM unit frequencies and resolution at 20MHz CPU clock onpage 31 Table added Synchronous baud rate and reload values on page 35 Table added Watchdog timer range on page 36 Table added Bootstrap Loader on page 38 Text changed Page format of the datasheet cover changed yy 42 1701 03 77 78 DATA SHEET ST10F167 Information furnished is believed to be accurate and reliable However STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics Specifications mentioned in this publication are subject to change without notice This publication supersedes and replaces all information previously supplied STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics 1971 3 The ST logo is a registered trademark of STMicroelectronics O 1998 STMicroelectronics All Rights Reserved STM
54. erter Overrun Error Interrupt Control Reg 0000h BUSCONOb FFOCh 86h Bus Configuration Register O OXXOh BUSCONI b FF14h 8Ah Bus Configuration Register 1 0000h BUSCON2 b FF16h 8Bh Bus Configuration Register 2 0000h BUSCON3b FF18h 8Ch Bus Configuration Register 3 0000h BUSCON4b FF1Ah 8Dh Bus Configuration Register 4 0000h CAPREL FE4Ah 25H GPT2 Capture Reload Register 0000h CCO FE80h 40h CAPCOM Register 0 0000h CCOIC b FF78h BCh CAPCOM Register 0 Interrupt Control Register 0000h CC1 FE82h 41h CAPCOM Register 1 0000h CC1IC b FF7Ah BDh CAPCOM Register 1 Interrupt Control Register 0000h CC2 FE84h 42h CAPCOM Register 2 0000h CC2IC b FF7Ch BEh CAPCOM Register 2 Interrupt Control Register 0000h CC3 FE86h 43h CAPCOM Register 3 0000h CC3IC b FF7Eh BFh CAPCOM Register 3 Interrupt Control Register 0000h CC4 FE88h 44h CAPCOM Register 4 0000h CC4IC b FF80h COh CAPCOM Register 4 Interrupt Control Register 0000h CC5 FE8Ah 45h CAPCOM Register 5 0000h CC5IC b FF82h C1h CAPCOM Register 5 Interrupt Control Register 0000h CC6 FE8Ch 46h CAPCOM Register 6 0000h CC6IC b FF84h C2h CAPCOM Register 6 Interrupt Control Register 0000h Table 16 Special function registers listed by name 1571 42 1701 03 41 78 DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value CC7 FE8Eh 47h CAPCOM Register 7 0000h CC7IC b FF86h C3
55. external interrupt inputs are provided to service external interrupts with high precision reguirements These fast interrupt inputs feature programmable edge detection rising edge falling edge or both edges Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number The table below shows all of the possible ST10F167 interrupt sources and the corresponding hardware related interrupt flags vectors vector locations and trap interrupt numbers Source of Interrupt or Reguest Enable Interrupt Vector Trap PEC Service Reguest Flag Flag Vector Location Number CAPCOM Register O CCOIR CCOIE CCOINT 00 0040h 10h CAPCOM Register 1 CC1IR CC1IE CC1INT 00 0044h 11h Table 5 List of interrupt sources 22 78 42 1701 03 y DATA SHEET ST10F167 Source of Interrupt or Reguest Enable Interrupt Vector Trap PEC Service Reguest Flag Flag Vector Location Number CAPCOM Register 2 CC2IR CC2IE CC2INT 00 0048h 12h CAPCOM Register 3 CC3IR CC3IE CC3INT 00 004Ch 13h CAPCOM Register 4 CCAIR CCAIE CCAINT 00 0050h 14h CAPCOM Register 5 CC5IR CC5lE CC5INT 00 0054h 15h CAPCOM Register 6 CC6IR CC6IE CC6INT 00 0058h 16h CAPCOM Register 7 CC7IR CC7IE CC7INT 00 005Ch 17h CAPCOM Register 8 CC8IR CC8IE CC8INT 00 0060h 18h CAPCOM Register 9 CC9IR CC9IE CC9INT 00 0064h 19h CAPCOM Register
56. for BREO to trigger the indicated regain seguence Even if BREO is activated earlier the regain seguence is initiated by HOLD going high Please note that HOLD may also be deactivated without the ST10F167 reguesting the bus 2 The next ST10F167 driven bus cycle may start here Y 42 1701 03 a DATA SHEET ST10F167 21 Package Mechanical Data PIN 1 Dim mm inches IDENTIFICATION min ty max min ty max HE A 4 07 0 106 gos A1 0 25 0 010 a E A2 3 17 3 42 3 67 0 125 0 315 0 144 B 0 22 0 38 0 009 0 015 0 13 0 23 0 005 0 009 D 30 95 31 20 31 45 1 129 1 228 1 238 D1 27 90 28 00 28 10 1 098 1 120 1 106 D3 22 75 0 896 e 0 65 0 02 E 30 95 31 20 31 45 1 219 1 228 1 238 E i E1 27 90 28 00 28 10 1 098 1 102 1 106 Es E3 22 75 0 896 i L 0 65 0 80 0 95 0 026 0 031 0 037 L1 1 60 0 063 K 0 min 7 max Number of Pins K VR02061A M Figure 27 Package Outline PQFP144 28 x 28 mm 22 Ordering Information Salestype Temperature range Package ST10F167 Q6 40 C to 85 C PQFP144 28 x 28 76 78 42 1701 03 ST DATA SHEET ST10F167 23 Revision History This is revision 3 of this document The differences between rev 3 and rev 2 are as follows e Update ofthe ST logo and company name e Re formating of the micron symbol for correct transf
57. h CAPCOM Register 7 Interrupt Control Register 0000h CC8 FE90h 48h CAPCOM Register 8 0000h CC8IC b FF88h C4h CAPCOM Register 8 Interrupt Control Register 0000h CC9 FE92h 49h CAPCOM Register 9 0000h CC9IC b FF8Ah C5h CAPCOM Register 9 Interrupt Control Register 0000h CC10 FE94h 4Ah CAPCOM Register 10 0000h CC10IC b FF8Ch C6h CAPCOM Register 10 Interrupt Control Register 0000h CC11 FE96h 4Bh CAPCOM Register 11 0000h CC11lC b FF8Eh C7h CAPCOM Register 11 Interrupt Control Register 0000h CC12 FE98h 4Ch CAPCOM Register 12 0000h CC121C b FF90h C8h CAPCOM Register 12 Interrupt Control Register 0000h CC13 FE9Ah 4Dh CAPCOM Register 13 0000h CC13lC b FF92h C9h CAPCOM Register 13 Interrupt Control Register 0000h CC14 FE9Ch 4Eh CAPCOM Register 14 0000h CC14lC b FF94h CAh CAPCOM Register 14 Interrupt Control Register 0000h CC15 FE9Eh 4Fh CAPCOM Register 15 0000h CC15lC b FF96h CBh CAPCOM Register 15 Interrupt Control Register 0000h CC16 FE60h 30h CAPCOM Register 16 0000h CC16IC b FI60hE Boh CAPCOM Register 16 Interrupt Control Register 0000h CC17 FE62h 31h CAPCOM Register 17 0000h CC17IC b F162hE Bih CAPCOM Register 17 Interrupt Control Register 0000h CC18 FE64h 32h CAPCOM Register 18 0000h CC18IC b F164hE B2h CAPCOM Register 18 Interrupt Control Register 0000h CC19 FE66h 33h CAPCOM Register 19 0000h CC19IC b F166hE B3h CAPCOM Register 19 Interrupt Control Register 0000h CC20 FE68h 34h CAPCOM Register 20 0000h CC20lC b F168hE B4h C
58. iation and also the derived external timing depends on the mechanism used to generate fcopy This influence must be taken into consideration when calculating the timings for the ST10F167 Phase Locked Loop Operation tu LJ LILI LI LI LI LI TCL TCL Direct Clock Drive tm LI LI LILI LI LI LI LI teu LJ LI LI LI LI LI LI TCLTCL Figure 13 Generation Mechanisms for the CPU clock 20 5 3 Direct Drive When pin P0 15 POH 7 is low 0 during reset the on chip phase locked loop is disabled and the CPU clock is directly driven from the oscillator with the input clock signal The frequency of fcpy directly follows the frequency of fyrAL so the high and low time of fep i e the duration of an individual TCL is defined by the duty cycle of the input clock fyr A The timings listed below that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances This minimum value can be calculated via the following formula DC duty cycle For two consecutive TCLs the deviation caused by the duty cycle of fyr is compensated so the duration of 2TCL is always 1 fyta_ The minimum value TCLmin therefore has to be used only once fortimings that require an odd number of TCLs 1 3 Timings that require an even number of TCLs 2 4 may use the formula 2TCL 1 fy The address float timings in Multiplexed bus mode tj 4 and t45 use the maximum durati
59. icroelectronics GROUP OF COMPANIES Australia Brazil Canada China France Germany Italy Japan Korea Malaysia Malta Mexico Morocco The Netherlands Singapore Spain Sweden Switzerland Taiwan Thailand United Kingdom U S A 78 78 42 1701 03 y
60. lash memory Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation If bit FWE was set to 1 any read access on a Flash memory location means a particular program verify or erase verify read operation Flash write operations are disabled at reset Table 4 Flash control register bit definition 42 1701 03 17 78 DATA SHEET ST10F167 5 2 1 Flash memory security Security and reliability have been enhanced by built in features a key code sequence is used to enter the Write Erase mode preventing false write cycles a programmable option set by the programming board prevents access to the FLASH memory from the internal RAM or from External Memory If the security option is set the FLASH memory can only be accessed from a program within the FLASH memory area This protection can only be disabled by instructions executed from the FLASH memory START Program FCR Register Initialize Address Pointers FAIL YES Cr Load Source Value s and Set PCOUNT 0 Program Double Word Walt until Programming Time Elapsed NO PCOUNT PNmax PCOUNT PCOUNT 1 Vop FAIL permanently FAIL Okay YES Program Verify Mode Read Operation Data Okay Pulse Width TPRG 200 us TPRG PNmax 2 5 ms VR02057A Figure 4 PRESTO F write algorithm 18 78 42 1701 03 DATA SHEET
61. le bit This bit set at 1 anded with the OTP protection bit disables any access to the Flash by instructions fetched from the external memory space or from the internal RAM This write only bit is only significantif the general Flash memory protection is enabled If the protection is enabled the set ting of RPROT determines whether the Flash protection is active RPROT 1 or inactive RPROT 0 RPROT is the only FCR bit which can be modifi ed even in the Flash standard operation mode but only by an instruction executed from the Flash memory itself At reset RPROT is set to 1 Note that this bit position is also occupied by the read only bit FBUSY b1 FEE Flash erase program selection Selects the Flash write operation to be performed erase FEE 1 or programming FEE 0 Together with bits FWE and FWMSET bit FEE determined the operation mode of the Flash memory Note that setting bits FWE and FEE causes the corresponding Flash operation mode to be selected but does not launch the execution of the selected operation If bit FWE was set to 0 the setting of FEE is insignifi cant At reset FEE is set to 0 b0 FWE Flash write read enable This bit determines whether FLASH write operations are enabled FWE 1 or disabled FWE 0 By definition a FLASH write operation can be either programming or erasure Together with bits FEE and FWM SET bit FWE determines the operation mode of the F
62. me the next conversion is complete either an interrupt reguest is generated or the next conversion is suspended until the previous result has been read For applications which reguire less than 16 analog input channels the remaining channel inputs can be used as digital input port pins The A D converter of the ST10F167 supports four different conversion modes e Single Channel conversion mode The analog level on a specified channel is sampled once and converted to a digital result e Single Channel Continuous mode The analog level on a specified channel is repeatedly sampled and converted without software intervention e Auto Scan mode The analog levels on a prespecified number of channels are seguentially sampled and converted e Auto Scan Continuous mode the number of prespecified channels is repeatedly sampled and converted In addition channel injection mode injects a channel into a running seguence without disturbing this seguence The peripheral event controller stores the conversion results in memory without entering and exiting interrupt routines for each data transfer The following table shows the ADC unit conversion clock sample clock and complete conversion times ADCTC Conversion clocktcc ADSTC Sample clocktsc Complete conversion 00 0 6us 00 0 6us 9 7us 01 reserved 01 reserved 10 2 4us 10 9 6us 52 9us 11 1 2us 11 9 6us 36 1us Table 11 ADC sample clock and complete conversion times
63. modes or may be concatenated with another timer of the same module 10 1 GPT1 Each of the three timers T2 T3 T4 of module GPT1 can be configured individually for one of three basic modes of operation timer gated timer and counter mode In timer mode the input clock for a timer is derived from the CPU clock divided by a programmable prescaler counter mode allows a timer to be clocked in reference to external events Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the gate level on an external input pin Each timer has one associated port pin TxIN which serves as gate or clock input Table 8 GPT1 timer input freguencies resolution and periods lists the timer input freguencies resolution and periods for each pre scaler option at 25 MHz CPU clock This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode fcpy 20MHz Timer Input Selection T21 T3I T l 000B 001B 010B 011B 100B 101B 110B 111B Pre scaler 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 313 156 78 1 39 1 19 5 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400ns 800ns 1 60us 3 20us 6 40us 12 8us 25 6us 51 2us Period 26 2ms 52 4ms 105ms 210ms 419ms 839ms 1 68s 3 36s Table 8 GPT1 timer input freguencies resolution and periods The count direction up down for each timer is programmable by software
64. nd for every data write access on an 8 bit bus See WRCFG in register SYSCON for mode selection READY 97 Ready Input When the Ready function is enabled a high level at this pin during an external memory access will force the in sertion of memory cycle time waitstates until the pin returns to a low level ALE 98 O Address Latch Enable Output Can be used for latching the ad dress into external memory or an address latch in the multi plexed bus modes EA 99 External Access Enable pin A low level at this pin during and after Reset forces the ST10F167 to begin instruction execution out of external memory A high level forces execution out of the internal Flash Memory PORTO 1 0 PORTO consists of the two 8 bit bidirectional I O ports POL and POL O 100 107 POH It is bit wise programmable for input or output via direction POL 7 bits For a pin configured as input the output driver is put into POH O 108 high impedance state POH 7 111 117 In case of an external bus configuration PORTO serves as the address A and address data AD bus in multiplexed bus modes and as the data D bus in demultiplexed bus modes Demultiplexed bus modes Data Path Width 8 bit 16 bit POL O POL 7 DO D7 DO D7 POH 0 POH 7 1 0 D8 D15 Multiplexed bus modes Data Path Width 8 bit 16 bit POL O POL 7 ADO AD7 ADO AD7 POH 0 POH 7 A8 A15 AD8 AD15 Table 1 Pin description 42 1701 03 9 78 DATA SHEET
65. nfigured for Basic CAN functionality Both modes provide separate masks for acceptance filtering which allows to accept a number of identifi ers in Full CAN mode and also allows to disregard a number of identifi ers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped forthe maximum message length of 8 bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud The CAN Module uses two pins to interface to a bus transceiver 36 78 42 1701 03 y DATA SHEET ST10F167 16 Watchdog Timer The Watchdog Timer is a fail safe mechanism which prevents the microcontroller from malfunctioning for long periods of time The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Therefore the chip s start up procedure is always monitored The software must be designed to service the watchdog timer before it overflows If due to hardware or software related failures the software fails to do so the watchdog timer overflows and generates an internal hardware reset It pulls the RSTOUT pin low in order to allow external hardware components to be reset The Watchdog Timer is a 16 bit timer clocked with the system clock divided either by 2 or by 128 The high byte of the watchdog timer register can be set to a pre specified reload value stored
66. ng the sample time the input capacitance C can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock tsc depend on programming and can be taken from the table 52 78 42 1701 03 y DATA SHEET ST10F167 above This parameter includes the sample time ts the time for determining the digital result and the time to load the result register with the conversion result Values for the conversion clock tcc depend on programming and can be taken from the table above This parameter depends on the ADC control logic It is not a real maximum value but rather a fixum TUE is tested at Varer 5 0V Vagnp 0V Vpp 4 9V It is guaranteed by design character ization for all other voltages within the defined voltage range The specified TUE is guaranteed only if an overload condition see IOV specification occurs on maximum 2 not selected analog input pins and the absolute sum of input overload cur rents on all analog input pins does not exceed 10 mA During the reset calibration sequence the maximum TUE may be 4 LSB During the conversion the ADC s capacitance must be repeatedly charged or discharged The internal resistance of the reference voltage source must allow the capacitance to reach its
67. nput for Count Gate Reload Capture 75 1 0 P3 8 MRST SSC Master Rec Slave Transmit I O 76 1 0 P3 9 MTSR SSC Master Transmit Slave Rec O I 77 O P3 10 TxDO ASCO Clock Data Output Asyn Syn 78 1 0 P3 11 RxDO ASCO Data Input Asyn or I O Syn 79 O P3 12 BHE Ext Memory High Byte Enable Signal O WRH Ext Memory High Byte Write Strobe 80 1 0 P3 13 SCLK SSC Master Clock Outp Slave Cl Inp 81 O P3 15 CLKOUT System Clock Output CPU Clock P4 0 85 92 1 0 Port 4 is an 8 bit bidirectional I O port It is bit wise programma P4 7 ble for input or output via direction bits For a pin configured as input the output driver is put into high impedance state In case of an external bus configuration Port 4 can be used to output the segment address lines 85 O P4 0 A16 Least Significant Segment Addr Line 90 O P4 5 A21 Segment Address Line CAN_RxD CAN Receive Data Input 91 O P4 6 A22 Segment Address Line O CAN_TxD CAN Transmit Data Output 92 O P4 7 A23 Most Significant Segment Addr Line Table 1 Pin description 8 78 42 1701 03 ST DATA SHEET ST10F167 Input l Symbol Pin Output O Function RD 95 O External Memory Read Strobe RD is activated for every exter nal instruction or data read access WR 96 O External Memory Write Strobe In WR mode this pin is activat WRL ed for every external data write access In WRL mode this pin is activated for low byte data write accesses on a 16 bit bus a
68. on of TCL TCLmax 1 fxraL DG may instead of TOL im S7 42 1701 03 55 78 DATA SHEET ST10F167 20 5 4 Phase locked loop When pin P0 15 POH 7 is high 1 during reset the on chip phase locked loop is enabled and provides the CPU clock The PLL multiplies the input frequency by 4 i e fcpy fxraL 4 With every fourth transition of fyr the PLL circuit synchronizes the CPU clock to the input clock This synchronization is done smoothly i e the CPU clock frequency does not change abruptly Due to this adaptation to the input clock the frequency of fcpy is constantly adjusted so it is locked to fyqa The slight variation causes a jitter of fcp which also effects the duration of individual TCLs The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances The actual minimum value for TCL depends on the jitter of the PLL As the PLL is constantly adjusting its output frequency so that it remains locked to the applied input frequency crystal or oscillator the relative deviation for periods of more than one TCL is lower than for one single TCL see formula and figure below For a period of N TCL the minimum value is computed using the corresponding deviation Dy min Dy 4 N 15 where N number of consecutive TCLs and 1 lt N lt 40 So fora period of 3 TCLs i e N 3 D 4 3 15 3 8 TEL ue
69. or may be altered dynamically by an external signal on a port pin TxEUD to facilitate for example position tracking Timer T3 has output toggle latches TxOTL which changes state on each timer over flow underf ow The state of this latch may be output on port pins TxOUT e g for time out monitoring of external hardware components or may be used internally to clocktimers T2 and T4 for measuring long time periods with high resolution 28 78 42 1701 03 y DATA SHEET ST10F167 In addition to their basic operating modes timers T2 and T4 may be configured as reload or capture registers for timer T3 When used as capture or reload registers timers T2 and T4 are stopped The contents of timer T3 are captured into T2 or T4 in response to a signal at their associated input pins TxIN Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal this signal can be constantly generated without software intervention 10 2 GPT2 The GPT2 module provides precise event control and time measurement lt includes two timers T5 T6 and a capture reload register CAPREL Both timers can be clocked with an input clock which is derived from the CPU clock via a programmade prescaler or with external signals
70. ot exceed 50 mA 9 Power Down Current is to be defined mA ke al o 100 50 Figure 10 Supply idle current as a function of operating frequency 42 1701 03 51 78 DATA SHEET ST10F167 20 4 A D Converter Characteristics Vbo 5 V 2590 Vss 0 V T 40 to 85 C 4 0 V lt Varer lt Vppt0 1 V Vss 0 1 V lt Vieno lt Vss 0 2 V Limit Values Parameter Symbol Unit Test Condition min max Analog input voltage range Van SR V AGND V AREF V 1 Sample time ts CC 2 tsc 2 4 Conversion time te CC 14 tcc ts 3 4 4TCL Total unadjusted error TUECC 3 LSB 5 Internal resistance of reference RagerSR tcc 165 kQ tec in ns 6 7 voltage source 0 25 Internal resistance of analog RasrpcoR ts 330 kQ ts in ns 2 7 source 0 25 ADC input capacitance Cam CC 33 pF 7 Table 18 A D converter characteristics Sample time and conversion time of the ST10F167 s ADC are programmable The table below shows the timing calculations ADCON 15 14 ADCON 13 12 Conversion clock t Sample clock tsc ADCTC ADSTC 00 TCL 24 00 loc 01 Reserved do not use 01 tcc 2 10 TCL 96 10 toc 4 11 TCL 48 11 toc 8 Table 19 ADC timing calculations Notes 1 Vam may exceed Vacuno or Varer up to the absolute maximum ratings However the con version result in these cases will be X000 or X3FF yy respectively 2 Duri
71. port It is bit wise programma ble for input or output via direction bits For a pin configured as input the output driver is put into high impedance state Port 7 outputs can be configured as push pull or open drain drivers The input threshold of Port 7 is selectable TTL or special The following Port 7 pins also serve for alternate functions P7 0 POUTO PWM Channel 0 Output P7 3 POUT3 PWM Channel 3 Output P7 4 CC28IO CAPCOM CC28 Cap In Comp Out P7 7 CC31IlO CAPCOM2 CC31 Cap In Comp Out 6 78 Table 1 Pin description 42 1701 03 LT DATA SHEET ST10F167 Input l p Symbol Pin esa O Function P5 0 27 36 Port 5 is a 16 bit input only port with Schmitt Trigger character P5 15 39 44 istics The pins of Port 5 also serve as the up to 16 analog in put channels for the A D converter where P5 x eguals ANx Analog input channel x or they serve as timer inputs 39 P5 10 T6EUD GPT2 Timer T6 Ext Up Down Ctrl Input 40 P5 11 T5EUD GPT2 Timer T5 Ext Up Down Ctrl Input 41 P5 12 T6IN GPT2 Timer T6 Count Input 42 P5 13 T5IN GPT2 Timer T5 Count Input 43 P5 14 T4EUD GPT1 Timer T4 Ext Up Down Ctrl Input 44 P5 15 T2EUD GPT1 Timer T2 Ext Up Down Ctrl Input P2 0 47 54 1 0 Port 2 is a 16 bit bidirectional I O port It is bit wise programma P2 15 57 64 ble for input or output via direction bits For a pin configured as input the output driver is put into high impedance state Port 2 outputs c
72. rap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM No part of the standard mask ROM or Flash memory area is required The identification byte is returned in C5 19 Special Function Registers The following table lists all ST10F167 SFRs in alphabetical order Bit addressable SFRs are marked with the letter b in column Name SFRs within the Extended SFR Space ESFRs are marked with the letter E in column Physical Address An SFR can be specified via its individual mnemonic name Depending on the selected addressing mode an SFR can be accessed via its physical address using the Data Page Pointers or via its short 8 bit address without using the Data Page Pointers 40 78 42 1701 03 y DATA SHEET ST10F167 Name Physical 8 Bit Description Reset Address Address Value ADCIC b FF98h CCh A D Converter End of Conversion Interrupt Cont Reg 0000h ADCON b FFAOh DOh A D Converter Control Register 0000h ADDAT FEAOh 50h A D Converter Result Register 0000h ADDAT2 FOAOhE 50h A D Converter 2 Result Register 0000h ADDRSEL1 FE18h och Address Select Register 1 0000h ADDRSEL2 FE1Ah ODh Address Select Register 2 0000h ADDRSEL3 FE1Ch OEh Address Select Register 3 0000h ADDRSEL4 FE1Eh OFh Address Select Register 4 0000h ADEIC b FF9Ah CDh A D Conv
73. respective voltage level within tcc The maximum internal resistance results from the pro grammed conversion timing Not 100 tested guaranteed by design characterization 42 1701 03 53 78 DATA SHEET ST10F167 20 5 AC Characteristics 20 5 1 Test waveforms 2 4V 0 2Vpp 0 9 0 2Vpp 0 9 Test Points 0 45V 0 2Vpp 0 1 0 2Vpp 0 AC inputs during testing are driven at 2 4 V for a logic 1 and 0 4 V for a logic O Timing measurements are made at VIH min for a logic 1 and VIL max for a logic 0 Figure 11 Input output waveforms VOH VOH 0 1V VLoad 0 1V Timing MORO Ms Reference VLoad 0 1V Points VOL 0 1V VOL For timing purposes a port pin is no longer floating when a 100 mV change from load voltageoccurs butbeginsto floatwhena 100mV changefromtheloadedV cw VoLleveloccurs low lo 20 mA Figure 12 Float waveforms 20 5 2 Definition of internal timing The internal operation of the ST10F167 is controlled by the internal CPU clock fcpy Both edges of the CPU clock can trigger internal e g pipeline or external e g bus cycles operations The specification of the external timing AC Characteristics therefore depends on the time between two consecutive edges of the CPU clock called TCL see Table 22 54 78 42 1701 03 y DATA SHEET ST10F167 The CPU clock signal can be generated via differentmechanisms The duration of TCLs and their var
74. ries and external peripherals In addition different address ranges may be accessed with different bus characteristics Up to 5 external CS signals 4 windows plus default can be generated in order to save external glue logic Access to very slow memories is supported via a particular Ready function A HOLD HLDA protocol is available for bus arbitration For applications which reguire less than 16 MBytes of external memory space this address space can be restricted to 1 MByte 256 KByte or to 64 KByte In this case Port 4 outputs four two or no address lines If an address space of 16 MBytes is used it outputs all 8 address lines 20 78 42 1701 03 y DATA SHEET ST10F167 7 Central Processing Unit CPU Internal U N U Bi Mask Gen RAM Pt E Instr Reg NZ General 2KByte 4 Stage Purpose Pipeline B Registers WAI Data Pg Ptrd Code Seg Ptr Figure 6 CPU block diagram The CPU includes a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU Dedicated SFRs have been added for a separate multiply and divide unit a bit mask generator and a barrel shifter Most of the ST10F167 s instructions can be executed in one instruction cycle which reguires 100ns at20MHz CPU clock For example shift and rotate instructions are always processed in one machine cycle independent of the number of bits to be shifted All multiple cycle instructions have
75. s or error conditions that arise during run time Hardware Traps Hardware traps cause an immediate non maskalle system reaction which is similar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardwaretrap is additionally signified by an individual bit in the trap flag register TFR Except when another higher prioritized trap service is in progress a hardware trap will interrupt any actual program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts The table below shows all of the possible exceptions or error conditions that can arise during run time Exception Condition Un ae eee Mee Pub Reset Functions Hardware Reset RESET 00 0000h 00h lll Software Reset RESET 00 0000h 00h lll Watchdog Timer Overflow RESET 00 0000h 00h Hl Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 0008h 02h ll Stack Overflow STKOF STOTRAP 00 0010h 04h ll Stack Underfl ow STKUF STUTRAP 00 0018h 06h ll Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 00 0028h OAh Protected Instruction Fault PRTFLT BTRAP 00 0028h OAh Illegal Word Operand Access ILLOPA BTRAP 00 0028h OAh lllegal Instruction Access ILLINA BTRAP 00 0028h OAh Illegal External Bus Access ILLBUS BTRAP 00 0028h OAh Reserved 2Ch 3Ch 0Bh OFh Software Traps Any Any Current TRAP instruction p ar Es in steps of 4h IT 42 1
76. ses only in order to assure recognition at a specific clock edge Demultiplexed bus is the worst case For multiplexed bus 2TCL are to be added to the max imum values This adds even more time for deactivating READY The 2t4 and 2t refer to the next bus cycle tf refers to the current bus cycle 42 1701 03 71 78 DATA SHEET ST10F167 READY l E La Running cycle mL waitstate ponas i o CLKOUT A mu i E Figure 24 CLKOUT and READY Notes 1 Cycle as programmed including MCTC waitstates Example shows 0 MCTC WS 2 The leading edge of the respective command depends on RW delay 3 READY sampled HIGH at this sampling point generates a READY controlled waitstate READY sampled LOW at this sampling point terminates the currently running bus cycle 4 READY may be deactivated in response to the trailing rising edge of the corresponding command RD or WR 5 If the Asynchronous READY signal does not fulfil the indicated setup and hold times with respect to CLKOUT e g because CLKOUT is not enabled it must fulfil t37 in order to be safely synchronized This is guaranteed if READY is removed in response to the command see Note 6 Multiplexed bus modes have a MUX waitstate added after a bus cycle and an additional MTTC waitstate may be inserted here For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles for a demulti plexed bus without MTTC waitstate this delay is zero 7
77. set 4 CALLA CALLI CALLR Call absolute indirect relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack amp call absolute subroutine 4 TRAP Call interrupt service routine via immediate trap number 2 PUSH POP Push pop direct word register onto from system stack 2 SCXT Push direct word register onto system stack and update register with 4 word operand RET Return from intra segment subroutine 2 RETS Return from inter segment subroutine RETP Return from intra segment subroutine and pop direct word register 2 from system stack RETI Return from interrupt service subroutine 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Enter Power Down Mode assumes NMI pin low 4 SRVWDT Service Watchdog Timer 4 DISWDT Disable Watchdog Timer 4 EINIT Signify End of Initialization on RSTOUT pin 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP R Begin EXTended Page and Register sequence 2 4 EXTS R Begin EXTended Segment and Register sequence 2 4 NOP Null operation 2 Table 15 Instruction set summary S7 42 1701 03 39 78 DATA SHEET ST10F167 18 Bootstrap Loader The built in bootstrap loader of the ST10F167 provides a mechanism to load the startup program through the serial interface after reset The ST10F167 enters BSL mode when pin POL 4 is sampled low at the end of a hardware reset In this case the built in bootst
78. ta In tig SR 15 t 2TCL 35 ns with RW delay tc RdCS to Valid Data In t SR 50 tc 3TCL 25 ns no RW delay to RdCS WrCS Low Time Le CC 40 tc 2TCL 10 ns with RW delay dc RdCS WrCS Low Time tig CC 65 tc 3TCL 10 ns no RW delay ic Data valid to WrCS bo CC 35 tc 2TCL 15 to ns Data hold after RdCS ts SR 0 0 ns Data float after RACS ts SR 30 tr 2TCL 20 ns with RW delay te Data float after RdCS tes SR 5 TCL 20 ns no RW delay tr Address hold after tss CC 10 t 10 ns RdCS WrCS t Data hold after WrCS tz CC 10 t TCL 15 tr ns Table 23 Demultiplexed bus characteristics 66 78 42 1701 03 DATA SHEET ST10F167 A23 A16 a A15 A0 f to Address BHE i t a i t i Ma i hM lss A rt log 39 Read Cycle tty oe BUS D15 D8 hata ln gt D7 DO WW Write FE ae ES D15 D8 gt Lata out X D7 DO i H 1 lo WR peciam mt i 1 tat Lo leo gt WrCSx N Lg Figure 20 External memory cycle demultiplexed bus with read write delay normal ALE iy 42 1701 03 67 78 DATA SHEET ST10F167 i i i t e at Lo P mls m i i i i i j ALE A23 A16 i a A15 A0 E Address BHE a e etss 9 a i35 Read Cycle E e alis gt u

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