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1. SSCTIC SSC Transmit Intr Ctrl Reg SFR FF72 4 B9 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 37O 990 ILVL GLVL rw rw rw rw SSCRIC SSC Receive Intr Ctrl Reg SFR FF74 BAy Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T ES ILVL GLVL rw rw rw rw SSCEIC SSC Error Intr Ctrl Reg SFR FF76 BB Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ee ILVL GLVL rw rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 12 17 V2 0 2000 07 o nfineon ed technologies Derivatives The Watchdog Timer WDT 13 The Watchdog Timer WDT To allow recovery from software or hardware failure the C167CS provides a Watchdog Timer If the software fails to service this timer before an overflow occurs an internal reset sequence will be initiated This internal reset will also pull the RSTOUT pin low which also resets the peripheral hardware which might be the cause for the malfunction When the watchdog timer is enabled and the software has been designed to service it regularly before it overflows the watchdog timer will supervise the program execution as it only will overflow if the program does not progress properly The watchdog timer will also time out if a
2. RPOH Reset Value of POH SFR F108 844 Reset Value XXy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SALSEL CSSEL WRC rh rh rh rh Bit Function WRC Write Configuration 0 Pins WR and BHE operate as WRL and WRH signals 1 Pins WR and BHE operate as WR and BHE signals CSSEL Chip Select Line Selection Number of active CS outputs 00 3CSlines CS2 CS0 01 2 CS lines CS1 CSO 10 No CS lines at all 11 5CS lines CS4 CS0 Default without pulldowns SALSEL Segment Address Line Selection nr of active segment addr outputs 00 4 bit segment address A19 A16 01 No segment address lines at all 10 8 bit segment address A23 A16 11 2 bit segment address A17 A16 Default without pulldowns CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode i e the mechanism how the internal CPU clock is generated from the externally applied XTAL input clock Note RPOH is initialized during the reset configuration and permits to check the current configuration This configuration except for bit WRC can be changed via register RSTCON see Section 20 5 User s Manual 9 28 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Precautions and Hints The ext bus interface is enabled as long as at least one of the BUSCON registers has its BUSACT bit set PORT will output t
3. as Control Register SFR FF40 A0 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f ef Al d6 T2R T2M T2l rw rw rw rw rw T4CON Timer 4 Control Register SFR FF44 A24 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f f f f Euel Ub tar TAM TAI rw rw rw rw rw Users Manual 10 12 V2 0 2000 07 o nfineon ed technologies Derivatives The General Purpose Timer Units Bit Function Txl Timer x Input Selection Depends on the Operating Mode see respective sections TxM Timer x Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reload Mode 101 Capture Mode 110 Incremental Interface Mode 111 Heserved Do not use this combination TxR Timer x Run Bit 0 Timer Counter x stops 1 Timer Counter x runs TxUD Timer x Up Down Control TxUDE Timer x External Up Down Enable For the effects of bits TXUD and TxUDE refer to Table 10 1 see T3 section Count Direction Control for Auxiliary Timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3 The description and the table apply accordingly Timers T2 and T4 in Timer Mode or Gated Timer Mode When the auxiliary timers T2 and T4 are programmed to timer mode or gated timer mode their operation i
4. STKOV Stack Overflow Reg SFR FE14 0A Reset Value FA00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 stkov 0 r r r r rw r Bit Function stkov Modifiable portion of register STKOV Specifies the lower limit of the internal system stack The Stack Overflow Trap entered when SP lt STKOV may be used in two different ways Fatal error indication treats the stack overflow as a system error through the associated trap service routine Under these circumstances data in the bottom of the stack may have been overwritten by the status information stacked upon servicing the stack overflow trap Automatic system stack flushing allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKOV should be initialized to a value which represents the desired lowest Top of Stack address plus 12 according to the selected maximum stack size This considers the worst case that will occur when a stack overflow condition is detected just during entry into an interrupt service routine Then six additional stack word locations are required to push IP PSW and CSP for both the interrupt service routine and the hardware trap service routine More details about the stack overflow trap service routine and virtual stack management are given in Chapter 22 User s Manual 4 28 V2 0 2000 07 o nfineon ed technologies Derivatives
5. rw rw rw rw rw rw rw rw Bit Function EXIxES External Interrupt x Edge Selection Field x 7 0 00 Fast external interrupts disabled standard mode 01 Interrupt on positive edge rising 10 Interrupt on negative edge falling 11 Interrupt on any edge rising or falling Note The fast external interrupt inouts are sampled every 2 TCL The interrupt request arbitration and processing however is executed every 8 TCL These fast external interrupts use the interrupt nodes and vectors of the CAPCOM channels CC8 CC15 so the capture compare function cannot be used on the respective Port 2 pins with EXIxES 00g However general purpose IO is possible in all cases User s Manual 5 28 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions External Interrupt Source Control The input source for fast external interrupts controlled via register EXICON can be derived either from the associated port pin EXnIN or from an alternate source This selection is controlled via register EXISEL Activating the alternate input source e g permits the detection of transitions on the interface lines of disabled interfaces Upon this trigger the respective interface can be reactivated and respond to the detected activity EXISEL Ext Interrupt Source Reg ESFR F1DA EDy Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EX
6. Reload Reg TxREL Input Control foru GPT2 Timer T6 Interrupt Over Underflow ORP COM Timer Request Txi TxM x 0 7 MCB02013 Figure 16 3 Block Diagram of CAPCOM Timers TO and T7 Reload Reg TXREL cpu Interrupt GPT2 Timer T6 HERuest Over Underflow x 1 8 TxM MCB02014 Figure 16 4 Block Diagram of CAPCOM Timers T1 and T8 Note When an external input signal is connected to the input lines of both TO and T7 these timers count the input signal synchronously Thus the two timers can be regarded as one timer whose contents can be compared with 32 capture registers User s Manual 16 4 V2 0 2000 07 o nfineon e technologies Derivatives The Capture Compare Units The functions of the CAPCOM timers are controlled via the bitaddressable 16 bit control registers TO1CON and T78CON The high byte of TO1CON controls T1 the low byte of TO1CON controls TO the high byte of T78CON controls T8 the low byte of T78CON controls T7 The control options are identical for all four timers except for external input TO1CON CAPCOM Timer 0 1 Ctrl Reg SFR FF50 A8 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITIR T1M T1I TOR TOM TOI rw rw rw rw rw rw T78CON CAPCOM Timer 7 8 Ctrl Reg SFR FF20 90 Reset Value 00004 15 14 13 12 11 10 9 8 7
7. PECCx PEC Control Reg SFR FECyy 62 see Table 5 4 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INC BWT COUNT rw rw rw Bit Function COUNT PEC Transfer Count Counts PEC transfers and influences the channel s action see Table 5 5 BWT Byte Word Transfer Selection 0 Transfer a Word 1 Transfer a Byte INC Increment Control Modification of SRCPx or DSTPx 00 Pointers are not modified 01 Increment DSTPx by 1 or 2 BWT 10 Increment SRCPx by 1 or 2 BWT 11 Reserved Do not use this combination changed to 10 by hardware Table 5 4 PEC Control Register Addresses Register Address Reg Space Register Address Reg Space PECCO FECO 60 SFR PECC4 FEC84 64 SFR PECC1 FEC2 61 SFR PECC5 FECA 65 SFR PECC2 FEC4 62 SFR PECC6 FECC 66 SFR PECC3 FEC6 63 SFR PECC7 FECE 67 SFR User s Manual 5 12 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions Byte Word Transfer bit BWT controls if a byte or a word is moved during a PEC service cycle This selection controls the transferred data size and the increment step for the modified pointer Increment Control field INC controls if one of the PEC pointers is incremented after the PEC transfer It is not possible to increment both pointers however If the pointers are not modified INC 00 the respective channel will always move data fro
8. Bit Function ODP7 y Port 7 Open Drain control register bit y ODP7 y 0 Port line P7 y output driver in push pull mode ODPT y 1 Port line P7 y output driver in open drain mode Alternate Functions of Port 7 The upper four lines of Port 7 P7 7 4 serve as capture inputs or compare outputs CC311O CC281O for the CAPCOM2 unit The usage of the port lines by the CAPCOM unit its accessibility via software and the precautions are the same as described for the Port 2 lines As all other capture inputs the capture input function of pins P7 7 4 can also be used as external interrupt inputs sample rate 16 TCL The lower 4 lines of Port 7 P7 3 0 serve as outputs from the PWM module POUTS POUTO At these pins the value of the respective port output latch is XORed with the value of the PWM output rather than ANDed as the other pins do This allows to use the alternate output value either as it is port latch holds a 0 or invert its level at the pin port latch holds a 1 Note that the PWM outputs must be enabled via the respective PENx bits in PWMCON1 Table 7 9 summarizes the alternate functions of Port 7 Table 7 9 Alternate Functions of Port 7 Port 7 Pin Alternate Function P7 0 POUTO PWM model channel 0 output P7 1 POUT 1 PWM model channel 1 output P7 2 POUT2 PWM model channel 2 output P7 3 POUT3 PWM model channel 3 output P7 4 CC28lO Capture input compare output c
9. Table 10 12 GPT2 Timer Input Frequencies Resolution and Periods 2 33 MHz fcpu 33 MHz Timer Input Selection T5I T6l 0008 001g 010g 011g 100 101 110g 111g Prescaler 4 8 16 32 64 128 256 512 Factor Input 2 06 4 125 2 0625 1 031 515 62 257 81 128 91 64 45 Frequency MHz MHz MHz MHz_ kHz kHz kHz kHz Resolution 121 ns 242 ns 485 ns 970 ns 1 94 us 3 88 us 7 76 us 15 5 us Period 7 9 ms 15 9 ms 31 8 ms 63 6 ms 127 ms 254 ms 508 ms 1 02 s User s Manual 10 27 V2 0 2000 07 o nfineon ed technologies Derivatives The General Purpose Timer Units Timer 6 in Gated Timer Mode Gated timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to 010g or 011g Bit T6M 0 T6CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T6IN Timer T6 External Input Interrupt Request TxEUD TxUDE MCB02029 T6IN P5 12 T6EUD P5 10 x 6 T6OUT P3 1 n 2 9 Figure 10 18 Block Diagram of Core Timer T6 in Gated Timer Mode If T6M 0 0 the timer is enabled when T6IN shows a low level A high level at this pin stops the timer If TeM O 1 pin T6IN must have a high level in order to enable the timer In addition the
10. The On Chip CAN Interface no TXRQ 1 CPUUPD 0 yes NEWDAT 0 Load message into buffer no Transmission successful Q lt D o yes yes Bus free no TXRQ 0 RMTPND 0 no o INTPND 1 0 Reset 1 Set no Received remote frame with same identifier as this message object yes TXRQ 1 RMTPND 1 yes INTPND 1 no no MCA04395 Figure 19 6 CAN Controller Handling of Transmit Objects DIR 1 User s Manual 19 25 V2 0 2000 07 technologies C167CS Derivatives The On Chip CAN Interface es y Bus idle Do no TXRQ 1 CPUUPD 0 Received frame with same identifier as this message object yes yes NEWDAT 0 Load identifier and control into buffer yes no MSGLST 1 no Transmission successful yes Store message NEWDAT 1 TXRQ 0 TXRQ 0 RMTPND 0 RMTPND 0 NND yes INTPND 1 INTPND 1 no 0 Reset 1 Set MCA04396 Figure 19 7 CAN Controller Handling of Receive Objects DIR 0 User s Manual 19 26 V2 0 2000 07 technologies C167CS Derivatives The On Chip CAN Interface Power Up Initialization Update Start all bits undefined TXIE RXIE application cpecific application cpecific INTPND 0 RMTPND 0 T
11. 20 000 cee eee eee 15 2 15 2 Loading the Startup Code 20 0 e eee es 15 5 15 3 Exiting Bootstrap Loader Mode 00 cee eee eee 19 5 15 4 Choosing the Baudrate for the BSL 0000 0 eee eee 15 6 16 The Capture Compare Units Luuuululslsusus 16 1 16 1 The CAPCOM Timers cp stor x goa on Ro wows Ou a Ra m RC n 16 4 16 2 CAPCOM Unit Timer Interrupts lllssllsnnne 16 9 16 3 Capture Compare Registers 0 00 eee eee eee 16 10 16 4 Capture Mode 12222 hac ya RCRORUE CEDAR a DU EE DU ane Eod ani ates 16 13 16 5 Compare Modes eeeeleeeee eee 16 14 16 6 Capture Compare Interrupts llli 16 22 17 The Pulse Width Modulation Module 17 1 17 1 Operating Modes os ee ee ost ee ees re ee ees eee a ree 17 2 17 2 PWM Module Registers 00000 c cece eee 17 10 17 3 Interrupt Request Generation 00 0c cee eee 17 14 17 4 PWM Output SIgheals ss ert cp ended a uius Ape RE aoe ae Rod ees 17 15 18 The Analog Digital Converter 0 0000 ee 18 1 18 1 Mode Selection and Operation 2 0 0c eee eee eee 18 3 18 2 Conversion Timing Control 00 cece eee 18 13 18 3 A D Converter Interrupt Control lille 18 15 19 The On Chip CAN Interface 002 e eee eee 19 1 19 1 Functional Blocks of the CAN Module 00 000e 19 3 User s Manual l 3 V2 0 2
12. o MCT04465 Figure 15 1 Bootstrap Loader Sequence The Bootstrap Loader may be used to load the complete application software into ROMless systems it may load temporary software into complete systems for testing or calibration it may also be used to load a programming routine for Flash devices The BSL mechanism may be used for standard system startup as well as only for special occasions like system maintenance firmware update or end of line programming or testing User s Manual 15 1 V2 0 2000 07 o nfineon ed technologies Derivatives The Bootstrap Loader 15 1 Entering the Bootstrap Loader The C167CS enters BSL mode triggered by external configuration during a hardware reset when pin POL 4 is sampled low at the end of an external reset EA 0 when pin RD is sampled low at the end of an internal reset EA 1 In this case the built in bootstrap loader is activated independent of the selected bus mode The bootstrap loader code is stored in a special Boot ROM no part of the standard mask ROM OTP or Flash memory area is required for this The hardware that activates the BSL during reset may be a simple pull down resistor on POL 4 or RD for systems that use this feature upon every hardware reset You may want to use a switchable solution via jumper or an external signal for systems that only temporarily use the bootstrap loader RD Ext 2 o Signal e
13. 0 0000 10 2 3 Interrupt Control for GPT2 Timers and CAPREL 11 The Asynchronous Synchronous Serial Interface 11 1 Asynchronous Operation lsllllslsllsss 11 2 Synchronous Operation lsllllsslllesn User s Manual l 2 V2 0 2000 07 o nfineon ed technologies Derivatives Table of Contents Page 11 3 Hardware Error Detection Capabilities sess 11 10 11 4 ASCO Baud Rate Generation 00 0 cee ee eee 11 11 11 5 ASCO Interrupt Control 225 aes iss oe scueved aa RACER A OR re Res 11 15 12 The High Speed Synchronous Serial Interface 12 1 12 1 Full Duplex Operation 0 00 cee eee ee eee 12 7 12 2 Half Duplex Operation uses ested sie gb caia he ee oaa dab e 12 10 12 3 Continuous Transfers wasn ok saaana ties a dados PERE eee 1d 12 11 12 4 POMGOUNO asutetosteures Kad e ceu raa dus er eam edis ele we 12 12 12 5 Baud Rate GenbrallDhi s wes odes tae ca c ace ario AD EK A E x dd 12 13 12 6 Error Detection Mechanisms 0000 cece eee eeee 12 15 12 7 SSC Interrupt Control aue docete J xr tr id SER Ear qa c be ed 12 17 13 The Watchdog Timer WDT sess 13 1 13 1 Operation of the Watchdog Timer 0000 e eee eee 13 3 13 2 Reset Source Indication 225 rs homer Ra RE wa 13 6 14 The Real Time Clock 0 000 cee eee 14 1 15 The Bootstrap Loader 0 0 ee 15 1 15 1 Entering the Bootstrap Loader
14. CSR Control Status Register XReg EF00 Reset Value XX01 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0 OEN FO ok LEC TM CCE CPS EIE SIE IE INIT rh rh r rwh rwh rwh wo rw rw rw rw rw wh Bit Function Control Bits INIT Initialization Starts the initialization of the CAN controller when set INIT is set after a reset when entering the busoff state by the application software IE Interrupt Enable Enables or disables interrupt generation from the CAN module via the signal XINTR Does not affect status updates SIE Status Change Interrupt Enable Enables or disables interrupt generation when a message transfer reception or transmission is successfully completed or a CAN bus error is detected and registered in the status partition EIE Error Interrupt Enable Enables or disables interrupt generation on a change of bit BOFF or EWARN in the status partition CPS Clock Prescaler Control Bit 0 Standard mode the input clock is divided 2 1 The minimum input frequency to achieve a baudrate of 1 MBaud is fcpy 16 MHz 1 Fast mode the input clock is used directly 1 1 The minimum input frequency to achieve a baudrate of 1 MBaud is fcpy 8 MHz CCE Configuration Change Enable Allows or inhibits CPU access to the Bit Timing Register TM Test Mode must be 0 Make sure that this bit is always cleared when writing to the Control Register as this bit controls a special test mode that is used for production testing Du
15. MCT04374 Figure 10 9 Evaluation of the Incremental Encoder Signals Note Timer T3 operating in incremental interface mode automatically provides information on the sensors current position Dynamic information speed acceleration deceleration may be obtained by measuring the incoming signal periods This is facilitated by an additional special capture mode for timer T5 User s Manual 10 11 V2 0 2000 07 d nfineon e technologies Derivatives The General Purpose Timer Units 10 1 2 GPT 1 Auxiliary Timers T2 and TA Both auxiliary timers T2 and T4 have exactly the same functionality They can be configured for timer gated timer counter or incremental interface mode with the same options for the timer frequencies and the count signal as the core timer T3 In addition to these 4 counting modes the auxiliary timers can be concatenated with the core timer or they may be used as reload or capture registers in conjunction with the core timer The individual configuration for timers T2 and T4 is determined by their bitaddressable control registers T2CON and T4CON which are both organized identically Note that functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers Note The auxiliary timers have no output toggle latch and no alternate output function
16. Direction Open Drain Latch Latch Port Output Latch AltDir AItEN AltDataOut Driver AltDataln Latch i Clock AltDatalN Pin lt lt D Input Latch P8 3 0 MCB04430 Figure 7 30 Block Diagram of Port 8 Pins with Alternate CAPCOM IO and CAN Interface Function User s Manual 7 57 V2 0 2000 07 d nfineon e technologies Derivatives Dedicated Pins 8 Dedicated Pins Most of the input output or control signals of the functional the C167CS are realized as alternate functions of pins of the parallel ports There is however a number of signals that use separate pins including the oscillator special control signals and of course the power supply Table 8 1 summarizes the 33 dedicated pins of the C167CS Table 8 1 C167CS Dedicated Pins Pin s Function ALE Address Latch Enable RD External Read Strobe WR WRL External Write Write Low Strobe READY Ready Input EA External Access Enable NMI Non Maskable Interrupt Input XTAL1 XTAL2 Oscillator Input Output RSTIN Reset Input RSTOUT Reset Output VAREF VAGND Power Supply for Analog Digital Converter VDD Digital Power Supply 10 pins VSS Digital Reference Ground 10 pins NC Not connected pin Should not be connected to the PCB The Address Latch Enable signal ALE controls external address latches that provide a stable address i
17. 47 71p ASCO Receive SORIR SORIE SORINT 00 00AC 2By 43p ASCO Error SOEIR SOEIE SOEINT 00 00BO04 2C 445 SSC Transmit SCTIR SCTIE SCTINT 00 00B4 2D 45p SSC Receive SCRIR SCRIE SCRINT 0000B84 2Ej 46p SSC Error SCEIR SCEIE SCEINT 00 00BC 2Fy 47p PWM Channel 0 3 PWMIR PWMIE PWMINT 00 00FC 3Fy 63p CAN1 XPOIR XPOIE XPOINT 00 0100 40 64p CAN2 XP1IR XP1IE XP1INT 00 0104 41 65p Unassigned node XP2IR XP2IE XP2INT 00 0108 421 66p PLL OWD RTC XP3IR XP3IE XP3INT 00 010C 434 675 User s Manual 5 4 V2 0 2000 07 e nfineon technologies C167CS Derivatives Interrupt and Trap Functions Table 5 2 lists the vector locations for hardware traps and the corresponding status flags in register TFR It also lists the priorities of trap service for cases where more than one trap condition might be detected within the same instruction After any reset hardware reset software reset instruction SRST or reset by watchdog timer overflow program execution starts at the reset vector at location 00 0000 Reset conditions have priority over every other system activity and therefore have the highest priority trap priority IIl Software traps may be initiated to any vector location between 00 0000 and 00 01FC A service routine entered via a software TRAP instruction is always executed on the current CPU priority level which is indicated in bit field ILVL in register PSW This means tha
18. A A CCx eg e3 2g zd zd zd Direction Latch Port Output Latch Pin 1 3 1 Driver AltDataln Latch lt Clock AltDataln Pin lt e Input Latch MCB04364 P7 7 4 Figure 7 27 Block Diagram of Port 7 Pins P7 7 4 User s Manual 7 52 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 12 Port 8 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP8 Each port line can be switched into push pull or open drain mode via the open drain control register ODP8 P8 Port 8 Data Register SFR FFD4 EAy Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P8 7 P8 6 P8 5 P8 4 P8 3 P8 2 P8 1 P8 0 rwh rwh rwh rwh rwh rwh rwh rwh Bit Function P8 y Port data register P8 bit y DP8 P8 Direction Ctrl Register SFR FFD6 EBj Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP8 DP8 DP8 DP8 DP8 DP8 DP8 DP8 7 6 5 4 3 2 1 0 Bit Function DP8 y Port direction register DP8 bit y DP8 y 0 Port line P8 y is an input high impedance DP8 y 1 Port line P8 y is an output User s Manual 7 53 V2 0 2000 07 d nfineon e technologies Derivatives Paralle
19. The upper 256 Bytes of the SFR area the ESFR area and the internal RAM are bit addressable see Chapter 3 i e those register bits located within the respective sections can be directly manipulated using bit instructions The other SFRs must be accessed byte word wise Note All GPRs are bit addressable independent of the allocation of the register bank via the context pointer CP Even GPRs which are allocated to not bit addressable RAM locations provide this feature The read modify write approach may be critical with hardware effected bits In these cases the hardware may change specific bits while the read modify write operation is in progress where the writeback would overwrite the new bit value generated by the hardware The solution is either the implemented hardware protection see below or realized through special programming see Chapter 4 2 Protected bits are not changed during the read modify write sequence i e when hardware sets e g an interrupt request flag between the read and the write of the read modify write sequence The hardware protection logic guarantees that only the intended bit s is are effected by the write back operation Note If a conflict occurs between a bit manipulation generated by hardware and an intended software access the software access has priority and determines the final value of the respective bit A summary of the protected bits implemented in the C167CS can be found at the end of Chap
20. User s Manual 19 32 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Module Initialization The module initialization is enabled by setting bit INIT in the control register CSR This can be done by the CPU via software or automatically by the CAN controller on a hardware reset or if the EML switches to busoff state While INIT is set all message transfer from and to the CAN bus is stopped e the CAN transmit line CAN TXD is 1 recessive the control bits NEWDAT and RMTPND of the last message object are reset e the counters of the EML are left unchanged Setting bit CCE in addition permits changing the configuration in the Bit Timing Register To initialize the CAN Controller the following actions are required configure the Bit Timing Register CCE required e set the Global Mask Registers initialize each message object If a message object is not needed it is sufficient to clear its message valid bit MSGVAL i e to define it as not valid Otherwise the whole message object has to be initialized After the initialization sequence has been completed the CPU clears bit INIT Now the BSP synchronizes itself to the data transfer on the CAN bus by waiting for the occurrence of a sequence of 11 consecutive recessive bits i e Bus Idle before it can take part in bus activities and start message transfers The initialization of the message objects is independent of the state
21. User s Manual 2 14 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview A D Converter For analog signal measurement a 10 bit A D converter with 24 multiplexed input channels and a sample and hold circuit has been integrated on chip It uses the method of successive approximation The sample time for loading the capacitors and the conversion time is programmable and can so be adjusted to the external circuitry Overrun error detection protection is provided for the conversion result register ADDAT either an interrupt request will be generated when the result of a previous conversion has not been read from the result register at the time the next conversion is complete or the next conversion is suspended in such a case until the previous result has been read For applications which require less analog input channels the remaining channel inputs can be used as digital input or IO port pins The A D converter of the C167CS supports four different conversion modes In the standard Single Channel conversion mode the analog level on a specified channel is sampled once and converted to a digital result In the Single Channel Continuous mode the analog level on a specified channel is repeatedly sampled and converted without software intervention In the Auto Scan mode the analog levels on a prespecified number of channels are sequentially sampled and converted In the Auto Scan Continuous mode the numb
22. during operation SSC enabled by SSCEN 1 it provides access to a set of status flags Register SSCCON is shown below in each of the two modes SSCCON SSC Control Reg Pr M SFR FFB2 D9 Reset Value 00004 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC SSC SSC SSC EN MS AR BEN PEN REN TEN PO PH HB SRBM rw rw rw rw rw rw rw rw rw rw rw rw User s Manual 12 2 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface Bit Function Programming Mode SSCEN 0 SSCBM SSC Data Width Selection 0 Reserved Do not use this combination 1 15 Transfer Data Width is 2 16 bit lt SSCBM gt 1 SSCHB SSC Heading Control Bit 0 Transmit Receive LSB First 1 Transmit Receive MSB First SSCPH SSC Clock Phase Control Bit 0 Shift transmit data on the leading clock edge latch on trailing edge 1 Latch receive data on leading clock edge shift on trailing edge SSCPO SSC Clock Polarity Control Bit 0 Idle clock line is low leading clock edge is low to high transition 1 Idle clock line is high leading clock edge is high to low transition SSCTEN SSC Transmit Error Enable Bit 0 Ignore transmit errors 1 Check transmit errors SSCREN SSC Receive Error Enable Bit 0 Ignore receive errors 1 Check receive errors SSCPEN SSC Phase Error Enable Bi
23. o Oo E Ec Port Output Direction Latch Latch o AltDir 2 1 1 AItEN r Pin AltDataOut XJ Driver Clock Input Latch MCB04353 P3 15 P3 12 Figure 7 16 Block Diagram of Pins P3 15 CLKOUT FOUT and P3 12 BHE WRH Note Enabling the BHE or WRH function automatically enables the P3 12 output driver Setting bit DP3 12 1 is not required During bus hold pin BHE if enabled is floating Enabling the CLKOUT function automatically enables the P3 15 output driver Setting bit DP3 15 1 is not required User s Manual 7 32 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 8 Port 4 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP4 P4 Port 4 Data Register SFR FFC8 E4 Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P4 7 P4 6 P4 5 P4 4 P4 3 P4 2 P4 1 P4 0 Bit Function P4 y Port data register P4 bit y DP4 P4 Direction Ctrl Register SFR FFCA E5y Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP4 DP4 DP4 DP4 DP4 DP4 DP4 DPA 2 06 5 4 3 2 1 0 Bit Function DP4 y Port direction register DP4 bit y DP4 y 0 Port line P4 y is an input high impedance DP4 y 1 Port line P4 y is an
24. 1 EXECUTE N 2 N 1 N PEC WRITEBACK N 3 N 2 N 1 N PEC Response Time IR Flag MCT04333 Figure 5 5 Pipeline Diagram for PEC Response Time In Figure 5 5 above the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a PEC transfer instruction is injected into the decode stage of the pipeline suspending instruction N 1 and clearing the source s interrupt request flag to O Cycle 4 completes the injected PEC transfer and resumes the execution of instruction N f All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after the PEC data transfer Note When instruction N reads any of the PEC control registers PECC7 PECCO while a PEC request wins the current round of prioritization this round is repeated and the PEC data transfer is started one cycle later The minimum PEC response time is 3 states 6 TCL This requires program execution from the internal code memory no external operand read requests and setting the interrupt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum PEC response time under these conditions is 4 state times 8 TCL The PEC response time is increased by all delays of the instructions in the pipe
25. If this technique were not used each instruction would require four machine cycles This increased performance allows a greater number of tasks and interrupts to be processed Instruction Decoder Instruction decoding is primarily generated from PLA outputs based on the selected opcode No microcode is used and each pipeline stage receives control signals staged in control registers from the decode stage PLAs Pipeline holds are primarily caused by wait states for external memory accesses and cause the holding of signals in the control registers Multiple cycle instructions are performed through instruction injection and simple internal state machines which modify required control signals User s Manual 2 3 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview High Function 8 bit and 16 bit Arithmetic and Logic Unit All standard arithmetic and logical operations are performed in a 16 bit ALU In addition for byte operations signals are provided from bits six and seven of the ALU result to correctly set the condition flags Multiple precision arithmetic is provided through a CARRY IN signal to the ALU from previously calculated portions of the desired operation Most internal execution blocks have been optimized to perform operations on either 8 bit or 16 bit quantities Once the pipeline has been filled one instruction is completed per machine cycle except for multiply and divide An advanced Boot
26. The Central Processing Unit CPU The Stack Underflow Pointer STKUN This non bit addressable register is compared against the SP register after each operation which pops data from the system stack e g POP and RET instructions and after each addition to the SP register If the content of the SP register is greater than the content of the STKUN register a stack underflow hardware trap will occur Since the least significant bit of register STKUN is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKUN register can only contain values from F000 to FFFEj STKUN Stack Underflow Reg SFR FE16 0Bj Reset Value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 stkun 0 r r r r rw r Bit Function stkun Modifiable portion of register STKUN Specifies the upper limit of the internal system stack The Stack Underflow Trap entered when SP gt STKUN may be used in two different ways Fatal error indication treats the stack underflow as a system error through the associated trap service routine Automatic system stack refilling allows to use the system stack as a Stack Cache for a bigger external user stack In this case register STKUN should be initialized to a value which represents the desired highest Bottom of Stack address More details about the stack underflow trap service routine and virtual stack management are giv
27. 5 rw r r r rw Bit Function ID28 0 Identifier 29 bit Mask to filter the last incoming message Nr 15 with standard or extended identifier as configured User s Manual 19 18 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 3 The message object is the primary means of communication between CPU and CAN controller Each of the 15 message objects uses 15 consecutive bytes see Figure 19 5 and starts at an address that is a multiple of 16 Note All message objects must be initialized by the CPU even those which are not going to be used before clearing the INIT bit The Message Object Offset 0 lt Object Start Address EFnO H 2 Message Control MCR Arbitration UAR amp LAR 4 Message Object 1 EF10 H Msg Config MCFG 6 Message Object 2 EF20 H 8 10 Message Object 14 EFEO H 12 Message Object 15 EFFO H MCA04394 Figure 19 5 Message Object Address Map The general properties of a message object are defined via the Message Control Register MCR There is a dedicated register MCRn for each message object n Each element of the Message Control Register is made of two complementary bits This special mechanism allows the selective setting or resetting of specific elements leaving others unchanged without requiring read modify write cycles None of these elements will be affected by reset Table 19 1 shows how to use and in
28. An external clock signal e g from an external oscillator or from a master device may be fed to the input XTAL1 The Pierce oscillator then is not required to support the oscillation itself but is rather driven by the input signal In this case the input frequency range may be 0 to 50 MHz please note that the maximum applicable input frequency is limited by the device s maximum CPU frequency Note Oscillator measurement within the final target system is recommended to determine the actual oscillation allowance for the oscillator crystal system The measurement technique examples for evaluated systems and recommendations are provided in a specific application note about oscillators available via your representative or WWW User s Manual 6 2 V2 0 2000 07 o nfineon ed technologies Derivatives Clock Generation For input frequencies above 25 30 MHz the oscillator s output should be terminated as shown in Figure 6 3 at lower frequencies it may be left open This termination improves the operation of the oscillator by filtering out frequencies above the intended oscillator frequency XTAL1 XTAL2 15 pF Input Clock 3 kQ MCS04336 Figure 6 3 Oscillator Output Termination Note It is strongly recommended to measure the oscillation allowance or margin in the final target system layout to determine the optimum parameters for the oscillator operation User s Manual 6 3 V2 0 2000 07 o nfineon
29. Parallel Ports trigger an interrupt request in order to perform some special service routines External capture signals can only be applied if no address output is selected for PORT1 During external accesses in demultiplexed bus modes PORT1 outputs the 16 bit intra segment address as an alternate output function During external accesses in multiplexed bus modes when no BUSCON register selects a demultiplexed bus mode PORT is not used and is available for general purpose IO When an external bus mode is enabled the direction of the port pin and the loading of data into the port output latch are controlled by the bus controller hardware The input of the port output latch is disconnected from the internal bus and is switched to the line labeled Alternate Data Output via a multiplexer The alternate data is the 16 bit intrasegment address While an external bus mode is enabled the user software should not write to the port output latch otherwise unpredictable results may occur When the external bus modes are disabled the contents of the direction register last written by the user becomes active Alternate Function a b P1H 7 A15 CC271O P1H 6 A14 CC26lO P1H 5 A13 CC2510 P1H P1H 4 A12 CC2410 P1H 3 A11 P1H 2 A10 P1H 1 A9 P1H 0 A8 Port P1L 7 A7 AN23 P1L 6 A6 AN22 PILS A5 AN21 P1L 4 A4 AN20 PIL P1L 3 A3 AN19 P1L 2 A2 AN18 P1L 1 A1 AN17 P1L 0 AO AN16 General Purpose 8 16 Bit CAPCOM2 Input Output Demux Bu
30. Procedures may be called conditionally with instructions CALLA or CALLI or be called unconditionally using instructions CALLR or CALLS Note Any data pushed onto the system stack during execution of the subroutine must be popped before the RET instruction is executed Passing Parameters on the System Stack Parameters may be passed via the system stack through PUSH instructions before the subroutine is called and POP instructions during execution of the subroutine Base plus offset indirect addressing also permits access to parameters without popping these parameters from the stack during execution of the subroutine Indirect addressing provides a mechanism of accessing data referenced by data pointers which are passed to the subroutine In addition two instructions have been implemented to allow one parameter to be passed on the system stack without additional software overhead The PCALL push and call instruction first pushes the reg operand and the IP contents onto the system stack and then passes control to the subroutine specified by the caddr operand When exiting from the subroutine the RETP return and pop instruction first pops the IP and then the reg operand from the system stack and returns to the calling program User s Manual 22 9 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming Cross Segment Subroutine Calls Calls to subroutines in different segments require the use of
31. The chip select lines of Port 6 additionally have an internal weak pullup device This device is switched on under the following conditions always during reset for all potential CS output pins e if the Port 6 line is used as a chip select output and the C167CS is in Hold mode invoked through HOLD and the respective pin driver is in push pull mode ODP6 x 0 This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection and to allow another master to access the external memory via the same chip select lines Wired AND while the C167CS is in Hold mode With ODP6 x 1 open drain output selected the internal pullup device will not be active during Hold mode external pullup devices must be used in this case When entering Hold mode the CS lines are actively driven high for one clock phase then the output level is controlled by the pullup devices if activated After reset the CS function must be used if selected so In this case there is no possibility to program any port latches before Thus the alternate function CS is selected automatically in this case Note The open drain output option can only be selected via software earliest during the initialization routine the configured chip select lines via CSSEL will be in push pull output driver mode directly after reset User s Manual 7 44 V2 0 2000 07 o Infineon technologies C167CS
32. User ROM access User ROM access User s Manual V2 0 2000 07 o nfineon e technologies Derivatives The Bootstrap Loader 15 2 Loading the Startup Code After sending the identification byte the BSL enters a loop to receive 32 Bytes via ASCO These bytes are stored sequentially into locations 00 FA40 through O0 FA5F of the internal RAM So up to 16 instructions may be placed into the RAM area To execute the loaded code the BSL then jumps to location 00 FA40 i e the first loaded instruction The bootstrap loading sequence is now terminated the C167CS remains in BSL mode however Most probably the initially loaded routine will load additional code or data as an average application is likely to require substantially more than 16 instructions This second receive loop may directly use the pre initialized interface ASCO to receive data and store it to arbitrary user defined locations This second level of loaded code may be the final application code It may also be another more sophisticated loader routine that adds a transmission protocol to enhance the integrity of the loaded code or data It may also contain a code sequence to change the system configuration and enable the bus interface to store the received data into external memory This process may go through several iterations or may directly execute the final application In all cases the C167CS will still run in BSL mode i e with the watchdog timer di
33. 00 00E8 3A 58p CAPCOM Register 27 CC27IR CC27IE CC27INT 00 00EC 3By 59p CAPCOM Register 28 CC28IR CC28IE CC28INT 00 00F0 3Cj 60p CAPCOM Register 29 CC29IR CC29IE CC29INT 00 0110 44 68p User s Manual 5 3 V2 0 2000 07 o nfineon technologies C167CS Derivatives Table 5 1 Interrupt and Trap Functions C167CS Interrupt Notes and Vectors cont d Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Register 30 CC30IR CCSOIE CC30INT 10001144 45 69p CAPCOM Register 31 CC34IR CC31IE CC31lNT 00 0118 46 70p CAPCOM Timer 0 TOIR TOIE TOINT 00 0080 20 32p CAPCOM Timer 1 T1IR T1IE T1INT 00 00844 21 33p CAPCOM Timer 7 T7IR T7IE T7INT 00 00F4 3D 61p CAPCOM Timer 8 T8IR T8IE T8INT 00 00F8 3Ej 62p GPT1 Timer 2 T2IR T2lE T2INT 00 0088y 224 345 GPT1 Timer 3 TSIR TSIE T3INT 00 008Cy 234 85p GPT1 Timer 4 T4IR T4lE T4INT 00 0090 244 365 GPT2 Timer 5 T5IR T5IE T5INT 00 0094 254 37p GPT2 Timer 6 T6IR T6IE T6INT 00 0098 26 38p GPT2 CAPREL Register CRIR CRIE CRINT 00 009C 27 39p A D Conversion Complete ADCIR ADCIE ADCINT 00 00A04 284 40p A D Overrun Error ADEIR ADEIE ADEINT 00 00A44 29j 41p ASCO Transmit SOTIR SOTIE SOTINT 00 00A84 2Ay 42p ASCO Transmit Buffer SOTBIR SOTBIE SOTBINT 00 011C
34. 01044 0 4 0 2 00AC4 O0AD 1200 Baud 0 2 0 4 0207 0208 0 1 0 2 015A 015By 600 Baud 0 1 0 0 0410 0411 0 1 0 1 02B5 02B6 75 Baud 1 7 1FFFy 0 0 0 0 15B2 4 15B3 50 Baud 1 7 1FFF User s Manual 11 12 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Asynchronous Synchronous Serial Interface Table 11 3 ASCO Asynchronous Baudrate Generation for fcpy 25 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 781 KBaud 0 2 0000 19 2 KBaud 1 796 0 8 0027 0028 0 5 3 1 001A 7001Bj 9600 Baud 0 5 0 8 0050 0051 0 5 1 4 0035 00364 4800 Baud 0 5 0 2 00A1 00A2 0 5 0 5 006B 006C 2400 Baud 0 2 0 2 0145 0146 0 0 0 5 00D8 00D9 1200 Baud 0 0 0 2 028A4 028By 0 0 0 2 01B1 01B2 600 Baud 0 0 0 1 0515 0516 0 0 0 1 0363 0364 95 Baud 0 4 1FFF 0 096 0 0 1569 156A 63 Baud 1 0 1FFFY Table 11 4 ASCO Asynchronous Baudrate Generation for fcpy 33 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 1 031 MBaud 0 0926 0000 19 2 KBaud 1 3 0 5 00344 00354 2 3 0 5 00224 0
35. 127 ms 254 ms 508 ms 1 02 s 2 03 s User s Manual 10 6 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer 3 in Gated Timer Mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 010g or 011g Bit T3M 0 T3CON 3 selects the active level of the gate input In gated timer mode the same options for the input frequency as for the timer mode are available However the input clock to the timer in this mode is gated by the external input pin T3IN Timer T3 External Input To enable this operation pin T3IN must be configured as input i e the corresponding direction control bit must contain 0 Txl gt Interrupt Request TxEUD TxUDE MCB02029 T3IN P3 6 T3EUD P3 4 x 3 T3OUT P3 3 n 3 10 Figure 10 4 Block Diagram of Core Timer T3 in Gated Timer Mode If T3M 0 0 the timer is enabled when T3IN shows a low level A high level at this pin stops the timer If T3M 0 1 pin T3IN must have a high level in order to enable the timer In addition the timer can be turned on or off by software using bit T3R The timer will only run if T3R 1 and the gate is active It will stop if either TSR 0 or the gate is inactive Note A transition of the gate signal at pin T3IN does not cause an interrupt request User s Manual 10 7 V2 0 2000 07 o nfineon e technologies Derivativ
36. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function ODP2 y Port 2 Open Drain control register bit y ODP2 y 0 Port line P2 y output driver in push pull mode ODP2 y 1 Port line P2 y output driver in open drain mode User s Manual 7 24 V2 0 2000 07 j d nfineon ed technologies Derivatives Parallel Ports Alternate Functions of Port 2 All Port2 lines P2 15 P2 0 serve as capture inputs or compare outputs CC151O CCOIO for the CAPCOM unit The upper eight Port2 lines P2 15 P2 8 also serve as external interrupt inputs EX7IN EXOIN 16 TCL sample rate When a Port 2 line is used as a capture input the state of the input latch which represents the state of the port pin is directed to the CAPCOM unit via the line Alternate Pin Data Input If an external capture trigger signal is used the direction of the respective pin must be set to input If the direction is set to output the state of the port output latch will be read since the pin represents the state of the output latch This can be used to trigger a capture event through software by setting or clearing the port latch Note that in the output configuration no external device may drive the pin otherwise conflicts would occur When a Port 2 line is used as a compare output compare modes 1 and 3 the compare
37. All bit and word instructions can access the PSW register so no instructions like CLEAR CARRY or ENABLE INTERRUPTS are required External Memory Data Access does not require special instructions to load data pointers or explicitly load and store external data The C167CS provides a Von Neumann memory architecture and its on chip hardware automatically detects accesses to internal RAM GPRs and SFRs Multiplication and Division Multiplication and division of words and double words is provided through multiple cycle instructions implementing a Booth algorithm Each instruction implicitly uses the 32 bit register MD MDL lower 16 bits MDH upper 16 bits The MDRIU flag Multiply or Divide Register In Use in register MDC is set whenever either half of this register is written to or when a multiply divide instruction is started It is cleared whenever the MDL User s Manual 22 1 V2 0 2000 07 C167CS Derivatives technologies System Programming register is read Because an interrupt can be acknowledged before the contents of register MD are saved this flag is required to alert interrupt routines which require the use of the multiply divide hardware so they can preserve register MD This register however only needs to be saved when an interrupt routine requires use of the MD register and a previous task has not saved the current result This flag is easily tested by the Jump on bit instructions Multiplication or division
38. C167CS Derivatives technologies System Reset The C167CS s Pins after Reset After the reset sequence the different groups of pins of the C167CS are activated in different ways depending on their function Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORTO so either external accesses can takes place or the external control signals are inactive The general purpose IO pins remain in input mode high impedance until reprogrammed via software see Figure 20 3 The RSTOUT pin remains active low until the end of the initialization routine see description Internal Reset Condition 9 Initialization RSTIN Internal Reset Condition Initialization When the internal reset condition is extended by RSTIN the activation of the output signals is delayed until the end of the internal reset condition 1 Current bus cycle is completed or aborted Switches asinchronously with RSTIN sinchronously upon software or watchdog reset 3 The reset condition ends here The C 167CR starts program execution 4 Activation of the IO pins is controlled by software Execution of the EINIT instruction 7 8 The shaded area designates the internal reset sequence which starts after synchronization of RSTIN A short hardware reset is extended until the end of th
39. FORTH applications Network driver software CAN PROFIBUS User s Manual 1 6 V2 0 2000 07 o nfineon end technologies Derivatives Introduction 1 3 Abbreviations The following acronyms and terms are used within this document ADC Analog Digital Converter ALE Address Latch Enable ALU Arithmetic and Logic Unit ASC Asynchronous synchronous Serial Controller CAN Controller Area Network License Bosch CAPCOM CAPture and COMpare unit CISC Complex Instruction Set Computing CMOS Complementary Metal Oxide Silicon CPU Central Processing Unit EBC External Bus Controller ESFR Extended Special Function Register Flash Non volatile memory that may be electrically erased GPR General Purpose Register GPT General Purpose Timer unit HLL High Level Language lO Input Output OTP One Time Programmable memory PEC Peripheral Event Controller PLA Programmable Logic Array PLL Phase Locked Loop PWM Pulse Width Modulation RAM Random Access Memory RISC Reduced Instruction Set Computing ROM Read Only Memory RTC Real Time Clock SDD Slow Down Divider SFR Special Function Register SSC Synchronous Serial Controller XBUS Internal representation of the External Bus XRAM On chip extension RAM User s Manual 1 7 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview 2 Architectural Overview The architecture of the C167CS combines the advantages of both RISC and CISC processors in a very
40. If a previously received byte has not been read out of the receive buffer register at the time the reception of the next byte is complete both the error interrupt request flag SOEIR and the overrun error status flag SOOE will be set provided the overrun check has been enabled by bit SOOEN User s Manual 11 9 V2 0 2000 07 d nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface 11 3 Hardware Error Detection Capabilities To improve the safety of serial data exchange the serial channel ASCO provides an error interrupt request flag which indicates the presence of an error and three selectable error status flags in register SOCON which indicate which error has been detected during reception Upon completion of a reception the error interrupt request flag SOEIR will be set simultaneously with the receive interrupt request flag SORIR if one or more of the following conditions are met f the framing error detection enable bit SOFEN is set and any of the expected stop bits is not high the framing error flag SOFE is set indicating that the error interrupt request is due to a framing error Asynchronous mode only e f the parity error detection enable bit SOPEN is set in the modes where a parity bit is received and the parity check on the received data bits proves false the parity error flag SOPE is set indicating that the error interrupt request is due to a parity error Asynchronous mode
41. MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to one locked register BFLDH SYSCON2 03H 00H CLKCON 00B basic frequency KIK Users Manual 21 23 V2 0 2000 07 technologies C167CS Derivatives Examples where the PLL is Disabled ENTER SLOWDOWN EXIR BCLR MOV EXTR BF LDL MOV BSET BF LDH 1H ISNC 2 SYSCON2 4H SYSCON2 0FH 09H SYSCON2 0003H SYSCON2 2 ZEROS SYSCON2 03H 02H SDD_EXIT_AUTO MOV EXTR BF LDL MOV BSET BF LDH EXTR BSET SYSCON2 4H SYSCON2 0FH 09H SYSCON2 0003H SYSCON2 2 ZEROS SYSCON2 03H 00H 1H ISNC 2 User s Manual Power Management Currently running on basic clock frequ Next access to ESFR space PLLIE 0 i e Clear bits 3 0 Switch PLL interrupt disabled no EXTR required here to ESFR space and lock sequence Unlock sequence step 1 1001B Unlock sequence step 2 0011B Unlock sequence step 3 0111B Single access to CLKCON 10B SDD Currently running on SDD Clear bits 3 0 one locked register frequency PLL ofL frequency no EXTR required here Switch to ESFR space and lock sequence Unlock sequence step 1 1001B Unlock sequence step 2 0011B Unlock sequence step 3 0111B Single access to CLKCON 00B basic one locked register frequ
42. Regaining the Bus Note The falling BREQ edge shows the last chance for BREQ to trigger the indicated regain sequence Even if BREQ is activated earlier the regain sequence is initiated by HOLD going high BREQ and HOLD are connected via an external arbitration circuitry Please note that HOLD may also be deactivated without the C167CS requesting the bus User s Manual 9 34 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Connecting Bus Masters When multiple bus masters C167CSs or other masters shall share external resources a bus arbiter is required that determines the currently active bus master and also enables a C167CS which has surrendered its bus interface to regain control of it in case it must access the shared external resources The structure of this bus arbiter defines the degree of control the C167CS has over the external bus system Whenever the C167CS has released the bus there is no way of actively regaining control of it besides the activation of the BREQ signal In any case the C167CS must wait for the deactivation of its HOLD input Note The full arbitration logic is required if the other bus master does not automatically remove its hold request after having used the shared resources External Bus System C167CR or C167CR or C 67CR or other Master other Master other Master Bus Arbiter Logic Figure 9 14 Principle Arbitration Log
43. The CPU clock is distributed via separate clock drivers which feed the CPU itself and two groups of peripheral modules The RTC is fed with the prescaled oscillator clock fnrc via a separate clock driver so it is not affected by the clock control functions CD Idle Mode CPU CD PCDDIS Prescaler Peripherals p t Ports Intrl Ctrl SDD orts Intrl Ctrl ICD gt Interfaces P D Mode 32 1 IP RTC farc Oscillator Frequency Control Clock Drivers Figure 6 1 CPU Clock Generation Stages C P MCD04457 User s Manual 6 1 V2 0 2000 07 j e nfineon ed technologies Derivatives Clock Generation 6 1 Oscillator The main oscillator of the C167CS is a power optimized Pierce oscillator providing an inverter and a feedback element Pins XTAL1 and XTAL2 connect the inverter to the external crystal The standard external oscillator circuitry see Figure 6 2 comprises the crystal two low end capacitors and series resistor Rx2 to limit the current through the crystal The additional LC combination is only required for 3rd overtone crystals to suppress oscillation in the fundamental mode A test resistor Ro may be temporarily inserted to measure the oscillation allowance of the oscillator circuitry XTAL1 XTAL2 MCS04335 Figure 6 2 External Oscillator Circuitry The on chip oscillator is optimized for an input frequency range of 4 to 40 MHz
44. The basic register layout is shown below Table 16 7 lists the associated addresses CCxIC CAPCOM Intr Ctrl Reg E SFR See Table 16 7 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CCx CC IR AE ILVL GLVL wh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 16 22 V2 0 2000 07 _ e nfineon technologies C167CS Derivatives The Capture Compare Units Table 16 7 CAPCOM Unit Interrupt Control Register Addresses CAPCOM Unit CAPCONM Unit Register Address Reg Space Register Address Reg Space CCOIC FF7 8 BO SFR CC16IC F160 BO ESFR CC1IC FF7A BDy SFR CC171C F162 B1 ESFR CC2IC FF7C BE SFR CC18IC F164 B2 ESFR CCSIC FF7E BFy SFR CC19IC F166 B3 ESFR CC4IC FF80 CO SFR CC20IC F168 BA4 ESFR CC5IC FF82 C14 SFR CC211C F16A B5 ESFR CC6IC FF84 C2 SFR CC221C F16C B6 ESFR CC7IC FF86 C3 SFR CC23IC F16E B7 ESFR CC8IC FF88 C4 SFR CC24IC F170 B8 ESFR CC9IC FF8A C5y4 SFR CC25IC F1724 B94 ESFR CC10IC FF8C C6 SFR CC26IC F174 BA ESFR CC111C FF8E C7 SFR CC271C F176 BB ESFR CC12IC FF90 C8 SFR CC28IC F178 BC ESFR CC13IC FF92 C9 SFR CC29IC F184 C2 ESFR CC14IC FF94 CA SFR CC30IC F18C C6 ESFR CC15IC FF96 CBy SFR C
45. When a match occurs between the timer value and the value in a capture compare register specific actions will be taken based on the selected compare mode Pulse Width Modulation Unit The PWM Unit supports the generation of up to four independent high speed PWM signals It allows to generate standard edge aligned PWM signals as well as symmetrical center aligned PWM signals In Burst Mode two channels may be combined with their output signals ANDed where one channel gates the output signal of the other channel Single Shot Mode allows to generate single output pulses retriggerable under software control Each PWM channel is controlled by an up down counter with associated reload and compare registers The polarity of the PWM output signals may be controlled via the respective port output latch combination via EXOR User s Manual 2 17 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview Watchdog Timer The Watchdog Timer represents one of the fail safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time The Watchdog Timer is always enabled after a reset of the chip and can only be disabled in the time interval until the EINIT end of initialization instruction has been executed Thus the chip s start up procedure is always monitored The software has to be designed to service the Watchdog Timer before it overflows If due to hardware o
46. configurations with different types of memories and or peripherals The following parameters of an external bus cycle are programmable ALE Control defines the ALE signal length and the address hold time after its falling edge e Memory Cycle Time extendable with 1 15 waitstates defines the allowable access time Memory Tri State Time extendable with 1 waitstate defines the time for a data driver to float Read Write Delay Time defines when a command is activated after the falling edge of ALE READY Control defines if a bus cycle is terminated internally or externally Note Internal accesses are executed with maximum speed and therefore are not programmable External accesses use the slowest possible bus cycle after reset The bus cycle timing may then be optimized by the initialization software ALE N a 3 ALECTL MCTC MTTC MCD02225 Figure 9 5 Programmable External Bus Cycle User s Manual 9 12 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface ALE Length Control The length of the ALE signal and the address hold time after its falling edge are controlled by the ALECTLx bits in the BUSCON registers When bit ALECTL is set to 1 external bus cycles accessing the respective address window will have their ALE signal prolonged by half a CPU clock 1 TCL Also the address hold time
47. counts up or down controlled by hardware while its respective run control bit PTRx is set A timer is started PTRx 1 via software and is stopped PTRx 0 either via hardware or software depending on its operating mode Control bit PTRx enables or disables the clock input of counter PTx rather than controlling the PWM output signal Note For the register locations please refer to Table 17 2 further below Table 17 1 summarizes the PWM frequencies that result from various combinations of operating mode counter resolution input clock and pulse width resolution Table 17 1 PWM Output Frequency and Resolution Inp Clk fepy x PWM 8 bit PWM 10 bit PWM 12 bit PWM 14 bit PWM 16 bit PWM Counter resol Mode Resolution Resolution Resolution Resolution Resolution 16 MHz 1 0 62 50 kHz 15 63 kHz 3 91 kHz 976 6 Hz 244 1 Hz 62 5 ns 1 31 25 kHz 7 81 kHz 1 95 kHz 488 3 Hz 122 1 Hz 16 MHz 64 0 976 6 Hz 244 1 Hz 61 04 Hz 15 29 Hz 3 81 Hz 4 0 us 1 488 3 Hz 122 1 Hz 30 52 Hz 7 63 Hz 1 91 Hz 20 MHz 1 0 78 13 kHz 19 53 kHz 4 88 kHz 1 22 kHz 305 2 Hz 50 ns 1 39 06 kHz 9 77 kHz 2 44 kHz 610 4 Hz 152 6 Hz 20 MHz 64 0 1 22 kHz 305 2 Hz 76 29 Hz 19 07 Hz 4 77 Hz 3 2 us 1 610 4 Hz 152 6 Hz 38 15 Hz 9 54 Hz 2 38 Hz 25 MHz 1 0 97 66 kHz 24 41 kHz 6 10 kHz 1 53 kHz 381 5 Hz 40 ns 1 48 83 kHz 12 21 kHz 3 05 kHz 762 9 Hz 190 7 Hz 25 MHz 64 0 1
48. holds a branch instruction to the actual initialization routine that may be located anywhere in the address space Note When the Bootstrap Loader Mode was activated during a hardware reset the C167CS does not fetch instructions from the program memory The standard bootstrap loader expects data via serial interface ASCO User s Manual 20 8 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset 20 3 Application Specific Initialization Routine After a reset the modules of the C167CS must be initialized to enable their operation on a given application This initialization depends on the task the C167CS is to fulfill in that application and on some system properties like operating frequency connected external circuitry etc The following initializations should typically be done before the C167CS is prepared to run the actual application software Memory Areas The external bus interface can be reconfigured after an external reset because register BUSCONO is initialized to the slowest possible bus cycle configuration The programmable address windows can be enabled in order to adapt the bus cycle characteristics to different memory areas or peripherals Also after a single chip mode reset the external bus interface can be enabled and configured The internal program memory if available can be enabled and mapped after an external reset in order to use the on chip resources After a single chip mode reset the intern
49. is decremented by a subtract instruction the IP value pushed represents the address of the instruction after the instruction following the subtract instruction For recovery from stack overflow it must be ensured that there is enough excess space on the stack for saving the current system state PSW IP in segmented mode also CSP twice Otherwise a system reset should be generated Stack Underflow Trap Whenever the stack pointer is incremented to a value which is greater than the value in the stack underflow register STKUN the STKUF flag is set in register TFR and the CPU will enter the stack underflow trap routine Again which IP value will be pushed onto the system stack depends on which operation caused the increment of the SP When an implicit increment of the SP is made through a POP or return instruction the IP value pushed is the address of the following instruction When the SP is incremented by an add instruction the pushed IP value represents the address of the instruction after the instruction following the add instruction Undefined Opcode Trap When the instruction currently decoded by the CPU does not contain a valid C167CS opcode the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine The IP value pushed onto the system stack is the address of the instruction that caused the trap This can be used to emulate unimplemented instructions The trap service routine can examine the faultin
50. lt CP gt 164 R11 lt CP gt 144 R10 lt CP gt 124 x H9 CP 104 H8 CP OEY RH7 RL7 R7 CP 0Cy RH6 RL6 R6 CP OAy RH5 RL5 R5 CP 084 RH4 RL4 R4 CP 064 RH3 RL3 R3 CP 044 RH2 RL2 R2 lt CP gt 024 RH1 RL1 R1 CP 004 RHO RLO RO The C167CS supports fast register bank context switching Multiple register banks can physically exist within the internal RAM at the same time Only the register bank selected by the Context Pointer register CP is active at a given time however Selecting a new active register bank is simply done by updating the CP register A particular Switch Context SCXT instruction performs register bank switching and an automatic saving of User s Manual 3 6 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization the previous context The number of implemented register banks arbitrary sizes is only limited by the size of the available internal RAM Details on using switching and overlapping register banks are described in Chapter 22 PEC Source and Destination Pointers The 16 word locations in the internal RAM from 00 FCEO to 00 FCFE just below the bit addressable section are provided as source and destination address pointers for data transfers on the eight PEC channels Each channel uses a pair of pointers stored in two subsequent word locations with the source pointer SRCPx on the lower and the destination poin
51. register RPOH This read only register holds the selection for the number of chip selects User s Manual 7 13 V2 0 2000 07 eo nfineon ed technologies Derivatives Parallel Ports and segment addresses Software can read this register in order to react according to the selected configuration if required When the reset is terminated the internal pullup devices are switched off and PORTO will be switched to the appropriate operating mode During external accesses in multiplexed bus modes PORTO first outputs the 16 bit intra segment address as an alternate output function PORTO is then switched to high impedance input mode to read the incoming instruction or data In 8 bit data bus mode two memory cycles are required for word accesses the first for the low byte and the second for the high byte of the word During write cycles PORTO outputs the data byte or word after outputting the address During external accesses in demultiplexed bus modes PORTO reads the incoming instruction or data word or outputs the data byte or word Alternate Function a b c d POH 7 D15 A15 AD15 POH 6 D14 A14 AD14 POH 5 D13 A13 AD13 POH POH 4 D12 A12 AD12 POH 3 D11 A11 AD11 POH 2 D10 A10 AD10 POH 1 D9 A9 AD9 Port 0 POH 0 D8 A8 AD8 POL 7 D7 D7 AD7 AD7 POL 6 D6 D6 AD6 AD6 POL 5 D5 D5 AD5 AD5 POL 4 D4 D4 AD4 AD4 POL POL 3 D3 D3 AD3 AD3 POL 2 D2 D2 AD2 AD2 POL 1 D1 D1 AD1 AD1 POL O DO DO ADO ADO General Purpose 8 Bit 16 Bit 8 Bit 1
52. the 10 bit result together with the number of the converted channel is transferred into the result register ADDAT and the interrupt request flag ADCIR is set The conversion result is placed into bitfield ADRES of register ADDAT If bit ADST is reset via software while a conversion is in progress the A D converter will stop after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Setting bit ADST while a conversion is running will abort this conversion and start a new conversion with the parameters specified in ADCON Note Abortion and restart see above are triggered by bit ADST changing from 0 to 1 Le ADST must be 0 before being set While a conversion is in progress the mode selection field ADM and the channel selection fields ADCH and ADX may be changed ADM will be evaluated after the current conversion ADCH and ADX will be evaluated after the current conversion fixed channel modes or after the current conversion sequence auto scan modes Note When selecting an extension channel AN23 AN16 only write numbers within the range 0 7 to bitfield ADCH Higher channel numbers are not defined for extension channels and will return invalid conversions results Fixed Channel Conversion Modes These modes are selected by programming the mode selection bitfield ADM in register ADCON to 00 single conversion or to 01 continuous conversion
53. where no internal program memory is provided User s Manual 9 21 V2 0 2000 07 _ e e Infineon technologies C167CS Derivatives BUSCONO The External Bus Interface Bus Control Register 0 SFR FF0C4 86 Reset Value 0XX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD ENO ENO ENO Co AGT CTL ENg BTYP Co co Ment wo IW rw rw rmwh wh rw rwh wo rw rw BUSCON1 Bus Control Register 1 SFR FF14 8A Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD ENT EN1 EN1 C1 AGT CTL i eNy BTYP C1 c1 MEIG rw rw z rw rw rw rw rw rw rw rw rw BUSCON2 Bus Control Register 2 SFR FF164 8Bp Reset Value 00004 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN2 EN2 EN2 C2 ACT CTL EN2 BTYP C2 c2 MCTC rw rw rw rw rw rw rw rw rw rw rw BUSCONS3 Bus Control Register 3 SFR FF18 8C Reset Value 0000 15 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN3 EN3 EN3 C3 CT CIL ENS BTYP C3 C3 METE rw rw rw rw rw rw rw rw rw rw rw BUSCON4 Bus Control Register 4 SFR FF1Ap 8Dp Reset Value 00004 15
54. 0 P5 P5 P5 P5 P5 P5 P5 P5 MS 2 43 ae 13 40 9 P57 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 r r r r r r r r r r r r r r r r Bit Function P5 y Port data register P5 bit y Read only Alternate Functions of Port 5 Each line of Port 5 is also connected to the input multiplexer of the Analog Digital Converter All port lines can accept analog signals ANx that can be converted by the ADC For pins that shall be used as analog inputs it is recommended to disable the digital input stage via register P5DIDIS see description below This avoids undesired cross currents and switching noise while the analog input signal level is between V and Vip Some pins of Port 5 also serve as external GPT timer control lines Table 7 7 summarizes the alternate functions of Port 5 User s Manual 7 38 V2 0 2000 07 o nfineon technologies C167CS Derivatives Parallel Ports Table 7 7 Alternate Functions of Port 5 Port 5 Pin Alternate Function a Alternate Function b P5 0 Analog Input ANO P5 1 Analog Input AN1 P5 2 Analog Input AN2 P5 3 Analog Input AN3 P5 4 Analog Input AN4 P5 5 Analog Input AN5 P5 6 Analog Input AN6 P5 7 Analog Input AN7 P5 8 Analog Input AN8 P5 9 Analog Input AN9 P5 10 Analog Input AN10 T6EUD Timer 6 ext Up Down Input P5 11 Analog Input AN11 T5EUD Ti
55. 011g removes the CAN interface lines completely from Port 4 The maximum external address space of 16 MByte is available in this case The CAN interface lines are mapped to Port 8 Two pairs of Port 8 pins can be selected No Assignment IPC 111g disconnects the CAN interface lines from the port logic This avoids undesired currents through the interface pin drivers while the C167CS is in a power saving state After reset the CAN interface lines are disconnected Bus Sharing internally combines the interface lines of both CAN modules receive line is shared transmit lines are ANDed This provides up to 30 message objects 2 x 15 on a single physical CAN bus Bus sharing is enabled by simply assigning both CAN interfaces to the same pair of port pins Note Assigning CAN interface signals to a port pin overrides the other alternate function of the respective pin segment address on Port 4 CAPCOM lines on Port 8 User s Manual 19 41 V2 0 2000 07 d nfineon ed technologies Derivatives System Reset 20 System Reset The internal system reset function provides initialization of the C167CS into a defined default state and is invoked either by asserting a hardware reset signal on pin RSTIN Hardware Reset Input upon the execution of the SRST instruction Software Reset or by an overflow of the watchdog timer Whenever one of these conditions occurs the microcontroller is reset into its predefined default sta
56. 10 ns Input pulses with a duration of 100 ns minimum are recognized and generate an interrupt request This filter delays the recognition of an external wakeup signal by approx 100 ns but the spike suppression ensures safe and robust operation of the sleep wakeup mechanism in an active environment a 100 ns 10ns Signal Interrupt Request Rejected Recognized MCD04456 Figure 5 6 Input Noise Filter Operation User s Manual 5 30 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 9 Trap Functions Traps interrupt the current execution similar to standard interrupts However trap functions offer the possibility to bypass the interrupt system s prioritization process in cases where immediate system reaction is required Trap functions are not maskable and always have priority over interrupt requests on any priority level The C167CS provides two different kinds of trapping mechanisms Hardware traps are triggered by events that occur during program execution e g illegal access or undefined opcode software traps are initiated via an instruction within the current execution flow Software Traps The TRAP instruction is used to cause a software call to an interrupt service routine The trap number that is specified in the operand field of the trap instruction determines which vector location in the address range from 00 0000 through 00 01FC will be
57. 1000 0000 0000 After PUSH After PUSH FBFE 1111 1011 1 M FBFE 1 1 1 1 10 1111 1110 FBFE 1111 1011 1111 1110 Phys A FBFE 1 1111 1110 FB7E H11 1011 0111 1110 lt SP gt FE 1111 1110 64 words Stack Size 256 words MCA04408 Figure 22 1 Physical Stack Address Generation The following example demonstrates the circular stack mechanism which is also an effect of this virtual stack mapping First register R1 is pushed onto the lowest physical stack location according to the selected maximum stack size With the following instruction register R2 will be pushed onto the highest physical stack location although the SP is decremented by 2 as for the previous push operation MOV SP 40F802H Set SP before last entry Pe Of physical stack of 256 words SP F802H Physical stack addr PUSH R1 SP F800H Physical stack addr PUSH R2 SP F7FEH Physical stack addr User s Manual 22 6 FAO2H FAOOH FBFEH V2 0 2000 07 j d nfineon ed technologies Derivatives System Programming The effect of the address transformation is that the physical stack addresses wrap around from the end of the defined area to its beginning When flushing and filling the internal stack this circular stack mechanism only requires to move that portion of stack data which is really to be re used i e the upper part of the defined stack area instead of the whole stack area Stack data that remain in the low
58. 12 do not support open drain mode P3 Port 3 Data Register SFR FFC4 E2 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P3 P3 P3 P3 P3 P3 P3 45 43 42 44 40 9 8 P37 P3 6 P3 5 P34 P3 3 P3 2 P3 1 P3 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P3 y Port data register P3 bit y DP3 P3 Direction Ctrl Register SFR FFC6 E34 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O0 DP3 _ DP3 DP3 DP3 DPS3 DPS3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 DP3 15 13 412 11 10 9 8 7 6 5 4 3 2 4 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function DP3 y Port direction register DP3 bit y DP3 y 0 Port line P3 y is an input high impedance DP3 y 1 Port line P3 y is an output User s Manual 7 28 V2 0 2000 07 T e nfineon technologies ODP3 C167CS Derivatives Parallel Ports P3 Open Drain Ctrl Reg ESFR F1C6 E3 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 95 euren er aap or p np oor ORP ep QPP o rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function ODP3 y Port 3 Open Drain control register bit y ODP3 y 0 Port line P3 y output driver in push pull mode ODP3 y 1 Port line P3 y output driver in
59. 14 18 12 11 10 9 8 7 6 5 4 3 2 1 0 BUS ALE CSW CSR RDY BSW EW MTT RWD EN4 EN4 EN4 C4 CT CIL EN4 BTYP C4 c4 MAIG rw rw rw rw rw rw rw rw rw rw rw User s Manual 9 22 V2 0 2000 07 d nfineon ed technologies Derivatives The External Bus Interface Bit Function MCTC Memory Cycle Time Control Number of memory cycle time wait states 0000 15 waitstates Number 15 lt MCTC gt 1111 No waitstates Note The definition of bitfield MCTCx changes if RDYENx 1 see Chapter 9 4 RWDCx Read Write Delay Control for BUSCONx 0 With rd wr delay activate command 1 TCL after falling edge of ALE q1 No rd wr delay activate command with falling edge of ALE MTTCx Memory Tristate Time Control 0 1 waitstate E No waitstate BTYP External Bus Configuration 00 8 bit Demultiplexed Bus 01 8 bit Multiplexed Bus 10 16 bit Demultiplexed Bus 11 16 bit Multiplexed Bus Note For BUSCONO BTYP is defined via PORTO during reset EWENx Early Write Enable 0 Normal WR signal i Early write WR signal is deactivated and write data is tristated one TCL earlier ALECTLx ALE Lengthening Control 0 Normal ALE signal 3 Lengthened ALE signal BUSACTx Bus Active Control 0 External bus disabled 1 External bus enabled within respective address window ADDRSEL BSWCx BUSCON Switch Control 0 Address windows are switched immediately p A tristate waitstate is inserted if the next bus cycle accesse
60. 53 kHz 381 5 Hz 95 37 Hz 23 84 Hz 5 96 Hz 2 56 us 1 762 9 Hz 190 7 Hz 47 68 Hz 11 92 Hz 2 98 Hz 33 MHz 1 0 128 9 kHz 32 23 kHz 8 06 kHz 2 01 kHz 503 5 Hz 30 3 ns 1 64 45 kHz 16 11 kHz 4 08 kHz 1 01 kHz 251 8 Hz 33 MHz 64 0 2 01 kHz 503 5 Hz 125 9 Hz 31 47 Hz 7 87 Hz 1 94 us 1 1 01 kHz 251 8 Hz 62 94 Hz 15 74 Hz 3 98 Hz User s Manual 17 10 V2 0 2000 07 d nfineon en technologies Derivatives The Pulse Width Modulation Module Period Registers PPx The 16 bit period register PPx see Table 17 2 for locations of a PWM channel determines the period of a PWM cycle i e the frequency of the PWM signal This register is buffered with a shadow register The shadow register is loaded from the respective PPx register at the beginning of every new PWM cycle or upon a write access to PPx while the timer is stopped The CPU accesses the PPx register while the hardware compares the contents of the shadow register with the contents of the associated counter PTx When a match is found between counter and PPx shadow register the counter is either reset to 0000 or the count direction is switched from counting up to counting down depending on the selected operating mode of that PWM channel Pulse Width Registers PWx The 16 bit pulse width register PWx see Table 17 2 for locations of a PWM channel holds the actual PWM pulse width value which corresponds to the duty cycle of the PWM signal This register is buf
61. 6 5 4 3 2 1 O0 T8R T8M T8l T7R T7M T7I rw rw rw rw z z rw rw Bit Function Txl Timer Counter x Input Selection Timer Mode TxM 0 Input Frequency fopy o Txl 3 See also Table 16 2 Table 16 4 for examples Counter Mode TxM 2 1 000 Overflow Underflow of GPT2 Timer 6 001 Positive rising edge on pin T7IN 010 Negative falling edge on pin T7IN 011 Any edge rising and falling on pin T7IN 1XX Reserved TxM Timer Counter x Mode Selection 0 Timer Mode Input derived from internal clock a Counter Mode Input from External Input or T6 TxR Timer Counter x Run Control 0 Timer Counter x is disabled 1 Timer Counter x is enabled 1 This selection is available for timers TO and T7 Timers T1 and T8 will stop at this selection User s Manual 16 5 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units The timer run flags TOR T1R T7R and T8R allow for enabling and disabling the timers The following description of the timer modes and operation always applies to the enabled state of the timers i e the respective run flag is assumed to be set to 1 In all modes the timers are always counting upward The current timer values are accessible for the CPU in the timer registers Tx which are non bitaddressable SFRs When the CPU writes to a register Tx in the state immediately before the respective timer increment or reload is to be per
62. 746 31 25 10 MHz 10000 5000 13333 33 158 73 1156 25 044 09 5000 2500 1666 67 79 365 78 125 12 MHz 12000 16000 4000 190 476 187 5 05 OBH 6000 3000 2000 95 238 93 75 16 MHz 16000 18000 5333 33 253 968 250 074 OF y 8000 4000 2666 67 126 984 125 20 MHz 20000 10000 6666 67 317 46 312 5 094 134 10000 5000 3333 33 158 73 1156 25 25 MHz 25000 12500 8333 33 396 825 390 625 OB 184 12500 6250 4166 67 198 413 195 313 1 04167 0Cy 0 96154 33 MHz 33000 16500 11000 523 810 515 625 OFy 20H 16500 8250 5500 261 905 257 816 1 03125 104 0 97059 Users Manual 21 21 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management 21 7 Security Mechanism The power management control registers belong to a set of registers see Table 21 7 which control functions and modes which are critical for the C167CS s operation For this reason they are locked except for bitfield SYSRLS in register SYSCON2 after the execution of EINIT like register SYSCON so these vital system functions cannot be changed inadvertently e g by software errors However as these registers control important functions e g the power management they need to be accessed during operation to select the appropriate mode The system control software gets this access via a special unlock sequence which allows one single write access to one register of this set when executed properly
63. After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit fields ADCH ADX will be converted After the conversion is complete the interrupt request flag ADCIR will be set In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new conversion of the channel specified in ADCH ADX ADCIR will be set after each completed conversion When bit ADST is reset by software while a conversion is in progress the converter will complete the current conversion and then stop and reset bit ADBSY User s Manual 18 6 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter Auto Scan Conversion Modes These modes are selected by programming the mode selection field ADM in register ADCON to 10g single conversion or to 115 continuous conversion Auto Scan modes automatically convert a sequence of analog channels beginning with the channel specified in bit fields ADCH ADX and ending with channel O channel 16 without requiring software to change the channel number After starting the converter through bit ADST the busy flag ADBSY will be set and the channel specified in bit fields ADCH ADX will be converted After the conversion is complete the interrupt request flag ADCIR will be set and the converter will automatically start a new conversion of the ne
64. Again the group priority increases with the numerical value of GLVL so 00g is the lowest and 11g is the highest group priority Note All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities Otherwise an incorrect interrupt vector will be generated Upon entry into the interrupt service routine the priority level of the source that won the arbitration and who s priority level is higher than the current CPU level is copied into bit field ILVL of register PSW after pushing the old PSW contents on the stack The interrupt system of the C167CS allows nesting of up to 15 interrupt service routines of different priority levels level 0 cannot be arbitrated Interrupt requests that are programmed to priority levels 15 or 14 i e ILVL 111Xg will be serviced by the PEC unless the COUNT field of the associated PECC register contains zero In this case the request will instead be serviced by normal interrupt processing Interrupt requests that are programmed to priority levels 13 through 1 will always be serviced by normal interrupt processing Note Priority level 0000g is the default level of the CPU Therefore a request on level 0 will never be serviced because it can never interrupt the CPU However an enabled interrupt request on level 0000g will terminate the C167CS s Idle mode and reactivate the CPU For interrupt requests which are to be serviced by
65. Bit Function FOCNT Frequency Output Counter FOTL Frequency Output Toggle Latch Is toggled upon each underflow of FOCNT FORV Frequency Output Reload Value Is copied to FOCNT upon each underflow of FOCNT FOSS Frequency Output Signal Select 0 Output of the toggle latch duty cycle 50 E Output of the reload counter duty cycle depends on FORV FOEN Frequency Output Enable 0 Frequency output generation stops when signal four is gets low 1 FOCNT is running four is gated to pin First reload after 0 1 transition Note It is not recommended to write to any part of bitfield FOCNT especially not while the counter is running Writing to FOCNT prior to starting the counter is obsolete because it will immediatley be reloaded from FORV Writing to FOCNT during operation may produce unintended counter values User s Manual 21 18 V2 0 2000 07 o nfineon e technologies Derivatives Power Management Signal four in the C167CS is an alternate function of pin P3 15 CLKOUT FOUT Direction CLKEN FOUT active PortLatch Sour foru MCA04481 Figure 21 7 Connection to Port Logic Functional Approach A priority ranking determines which function controls the shared pin Table 21 4 Priority Ranking for Shared Output Pin Priority Function Control 1 CLKOUT CLKEN 1 FOEN x 2 FOUT CLKEN 0 FOEN 1 3 General purpose IO CLKEN 0 F
66. Bus Arbitration Releasing the Bus Note The C167CS will complete the currently running bus cycle before granting bus access as indicated by the broken lines This may delay hold acknowledge compared to this figure Figure 9 12 shows the first possibility for BREQ to get active During bus hold pin BHE WHRH is floating An external pullup should be used if this is required User s Manual 9 33 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Exiting the Hold State The external bus master returns the access rights to the C167CS by driving the HOLD input high After synchronizing this signal the C167CS will drive the HLDA output high actively drive the control signals and resume executing external bus cycles if required Depending on the arbitration logic the external bus can be returned to the C167CS under two circumstances The external master does no more require access to the shared resources and gives up its own access rights or The C167CS needs access to the shared resources and demands this by activating its BREQ output The arbitration logic may then activate the other master s HOLD and so free the external bus for the C167CS depending on the priority of the different masters Note The Hold State is not terminated by clearing bit HLDEN oo S 1 3 a a a EE CSx Other c C 1 r Signals MCD02236 Figure 9 13 External Bus Arbitration
67. Bus Modes In the demultiplexed bus modes the 16 bit intra segment address is permanently output on PORT1 while the data uses PORTO 16 bit data or POL 8 bit data The upper address lines are permanently output on Port 4 if selected via SALSEL during reset No address latches are required The EBC initiates an external access by placing an address on the address bus After a programmable period of time the EBC activates the respective command signal RD WR WRL WRH Data is driven onto the data bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the data bus which is then tri stated again Write cycles The command signal is now deactivated If a subsequent external bus cycle is required the EBC places the respective address on the address bus The data remain valid on the bus until the next external bus cycle is started Bus Cycle sea Segment P4 Ben l MCD02061 Figure 9 3 Demultiplexed Bus Cycle User s Manual 9 5 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Switching Between the Bus Modes The EBC allow
68. DISWDT Note After a hardware reset that activates the Bootstrap Loader the watchdog timer will be disabled The software reset that terminates the BSL mode will then enable the WDT When the watchdog timer is not disabled via instruction DISWDT it will continue counting up even during Idle Mode If it is not serviced via the instruction SRVWDT by the time the count reaches FFFF the watchdog timer will overflow and cause an internal reset This reset will pull the external reset indication pin RSTOUT low The Watchdog Timer Reset Indication Flag WDTR in register WDTCON will be set in this case In bidirectional reset mode also pin RSTIN will be pulled low for the duration of the internal reset sequence and a long hardware reset will be indicated instead A watchdog reset will also complete a running external bus cycle before starting the internal reset sequence if this bus cycle does not use READY or samples READY active low after the programmed waitstates Otherwise the external bus cycle will be aborted To prevent the watchdog timer from overflowing it must be serviced periodically by the user software The watchdog timer is serviced with the instruction SRVWDT which is a protected 32 bit instruction Servicing the watchdog timer clears the low byte and reloads the high byte of the watchdog timer register WDT with the preset value from bitfield WDTREL which is the high byte of register WDTCON Servicing the watchdog timer will
69. EXTR extend register instruction redirects accesses in short addressing modes to the ESFR space for 1 4 instructions so the additional registers can be accessed this way too The EXTPR and EXTSR instructions combine the DPP override mechanism with the redirection to the ESFR space using a single instruction Note Instructions EXTR EXTPR and EXTSR inhibit interrupts the same way as ATOMIC The switching to the ESFR area and data page overriding is checked by the development tools or handled automatically Nested Locked Sequences Each of the described extension instruction and the ATOMIC instruction starts an internal extension counter counting the effected instructions When another extension or ATOMIC instruction is contained in the current locked sequence this counter is restarted with the value of the new instruction This allows the construction of locked sequences longer than 4 instructions Note Interrupt latencies may be increased when using locked code sequences PEC requests are not serviced during idle mode if the IDLE instruction is part of a locked sequence User s Manual 22 15 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 10 Handling the Internal Code Memory The Mask ROM OTP Flash versions of the C167CS provide on chip code memory that may store code as well as data The lower 32 KByte of this code memory are referred to as the internal ROM area Access to this internal
70. FEAE 1574 Watchdog Timer Register read only 0000 WDTCON b FFAE D7y_ Watchdog Timer Control Register 2 00xx XPOIC b F186 E C3 4 CAN I Interrupt Control Register 0000 XP1IC b F18E E C74 CAN Interrupt Control Register 00004 XP2IC b F1964 E CB Unassigned Interrupt Control Register 0000 XP3IC b F19E E CFy RTC PLL OWD Interrupt Control Register 00004 XPERCON F0244 124 X Peripheral Control Register 04014 ZEROS b FF1C 8E Constant Value 0 s Register read only 0000 1 The System configuration is selected during reset 2 User s Manual The reset value depends on the indicated reset source 23 13 V2 0 2000 07 o nfineon technologies 23 4 C167CS Derivatives The Register Set Special Function Registers Ordered by Address Table 23 4 lists all SFRs which are implemented in the C167CS ordered by their physical address Bit addressable SFRs are marked with the letter b in column Name SFRs within the extended SFR space ESFRs are marked with the letter E in column Physical Address Registers within on chip X Peripherals are marked with the letter X in column Physical Address Table 23 4 C167CS Registers Ordered by Address Name Physical 8 bit Description Reset Address Addr Value C2CSR EEOO X CAN Control Status Register XX014 C2PCIR EEO24 X CAN2Port Control and Interrupt Reg
71. FFF STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 512 words Note Register SYSCON cannot be changed after execution of the EINIT instruction The function of bits XPER SHARE VISIBLE WRCFG BYTDIS ROMEN and ROMS1 is described in more detail in Chapter 9 User s Manual 4 14 V2 0 2000 07 d nfineon ed technologies Derivatives The Central Processing Unit CPU System Clock Output Enable CLKEN The system clock output function is enabled by setting bit CLKEN in register SYSCON to 1 If enabled port pin P3 15 takes on its alternate function as CLKOUT output pin The clock output is a 5096 duty cycle clock except for direct drive operation where CLKOUT reflects the clock input signal and for slowdown operation where CLKOUT mirrors the CPU clock signal whose frequency equals the CPU operating frequency four fcPu Note The output driver of port pin P3 15 is switched on automatically when the CLKOUT function is enabled The port direction bit is disregarded After reset the clock output function is disabled CLKEN 0 In emulation mode the CLKOUT function is enabled automatically While signal CLKOUT is tightly coupled to the CPU clock signal the programmable frequency signal FOUT controlled by register FOCON may be output on this pin Please refer to Chapter 21 Segmentation Disable Enable Control SGTDIS Bit SGTDIS allows to s
72. Generated Warm Reset b Automatic Power ON Reset MCA04483 Figure 20 1 External Reset Circuitry User s Manual 20 1 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset 20 1 Reset Sources Several sources external or internal can generate a reset for the C167CS Software can identify the respective reset source via the reset source indication flags in register WDTCON Generally any reset causes the same actions on the C167CS s modules The differences are described in the following sections Hardware Reset A hardware reset is triggered when the reset input signal RSTIN is latched low To ensure the recognition of the RSTIN signal latching it must be held low for at least 100 ns plus 2 CPU clock cycles input filter plus synchronization Also shorter RSTIN pulses may trigger a hardware reset if they coincide with the latch s sample point The actual minimum duration for a reset pulse depends on the current CPU clock generation mode The worstcase is generating the CPU clock via the SlowDown Divider using the maximum factor while the configured basic mode uses the prescaler fcpy fosc 64 in this case After the reset sequence has been completed the RSTIN input is sampled again When the reset input signal is inactive at that time the internal reset condition is terminated indicated as short hardware reset SHWR When the reset input signal is still active at that time the internal re
73. I n BRANCH nec IARGET I ARGET H WRITEBACK I n BRANCH Insect TT aRGET Time gt MCT04328 Figure 4 3 User s Manual 4 4 Standard Branch Instruction Pipelining V2 0 2000 07 o nfineon e technologies Derivatives The Central Processing Unit CPU If a conditional branch is not taken there is no deviation from the sequential program flow and thus no extra time is required In this case the instruction after the branch instruction will enter the decode stage of the pipeline at the beginning of the next machine cycle after decode of the conditional branch instruction Cache Jump Instruction Processing The C167CS incorporates a jump cache to optimize conditional jumps which are processed repeatedly within a loop Whenever a jump on cache is taken the extra time to fetch the branch target instruction can be saved and thus the corresponding cache jump instruction in most cases takes only one machine cycle This performance is achieved by the following mechanism Whenever a cache jump instruction passes through the decode stage of the pipeline for the first time and provided that the jump condition is met the jump target instruction is fetched as usual causing a time delay of one machine cycle In contrast to standard branch instructions however the target instruction of a cache jump instruction JMPA JMPR JB JBC JNB JNBS is additionally
74. Individual port drivers can be disabled simply by configuring them for input The bus interface pins can be separately disabled by releasing the external bus disable all address windows by clearing the BUSACT bits and switching the ports to input if necessary Of course the required software in this case must be executed from internal memory User s Manual 21 5 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management SYSCON1 System Control Reg 1 ESFR F1DC EE Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLEEP CON rw Bit Function SLEEPCON SLEEP Mode Configuration mode entered upon the IDLE instruction 00 Normal IDLE mode 01 SLEEP mode with RTC running 10 Reserved 11 SLEEP mode with RTC and oscillator stopped Note SYSCONI is write protected after the execution of EINIT unless it is released via the unlock sequence see Table 21 6 21 3 Power Down Mode The microcontroller can be switched to Power Down mode which reduces the power consumption to a minimum Clocking of all internal blocks is stopped RTC and oscillator optionally the contents of the internal RAM however are preserved through the voltage supplied via the Vpp pins The watchdog timer is stopped in Power Down mode This mode can only be terminated by an external hardware reset i e by asserting a low level on the RSTIN pin This reset wil
75. L429 P3 13 SCLK P5 3 AN3 cf30 P3 12 BHE WRH P5 4 AN4 r 31 P3 111 RxDO P5 5 AN5 432 P3 10 TxDO P5 6 AN6 433 P3 9 MTSR P5 7 AN7 cf34 P3 8 MRST P5 8 AN8 F435 P3 7 T2IN P5 9 AN9 F436 730 P3 6 T3IN 3 4 GEDAZZAA v 00000000 828 eaZZZZZZZZZEZEQZ va Dpgopng eoraeozx ort 9r99zootogagps eaor EETA OOo0O0O0O0O09090 B Ga oO See Soe Eee 2 ee Qooooooo 65nS6nnesegEcEg9gccs ocllrszao SESTA ON OOOOOOOrg cdoxgp Soateaetqsos ANAA AA A A DROrAMT c O c5 c5 zx zz amp a oanana Torr W a ZEZN0gE S8Q200056 e of Srpg 5 o99o000z row Oo mc Li T vnd as Naoe mWO lo 1 lo 10 Qu Vu X Te tQ aa qa NNNNNO aanta S a a MCP04431 Figure 25 1 Pin Configuration P MQFP 144 Package top view Note Signals CAN1 TxD and CAN1_RxD are not available in all derivatives of the C167CS User s Manual 25 2 V2 0 2000 07 e nfineon technologies C167CS Derivatives 26 Keyword Index Keyword Index This section lists a number of keywords which refer to specific details of the C167CS in terms of its architecture its functional units or functions This helps to quickly find the answer to specific questions about the C167CS A Access to X Peripherals 9 40 Acronyms 1 7 Adapt Mode 20 15 ADC 2 15 18 1 ADCIC ADEIC 18 15 ADCON 18 3 ADDAT ADDAT2 18 6 Address Arbitration 9 27 Area Definition 9 26 Boundaries 3 12 Segment 9 9 20 18 ADDRSELx 9 25 9 27 ALE length 9 13 Alternate signals 7 9 ALU 4 16 An
76. P5D P5D P5D P5D P5D P5D P5D P5D P5D P5D P5D P5D P5D P5D P5D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function P5D y Port 5 Bit y Digital Input Control P5D y 20 Digital input stage connected to port line P5 y P5D y 21 Digital input stage disconnected from port line P5 y When being read or used as alternate input this line appears as 1 Port 5 pins have a special port structure see Figure 7 20 first because it is an input only port and second because the analog input channels are directly connected to the pins rather than to the input latches User s Manual 7 40 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Internal Bus xe to o tc DiglnputEN Clock AltDataln lt Input Pin ChannelSelect Latch Analoglnput lt MCB04357 P5 15 0 Figure 7 20 Block Diagram of a Port 5 Pin Note The AltDataln line does not exist on all Port 5 inputs User s Manual 7 41 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 10 Port 6 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP6 Each port line can be switched into push pull or open drain mode via the open
77. P8 0 CC23lO P8 7 CC2810O P7 4 CC3110 P7 7 CC241O P1H 4 CC2710 m m rm rm P1H 7 ODPx Port x Open Drain Control Register Tx CAPCOM Timer x Register DPx Port x Direction Control Register CCO 15 CAPCOM Register 0 15 Px Port x Data Register CC16 31 CAPCOM Register 16 31 TO1CON CAPCOM1 Timers TO T1 Control Register CCMO 3 CAPCOM Mode Control Register 0 3 T78CON CAPCOM2 Timers T7 T8 Control Register CCMA 7 CAPCOM2 Mode Control Register 4 7 TOIC T1IC CAPCOM Timer 0 1 Interrupt Ctrl Reg CC0 151IC CAPCOM1 Interrupt Ctrl Reg 0 15 T7IC T8IC_ CAPCOM Timer 7 8 Interrupt Ctrl Reg CC16 311C CAPCOM2 Interrupt Ctrl Reg 16 31 TxREL CAPCOM Timer x Reload Register MCA04386 Figure 16 1 SFRs and Port Pins Associated with the CAPCOM Units User s Manual 16 1 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units From the programmer s point of view the term CAPCOM unit refers to a set of SFRs which are associated with this peripheral including the port pins which may be used for alternate input output functions including their direction control bits A CAPCOM unit is typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation or recording of the time at which specific events occur It also allows the implementation of up to 16 software timers The maximum resolution of the CAPCOM units is 8 CPU clock cycles 16 TCL
78. Port 3 pins are not necessary Note Serial data transmission or reception is only possible when the Baud Hate Generator Run Bit SOR is set to 1 Otherwise the serial interface is idle Do not program the mode control field SOM in register SOCON to one of the reserved combinations to avoid unpredictable behavior of the serial interface User s Manual 11 4 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface 11 1 Asynchronous Operation Asynchronous mode supports full duplex communication where both transmitter and receiver use the same data frame format and the same baud rate Data is transmitted on pin TXDO and received on pin RXDO These signals are alternate port functions Reload Register SOR SOM SOSTP Clock Receive Int Sonn Request Transmit Int Serial Port Control SOTIR RXDO P3 1 1 Request Error Int Shift Clock SOEIR Request MUX Samp Receive Shift Transmit Shift ling Register Register Receive Buffer Reg SORBUF lt Internal Bus gt ceia Figure 11 2 Asynchronous Mode of Serial Channel ASCO TXDO P3 10 Transmit Buffer Reg SOTBUF Asynchronous Data Frames 8 bit data frames either consist of 8 data bits D7 DO SOM 0015 or of 7 data bits D6 DO plus an automatically generated parity bit SOM 011 Parity may be odd or even depending on bit SOODD in register SOCON An
79. ROM area is controlled during the reset configuration and via software The ROM area may be mapped to segment 0 to segment 1 or the code memory may be disabled at all Note The internal ROM area always occupies an address area of 32 KByte even if the implemented mask ROM OTP Flash memory is smaller than that e g 8 KByte Of course the total implemented memory may exceed 32 KBytes Code Memory Configuration During Reset The control input pin EA External Access enables the user to define the address area from which the first instructions after reset are fetched When EA is low 0 during reset the internal code memory is disabled and the first instructions are fetched from external memory When EA is high 1 during reset the internal code memory is globally enabled and the first instructions are fetched from the internal memory Note Be sure not to select internal memory access after reset on ROMless devices Mapping the Internal ROM Area After reset the internal ROM area is mapped into segment 0 the system segment 00 0000 00 7FFF 4 as a default This is necessary to allow the first instructions to be fetched from locations 00 0000 ff The ROM area may be mapped to segment 1 01 0000 01 7FFFjj by setting bit ROMS1 in register SYSCON The internal ROM area may now be accessed through the lower half of segment 1 while accesses to segment 0 will now be made to external memory This adds flexibility to the
80. Register 5 0000 CCM6 b FF26 93 CAPCOM Mode Control Register 6 0000 CCM7 b FF28 944 CAPCOM Mode Control Register 7 00004 PWMCONOb FF30 98 PWM Module Control Register 0 0000 PWMCON1b FF324 99 PWM Module Control Register 1 0000 T2CON b FF404 AO GPT1 Timer 2 Control Register 0000 T3CON b FF424 Ali GPT1 Timer 3 Control Register 00004 T4CON b FF444 A24 GPT1 Timer 4 Control Register 00004 T5CON b FF464 A34 GPT2 Timer 5 Control Register 0000 T6CON b FF484 A44 GPT2 Timer 6 Control Register 00004 TO1CON b FF504 A84 CAPCOM Timer 0 and Timer 1 Ctrl Reg 0000 CCMO b FF524 A9 CAPCOM Mode Control Register 0 0000 CCM1 b FF54 AA CAPCOM Mode Control Register 1 00004 CCM2 b FF56 AB CAPCOM Mode Control Register 2 0000 CCM3 b FF58y ACy CAPCOM Mode Control Register 3 00004 T2IC b FF604 BO GPT1 Timer 2 Interrupt Control Register 0000 T3IC b FF62 Bip GPT1 Timer 3 Interrupt Control Register 00004 TAIC b FF64 B2 GPT1 Timer 4 Interrupt Control Register 0000 T5IC b FF66 B3 GPT2 Timer 5 Interrupt Control Register 00004 T6IC b FF68y B4 GPT2 Timer 6 Interrupt Control Register 0000 CRIC b FF6A B5 GPT2 CAPREL Interrupt Control Register 0000 SOTIC b FF6C B6 Serial Channel 0 Transmit Interrupt Control 0000 Register SORIC b FFeE B7 Serial Channel 0 Receive Interrupt Control 00004 Register SOEIC b FF70 B84 Serial Channel 0 Error Interrupt Control 00004 Register SSCTI
81. S Input Latch MCB04361 P6 5 Figure 7 24 Block Diagram of Pin P6 5 HOLD Users Manual 7 47 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 11 Port 7 If this 8 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP7 Each port line can be switched into push pull or open drain mode via the open drain control register ODP7 P7 Port 7 Data Register SFR FFDOj E8 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 rw rw rw rw rw rw rw rw Bit Function P7 y Port data register P7 bit y DP7 P7 Direction Ctrl Register SFR FFD2 E94 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP7 DP7 DP7 DP7 DP7 DP7 DP7 DP7 7 6 ES 4 3 2 T 0 Bit Function DP7 y Port direction register DP7 bit y DP7 y 0 Port line P7 y is an input high impedance DP7 y 1 Port line P7 y is an output User s Manual 7 48 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports ODP7 P7 Open Drain Ctrl Reg ESFR F1D24 E9 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 ODP7 7 6 5 4 3 2 2 1 0
82. T2CON or TACON to 101g The active edge of the external input signal is determined by bit fields T2l or T4l When these fields are programmed to X01g interrupt request flags T2IR or T4IR in registers T2IC or T4IC will be set on a positive external transition at pins T2IN or TAIN respectively When T2l or T4l are programmed to X10p then a negative external transition will set the corresponding request flag When T2l or T4l are programmed to X11p both a positive and a negative transition will set the request flag In all three cases the contents of the core timer T3 will be captured into the auxiliary timer registers T2 or T4 based on the transition at pins T2IN or T4IN When the interrupt enable bits T2lE or T4IE are set a PEC request or an interrupt request for vector T2INT or T4INT will be generated Pin CAPIN differs slightly from the timer input pins as it can be used as external interrupt input pin without affecting peripheral functions When the capture mode enable bit T5SC in register T5CON is cleared to 0 signal transitions on pin CAPIN will only set the interrupt request flag CRIR in register CRIC and the capture function of register CAPREL is not activated So register CAPREL can still be used as reload register for GPT2 timer T5 while pin CAPIN serves as external interrupt input Bit field Cl in register T5CON selects the effective transition of the external interrupt input signal When Cl is programmed to 015g a positive exter
83. T3OTL can be used in a number of different configurations Depending on the selected active transition the following functions can be performed If both a positive and a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer each time it overflows or underflows This is the standard reload mode reload on overflow underflow If either a positive or a negative transition of T3OTL is selected to trigger a reload the core timer will be reloaded with the contents of the auxiliary timer on every second overflow or underflow Using this single transition mode for both auxiliary timers allows to perform very flexible pulse width modulation PWM One of the auxiliary timers is programmed to reload the core timer on a positive transition of T3OTL the other is programmed for a reload on a negative transition of T3OTL With this combination the core timer is alternately reloaded from the two auxiliary timers Figure 10 13 shows an example for the generation of a PWM signal using the alternate reload mechanism T2 defines the high time of the PWM signal reloaded on positive transitions and T4 defines the low time of the PWM signal reloaded on negative transitions The PWM signal can be output on TSOUT with T3OE 1 port latch 1 and direction bit 1 With this method the high and low time of the PWM signal can be varied in a wide range Note T
84. T6OUT P3 0 TOIN General Purpose Input Output MCA04426 Figure 7 14 Port310 and Alternate Functions The port structure of the Port3 pins depends on their alternate function see Figure 7 15 When the on chip peripheral associated with a Port 3 pin is configured to use the alternate input function it reads the input latch which represents the state of the pin via the line labeled Alternate Data Input Port 3 pins with alternate input functions are TOIN T2IN T3IN T4IN T3EUD and CAPIN When the on chip peripheral associated with a Port 3 pin is configured to use the alternate output function its Alternate Data Output line is ANDed with the port output latch line When using these alternate functions the user must set the direction of the port line to output DP3 y 1 and must set the port output latch P3 y 1 Otherwise the pin is in its high impedance state when configured as input or the pin is stuck at 0 when the port output latch is cleared When the alternate output functions are not used the Alternate Data Output line is in its inactive state which is a high level 1 Port 3 pins with alternate output functions are T6OUT T3OUT TxDO and CLKOUT FOUT When the on chip peripheral associated with a Port 3 pin is configured to use both the alternate input and output function the descriptions above apply to the respective current operating mode The direction must be set accordingly
85. The EXTP extend page instruction allows switching to an arbitrary data page for 1 4 instructions without having to change the current DPPs EXTP R15 1 The override page number is stored in R15 MOV RO R14 The 14 bit page offset is stored in R14 MOV R1 R13 Ihis instruction uses the std DPP scheme The EXTS extend segment instruction allows switching to a 64 KByte segment oriented data access scheme for 1 4 instructions without having to change the current DPPs In this case all 16 bits of the operand address are used as segment offset with the segment taken from the EXTS instruction This greatly simplifies address calculation with continuous data like huge arrays in C EXTS 15 1 The override seg is 15 0F 0000H 0F FFFFH MOV RO R14 The 16 bit segment offset is stored in R14 MOV R1 R13 Ihis instruction uses the std DPP scheme Note Instructions EXTP and EXTS inhibit interrupts the same way as ATOMIC As long as any Class B trap is pending any of the class B trap flags in register TFR is set the EXTend instructions will not work Clear the respective B trap flag at the beginning of a B trap routine if EXT shall be used within the routine Short Addressing in the Extended SFR ESFR Space The short addressing modes of the C167CS REG or BITOFF implicitly access the SFR space The additional ESFR space would have to be accessed via long addressing modes MEM or Rw The
86. This provides a maximum of security Note Of course all these registers may be read at any time without restrictions The unlock sequence is executed by writing defined values to bitfield SYSRLS using defined instructions see Table 21 6 The instructions of the unlock sequence including the intended write access must be secured with an EXTR instruction switch to ESFR space and lock interrupts Note The unlock sequence is aborted if the locked range EXTR does not cover the complete sequence The unlock sequence provides no write access to register SYSCON Table 21 6 Unlock Sequence for Secured Registers Step SYSRLS Instruction Notes 00005 Status before release sequence 1 1001 BFLDL OR ORB Read Modify Write access XOR XORB 2 0011 5 MOV MOVB MOVBS Write access MOVBZ 3 0111 BSET BMOV2 BMOVN2 Read Modify Write access BOR BXOR bit instruction 4 Single read modify write access to SYSCON1 SYSCON2 or SYSCONS 0000p Status after release sequence 1 SYSRLS must be set to 0000s before the first step if any OR command is used 2 Usually byte accesses should not be used for special function registers 3 SYSRLS is cleared by hardware if unlock sequence and write access were successful SYSRLS shows the last value written otherwise User s Manual 21 22 V2 0 2000 07 C167CS Derivatives technologies Power Management The following
87. Time fg ADCTC Basic Clock fpc ADSTC 00 fcpu 4 00 tac x 8 01 fopu 2 01 fgc x 16 10 fcpu 16 10 tac x 32 11 fopu 8 11 tac x 64 User s Manual 18 13 V2 0 2000 07 oe nfineon e technologies Derivatives The Analog Digital Converter The time for a complete conversion includes the sample time fs the conversion itself and the time required to transfer the digital value to the result register 2 tcpy as shown in the example below Note The non linear decoding of bit field ADCTC provides compatibility with 80C166 designs for the default value 00 after reset Converter Timing Example Assumptions Jopu 25 MHz i e tcpy 40 ns ADCTC 00 ADSTC 00 Basic clock fac fcpy 4 6 25 MHz i e tag 160 ns Sample time ts tgc X8 1280 ns Conversion time f ts 40 tgc 2 tcpy 1280 6400 80 ns 7 76 us Note For the exact specification please refer to the data sheet of the selected derivative Users Manual 18 14 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter 18 3 A D Converter Interrupt Control At the end of each conversion interrupt request flag ADCIR in interrupt control register ADCIC is set This end of conversion interrupt request may cause an interrupt to vector ADCINT or it may trigger a PEC data transfer which reads the conversion result from register ADDAT e g to store it into a table in the internal RAM for later evalua
88. TxIC will be set This will cause an interrupt to the respective timer interrupt vector T2INT T3INT or T4INT or trigger a PEC service if the respective interrupt enable bit T2IE T3IE or T4IE in register TxIC is set There is an interrupt control register for each of the three timers T21C Timer 2 Intr Ctrl Reg SFR FF60 B0 Reset Value 00 15 14 13 12 11 10 9 8 7 6 3 2 1 0 T2IR T2IE ILVL GLVL wh rw rw rw T3IC Timer 3 Intr Ctrl Reg SFR FF62 B1 Reset Value 00 15 14 13 12 11 10 9 8 7 6 3 2 1 0 T3IR T3IE ILVL GLVL rwh rw rw rw TAIC Timer 4 Intr Ctrl Reg SFR FF64 B2 Reset Value 00 15 14 13 12 11 10 9 8 7 6 3 2 1 0 TAIR T4IE ILVL GLVL rwh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 10 21 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units 10 2 Timer Block GPT2 From a programmer s point of view the GPT2 block is represented by a set of SFRs as summarized below Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Fu
89. When the bootstrap loader mode is entered via an internal reset EA 1 the default configuration selects the prescaler for clock generation In this case the bootstrap loader will begin to operate with fcopy fosc 2 which will limit the maximum bauarate for ASCO at low input frequencies intended for PLL operation Higher levels of the bootstrapping sequence can then switch the clock generation mode via register RSTCON e g to PLL in order to achieve higher bauarates for the download User s Manual 15 8 V2 0 2000 07 C167CS Derivatives technologies The Capture Compare Units 16 The Capture Compare Units The C167CS provides two almost identical Capture Compare CAPCOM units which only differ in the way they are connected to the C167CS s IO pins They provide 32 channels which interact with 4 timers The CAPCOM units can capture the contents of a timer on specific internal or external events or they can compare a timer s content with given values and modify output signals in case of a match With this mechanism they support generation and control of timing sequences on up to 16 channels per unit with a minimum of software intervention Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions TO1CON TOIC T1IC T78CON T7IC T8IC CCOIC 3IC CCAIC 71C CC8IC 111C CC121C 151C CC161C 19IC CC201C 231C CC24IC 271C CC28IC 311C CCOIO P2 0 CC1510 P2 15 CC161O
90. X CAN 1 Lower Arbitration Register msg n UUUU C1MCFGn EFn6y X CAN1 Message Configuration Register UU msg n XPERCON F0244 124 X Peripheral Control Register 04014 PTO F030 E 184 PWM Module Up Down Counter 0 0000 PT1 F0324 E 19 PWM Module Up Down Counter 1 00004 PT2 F0344 E 1Ay PWM Module Up Down Counter 2 00004 PT3 FO36 E 1B4 PWM Module Up Down Counter 3 00004 PPO F0384 E 1C PWM Module Period Register 0 00004 PP1 FO3A E 1D PWM Module Period Register 1 0000 PP2 FOSC E 1E PWM Module Period Register 2 0000 PP3 FOSE E 1F4 PWM Module Period Register 3 0000 T7 F050 E 284 CAPCOM Timer 7 Register 0000 T8 F052 E 294 CAPCOM Timer 8 Register 0000 T7REL F054 E 2Ay CAPCOM Timer 7 Reload Register 0000 T8REL FO564 E 2B4 CAPCOM Timer 8 Reload Register 0000 IDMEM2 F076 E 3B _ Identifier 50014 IDPROG F078 E 3C Identifier 4040 IDMEM F07A E 3D Identifier 30404 IDCHIP FO7C E 3Ey4 Identifier OCxxy IDMANUF FO7E E 3Fy Identifier 18204 POCONOL F080 E 404 Port POL Output Control Register 00004 POCONOH F082 E 41 Port POH Output Control Register 0000 POCON1L F084 E 424 Port P1L Output Control Register 0000 POCON1H F086 E 434 Port P1H Output Control Register 00004 POCON2 F088 E 444 Port P2 Output Control Register 00004 POCON3 FO8A E 454 Port P3 Output Control Register 0000 POCON4 FO8C E 464 Port P4 Output Control Register 0000 POCON6 FO8E E 4
91. a DPP1PN rw DPP2 Data Page Pointer 2 SFR FE04 02 Reset Value 0002 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPP2PN rw DPP3 Data Page Pointer 3 SFR FE06 03 Reset Value 00034 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s DPP3PN User s Manual V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU Bit Function DPPxPN Data Page Number of DPPx Specifies the data page selected via DPPx Only the least significant two bits of DPPx are significant when segmentation is disabled The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16 bit addressing modes except for override accesses via EXTended instructions and PEC data transfers After reset the Data Page Pointers are initialized in a way that all indirect or direct long 16 bit addresses result in identical 18 bit addresses This allows to access data pages 3 0 within segment 0 as shown in Figure 4 6 If the user does not want to use any data paging no further action is required Data paging is performed by concatenating the lower 14 bits of an indirect or direct long 16 bit address with the contents of the DPP register selected by the upper two bits of the 16 bit address The contents of the selected DPP register specify one of the 1024 possible data pages This data page base
92. address together with the 14 bit page offset forms the physical 24 bit address selectable part is driven to the address pins In case of non segmented memory mode only the two least significant bits of the implicitly selected DPP register are used to generate the physical address Thus extreme care should be taken when changing the content of a DPP register if a non segmented memory model is selected because otherwise unexpected results could occur In case of the segmented memory mode the selected number of segment address bits via bitfield SALSEL of the respective DPP register is output on the respective segment address pins of Port 4 for all external data accesses A DPP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a new DPP value is not yet usable for the operand address calculation of the instruction immediately following the instruction updating the DPP register User s Manual 4 23 V2 0 2000 07 C167CS Derivatives technologies The Central Processing Unit CPU 16 Bit Data Address 15 14 0 J a Pd DPP Registers 4 DPP3 11 14 Bit Intra Page Address DERE 0 concatenated with DPP1 01 content of DPPx DPP0 00 Affer reset or with segmentation disabled the DPP registers select data pages 3 0 All of the internal memory is accessible in these cases MCA02264 Figure 4 6 Addressing via the Data Pa
93. after the falling edge of ALE on a multiplexed bus will be prolonged by half a CPU clock so the data transfer within a bus cycle refers to the same CLKOUT edges as usual i e the data transfer is delayed by one CPU clock This allows more time for the address to be latched Note ALECTLO is 1 after reset to select the slowest possible bus cycle the other ALECTLx are 0 after reset Normal Multiplexed Lengthened Multiplexed Bus Cycle En Bus Cycle segment Address Address P4 ALE N N lt lt a Setup Hold wus po CCO ERE NND NC EC 7 BUS Py Mis MCD02235 Figure 9 6 ALE Length Control User s Manual 9 13 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Programmable Memory Cycle Time The C167CS allows the user to adjust the controller s external bus cycles to the access time of the respective memory or peripheral This access time is the total time required to move the data to the destination It represents the period of time during which the controller s signals do not change e Bus Cycle Segment X Addess X MCTC Wait States 1 15 MCT02063 Figure 9 7 Memory Cycle Time The external bus cycles of the C167CS can be extended for a memory or peripheral which cannot keep pace with the controllers maximum speed by in
94. an Undefined Opcode trap class B occurs simultaneously with an NMI trap class A both the NMI and the UNDOPC flag is set the IP of the instruction with the undefined opcode is pushed onto the system stack but the NMI trap is executed After return from the NMI service routine the IP is popped from the stack and immediately pushed again because of the pending UNDOPC trap User s Manual 5 33 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions External NMI Trap Whenever a high to low transition on the dedicated external NMI pin Non Maskable Interrupt is detected the NMI flag in register TFR is set and the CPU will enter the NMI trap routine The IP value pushed on the system stack is the address of the instruction following the one after which normal processing was interrupted by the NMI trap Note The NMI pin is sampled with every CPU clock cycle to detect transitions Stack Overflow Trap Whenever the stack pointer is decremented to a value which is less than the value in the stack overflow register STKOV the STKOF flag in register TFR is set and the CPU will enter the stack overflow trap routine Which IP value will be pushed onto the system stack depends on which operation caused the decrement of the SP When an implicit decrement of the SP is made through a PUSH or CALL instruction or upon interrupt or trap entry the IP value pushed is the address of the following instruction When the SP
95. and CC16 CC23 110 Compare Mode 2 Interrupt Only Only one interrupt per timer period 1 1 1 Compare Mode 3 Set Output Pin on each Match Reset output pin on each timer overflow Only one interrupt per timer period The detailed discussion of the capture and compare modes is valid for all the capture compare channels so registers bits and pins are only referenced by the placeholder x Note A capture or compare event on channel 31 may be used to trigger a channel injection on the C167CS s A D converter if enabled User s Manual 16 12 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units 16 4 Capture Mode In response to an external event the content of the associated timer TO T1 or T7 T8 depending on the used CAPCOM unit and the state of the allocation control bit ACCx is latched into the respective capture register CCx The external event causing a capture can be programmed to be either a positive a negative or both a positive or a negative transition at the respective external input pin CCxlO The triggering transition is selected by the mode bits CCMODx in the respective CAPCOM mode control register In any case the event causing a capture will also set the respective interrupt request flag CCxIR which can cause an interrupt or a PEC service request when enabled Edge Select Capture Reg CCx Interrupt gt Request CCMODx Input Interrup
96. and shifts the incoming data frame into the receive shift register When the last stop bit has been received the content of the receive shift register is transferred to the receive data buffer register SORBUF Simultaneously the receive interrupt request flag SORIR is set after the 9th sample in the last stop bit time slot as programmed regardless whether valid stop bits have been received or not The receive circuit then waits for the next start bit 1 to 0 transition at the receive data input pin The receiver input pin RXDO must be configured for input i e the respective direction latch must be 0 Asynchronous reception is stopped by clearing bit SOREN A currently received frame is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Start bits that follow this frame will not be recognized Note In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive interrupt request will be activated and no data will be transferred User s Manual 11 7 V2 0 2000 07 o Infineon technologies C167CS Derivatives The Asynchronous Synchronous Serial Interface 11 2 Synchronous Operation Synchronous mode supports half duplex communication basically for simple IO expansion via shift registers Data is transmitted and received via pin RXDO while pin TXDO outputs
97. automatically like SSCEIR but rather must be cleared by software after servicing This allows servicing of some error conditions via interrupt while the others may be polled by software Note The error interrupt handler must clear the associated enabled errorflag s to prevent repeated interrupt requests A Receive Error Master or Slave mode is detected when a new data frame is completely received but the previous data was not read out of the receive buffer register SSCRB This condition sets the error flag SSCRE and when enabled via SSCREN the error interrupt request flag SSCEIR The old data in the receive buffer SSCRB will be overwritten with the new value and is unretrievably lost A Phase Error Master or Slave mode is detected when the incoming data at pin MRST master mode or MTSR slave mode sampled with the same frequency as the CPU clock changes between one sample before and two samples after the latching edge of the clock signal see Clock Control This condition sets the error flag SSCPE and when enabled via SSCPEN the error interrupt request flag SSCEIR A Baud Rate Error Slave mode is detected when the incoming clock signal deviates from the programmed baud rate by more than 100 i e it either is more than double or less than half the expected baud rate This condition sets the error flag SSCBE and when enabled via SSCBEN the error interrupt request flag SSCEIR Using this error detection capability requ
98. branched to Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector had occurred PSW CSP in segmentation mode and IP are pushed on the internal system stack and a jump is taken to the specified vector location When segmentation is enabled and a trap is executed the CSP for the trap service routine is set to code segment 0 No Interrupt Request flags are affected by the TRAP instruction The interrupt service routine called by a TRAP instruction must be terminated with a RETI return from interrupt instruction to ensure correct operation Note The CPU level in register PSW is not modified by the TRAP instruction so the service routine is executed on the same priority level from which it was invoked Therefore the service routine entered by the TRAP instruction can be interrupted by other traps or higher priority interrupts other than when triggered by a hardware trap Hardware Traps Hardware traps are issued by faults or specific system states that occur during runtime of a program not identified at assembly time A hardware trap may also be triggered intentionally e g to emulate additional instructions by generating an Illegal Opcode trap The C167CS distinguishes eight different hardware trap functions When a hardware trap condition has been detected the CPU branches to the trap vector location for the respective trap condition Depending on the trap condition the instruction which caused the
99. complete error etc For interfacing with external hardware specific pins of the parallel ports are used when an input or output function has been selected for a peripheral During this time the port pins are controlled by the peripheral when used as outputs or by the external hardware which controls the peripheral when used as inputs This is called the alternate input or output function of a port pin in contrast to its function as a general purpose lO pin User s Manual 2 11 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview Peripheral Timing Internal operation of CPU and peripherals is based on the CPU clock f py The on chip oscillator derives the CPU clock from the crystal or from the external clock signal The clock signal which is gated to the peripherals is independent from the clock signal which feeds the CPU During Idle mode the CPU s clock is stopped while the peripherals continue their operation Peripheral SFRs may be accessed by the CPU once per state When an SFR is written to by software in the same state where it is also to be modified by the peripheral the software write operation has priority Further details on peripheral timing are included in the specific sections about each peripheral Programming Hints Access to SFRs All SFRs reside in data page 3 of the memory space The following addressing mechanisms allow to access the SFRs Indirect or direct addressin
100. continuous or auto scan mode without changing the current operating mode After the conversion of this specific channel the ADC continues with the original operating mode Channel Injection mode is enabled by setting bit ADCIN in register ADCON and requires the Wait for ADDAT Read Mode ADWR 1 The channel to be converted in this mode is specified in bitfields CHNR and CHX of register ADDAT2 Note Bitfields CHNR and CHX in ADDAT2 are not modified by the A D converter but only the ADRES bit field Since the channel number for an injected conversion is not buffered bitfields CHNR CHX of ADDAT2 must never be modified during the sample phase of an injected conversion otherwise the input multiplexer will switch to the new channel It is recommended to only change the channel number with no injected conversion running Lab x1 x 2 x 3 x 4 Conversion of Channel v Write ADDAT x 1 X x 1 x 2 x 3 x 4 ADDAT Ful EL El psg pg qug p Read ADDAT x 1 X x 1 x 2 x 3 x 4 Injected Channel Injection Conversion Request of Channel y Write ADDAT2 ADDAT2 Full Int Request ADEINT Read ADDAT2 MCA01971 Figure 18 5 Channel Injection Example User s Manual 18 9 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter A Channel Injection can be Triggered in Two Ways setting of the Channel Injection Request bit ADCRQ via software a comp
101. counting pulse width and duty cycle measurements pulse generation or pulse multiplication The five 16 bit timers are organized in two separate modules GPT1 and GPT2 Each timer in each module may operate independently in a number of different modes or may be concatenated with another timer of the same module Each timer can be configured individually for one of four basic modes of operation which are Timer Gated Timer Counter Mode and Incremental Interface Mode GPT 1 timers In Timer Mode the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler while Counter Mode allows a timer to be clocked in reference to external events via TxIN Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on its external input pin TxIN In Incremental Interface Mode the GPT1 timers can be directly connected to the incremental position sensor signals A and B via the respective inputs TxIN and TxEUD Direction and count signals are internally derived from these two input signals so the contents of timer Tx corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input The count direction up down for each timer is programmable by software or may additionally be altered dynamically by an external signal TxEUD to facilitate e g position tracking The core timers T3 and T6 ha
102. current CPU priority and the interrupt system is globally enabled After the PEC data transfer has been completed the CPU remains in Idle mode Otherwise if the PEC request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU does not remain in Idle mode but continues program execution with the instruction following the IDLE instruction User s Manual 21 3 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management Denied CPU Interrupt Request Accepted Active IDLE Instruction Idle Mode Mode Denied PEC Request Executed PEC Request MCA04407 Figure 21 2 Transitions between Idle Mode and Active Mode Idle mode can also be terminated by a Non Maskable Interrupt i e a high to low transition on the NMI pin After Idle mode has been terminated by an interrupt or NMI request the interrupt system performs a round of prioritization to determine the highest priority request In the case of an NMI request the NMI trap will always be entered Any interrupt request whose individual Interrupt Enable flag was set before Idle mode was entered will terminate Idle mode regardless of the current CPU priority The CPU will not go back into Idle mode when a CPU interrupt request is detected even when the interrupt was not serviced because of a higher CPU priority or a globally disabled interrupt system IEN 0 The CPU will only go back into Idle mode w
103. cycle 4 Data drivers are disabled in a multiplexed normal write cycle 4 Early Write ma KOX MCT04005 Figure 9 9 User s Manual 9 17 Read Write Signal Duration Control V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 4 READY Controlled Bus Cycles For situations where the programmable waitstates are not enough or where the response access time of a peripheral is not constant the C167CS provides external bus cycles that are terminated via a READY input signal synchronous or asynchronous In this case the C167CS first inserts a programmable number of waitstates 0 7 and then monitors the READY line to determine the actual end of the current bus cycle The external device drives READY low in order to indicate that data have been latched write cycle or are available read cycle Bus Cycle Bus Cycle with active READY extended via READY 1 WS 2 WS 1 WS 2 WS AE f SREADY Y aia AREADY Y 7 ala MCD02237 A Evaluation sampling of the READY input Figure 9 10 READY Controlled Bus Cycles The READY function is enabled via the RDYENXx bits in the BUSCON registers When this function is selected RDYENx 1 only the lower 3 bits of the respective MCTC bit field define the number of inserted waitstates 0 7 while t
104. date material Note As the architecture and the basic features i e CPU core and built in peripherals are identical for most of the currently offered versions of the C167CS the descriptions within this manual that refer to the C167CS also apply to the other variations unless otherwise noted User s Manual 1 3 V2 0 2000 07 o nfineon oi technologies Derivatives Introduction 1 2 Summary of Basic Features The C167CS is an improved representative of the Infineon family of full featured 16 bit single chip CMOS microcontrollers It combines high CPU performance up to 12 5 16 5 million instructions per second with high peripheral functionality and means for power reduction Several key features contribute to the high performance of the C167CS the indicated timings refer to a CPU clock of 25 33 MHz High Performance 16 bit CPU with Four Stage Pipeline e 80 60 ns minimum instruction cycle time with most instructions executed in 1 cycle e 400 300 ns multiplication 16 bit x 16 bit 800 600 ns division 32 bit 16 bit Multiple high bandwidth internal data buses Register based design with multiple variable register banks Single cycle context switching support 16 MBytes linear address space for code and data Von Neumann architecture System stack cache support with automatic stack overflow underflow detection Control Oriented Instruction Set with High Efficiency Bit byte and word data types Flex
105. delay and the output driver delay rounded up to the nearest multiple of ty To fulfill the requirements of the CAN specification the following conditions must be met TSeq2 gt lTSeg2 fsuw gt Irgegi Z 9 X fq gt lTSeg1 fsuw gt 2x ty Information Processing Time Prop Note In order to achieve correct operation according to the CAN protocol the total bit time should be at least 8 tg ie TSEG1 TSEG22 5 So to operate with a baudrate of 1 MBit sec the XCLK frequency has to be at least 8 16 MHz depending on the prescaler control bit CPS in register CSR The maximum tolerance df for XCLK depends on the Phase Buffer Segment 1 PB1 the Phase Buffer Segment 2 PB2 and the Resynchronization Jump Width SJW min PB1 PB2 d lt 25x 3xbittime PB2 AND fsJw d lt 30x bit time The examples below show how the bit timing is to be calculated under specific circumstances Users Manual 19 14 V2 0 2000 07 o nfineon n technologies Derivatives The On Chip CAN Interface Bit Timing Example for High Baudrate This example makes the following assumptions XCLK frequency 20 MHz BRP 00 CPS 0 Baudrate 1 Mbit sec t 100 ns 2x xCLK bus driver delay 50 ns receiver circuit delay 30 ns bus line 40 m delay 220 ns TSuw 100ns 1x t TSeg1 700 nS Prop fsJw l l tTSeg2 200ns Information Processing Time Bit 1000 nS sync frSegt frSeg2 E min PB1 PB2 2x 13 x bit ti
106. depending on its source Table 13 2 summarizes the possible combinations Table 13 2 Reset Indication Flag Combinations Event Reset Indication Flags LHWR SHWR SWR WDTR Long Hardware Reset 1 1 1 0 Short Hardware Reset 1 1 0 Software Reset 1 Watchdog Timer Reset 1 1 EINIT instruction 0 0 0 SRVWDT instruction 0 1 Description of table entries 1 flag is set 0 flag is cleared flag is not affected flag is set in bidirectional reset mode not affected otherwise Long Hardware Reset is indicated when the RSTIN input is still sampled low active at the end of a hardware triggered internal reset sequence Short Hardware Reset is indicated when the RSTIN input is sampled high inactive at the end of a hardware triggered internal reset sequence Software Reset is indicated after a reset triggered by the excution of instruction SRST Watchdog Timer Reset is indicated after a reset triggered by an overflow of the watchdog timer Note When bidirectional reset is enabled the RSTIN pin is pulled low for the duration of the internal reset sequence upon any sort of reset Therefore always a long hardware reset LHWR will be recognized in any case User s Manual 13 6 V2 0 2000 07 o nfineon e technologies Derivatives The Real Time Clock 14 The Real Time Clock The Real Time Clock RTC module of the C167CS basically
107. driven to the port pin The descriptions below refer to the standard case after reset i e direct driving User s Manual 17 2 V2 0 2000 07 o nfineon nd technologies Derivatives The Pulse Width Modulation Module Mode 0 Standard PWM Generation Edge Aligned PWM Mode 0 is selected by clearing the respective bit PMx in register PWMCON1 to 0 In this mode the timer PTx of the respective PWM channel is always counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is reset to 0000 and continues counting up with subsequent count pulses The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is reset to 0000 i e below the pulse width shadow register The period of the resulting PWM signal is determined by the value of the respective PPx shadow register plus 1 counted in units of the timer resolution PWM Periodyogeo PPx 1 The duty cycle of the PWM output signal is controlled by the value in the respective pulse width shadow register This mechanism allows the selection of duty cycles from 0 to 100 including the boundaries For a value of 0000 the output will remain at a high level representing a duty cycle of 10095 For a value higher than the value in the period register the output will remain a
108. e Non segmented mode 64 KByte with A15 AO on PORTO or PORT 1 2 bit segmented mode 256 KByte with A17 A16 on Port 4 and A15 A0 on PORTO or PORTI1 4 bit segmented mode 1 MByte with A19 A16 on Port 4 and A15 A0 on PORTO or PORT1 8 bit segmented mode 16 MByte with A22 A16 on Port 4 and A15 A0 on PORTO or PORT1 Each bank can be directly addressed via the address bus while the programmable chip select signals can be used to select various memory banks The C167CS also supports four different bus types Multiplexed 16 bit Bus with address and data on PORTO Default after Reset Multiplexed 8 bit Bus with address and data on PORTO POL Demultiplexed 16 bit Bus with address on PORT1 and data on PORTO e Demultiplexed 8 bit Bus with address on PORT1 and data on POL Memory model and bus mode are selected during reset by pin EA and PORTO pins For further details about the external bus configuration and control please refer to Chapter 9 External word and byte data can only be accessed via indirect or long 16 bit addressing modes using one of the four DPP registers There is no short addressing mode for external operands Any word data access is made to an even byte address For PEC data transfers the external memory in segment 0 can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The external memory is not provided for single bit storage and therefore i
109. every second overflow underflow of the core timer T6 This configuration forms a 33 bit timer 16 bit core timer T6OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T6 can operate in timer gated timer or counter mode in this case Tyl fopu Core Timer Ty TyOTL fj TyOUT TyR Up Down Interrupt Request Edge Select Interrupt pe Auxiliary Timer Tx Request TxR Txl Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL MCB02034 T6OUT P3 1 x 5 y 6 n 2 9 Figure 10 21 Concatenation of Core Timer T6 and Auxiliary Timer T5 User s Manual 10 33 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units GPT2 Capture Reload Register CAPREL in Capture Mode This 16 bit register can be used as a capture register for the auxiliary timer T5 This mode is selected by setting bit T5SC 1 in control register T5CON Bit CT3 selects the external input pin CAPIN or the input pins of timer T3 as the source for a capture trigger Either a positive a negative or both a positive and a negative transition at pin CAPIN can be selected to trigger the capture function or transitions on input T3IN or input T3EUD or both inputs T3IN and T3EUD The active edge is controlled by bit field Cl in r
110. fixed access time and peripherals operating with READY may be grouped into the same address window The external waitstate control logic in this case would activate READY either upon the memory s chip select or with the peripheral s READY output After the predefined number of waitstates the C167CS will check its READY line to determine the end of the bus cycle For a memory access it will be low already see example a in Figure 9 10 for a peripheral access it may be delayed see example b in Figure 9 10 As memories tend to be faster than peripherals there should be no impact on system performance When using the READY function with so called normally ready peripherals it may lead to erroneous bus cycles if the READY line is sampled too early These peripherals pull their READY output low while they are idle When they are accessed they deactivate READY until the bus cycle is complete then drive it low again If however the peripheral deactivates READY after the first sample point of the C167CS the controller samples an active READY and terminates the current bus cycle which of course is too early By inserting predefined waitstates the first READY sample point can be shifted to a time where the peripheral has safely controlled the READY line e g after 2 waitstates in Figure 9 10 User s Manual 9 19 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9
111. following codes are defined 55g 8xC166 A5 Previous versions of the C167 obsolete B5 Previous versions of the C165 C5 C167 derivatives D5 4 All devices equipped with identification registers Note The identification byte D5 does not directly identify a specific derivative This information can in this case be obtained from the identification registers When the C167CS has entered BSL mode the following configuration is automatically set values that deviate from the normal reset values are marked Watchdog Timer Disabled Register STKUN FCOO Context Pointer CP FA00 Register STKOV F600 Stack Pointer SP FA40 Register BUSCONO acc to startup config Register SOCON 8011 P3 10 TXDO d Register SOBG acc to 00 byte DP3 10 d Other than after a normal reset the watchdog timer is disabled so the bootstrap loading sequence is not time limited Pin TxDO is configured as output so the C167CS can return the identification byte Note Even if the internal ROM OTP Flash is enabled no code can be executed out of it while the C167CS is in BSL mode 1 The external host should not send the zero byte before the end of the BSL initialization time see Figure 15 1 to make sure that it is correctly received User s Manual 15 3 V2 0 2000 07 o nfineon technologies C167CS Derivatives Memory Configuration after Reset The Bootstrap Loader The configuration i e the accessibility of the C
112. for Read Control ADCIN ADC Channel Injection Enable ADCRQ ADC Channel Injection Request Flag ADSTC ADC Sample Time Control Defines the ADC sample time in a certain range 00 fpc X 8 01 tBc X 16 10 pc X 32 11 tBc X 64 ADCTC ADC Conversion Time Control Defines the ADC basic conversion clock fpc 00 feo fcpu 4 01 feo Sopu 2 10 fac fcopu 16 11 fac fcpu 8 LI The two groups of channels are handled independently Standard channels AN15 ANO are selected with ADCH Fy O4 and ADX 0 extension channels AN23 AN16 are selected with ADCH 7 04 and ADX 1 2 Bit ADX is available only after the execution of instruction EINIT Before EINIT bit ADCON 6 controls production testmodes and must remain cleared Bitfields ADCH and ADX specify the analog input channel which is to be converted first channel of a conversion sequence in auto scan modes Bitfield ADM selects the operating mode of the A D converter A conversion or a sequence is then started by setting bit ADST Clearing ADST stops the A D converter after a certain operation which depends on the selected operating mode The busy flag read only ADBSY is set as long as a conversion is in progress The result of a conversion is stored in the result register ADDAT or in register ADDAT2 for an injected conversion Note Bitfields CHNR and CHX of register ADDAT are loaded by the ADC to indicate which channel the result refers
113. group priority 2 level 13 group priority 2 0001 11 CPU interrupt CPU interrupt level 1 group priority 3 level 1 group priority 3 0001 00 CPU interrupt CPU interrupt level 1 group priority O level 1 group priority O 0000 XX No service No service Note All requests on levels 13 1 cannot initiate PEC transfers They are always serviced by an interrupt service routine No PECC register is associated and no COUNT field is checked User s Manual 5 9 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions Interrupt Control Functions in the PSW The Processor Status Word PSW is functionally divided into 2 parts the lower byte of the PSW basically represents the arithmetic status of the CPU the upper byte of the PSW controls the interrupt system of the C167CS and the arbitration mechanism for the external bus interface Note Pipeline effects have to be considered when enabling disabling interrupt requests via modifications of register PSW see Chapter 4 PSW Processor Status Word SFR FF10 884 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HLD USR MUL rw rw rw rw rwh rwh rwh rwh rwh rwh Bit Function N C V Z E CPU status flags Described in Chapter 4 MULIP USRO Define the current status of the CPU ALU multiplication unit HLDEN HOLD Enable Enables External Bus A
114. here reside on the same or on separate devices User s Manual 19 38 V2 0 2000 07 technologies C167CS Derivatives The On Chip CAN Interface CAN CAN1_TXD Transceiver Physical Layer CAN Bus A C167CS CAN CAN2_TXD Transceiver CAN2_RXD CAN Bus B Physical Layer MCA04474 Figure 19 12 Connection to Separate CAN Buses CAN_RXD CAN Transceiver CAN Bus CAN_TXD Physical Layer MCA04475 Figure 19 13 Connection to a Single CAN Bus User s Manual 19 39 V2 0 2000 07 E 5 nfineon technologies Port Control C167CS Derivatives The On Chip CAN Interface The receive data line and the transmit data line of the CAN module are alternate port functions Make sure that the respective port pin for the receive line is switched to input in order to enable proper reception The respective port driver for the transmit will automatically be switched ON This provides a standard pin configuration without additional software control and also works in emulation mode where the port direction registers cannot be controlled The receive and transmit line of the CAN module may be assigned to several port pins of the C167CS under software control This assignment is selected via bitfield IPC Interface Port Connection in register PCIR Table 19 5 Assignment of CAN Interface Lines to Port Pins IPC CAN RXD C
115. high because the EBC switches to an internal XCS signal The external control signals RD and WR or WRL WRH if enabled remain inactive high Table 9 7 Status of the External Bus Interface During EBC Idle State Pins Internal accesses only XBUS accesses PORTO Tristated floating Tristated floating for read accesses XBUS write data for write accesses PORT1 Last used external address Last used XBUS address if used for the bus interface if used for the bus interface Port 4 Last used external segment address Last used XBUS segment address on selected pins on selected pins Port 6 Active external CS signal Inactive high for selected CS corresponding to last used address signals BHE Level corresponding to last external Level corresponding to last XBUS access access ALE Inactive low Pulses as defined for X Peripheral RD Inactive high Inactive high WR WRL Inactive high Inactive high WRH Inactive high Inactive high 1 Used and driven in visible mode User s Manual 9 30 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 7 External Bus Arbitration In embedded systems it may be efficient to share external resources like memory banks or peripheral devices among more than one microcontroller or processor The C167CS supports this approach with the possibility to arbitrate the access to its external bus i e to the external resourc
116. internal CPU clock or may be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range of variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition external count inputs for CAPCOM timers TO and T7 allow event scheduling for the capture compare registers relative to external events Both of the two capture compare register arrays contain 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer TO or T1 T7 or T8 respectively and programmed for capture or compare function Each register has one port pin associated with it which serves as an input pin for triggering the capture function or as an output pin to indicate the occurrence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers
117. internal instruction pipeline a new CP value is not yet usable for GPR address calculations of the instruction immediately following the instruction updating the CP register The Switch Context instruction SCXT allows to save the content of register CP on the stack and updating it with a new value in just one machine cycle User s Manual 4 25 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU Internal RAM EN a CP 30 CP 28 2 2 2 2 MISJA Context Pointer Z D PISIS N MCD02003 Figure 4 7 Register Bank Selection via Register CP Several addressing modes use register CP implicitly for address calculations The addressing modes mentioned below are described in Chapter 24 Short 4 Bit GPR Addresses mnemonic Rw or Rb specify an address relative to the memory location specified by the contents of the CP register i e the base of the current register bank Depending on whether a relative word Rw or byte Rb GPR address is specified the short 4 bit GPR address is either multiplied by two or not before it is added to the content of register CP see Figure 4 8 Thus both byte and word GPR accesses are possible in this way GPRs used as indirect address pointers are always accessed wordwise For some instructions only the first four GPRs can be used as indirect address pointers These GPRs are specified via short 2 bit GPR addresses Th
118. interrupt request will be activated and no data will be transferred This feature may be used to control communication in multi processor system When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the additional 9th bit is a 1 for an address byte and a 0 fora data byte so no slave will be interrupted by a data byte An address byte will interrupt all slaves operating in 8 bit data wake up bit mode so each slave can examine the 8 LSBs of the received character the address The addressed slave will switch to 9 bit data mode e g by clearing bit SOM O which enables it to also receive the data bytes that will be coming having the wake up bit cleared The slaves that were not being addressed remain in 8 bit data wake up bit mode ignoring the following data bytes 1st 2nd Stop Stop Bit Bit e Data Bit D8 e Parity e Wake up Bit MCT04378 Figure 11 4 Asynchronous 9 bit Data Frames User s Manual 11 6 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface Asynchronous transmission begins at the next overflow of the divide by 16 counter see Figure 11 4 provided that SOR is set and data has been loaded into SOTBUF The transmitted data frame consists of three basic el
119. interrupt requests have been serviced or until interrupt generation is disabled CSR IE 0 Note The interrupt node is activated only upon a 0 1 transition of the CAN interrupt signal The CAN interrupt service routine should only be left after INTID has been verified to be 00 4 The interrupt with the lowest number has the highest priority If a higher priority interrupt lower number occurs before the current interrupt is processed INTID is updated and the new interrupt overrides the last one INTID is also updated when the respective source request has been processed This is indicated by clearing the INTPND flag in the respective object s message control register MCRn or by reading the status partition of register CSR in case of a status change interrupt The updating of INTID is done by the CAN state machine and takes up to 6 CAN clock cycles 1 CAN clock cycle 1 or 2 CPU clock cycles determined by the prescaler bit CPS depending on current state of the state machine Note A worst case condition can occur when BRP 00 AND the CAN controller is storing a just received message AND the CPU is executing consecutive accesses to the CAN module In this rare case the maximum delay may be 26 CAN clock cycles The impact of this delay can be minimized by clearing bit INTPND at an early User s Manual 19 10 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface stage of interrupt proce
120. most instructions but only GPRs RO R3 can be specified as the user stack pointer Rb Rw or Rw Rw Post increment Indirect Addressing Used to pop one byte or word from a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer User s Manual 22 8 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 2 Register Banking Register banking provides the user with an extremely fast method to switch user context A single machine cycle instruction saves the old bank and enters a new register bank Each register bank may assign up to 16 registers Each register bank should be allocated during coding based on the needs of each task Once the internal memory has been partitioned into a register bank space internal stack space and a global internal memory area each bank pointer is then assigned Thus upon entry into a new task the appropriate bank pointer is used as the operand for the SCXT switch context instruction Upon exit from a task a simple POP instruction to the context pointer CP restores the previous task s register bank 22 3 Procedure Call Entry and Exit To support modular programming a procedure mechanism is provided to allow coding of frequently used portions of code into subroutines The CALL and RET instructions store and restore the value of the instruction pointer IP on the system stack before and after a subroutine is executed
121. nfineon e technologies Derivatives The General Purpose Timer Units Timer 3 in Incremental Interface Mode Incremental Interface mode for the core timer T3 is selected by setting bit field T3M in register T3CON to 110 In incremental interface mode the two inputs associated with timer T3 T3IN T3EUD are used to interface to an incremental encoder T3 is clocked by each transition on one or both of the external input pins which gives 2 fold or 4 fold resolution of the encoder input T3IN Edge T3l T3R TSOE Up Down p Interrupt Request Phase T3EUD Detect T3UDE MCB04000B Figure 10 6 Block Diagram of Core Timer T3 in Incremental Interface Mode Bitfield T3l in control register T3CON selects the triggering transitions see Table 10 6 In this mode the sequence of the transitions of the two input signals is evaluated and generates count pulses as well as the direction signal So T3 is modified automatically according to the speed and the direction of the incremental encoder and its contents therefore always represent the encoder s current position Table 10 6 GPT1 Core Timer T3 Incremental Interface Mode Input Edge Selection T3I Triggering Edge for Counter Increment Decrement 000 None Counter T3 stops 001 Any transition rising or falling edge on T3IN 010 Any transition rising or falling edge on T3bEUD 0 1 1 Any transition rising or falling ed
122. o nfineon ed technologies Derivatives Table of Contents Page 1 uues iMMF 1 1 1 1 The Members of the 16 bit Microcontroller Family 1 2 1 2 Summary of Basic Features 0 0 00 eee eee 1 4 1 3 POOEVIAUOMS o 32 47 94 euin pats He R2 97 ur ded eh RT a U a aihn 1 7 2 Architectural Overview 0 000 ee 2 1 2 1 Basic CPU Concepts and Optimizations 02200 eee 2 2 2 1 1 High Instruction Bandwidth Fast Execution 2 3 2 1 2 Programmable Multiple Priority Interrupt System 2 7 2 2 The On Chip System Resources 0 2000 e eee eee eee 2 8 2 3 The On Chip Peripheral Blocks 02 00 e eee eee 2 11 2 4 Power Management Features 02020000 cee eee 2 18 2 5 Pr tected BS weree o tecst nankin E PEE awe kiwi dea doy Kc PR 2 19 3 Memory Organization aaa 3 1 3 1 Internal ROM Area 4008 baci made RE Eom dox x8 c3 EC o a ed 3 3 3 2 Internal RAM and SFR Area 0 00 cece eee 3 4 3 3 The On Chip XRAM a sauce qi ute gee 208 790 hee Boa G8 898 e eos xod ae 3 9 3 4 External Memory Space ueeexadsdaedpasrtregessGs esEetda EG 3 11 3 5 Crossing Memory Boundaries 0000 cee eee eens 3 12 3 6 Protection of the On Chip Mask ROM 0000 00 eee 3 13 4 The Central Processing Unit CPU 0 2 4 1 4 1 Instruction Pipelining ntetacadd Sek Se dx m
123. o Start 1B 8 oot POL 4 Proposal for Internal Reset Proposal for Internal Reset Proposal for Combined Circuitry EA 1 EA 0 MCA04466 Figure 15 2 Hardware Provisions to Activate the BSL The ASCO receiver is only enabled after the identification byte has been transmitted A half duplex connection to the host is therefore sufficient to feed the BSL Note The proper reset_configuration for BSL mode requires more pins to be driven besides POL 4or RD __ For an external reset EA 0 bitfield SMOD must be configured as 1011p see section Section 20 4 1 For an internal reset EA 1 pin ALE must be driven to a defined level e g ALE 0 for the standard bootstrap loader see section Section 20 4 2 User s Manual 15 2 V2 0 2000 07 o nfineon e technologies Derivatives The Bootstrap Loader Initial State in BSL Mode After entering BSL mode and the respective initialization the C167CS scans the RxDO line to receive a zero byte i e one start bit eight 0 data bits and one stop bit From the duration of this zero byte it calculates the corresponding baudrate factor with respect to the current CPU clock initializes the serial interface ASCO accordingly and switches pin TxDO to output Using this baudrate an identification byte is returned to the host that provides the loaded data This identification byte identifies the device to be booted The
124. of the external clock within the specified frequency range the PLL will be synchronous with this clock at a frequency of F x fosc i e the PLL locks to the external clock When PLL operation is selected the CPU clock is a selectable multiple of the oscillator frequency i e the input frequency Table 6 1 lists the possible selections User s Manual 6 6 V2 0 2000 07 o nfineon technologies C167CS Derivatives Clock Generation Table 6 1 C167CS Clock Generation Modes RPOH 7 5 CPU Frequency External Clock Notes POH 7 5 fcpu fosc xF Input Range 11 1 fosc x 4 2 5 to 8 25 MHz Default configuration 11 0 fosc x3 3 33 to 11 MHz 10 1 fosc x2 5 to 16 5 MHz 10 0 Josc x5 2 to 6 6 MHz 01 1 fosc X 1 1 to 33 MHz Direct drive 7 01 0 fosc x 1 5 6 66 to 22 MHz 00 1 fosc 2 2 to 66 MHz CPU clock via prescaler 000 fosc x 2 5 4 to 13 2 MHz 1 The external clock input range refers to a CPU clock range of 10 33 MHz 2 The maximum frequency depends on the duty cycle of the external clock signal In emulation mode pin P0 15 POH 7 is inverted i e the configuration 111 would select direct drive in emulation mode The PLL constantly synchronizes to the external clock signal Due to the fact that the external frequency is 1 F th of the PLL output frequency the output frequency may be slightly higher or lower than the desired frequency This jitter is irrelev
125. of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 3 the port latch is set upon a compare event and cleared upon a timer overflow see Figure 16 9 However when compare value and reload value for a channel are equal the respective interrupt requests will be generated only the output signal is not changed set and clear would coincide in this case Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective User s Manual 16 18 V2 0 2000 07 o nfineon e technologies Derivatives The Capture Compare Units Double Register Compare Mode In double register compare mode two compare registers work together to control one output pin This mode is selected by a special combination of modes for these two registers For double register mode the 16 capture compare registers of each CAPCOM unit are regarded as two banks of 8 registers each Registers CCO CC7 and CC16 CC23 form bank 1 while registers CC8 CC15 and CC24 CC31 form bank 2 respectively For double register mode a bank 1 register and a bank 2 register form a register pair Both registers of this register pair operate on the pin associated with the bank 1 register pins CCOIO CC7IO and CC16lO CC23IO The relat
126. output User s Manual 7 33 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports ODP4 P4 Open Drain Ctrl Reg ESFR F1CA E5y Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP4 ODP4 ODP4 ODP4 ODP4 ODP4 ODP4 ODP4 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw Bit Function ODP4 y Port 4 Open Drain control register bit y ODP4 y 0 Port line P4 y output driver in push pull mode ODP4 y 1 Port line P4 y output driver in open drain mode User s Manual 7 34 V2 0 2000 07 d nfineon ed technologies Derivatives Parallel Ports Alternate Functions of Port 4 During external bus cycles that use segmentation i e an address space above 64 KByte a number of Port 4 pins may output the segment address lines The number of pins that is used for segment address output determines the external address space which is directly accessible The other pins of Port 4 if any may be used for general purpose IO or for the CAN interface If segment address lines are selected the alternate function of Port 4 may be necessary to access e g external memory directly after reset For this reason Port 4 will be switched to this alternate function automatically The number of segment address lines is selected via bitfield SALSEL in register RPOH During an external reset register RPOH is configured according to the
127. overflow traps in this case serve for fatal error detection only For the linear stack option all modifiable bits of register SP are used to access the physical stack Although the stack pointer may cover addresses from 00 F000 up to O00 FFFE the physical system stack must be located within the internal RAM and therefore may only use the address range 00 F200 00 F600 00 FA00 to 00 FDFE It is the user s responsibility to restrict the system stack to the internal RAM range Note Avoid stack accesses below the IRAM area ESFR space and reserved area and within address range 00 FE00 and 00 FFFE SFR space Otherwise unpredictable results will occur User Stacks User stacks provide the ability to create task specific data stacks and to off load data from the system stack The user may push both bytes and words onto a user stack but is responsible for using the appropriate instructions when popping data from the specific user stack No hardware detection of overflow or underflow of a user stack is provided The following addressing modes allow implementation of user stacks Rw Rb or Rw Rw Pre decrement Indirect Addressing Used to push one byte or word onto a user stack This mode is only available for MOV instructions and can specify any GPR as the user stack pointer Rb Rw or Rw Rwj Post increment Index Register Indirect Addressing Used to pop one byte or word from a user stack This mode is available to
128. provisions most of the C167CS s instructions can be executed in just one machine cycle which requires 2 CPU clock cycles 2 x 1 fcpy 4 TCL For example shift and rotate instructions are always processed within one machine cycle independent of the number of bits to be shifted Branch multiply and divide instructions normally take more than one machine cycle These instructions however have also been optimized For example branch instructions only require an additional machine cycle when a branch is taken and most branches taken in loops require no additional machine cycles at all due to the so called Jump Cache A 32 bit 16 bit division takes 20 CPU clock cycles a 16 bit x 16 bit multiplication takes 10 CPU clock cycles The instruction cycle time has been dramatically reduced through the use of instruction pipelining This technique allows the core CPU to process portions of multiple sequential instruction stages in parallel The following four stage pipeline provides the optimum balancing for the CPU core FETCH In this stage an instruction is fetched from the internal ROM or RAM or from the external memory based on the current IP value DECODE In this stage the previously fetched instruction is decoded and the required operands are fetched EXECUTE In this stage the specified operation is performed on the previously fetched operands WRITE BACK In this stage the result is written to the specified location
129. register MDL or MDH is written via software or when a multiply or divide instruction is executed Internal Machine Status The multiply divide unit uses these bits to control internal operations Never modify these bits without saving and restoring register MDC When a division or multiplication was interrupted before its completion and the multiply divide unit is required the MDC register must first be saved along with registers MDH and MDL to be able to restart the interrupted operation later and then it must be cleared prepare it for the new calculation After completion of the new division or multiplication the state of the interrupted multiply or divide operation must be restored The MDRIU flag is the only portion of the MDC register which might be of interest for the user The remaining portions of the MDC register are reserved for dedicated use by the hardware and should never be modified by the user in another way than described above Otherwise a correct continuation of an interrupted multiply or divide operation cannot be guaranteed A detailed description of how to use the MDC register for programming multiply and divide algorithms can be found in Chapter 22 User s Manual 4 32 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The Constant Zeros Register ZEROS All bits of this bit addressable register are fixed to 0 by hardware This register can be read onl
130. register PWx with a shadow latch two comparators and the necessary control logic The operation of all four channels is controlled by two common control registers PWMCONO and PWMCON1 and the interrupt control and status is handled by one interrupt control register PWMIC which is also common for all channels User s Manual 17 V2 0 2000 07 o nfineon end technologies Derivatives The Pulse Width Modulation Module PPx Period Register Shadow Register Fx 16 Bit Up Down Counter Write Control Up Down Clear Control i Run CPU Input E Control Match OU Enable u pu I Comparator ani O POUTx Shadow Register L PWx Pulse Width Reg User Read amp Writeable MCB01948 Figure 17 2 PWM Channel Block Diagram 17 1 Operating Modes The PWM module provides four different operating modes Standard PWM generation edge aligned PWM available on all four channels e Symmetrical PWM generation center aligned PWM available on all four channels Burst mode combines channels 0 and 1 Single shot mode available on channels 2 and 3 Note The output signals of the PWM module are XORed with the outputs of the respective port output latches After reset these latches are cleared so the PWM signals are directly driven to the port pins By setting the respective port output latch to 1 the PWM signal may be inverted XORed with 1 before being
131. reload values must be adapted Please note that the reduced CPU frequency decreases e g timer resolution and increases the step width e g for baudrate generation The oscillator frequency in such a case should be chosen to accomodate the required resolutions and or baudrates User s Manual 21 11 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management SYSCON2 System Control Reg 2 ESFR F1D0j4 E8j Reset Value 00X04 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ons CLKREL CLKCON SCS RCS PDCON SYSRLS r rw rw rw rw rw rw Bit Function SYSRLS Register Release Function Unlock field Must be written in a defined way in order to execute the unlock sequence See separate description Table 21 6 PDCON Power Down Control during power down mode 00 RTC On Ports On default after reset 01 RTC On Ports Off 10 RTC Off Ports On 11 RTC Off Ports Off RCS RTC Clock Source not affected by a reset 0 Main oscillator 1 Reserved SCS SDD Clock Source not affected by a reset 0 Main oscillator T Reserved CLKCON Clock State Control 00 Running on configured basic frequency 01 Running on slow down frequency PLL remains ON 10 Running on slow down frequency PLL switched OFF 11 Reserved Do not use this combination CLKREL Reload Counter Value for Slowdown Divider SDD factor CLKREL 1 CLKLOCK Clock Signal Status Bi
132. response time including external accesses will occur when instructions N and N 1 are executed out of external memory instructions N 1 and N require external operand read accesses and instructions N 3 N 2 and N 1 write back external operands In this case the PEC response time is the time to perform 7 word bus accesses e When instructions N and N 1 are executed out of external memory but all operands for instructions N 3 through N 1 are in internal memory then the PEC response time is the time to perform 1 word bus access plus 2 state times Once a request for PEC service has been acknowledged by the CPU the execution of the next instruction is delayed by 2 state times plus the additional time it might take to fetch the source operand from internal code memory or external memory and to write the destination operand over the external bus in an external program environment Note A bus access in this context includes all delays which can occur during an external bus cycle User s Manual 5 24 V2 0 2000 07 d nfineon ed technologies Derivatives Interrupt and Trap Functions 5 7 Interrupt Node Sharing Interrupt nodes may be shared between several module requests either if the requests are generated mutually exclusive or if the requests are generated at a low rate If more than one source is enabled in this case the interrupt handler will first have to determine the requesting source However thi
133. rounded Using a baudrate crystal e g 18 432 MHz will provide correct baudrates without deviation errors User s Manual 11 11 V2 0 2000 07 _ nfineon technologies C167CS Derivatives The Asynchronous Synchronous Serial Interface Table 11 1 ASCO Asynchronous Baudrate Generation for fcpy 16 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 500 KBaud 0 0 0000 19 2 KBaud 0 2 3 5 0019 001A4 2 1 3 5 001040011 9600 Baud 0 2 1 7 0033p 00344 2 1 0 8 0021 00224 4800 Baud 0 2 0 8 00674 00684 0 696 0 826 0044 0045 2400 Baud 0 2 0 3 00CFp 00D04 0 626 0 196 0089 008A4 1200 Baud 0 4 0 1 O19FY 01A04 0 3 0 1 1011440115 600 Baud 0 0 0 1 0340 0841 0 1 0 1 022A 4 022By 61 Baud 0 196 1FFFy 0 096 0 0 115By 115C 40 Baud 1 796 1FFF Table 11 2 ASCO Asynchronous Baudrate Generation for fcpy 20 MHz Baud Rate SOBRS 0 SOBRS 1 Deviation Error Reload Value Deviation Error Reload Value 625 KBaud 0 0 0000 19 2 KBaud 1 7 1 4 001F 0020 3 3 1 4 001440015 9600 Baud 0 2 1 4 0040 0041 1 096 1 496 002A 002By 4800 Baud 0 2 0 6 0081 0082 1 0 0 2 0055 0056 2400 Baud 0 296 0 2 0103
134. scalable frequency or temporarily can be switched off completely This clock signal is generated via a reload counter so the output frequency can be selected in small steps An optional toggle latch provides a clock signal with a 5096 duty cycle FOEN forpu FOSS MCA04480 Figure 21 6 Clock Output Signal Generation Signal four always provides complete output periods see Signal Waveforms below When four is started FOEN gt 1 FOCNT is loaded from FORV When four is stopped FOEN gt 0 FOCNT is stopped when four has reached or is 0 Signal four is independent from the peripheral clock driver PCD While CLKOUT would stop when PCD is disabled four will keep on toggling Thus external circuitry may be controlled independent from on chip peripherals Note Counter FOCNT is clocked with the CPU clock signal f cpy see Figure 21 6 and therefore will also be influenced by the SDD operation Register FOCON provides control over the output signal generation frequency waveform activation as well as all status information counter value FOTL User s Manual 21 17 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management FOCON Frequ Output Control Reg SFR FFAAp D5p Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FO FO FO EN SS FORV TL FOCNT rw rw rw rw rw
135. source can be assigned to a specific priority A second level called group priority allows to specify an internal order for simultaneous requests from a group of different sources on the same priority level At the end of each instruction cycle the one source request with the highest current priority will be determined by the interrupt system This request will then be serviced if its priority is higher than the current CPU priority in register PSW Interrupt System Register Description Interrupt processing is controlled globally by register PSW through a general interrupt enable bit IEN and the CPU priority field ILVL Additionally the different interrupt sources are controlled individually by their specific interrupt control registers IC Thus the acceptance of requests by the CPU is determined by both the individual interrupt control registers and the PSW PEC services are controlled by the respective PECCx register and the source and destination pointers which specify the task of the respective PEC service channel 5 1 1 Interrupt Control Registers All interrupt control registers are organized identically The lower 8 bits of an interrupt control register contain the complete interrupt status information of the associated source which is required during one round of prioritization the upper 8 bits of the respective register are reserved All interrupt control registers are bit addressable and all bits can be read or written v
136. state time waitstate requires one CPU clock 2 TCL and is controlled via the MTTOx bits of the BUSCON registers A waitstate will be inserted if bit MTTCx is 0 default after reset Note External bus cycles in multiplexed bus modes implicitly add one tri state time waitstate in addition to the programmable MTTC waitstate User s Manual 9 15 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Read Write Signal Delay The C167CS allows the user to adjust the timing of the read and write commands to account for timing requirements of external peripherals The read write delay controls the time between the falling edge of ALE and the falling edge of the command Without read write delay the falling edges of ALE and command s are coincident except for propagation delays With the delay enabled the command s become active half a CPU clock 1 TCL after the falling edge of ALE The read write delay does not extend the memory cycle time and does not slow down the controller in general In multiplexed bus modes however the data drivers of an external device may conflict with the C167CS s address when the early RD signal is used Therefore multiplexed bus cycles should always be programmed with read write delay The read write delay is controlled via the RWDCx bits in the BUSCON registers The command s will be delayed if bit RWDOx is 0 default after reset Early WR Signal Deactivatio
137. system software The interrupt trap vector table which uses locations 00 0000 through 00 01FF is now part of the external memory and may therefore be modified i e the system software may now change interrupt trap handlers according to the current condition of the system The internal code memory can still be used for fixed software routines like IO drivers math libraries application specific invariant routines tables etc This combines the advantage of an integrated non volatile memory with the advantage of a flexible adaptable software system User s Manual 22 16 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming Enabling and Disabling the Internal Code Memory After Reset If the internal code memory does not contain an appropriate startup code the system may be booted from external memory while the internal memory is enabled afterwards to provide access to library routines tables etc If the internal code memory only contains the startup code and or test software the system may be booted from internal memory which may then be disabled after the software has switched to executing from e g external memory in order to free the address space occupied by the internal code memory which is now unnecessary User s Manual 22 17 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 11 Pits Traps and Mines Although handling the internal code memory provides powe
138. the CALLS call inter segment subroutine instruction This instruction preserves both the CSP code segment pointer and IP on the system stack Upon return from the subroutine a RETS return from inter segment subroutine instruction must be used to restore both the CSP and IP This ensures that the next instruction after the CALLS instruction is fetched from the correct segment Note It is possible to use CALLS within the same segment but still two words of the stack are used to store both the IP and CSP Providing Local Registers for Subroutines For subroutines which require local storage the following methods are provided Alternate Bank of Registers Upon entry into a subroutine it is possible to specify a new set of local registers by executing the SCXT switch context instruction This mechanism does not provide a method to recursively call a subroutine Saving and Restoring of Registers To provide local registers the contents of the registers which are required for use by the subroutine can be pushed onto the stack and the previous values be popped before returning to the calling routine This is the most common technique used today and it does provide a mechanism to support recursive procedures This method however requires two machine cycles per register stored on the system stack one cycle to PUSH the register and one to POP the register Use of the System Stack for Local Registers It is possible to use the SP and CP
139. the PEC the associated PEC channel number is derived from the respective ILVL LSB and GLVL see Figure 5 1 So programming a source to priority level 15 ILVL 11115 selects the PEC channel group 7 4 programming a source to priority level 14 ILVL 1110p selects the PEC channel group 3 0 The actual PEC channel number is then determined by the group priority field GLVL Simultaneous requests for PEC channels are prioritized according to the PEC channel number where channel 0 has lowest and channel 8 has highest priority Note All sources that request PEC service must be programmed to different PEC channels Otherwise an incorrect PEC channel may be activated User s Manual 5 8 V2 0 2000 07 j Infineon e technologies Derivatives Interrupt and Trap Functions Interrupt Control Register PEC Control PEC Channel MCA04330 Figure 5 1 Priority Levels and PEC Channels Table 5 3 shows in a few examples which action is executed with a given programming of an interrupt control register Table 5 3 Interrupt Priority Examples Priority Level Type of Service ILVL GLVL COUNT 004 COUNT 004 1111 411 CPU interrupt PEC service level 15 group priority 3 channel 7 1111 10 CPU interrupt PEC service level 15 group priority 2 channel 6 1110 10 CPU interrupt PEC service level 14 group priority 2 channel 2 1101 10 CPU interrupt CPU interrupt level 13
140. the first clock User s Manual 12 8 V2 0 2000 07 oe nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface edge generated by the master may be already used to clock in the first data bit So the slave s first data bit must already be valid at this time Note On the SSC always a transmission and a reception takes place at the same time regardless whether valid data has been transmitted or received This is different e g from asynchronous reception on ASCO The initialization of the SCLK pin on the master requires some attention in order to avoid undesired clock transitions which may disturb the other receivers The state of the internal alternate output lines is 1 as long as the SSC is disabled This alternate output signal is ANDed with the respective port line output latch Enabling the SSC with an idle low clock SSCPO 0 will drive the alternate data output and via the AND the port pin SCLK immediately low To avoid this use the following sequence select the clock idle level SSCPO x load the port output latch with the desired clock idle level P3 13 x switch the pin to output DP3 13 1 enable the SSC SSCEN 1 e if SSCPO 0 enable alternate data output P3 13 1 The same mechanism as for selecting a slave for transmission separate select lines or special commands may also be used to move the role of the master to anot
141. the physical address No additional switching or selecting is necessary during run time except when more than the four address windows plus the default is to be used Reprogramming the BUSCON and or ADDRSEL registers allows to either change the bus mode for a given address window or change the size of an address window that uses a certain bus mode Reprogramming allows to use a great number of different address windows more than BUSCONS are available on the expense of the overhead for changing the registers and keeping appropriate tables Note Be careful when changing the configuration for an address area that currently supplies the instruction stream Due to the internal pipelining the first instruction fetch that will use the new configuration depends on the instructions prior to the configuration change Special care is required when changing bits like BUSACT or RDYEN in order not to cut the instruction stream inadvertently Only change the other configuration bits after checking that the respective application can cope with the intended modification s It is recommended to change ADDRSEL registers only while the respective BUSACT bit in the associated BUSCON register is cleared Switching from demultiplexed to multiplexed bus mode represents a special case The bus cycle is started by activating ALE and driving the address to Port 4 and PORT1 as usual if another BUSCON register selects a demultiplexed bus However in the User s Man
142. the shift clock These signals are alternate port functions Synchronous mode is selected with SOM 000p 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator The shift clock is only active as long as data bits are transmitted or received Reload Register CPU Clock gt SOR Receive Int ARR Request Serial Port Control SOTIR Transmit Int TXDO P3 10 bal J Shift Clock SOEIR Error Int Request Receive Dp pn Receive Shift RXD0 P3 11 MUX Register E Transmit Receive Buffer Reg SORBUF MCB02220 Figure 11 5 Synchronous Mode of Serial Channel ASCO User s Manual 11 8 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface Synchronous transmission begins within 4 state times after data has been loaded into SOTBUF provided that SOR is set and SOREN 0 half duplex no reception Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The data bits are transmitted synchronous with the shift clock After the bit time for the 8th data bit bo
143. the software initialization routine WDTR is reset to 0 by an external hardware reset by servicing the watchdog timer or after EINIT After the internal reset has completed the operation of the watchdog timer can be disabled by the DISWDT Disable Watchdog Timer instruction This instruction has been implemented as a protected instruction For further security its execution is only enabled in the time period after a reset until either the SRVWDT Service Watchdog Timer or the EINIT instruction has been executed Thereafter the DISWDT instruction will have no effect Reset Values for the C167CS Registers During the reset sequence the registers of the C167CS are preset with a default value Most SFRs including system registers and peripheral control and data registers are cleared to zero so all peripherals and the interrupt system are off or idle after reset A few exceptions to this rule provide a first pre initialization which is either fixed or controlled by input pins DPP1 00014 points to data page 1 DPP2 00024 points to data page 2 DPP3 0003 points to data page 3 CP FCO00 STKUN FCOO STKOV FAOOW SP FCOO WDTCON 00XX value depends on the reset source SORBUF XXy undefined SSCRB XXXXy undefined SYSCON 0XX0 set according to reset configuration BUSCONO 0XXO0j set according to reset configuration RPOH XXy reset levels of POH ONES FFFFy fixed value User s Manual 20 5 V2 0 2000 07
144. this In larger sequential programs make sure that the highest used code location of a segment contains an unconditional branch instruction to the respective following segment to prevent the prefetcher from trying to leave the current segment Data Pages are contiguous blocks of 16 KByte each They are referenced via the data page pointers DPP3 0 and via an explicit data page number for data accesses overriding the standard DPP scheme Each DPP register can select one of the possible 1024 data pages The DPP register that is used for the current access is selected via the two upper bits of the 16 bit data address Subsequent 16 bit data addresses that cross the 16 KByte data page boundaries therefore will use different data page pointers while the physical locations need not be subsequent within memory User s Manual 3 12 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization 3 6 Protection of the On Chip Mask ROM The on chip mask ROM of the C167CS can be protected against read accesses of both code and data ROM protection is established during the production process of the device a ROM mask can be ordered with a ROM protection or without it No software control is possible i e the ROM protection cannot be disabled or enabled by software When a device has been produced with ROM protection active the ROM contents are protected against unauthorized access by the following measures No data read ac
145. through upon completion no machine cycles are lost when exiting the loop No special instructions are required to perform loops and loops are automatically detected during execution of branch instructions The second loop enhancement allows the detection of the end of a table and avoids the use of two compare instructions embedded in loops One simply places the lowest negative number at the end of the specific table and specifies branching if neither this value nor the compared value have been found Otherwise the loop is terminated if either condition has been met The terminating condition can then be tested The third loop enhancement provides a more flexible solution than the Decrement and Skip on Zero instruction which is found in other microcontrollers Through the use of Compare and Increment or Decrement instructions the user can make comparisons to any value This allows loop counters to cover any range This is particularly advantageous in table searching Saving of system state is automatically performed on the internal system stack avoiding the use of instructions to preserve state upon entry and exit of interrupt or trap routines Call instructions push the value of the IP on the system stack and require the same execution time as branch instructions Instructions have also been provided to support indirect branch and call instructions This supports implementation of multiple CASE statement branching in assembler macros and hi
146. trap is either completed or cancelled i e it has no effect on the system state before the trap handling routine is entered Hardware traps are non maskable and always have priority over every other CPU activity If several hardware trap conditions are detected within the same instruction cycle the highest priority trap is serviced see Table 5 2 User s Manual 5 31 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions PSW CSP in segmentation mode and IP are pushed on the internal system stack and the CPU level in register PSW is set to the highest possible priority level i e level 15 disabling all interrupts The CSP is set to code segment zero if segmentation is enabled A trap service routine must be terminated with the RETI instruction The eight hardware trap functions of the C167CS are divided into two classes Class A traps are E external Non Maskable Interrupt NMI Stack Overflow Stack Underflow Trap These traps share the same trap priority but have an individual vector address Class B traps are Undefined Opcode Protection Fault Illegal Word Operand Access Illegal Instruction Access Illegal External Bus Access Trap These traps share the same trap priority and the same vector address The bit addressable Trap Flag Register TFR allows a trap service routine to identify the kind of trap which caused the exception Each trap function is indicated b
147. trigger signal can be a positive a negative or both a positive and a negative transition The two least significant bits of bit field Txl are used to select the active transition see Table 10 8 while the most significant bit Txl 2 is irrelevant for capture mode It is recommended to keep this bit cleared Txl 2 0 Note When programmed for capture mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or T4R Edge Select Capture Register Tx Interrupt Request Input pd Interrupt Clock Core Timer T3 Request Up Down X224 MCB02038 Figure 10 14 GPT1 Auxiliary Timer in Capture Mode Upon a trigger selected transition at the corresponding input pin TxIN the contents of the core timer are loaded into the auxiliary timer register and the associated interrupt request flag TxIR will be set Note The direction control bits for T2IN and T4IN must be set to 0 and the level of the capture trigger signal should be held high or low for at least 8 fep cycles before it changes to ensure correct edge detection User s Manual 10 20 V2 0 2000 07 o nfineon technologies C167CS Derivatives 10 1 3 The General Purpose Timer Units Interrupt Control for GPT1 Timers When a timer overflows from FFFF to 0000 when counting up or when it underflows from 0000 to FFFFy when counting down its interrupt request flag T2IR TSIR or T4IR in register
148. true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of six IO ports can be configured pin by pin for push pull operation or open drain operation via control registers During the internal reset all port pins are configured as inputs All port lines have programmable alternate input or output functions associated with them PORTO and PORT1 may be used as address and data lines when accessing external memory while Port 4 outputs the additional segment address bits A23 19 17 A16 in systems where segmentation is used to access more than 64 KBytes of memory Port 6 provides the optional bus arbitration signals BREQ HLDA HOLD and the chip select signals CS4 CSO Port 2 accepts the fast external interrupt inputs and provides inputs outputs for the CAPCOM unit Port 3 includes alternate functions of timers serial interfaces the optional bus control signal BHE and the system clock output CLKOUT FOUT Port 5 is used for timer control signals and for the analog inputs to the A D Converter The analog extension channels are connected via P1L Port 7 provides the output signals from the PWM unit and inputs outputs for the CAPCOM2 unit more on P1H Port 8 provides inputs outputs for the CAPCOM2 unit Four pins of PORT1 may also be used as inputs outputs for the CAPCOM2 unit All port lines that are not used for these alternate functions may be used as general purpose IO lines
149. used for general purpose IO the direction of each line can be configured via the corresponding direction register DP2 Each port line can be switched into push pull or open drain mode via the open drain control register ODP2 P2 Port 2 Data Register SFR FFCO E0 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P2 P2 P2 P2 P2 P2 15 44 13 12 11 19 P2 9 P2 8 P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh rwh Bit Function P2 y Port data register P2 bit y DP2 P2 Direction Ctrl Register SFR FFC2 E1 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 DP2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bit Function DP2 y Port direction register DP2 bit y DP2 y 0 Port line P2 y is an input high impedance DP2 y 1 Port line P2 y is an output User s Manual 7 23 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports ODP2 P2 Open Drain Ctrl Reg ESFR F1C2 E1 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 ODP2 15
150. value pushed onto the system stack is the illegal odd target address of the branch instruction Illegal External Bus Access Trap Whenever the CPU requests an external instruction fetch data read or data write and no external bus configuration has been specified the ILLBUS flag in register TFR is set and the CPU enters the illegal bus access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap User s Manual 5 35 V2 0 2000 07 o nfineon ed technologies Derivatives Clock Generation 6 Clock Generation All activities of the C167CS s controller hardware and its on chip peripherals are controlled via the system clock signal fep This reference clock is generated in three stages see also Figure 6 1 Oscillator The on chip Pierce oscillator can either run with an external crystal and appropriate oscillator circuitry or it can be driven by an external oscillator or another clock source Frequency Control The input clock signal feeds the controller hardware directly providing phase coupled operation on not too high input frequency divided by 2 in order to get 5096 duty cycle clock signal via an on chip phase locked loop PLL providing max performance on low input frequency via the Slow Down Divider SDD in order to reduce the power consumption The resulting internal clock signal is referred to as CPU clock fcpy Clock Drivers
151. via the SFR space In order to minimize the use of the EXTR instructions the ESFR area mostly holds registers which are mainly required for initialization and mode selection Registers that need to be accessed frequently are allocated to the standard SFR area wherever possible Note The tools are equipped to monitor accesses to the ESFR area and will automatically insert EXTR instructions or issue a warning in case of missing or excessive EXTR instructions User s Manual 3 8 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization 3 3 The On Chip XRAM The C167CS provides access to 8 KByte of on chip extension RAM The XRAM is located within data page 3 and is split into two XRAM areas of 2 KByte and 6 KByte organized as 1 K x 16 and 3 K x 16 As the XRAM is connected to the internal XBUS it is accessed like external memory however no external bus cycles are executed for these accesses XRAM accesses are globally enabled or disabled via bit XPEN in register SYSCON This bit is cleared after reset and may be set via software during the initialization to allow accesses to the on chip XRAM When the XRAM is disabled default after reset all accesses to the XRAM area are mapped to external locations The XRAM may be used for both code instructions and data variables user stack tables etc storage Code fetches are always made on even byte addresses The highest possible code storage location in the XRAM i
152. well balanced way The sum of the features which are combined result in a high performance microcontroller which is the right choice not only for today s applications but also for future engineering challenges The C167CS not only integrates a powerful CPU core and a set of peripheral units into one chip but also connects the units in a very efficient way One of the four buses used concurrently on the C167CS is the XBUS an internal representation of the external bus interface This bus provides a standardized method of integrating application specific peripherals to produce derivatives of the standard C167CS Dual Port RAM 3 KByte Instr Data 32 KByte ProgMem C166 Core T IRAM Data Internal 32 jo CPU E XRAM I SEG Osc PLL J AE 6 2 KByte External Instr Data aO Interrupt Controller Priorit Interrupt Bus ES CAN2 Jaf e 4 e Rev 2 0B active Peripheral Data Bus i CAN1 Rev 2 0B active On Chip XBUS 16 Bit Dem ADC ASCO SSC 10 Bit USART SP 16 8 EBC Channels XBUS Control External Bus CZ Control MCB04323 7CSR Figure 2 1 C167CS Functional Block Diagram User s Manual 2 1 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview 2 1 Basic CPU Concepts and Optimizations The main core of the CPU consists o
153. y 0 Port line POX y is an input high impedance DPOX y 1 Port line POX y is an output Alternate Functions of PORTO When an external bus is enabled PORTO is used as data bus or address data bus Note that an external 8 bit demultiplexed bus only uses POL while POH is free for IO provided that no other bus mode is enabled PORTO is also used to select the system startup configuration During reset PORTO is configured to input and each line is held high through an internal pullup device Each line can now be individually pulled to a low level see DC level specifications in the respective Data Sheets through an external pulldown device A default configuration is selected when the respective PORTO lines are at a high level Through pulling individual lines to a low level this default can be changed according to the needs of the applications The internal pullup devices are designed such that an external pulldown resistors see Data Sheet specification can be used to apply a correct low level These external pulldown resistors can remain connected to the PORTO pins also during normal operation however care has to be taken such that they do not disturb the normal function of PORTO this might be the case for example if the external resistor is too strong With the end of reset the selected bus configuration will be written to the BUSCONO register The configuration of the high byte of PORTO will be copied into the special
154. 0 2000 07 d Infineon iis technologies Derivatives The Analog Digital Converter The external analog reference voltages Varner and Vagnp are fixed The separate supply for the ADC reduces the interference with other digital signals The sample time as well as the conversion time is programmable so the ADC can be adjusted to the internal resistances of the analog sources and or the analog reference voltage supply ADCON Conversion Control Interrupt Requests ANO 10 Bit Result Reg ADDAT Converter Result Reg ADDAT2 AN15 AN16 VAGND AN23 MCA04471 Figure 18 2 Analog Digital Converter Block Diagram User s Manual 18 2 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter 18 1 Mode Selection and Operation The analog input channels AN15 ANO are alternate functions of Port 5 which is an input only port The Port 5 lines may either be used as analog or digital inputs For pins that shall be used as analog inputs it is recommended to disable the digital input stage via register PSDIDIS This avoids undesired cross currents and switching noise while the analog input signal level is between Vi and Vj The analog input channels AN23 AN16 are alternate functions of PORT1 which is an IO port The port lines P1L 7 0 may either be used as analog inputs or digital IOs For pins that shall be used as analog inputs it is recommended to disable the digita
155. 0 2000 07 C167CS Derivatives technologies The Analog Digital Converter x 3 x x 2 x 3 Conversion of Channel Wait until ADDAT 2 is Write ADDAT x 1 ADDAT Full L Read ADDAT Injected Conversion Channel Injection of Channey Request ADDAT2 Full Write ADDAT2 y Int Request ADEINT Read ADDAT2 Temp Latch Full Hx x1 x 2 x 3 Conversion of Channel Write ADDAT ADDAT Full Read ADDAT Temp Latch Full Channel Injection en Request Wait until DAT y Write ADDAT2 ADDAT2 is ADDAT2 Full read Int Request ADEINT Read ADDAT2 y MCA01972 Figure 18 6 Channel Injection Example with Wait for Read User s Manual 18 11 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter Arbitration of Conversions Conversion requests that are activated while the ADC is idle immediately trigger the respective conversion If a conversion is requested while another conversion is currently in progress the operation of the A D converter depends on the kind of the involved conversions standard or injected Note A conversion request is activated if the respective control bit ADST or ADCRQ is toggled from 0 to 1 i e the bit must have been zero before being set Table 18 1 summarizes the ADC operation in the possible situations Table 18 1 Conversion Arbitration Conversion New R
156. 00 PLL fx 2 5 100 PLL fx 5 001 Prescaler f 2 101 PLL fx 2 010 PLL fx 1 5 110 PLL fx 3 011 Direct Drive f f 111 PLL fx 4 1 RSTLEN is always valid for the next reset sequence An initial power up reset however is expected to last considerably longer than any configurable reset sequence User s Manual 20 23 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Note RSTCON is write protected after the execution of EINIT unless it is released via the unlock sequence see Section 21 7 RSTCON can only be accessed via its long mem adaress User s Manual 20 24 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management 21 Power Management For an increasing number of microcontroller based systems it is an important objective to reduce the power consumption of the system as much as possible A contradictory objective is however to reach a certain level of system performance Besides optimization of design and technology a microcontrollers power consumption can generally be reduced by lowering its operating frequency and or by reducing the circuitry that is clocked The architecture of the C167CS provides three major means of reducing its power consumption see Figure 21 1 under software control Reduction of the CPU frequency for Slow Down operation Flexible Clock Generation Management Selection of the active peripheral modules Flexible Peripheral Manage
157. 000 07 o nfineon ed technologies Derivatives Table of Contents Page 19 2 General Functional Description 00 eee ee eee 19 8 19 2 1 CAN Interrupt Handling 002 eee eee 19 10 19 2 2 Configuration of the Bit Timing 000 ce eee eee 19 12 19 2 3 Mask Registers Lu ied hae eq MR 9d e d Und 9 eh 202 ORA TRE Fo 19 16 19 3 The Message Object 0 0c cece eens 19 19 19 4 Controlling the CAN Module 0 000 e eee eee eee 19 31 19 5 Configuration Examples for Message Objects 19 35 19 6 The Second CAN Module CAN2 00 cee eee 19 37 19 7 The CAN Application Interface 00 cee ee 19 38 20 System Reset ong ig Mead oak vh whee ewe E d Adda Edw i 20 1 20 1 Reset SourceS ane va acide m da ek eee ac d nt hs Botte se edd amp 20 2 20 2 Status After Reset casse ee etek ea x X heen ed oe aw Sew ee ea 20 5 20 3 Application Specific Initialization Routine llle 20 9 20 4 System Startup Configuration 002 20 12 20 4 1 System Startup Configuration upon an External Reset 20 13 20 4 2 System Startup Configuration upon a Single Chip Mode Reset 20 20 20 5 System Configuration via Software llle 20 22 21 Power Management 000 cee cece eee eee 21 1 21 1 25 Ctr Hea ad Sad doe eae RARE eee eee ae aes 21 3 21 2 Sleep MOUE 22254554564 56 2555 a riua imada sees setan eens 5 21 5 21 3 Powe
158. 000 07 o nfineon oo technologies Derivatives Architectural Overview The On Chip CAN Modules The integrated CAN Modules CAN1 CAN2 handle the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active i e the on chip CAN Module can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers The modules provide Full CAN functionality on up to 15 message objects up to 30 objects if both modules are connected to the same physical bus Message object 15 may be configured for Basic CAN functionality Both modes provide separate masks for acceptance filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects and are equipped for the maximum message length of 8 Bytes The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud Each CAN Module uses two pins configurable both modules may use the same pair of pins to interface to a bus transceiver Parallel Ports The C167CS provides up to 111 IO lines which are organized into eight input output ports and one input port All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers The IO ports are
159. 004 TO FE504 284 CAPCOM Timer 0 Register 00004 T1 FE52y 294 CAPCOM Timer 1 Register 0000 TOREL FE54 2Ay CAPCOM Timer 0 Reload Register 0000 T1REL FE564 2By CAPCOM Timer 1 Reload Register 0000 CC16 FE60 304 CAPCOM Register 16 0000 CC17 FE62 314 CAPCOM Register 17 0000 CC18 FE64 324 CAPCOM Register 18 0000 CC19 FE66 334 CAPCOM Register 19 0000 User s Manual 23 18 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value CC20 FE68 344 CAPCOM Register 20 00004 CC21 FE6A 354 CAPCOM Register 21 0000 CC22 FE6C 1364 CAPCOM Register 22 00004 CC23 FE6E 374 CAPCOM Register 23 0000 CC24 FE70y 384 CAPCOM Register 24 00004 CC25 FE724 39 CAPCOM Register 25 0000 CC26 FE744 3A CAPCOM Register 26 0000 CC27 FE76y 3By CAPCOM Register 27 00004 CC28 FE78y 3C CAPCOM Register 28 00004 CC29 FE7A 3Dy4 CAPCOM Register 29 0000 CC30 FE7C 3Ey4 CAPCOM Register 30 00004 CC31 FE7E 3Fy4 CAPCOM Register 31 0000 CCO FE80 40 CAPCOM Register 0 0000 CC1 FE824 414 CAPCOM Register 1 0000 CC2 FE84 42 CAPCOM Register 2 00004 CC3 FE86 434 CAPCOM Register 3 0000 CC4 FE88 444 CAPCOM Register 4 0000 CC5 FE8A 454 CAPCOM Register 5 0000 CC6 FE8C
160. 0234 9600 Baud 0 4 0 5 O006A O06By 0 9 0 5 00464 00474 4800 Baud 0 4 0 1 00D5 00D6 0 2 0 5 008E 008F 2400 Baud 0 2 0 1 01AC 01ADy 0 2 0 2 011D 011E 1200 Baud 0 0 0 1 035Ap 035B4 0 2 0 0 023B 4 023C 600 Baud 0 0 0 0 06B5 06B6 0 1 0 0 04784 04794 125 Baud 7 1 1FFF t 0 096 157Cy 84 Baud 0 996 1FFF User s Manual 11 13 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Asynchronous Synchronous Serial Interface Synchronous Mode Baud Rates For synchronous operation the baud rate generator provides a clock with 4 times the rate of the established baud rate The baud rate for synchronous operation of serial channel ASCO can be determined by the following formula SOBRL CPU 4 x 2 lt SOBRS gt x Bgync cPU 1 c e PP Sync 4 x 2 SOBRS x lt SOBRL gt 1 lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integers lt SOBRS gt represents the value of bit SOBRS i e 0 or 1 taken as integer Table 11 5 gives the limit baudrates depending on the CPU clock frequency and bit SOBRS Table 11 5 ASCO Synchronous Baudrate Generation CPU clock SOBRS 0 SOBRS 1 fcPu Min Baudrate Max Baudrate Min Baudrate Max Baudrate 16 MHz 244 Baud 2 000 MBaud 16
161. 08 111g Prescaler 1 N 8 16 32 64 128 256 512 1024 Input Frequency 4 125 2 063 1 031 515 63 257 81 128 91 64 453 32 227 MHz MHz MHz kHz kHz kHz kHz kHz Resolution 242 485 970 1 94 3 88 7 16 15 52 31 03 ns ns ns us us us us us Period 15 89 31 78 63 55 127 10 254 20 508 40 1 017 2 034 ms ms ms ms ms ms S S User s Manual 16 7 V2 0 2000 07 o nfineon e technologies Derivatives The Capture Compare Units Counter Mode The bits TxM in SFRs TO1CON and T78CON select between timer or counter mode for the respective timer In Counter mode TxM 1 the input clock for a timer can be derived from the overflows underflows of timer T6 in block GPT2 In addition timers TO and T7 can be clocked by external events Either a positive a negative or both a positive and a negative transition at pin TOIN or T7IN alternate port input function respectively can be selected to cause an increment of TO T7 When T1 or T8 is programmed to run in counter mode bit field Txl is used to enable the overflows underflows of timer T6 as the count source This is the only option for these timers and it is selected by the combination Txl 000g When bit field Txl is programmed to any other valid combination the respective timer will stop When TO or T7 is programmed to run in counter mode bit field Txl is used to select the count source and transition if the source is the input pin w
162. 1 5 3 High 16 bit latch word bus P1H P1L 16 bit Demultipl Very high 1 1 2 Low no latch word bus Note PORT1 becomes available for general purpose IO when none of the BUSCON registers selects a demultiplexed bus mode User s Manual 9 8 V2 0 2000 07 d nfineon ed technologies Derivatives The External Bus Interface Disable Enable Control for Pin BHE BYTDIS EN Bit BYTDIS is provided for controlling the active low Byte High Enable BHE pin The function of the BHE pin is enabled if the BYTDIS bit contains a 0 Otherwise it is disabled and the pin can be used as standard IO pin The BHE pin is implicitly used by the External Bus Controller to select one of two byte organized memory chips which are connected to the C167CS via a word wide external data bus After reset the BHE function is automatically enabled BYTDIS 0 if a 16 bit data bus is selected during reset otherwise it is disabled BYTDIS 1 It may be disabled if byte access to 16 bit memory is not required and the BHE signal is not used Segment Address Generation During external accesses the EBC generates a programmable number of address lines on Port 4 which extend the 16 bit address output on PORTO or PORT1 and so increase the accessible address space The number of segment address lines is selected during reset and coded in bit field SALSEL in register RPO see Table 9 3 Table 9 3 Decoding of Seg
163. 12 The High Speed Synchronous Serial Interface The high speed Synchronous Serial Interface SSC provides flexible high speed serial communication between the C167CS and other microcontrollers microprocessors or external peripherals The SSC supports full duplex and half duplex synchronous communication up to 6 25 8 25 MBaud 25 33 MHz CPU clock The serial clock signal can be generated by the SSC itself master mode or be received from an external master slave mode Data width shift direction clock polarity and phase are programmable This allows communication with SPl compatible devices Transmission and reception of data is double buffered A 16 bit baud rate generator provides the SSC with a separate serial clock signal The high speed synchronous serial interface can be configured in a very flexible way so it can be used with other synchronous serial interfaces e g the ASCO in synchronous mode serve for master slave or multimaster interconnections or operate compatible with the popular SPI interface So it can be used to communicate with shift registers IO expansion peripherals e g EEPROMs etc or other controllers networking The SSC supports half duplex and full duplex communication Data is transmitted or received on pins MTSR P3 9 Master Transmit Slave Receive and MRST P3 8 Master Receive Slave Transmit The clock signal is output or input on pin SCLK P3 13 These pins are alternate functions of Port 3 pins Po
164. 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL2 Address Select Register 2 SFR FE1Ap 0Dp Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL3 Address Select Register 3 SFR FE1C 0Ey Reset Value 00004 15 14 43 12 11 10 9 8 7 6 5 4 3 2 1 0 RGSAD RGSZ rw rw ADDRSEL4 Address Select Register 4 SFR FE1E 0OF Reset Value 00004 15 14 13 12 11 10 9 8 7 B 5 4 3 2 f 0 RGSAD RGSZ rw rw Bit Function RGSZ Range Size Selection Defines the size of the address area controlled by the respective BUSCONx ADDRSELx register pair See Table 9 6 RGSAD Range Start Address Defines the upper bits of the start address of the respective address area See Table 9 6 User s Manual 9 25 V2 0 2000 07 d nfineon ed technologies Derivatives The External Bus Interface Note There is no register ADDRSELO as register BUSCONO controls all external accesses outside the four address windows of BUSCONA BUSCON1 within the complete address space Definition of Address Areas The four register pairs BUSCON4 ADDRSEL4 BUSCON1 ADDRSEL1 allow to define 4 separate address areas within the address space of the C167CS Within each of these address areas external accesses can be controlled by one of the four different bus modes independent of each other and of the bus mode specified in register BUSCONO Each ADDRSELx register in a way cuts out an address window within which the paramet
165. 167CS s memory areas after reset in bootstrap loader mode differs from the standard case Pin EA does not select the code source in BSL mode and accesses to the internal code memory are partly redirected while the C167CS is in BSL mode see Table 15 1 All code fetches are made from the special Boot ROM while data accesses read from the internal code memory Data accesses will return undefined values on ROMless devices Note The code in the Boot ROM is not an invariant feature of the C167CS User software should not try to execute code from the internal ROM area while the BSL mode is still active as these fetches will be redirected to the Boot ROM The Boot ROM will also move to segment 1 when the internal ROM area is mapped to segment 1 Table 15 1 BSL Memory Configurations 16 MBytes 16 MBytes 16 MBytes LC LC LC LC LC LC kl Access to Access to kl Depends external external on reset bus bus config 1 disabled 1 enabled 1 EA PO Int Int Int RM L 2 RM L 2D ram L 2D i i I O O Access to O O Access to O Depends RD int ROM RD int ROM on reset 3 9 enabled 9 9 enabled 9 config co gt co gt 5 MCA04383 MCA04384 MCA04385 BSL mode active Yes Yes No EA pin high low acc to application Code fetch from internal ROM area Boot ROM access Boot ROM access User ROM access Data fetch from internal ROM area User ROM access
166. 167CS system control instructions User s Manual 4 2 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU A set of Special Function Registers is dedicated to the functions of the CPU core General System Configuration SYSCON RPOH CPU Status Indication and Control PSW Code Access Control IP CSP e Data Paging Control DPPO DPP1 DPP2 DPP3 GPRs Access Control CP System Stack Access Control SP STKUN STKOV Multiply and Divide Support MDL MDH MDC ALU Constants Support ZEROS ONES 4 1 Instruction Pipelining The instruction pipeline of the C167CS partitiones instruction processing into four stages of which each one has its individual task 15 _ FETCH In this stage the instruction selected by the Instruction Pointer IP and the Code Segment Pointer CSP is fetched from either the internal ROM internal RAM or external memory 2nd DECODE In this stage the instructions are decoded and if required the operand addresses are calculated and the respective operands are fetched For all instructions which implicitly access the system stack the SP register is either decremented or incremented as specified For branch instructions the Instruction Pointer and the Code Segment Pointer are updated with the desired branch target address provided that the branch is taken 3 d gt EXECUTE In this stage an operation is performed on the previously fetched operand
167. 19IC b F1664 E B3 CAPCOM Register 19 Interrupt Ctrl Reg 0000 CC20IC b F1684 E B44 CAPCOM Register 20 Interrupt Ctrl Reg 0000 CC21IC b F16A E B5 CAPCOM Register 21 Interrupt Ctrl Reg 0000 CC221C b F16C4 E B6 CAPCOM Register 22 Interrupt Ctrl Reg 0000 CC23IC b F16E4 E B7 CAPCOM Register 23 Interrupt Ctrl Reg 0000 CC24C b F170 E B8 CAPCOM Register 24 Interrupt Ctrl Reg 0000 CC25IC b F172 E B9 CAPCOM Register 25 Interrupt Ctrl Reg 0000 CC26lC b F1744 E BA CAPCOM Register 26 Interrupt Ctrl Reg 0000 CC27IC b F1764 E BB CAPCOM Register 27 Interrupt Ctrl Reg 0000 CC28IC b F1784 E BC CAPCOM Register 28 Interrupt Ctrl Reg 00004 T7IC b F17Ay E BDy CAPCOM Timer 7 Interrupt Ctrl Reg 0000 User s Manual 23 16 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value T8IC b F17Cp EJBE CAPCOM Timer 8 Interrupt Ctrl Reg 0000 PWMIC b F1i7E E BF PWM Module Interrupt Control Register 0000 CC29IC b F1844 E C24 CAPCOM Register 29 Interrupt Ctrl Reg 00004 XPOIC b F186 E C3 4 CAN I Interrupt Control Register 00004 CC30IC b F18C4 E C64 CAPCOM Register 30 Interrupt Ctrl Reg 00004 XP1IC b F18E E C7y4 CAN Interrupt Control Registe
168. 2 SOEIC SORIC SOTIC SOTBIC 11 15 SORBUF 11 7 11 9 SOTBUF 11 7 11 9 Security Mechanism 21 22 Segment Address 9 9 20 18 boundaries 3 12 Segmentation 4 20 Enable Disable 4 15 Serial Interface 2 13 11 1 Asynchronous 11 5 CAN 2 14 19 1 Synchronous 11 8 12 1 SFR 3 8 23 4 23 14 Sharing X Peripherals 9 40 Single Chip Mode 9 2 startup configuration 20 20 Single shot mode PWM 17 8 Slave mode External bus 9 35 Sleep Mode 21 5 Slow Down Mode 21 10 Software Reset 20 3 system configuration 20 22 User s Manual Keyword Index Traps 5 31 Source Interrupt 5 2 Reset 13 6 SP 4 27 Special operation modes config 20 16 SSC 12 1 Baudrate generation 12 13 Error Detection 12 15 Full Duplex 12 7 Half Duplex 12 10 SSCBR 12 13 SSCCON 12 2 12 4 SSCEIC SSCRIC SSCTIC 12 17 SSCRB SSCTB 12 8 Stack 3 5 4 27 22 4 Startup Configuration 20 7 20 12 external reset 20 13 single chip 20 20 via software 20 22 STKOV 4 28 STKUN 4 29 Subroutine 22 10 Synchronous Serial Interface gt SSC 12 1 SYSCON 4 13 9 20 SYSCON1 21 6 SYSCON2 21 12 SYSCONS 21 15 T TO1CON 16 5 T2CON 10 12 T2IC T3IC T4IC 10 21 T3CON 10 3 T4CON 10 12 T5CON 10 30 T5IC T6IC 10 38 T6CON 10 24 T78CON 16 5 T7IC 16 9 T8IC 16 9 TFR 5 33 26 5 V2 0 2000 07 j e nfineon technologies C167CS Derivatives Threshold 7 2 Timer 2 16 10 1 10 22 Auxiliary Timer 10 12 10 30 CAPCOM 16 4 Concatenation 10 16 10 33 Core Time
169. 2 Baud 1 333 MBaud 20 MHz 305 Baud 2 500 MBaud 203 Baud 1 666 MBaud 25 MHz 381 Baud 3 125 MBaud 254 Baud 2 083 MBaud 33 MHz 504 Baud 4 125 MBaud 336 Baud 2 750 MBaud User s Manual 11 14 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface 11 5 ASCO Interrupt Control Four bit addressable interrupt control registers are provided for serial channel ASCO Register SOTIC controls the transmit interrupt SOTBIC controls the transmit buffer interrupt SORIC controls the receive interrupt and SOEIC controls the error interrupt of serial channel ASCO Each interrupt source also has its own dedicated interrupt vector SOTINT is the transmit interrupt vector SOTBINT is the transmit buffer interrupt vector SORINT is the receive interrupt vector and SOEINT is the error interrupt vector The cause of an error interrupt request framing parity overrun error can be identified by the error status flags in control register SOCON Note In contrast to the error interrupt request flag SOEIR the error status flags SOFE SOPE SOOE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software mis Tx Intr Ctrl Reg SFR FF6C B6 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SB a ILVL GLVL wh rw rw rw SOTBIC ASC
170. 24 capture input CC27 CC24 P8 7 0 CC23 161O CAPCOM register 23 16 capture input CC23 CC16 P2 15 0 CC15 01O CAPCOM register 15 0 capture input CC15 CCO P3 7 T2IN Auxiliary timer T2 input pin T2CON P3 5 T4IN Auxiliary timer T4 input pin T4CON P3 2 CAPIN GPT2 capture input pin T5CON When port pins CCxIO are to be used as external interrupt input pins bit field CCMODx in the control register of the corresponding capture compare register CCx must select capture mode When CCMODx is programmed to 001g the interrupt request flag CCxIR in register CCxIC will be set on a positive external transition at pin CCxlO When CCMODx is programmed to 010g a negative external transition will set the interrupt request flag When CCMODx 011g both a positive and a negative transition will set User s Manual 5 26 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions the request flag In all three cases the contents of the allocated CAPCOM timer will be latched into capture register CCx independent whether the timer is running or not When the interrupt enable bit CCxIE is set a PEC request or an interrupt request for vector CCxINT will be generated Pins T2IN or T4IN can be used as external interrupt input pins when the associated auxiliary timer T2 or T4 in block GPT1 is configured for capture mode This mode is selected by programming the mode control fields T2M or T4M in control registers
171. 3 Data Page Ptr Code Seg Ptr MCB02147 Figure 4 1 CPU Block Diagram User s Manual 4 1 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU If possible the CPU continues operating while an external memory access is in progress If external data are required but are not yet available or if a new external memory access is requested by the CPU before a previous access has been completed the CPU will be held by the EBC until the request can be satisfied The EBC is described in a dedicated chapter The on chip peripheral units of the C167CS work nearly independent of the CPU with a separate clock generator Data and control information is interchanged between the CPU and these peripherals via Special Function Registers SFRs Whenever peripherals need a non deterministic CPU action an on chip Interrupt Controller compares all pending peripheral service requests against each other and prioritizes one of them If the priority of the current CPU operation is lower than the priority of the selected peripheral request an interrupt will occur Basically there are two types of interrupt processing Standard interrupt processing forces the CPU to save the current program status and the return address on the stack before branching to the interrupt vector jump table PEC interrupt processing steals just one machine cycle from the current CPU activity to perform a single data
172. 3 11 ms 20 MHz fCPU E 1 0 fcpu 128 1 64 ms 211 4 ms 419 4 ms 1 1 fcpu 256 3 28 ms 422 7 ms 838 9 ms 0 0 fcpu 2 20 48 us 2 64 ms 5 24 ms 0 1 4 40 96 s 5 28 ms 10 49 ms 25 MHz foru E 1 0 fcpu 128 1 31 ms 169 1 ms 335 5 ms 1 1 fopy 256 2 62 ms 338 2 ms 671 1 ms 0 0 fopu 2 15 52 us 2 00 ms 3 97 ms 0 1 4 31 03 s 4 00 ms 7 94 ms 33 MHz JoPu a 1 0 fcpu 128 0 99 ms 128 1 ms 254 2 ms 1 1 fcpu 256 1 99 ms 256 2 ms 508 4 ms Note For safety reasons the user is advised to rewrite WDTCON each time before the watchdog timer is serviced User s Manual 13 5 V2 0 2000 07 o nfineon ed technologies Derivatives The Watchdog Timer WDT 13 2 Reset Source Indication The reset indication flags in register WDTCON provide information on the source for the last reset As the C167CS starts executing from location 00 0000 after any possible reset event the initialization software may check these flags in order to determine if the recent reset event was triggered by an external hardware signal via RSTIN by software itself or by an overflow of the watchdog timer The initialization and also the further operation of the microcontroller system can thus be adapted to the respective circumstances e g a special routine may verify the software integrity after a watchdog timer reset The reset indication flags are not mutually exclusive i e more than one flag may be set after reset
173. 3 35 S B3B5 10 999s FFEC 1 024ms 8 MHz Main 32 0 us 2 10s 85EE 1 000s FFE1 0 992ms 10 MHz Main 25 6 us 1 68 s 676A 0 999s FFD9 0 998 ms 12 MHz Main 21 3 us 1 40s 48E5 1 000s FFD2 1 003ms 16 MHz Main 16 0 us 1 05s OBDC 1 000s FFC2 0 992ms Increased RTC Accuracy through Software Correction The accuracy of the C167CS s RTC is determined by the oscillator frequency and by the respective prescaling factor excluding or including T14 The accuracy limit generated by the prescaler is due to the quantization of a binary counter where the average is zero while the accuracy limit generated by the oscillator frequency is due to the difference between ideal and real frequency and therefore accumulates over time The total accuracy of the RTC can be further increased via software for specific applications that demand a high time accuracy The key to the improved accuracy is the knowledge of the exact oscillator frequency The relation of this frequency to the expected ideal frequency is a measure for the RTC s deviation The number N of cycles after which this deviation causes an error of 1 cycle can be easily computed So the only action is to correct the count by 1 after each series of N cycles This correction may be applied to the RTC register as well as to T14 Also the correction may be done cyclic e g within T14 s interrupt service routine or by evaluating a formula when the RTC reg
174. 33 MHz SSCBR Reserved SSCBR must be gt 0 0000 4 00 MBaud 5 00 MBaud 6 25 MBaud 8 25 MBaud 0001 2 67 MBaud 3 33 MBaud 4 17 MBaud 5 50 MBaud 0002 2 00 MBaud 2 50 MBaud 3 13 MBaud 4 13 MBaud 0003 1 60 MBaud 2 00 MBaud 2 50 MBaud 3 30 MBaud 0004 1 00 MBaud 1 25 MBaud 1 56 MBaud 2 06 MBaud 0007 800 KBaud 1 0 MBaud 1 25 MBaud 1 65 MBaud 0009 100 KBaud 125 KBaud 156 KBaud 206 KBaud 004Fy 80 KBaud 100 KBaud 125 KBaud 165 KBaud 0063 64 KBaud 80 KBaud 100 KBaud 132 KBaud 007Cy 48 5 KBaud 60 6 KBaud 75 8 KBaud 100 KBaud 00A4j 1 0 KBaud 1 25 KBaud 1 56 KBaud 2 06 KBaud 1F3Fy 800 Baud 1 0 KBaud 1 25 KBaud 1 65 KBaud 270Fy 640 Baud 800 Baud 1 0 KBaud 1 32 KBaud 30D3 122 1 Baud 152 6 Baud 190 7 Baud 251 7 Baud FFFFy User s Manual 12 14 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 6 Error Detection Mechanisms The SSC is able to detect four different error conditions Receive Error and Phase Error are detected in all modes while Transmit Error and Baudrate Error only apply to slave mode When an error is detected the respective error flag is set When the corresponding Error Enable Bit is set also an error interrupt request will be generated by setting SSCEIR see Figure 12 6 The error interrupt handler may then check the error flags to determine the cause of the error interrupt The error flags are not reset
175. 4 P1L P1H PORT1 Data Register BUSCONx Bus Mode Control Register 0 4 DP3 Port 3 Direction Control Register SYSCON System Control Register P3 Port 3 Data Register RPOH Port POH Reset Configuration Register P4 Port 4 Data Register ODP6 Port 6 Open Drain Control Register DP6 Port 6 Direction Control Register P6 Port 6 Data Register MCA04367 Figure 9 1 SFRs and Port Pins Associated with the External Bus Interface Accesses to external memory or peripherals are executed by the integrated External Bus Controller EBC The function of the EBC is controlled via the SYSCON register and the BUSCONx and ADDRSELx registers The BUSCONXx registers specify the external bus cycles in terms of address mux demux data width 16 bit 8 bit chip selects and length waitstates READY control ALE RW delay These parameters are used for accesses within a specific address area which is defined via the corresponding register ADDRSELx The four pairs BUSCON1 ADDRSEL1 BUSCON4 ADDRSEL4 allow to define four independent address windows while all external accesses outside these windows are controlled via register BUSCONO User s Manual 9 1 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 1 Single Chip Mode Single chip mode is entered when pin EA is high during reset In this case register BUSCONO is initialized with 00CO which also resets bit BUSACTO so no external bus is enabled In single c
176. 4 13 12 11 10 9 8 7 6 9 4 3 2 1 0 read empty for byte registers std hw write d M bitfield bit rw wh rw r Ww rw Bit Function bit field name Explanation of bit field name Description of the functions controlled by the different possible values of this bit field Elements REG_NAME Short name of this register A16 A8 Long 16 bit address Short 8 bit address SFR ESFR XReg Register space SFR ESFR or External XBUS Register Register contents after reset 0 1 defined value X undefined U unchanged undefined X after power up rw Access modes can be read and or write xh Bits that are set cleared by hardware are marked with a shaded access box and an h in it User s Manual 23 1 V2 0 2000 07 o nfineon technologies 23 2 C167CS Derivatives CPU General Purpose Registers GPRs The Register Set The GPRs form the register bank that the CPU works with This register bank may be located anywhere within the internal RAM via the Context Pointer CP Due to the addressing mechanism GPR banks can only reside within the internal RAM All GPRs are bit addressable Table 23 1 General Purpose Word Registers Name Physical 8 bit Description Reset Address Address Value RO CP 0 FO CPU General Purpose Word Reg RO UUUU H1 CP 2 Fiy CPU G
177. 4 PWM timers simultaneously with one bitfield instruction PWMCONO PWM Control Register 0 SFR FF30 984 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIR PIR PIR PIR PIE PIE PIE PIE PTI PTI PTI PTI PTR PTR PTR PTR 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 rwh rwh rwh rwh rw rw rw rw rw rw rw rw rwh rwh rw rw Bit Function PTRx PWM Timer x Run Control Bit 0 Timer PTx is disconnected from its input clock LE Timer PTx is running PTIx PWM Timer x Input Clock Selection 0 Timer PTx clocked with CLKcpy 1 Timer PTx clocked with CLKcpy 64 PIEx PWM Channel x Interrupt Enable Flag 0 Interrupt from channel x disabled 1 Interrupt from channel x enabled PIRx PWM Channel x Interrupt Request Flag 0 No interrupt request from channel x T1 Channel x interrupt pending must be reset via software User s Manual 17 12 V2 0 2000 07 o nfineon es technologies Derivatives The Pulse Width Modulation Module PWM Control Register PWMCON1 Register PWMCON1 controls the operating modes and the outputs of the four PWM channels The basic operating mode for each channel standard edge aligned or symmetrical center aligned PWM mode is selected by the mode bits PMx Burst mode channels 0 and 1 and single shot mode channel 2 or 3 are selected by separate control bits The output signal of each PWM channel is individually ena
178. 464 CAPCOM Register 6 0000 CC7 FE8E 474 CAPCOM Register 7 00004 CC8 FE90 48 CAPCOM Register 8 00004 CC9 FE92 49 CAPCOM Register 9 00004 CC10 FE94 4A CAPCOM Register 10 0000 CC11 FE96 4B CAPCOM Register 11 0000 CC12 FE98 4Cy CAPCOM Register 12 00004 CC13 FE9A 4Dy CAPCOM Register 13 00004 CC14 FE9C 4E 4 CAPCOM Register 14 0000 CC15 FE9E 4Fy CAPCOM Register 15 00004 ADDAT FEAO 1504 A D Converter Result Register 0000 P1DIDIS FEA4 1524 PORT1 Digital Input Disable Register 0000 User s Manual 23 19 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value WDT FEAE 1574 Watchdog Timer Register read only 00004 SOTBUF FEBO 584 Serial Channel 0 Transmit Buffer Register 00004 SORBUF FEB2 594 Serial Channel 0 Receive Buffer Register XXXXy read only SOBG FEBA4 5Ay_ Serial Channel 0 Baud Rate Generator 00004 Reload Register PECCO FECO 604 PEC Channel 0 Control Register 0000 PECC1 FEC2 614 PEC Channel 1 Control Register 00004 PECC2 FEC4 624 PEC Channel 2 Control Register 0000 PECC3 FEC6 634 PEC Channel 3 Control Register 0000 PECCA FEC8 644 PEC Channel 4 Control Register 00004 PECC5 FECA 654 PEC Channel 5 Control Registe
179. 4lC b FF94 CAy CAPCOM Register 14 Interrupt Ctrl Reg 00004 CC15lIC b FF96 CBy CAPCOM Register 15 Interrupt Ctrl Reg 0000 ADCIC b FF98 CC A D Converter End of Conversion Interrupt 00004 Control Register ADEIC b FF9A CDy A D Converter Overrun Error Interrupt 0000 Control Register TOIC b FF9C CEy CAPCOM Timer 0 Interrupt Ctrl Reg 00004 T1lIC b FF9E CFy CAPCOM Timer 1 Interrupt Ctrl Reg 0000 ADCON b FFA0 DOW A D Converter Control Register 00004 P5 b FFA2 Dip Port 5 Register read only XXXXy P5DIDIS b FFA4 D24 Port 5 Digital Input Disable Register 0000 FOCON b FFAA D54 Frequency Output Control Register 00004 TFR b FFAC D6 Trap Flag Register 0000 WDTCON b FFAE D7 _ Watchdog Timer Control Register 2 00xx SOCON b FFBO0j D84 Serial Channel 0 Control Register 00004 SSCCON b FFB2j D94 SSC Control Register 00004 User s Manual 23 22 V2 0 2000 07 e nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value P2 b FFCO E0 Port 2 Register 0000 DP2 b FFC2 Ely Port2 Direction Control Register 00004 P3 b FFC4 E2 Port 3 Register 0000 DP3 b FFC6 E34 Port 3 Direction Control Register 00004 P4 b FFC8 E44 Port 4 Register 7 bits 004 DP4 b FFCA E54 Port 4 Direction Contr
180. 5 Controlling the External Bus Controller A set of registers controls the functions of the EBC General features like the usage of interface pins WR BHE segmentation and internal ROM mapping are controlled via register SYSCON The properties of a bus cycle like chip select mode usage of READY length of ALE external bus mode read write delay and waitstates are controlled via registers BUSCON4 BUSCONO Four of these registers BUSCONA BUSCON 1 have an address select register ADDRSEL4 ADDRSEL1 associated with them which allows to specify up to four address areas and the individual bus characteristics within these areas All accesses that are not covered by these four areas are then controlled via BUSCONO This allows to use memory components or peripherals with different interfaces within the same system while optimizing accesses to each of them SYSCON System Control Register SFR FF12 894 Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 O BD ROM SGT ROM BYT CLK WR CS OWD VISI XPER STKSZ 1 DIS EN DIS EN CFG CFG DIS BST XPEN BLE SHARE rw rw rw wh rwh rw rwh rw mh rw w rw rw Bit Function XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the ext bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals ar
181. 5 is cleared after the current timer value has been latched into register CAPREL Note Bit T5SC only controls whether a capture is performed or not If T5SC 0 the selected trigger event can still be used to clear timer T5 or to generate an interrupt request This interrupt is controlled by the CAPREL interrupt control register CRIC GPT2 Capture Reload Register CAPREL in Reload Mode This 16 bit register can be used as a reload register for the core timer T6 This mode is selected by setting bit T6SR 1 in register T6CON The event causing a reload in this mode is an overflow or underflow of the core timer T6 When timer T6 overflows from FFFF to 0000 when counting up or when it underflows from 0000 to FFFFy when counting down the value stored in register CAPREL is loaded into timer T6 This will not set the interrupt request flag CRIR associated with the CAPREL register However interrupt request flag T6IR will be set indicating the overflow underflow of T6 CAPREL Register v en 4r Den T6SR T6OE Input Interrupt Clock Core Timer T6 Request Up Down MCB02045 Figure 10 23 GPT2 Register CAPREL in Reload Mode User s Manual 10 35 V2 0 2000 07 o nfineon ed technologies Derivatives The General Purpose Timer Units GPT2 Capture Reload Register CAPREL in Capture And Reload Mode Since the reload function and the capture function of register CAPREL can be enabled individu
182. 6 allowing access to 256 KByte Note The selected number of segment address lines can be changed via software after reset see Section 20 4 2 User s Manual 20 18 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Clock Generation Control Pins POH 7 POH 6 and POH 5 CLKCFG select the basic clock generation mode during reset The oscillator clock either directly feeds the CPU and peripherals direct drive it is divided by 2 or it is fed to the on chip PLL which then provides the CPU clock signal selectable multiple of the oscillator frequency i e the input frequency These bits are latched in register RPOH Table 20 6 C167CS Clock Generation Modes POH 7 5 CPU Frequency External Clock Notes CLKCFG fcpu fosc x F Input Rang 11 1 Josc x 4 2 5 to 8 25 MHz Default configuration 110 fosc x 3 3 33 to 11 MHz 10 1 fosc x 2 5 to 16 5 MHz 100 fosc x 5 2 to 6 6 MHz 0 1 1 fosc x 1 1 to 33 MHz Direct drive 010 fosc x 1 5 6 66 to 22 MHz 00 1 fosc 2 2 to 66 MHz CPU clock via prescaler 000 fosc x 2 5 4 to 13 2 MHz LI The external clock input range refers to a CPU clock range of 10 33 MHz The maximum frequency depends on the duty cycle of the external clock signal In emulation mode pin P0 15 POH 7 is inverted i e the configuration 111 would select direct drive in emulation mode Default On chip PLL is active w
183. 6 Bit Input Output Demux Bus Demux Bus MUX Bus MUX Bus MCA04344 Figure 7 6 PORTO IO and Alternate Functions While external bus cycles are executed PORTO is controlled by the bus controller The port direction is determined by the type of the bus cycle the data are transferred directly from to the bus controller hardware The alternate output data can be the 16 bit intrasegment address or the 8 16 bit data information While PORTO is not used by the bus controller it is controlled by its direction and output latch registers User software must therefore be very careful when writing to PORTO registers while the external bus is enabled In most cases keeping the reset values will be the best choice Figure 7 7 shows the structure of a PORTO pin User s Manual 7 14 V2 0 2000 07 j e i C167CS Infineon Baa Parallel Ports Internal Bus Write Read Port Output Direction Latch Latch 0 AltDir AItEN Pin 0 AltDataOut M J Driver Clock AltDatalN lt o Input Latch MCB04345 POH 7 0 POL 7 0 Figure 7 7 Block Diagram of a PORTO Pin User s Manual 7 15 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 5 PORT1 The two 8 bit ports P1H and P1L represent the higher and lower part of PORT1 respectively Both halfs of PORT1 can be written e g via a PEC transfer without effecting the other half If th
184. 6 The Second CAN Module CAN2 Module CAN is basically identical with module CAN1 It provides the same set of message objects operating modes and registers While the number sequence and function of the CAN registers are exactly the same as in module CAN1 module CAN2 of course resides in a separate address window Table 19 2 CAN Register Summary Register Locations in Module CAN2 Register Locations in Module CAN1 C2CSR EEO0 C1CSR EFOO C2PCIR EE02 C1PCIR EF02 C2BTR EFE04 C1BTR EFO4 C2GMS EE06 C1GMS EFO6 C2UGML EE08 C1UGML EF08 C2LGML EEOA C1LGML EFOA C2UMLM EEOC C1UMLM EFOCy C2LMLM EEOE C1LMLM EFOE C2MCRn EEn0y C1MCRn EFn0y C2UARn EEn2y C1UARn EFn2y C2LARn EEn4y C1LARn EFn4j C2MCFGn EEn6j C1MCFGn EFn6y Data area CAN2 EEn j EEnBg Data area CAN1 EFn7y EFnEy The on chip interrupt generation works in exactly the same way as in module CAN1 Module CAN2 is connected to a separate interrupt node So each CAN module can be accessed and serviced independently Table 19 3 CAN Interrupt Connection Module Interrupt Node Interrupt Flag Interrupt Vector CAN1 XPOIC XPOIR XPOINT CAN2 XP11C XP1IR XP1INT It also uses a separate physical interface Section 19 7 User s Manual to connect to an external CAN bus see 19 37 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 7 The CAN Ap
185. 7 76 us minimum auto scan modes channel injection mode Two 16 channel Capture Compare Units with 2 independent time bases each very flexible PWM unit event recording unit with different operating modes includes four 16 bit timers counters maximum resolution fcpy 8 e 4 channel PWM unit Two Multifunctional General Purpose Timer Units GPT1 Three 16 bit timers counters maximum resolution fcpy 8 GPT2 Two 16 bit timers counters maximum resolution fcpy 4 Asynchronous Synchronous Serial Channels USART with baud rate generator parity framing and overrun error detection High Speed Synchronous Serial Channel programmable data length and shift direction Two on chip CAN Bus Modules Rev 2 0B active Real Time Clock e Watchdog Timer with programmable time intervals Bootstrap Loader for flexible system initialization 111 IO Lines with Individual Bit Addressability e Tri stated in input mode Selectable input thresholds not on all pins Push pull or open drain output mode Programmable port driver control Different Temperature Ranges e Oto 70 C 40 to 85 C 40 to 125 C User s Manual 1 5 V2 0 2000 07 o nfineon oi technologies Derivatives Introduction Infineon CMOS Process Low power CMOS technology including power saving Idle and Power Down modes 144 pin Plastic Metric Quad Flat Pack MQFP Package P MQFP 28 x 28 mm body 0 65 mm 25 6 mil lead spacing surface mount te
186. 74 BA SSC Receive Interrupt Control Register 00004 SSCTB FOBO E 584 SSC Transmit Buffer 0000 SSCTIC b FF724 B9 SSC Transmit Interrupt Control Register 0000 STKOV FE144 OA CPU Stack Overflow Pointer Register FAOOW STKUN FE16 OB CPU Stack Underflow Pointer Register FCOO SYSCON b FF124 89 CPU System Configuration Register 1 0xx0 SYSCON1 b F1DC E EE CPU System Configuration Register 1 0000 SYSCON2 b F1DO E E8j CPU System Configuration Register 2 0000 SYSCONS3 b F1D4 E EA CPU System Configuration Register 3 0000 TO FE50 28 CAPCOM Timer 0 Register 0000 TO1CON b FF504 A84 CAPCOM Timer 0 and Timer 1 Ctrl Reg 00004 User s Manual 23 11 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value TOIC b FF9C CEy CAPCOM Timer 0 Interrupt Ctrl Reg 0000 TOREL FE54 2Ay CAPCOM Timer 0 Reload Register 0000 T1 FE52y 294 CAPCOM Timer 1 Register 00004 T14 FOD2 E 694 RTC Timer 14 Register XXXXy T14REL FODO E 684 RTC Timer 14 Reload Register XXXXy T1IC b FF9E CFy CAPCOM Timer 1 Interrupt Ctrl Reg 00004 T1REL FE564 2By CAPCOM Timer 1 Reload Register 0000 T2 FE40 204 GPT1 Timer 2 Register 00004 T2CON b FF404 AO GPT1 Timer 2 Control Regist
187. 74 Port P6 Output Control Register 0000 POCON7 F090 E 484 Port P7 Output Control Register 0000 User s Manual 23 15 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value POCONG F092 E 494 Port P8 Output Control Register 00004 ADDAT2 FOAO E 504 A D Converter 2 Result Register 00004 POCON20 FOAA p E 554 Dedicated Pin Output Control Register 0000 SSCTB FOBO E 584 SSC Transmit Buffer 00004 SSCRB FOB2 E59 SSC Receive Buffer XXXXy SSCBR FOB4 E 5Ay SSC Baudrate Register 0000 T14REL FODO E 68 RTC Timer 14 Reload Register XXXXy T14 FOD2y E 694 RTC Timer 14 Register XXXXy RTCL FOD4 E 6Ay_ RTC Low Register XXXXy RTCH FOD6 E 6By RTC High Register XXXXy DPOL b F100 E804 POL Direction Control Register 004 DPOH b F102 E 81 POH Direction Control Register 001 DP1L b F1044 E82 P1L Direction Control Register 004 DP1H b F1064 E83 P1H Direction Control Register 004 RPOH b F108 E 84 System Startup Configuration Register XXy read only CC16IC b F1604 E BO CAPCOM Register 16 Interrupt Ctrl Reg 0000 CC17IC b F1624 E B1 CAPCOM Register 17 Interrupt Ctrl Reg 0000 CC18IC b F1644 E B2 CAPCOM Register 18 Interrupt Ctrl Reg 00004 CC
188. 7IN T7IN P2 14 CC14lO EX6IN P2 13 CC13lO EX5IN P2 12 CC12lO EX4IN P2 11 CC111O EX3IN P2 10 CC1010 EX2IN P2 9 CC9IO EX1IN P2 8 CC8lO EXOIN Pot2 la Lp27 CC7IO P2 6 CC6lO P2 5 CC5IO P2 4 CC4IO P2 3 CC3IO P2 2 CC2lO P2 1 CC1IO P2 0 CCOIO General Purpose CAPCOM 1 Fast External CAPCOM2 Input Output Capt Inp Comp Output Interrupt Input Timer T7 Input MCA04349 Figure 7 12 Port 210 and Alternate Functions User s Manual 7 26 V2 0 2000 07 e Infineon iis technologies Derivatives Parallel Ports The pins of Port 2 combine internal bus data and alternate data output before the port latch input Internal Bus 9o 2 o e o Eg zog zog Sa Sc Direction Latch Port Output Latch Pin Driver AltDataln Latch lt Clock AltDataln Pin lt e o Input EXZIN Latch 4 MCB04350 P2 15 0 x 2 15 0 z 7 0 Figure 7 13 Block Diagram of a Port 2 Pin Note Fast external interrupt inputs only on the upper eight pins of Port2 User s Manual 7 27 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 7 Port 3 If this 15 bit port is used for general purpose IO the direction of each line can be configured via the corresponding direction register DP3 Most port lines can be switched into push pull or open drain mode via the open drain control register ODP3 pins P3 15 and P3
189. A04371 Figure 10 1 SFRs and Port Pins Associated with Timer Block GPT1 User s Manual 10 1 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units All three timers of block GPT1 T2 T3 T4 can run in 4 basic modes which are timer gated timer counter and incremental interface mode and all timers can either count up or down Each timer has an alternate input function pin TxIN associated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software or may be dynamically altered by a signal at an external control input pin Each overflow underflow of core timer T3 is latched in the toggle FlipFlop T3OTL and may be indicated on an alternate output function pin The auxiliary timers T2 and T4 may additionally be concatenated with the core timer or used as capture or reload registers for the core timer The current contents of each timer can be read or modified by the CPU by accessing the corresponding timer registers T2 T3 or T4 which are located in the non bitaddressable SFR space When any of the timer registers is written to by the CPU in the state immediately before a timer increment decrement reload or capture is to be performed the CPU write operation has priority in order to guarantee correct results U D Jti T2 GPT1 Timer T2 Interrup
190. AM and organizational page segment memory area User s Manual 3 2 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization 3 1 Internal ROM Area The C167CS may reserve an address area of variable size depending on the version for on chip mask programmable ROM Flash OTP memory organized as X x 32 The lower 32 KByte of this on chip memory block are referred to as Internal ROM Area Internal ROM accesses are globally enabled or disabled via bit ROMEN in register SYSCON This bit is set during reset according to the level on pin EA or may be altered via software If enabled the internal ROM area occupies the lower 32 KByte of either segment 0 or segment 1 alternate ROM area This mapping is controlled by bit ROMS1 in register SYSCON Note The size of the internal ROM area is independent of the size of the actual implemented Program Memory Also devices with less than 32 KByte of Program Memory or with no Program Memory at all will have this 32 KByte area occupied if the Program Memory is enabled Devices with a larger Program Memory provide the mapping option only for the internal ROM area Devices with a Program Memory size above 32 KByte expand the ROM area from the middle of segment 1 i e starting at address 01 8000 The internal Program Memory can be used for both code instructions and data constants tables etc storage Code fetches are always made on even byte addresses The highe
191. AN TXD Notes 000 P4 5 P4 4 P4 6 P4 7 Module specific assignments CAN1 CAN2 001 P4 7 P4 6 Pins P4 5 0 available for segment address lines A21 A16 4 MByte external address space 010 P8 0 P8 1 Port 4 available for segment address lines A23 A16 16 MByte external address space 011 P82 P8 3 Port 4 available for segment address lines A23 A16 16 MByte external address space 100 Reserved Do not use this combination 101 Reserved Do not use this combination 110 Reserved Do not use this combination 111 Idle Disconnected No port assigned Default after Reset recessive 1 This assignment is compatible with previous derivatives where the assignment of CAN interface lines was fixed User s Manual 19 40 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface The location of the CAN interface lines can now be selected via software according to the requirements of an application Compatible Assignment IPC 000g makes the C167CS suitable for applications with a given hardware board layout The CAN interface lines are connected to the port pins to which they are hardwired in previous derivatives Wide Address Assignment IPC 001g uses the two upper pins of Port 4 leaving room for six segment address lines A21 A16 A contiguous external address space of 4 MByte is available in this case Full Address Assignment IPC 010g or
192. Allocation Bit for Capture Compare Register CCx 0 CCx allocated to Timer T7 1 CCx allocated to Timer T8 User s Manual 16 11 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units Each of the registers CCx may be individually programmed for capture mode or one of 4 different compare modes and may be allocated individually to one of the two timers of the respective CAPCOM unit TO or T1 and T7 or T8 respectively A special combination of compare modes additionally allows the implementation of a double register compare mode When capture or compare operation is disabled for one of the CCx registers it may be used for general purpose variable storage Table 16 5 Selection of Capture Modes and Compare Modes CCMODx Selected Operating Mode 000 Disable Capture and Compare Modes The respective CAPCOM register may be used for general variable storage 001 Capture on Positive Transition Rising Edge at Pin CCxlO 010 Capture on Negative Transition Falling Edge at Pin CCxlO 0 1 1 Capture on Positive and Negative Transition Both Edges at Pin CCxlO 100 Compare Mode 0 Interrupt Only Several interrupts per timer period Enables double register compare mode for registers CC8 CC15 and CC24 CC31 101 Compare Mode 1 Toggle Output Pin on each Match Several compare events per timer period This mode is required for double register compare mode for registers CCO CC7
193. B Subtraction with Carry of two words or bytes SUBC SUBCB 16 x16 bit signed or unsigned multiplication MUL MULU 16 16 bit signed or unsigned division DIV DIVU e 32 16 bit signed or unsigned division DIVL DIVLU 1 s complement of a word or byte CPL CPLB 2 s complement negation of a word or byte NEG NEGB Logical Instructions Bitwise ANDing of two words or bytes AND ANDB Bitwise ORing of two words or bytes OR ORB Bitwise XORing of two words or bytes XOR XORB Compare and Loop Control Instructions Comparison of two words or bytes CMP CMPB Comparison of two words with post increment by either 1 or 2 CMPI1 CMPI2 Comparison of two words with post decrement by either 1 or 2 CMPD1 CMPD2 User s Manual 24 1 V2 0 2000 07 o nfineon end technologies Derivatives Instruction Set Summary Boolean Bit Manipulation Instructions e Manipulation of a maskable bit field in either the high or the low byte of a word BFLDH BFLDL e Setting a single bit to 1 BSET Clearing a single bit to 0 BCLR e Movement of a single bit BMOV e Movement of a negated bit BMOVN e ANDing of two bits BAND ORing of two bits BOR e XORing of two bits BXOR Comparison of two bits BCMP Shift and Rotate Instructions e Shifting right of a word SHR e Shifting left of a word SHL Rotating right of a word ROR Rotating left of a word ROL Arithmetic shifting right of a word sign b
194. C b FF72 B9 SSC Transmit Interrupt Control Register 0000 SSCRIC b FF74 BA SSC Receive Interrupt Control Register 0000 SSCEIC b FF76j BBy SSC Error Interrupt Control Register 0000 User s Manual 23 21 V2 0 2000 07 o nfineon ed technologies Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value CCOIC b FF78y BC CAPCOM Register 0 Interrupt Ctrl Reg 0000 CC1IC b FF7Ay BDy CAPCOM Register 1 Interrupt Ctrl Reg 00004 CC2IC b FF7Cy BE CAPCOM Register 2 Interrupt Ctrl Reg 0000 CC3IC b FF7Ey BF CAPCOM Register 3 Interrupt Ctrl Reg 00004 CC4IC b FF80 CO CAPCOM Register 4 Interrupt Ctrl Reg 0000 CC5IC b FF82 C14 CAPCOM Register 5 Interrupt Ctrl Reg 0000 CC6IC b FF84 C24 CAPCOM Register 6 Interrupt Ctrl Reg 0000 CC7IC b FF86 C34 CAPCOM Register 7 Interrupt Ctrl Reg 0000 CC8IC b FF88 C44 CAPCOM Register 8 Interrupt Ctrl Reg 00004 CC9IC b FF8A C5 CAPCOM Register 9 Interrupt Ctrl Reg 00004 CC10IC b FF8C C6 CAPCOM Register 10 Interrupt Ctrl Reg 00004 CC11lC b FF8E C7 CAPCOM Register 11 Interrupt Ctrl Reg 0000 CC121C b FF90 C84 CAPCOM Register 12 Interrupt Ctrl Reg 00004 CC13IC b FF92 C94 CAPCOM Register 13 Interrupt Ctrl Reg 0000 CC1
195. C31IC F194 CA ESFR User s Manual 16 23 V2 0 2000 07 o nfineon en technologies Derivatives The Pulse Width Modulation Module 17 The Pulse Width Modulation Module The Pulse Width Modulation PWM Module of the C167CS allows the generation of up to 4 independent PWM signals These PWM signals can be generated within a wide range of output frequencies which depends on e the CPU clock frequency fcpy e the selected counter resolution fcpy 1 or fepy 64 e the operating mode edge center aligned e the required PWM resolution 1 bit 16 bit The maximum PWM output frequency in a real application is primarily determined by the PWM resolution which is required for that application Ports amp Direction Control Data Registers Control Registers Control Registers and Alternate Functions Interrupt Control PWMCONO PWMCON 1 PWMIC E POUTO P7 0 POUT1 P7 1 POUT2 P7 2 POUT3 P7 3 ODP7 Port 7 Open Drain Control Register PPx PWM Period Register x DP7 Port 7 Direction Control Register PWx PWM Pulse Width Register x P7 Port 7 Data Register PTX PWM Counter Register x PWMIC PWM interrupt Control Register PWMCONx PWM Control Register 0 1 MCA04387 Figure 17 1 SFRs and Port Pins Associated with the PWM Module The Pulse Width Modulation Module consists of 4 independent PWM channels Each channel has a 16 bit up down counter PTx a 16 bit period register PPx with a shadow latch a 16 bit pulse width
196. CAN module is controlled by the C167CS via hardware signals e g reset and via register accesses executed by software Accessing the On Chip CAN Module The CAN module is implemented as an X Peripheral and is therefore accessed like an external memory or peripheral That means that the registers of the CAN module can be read and written using 16 bit or 8 bit direct or indirect MEM addressing modes Also bit handling is not supported via the XBUS Since the XBUS to which the CAN module is connected also represents the external bus CAN accesses follow the same rules and procedures as accesses to the external bus CAN accesses cannot be executed in parallel to external instruction fetches or data read writes but are arbitrated and inserted into the external bus access stream Accesses to the CAN module use demultiplexed addresses a 16 bit data bus byte accesses possible two waitstates and no tristate waitstate The CAN address area starts at 00 EFOO and covers 256 Bytes This area is decoded internally so none of the programmable address windows must be sacrificed in order to access the on chip CAN module The advantage of locating the CAN address area in segment 0 is that the CAN module is accessible via data page 3 which is the system data page accessed usually through the system data page pointer DPP3 In this way the internal addresses such like SFRs internal RAM and the CAN registers are all located within the same data pa
197. CAN protocol The BTL synchronizes on a recessive to dominant busline transition at Start of Frame hard synchronization and on any further recessive to dominant busline transition if the CAN controller itself does not transmit a dominant bit resynchronization The BTL also provides programmable time segments to compensate for the propagation delay time and for phase shifts and to define the position of the Sample Point in the bit time The programming of the BTL depends on the baudrate and on external physical delay times Intelligent Memory The Intelligent Memory CAM RAM Array provides storage for up to 15 message objects of maximum 8 data bytes length Each of these objects has a unique identifier and its own set of control and status bits After the initial configuration the Intelligent Memory can handle the reception and transmission of data without further CPU actions Organization of Registers and Message Objects All registers and message objects of the CAN controller are located in the special CAN address area of 256 Bytes which is mapped into segment 0 and uses addresses 00 EFOO0 through OO EFFF All registers are organized as 16 bit registers located on word addresses However all registers may be accessed bytewise in order to select special actions without effecting other mechanisms Register Naming reflects the specific name of a register as well as a general module indicator This results in unique register names E
198. CAPCOM Register 3 CC3IR CC3IE CC3INT 00 004C 13 19p CAPCOM Register 4 CCAIR CC4IE CC4INT 00 00504 14 20p CAPCOM Register 5 CC5IR CC5IE CCBSINT 00 0054 15 21p CAPCOM Register 6 CC6IR CC6IE CC6INT 00 0058 16 22p CAPCOM Register 7 CC7IR CC7IE CC7INT 00 005Cy 17 23p CAPCOM Register 8 CC8IR CC8IE CC8INT 00 0060 18 24p CAPCOM Register 9 CC9IR CC9IE CC9INT 00 0064 19 25p CAPCOM Register 10 CC10IR CC410IE CC10INT 00 0068 1A 26p CAPCOM Register 11 CC11IR CC11IE CC11INT 00 006C4 1Bj 27p CAPCOM Register 12 CC121lR CC12IE CC12INT 00 0070 1C 28p CAPCOM Register 13 CC13IR CC1SIE CC13INT 00 00744 1Dj 29p CAPCOM Register 14 CC14IR CC14IE CC14INT 10000784 1Ej 30p CAPCOM Register 15 CC15IR CC15IE CC15INT 00 007Cy 1Fy 31p CAPCOM Register 16 CC16IR CC16lE CC16lNT 00 00C0 30 48p CAPCOM Register 17 CC17IR CC17IE CC17INT 00 00C4 31 49p CAPCOM Register 18 CC18IR CC18IE CC18INT 00 00C8 32 50p CAPCOM Register 19 CC19IR CC19IE CC19INT 00 00CCj 33 51p CAPCOM Register 20 CC20IR CC20IE CC20INT 00 00DO 34 52p CAPCOM Register 21 CC21IR CC21IE CC21INT 00 00D4 35 53p CAPCOM Register 22 CC22IR CC22lE CC22INT 00 00D8 36 54p CAPCOM Register 23 CC23IR CC23IE CC23INT 00 00DC 37 55p CAPCOM Register 24 CC24IR CC24IE CC24INT 00 00E0 38 56p CAPCOM Register 25 CC25IR CC25IE CC25INT 00 00E4 39 57p CAPCOM Register 26 CC26IR CC26lE CC26INT
199. COM Register 20 0000 CC20IC b F1684 E B44 CAPCOM Register 20 Interrupt Ctrl Reg 0000 CC21 FE6A 354 CAPCOM Register 21 0000 CC21IC b F16A E B5 CAPCOM Register 21 Interrupt Ctrl Reg 0000 CC22 FE6C 1364 CAPCOM Register 22 00004 CC221C b F16C4 E B6 CAPCOM Register 22 Interrupt Ctrl Reg 0000 CC23 FE6E 374 CAPCOM Register 23 00004 CC23IC b F16E E B7 CAPCOM Register 23 Interrupt Ctrl Reg 00004 CC24 FE70y 384 CAPCOM Register 24 00004 CC24C b F170 E B8 CAPCOM Register 24 Interrupt Ctrl Reg 0000 CC25 FE72y 39 CAPCOM Register 25 0000 CC25IC b F172 E B9 CAPCOM Register 25 Interrupt Ctrl Reg 0000 CC26 FE74 3Ay CAPCOM Register 26 0000 CC26lC b F1744 E BA CAPCOM Register 26 Interrupt Ctrl Reg 0000 CC27 FE76y 3By CAPCOM Register 27 00004 CC27IC b F1764 E BB CAPCOM Register 27 Interrupt Ctrl Reg 0000 CC28 FE78y 3C CAPCOM Register 28 00004 User s Manual 23 6 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value CC28IC b F1784 E BC CAPCOM Register 28 Interrupt Ctrl Reg 00004 CC29 FE7A 3Dy CAPCOM Register 29 00004 CC29IC b F1844 E C24 CAPCOM Register 29 Interrupt Ctrl Reg 0000 CC2IC b FF7Cy BE CAPCOM Register 2 Interr
200. CS just below the bit addressable area see Figure 5 2 00 FCFE 00 FCEE 00 FCFC 00 FCEC 00 FCFA 00 FCEA 00 FCF8 00 FCEB8 00 FCF6 00 FCE6 00 FCFA 00 FCEA 00 FCF2 00 FCE2 00 FCFO PESE MCA04331 Figure 5 2 Mapping of PEC Pointers into the Internal RAM User s Manual 5 14 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions PEC data transfers do not use the data page pointers DPP3 DPPO The PEC source and destination pointers are used as 16 bit intra segment addresses within segment 0 so data can be transferred between any two locations within the first four data pages 3 0 The pointer locations for inactive PEC channels may be used for general data storage Only the required pointers occupy RAM locations Note If word data transfer is selected for a specific PEC channel i e BWT 0 the respective source and destination pointers must both contain a valid word address which points to an even byte boundary Otherwise the Illegal Word Access trap will be invoked when this channel is used User s Manual 5 15 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 3 Prioritization of Interrupt and PEC Service Requests Interrupt and PEC service requests from all sources can be enabled so they are arbitrated and serviced if they win or they may be disabled so their requests are disreg
201. Check Register This register generates the Cyclic Redundancy Check CRO code to be transmitted after the data bytes and checks the CRC code of incoming messages This is done by dividing the data stream by the code generator polynomial Error Management Logic The Error Management Logic EML is responsible for the fault confinement of the CAN device Its counters the Receive Error Counter and the Transmit Error Counter are incremented and decremented by commands from the Bit Stream Processor According to the values of the error counters the CAN controller is set into the states error active error passive and busoff The CAN controller is error active if both error counters are below the error passive limit of 128 It is error passive if at least one of the error counters equals or exceeds 128 It goes busoff if the Transmit Error Counter equals or exceeds the busoff limit of 256 The device remains in this state until the busoff recovery sequence is finished Additionally there is the bit EWRN in the Status Register which is set if at least one of the error counters equals or exceeds the error warning limit of 96 EWRN is reset if both error counters are less than the error warning limit User s Manual 19 5 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Bit Timing Logic This block BTL monitors the busline input CAN RXD and handles the busline related bit timing according to the
202. Current High Current Mode Mode Output Level 0 T 0 d 0 b Push Strong TL ON transistors Weak Nr ON T ON ON Pull Strong TL ON transistors Weak ON m ON m ON 1 The upper push transistors are always off for output pins that operate in open drain mode User s Manual 7 6 V2 0 2000 07 o nfineon e technologies Derivatives Parallel Ports The Port Output Control registers POCONXx provide the corresponding control bits For each feature edge driver characteristic and for each port nibble a 2 bit control field is provided i e 4 bits for each port nibble Word ports consume four control nibbles each byte ports consume two control nibbles each where each control nibble controls 4 pins of the respective port The general register layout shown below is valid for all POCON registers Please note that for byte ports only two pairs of bitfields are provided see Table 7 2 POCON Port Output Control Reg ESFR FOxxy yyyu Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PN3DC PN3EC PN2DC PN2EC PN1DC PN1EC PNODC PNOEC rw rw rw rw rw rw rw rw Bit Function PNxEC Port Nibble x Edge Characteristic Defines the output rise fall time tgp 00 Fast edge mode rise fall times depend on the driver s dimensioning 01 Reduced edge mode 10 Reserved 11 Reserved PNxDC Po
203. DY input is not evaluated during these waitstates An internal pullup ensures an inactive high level on the READY input The External Access Enable Pin EA determines if the C167CS after reset starts fetching code from the internal ROM area EA 1 or via the external bus interface EA 0 Be sure to hold this input low for ROMless devices At the end of the internal reset sequence the EA signal is latched together with the configuration PORTO RD ALE The Non Maskable Interrupt Input NMI allows to trigger a high priority trap via an external signal e g a power fail signal It also serves to validate the PWRDN instruction that switches the C167CS into Power Down mode The NMI pin is sampled with every CPU clock cycle to detect transitions User s Manual 8 2 V2 0 2000 07 o nfineon e technologies Derivatives Dedicated Pins The Oscillator Input XTAL1 and Output XTAL2 connect the internal Main Oscillator to the external crystal The oscillator provides an inverter and a feedback element The standard external oscillator circuitry see Chapter 6 comprises the crystal two low end capacitors and series resistor to limit the current through the crystal The main oscillator is intended for the generation of the basic operating clock signal of the C167CS An external clock signal may be fed to the input XTAL1 leaving XTAL2 open or terminating it for higher input frequencies The Reset Input RSTIN al
204. Derivatives Parallel Ports Internal Bus lt A A A o o o Oo o 0 g E g E p Er E c So Port Output Direction Latch Latch AltDir 1 AItEN Pin hibaiacu bP oO Driver Clock Input Latch MCB04359 P6 7 P6 4 0 Figure 7 22 Block Diagram of Port 6 Pins with an Alternate Output Function User s Manual 7 45 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports The bus arbitration signals HOLD HLDA and BREQ are selected with bit HLDEN in register PSW When the bus arbitration signals are enabled via HLDEN also these pins are switched automatically to the appropriate direction Note that the pin drivers for HLDA and BREQ are automatically controlled while the pin driver for HOLD is automatically disabled Internal Bus Port Output Direction Open Drain Latch Latch Latch AltDir 1 AItEN s Pin hibaiacu 2 LO Driver Clock AltDataln lt e Input Latch MCB04360 P6 6 Figure 7 23 Block Diagram of Pin P6 6 HLDA User s Manual 7 46 V2 0 2000 07 o Infineon technologies C167CS Derivatives Parallel Ports Internal Bus Write Read Write Read Write Read Port Output Direction Open Drain Latch Latch Latch AltDir 0 AItEN Pin Dj O Driver Clock AltDataln lt
205. Derivatives Parallel Ports 7 Parallel Ports In order to accept or generate single external control signals or parallel data the C167CS provides up to 111 parallel IO lines organized into one 16 bit IO port Port 2 eight 8 bit IO ports PORTO made of POH and POL PORT1 made of P1H and P1L Port 4 Port 6 Port 7 Port 8 one 15 bit IO port Port 3 and one 16 bit input port Port 5 These port lines may be used for general purpose Input Output controlled via software or may be used implicitly by the C167CS s integrated peripherals or the External Bus Controller All port lines are bit addressable and all input output lines are individually bit wise programmable as inputs or outputs via direction registers except Port 5 of course The IO ports are true bidirectional ports which are switched to high impedance state when configured as inputs The output drivers of six IO ports 2 3 4 6 7 8 can be configured pin by pin for push pull operation or open drain operation via control registers The logic level of a pin is clocked into the input latch once per state time regardless whether the port is configured for input or output Data Input Output Direction Control Port Driver Control Diverse Control Registers Registers Register Registers POCONG E DP7 POCON7 DP8 POCONS8 POCON20 E MCA04460 Figure 7 1 SFRs and Pins associated with the Parallel Ports User s Manual 7 1 V2 0 2000 07 o nfin
206. Each CAPCOM unit consists of two 16 bit timers TO T1 in CAPCOM T7 T8 in CAPCOMz2 each with its own reload register TXREL and a bank of sixteen dual purpose 16 bit capture compare registers CCO through CC15 in CAPCOM1 CC16 through CC31 in CAPCOM2 The input clock for the CAPCOM timers is programmable to several prescaled values of the CPU clock or it can be derived from an overflow underflow of timer T6 in block GPT2 TO and T7 may also operate in counter mode from an external input where they can be clocked by external events Each capture compare register may be programmed individually for capture or compare function and each register may be allocated to either timer of the associated unit All capture compare registers of each module have one port pin associated with it respectively which serves as an input pin for the capture function or as an output pin for the compare function The capture function causes the current timer contents to be latched into the respective capture compare register triggered by an event transition on its associated port pin The compare function may cause an output signal transition on that port pin whose associated capture compare register matches the current timer contents Specific interrupt requests are generated upon each capture compare event or upon timer overflow Figure 16 2 shows the basic structure of the two CAPCOM units User s Manual 16 2 V2 0 2000 07 j e nfineon tech
207. G the C167CS s input clock is fed to the on chip phase locked loop circuit which multiplies its frequency by a factor of F 2 1 5 5 selectable via CLKCFG see Table 6 1 and generates a CPU clock signal with 5096 duty cycle i e fcpy fosc x F The on chip PLL circuit allows operation of the C167CS on a low frequency external clock while still providing maximum performance The PLL also provides fail safe mechanisms which allow the detection of frequency deviations and the execution of emergency actions in case of an external clock failure When the PLL detects a missing input clock signal it generates an interrupt request This warning interrupt indicates that the PLL frequency is no more locked i e no more stable This occurs when the input clock is unstable and especially when the input clock fails completely e g due to a broken crystal In this case the synchronization mechanism will reduce the PLL output frequency down to the PLL s base frequency 2 5 MHz The base frequency is still generated and allows the CPU to execute emergency actions in case of a loss of the external clock On power up the PLL provides a stable clock signal within ca 1 ms after Vpp has reached the specified valid range even if there is no external clock signal in this case the PLL will run on its base frequency of 2 5 MHz The PLL starts synchronizing with the external clock signal as soon as it is available Within ca 1 ms after stable oscillations
208. I7SS EXI6SS EXI5SS EXIASS EXI3SS EXI2SS EXHSS EXIOSS rw rw rw rw rw rw rw rw Bit Function EXIxSS External Interrupt x Source Selection Field x 7 0 00 Input from associated EXzIN pin 01 Input from alternate pin 10 Input from pin EXzIN ORed with alternate pin 11 Input from pin EXzIN ANDed with alternate pin Table 5 9 summarizes the association of the bitfields of register EXISEL with the respective interface input lines Table 5 9 Connection of Interface Inputs to External Interrupt Nodes Bitfield Associated Interface Line Notes EXIOSS CAN1 RxD The used pin depends on the EXHSS CAN2 RxD assignment for the respective module EXI2SS RxDO ASCO EXI3SS SCLK SSC User s Manual 5 29 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions External Interrupts During Sleep Mode During Sleep mode all peripheral clock signals are deactivated which also disables the standard edge detection logic for the fast external interrupts However transitions on these interrupt inputs must be recognized in order to initiate the wakeup Therefore during Sleep mode a special edge detection logic for the fast external interrupts EXzIN is activated which requires no clock signal therefore also works in Sleep mode and is equipped with an analog noise filter This filter suppresses spikes generated by noise up to
209. IR CCxIR TyIR State COXIO I i 1 0 time Event 1 Event 2 COx cv2 CCx cv1 Output pin CCxIO only effected in mode 3 No changes in mode 2 X 31 0 y 0 1 7 8 MCBO02021 Figure 16 9 Timing Example for Compare Modes 2 and 3 User s Manual 16 17 V2 0 2000 07 j d nfineon e technologies Derivatives The Capture Compare Units Compare Mode 3 Compare mode 3 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 111g In compare mode 3 only one compare event will be generated per timer period When the first match within the timer period is detected the interrupt request flag CCxIR is set to 1 and also the output pin CCxIO alternate port function will be set to 1 The pin will be reset to 0 when the allocated timer overflows If a match was found for register CCx in this mode all further compare events during the current timer period are disabled for CCx until the corresponding timer overflows If after a match was detected the compare register is reloaded with a new value this value will not become effective until the next timer period In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 3 this port pin must be configured as output i e the corresponding direction control bit must be set to 1 With this configuration the initial state
210. Input MTSR Serial P3 9 1 DP3 9 1 Serial P3 9 x DP3 9 0 Data Data Output Input MRST Serial P3 8 x DP3 8 Serial P3 8 1 DP3 8 1 Data Data Input Output Note In Table 12 1 an x means that the actual value is irrelevant in the respective mode however it is recommended to set these bits to 1 so they are already in the correct state when switching between master and slave mode User s Manual 12 12 V2 0 2000 07 _ d nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 5 Baud Rate Generation The serial channel SSC has its own dedicated 16 bit baud rate generator with 16 bit reload capability permitting baud rate generation independent from the timers The baud rate generator is clocked with the CPU clock divided by 2 fcpy 2 The timer is counting downwards and can be started or stopped through the global enable bit SSCEN in register SSCCON Register SSCBR is the dual function Baud Rate Generator Reload register Reading SSCBR while the SSC is enabled returns the content of the timer Reading SSCBR while the SSC is disabled returns the programmed reload value In this mode the desired reload value can be written to SSCBR Note Never write to SSCBR while the SSC is enabled The formulas below calculate either the resulting baud rate for a given reload value or the required reload
211. Interrupt Source Select Register 0000 FOCON b FFAA D54 Frequency Output Control Register 0000 IDCHIP FO7Cy E SEQ Identifier OCxxy IDMANUF FO7E E 3Fy Identifier 1820 IDMEM F07A E 3D4 Identifier 30404 IDMEM2 FO764 E 3Byj Identifier 50014 IDPROG FO78y E 3C Identifier 4040 ISNC b FIDE E EF Interrupt Subnode Control Register 0000 MDC b FFOE 874 CPU Multiply Divide Control Register 0000 MDH FEOC 064 CPU Multiply Divide Register High Word 0000 MDL FEOE 074 CPU Multiply Divide Register Low Word 0000 User s Manual 23 8 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value ODP2 b F1C24 E El Port 2 Open Drain Control Register 0000 ODP3 b F1C6 E E34 Port 3 Open Drain Control Register 0000 ODP4 b F1CAp E E54 Port 4 Open Drain Control Register 004 ODP6 b FiCE E E7 Port 6 Open Drain Control Register 004 ODP7 b F1D2 E E9 Port 7 Open Drain Control Register 004 ODP8 b F1D6 E EBy Port 8 Open Drain Control Register 004 ONES b FF1E 8F Constant Value 1 s Register read only FFFFy POH b FF024 814 Port 0 High Register Upper half of PORTO 004 POL b FFOO 80 Port 0 Low Register Lower half of PORTO 004 P1DIDIS FEA4 1524 PORT1 Digit
212. LK signal has been detected Transmit data is written into the transmit buffer SSCTB When the contents of the buffer are moved to the shift register immediately if no transfer is currently active a transmit interrupt request SSCTIR is generated indicating that SSCTB may be reloaded again The busy flag SSCBSY is set when the transfer starts with the next following shift clock in master mode immediately in slave mode Note If no data is written to SSCTB prior to a slave transfer this transfer starts after the first latching edge of the external SCLK signal is detected No transmit interrupt is generated in this case When the contents of the shift register are moved to the receive buffer SSCRB after the programmed number of bits 2 16 have been transferred i e after the last latching edge of the current transfer a receive interrupt request SSCRIR is generated The busy flag SSCBSY is cleared at the end of the current transfer with the next following shift clock in master mode immediately in slave mode When the transmit buffer is not empty at that time in the case of continuous transfers the busy flag is not cleared and the transfer goes on after moving data from the buffer to the shift register Software should not modify SSCBSY as this flag is hardware controlled Note Only one SSC etc can be master at a given time The transfer of serial data bits can be programmed in many respects e the data width can be
213. Manual 5 13 V2 0 2000 07 j e nfineon ed technologies Derivatives Interrupt and Trap Functions Continuous transfers are selected by the value FF in bit field COUNT In this case COUNT is not modified and the respective PEC channel services any request until it is disabled again When COUNT is decremented from 01 to 00 after a transfer the request flag is not cleared which generates another request from the same source When COUNT already contains the value 004 the respective PEC channel remains idle and the associated interrupt service routine is activated instead This allows to choose if a level 15 or 14 request is to be serviced by the PEC or by the interrupt service routine Note PEC transfers are only executed if their priority level is higher than the CPU level i e only PEC channels 7 4 are processed while the CPU executes on level 14 All interrupt request sources that are enabled and programmed for PEC service should use different channels Otherwise only one transfer will be performed for all simultaneous requests When COUNT is decremented to 00 and the CPU is to be interrupted an incorrect interrupt vector will be generated The source and destination pointers specifiy the locations between which the data is to be moved A pair of pointers SRCPx and DSTPx is associated with each of the 8 PEC channels These pointers do not reside in specific SFRs but are mapped into the internal RAM of the C167
214. N TAIN Timers T3EUD T3OUT CAPIN T6OUT TOIN Port 4 Selected segment address lines in systems A23 A16 with more than 64 KBytes of ext resources CAN interface s when assigned CAN1 TxD CAN1 RxD CAN2 TxD CAN2 RxD Port5 Analog input channels to the A D converter AN15 ANO Timer control signal inputs T2EUD TAEUD T5IN T6IN Port6 Bus arbitration signals BREQ HLDA HOLD Chip select output signals CS4 CSO Port 7 Capture inputs or compare outputs of the CC311O CC28lO CAPCOM units PWM output signals POUTS POUTO Port8 Capture inputs or compare outputs of the CC23lO CC16lO CAPCOM units CAN interface s when assigned CAN1 TxD CAN1 RxD CAN2 TxD CAN2 RxD User s Manual 7 9 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports If an alternate output function of a pin is to be used the direction of this pin must be programmed for output DPx y 1 except for some signals that are used directly after reset and are configured automatically Otherwise the pin remains in the high impedance state and is not effected by the alternate output function The respective port latch should hold a 1 because its output is combined with the alternate output data X Peripherals peripherals connected to the on chip XBUS control their associated lO pins directly via separate control lines If an alternate input function of a pin is used the direction of the pin must be programmed
215. O Tx Buf Intr Ctrl Reg SFR FF9C CEy Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 i TBIR TBIE ENE GENE rwh rw rw rw SORIC ASCO Rx Intr Ctrl Reg SFR FF6E B7j Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 s Sn aie ILVL GLVL rwh rw rw rw User s Manual 11 15 V2 0 2000 07 d nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface SOEIC ASCO Error Intr Ctrl Reg SFR FF70 B84 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 so SO EIR EIE ILVL GLVL rwh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields Using the ASCO Interrupts For normal operation i e besides the error interrupt the ASCO provides three interrupt requests to control data exchange via this serial channel e SOTBIR is activated when data is moved from SOTBUF to the transmit shift register e SOTIR is activated before the last bit of an asynchronous frame is transmitted or after the last bit of a synchronous frame has been transmitted e SORIR is activated when the received frame is moved to SORBUF While the task of the receive interrupt handler is quite clear the transmitter is serviced by two interrupt handlers This provides advantages for the servicing software For single tr
216. OEN 0 Note For the generation of foyr pin FOUT must be switched to output i e DP3 15 7 While four is disabled the pin is controlled by the port latch see Figure 21 7 The port latch P3 15 must be 0 in order to maintain the foyr inactive level on the pin User s Manual 21 19 V2 0 2000 07 j Infineon Miis technologies Derivatives Power Management 1 four FORV 0 2 1 Jour FORV 2 2 1 four FORV 5 2 FOEN 1 FOEN 0 1 FOSS 1 Output of Counter t i 2 FOSS 0 Output of Toggle Latch The counter starts here The counter stops here MCT04482 Figure 21 8 Signal Waveforms Note The output signal for FOSS 1 is high for the duration of one fep cycle for all reload values FORV gt 0 For FORV 0 the output signal corresponds to fcpy User s Manual 21 20 V2 0 2000 07 d nfineon ed technologies Derivatives Power Management Output Frequency Calculation The output frequency can be calculated as four fcpu FORV 1 x 2 FOSS SO foUTmin cPU 128 FORV SFu FOSS 10 and foutmax cPU 1 FORV 00 4 FOSS 1 Table 21 5 Selectable Output Frequency Range for foyt fcPu four in KHz for FORV xx FOSS 1 0 FORV for fourt 1 MHz 004 014 024 3Ey 3Fy FOSS 0 FOSS 1 4MHz 4000 2000 11333 33 63 492 62 5 01 03 2000 1000 1666 67 131
217. OPYL are only required if the current routine could have interrupted a previous routine which contained a MUL or DIV instruction Register MDC is also saved because it is possible that a previous routine s Multiply or Divide instruction was interrupted while in progress In this case the information about how to restart the instruction is contained in this register Register MDC must be cleared to be correctly initialized for a subsequent multiplication or division The old MDC contents must be popped from the stack before the RETI instruction is executed For a division the user must first move the dividend into the MD register If a 16 16 bit division is specified only the low portion of register MD must be loaded The result is also stored into register MD The low portion MDL contains the integer result of the division while the high portion MDH contains the remainder The following instruction sequence performs a 32 by 16 bit division MOV MDH R1 Move dividend to MD register Sets MDRIU MOV MDL R2 Move low portion to MD DIV R3 Divide 32 16 signed R3 holds divisor JMPR cc V ERROR Test for divide overflow MOV R3 MDH Move remainder to R3 MOV RA MDL Move integer result to R4 Clears MDRIU Whenever a multiply or divide instruction is interrupted while in progress the address of the interrupted instruction is pushed onto the stack and the MULIP flag in the PSW of the interrupting routine is set When the interrupt routin
218. OV instructions of either constants or memory values to specific SFRs Specific control flags may also be altered via bit instructions Once in operation the peripheral operates autonomously until an end condition is reached at which time it requests a PEC transfer or requests CPU servicing through an interrupt routine Information may also be polled from peripherals through read accesses to SFRs or bit operations including branch tests on specific control bits in SFRs To ensure proper allocation of peripherals among multiple tasks a portion of the internal memory has been made bit addressable to allow user semaphores Instructions have also been provided to lock out tasks via software by setting or clearing user specific bits and conditionally branching based on these specific bits It is recommended that bit fields in control SFRs are updated using the BFLDH and BFLDL instructions or a MOV instruction to avoid undesired intermediate modes of operation which can occur when BCLR BSET or AND OR instruction sequences are used 22 7 Trap Interrupt Entry and Exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level Traps are entered regardless of the current CPU priority When either a trap or interrupt routine is entered the state of the machine is preserved on the system stack and a branch to the appropriate trap interrupt vector is made All trap and interrupt routines require t
219. PER PER PER PER PER PER PER PER PER PER PER PER PER PER PER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IW w IW IW IW IW TW TW TW TW TW TW TW Ww IW IW Bit Function XPERn XBUS Module n Select 0 Module n is not visible i e this module does not appear in the address space address window is disabled does not influence the port pins if Module n is selected and can be enabled via XPEN it is then accessible and may interface to port pins Note Register XPERCON can only be written while bit SYSCON XPEN 0 While XBUS peripherals are enabled XPEN 1 XPERCON is locked Table 9 9 summarizes the assignment of XPERCON bits to XBUS peripherals and also the number of waitstates which are used when accessing the respective peripheral Table 9 9 Association of XBUS Peripherals to XPERCON Bits in the C167CS Control Bit Associated XBUS Peripheral Default Status Waitstates XPERO CAN1 Selected 2 XPER1 CAN2 Off 2 XPER10 XRAM 2 KByte Selected 0 XPER11 XRAM 6 KByte 2 Off 0 Others Not assigned The default assignment XPERCON reset value 04014 selects a set of XBUS peripherals which is compatible with the C167CS The address decoder cuts out an 8 KByte window even if the XRAM itself only provides 6 KBytes User s Manual 9 38 V2 0 2000 07 o nfineon ed technologies Derivati
220. PRE WDTIN Y y fopy _ MUX MUX ahs gt WDT Low Byte WDT High Byte WDTR Clear A e RSTOUT gt Y Reset WDT Control WDTREL MCB04470 Figure 13 2 Watchdog Timer Block Diagram User s Manual 13 2 V2 0 2000 07 o nfineon ed technologies Derivatives The Watchdog Timer WDT 13 1 Operation of the Watchdog Timer The current count value of the Watchdog Timer is contained in the Watchdog Timer Register WDT which is a non bitaddressable read only register The operation of the Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register WDTCON This register specifies the reload value for the high byte of the timer selects the input clock prescaling factor and also provides flags that indicate the source of a reset After any reset except see note the watchdog timer is enabled and starts counting up from 0000 with the default frequency fwpr fcpu 2 The default input frequency may be changed to another frequency fwpr cpy 4 128 256 by programming the prescaler bits WDTPRE and WDTIN The watchdog timer can be disabled by executing the instruction DISWDT Disable Watchdog Timer Instruction DISWDT is a protected 32 bit instruction which will ONLY be executed during the time between a reset and execution of either the EINIT End of Initialization or the SRVWDT Service Watchdog Timer instruction Either one of these instructions disables the execution of
221. PU operation is halted and the on chip memory modules are disabled Note Peripherals that have been disabled via software also remain disabled after entering Idle mode of course Idle mode is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed bitfield SLEEPCON in register SYSCON must be 00g To prevent unintentional entry into Idle mode the IDLE instruction has been implemented as a protected 32 bit instruction Idle mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered regardless of bit IEN For a request selected for CPU interrupt service the associated interrupt service routine is entered if the priority level of the requesting source is higher than the current CPU priority and the interrupt system is globally enabled After the RETI Return from Interrupt instruction of the interrupt service routine is executed the CPU continues executing the program with the instruction following the IDLE instruction Otherwise if the interrupt request cannot be serviced because of a too low priority or a globally disabled interrupt system the CPU immediately resumes normal program execution with the instruction following the IDLE instruction For a request which was programmed for PEC service a PEC data transfer is performed if the priority level of this request is higher than the
222. Port 3 pins with alternate input output functions are MTSR MRST RxDO and SCLK Note Enabling the CLKOUT function automatically enables the P3 15 output driver Setting bit DP3 15 1 is not required The CLKOUT function is automatically enabled in emulation mode User s Manual 7 30 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Internal Bus A A o o o oO o Eg Zg tos Er So Port Output Direction Open Drain Latch Latch Latch A Pin AltDataOut e gt Driver Clock AltDataln 4 e Input Latch MCB04352 P3 13 P3 11 0 Figure 7 15 Block Diagram of a Port 3 Pin with Alternate Input or Alternate Output Function Pin P3 12 BHE WRH is one more pin with an alternate output function However its structure is slightly different see Figure 7 16 because after reset the BHE or WRH function must be used depending on the system startup configuration In these cases there is no possibility to program any port latches before Thus the appropriate alternate function is selected automatically If BHE WRH is not used in the system this pin can be used for general purpose IO by disabling the alternate function BYTDIS 1 WRCFG 0 User s Manual 7 31 V2 0 2000 07 o nfineon technologies C167CS Derivatives Parallel Ports Internal Bus
223. Right Rounding Error Evaluation C flag V flag Rounding Error Quantity 0 0 No rounding error 0 1 0 Rounding error lt 1 2 LSB 1 0 Rounding error 1 2 LSB 1 1 Rounding error gt 1 2 LSB Z Flag The Z flag is normally set to 1 if the result of an ALU operation equals zero otherwise it is cleared For the addition and subtraction with carry the Z flag is only set to 1 if the Z flag already contains a 1 and the result of the current ALU operation additionally equals zero This mechanism is provided for the support of multiple precision calculations For Boolean bit operations with only one operand the Z flag represents the logical negation of the previous state of the specified bit For Boolean bit operations with two operands the Z flag represents the logical NORing of the two specified bits For the prioritize ALU operation the Z flag indicates if the second operand was zero or not E Flag The E flag can be altered by instructions which perform ALU or data movement operations The E flag is cleared by those instructions which cannot be reasonably used for table search operations In all other cases the E flag is set depending on the value of the source operand to signify whether the end of a search table is reached or not If the value of the source operand of an instruction equals the lowest negative number which is representable by the data format of the corresponding instruction 8000
224. SCONO is initialized to 00CO0 bit ROMEN in register SYSCON willbe setto 1 bit BYTDIS in register SYSCON is set i e BHE WRH is disabled bit WRCFG in register SYSCON is set according to pin POH O WRC The other bits of register BUSCONO and the other BUSCON registers are cleared This default initialization selects the slowest possible external accesses using the configured bus type When the internal reset has completed the configuration of PORTO PORT1 Port 4 Port 6 and of the BHE signal High Byte Enable alternate function of P3 12 depends on the bus type which was selected during reset When any of the external bus modes was selected during reset PORTO will operate in the selected bus mode Port 4 will output the selected number of segment address lines all zero after reset Port 6 will drive the selected number of CS lines CSO will be 0 while the other active CS lines will be 1 When no memory accesses above 64 K are to be performed segmentation may be disabled When the on chip bootstrap loader was activated during reset pin TxDO alternate port function will be switched to output mode after the reception of the zero byte All other pins remain in the high impedance state until they are changed by software or peripheral operation User s Manual 20 7 V2 0 2000 07 j Infineon iiis technologies Derivatives System Reset Reset Output Pin The RSTOUT pin is dedicated to genera
225. Share mode XPER Share Mode The C167CS can share its on chip XBUS peripherals with other external bus masters i e it can allow them to access its X Peripherals while it is in hold mode This external access is enabled via bit XPERSHARE in register SYSCON and is only possible while the host controller is in hold mode During XPER Share mode the C167CS s bus interface inverts its direction so the external master can drive address control and data signals to the respective peripheral This can be used e g to install a mailbox memory in a multi processor system Note When XPER Share mode is disabled no accesses to on chip XBUS peripherals can be executed from outside User s Manual 9 40 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units 10 The General Purpose Timer Units The General Purpose Timer Units GPT1 and GPT2 represent very flexible multifunctional timer structures which may be used for timing event counting pulse width measurement pulse generation frequency multiplication and other purposes They incorporate five 16 bit timers that are grouped into the two timer blocks GPT1 and GPT2 Block GPT1 contains 3 timers counters with a maximum resolution of 16 TCL while block GPT2 contains 2 timers counters with a maximum resolution of 8 TCL and a 16 bit Capture Reload register CAPREL Each timer in each block may operate independently in a number of different modes such as gated
226. Table 21 1 State of C167CS Output Pins during Idle and Power Down Mode C167CS External Bus Enabled No External Bus Output Pin s Idie Mode Sleep and Idle Mode Sleep and Power Down Power Down CLKOUT Active toggling High Active toggling High FOUT Active toggling Hold high low Active toggling Hold high low ALE Low Low RD WR High High POL Floating Port Latch Data POH A15 A8 Float Port Latch Data PORT 1 Last Address Port Latch Data Port Latch Data Port 4 Port Latch Data Last segment Port Latch Data BHE Last value Port Latch Data CSx Last value Port Latch Data RSTOUT High if EINIT was executed before entering Idle or Power Down mode Low otherwise Other Port Port Latch Data Alternate Function Output Pins 1 For multiplexed buses with 8 bit data bus 2 For demultiplexed buses 9 The CS signal that corresponds to the last address remains active low all other enabled CS signals remain inactive high By accessing an on chip X Periperal prior to entering a power save mode all external CS signals can be deactivated User s Manual 21 9 V2 0 2000 07 d Infineon Miis technologies Derivatives Power Management 21 4 Slow Down Operation A separate clock path can be selected for Slow Down operation bypassing the basic clock path used for standard operation The programmable Slow Down Divider SDD divides the oscillator frequency by a factor of 1 32 which
227. The corresponding interrupt code in bitfield INTID is O1 y The busoff recovery sequence cannot be shortened by setting or resetting INIT User s Manual 19 34 V2 0 2000 07 d nfineon ed technologies Derivatives The On Chip CAN Interface 19 5 Configuration Examples for Message Objects The two examples below represent standard applications for using CAN messages Both examples assume that identifier and direction are already set up correctly The respective contents of the Message Control Register MCR are shown Configuration Example of a Transmission Object This object shall be configured for transmission It shall be transmitted automatically in response to remote frames but no receive interrupts shall be generated for this object MCR Data bytes are not written completely gt CPUUPD 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01 01 10 01 10 01 01 01 RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND MCR Remote frame was received in the meantime RMTPND 1 TXRQ 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 10 10 10 01 10 01 01 01 RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND After updating the message the CPU should clear CPUUPD and set NEWDAT The previously received remote request will then be answered If the CPU wants to transmit the message actively it sho
228. UR Saeed sat uo ad Se 4 3 4 2 Particular Pipeline Effects 22s stews akek dees Reads y hd gr sudo 4 6 4 3 Bit Handling and Bit Protectlon exce eases EX ee ee Wakao ROS Es 4 10 4 4 Instruction State Times 0 ccc eee eee Ik 4 11 4 5 CPU Special Function Registers 0 0c cece 4 12 5 Interrupt and Trap Functions 00 eee 5 1 5 1 Interrupt System Structure 0 0 ees 5 2 9 1 1 Interrupt Control Registers 2 e eee eee 5 6 5 2 Operation of the PEC Channels 0 00 e eens 5 12 5 3 Prioritization of Interrupt and PEC Service Requests 5 16 5 4 Saving the Status During Interrupt Service 2 4 5 18 5 5 Interrupt Response Times 2 00 cece eee ees 5 20 5 6 PEG Response Times sciceadsearcad onuesiaeeeds sn G di Xaedpss 5 23 5 7 Interrupt Node Sharing aseaciendteddeedseaeeetesaeeddedages 5 25 5 8 External Interrupts us acia aliae ewe enaena 5 26 5 9 Tap FUNCIONS smana tule nda eeaeee aa a REE se 5 31 6 Clock Generation aana anana 6 1 6 1 Oscillator ceee eee aie eedan EnA de moe ESE Wee ee De re eS 6 2 6 2 Frequency Control 23 ed es E a RO tenet radeon eee race Riad 6 4 User s Manual l 1 V2 0 2000 07 j e nfineon technologies C167CS Derivatives Table of Contents 6 3 Oscillator Watchdog s uoa Sonde oec ene ones 6 4 Clock Drivers esee 7 Parallel Ports eee 7 1 Inpu
229. User s Manual V2 0 July 2000 C167CS Derivatives 16 Bit Single Chip Microcontroller Microcontrollers Never stop thinking Edition 2000 07 Published by Infineon Technologies AG St Martin Strasse 53 D 81541 M nchen Germany Infineon Technologies AG 2000 All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as warranted characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Infineon Technologies is an approved CECC manufacturer Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide see address list Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device o
230. V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value CSP FE08j 044 CPU Code Segment Pointer Register 0000 8 bits not directly writeable MDH FEOC 064 CPU Multiply Divide Register High Word 0000 MDL FEOE 074 CPU Multiply Divide Register Low Word 0000 CP FE10 084 CPU Context Pointer Register FCOO SP FE12 09 CPU System Stack Pointer Register FCOO STKOV FE144 OA CPU Stack Overflow Pointer Register FAOO STKUN FE16y OB CPU Stack Underflow Pointer Register FCO00 ADDRSEL1 FE18 OC Address Select Register 1 00004 ADDRSEL2 FE1A OD Adadress Select Register 2 00004 ADDRSEL3 FE1C OE Adadress Select Register 3 0000 ADDRSEL4 FE1E OF Adadress Select Register 4 00004 PWO FE30y 184 PWM Module Pulse Width Register 0 0000 PW1 FE32y 19 PWM Module Pulse Width Register 1 0000 PW2 FE34 1Ay PWM Module Pulse Width Register 2 00004 PW3 FE364 1By PWM Module Pulse Width Register 3 0000 T2 FE40 204 GPT1 Timer 2 Register 00004 T3 FE424 214 GPT1 Timer 3 Register 00004 TA FE44 224 GPT1 Timer 4 Register 0000 T5 FE464 234 GPT2 Timer 5 Register 0000 T6 FE48y 244 GPT2 Timer 6 Register 0000 CAPREL FE4A 254 GPT2 Capture Reload Register 00
231. V2 0 2000 07 o nfineon en technologies Derivatives The Pulse Width Modulation Module 17 4 PWM Output Signals The output signals of the four PWM channels POUTS POUTO are alternate output functions on Port 7 P7 3 P7 0 The output signal of each PWM channel is individually enabled by control bit PENx in register PWMCON1 The PWM signals are XORed with the respective port latch outputs before being driven to the port pins This allows driving the PWM signal directly to the port pin P7 x 0 or drive the inverted PWM signal P7 x 1 PWM 3 e o Latch P7 3 XOR H PinP7 3 PWM 2 eo a Latch P7 2 XOR H Pin P72 PWM 1 PWM 0 MCA02277 Figure 17 7 PWM Output Signal Generation Note Using the open drain mode on Port 7 allows the combination of two or more PWM outputs through a Wired AND configuration using an external pullup device This provides sort of a burst mode for any PWM channel User s Manual 17 15 V2 0 2000 07 d nfineon en technologies Derivatives The Pulse Width Modulation Module Software Control of the PWM Outputs In an application the PWM output signals are generally controlled by the PWM module However it may be necessary to influence the level of the PWM output pins via software either to initialize the system or to react on some extraordinary condition e g a system fault or an emergency Clearing the time
232. Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P8L P7L P6L P4L P3H P3L P2H P2L IN IN IN IN IN IN IN IN rw rw rw rw rw rw rw rw Bit Function PxLIN Port x Low Byte Input Level Selection 0 Pins Px 7 Px 0 switch on standard TTL input levels 1 Pins Px 7 Px 0 switch on special threshold input levels PxHIN Port x High Byte Input Level Selection 0 Pins Px 15 Px 8 switch on standard TTL input levels 1 Pins Px 15 Px 8 switch on special threshold input levels User s Manual 7 2 V2 0 2000 07 j d nfineon ed technologies Derivatives Parallel Ports All options for individual direction and output mode control are available for each pin independent from the selected input threshold The input hysteresis provides stable inputs from noisy or slowly changing external signals Hysteresis Input Level Bit State MCT04341 Figure 7 2 Hysteresis for Special Input Thresholds User s Manual 7 3 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 2 Output Driver Control The output driver of a port pin is activated by switching the respective pin to output i e DPx y 1 The value that is driven to the pin is determined by the port output latch or by the associated alternate function e g address peripheral IO etc The user softwa
233. X y is an input high impedance DP1X y 1 Port line P1X y is an output Alternate Functions of PORT1 When a demultiplexed external bus is enabled PORT1 is used as address bus Note that demultiplexed bus modes use PORT1 as a 16 bit port Otherwise all 16 port lines can be used for general purpose IO The lower eight pins of PORT1 P1L 7 P1L 0 are also connected to the input multiplexer of the Analog Digital Converter For pins that shall be used as analog inputs itis recommended to disable the digital input stage via register P1DIDIS see description below This avoids undesired cross currents and switching noise while the analog input signal level is between Vi and Vj These port lines accept analog signal for the extension channels AN23 AN16 The upper four pins of PORT1 P1H 7 P1H 4 also serve as capture inputs or compare outputs CC271O CC241O for the CAPCOM2 unit The usage of the port lines by the CAPCOM unit its accessibility via software and the precautions are the same as described for the Port 2 lines As all other capture inputs the capture input function of pins P1H 7 P1H 4 can also be used as external interrupt inputs sample rate 16 TCL As a side effect the capture input capability of these lines can also be used in the address bus mode Hereby changes of the upper address lines could be detected and User s Manual 7 17 V2 0 2000 07 o nfineon e technologies Derivatives
234. XRQ 0 CPUUPD 1 Identifier application cpecific NEWDAT 0 Direction transmit DLC application cpecific MSGVAL 1 XTD application cpecific CPUUPD 1 NEWDAT 1 Update Write calculate message contents Update End CPUUPD 0 gt Want to send TXRQ 1 l 0 Reset 1 Set MCA04397 Figure 19 8 CPU Handling of Transmit Objects DIR 1 User s Manual 19 27 V2 0 2000 07 technologies C167CS Derivatives The On Chip CAN Interface Power Up all bits undefined TXIE application cpecific RXIE application cpecific INTPNDd 0 RMTPND 0 TXRQ 0 Initialization FEL PP Identifier application cpecific NEWDAT 0 Direction receive DLC value of DLC in transmitter MSGVAL 1 XTD application cpecific Process Start NEWDAT 0 Process message contents gt Process gt lt Process End Restart process Request Update 0 Reset 1 Set MCA04398 Figure 19 9 CPU Handling of Receive Objects DIR 0 User s Manual 19 28 V2 0 2000 07 C167CS Derivatives The On Chip CAN Interface technologies Power Up all bits undefined RXIE application cpecific INTPND 0 RMTPND 0 MSGLST 0 Identifier application cpecific NEWDAT 0 Direction receive DLC value of DLC in transmit
235. a set of interrupt sources with the same importance i e the same priority from the system s viewpoint Interrupts of the same class must not interrupt each other The C167CS supports this function with two features Classes with up to 4 members can be established by using the same interrupt priority ILVL and assigning a dedicated group level GLVL to each member This functionality is built in and handled automatically by the interrupt controller Classes with more than 4 members can be established by using a number of adjacent interrupt priorities ILVL and the respective group levels 4 per ILVL Each interrupt service routine within this class sets the CPU level to the highest interrupt priority within the class All requests from the same or any lower level are blocked now i e no request of this class will be accepted User s Manual 5 16 V2 0 2000 07 o nfineon technologies C167CS Derivatives Interrupt and Trap Functions The example below establishes 3 interrupt classes which cover 2 or 3 interrupt priorities depending on the number of members in a class A level 6 interrupt disables all other sources in class 2 by changing the current CPU level to 8 which is the highest priority ILVL in class 2 Class 1 requests or PEC requests are still serviced in this case The 24 interrupt sources excluding PEC requests are so assigned to 3 classes of priority rather than to 7 different levels as the hardware support woul
236. ach time a CPU write access to the port output latch occurs the input multiplexer of the port output latch is switched to the line connected to the internal bus The port output latch will receive the value from the internal bus and the hardware triggered change will be lost As all other capture inputs the capture input function of pins P2 15 P2 0 can also be used as external interrupt inputs sample rate 16 TCL or as Fast External Interrupt inputs sample rate 2 TCL P2 15 in addition serves as input for CAPCOMe timer T7 T7IN Table 7 4 summarizes the alternate functions of Port 2 User s Manual 7 25 V2 0 2000 07 o nfineon technologies C167CS Derivatives Table 7 4 Alternate Functions of Port 2 Parallel Ports Port 2 Pin Alternate Alternate Function b Alternate Function c Function a P2 0 CCOIO P2 1 CC1IO P2 2 CC2lO P2 3 CC3IO P2 4 CCAIO P2 5 CC5IO P2 6 CC6lO P2 7 CC7IO P2 8 CC8lIO EXOIN Fast External Interrupt O Inp P2 9 CCS9IO EX1IN Fast External Interrupt 1 Inp P2 10 CC10I0 EX2IN Fast External Interrupt 2 Inp P2 11 CC111O EXSIN Fast External Interrupt 3 Inp P2 12 CC121O EXAIN Fast External Interrupt 4 Inp P2 13 CC13lIO EXSIN Fast External Interrupt 5 Inp P2 14 CC14IO EX6IN Fast External Interrupt 6 Inp P2 15 CC151IO EX7IN Fast External Interrupt 7 Inp T7IN Timer T7 Ext Count Input Alternate Function a b c P2 15 CC1510 EX
237. al 20 2 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Software Reset The reset sequence can be triggered at any time via the protected instruction SRST Software Reset This instruction can be executed deliberately within a program e g to leave bootstrap loader mode or upon a hardware trap that reveals a system failure Note A software reset only latches the configuration of the bus interface SALSEL CSSEL WRC BUSTYP from PORTO in case of an external reset If bidirectional reset is enabled a software reset is executed like a long hardware reset Watchdog Timer Reset When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence Other than hardware and software reset the watchdog reset completes a running external bus cycle if this bus cycle either does not use READY at all or if READY is sampled active low after the programmed waitstates When READY is sampled inactive high after the programmed waitstates the running external bus cycle is aborted Then the internal reset sequence is started Note A watchdog reset only latches the configuration of the bus interface SALSEL CSSEL WRC BUSTYP from PORTO in case of an external reset If bidirectional reset is enabled a watchdog timer reset is executed like a long hardware reset The watchdog reset cannot occur while the C167CS is in bootstrap loade
238. al Input Disable Register 00004 P1H b FFO64 834 Port1 High Register Upper half of PORT1 00H P1L b FF0444 82 Port 1 Low Register Lower half of PORT1 00 P2 b FFCO E0 Port 2 Register 0000 P3 b FFC4 E2 Port 3 Register 00004 P4 b FFC8 E44 Port 4 Register 7 bits 004 P5 b FFA2 Dip Port 5 Register read only XXXXy P5DIDIS b FFA4 D24 Port 5 Digital Input Disable Register 0000 P6 b FFCC E6 Port 6 Register 8 bits 004 P7 b FFDO E84 Port 7 Register 8 bits 004 P8 b FFD4 EAy Port 8 Register 8 bits 004 PECCO FECO 604 PEC Channel 0 Control Register 0000 PECC1 FEC2 614 PEC Channel 1 Control Register 00004 PECC2 FEC4 624 PEC Channel 2 Control Register 0000 PECC3 FEC6 163 PEC Channel 3 Control Register 0000 PECC4 FEC8 644 PEC Channel 4 Control Register 00004 PECC5 FECA 654 PEC Channel 5 Control Register 00004 PECC6 FECC 664 PEC Channel 6 Control Register 0000 PECC7 FECE 674 PEC Channel 7 Control Register 0000 PICON F1C4 E E24 Port Input Threshold Control Register 0000 POCONOH F082 E 414 Port POH Output Control Register 0000 User s Manual 23 9 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Ad
239. al function registers can be addressed via indirect and long 16 bit addressing modes Using an 8 bit offset together with an implicit base address allows to address word SFRs and their respective low bytes However this does not work for the respective high bytes Note Writing to any byte of an SFR causes the non addressed complementary byte to be cleared The upper half of each register block is bit addressable so the respective control status bits can directly be modified or checked using bit addressing When accessing registers in the ESFR area using 8 bit addresses or direct bit addressing an Extend Register EXTR instruction is required before to switch the short addressing mechanism from the standard SFR area to the Extended SFR area This is not required for 16 bit and indirect addresses The GPRs H15 RO are duplicated i e they are accessible within both register blocks via short 2 4 or 8 bit addresses without switching ESFR SWITCH EXAMPLE EXTR 4 Switch to ESFR area for next 4 instr MOV ODP2 datal6 ODP2 uses 8 bit reg addressing BFLDL DP6 mask data8 Bit addressing for bit fields BSET DP1H 7 Bit addressing for single bits MOV T8REL R1 I8REL uses 16 bit mem address Rl is duplicated into the ESFR space EXTR is not required for this access gt SSS SSS SS SS The scope of the EXTR 4 instruction P ends here MOV T8REL R1 T8REL uses 16 bit mem address Rl is accessed
240. al increment of either the PEC source or the destination pointer Just one cycle is stolen from the current CPU activity to perform a PEC service 2 Multiple Priority Interrupt Controller This controller allows all interrupts to be placed at any specified priority Interrupts may also be grouped which provides the user with the ability to prevent similar priority tasks from interrupting each other For each of the possible interrupt sources there is a separate control register which contains an interrupt request flag an interrupt enable flag and an interrupt priority bitfield Once having been accepted by the CPU an interrupt service can only be interrupted by a higher prioritized service request For standard interrupt processing each of the possible interrupt sources has a dedicated vector location 3 Multiple Register Banks This feature allows the user to specify up to sixteen general purpose registers located anywhere in the internal RAM A single one machine cycle instruction allows to switch register banks from one task to another 4 Interruptable Multiple Cycle Instructions Reduced interrupt latency is provided by allowing multiple cycle instructions multiply divide to be interruptable With an interrupt response time within a range from just 5 to 10 CPU clock cycles in case of internal program execution the C167CS is capable of reacting very fast on non deterministic events Its fast external interrupt inputs are sampl
241. al program memory can be remapped or disabled at all in order to utilize external memory partly or completely Programmable program memory can be programmed e g with data received over a serial link Note Initial Flash or OTP programming will rather be done in bootstrap loader mode System Stack The default setup for the system stack size stackpointer upper and lower limit registers can be adjusted to application specific values After reset registers SP and STKUN contain the same reset value O0 FCOO while register STKOV contains 00 FA00 With the default reset initialization 256 words of system stack are available where the system stack selected by the SP grows downwards from 00 FBFE Note The interrupt system which is disabled upon completion of the internal reset should remain disabled until the SP is initialized Traps incl NMI may occur even though the interrupt system is still disabled Register Bank The location of a register bank is defined by the context pointer CP and can be adjusted to an application specific bank before the general purpose registers GPRs are used After reset register CP contains the value 00 FCOO i e the register bank selected by the CP grows upwards from 00 FCO00 User s Manual 20 9 V2 0 2000 07 d nfineon ed technologies Derivatives System Reset On Chip RAM Based on the application the user may wish to initialize portions of the internal writable memo
242. ally by bits T5SC and T6SR the two functions can be enabled simultaneously by setting both bits This feature can be used to generate an output frequency that is a multiple of the input frequency Up Down Input m Interrupt Clock Auxiliary Timer T5 Request Edge Select T5CLR f AY T5SC Interrupt Request CAPREL Register TeoUT T6SR Input Interrupt Clock Core Timer T6 Request Up Down MCB02046B Figure 10 24 GPT2 Register CAPREL in Capture And Reload Mode This combined mode can be used to detect consecutive external events which may occur aperiodically but where a finer resolution that means more ticks within the time between two external events is required User s Manual 10 36 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units For this purpose the time between the external events is measured using timer T5 and the CAPREL register Timer T5 runs in timer mode counting up with a frequency of e g Jcpu 32 The external events are applied to pin CAPIN When an external event occurs the timer T5 contents are latched into register CAPREL and timer T5 is cleared T5CLR 1 Thus register CAPREL always contains the correct time between two events measured in timer T5 increments Timer T6 which runs in timer mode counting down with a frequency of e g fcpu 4 uses the value in register CAPREL to perform a reload on u
243. alog Digital Converter 2 15 18 1 Arbitration Address 9 27 External Bus 9 31 Master Slave mode 9 35 Signals 9 32 ASCO 11 1 Asynchronous mode 11 5 Baudrate 11 11 Error Detection 11 10 Interrupts 11 15 Synchronous mode 11 8 Asynchronous Serial Interface gt ASCO 11 1 Auto Scan conversion 18 7 B Baudrate User s Manual ASCO 11 11 Bootstrap Loader 15 6 SSC 12 13 BHE 7 31 9 9 Bidirectional reset 20 4 Bit addressable memory 3 4 Handling 4 10 Manipulation Instructions 24 2 protected 2 19 4 10 reserved 2 12 Bootstrap Loader 15 1 20 16 Boundaries 3 12 BTR 19 13 Burst mode PWM 17 7 Bus Arbitration 9 31 CAN 2 14 19 1 19 38 Demultiplexed 9 5 Idle State 9 30 Mode Configuration 9 3 20 17 Multiplexed 9 4 BUSCONXx 9 22 9 27 C CAN Interface 2 14 19 1 activation 19 32 port control 19 40 second 19 37 CAPCOM 2 17 interrupt 16 22 timer 16 4 unit 16 1 Capture Mode CAPCOM 16 13 GPT1 10 20 V2 0 2000 07 e nfineon technologies C167CS Derivatives GPT2 CAPREL 10 34 Capture Compare unit 16 1 CCMO CCM1 CCM2 CCM3 16 10 CCM4 CCM5 CCM6 CCM7 16 11 CCxIC 16 22 Center aligned PWM 17 5 Chip Select Configuration 9 10 20 18 Latched Early 9 11 Clock distribution 6 1 21 14 generator modes 6 7 20 19 output signal 21 17 Code memory handling 22 16 Compare modes 16 14 double register 16 19 Concatenation of Timers 10 16 10 33 Configuration Address 9 9 20 18 Bus Mode 9 3 20 17 C
244. also reset bit WDTR After being serviced the watchdog timer continues counting up from the value lt WDTREL gt x 29 Instruction SRVWDT has been encoded in such a way that the chance of unintentionally servicing the watchdog timer e g by fetching and executing a bit pattern from a wrong location is minimized When instruction SRVWDT does not match the format for User s Manual 13 3 V2 0 2000 07 o nfineon e technologies Derivatives The Watchdog Timer WDT protected instructions the Protection Fault Trap will be entered rather than the instruction be executed WDTCON WDT Control Register SFR FFAE D7 Reset Value 00XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WDT LHW SHW SW WDT WDT WDTREL PRE R HR RR IN rw rh rh rh m rw Bit Function WDTIN Watchdog Timer Input Frequency Select Controls the input clock prescaler See Table 13 1 WDTR Watchdog Timer Reset Indication Flag Cleared by a hardware reset or by the SRVWDT instruction SWR Software Reset Indication Flag SHWR Short Hardware Reset Indication Flag LHWR Long Hardware Reset Indication Flag WDTPRE Watchdog Timer Input Prescaler Control Controls the input clock prescaler See Table 13 1 WDTREL Watchdog Timer Reload Value for the high byte of WDT Note The reset value depends on the reset source see description below The execution of EINIT clears the reset ind
245. and T4 is selected by setting bit field TxM in the respective register TXCON to 100g In reload mode the core timer T3 is reloaded with the contents of an auxiliary timer register triggered by one of two different signals The trigger signal is selected the same way as the clock source for counter mode see Table 10 8 i e a transition of the auxiliary timer s input or the output toggle latch T3OTL may trigger the reload Note When programmed for reload mode the respective auxiliary timer T2 or T4 stops independent of its run flag T2R or TAR Source Edge Select Reload Register Tx _ Interrupt TxIN Request Txl Input Interrupt Clock CoreTimerT3 Timer T3 Request Up Down rsour X224 Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL MCB02035 Figure 10 12 GPT1 Auxiliary Timer in Reload Mode Upon a trigger signal T3 is loaded with the contents of the respective timer register T2 or T4 and the interrupt request flag T2IR or T4IR is set Note When a T3OTL transition is selected for the trigger signal also the interrupt request flag T3IR will be set upon a trigger indicating T3 s overflow or underflow Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 User s Manual 10 17 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units The reload mode triggered by
246. and expected baudrate SSCBSY SSC Busy Flag Set while a transfer is in progress Do not write to SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 1 Transmission and reception enabled Access to status flags and M S control Note The target of an access to SSCCON control bits or flags is determined by the state of SSCEN prior to the access i e writing C057 to SSCCON in programming mode SSCEN 0 will initialize the SSC SSCEN was 0 and then turn it on SSCEN 1 When writing to SSCCON make sure that reserved locations receive zeros User s Manual 12 4 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface The shift register of the SSC is connected to both the transmit pin and the receive pin via the pin control logic see block diagram Transmission and reception of serial data is synchronized and takes place at the same time i e the number of transmitted bits is also received The major steps of the state machine of the SSC are controlled by the shift clock signal see Figure 12 2 In master mode SSCMS 1 two clocks per bit time are generated each upon an underflow of the baudrate counter In slave mode SSCMS 0 one clock per bit time is generated when the latching edge of the external SC
247. and lower part of PORTO respectively Both halfs of PORTO can be written e g via a PEC transfer without effecting the other half If this port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DPOH and DPOL POL PORTO Low Register SFR FF00 80 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POL POL POL POL POL POL POL POL 7 6 5 4 3 2 1 0 POH PORTO High Register SFR FF02 81 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POH POH POH POH POH POH POH POH 7 6 5 4 3 2 1 0 Bit Function POX y Port data register POH or POL bit y User s Manual 7 12 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports DPOL POL Direction Ctrl Register ESFR F100 80 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOL DPOL DPOL DPOL DPOL DPOL DPOL DPOL T 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DPOH POH Direction Ctrl Register ESFR F102 81 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DPOH DPOH DPOH DPOH DPOH DPOH DPOH DPOH 7 6 5 4 3 2 1 0 Bit Function DPOX y Port direction register DPOH or DPOL bit y DPOX
248. ansfers is sufficient to use the transmitter interrupt SOTIR which indicates that the previously loaded data has been transmitted except for the last bit of an asynchronous frame For multiple back to back transfers it is necessary to load the following piece of data at last until the time the last bit of the previous frame has been transmitted In asynchronous mode this leaves just one bit time for the handler to respond to the transmitter interrupt request in synchronous mode it is impossible at all Using the transmit buffer interrupt SOTBIR to reload transmit data gives the time to transmit a complete frame for the service routine as SOTBUF may be reloaded while the previous data is still being transmitted User s Manual 11 16 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface Idle t Asynchronous Mode SORIR SORIR SORIR SOTIR SOTIR SOTIR SOTBIR SOTBIR SOTBIR Idle Idle Synchronous Mode SORIR SORIR SORIR MCT04379 Figure 11 6 ASCO Interrupt Generation As shown in Figure 11 6 SOTBIR is an early trigger for the reload routine while SOTIR indicates the completed transmission Software using handshake therefore should rely on SOTIR at the end of a data block to make sure that all data has really been transmitted User s Manual 11 17 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface
249. ant for longer time periods For short periods 1 4 CPU clock cycles it remains below 4 PLL Circuit DS Fou F fin gt fou Reset Reset PWRDN Sleep Lock OWD XP3INT CLKCFG RPOH 7 5 MCB04339 Figure 6 6 PLL Block Diagram User s Manual 6 7 V2 0 2000 07 o nfineon ed technologies Derivatives Clock Generation 6 3 Oscillator Watchdog The C167CS provides an Oscillator Watchdog OWD which monitors the clock signal fed to input XTAL1 of the on chip oscillator either with a crystal or via external clock drive in prescaler or direct drive mode not if the PLL provides the basic clock For this operation the PLL provides a clock signal base frequency which is used to supervise transitions on the oscillator clock This PLL clock is independent from the XTAL1 clock When the expected oscillator clock transitions are missing the OWD activates the PLL Unlock OWD interrupt node and supplies the CPU with the PLL clock signal instead of the selected oscillator clock see Figure 6 4 Under these circumstances the PLL will oscillate with its base frequency In direct drive mode the PLL base frequency is used directly fcpy 2 5 MHz In prescaler mode the PLL base frequency is divided by 2 fcpy 1 2 5 MHz If the oscillator clock fails while the PLL provides the basic clock the system will be supplied with the PLL base frequency anyway With this PLL clock signal the CPU can either execut
250. anual 23 7 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value CP FE10 084 CPU Context Pointer Register FCOO CRIC b FF6Ay B5 GPT2 CAPREL Interrupt Control Register 00004 CSP FE084 044 CPU Code Segment Pointer Register 00004 8 bits not directly writeable DPOH b F102 E 81 POH Direction Control Register 00H DPOL b F100 E 80 POL Direction Control Register 004 DP1H b F1064 E83 P1H Direction Control Register 004 DP1L b F1044 E82 P1L Direction Control Register 004 DP2 b FFC2 E1y_ Port2 Direction Control Register 00004 DP3 b FFC6 E34 Port 3 Direction Control Register 0000 DP4 b FFCA E5 Port 4 Direction Control Register 00 DP6 b FFCE E74 Port6 Direction Control Register 004 DP7 b FFD24 E94 Port 7 Direction Control Register 00H DP8 b FFD6 EBy Port 8 Direction Control Register 00H DPPO FE00 00 CPU Data Page Pointer 0 Register 10 bits 0000 DPP1 FE024 014 CPU Data Page Pointer 1 Register 10 bits 0001 DPP2 FE04 02 4 CPU Data Page Pointer 2 Register 10 bits 00024 DPP3 FE064 034 CPU Data Page Pointer 3 Register 10 bits 0003 EXICON b F1CO E EO External Interrupt Control Register 0000 EXISEL b F1DA4 E ED External
251. arded and not serviced Enabling and disabling interrupt requests may be done via three mechanisms Control bits allow to switch each individual source ON or OFF so it may generate a request or not The control bits xxIE are located in the respective interrupt control registers All interrupt requests may be enabled or disabled generally via bit IEN in register PSW This control bit is the main switch that selects if requests from any source are accepted or not For a specific request to be arbitrated the respective source s enable bit and the global enable bit must both be set The priority level automatically selects a certain group of interrupt requests that will be acknowledged disclosing all other requests The priority level of the source that won the arbitration is compared against the CPU s current level and the source is only serviced if its level is higher than the current CPU level Changing the CPU level to a specific value via software blocks all requests on the same or a lower level An interrupt source that is assigned to level 0 will be disabled and never be serviced The ATOMIC and EXTend instructions automatically disable all interrupt requests for the duration of the following 1 4 instructions This is useful e g for semaphore handling and does not require to re enable the interrupt system after the unseparable instruction sequence see Chapter 22 Interrupt Class Management An interrupt class covers
252. are assumed if any of the signals WRH or WRL gets active These modes save external glue logic when accessing external devices like latches or drivers that only provide a single enable input Address Chip Select signals remain active during the complete bus cycle For address chip select signals two generation modes can be selected via bit CSCFG in register SYSCON A latched address chip select signal CSCFG 0 becomes active with the falling edge of ALE and becomes inactive at the beginning of an external bus cycle that accesses a different address window No spikes will be generated on the chip select lines and no changes occur as long as locations within the same address window or within internal memory excluding X Peripherals and XRAM are accessed An early address chip select signal CSCFG 1 becomes active together with the address and BHE if enabled and remains active until the end of the current bus cycle Early address chip select signals are not latched internally and may toggle intermediately while the address is changing Note CSO provides a latched address chip select directly after reset except for single chip mode when the first instruction is fetched Internal pullup devices hold all CS lines high during reset After the end of a reset sequence the pullup devices are switched off and the pin drivers control the pin levels on the selected CS lines Not selected CS lines will enter the high impedan
253. are or a capture event of Capture Compare register CC31 of the CAPCOM2 unit which also sets bit ADCRQ The second method triggers a channel injection at a specific time on the occurrence of a predefined count value of the CAPCOM timers or on a capture event of register CC31 This can be either the positive the negative or both the positive and the negative edge of an external signal In addition this option allows recording the time of occurrence of this signal Note The channel injection request bit ADCRQ will be set on any interrupt request of CAPCOM2 channel CC31 regardless whether the channel injection mode is enabled or not It is recommended to always clear bit ADCRQ before enabling the channel injection mode After the completion of the current conversion if any is in progress the converter will start inject the conversion of the specified channel When the conversion of this channel is complete the result will be placed into the alternate result register ADDAT2 and a Channel Injection Complete Interrupt request will be generated which uses the interrupt request flag ADEIR for this reason the Wait for ADDAT Read Mode is required Note If the temporary data register used in Wait for ADDAT Read Mode is full the respective next conversion standard or injected will be suspended The temporary register can hold data for ADDAT from a standard conversion or for ADDAT2 from an injected conversion User s Manual 18 10 V2
254. areas including internal ROM Flash OTP where integrated internal RAM the internal Special Function Register Areas SFRs and ESFRs the address areas for integrated XBUS peripherals and external memory are mapped into one common address space The C167CS provides a total addressable memory space of 16 MBytes This address space is arranged as 256 segments of 64 KBytes each and each segment is again subdivided into four data pages of 16 KBytes each see Figure 3 1 m m FF FFFF 254 129 Ot FFFF ua Begin of 126 65 Prog Memory uum 40 0000 D gt 5 E 01 8000 Kel Q p LP FFFF 9 Q S H y Alternate glo r ROM a E Area zo o E J 01 0000 g 080000 o x Lu e c o x o 02 FFFF Internal EARUM Ot FFFF Area 000000 000000 Total Address Space Segments 1 and 0 16 MByte Segments 255 0 64 64 Kbyte MCA04325 Figure 3 1 Address Space Overview User s Manual 3 1 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization Most internal memory areas are mapped into segment 0 the system segment The upper 4 KByte of segment 0 00 F000 00 FFFFjj hold the Internal RAM and Special Function Register Areas SFR and ESFR The lower 32 KByte of segment 0 00 0000 007FFFy may be occupied by a part of the on chip ROM Flash OTP memory and is called the Internal ROM area This ROM area can b
255. as possible This makes it easy to use User s Manual 19 3 V2 0 2000 07 C167CS Derivatives The On Chip CAN Interface technologies BTL Configuration Timing Generator Tx Rx Shift Register Clocks Messages Handlers Intelligent Memory to all Interrupt Control Register Status Control Status Register Vv io ABUS MCB04391 Figure 19 2 CAN Controller Block Diagram User s Manual 19 4 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Tx Rx Shift Register The Transmit Receive Shift Register holds the destuffed bit stream from the bus line to allow the parallel access to the whole data or remote frame for the acceptance match test and the parallel transfer of the frame to and from the Intelligent Memory Bit Stream Processor The Bit Stream Processor BSP is a sequencer controlling the sequential data stream between the Tx Rx Shift Register the CRC Register and the bus line The BSP also controls the EML and the parallel data stream between the Tx Rx Shift Register and the Intelligent Memory such that the processes of reception arbitration transmission and error signalling are performed according to the CAN protocol Note that the automatic retransmission of messages which have been corrupted by noise or other external error conditions on the bus line is handled by the BSP Cyclic Redundancy
256. avior of the SSC to a variety of serial interfaces A specific clock edge rising or falling is used to shift out transmit data while the other clock edge is used to latch in receive data Bit SSCPH selects the leading edge or the trailing edge for each function Bit SSCPO selects the level of the clock line in the idle state So for an idle high clock the leading edge is a falling one a 1 to 0 transition Figure 12 3 is a summary Serial Clock SCLK ier LK X YX on on a oe MTSR MRST First Last Bit i Transmit Data Bit Latch Data MCD01960 Shift Data Figure 12 3 Serial Clock Phase and Polarity Options User s Manual 12 6 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 1 Full Duplex Operation The different devices are connected through three lines The definition of these lines is always determined by the master The line connected to the master s data output pin MTSR is the transmit line the receive line is connected to its data input line MRST and the clock line is connected to pin SCLK Only the device selected for master operation generates and outputs the serial clock on pin SCLK All slaves receive this clock so their pin SCLK must be switched to input mode DP3 13 0 The output of the master s shift register is connected to the external transmit line which in turn is connected to the slaves shift register i
257. basic interrupt response time for the C167CS is 3 instruction cycles Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 H DECODE N 1 N TRAP 1 TRAP 2 EXECUTE N 2 N 1 N TRAP WRITEBACK N 3 N 2 N 1 N IR Flag MCT04332 Figure 5 4 Pipeline Diagram for Interrupt Response Time All instructions in the pipeline including instruction N during which the interrupt request flag is set are completed before entering the service routine The actual execution time for these instructions e g waitstates therefore influences the interrupt response time In Figure 5 4 the respective interrupt request flag is set in cycle 1 fetching of instruction N The indicated source wins the prioritization round during cycle 2 In cycle 3 a TRAP instruction is injected into the decode stage of the pipeline replacing instruction N 1 and clearing the source s interrupt request flag to 0 Cycle 4 completes the injected TRAP instruction save PSW IP and CSP if segmented mode and fetches the first instruction I1 from the respective vector location All instructions that entered the pipeline after setting of the interrupt request flag N 1 N 2 will be executed after returning from the interrupt service routine The minimum interrupt response time is 5 states 10 TCL This requires program execution from the internal code memory no external operand read requests and setting the interr
258. ble Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal program memory disabled accesses to the ROM area use the external bus 1 Internal program memory enabled SGTDIS Segmentation Disable Enable Control Cleared after reset 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7FFF 1 Internal ROM area mapped to segment 1 01 0000 01 7 FFF STKSZ System Stack Size Selects the size of the system stack in the internal RAM from 32 to 1024 words Note Register SYSCON cannot be changed after execution of the EINIT instruction Bit SGTDIS controls the correct stack operation push pop of CSP or not during traps and interrupts The layout of the BUSCON registers and ADDRSEL registers is identical respectively Registers BUSCON4 BUSCON1 which control the selected address windows are completely under software control while register BUSCONO which e g is also used for the very first code access after reset is partly controlled by hardware i e it is initialized via PORTO during the reset sequence This hardware control allows to define an appropriate external bus for systems
259. bled by bit PENx If the output is not enabled the respective pin can be used for general purpose IO and the PWM channel can only be used to generate an interrupt request PWMCON 1 PWM Control Register 1 SFR FF32 99 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB PEN PEN PEN PEN PS3 PS2 01 PM3 PM2 PM1 PMO 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw Bit Function PENx PWM Channel x Output Enable Bit 0 Channel x output signal disabled generate interrupt only E Channel x output signal enabled PMx PWM Channel x Mode Control Bit 0 Channel x operates in mode 0 i e edge aligned PWM 1 Channel x operates in mode 1 i e center aligned PWM PBO1 PWM Channel 0 1 Burst Mode Control Bit 0 Channel 0 and channel 1 work independently in their respective standard mode 1 Outputs of channels 0 and 1 are ANDed to POUTO in burst mode PSx PWM Channel x Single Shot Mode Control Bit 0 Channel x works in respective standard mode 1 Channel x operates in single shot mode User s Manual 17 13 V2 0 2000 07 o nfineon es technologies Derivatives The Pulse Width Modulation Module 17 3 Interrupt Request Generation Each of the four channels of the PWM module can generate an individual interrupt request Each of these channel interrupts can activate the common module interrupt which actually interrupts the CPU Thi
260. ccess external memory before a jump to segment 0 in this case is executed General Rules When mapping the code memory no instruction or data accesses should be made to the internal memory otherwise unpredictable results may occur To avoid these problems the instructions that configure the internal code memory should be executed from external memory or from the on chip RAM Whenever the internal code memory is disabled enabled or remapped the DPPs must be explicitly re loaded to enable correct data accesses to the internal and or external memory User s Manual 22 18 V2 0 2000 07 o nfineon ed technologies Derivatives The Register Set 23 The Register Set This section summarizes all registers which are implemented in the C167CS and explains the description format which is used in the chapters describing the function and layout of the SFRs For easy reference the registers are ordered according to two different keys except for GPRs Ordered by address to check which register a given address references Ordered by register name to find the location of a specific register 23 1 Register Description Format In the respective chapters the function and the layout of the SFRs is described in a specific format which provides a number of details about the described special function register The example below shows how to interpret these details REG NAME Name of Register E SFR A16 A8 Reset Value 15 1
261. ccwopis JAGE ccWwopi2 rw rw rw rw rw rw rw rw User s Manual 16 10 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units Capture Compare Mode Registers for the CAPCOM2 Unit CC16 CC32 CCMA CAPCOM Mode Ctrl Reg 4 SFR FF224 91 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Acc ccmopig CC ccwopis ACC ccmopi7 AGC ccmopie rw rw rw rw rw rw rw rw CCM5 CAPCOM Mode Ctrl Reg 5 SFR FF244 92 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ACC ACC ACC a ccMop23 ccwop22 A amp ccmop21 amp k ccMoD20 nw rw rw rw rw rw rw rw CCM6 CAPCOM Mode Ctrl Reg 6 SFR FF26 93 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ACC ACC ACC ge ccMop27 ALC ccMop2e AZ ccmop2s ccMOoD24 rw rw rw rw rw rw rw rw CCM7 CAPCOM Mode Cirl Reg 7 SFR FF28 4 941 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ACC ACC ACC amp ccMopsi ccmop30 ccmop29 CCMOD28 rw rw rw rw rw rw rw rw Bit Function CCMODx Mode Selection for Capture Compare Register CCx The available capture compare modes are listed in Table 16 5 ACCx
262. ce state and are available for general purpose IO The pullup devices are also active during bus hold on the selected CS lines while HLDA is active and the respective pin is switched to push pull mode Open drain outputs will float during bus hold In this case external pullup devices are required or the new bus master is responsible for driving appropriate levels on the CS lines Segment Address versus Chip Select The external bus interface of the C167CS supports many configurations for the external memory By increasing the number of segment address lines the C167CS can address a linear address space of 256 KByte 1 MByte or 16 MByte This allows to implement a large sequential memory area and also allows to access a great number of external devices using an external decoder By increasing the number of CS lines the C167CS can access memory banks or peripherals without external glue logic These two features may be combined to optimize the overall system performance Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmentation disabled User s Manual 9 11 V2 0 2000 07 d nfineon ed technologies Derivatives The External Bus Interface 9 3 Programmable Bus Characteristics Important timing characteristics of the external bus interface have been made user programmable to allow to adapt it to a wide range of different external bus and memory
263. cesses to the internal ROM by any instruction which is executed from any location outside the on chip mask ROM including IRAM XRAM and external memory A program cannot read any data out of the protected ROM from outside The read data will be replaced by the default value 009B for any read access to any location No codes fetches from the internal ROM by any instruction which is executed from any location outside the on chip mask ROM including IRAM XRAM and external memory A program cannot branch to a location within the protected ROM from outside This applies to JUMPs as well as to RETurns i e a called routine within RAM or external memory can never return to the protected ROM The fetched code will be replaced by the default value 009BH for any access to any location This default value will be decoded as the instruction TRAP 00 which will restart program execution at location 00 0000 Note ROM protection may be used for applications where the complete software fits into the on chip ROM or where the on chip ROM holds an initialization software which is then replaced by an external e g application software In the latter case no data constants tables etc can be stored within the ROM The ROM itself should be mapped to segment 1 before branching outside so an interrupt vector table can established in external memory User s Manual 3 13 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Pro
264. cessing Unit CPU 4 The Central Processing Unit CPU Basic tasks of the CPU are to fetch and decode instructions to supply operands for the arithmetic and logic unit ALU to perform operations on these operands in the ALU and to store the previously calculated results As the CPU is the main engine of the C167CS controller it is also affected by certain actions of the peripheral subsystem Since a four stage pipeline is implemented in the C167CS up to four instructions can be processed in parallel Most instructions of the C167CS are executed in one machine cycle 2 CPU clock periods due to this parallelism This chapter describes how the pipeline works for sequential and branch instructions in general and which hardware provisions have been made to speed the execution of jump instructions in particular The general instruction timing is described including standard and exceptional timing While internal memory accesses are normally performed by the CPU itself external peripheral or memory accesses are performed by a particular on chip External Bus Controller EBC which is automatically invoked by the CPU whenever a code or data address refers to the external address space CPU gt Internal SP RAM STKOV MDL SKON ML Exec Unit Mul Div HW Instr Ptr Bit Mask Gen General Instr Reg Purpose ROM d 16 bit ipeline egisters Barrel Shifter PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON
265. cessor Status Word PSW This bit addressable register reflects the current state of the microcontroller Two groups of bits represent the current ALU status and the current CPU interrupt status A separate bit USRO within register PSW is provided as a general purpose user flag PSW Program Status Word SFR FF10 884 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HLD MUL ILVL IEN EN USRO ip E Z V C N rwh w rw rw rwh rwh rwh rwh rwh rwh Bit Function N Negative Result Set when the result of an ALU operation is negative C Carry Flag Set when the result of an ALU operation produces a carry bit V Overflow Result Set when the result of an ALU operation produces an overflow Z Zero Flag Set when the result of an ALU operation is zero E End of Table Flag Set when the source operand of an instruction is 80004 or 80y MULIP Multiplication Division In Progress 0 There is no multiplication division in progress 1 A multiplication division has been interrupted USRO User General Purpose Flag May be used by the application software HLDEN ILVL Interrupt and EBC Control Fields IEN Define the response to interrupt requests and enable external bus arbitration Described in Chapter 5 ALU Status N C V Z E MULIP The condition flags N C V Z E within the PSW indicate the ALU status due to the last recent
266. chnology Complete Development Support For the development tool support of its microcontrollers Infineon follows a clear third party concept Currently around 120 tool suppliers world wide ranging from local niche manufacturers to multinational companies with broad product portfolios offer powerful development tools for the Infineon C500 and C166 microcontroller families guaranteeing a remarkable variety of price performance classes as well as early availability of high quality key tools such as compilers assemblers simulators debuggers or in circuit emulators Infineon incorporates its strategic tool partners very early into the product development process making sure embedded system developers get reliable well tuned tool solutions which help them unleash the power of Infineon microcontrollers in the most effective way and with the shortest possible learning curve The tool environment for the Infineon 16 bit microcontrollers includes the following tools Compilers C MODULA2 FORTH Macro assemblers linkers locators library managers format converters Architectural simulators e HLL debuggers Real time operating systems e VHDL chip models e In circuit emulators based on bondout or standard chips Plug in emulators Emulation and clip over adapters production sockets Logic analyzer disassemblers Starter kits Evaluation boards with monitor programs Industrial boards also for CAN FUZZY PROFIBUS
267. chosen from 2 bits to 16 bits e transfer may start with the LSB or the MSB e the shift clock may be idle low or idle high data bits may be shifted with the leading or trailing edge of the clock signal the baudrate may be set within a wide range see baudrate generation e the shift clock can be generated master or received slave This allows the adaptation of the SSC to a wide range of applications where serial data transfer is required User s Manual 12 5 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface The Data Width Selection supports the transfer of frames of any length from 2 bit characters up to 16 bit characters Starting with the LSB SSCHB 0 allows communication e g with ASCO devices in synchronous mode C166 Family or 8051 like serial interfaces Starting with the MSB SSCHB 1 allows operation compatible with the SPI interface Regardless which data width is selected and whether the MSB or the LSB is transmitted first the transfer data is always right aligned in registers SSCTB and SSCRB with the LSB of the transfer data in bit O of these registers The data bits are rearranged for transfer by the internal shift register logic The unselected bits of SSCTB are ignored the unselected bits of SSCRB will be not valid and should be ignored by the receiver service routine The Clock Control allows the adaptation of transmit and receive beh
268. ck In these cases an instruction that does not access these resources should be inserted Code accesses to the new ROM area are only possible after an absolute branch to this area Note As a rule instructions that change ROM mapping should be executed from internal RAM or external memory User s Manual 4 8 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU BUSCON ADDRSEL The instruction following an instruction that changes the properties of an external address area cannot access operands within the new area In these cases an instruction that does not access this address area should be inserted Code accesses to the new address area should be made after an absolute branch to this area Note As a rule instructions that change external bus properties should not be executed from the respective external memory area Timing Instruction pipelining reduces the average instruction processing time in a wide scale from four to one machine cycles mostly However there are some rare cases where a particular pipeline situation causes the processing time for a single instruction to be extended either by a half or by one machine cycle Although this additional time represents only a tiny part of the total program execution time it might be of interest to avoid these pipeline caused time delays in time critical program modules Besides a general execution time description Section 4 3 provides so
269. complete This allows the transmission of characters back to back without gaps Data reception is enabled by the Receiver Enable Bit SOREN After reception of a character has been completed the received data and if provided by the selected operating mode the received parity bit can be read from the read only Receive Buffer register SORBUF Bits in the upper half of SORBUF which are not valid in the selected operating mode will be read as zeros Data reception is double buffered so that reception of a second character may already begin before the previously received character has been read out of the receive buffer register In all modes receive buffer overrun error detection can be selected through bit User s Manual 11 3 V2 0 2000 07 j d nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface SOOEN When enabled the overrun error status flag SOOE and the error interrupt request flag SOEIR will be set when the receive buffer register has not been read by the time reception of a second character is complete The previously received character in the receive buffer is overwritten The Loop Back option selected by bit SOLB allows the data currently being transmitted to be received simultaneously in the receive buffer This may be used to test serial communication routines at an early stage without having to provide an external network In loop back mode the alternate input output functions of the
270. converting can be programmed within a certain range in the C167CS relative to the CPU clock The absolute time that is consumed by the different conversion steps therefore is independent from the general speed of the controller This allows adjusting the A D converter of the C167CS to the properties of the system Fast Conversion can be achieved by programming the respective times to their absolute possible minimum This is preferable for scanning high frequency signals The internal resistance of analog source and analog supply must be sufficiently low however High Internal Resistance can be achieved by programming the respective times to a higher value or the possible maximum This is preferable when using analog sources and supply with a high internal resistance in order to keep the current as low as possible The conversion rate in this case may be considerably lower however The conversion time is programmed via the upper two bits of register ADCON Bitfield ADCTC conversion time control selects the basic conversion clock fac used for the operation of the A D converter The sample time is derived from this conversion clock Table 18 2 lists the possible combinations The timings refer to CPU clock cycles where tepu 1 fopu The limit values for fac see data sheet must not be exceeded when selecting ADCTC and fcpy Table 18 2 ADC Conversion Timing Control ADCON 15 14 A D Converter ADCON 13 12 Sample
271. ct registers programmable ADDRSELx and hardwired XADRSx This comparison is done in four levels Priority 1 Priority 2 Priority 3 Priority 4 The hardwired XADRSx registers are evaluated first A match with one of these registers directs the access to the respective X Peripheral using the corresponding XBCONXx register and ignoring all other ADDRSELx regis ters Registers ADDRSEL2 and ADDRSEL4 are evaluated before ADDRSEL1 and ADDRSELS respectively A match with one of these registers directs the access to the respective external area using the corresponding BUS CONXx register and ignoring registers ADDRSEL1 3 see Figure 9 11 A match with registers ADDRSEL1 or ADDRSELS directs the access to the respective external area using the corresponding BUSCONx register If there is no match with any XADRSx or ADDRSELx register the access to the external bus uses register BUSCONO XBCONO BUSCON2 BUSCON1 BUSCONO H E m BUSCON4 BUSCONS Ise C E amm 3 Active Window Inactive Window C MCA04368 Figure 9 11 Address Window Arbitration Note Only the indicated overlaps are defined All other overlaps lead to erroneous bus cycles E g ADDRSEL4 may not overlap ADDRSEL2 or ADDRSEL1 The hardwired XADRSx registers are defined non overlapping User s Manual 9 27 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface
272. d 1G Alternate Output Function Enabled T3OTL Timer 3 Output Toggle Latch Toggles on each overflow underflow of T3 Can be set or reset by software 1 For the effects of bits T3UD and T3UDE refer to the direction Table 10 1 User s Manual 10 3 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer 3 Run Bit The timer can be started or stopped by software through bit T3R Timer T3 Run Bit If T3R 0 the timer stops Setting T3R to 1 will start the timer In gated timer mode the timer will only run if T3R 1 and the gate is active high or low as programmed Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T3EUD Timer T3 External Up Down Control Input which is the alternate input function of port pin P3 4 These options are selected by bits T3UD and T3UDE in control register T3CON When the up down control is done by software bit T3UDE 0 the count direction can be altered by setting or clearing bit T3UD When T3UDE 1 pin T3EUD is selected to be the controlling source of the count direction However bit T3UD can still be used to reverse the actual count direction as shown in Table 10 1 If T3UD 0 and pin T3GEUD shows a low level the timer is counting up With a high level at T3bEUD the timer is counting down If T3UD 1 a high level at pin T3EUD
273. d Output Waveform in Mode 1 User s Manual 17 6 V2 0 2000 07 o nfineon en technologies Derivatives The Pulse Width Modulation Module Burst Mode Burst mode is selected by setting bit PBO1 in register PWMCON1 to 1 This mode combines the signals from PWM channels 0 and 1 onto the port pin of channel 0 The output of channel 0 is replaced with the logical AND of channels 0 and 1 The output of channel 1 can still be used at its associated output pin if enabled Each of the two channels can either operate in mode O or 1 Note It is guaranteed by design that no spurious spikes will occur at the output pin of channel 0 in this mode The output of the AND gate will be transferred to the output pin synchronously to internal clocks XORing of the PWM signal and the port output latch value is done after the ANDing of channel 0 and 1 PPO Period Value PTO Count Value Channel 0 PP1 Count Channel 1 Resulting Output POUTO MCAO01951 Figure 17 5 Operation and Output Waveform in Burst Mode User s Manual 17 7 V2 0 2000 07 o nfineon es technologies Derivatives The Pulse Width Modulation Module Single Shot Mode Single shot mode is selected by setting the respective bit PSx in register PWMCON 1 to 1 This mode is available for PWM channels 2 and 3 In this mode the timer PTx of the
274. d as a 48 bit timer which is clocked with the RTC input frequency divided by the fixed prescaler The reload register T14REL should be cleared to get a 48 bit binary timer However any other reload value may be used The maximum usable timespan is 249 1014 T14 input clocks which would equal more than 100 years at an oscillator frequency of 20 MHz User s Manual 14 2 V2 0 2000 07 o nfineon e technologies Derivatives The Real Time Clock RTC Register Access The actual value of the RTC is represented by the 3 registers T14 RTCL and RTCH As these registers are concatenated to build the RTC counter chain internal overflows occur while the RTC is running When reading or writing the RTC value make sure to account for such internal overflows in order to avoid reading writing corrupted values When reading writing e g 0000 to RTCH and then accessing RTCL will produce a corrupted value as RTCL may overflow before it can be accessed In this case however RTCH would be 00014 The same precautions must be taken for T14 and T14REL RTC Interrupt Generation The RTC interrupt shares the XPER3 interrupt node with the PLL OWD interrupt This is controlled by the interrupt subnode control register ISNC The interrupt handler can determine the source of an interrupt request via the separate interrupt request and enable flags see Figure 14 3 provided in register ISNC Note If only one source is enabled no additional software check is
275. d do Table 5 6 Software Controlled Interrupt Classes Example ILVL GLVL Interpretation Priority 5 l gt 1 15 PEC service on up to 8 channels 14 13 12 X X X Interrupt Class 1 11 X 5 sources on 2 levels 10 9 8 X X X Interrupt Class 2 7 X x x 9 sources on 3 levels 6 X 5 X X X Interrupt Class 3 4 X 5 sources on 2 levels 3 2 1 0 No service User s Manual 5 17 V2 0 2000 07 d Infineon iiis technologies Derivatives Interrupt and Trap Functions 5 4 Saving the Status During Interrupt Service Before an interrupt request that has been arbitrated is actually serviced the status of the current task is automatically saved on the system stack The CPU status PSW is saved along with the location where the execution of the interrupted task is to be resumed after returning from the service routine This return location is specified through the Instruction Pointer IP and in case of a segmented memory model the Code Segment Pointer CSP Bit SGTDIS in register SYSCON controls how the return location is stored The system stack receives the PSW first followed by the IP unsegmented or followed by CSP and then IP segmented mode This optimizes the usage of the system stack if segmentation is disabled The CPU priority field ILVL in PSW is updated with the priority of the interrupt request that is to be serviced s
276. d register RTCH FOD6y 6By UUUU High word of RTC register RTCL FOD4y 6Ay UUUU Low word of RTC register Note The RTC registers are not affected by a reset After a power on reset however they are undefined User s Manual 14 1 V2 0 2000 07 o nfineon ed technologies Derivatives The Real Time Clock T14REL Interrupt Request MCD04432 Figure 14 2 RTC Block Diagram System Clock Operation A real time system clock can be maintained that keeps on running also during idle mode and power down mode optionally and represents the current time and date This is possible as the RTC module is not effected by a reset The maximum resolution minimum stepwidth for this clock information is determined by timer T14 s input clock The maximum usable timespan is achieved when T14REL is loaded with 0000 and so T14 divides by 216 Cyclic Interrupt Generation The RTC module can generate an interrupt request whenever timer T14 overflows and is reloaded This interrupt request may e g be used to provide a system time tick independent of the CPU frequency without loading the general purpose timers or to wake up regularly from idle mode The interrupt cycle time can be adjusted via the timer T14 reload register T14REL Please refer to RTC Interrupt Generation below for more details 48 bit Timer Operation The concatenation of the 16 bit reload timer T14 and the 32 bit RTC timer can be regarde
277. d values Usually the CPU will clear this bit before working on the data and verify that the bit is still cleared once it has finished working to ensure that it has worked on a consistent set of data and not part of an old message and part of the new message For transmit objects the CPU will set this bit along with clearing bit CPUUPD This will ensure that if the message is actually being transmitted during the time the message was being updated by the CPU the CAN controller will not reset bit TXRQ In this way bit TXRQ is only reset once the actual data has been transferred When the CPU requests the transmission of a receive object a remote frame will be sent instead of a data frame to request a remote node to send the corresponding data frame This bit will be cleared by the CAN controller along with bit RMTPND when the message has been successfully transmitted if bit NEWDAT has not been set If there are several valid message objects with pending transmission request the message with the lowest message number is transmitted first This arbitration is done when several objects are requested for transmission by the CPU or when operation is resumed after an error frame or after arbitration has been lost Arbitration Registers The Arbitration Registers UARn amp LARn are used for acceptance filtering of incoming messages and to define the identifier of outgoing messages A received message with a matching identifier is accepted as a data fram
278. ddition T3OTL can be used in conjunction with the timer over underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4 For this purpose the state of T3OTL does not have to be available at pin T3OUT because an internal connection is provided for this option Timer 3 in Timer Mode Timer mode for the core timer T3 is selected by setting bit field T3M in register T2CON to 000p In this mode T3 is clocked with the internal system clock CPU clock divided by a programmable prescaler which is selected by bit field T3l The input frequency frs for timer T3 and its resolution rr are scaled linearly with lower clock frequencies fopy as can be seen from the following formula cPU 8 x o T3l rra us ft3 Bx xt fopu MHz Interrupt Request TxOUT MCB02028 TSEUD P3 4 X 3 TSOUT P3 3 n 3 10 Figure 10 3 Block Diagram of Core Timer T3 in Timer Mode User s Manual 10 5 V2 0 2000 07 e nfineon technologies C167CS Derivatives The General Purpose Timer Units The timer input frequencies resolution and periods which result from the selected prescaler option are listed in Table 10 2 This table also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits Table 10 2 GPT1 T
279. dered by Name Name Physical 8 bit Description Reset Address Addr Value ADCIC b FF98 CC A D Converter End of Conversion Interrupt 00004 Control Register ADCON b FFA0 DOW A D Converter Control Register 00004 ADDAT FEAO 504 A D Converter Result Register 0000 ADDAT2 FOAO E 504 _ A D Converter 2 Result Register 00004 ADDRSEL1 FE18 OC Address Select Register 1 00004 ADDRSEL2 FE1A OD Adadress Select Register 2 00004 ADDRSEL3 FE1C OE Adadress Select Register 3 00004 ADDRSEL4 FE1E OF Adadress Select Register 4 00004 ADEIC b FF9A CD A D Converter Overrun Error Interrupt 0000 Control Register BUSCONO b FFOC 864 Bus Configuration Register 0 00004 BUSCONT1 b FF14 8A Bus Configuration Register 1 0000 BUSCON b FF16 8B Bus Configuration Register 2 0000 BUSCONS b FF18 8C Bus Configuration Register 3 0000 BUSCON4 b FF1A 18D Bus Configuration Register 4 0000 C1BTR EF044 X CAN1 Bit Timing Register UUUU C1CSR EFOO X CAN 1 Control Status Register XX014 C1GMS EF064 X CAN1 Global Mask Short UFUU CiLARn EFn4 X CAN 1 Lower Arbitration Register msg n UUUU C1LGML EFOA X CAN1 Lower Global Mask Long UUUUJ C1LMLM EFOE X CAN1 Lower Mask of Last Message UUUU C1MCFGn EFn6y X CAN1 Message Configuration Register UU msg n C1MCRn EFnO X CAN1 Message Ctrl Reg msg n UUUU User s Manual 23 4 V2 0 2000 07 o nfineon technologies C167CS Derivativ
280. directional reset feature in an application Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset The reset indication flags always indicate a long hardware reset The PORTO configuration is treated like on a hardware reset Especially the bootstrap loader may be activated when POL 4 is low Pin RSTIN may only be connected to external reset devices with an open drain output driver Ashort hardware reset is extended to the duration of the internal reset sequence User s Manual 8 3 V2 0 2000 07 _ d nfineon e technologies Derivatives Dedicated Pins The Reset Output RSTOUT provides a special reset signal for external circuitry RSTOUT is activated at the beginning of the reset sequence triggered via RSTIN a watchdog timer overflow or by the SRST instruction RSTOUT remains active low until the EINIT instruction is executed This allows to initialize the controller before the external circuitry is activated Note During emulation mode pin RSTOUT is used as an input and therefore must be driven by the external circuitry The Power Supply pins for the Analog Digital Converter VAREF and VAGND provide a separate power supply reference voltage for the on chip ADC This reduces the noise that is coupled to the analog input signals from the digital logic sections and so improves the stability of the conversion results when VAREF and VAGND are properly disco
281. dr Value POCONOL F080 E 40 Port POL Output Control Register 0000 POCON1H F086 E 434 Port P1H Output Control Register 0000 POCON1L F084 E 424 Port P1L Output Control Register 00004 POCON2 F088 E 444 Port P2 Output Control Register 00004 POCON20 FOAA E 554 Dedicated Pin Output Control Register 0000 POCONS3 FO8A E 454 Port P3 Output Control Register 00004 POCONA F08C E 464 Port P4 Output Control Register 00004 POCON6 FO8E E 474 Port P6 Output Control Register 0000 POCON7 F090 E 48 Port P7 Output Control Register 0000 POCONS8 F092 E 494 Port P8 Output Control Register 0000 PPO F038 E 1C PWM Module Period Register 0 0000 PP1 FOSA E 1D PWM Module Period Register 1 0000 PP2 FO3C E 1E PWM Module Period Register 2 0000 PP3 FOSE E 1F4 PWM Module Period Register 3 0000 PSW b FF10 88 CPU Program Status Word 0000 PTO F030 E 184 PWM Module Up Down Counter 0 00004 PT1 F0324 E 194 PWM Module Up Down Counter 1 00004 PT2 F0344 E 1Ay PWM Module Up Down Counter 2 00004 PT3 F0364 E 1B4 PWM Module Up Down Counter 3 00004 Pwo FE30y 18 PWM Module Pulse Width Register 0 0000 PW1 FE32y 19 PWM Module Pulse Width Register 1 0000 PW2 FE344 1A4 PWM Module Pulse Width Register 2 00004 PW3 FE36 1B PWM Module Pulse Width Register 3 0000 PWMCONoOb FF30 98 PWM Module Control Register 0 0000 PWMCON1b FF324 99 PWM Module Control Register 1 0000 PWMIC b F17E E BF PWM Mo
282. drain control register ODP6 P6 Port 6 Data Register SFR FFCC E6 Reset Value 00 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 P6 7 P6 6 P6 5 P6 4 P6 3 P6 2 P6 1 P6 0 Bit Function P6 y Port data register P6 bit y DP6 P6 Direction Ctrl Register SFR FFCEJ E74 Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP6 DP6 DP6 DP6 DP6 DP6 DP6 DP6 7 6 5 4 3 2 1 0 Bit Function DP6 y Port direction register DP6 bit y DP6 y 0 Port line P6 y is an input high impedance DP6 y 1 Port line P6 y is an output User s Manual 7 42 V2 0 2000 07 d nfineon e technologies Derivatives Parallel Ports ODP6 P6 Open Drain Ctrl Reg ESFR F1CEJ E74 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 one a ES kr ie E en rA vd rw rw rw rw rw rw rw rw Bit Function ODP6 y Port 6 Open Drain control register bit y ODP6 y 0 Port line P6 y output driver in push pull mode ODP6 y 1 Port line P6 y output driver in open drain mode Alternate Functions of Port 6 A programmable number of chip select signals CS4 CSO derived from the bus control registers BUSCON4 BUSCONO can be output on 5 pins of Port 6 The other 3 pins may be used for bus arbitration to acc
283. dule Interrupt Control Register 00004 RPOH b F1084 E 84 System Startup Configuration Register XXy read only RSTCON b F1E0 m Reset Control Register OOXXy RTCH FOD6 E 6B RTC High Register XXXXy User s Manual 23 10 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value RTCL FOD4 EJ6A RTC Low Register XXXXy SOBG FEBA4 5Ay_ Serial Channel 0 Baud Rate Generator 00004 Reload Register SOCON b FFBOj D84 Serial Channel 0 Control Register 0000 SOEIC b FF70 B84 Serial Channel 0 Error Interrupt Control 00004 Register SORBUF FEB2 594 Serial Channel 0 Receive Buffer Register XXXXy read only SORIC b FFe6E B7 Serial Channel 0 Receive Interrupt Control 0000 Register SOTBIC b F19Cj E CE Serial Channel 0 Transmit Buffer Interrupt 0000 Control Register SOTBUF FEBO 584 Serial Channel 0 Transmit Buffer Register 0000 SOTIC b FF6C B6 Serial Channel 0 Transmit Interrupt Control 0000 Register SP FE124 09 CPU System Stack Pointer Register FCOO SSCBR FOB4 E 5Ay SSC Baudrate Register 0000 SSCCON b FFB2 D94 SSC Control Register 0000 SSCEIC b FF76 BBy SSC Error Interrupt Control Register 00004 SSCRB FOB2 E59 SSC Receive Buffer XXXXy SSCRIC b FF
284. e matching object has DIR 0 oras a remote frame matching object has DIR 1 For matching the corresponding Global Mask has to be considered in case of message object 15 also the Mask of Last Message Extended frames using Global Mask Long can be stored only in message objects with XTD 1 standard frames using Global Mask Short only in message objects with XTD 0 Message objects should have unique identifiers i e if some bits are masked out by the Global Mask Registers i e don t care then the identifiers of the valid message objects should differ in the remaining bits which are used for acceptance filtering If a received message data frame or remote frame matches with more than one valid message object it is associated with the object with the lowest message number l e a received data frame is stored in the lowest object or the lowest object is sent in response to a remote frame The Global Mask is used for matching here User s Manual 19 21 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface After a transmission data frame or remote frame the transmit request flag of the matching object with the lowest message number is cleared The Global Mask is not used in this case When the CAN controller accepts a data frame the complete message is stored into the corresponding message object including the identifier also masked bits standard iden
285. e Timer Units Table 10 8 GPT1 Auxiliary Timer Counter Mode Input Edge Selection T2l TAI Triggering Edge for Counter Increment Decrement X00 None Counter Tx is disabled 0 0 1 Positive transition rising edge on TxIN 010 Negative transition falling edge on TxIN 0 1 1 Any transition rising or falling edge on TxIN 101 Positive transition rising edge of output toggle latch T3OTL 110 Negative transition falling edge of output toggle latch T3OTL 111 Any transition rising or falling edge of output toggle latch T3OTL Note Only state transitions of T3OTL which are caused by the overflows underflows of T3 will trigger the counter function of T2 T4 Modifications of T3OTL via software will NOT trigger the counter function of T2 T4 For counter operation pin TxIN must be configured as input i e the respective direction control bit must be 0 The maximum input frequency which is allowed in counter mode is fcpu 16 To ensure that a transition of the count input signal which is applied to TxIN is correctly recognized its level should be held for at least 8 fcpy cycles before it changes User s Manual 10 15 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer Concatenation Using the toggle bit T3OTL as a clock source for an auxiliary timer in counter mode concatenates the core timer T3 with the respective auxiliary timer Depending on which transit
286. e a controlled shutdown sequence bringing the system into a defined and safe idle state or it can provide an emergency operation of the system with reduced performance based on this normally slower emergency clock Note The CPU clock source is only switched back to the oscillator clock after a hardware reset The oscillator watchdog can be disabled by setting bit OWDDIS in register SYSCON In this case the PLL remains idle and provides no clock signal while the CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD Also no interrupt request will be generated in case of a missing oscillator clock Note At the end of an external reset bit OWDDIS reflects the inverted level of pin RD at that time Thus the oscillator watchdog may also be disabled via hardware by externally pulling the RD line low upon a reset similar to the standard reset configuration via PORTO The oscillator watchdog cannot provide full security while the CPU clock signal is generated by the SlowDown Divider because the OWD cannot switch to the PLL clock in this case see Figure 6 4 OWD interrupts are only recognizable if fosc is still available e g input frequency too low or intermittent failure only A broken crystal cannot be detected by software OWD interrupt server as no SDD clock is available in such a case User s Manual 6 8 V2 0 2000 07 o nfineon ed technologies Derivatives Clock Generation 6 4 Clock Dri
287. e capable of requesting interrupt or PEC service in the C167CS the associated interrupt vectors their locations and the associated trap numbers It also lists the mnemonics of the affected Interrupt Request flags and their corresponding Interrupt Enable flags The mnemonics are composed of a part that specifies the respective source followed by a part that specifies their function IR Interrupt Request flag IE Interrupt Enable flag Note Each entry of the interrupt vector table provides room for two word instructions or one doubleword instruction The respective vector location results from multiplying the trap number by 4 4 Bytes per entry All interrupt nodes that are currently not used by their associated modules or are not connected to a module in the actual derivative may be used to generate software controlled interrupt requests by setting the respective IH flag User s Manual 5 2 V2 0 2000 07 o nfineon technologies C167CS Derivatives Table 5 1 Interrupt and Trap Functions C167CS Interrupt Notes and Vectors Source of Interrupt or Request Enable Interrupt Vector Trap PEC Service Request Flag Flag Vector Location Number CAPCOM Register 0 CCOIR CCOIE CCOINT 00 0040 10 16p CAPCOM Register 1 CC1IR CC1IE CCAINT 00 0044 11 17p CAPCOM Register 2 CC2IR CC2IE CC2INT 00 0048 12 18p
288. e default configuration values which are selected and the bitfields that permit software modification System Startup Configuration upon a Single Chip Mode Reset Table 20 7 Default Configuration for Single Chip Mode Reset Configuration Default Values External Software Access Parameter RPOH XX2D Config CLKCFG Generation 001 Prescaler operation P0 15 13 RSTCON 15 13 mode of basic clock i e fepy fosc 2 SALSEL Number of 01 No segment address P0 12 11 RSTCON 12 11 active segment lines address lines CSSEL Number of 10 No chip select lines P0 10 9 RSTCON 10 9 active CS lines WRC Write signal RPOH O 1 P0 8 SYSCON WRCFG encoding SYSCON WRCFG 0 i e WR and BHE BTYP Default bustype BUSCONO BTYP 11 P0 7 6 BUSCONO BTYP BUSCONO i e 16 bit MUX bus SMOD Special modes Startup modes selected via P0 5 2 start boot modes pins RD and ALE ADP Adapt mode Not possible PO 1 EMU Emulation mode Not possible P0 0 OWD disable SYSCON OWDDIS 0 RD SYSCON OWDDIS i e OWD is active 1 Refers to the configuration pins which are replaced by the default values 2 Software can modify the default values via these bitfields Note Single chip mode reset cannot be selected on ROMless devices The attempt to read the first instruction after reset will fail in such a case User s Manual 20 20 V2 0 2000 07 o nfineo
289. e done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0 Pin RSTIN is an input only 1 Pin RSTIN is pulled low during the internal reset sequence after any reset OWDDIS Oscillator Watchdog Disable Bit Configured via pin RD upon a reset 0 The on chip oscillator watchdog is enabled and active 1 The on chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input User s Manual 9 20 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Bit Function CSCFG Chip Select Configuration Control Cleared after reset 0 Latched CS mode The CS signals are latched internally and driven to the enabled port pins synchronously 1 Unlatched CS mode The CS signals are directly derived from the address and driven to the enabled port pins WRCFG Write Configuration Control Configured via pin POH O upon a reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH CLKEN System Clock Output Enable CLKOUT cleared after reset 0 CLKOUT disabled pin may be used for FOUT or gen purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Ena
290. e for each port line If the respective control bit ODPx y is 0 default after reset the output driver is in the push pull mode If ODPx y is 1 the open drain configuration is selected Note that all ODPx registers are located in the ESFR space 1 1 Push Pull Output Driver Open Drain Output Driver MCS01975 Figure 7 3 Output Drivers in Push Pull Mode and in Open Drain Mode User s Manual 7 4 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Driver Characteristic This defines either the general driving capability of the respective driver or if the driver strength is reduced after the target output level has been reached or not Reducing the driver strength increases the output s internal resistance which attenuates noise that is imported exported via the output line For driving LEDs or power transistors however a stable high output current may still be required The controllable output drivers of the C167CS pins feature two differently sized transistors strong and weak for each direction push and pull The time of activating deactivating these transistors determines the output characteristics of the respective port driver Three modes can be selected to adapt the driver characteristics to the application s requirements In High Current Mode both transistors are activated all the time In this case the driver provides maximum output current even af
291. e is exited with the RETI instruction this bit is implicitly tested before the old PSW is popped from the stack If MULIP 1 the multiply divide instruction is re read from the location popped from the stack return address and will be completed after the RETI instruction has been executed Note The MULIP flag is part of the context of the interrupted task When the interrupting routine does not return to the interrupted task e g scheduler switches to another task the MULIP flag must be set or cleared according to the context of the task that is switched to BCD Calculations No direct support for BCD calculations is provided in the C167CS BCD calculations are performed by converting BCD data to binary data performing the desired calculations using standard data types and converting the result back to BCD data Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10p Conversion from BCD data to binary data is enhanced by multiple bit shift instructions This provides similar performance compared to instructions directly supporting BCD data types while no additional hardware is required User s Manual 22 3 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 1 Stack Operations The C167CS supports two types of stacks The system stack is used implicitly by the controller and is located in the internal RAM The user stack provide
292. e remapped to segment 1 01 0000 01 7F FF 4 to enable external memory access in the lower half of segment 0 or the internal ROM may be disabled at all Code and data may be stored in any part of the internal memory areas except for the SFR blocks which may be used for control data but not for instructions Note Accesses to the internal ROM area on ROMless devices will produce unpredictable results Bytes are stored at even or odd byte addresses Words are stored in ascending memory locations with the low byte at an even byte address being followed by the high byte at the next odd byte address Double words code only are stored in ascending memory locations as two subsequent words Single bits are always stored in the specified bit position at a word address Bit position 0 is the least significant bit of the byte at an even byte address and bit position 15 is the most significant bit of the byte at the next odd byte address Bit addressing is supported for a part of the Special Function Registers a part of the internal RAM and for the General Purpose Registers XXXX6 H ep mm Tnm GI omm Ie Byte XXXX3 H Byte XXXX2 H Word High Byte XXXX1 H Word Low Byte XXXX0 H XXXXF H MCD01996 Figure 3 2 Storage of Words Bytes and Bits in a Byte Organized Memory Note Byte units forming a single word or a double word must always be stored within the same physical internal external ROM R
293. e reset sequence in Bidirectional reset mode A software or WDT reset activates the RSTIN line in Bidirectional reset mode MCS02258 Figure 20 3 Reset Input and Output Signals User s Manual 20 6 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Ports and External Bus Configuration during Reset During the internal reset sequence all of the C167CS s port pins are configured as inputs by clearing the associated direction registers and their pin drivers are switched to the high impedance state This ensures that the C167CS and external devices will not try to drive the same pin to different levels Pin ALE is held low through an internal pulldown and pins RD WR and READY are held high through internal pullups Also the pins that can be configured for CS output will be pulled high The registers SYSCON and BUSCONO are initialized according to the configuration selected via PORTO When an external start is selected pin EA 0 the Bus Type field BTYP in register BUSCONO is initialized according to POL 7 and POL 6 bit BUSACTO in register BUSCONO is set to 1 bit ALECTLO in register BUSCONO is set to 1 bit ROMEN in register SYSCON will be cleared to O bit BYTDIS in register SYSCON is set according to the data bus width set if 8 bit bit WRCFG in register SYSCON is set according to pin POH O WRC When an internal start is selected pin EA 1 e register BU
294. e respective physical address calculation is identical to that for the short 4 bit GPR addresses Short 8 Bit Register Addresses mnemonic reg or bitoff within a range from FO to FF interpret the four least significant bits as short 4 bit GPR address while the four most significant bits are ignored The respective physical GPR address calculation is identical to that for the short 4 bit GPR addresses For single bit accesses on a GPR the GPR s word address is calculated as just described but the position of the bit within the word is specified by a separate additional 4 bit value User s Manual 4 26 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU Specified by reg or bitoff Internal RAM Must be within the internal RAM area For byte GPR For word GPR accesses accesses MCD02005 Figure 4 8 Implicit CP Use by Short GPR Addressing Modes The Stack Pointer SP This non bit addressable register is used to point to the top of the internal system stack TOS The SP register is pre decremented whenever data is to be pushed onto the stack and it is post incremented whenever data is to be popped from the stack Thus the system stack grows from higher toward lower memory locations Since the least significant bit of register SP is tied to 0 and bits 15 through 12 are tied to 1 by hardware the SP register can only contain values from F000 to FFFE
295. e tested bit in case of jump taken semaphore support JBC Call Instructions Conditional calling of an either absolutely or indirectly addressed subroutine within the current code segment CALLA Unconditional calling of a relatively addressed subroutine within the current code segment CALLR Unconditional calling of an absolutely addressed subroutine within any code segment CALLS Unconditional calling of an absolutely addressed subroutine within the current code segment plus an additional pushing of a selectable register onto the system stack PCALL Unconditional branching to the interrupt or trap vector jump table in code segment 0 TRAP Return Instructions Returning from a subroutine within the current code segment HET Returning from a subroutine within any code segment RETS Returning from a subroutine within the current code segment plus an additional popping of a selectable register from the system stack RETP Returning from an interrupt service routine RETI User s Manual 24 3 JMPI JMPR JNB JNBS CALLI V2 0 2000 07 o nfineon e technologies Derivatives Instruction Set Summary System Control Instructions Resetting the C167CS via software SRST Entering the Idle mode IDLE Entering the Power Down mode PWRDN Servicing the Watchdog Timer SRVWDT Disabling the Watchdog Timer DISWDT Signifying the end of the initialization routine pulls pin RSTOUT high and disables the eff
296. e to be considered e Instruction fetch from an external location Operand read from an external location e Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt response time including external accesses will occur when instructions N N 1 and N 2 are executed out of external memory instructions N 1 and N require external operand read accesses instructions N 3 through N write back external operands and the interrupt vector also points to an external location In this case the interrupt response time is the time to perform 9 word bus accesses because instruction 1 cannot be fetched via the external bus until all write fetch and read requests of preceding instructions in the pipeline are terminated e When the above example has the interrupt vector pointing into the internal code memory the interrupt response time is 7 word bus accesses plus 2 states because fetching of instruction 11 from internal code memory can start earlier e When instructions N N 1 and N 2 are executed out of external memory and the interrupt vector also points to an external location but all operands for instructions N 3 through N are in internal memory then the interrupt response time is the time to perfo
297. e transition rising edge of output toggle latch T6OTL 110 Negative transition falling edge of output toggle latch TeOTL 111 Any transition rising or falling edge of output toggle latch T6OTL Note Only state transitions of TEOTL which are caused by the overflows underflows of T6 will trigger the counter function of T5 Modifications of TGOTL via software will NOT trigger the counter function of T5 The maximum input frequency which is allowed in counter mode is fcpy 8 To ensure that a transition of the count input signal which is applied to T5lN is correctly recognized its level should be held high or low for at least 4 fcpy cycles before it changes User s Manual 10 32 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer Concatenation Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode concatenates the core timer T6 with the auxiliary timer Depending on which transition of T6OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter e 32 bit Timer Counter If both a positive and a negative transition of T6OTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T6 Thus the two timers form a 32 bit timer e 33 bit Timer Counter If either a positive or a negative transition of TGOTL is selected to clock the auxiliary timer this timer is clocked on
298. ect of any later execution of a DISWDT instruction EINIT Miscellaneous e Null operation which requires 2 Bytes of storage and the minimum time for execution NOP Definition of an unseparable instruction sequence ATOMIC Switch reg bitoff and bitaddr addressing modes to the Extended SFR space EXTR Override the DPP addressing scheme using a specific data page instead of the DPPs and optionally switch to ESFR space EXTP EXTPR Override the DPP addressing scheme using a specific segment instead of the DPPs and optionally switch to ESFR space EXTS EXTSR Note The ATOMIC and EXT instructions provide support for uninterruptable code sequences e g for semaphore operations They also support data addressing beyond the limits of the current DPPs except ATOMIC which is advantageous for bigger memory models in high level languages Hefer to Chapter 22 for examples Protected Instructions Some instructions of the C167CS which are critical for the functionality of the controller are implemented as so called Protected Instructions These protected instructions use the maximum instruction format of 32 bits for decoding while the regular instructions only use a part of it e g the lower 8 bits with the other bits providing additional information like involved registers Decoding all 32 bits of a protected doubleword instruction increases the security in cases of data distortion during instruction fetching Critical operation
299. ed technologies Derivatives Clock Generation 6 2 Frequency Control The CPU clock is generated from the oscillator clock in either of two software selectable ways The basic clock is the standard operating clock for the C167CS and is required to deliver the intended maximum performance The clock configuration in register RPOH bitfield CLKCFG RPOH 7 5 determines one of three possible basic clock generation modes Direct Drive the oscillator clock is directly fed to the controller hardware Prescaler the oscillator clock is divided by 2 to achieve a 5096 duty cycle PLL the oscillator clock is multiplied by a configurable factor of F 2 1 5 5 The Slow Down clock is the oscillator clock divided by a programmable factor of 1 32 additional 2 1 divider in prescaler mode This alternate possibility runs the C167CS at a lower frequency depending on the programmed slow down factor and thus greatly reduces its power consumption Oscillator Clock fosc CPU Clock forpu MCD04458 Figure 6 4 Frequency Control Paths Note The configuration register RPOH is loaded with the logic levels present on the upper half of PORTO POH after a long hardware reset i e bitfield CLKCFG represents the logic levels on pins P0 15 13 POH 7 5 User s Manual 6 4 V2 0 2000 07 o nfineon ed technologies Derivatives Clock Generation The internal operation o
300. ed every CPU clock cycle and allow to recognize even very short external signals The C167CS also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run time so called Hardware Traps Hardware traps cause an immediate non maskable system reaction which is similar to a standard interrupt service branching to a dedicated vector table location The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register TFR Except for another higher prioritized trap service being in progress a hardware trap will interrupt any current program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts Software interrupts are supported by means of the TRAP instruction in combination with an individual trap interrupt number User s Manual 2 7 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview 2 2 The On Chip System Resources The C167CS controllers provide a number of powerful system resources designed around the CPU The combination of CPU and these resources results in the high performance of the members of this controller family Peripheral Event Controller PEC and Interrupt Control The Peripheral Event Controller allows to respond to an interrupt request with a single data transfer word or byte which only consumes one instruction cycle and does not requ
301. edded control applications a significant increase in CPU performance and peripheral functionality over conventional 8 bit controllers is required from microcontrollers for high end embedded control systems In order to achieve this high performance goal Infineon has decided to develop its family of 16 bit CMOS microcontrollers without the constraints of backward compatibility Of course the architecture of the 16 bit microcontroller family pursues successful hardware and software concepts which have been established in Infineon s popular 8 bit controller families About this Manual This manual describes the functionality of a number of 16 bit microcontrollers of the Infineon C166 Family the C167 class As these microcontrollers provide a great extent of identical functionality it makes sense to describe a superset of the provided features For this reason some sections of this manual do not refer to all the C167 derivatives that are offered e g devices without on chip program memory These sections contain respective notes wherever possible The descriptions in this manual refer to the following derivatives of the C167 class e C167CS 4RM Version with 32 KByte ROM C167CS LM Version without on chip program memory This manual is valid for the versions with on chip ROM of the mentioned derivatives as well as for the ROMless versions Of course it refers to all devices of the different available temperature ranges and packages For sim
302. edded control applications the ADC supports the following conversion modes Fixed Channel Single Conversion produces just one result from the selected channel Fixed Channel Continuous Conversion repeatedly converts the selected channel Auto Scan Single Conversion produces one result from each of a selected group of channels Auto Scan Continuous Conversion repeatedly converts the selected group of channels Wait for ADDAT Read Mode start a conversion automatically when the previous result was read Channel Injection Mode insert the conversion of a specific channel into a group conversion auto scan A set of SFRs and port pins provide access to control functions and results of the ADC Ports amp Direction Control Alternate Functions Data Registers Control Registers Interrupt Control ADDAT ADCON ADCIC P5DIDIS ADDAT2 ADEIC P1DIDIS P5 Port 5 Analog Input Port ADDAT A D Converter Result Register ANO P5 0 AN15 P5 15 ADDAT2 A D Converter Channel Injection Result Reg P5DIDIS Port 5 Digital Input Disable Register ADCON A D Converter Control Register P1L Port 1 Input Output Port Lower Part ADCIC A D Converter Interrupt Control Register AN16 P1L 0 AN23 P1L 7 End of Conversion P1DIDIS Port 1 Digital Input Disable Register ADEIC A D Converter Interrupt Control Register Overrun Error Channel Injection MCA04472 Figure 18 1 SFRs and Port Pins Associated with the A D Converter User s Manual 18 1 V2
303. efault modes refer to pins at high level i e without external pulldown devices connected Please also consider the note above User s Manual 20 13 V2 0 2000 07 o nfineon technologies C167CS Derivatives Emulation Mode Pin POL O EMU selects the Emulation Mode when latched low at the end of reset This mode is used for special emulation and testing purposes and is of minor use for standard C167CS applications so POL O should be held high Emulation mode provides access to integrated XBUS peripherals via the external bus interface pins direction reversed of the C167CS The CPU and the generic peripherals are disabled all modules connected via the XBUS are active System Reset Table 20 1 Emulation Mode Summary Pin s Function Notes Port 4 Address input The segment address lines configured at reset PORT 1 must be driven externally PORTO Data input output RD WR Control signal input ALE Unused input Hold LOW CLKOUT CPU clock output Enabled automatically RSTOUT Reset input Drive externally for an XBUS peripheral reset RSTIN Reset input Standard reset for complete device Port 6 Interrupt output Sends XBUS peripheral interrupt request e g to the emulation system Default Emulation Mode is off Note In emulation mode pin P0 15 POH 7 is inverted i e the configuration 111 would select direct drive in emulation mode E Emulation mode can only be activa
304. egister TSCON The same coding is used as in the two least significant bits of bit field T5l see Table 10 14 The maximum input frequency for the capture trigger signal at CAPIN is fcpy 8 To ensure that a transition of the capture trigger signal is correctly recognized its level should be held for at least 4 fc py cycles before it changes Up Down Input m Interrupt Clock Auxiliary Timer T5 Request Select T5CLR wd T5SC Interrupt Request CAPREL Register MCB02044B Figure 10 22 GPT2 Register CAPREL in Capture Mode When the timer T3 capture trigger is enabled CT3 1 register CAPREL captures the contents of T5 upon transitions of the selected input s These values can be used to measure T3 s input signals This is useful e g when T3 operates in incremental interface mode in order to derive dynamic information speed acceleration from the input signals User s Manual 10 34 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units When a selected transition at the selected input pin s CAPIN T3IN T3EUD is detected the contents of the auxiliary timer T5 are latched into register CAPREL and interrupt request flag CRIR is set With the same event timer T5 can be cleared to 00004 This option is controlled by bit TS5CLR in register T5CON If T5CLR 0 the contents of timer T5 are not affected by a capture If TBCLR 1 timer T
305. elect either the segmented or non segmented memory mode In non segmented memory mode SGTDIS 1 it is assumed that the code address space is restricted to 64 KBytes segment 0 and thus 16 bits are sufficient to represent all code addresses For implicit stack operations CALL or RET the CSP register is totally ignored and only the IP is saved to and restored from the stack In segmented memory mode SGTDIS 0 it is assumed that the whole address space is available for instructions For implicit stack operations CALL or RET the CSP register and the IP are saved to and restored from the stack After reset the segmented memory mode is selected Note Bit SGTDIS controls if the CSP register is pushed onto the system stack in addition to the IP register before an interrupt service routine is entered and it is repopped when the interrupt service routine is left again System Stack Size STKSZ This bitfield defines the size of the physical system stack which is located in the internal RAM of the C167CS An area of 32 512 words or all of the internal RAM may be dedicated to the system stack A so called circular stack mechanism allows to use a bigger virtual stack than this dedicated RAM area These techniques as well as the encoding of bitfield STKSZ are described in more detail in Chapter 22 User s Manual 4 15 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The Pro
306. ements the start bit the data field 8 or 9 bits LSB first including a parity bit if selected the delimiter 1 or 2 stop bits Data transmission is double buffered When the transmitter is idle the transmit data loaded into SOTBUF is immediately moved to the transmit shift register thus freeing SOTBUF for the next data to be sent This is indicated by the transmit buffer interrupt request flag SOTBIR being set SOTBUF may now be loaded with the next data while transmission of the previous one is still going on The transmit interrupt request flag SOTIR will be set before the last bit of a frame is transmitted i e before the first or the second stop bit is shifted out of the transmit shift register The transmitter output pin TXDO must be configured for alternate data output i e the respective port output latch and the direction latch must be 1 Asynchronous reception is initiated by a falling edge 1 to 0 transition on pin RXDO provided that bits SOR and SOREN are set The receive data input pin RXDO is sampled at 16 times the rate of the selected baud rate A majority decision of the 7th 8th and 9th sample determines the effective bit value This avoids erroneous results that may be caused by noise If the detected value is not a 0 when the start bit is sampled the receive circuit is reset and waits for the next 1 to O transition at pin RXDO If the start bit proves valid the receive circuit continues sampling
307. en in Chapter 22 Scope of Stack Limit Control The stack limit control realized by the register pair STKOV and STKUN detects cases where the stack pointer SP is moved outside the defined stack area either by ADD or SUB instructions or by PUSH or POP operations explicit or implicit i e CALL or RET instructions This control mechanism is not triggered i e no stack trap is generated when e the stack pointer SP is directly updated via MOV instructions e the limits of the stack area STKOV STKUN are changed so that SP is outside of the new limits User s Manual 4 29 V2 0 2000 07 d nfineon ed technologies Derivatives The Central Processing Unit CPU The Multiply Divide High Register MDH This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the high order 16 bits of the 32 bit result For long divisions the MDH register must be loaded with the high order 16 bits of the 32 bit dividend before the division is started After any division register MDH represents the 16 bit remainder uhisi High Reg SFR FEOC 06 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mdh rwh Bit Function mdh Specifies the high order 16 bits of the 32 bit multiply and divide reg MD W
308. eneral Purpose Word Reg R1 UUUU H2 CP 4 F2y CPU General Purpose Word Reg R2 UUUU R3 CP 6 F3y CPU General Purpose Word Reg R3 UUUU H4 CP 8 F4y CPU General Purpose Word Reg R4 UUUU R5 CP 10 F5y CPU General Purpose Word Reg R5 UUUU R6 CP 12 F6y CPU General Purpose Word Reg R6 UUUU H7 CP 14 F7y CPU General Purpose Word Reg R7 UUUU H8 CP 16 F8y CPU General Purpose Word Reg R8 UUUU H9 CP 18 F9y CPU General Purpose Word Reg R9 UUUU R10 CP 20 FAQ CPU General Purpose Word Reg R10 UUUU R11 CP 22 FBy CPU General Purpose Word Reg R11 UUUU H12 CP 24 FO CPU General Purpose Word Reg R12 UUUU R13 CP 26 FD CPU General Purpose Word Reg R13 VUUUU R14 CP 28 FE CPU General Purpose Word Reg R14 UUUU R15 CP 30 FFy CPU General Purpose Word Reg R15 UUUU User s Manual 23 2 V2 0 2000 07 _ d nfineon ed technologies Derivatives The Register Set The first 8 GPRs R7 RO may also be accessed bytewise Other than with SFRs writing to a GPR byte does not affect the other byte of the respective GPR The respective halves of the byte accessible registers receive special names Table 23 2 General Purpose Byte Registers Name Physical 8 bit Description Reset Address Address Value RLO CP 0 FO CPU General Purpose Byte Reg RLO UU HHO CP 1 Fiy CPU Ge
309. eon ed technologies Derivatives Parallel Ports A write operation to a port pin configured as an input causes the value to be written into the port output latch while a read operation returns the latched state of the pin itself A read modify write operation reads the value of the pin modifies it and writes it back to the output latch Writing to a pin configured as an output DPx y 1 causes the output latch and the pin to have the written value since the output buffer is enabled Reading this pin returns the value of the output latch A read modify write operation reads the value of the output latch modifies it and writes it back to the output latch thus also modifying the level at the pin 7 1 Input Threshold Control The standard inputs of the C167CS determine the status of input signals according to TTL levels In order to accept and recognize noisy signals CMOS like input thresholds can be selected instead of the standard TTL thresholds for all pins of specific ports These special thresholds are defined above the TTL thresholds and feature a defined hysteresis to prevent the inputs from toggling while the respective input signal level is near the thresholds The Port Input Control register PICON allows to select these thresholds for each byte of the indicated ports i e 8 bit ports are controlled by one bit each while 16 bit ports are controlled by two bits each PICON Port Input Control Reg SFR F1CAJ E24 Reset
310. equest flags SOCON SOREN ASCO receiver enable flag SSCTIC SSCRIC SSCTIR SSCRIR SSC transmit receive interrupt request flags SSCEIC SSCEIR SSC error interrupt request flag SSCCON SSCBSY SSC busy flag SSCCON SSCBE SSCPE SSC error flags SSCCON SSCRE SSCTE SSC error flags ADCIC ADEIC ADCIR ADEIR ADC end of conv overrun intr request flag ADCON ADST ADCRQ ADC start flag injection request flag CC311C CC16IC CC31IR CC16IR CAPCOM2 interrupt request flags CC151C CCOIC CC15IR CCOIR CAPCOM1 interrupt request flags PWMIC PWMIR PWM module interrupt request flag PWMCONO PIR3 PTRO All bits of PWMCONO PWMCON 1 PS3 PENO All bits of PWMCON 1 TFR TFR 15 14 13 Class A trap flags TFR TFR 7 3 2 1 0 Class B trap flags P2 P2 15 P2 0 All bits of Port 2 P7 P7 7 P7 0 All bits of Port 7 P8 P8 7 P8 0 All bits of Port 8 XP3IC XPOIC XP3IR XPOIC X Peripheral interrupt request flags ISNC RTCIR PLLIR Interrupt node sharing request flags Y 2 135 protected bits User s Manual 2 20 V2 0 2000 07 j e e Infineon technologies 3 C167CS Derivatives Memory Organization Memory Organization The memory space of the C167CS is configured in a Von Neumann architecture This means that code and data are accessed within the same linear address space All of the physically separated memory
311. equested Conversion in Progress standard Injected Standard Abort running conversion Complete running conversion and start requested new start requested conversion after that conversion Injected Complete running conversion Complete running conversion start requested conversion after start requested conversion after that that Bit ADCRQ will be 0 for the second conversion however User s Manual 18 12 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter 18 2 Conversion Timing Control When a conversion is started first the capacitances of the converter are loaded via the respective analog input pin to the current analog input voltage The time to load the capacitances is referred to as sample time Next the sampled voltage is converted to a digital value in successive steps which correspond to the resolution of the ADC During these phases except for the sample time the internal capacitances are repeatedly charged and discharged via pins VAnge and VaAGwp The current that has to be drawn from the sources for sampling and changing charges depends on the time that each respective step takes because the capacitors must reach their final voltage level within the given time at least with a certain approximation The maximum current however that a source can deliver depends on its internal resistance The time that the two different actions during conversion take sampling and
312. er 00004 T2IC b FF6044 BO GPT1 Timer 2 Interrupt Control Register 0000 T3 FE424 214 GPT1 Timer 3 Register 00004 T3CON b FF42 Aly GPT1 Timer 3 Control Register 0000 T3IC b FF62 Bip GPT1 Timer 3 Interrupt Control Register 0000 TA FE44 224 GPT1 Timer 4 Register 0000 TACON b FF444 A24 GPT1 Timer 4 Control Register 00004 TAIC b FF64 B2 GPT1 Timer 4 Interrupt Control Register 0000 T5 FE464 234 GPT2 Timer 5 Register 0000 T5CON b FF464 A34 GPT2 Timer 5 Control Register 0000 T5IC b FF66 B3 GPT2 Timer 5 Interrupt Control Register 0000 T6 FE48y 244 GPT2 Timer 6 Register 0000 T6CON b FF484 A44 GPT2 Timer 6 Control Register 00004 T6IC b FF68 B44 GPT2 Timer 6 Interrupt Control Register 0000 T7 FO50y E 284 CAPCOM Timer 7 Register 0000 T78CON b FF20 90 CAPCOM Timer 7 and 8 Control Register 0000 T7IC b F17Ay E BDy CAPCOM Timer 7 Interrupt Ctrl Reg 00004 T7REL F054 E 2Ay CAPCOM Timer 7 Reload Register 0000 T8 F052 E 294 CAPCOM Timer 8 Register 0000 T8IC b F17Cy E BE CAPCOM Timer 8 Interrupt Ctrl Reg 0000 T8REL F056 E 2B4 CAPCOM Timer 8 Reload Register 0000 TFR b FFAC D6 _ Trap Flag Register 0000 User s Manual 23 12 V2 0 2000 07 e nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value WDT
313. er Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1XX Reserved Do not use this combination T5R Timer 5 Run Bit 0 Timer Counter 5 stops ji Timer Counter 5 runs T5UD Timer 5 Up Down Control T5UDE Timer 5 External Up Down Enable CT3 Timer 3 Capture Trigger Enable 0 Capture trigger from pin CAPIN T Capture trigger from T3 input pins User s Manual 10 30 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Bit Function CI Register CAPREL Capture Trigger Selection depending on bit CT3 00 Capture disabled 01 Positive transition rising edge on CAPIN or any transition on T3IN 10 Negative transition falling edge on CAPIN or any transition on T3EUD 11 Any transition rising or falling edge on CAPIN or any transition on T3IN or T3EUD T5CLR Timer 5 Clear Bit 0 Timer 5 not cleared on a capture 1 Timer 5 is cleared on a capture T5SC Timer 5 Capture Mode Enable 0 Capture into register CAPREL disabled 1 Capture into register CAPREL enabled For the effects of bits T5UD and T5UDE refer to the direction table see T6 section Count Direction Control for Auxiliary Timer The count direction of the auxiliary timer can be controlled in the same way as for the core timer T6 The description and the table apply accordingly Timer T5 in Timer Mode or Gated Timer Mode When the au
314. er of prespecified channels is repeatedly sampled and converted In addition the conversion of a specific channel can be inserted injected into a running sequence without disturbing this sequence This is called Channel Injection Mode The Peripheral Event Controller PEC may be used to automatically store the conversion results into a table in memory for later evaluation without requiring the overhead of entering and exiting interrupt routines for each data transfer Real Time Clock The C167CS contains a real time clock RTC which serves for different purposes System clock to determine the current time and date even during idle mode and power down mode optionally Cyclic time based interrupt e g to provide a system time tick independent of the CPU frequency without loading the general purpose timers or to wake up regularly from idle mode 48 bit timer for long term measurements the maximum usable timespan is more than 100 years The RTC module consists of a chain of 3 divider blocks a fixed 8 1 divider the reloadable 16 bit timer T14 and the 32 bit RTC timer accessible via registers RTCH and RTCL Both timers count up User s Manual 2 15 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview General Purpose Timer GPT Unit The GPT units represent a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and
315. er part of the internal stack need not be moved by the distance of the space being flushed or filled as the stack pointer automatically wraps around to the beginning of the freed part of the stack area Note This circular stack technique is applicable for stack sizes of 32 to 512 words STKSZ 000 to 100g it does not work with option STKSZ 1115 which uses the complete internal RAM for system stack In the latter case the address transformation mechanism is deactivated When a boundary is reached the stack underflow or overflow trap is entered where the user moves a predetermined portion of the internal stack to or from the external stack The amount of data transferred is determined by the average stack space required by routines and the frequency of calls traps interrupts and returns In most cases this will be approximately one quarter to one tenth the size of the internal stack Once the transfer is complete the boundary pointers are updated to reflect the newly allocated space on the internal stack Thus the user is free to write code without concern for the internal stack limits Only the execution time required by the trap routines affects user programs The following procedure initializes the controller for usage of the circular stack mechanism Specify the size of the physical system stack area within the internal RAM bitfield STKSZ in register SYSCON Define two pointers which specify the upper and lower bou
316. ers in register BUSCONXx are used to control external accesses The range start address of such a window defines the upper address bits which are not used within the address window of the specified size see Table 9 6 For a given window size only those upper address bits of the start address are used marked R which are not implicitly used for addresses inside the window The lower bits of the start address marked x are disregarded Table 9 6 Address Window Definition Bit field RGSZ Resulting Window Size Relevant Bits R of Start Addr A12 0000 4 KByte RRRRRRRRRR RR 0001 8 KByte RRRRRRRRRR R OX 0010 16 KByte RRRRRRRRR R xX x 0011 32 KByte RRRRRRRR RX X xX 0100 64 KByte RRRRRRRRX XXX 0101 128 KByte RRR RRR RX X X X X 0110 256 KByte RRR RRRX X X X X X 0111 512 KByte R RAR RX xx x xx x 1000 1 MByte RH ROAR xX 9x xxx xx x 1001 2 MByte RH OR Ro X x x x x x X X X 1010 4 MByte HOROX xX X X X X X X X 1 0 1 1 8 MByte RH X X X X X X X X X X X 11xx Reserved User s Manual 9 26 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Address Window Arbitration The address windows that can be defined within the C167CS s address space may partly overlap each other Thus e g small areas may be cut out of bigger windows in order to effectively utilize external resources especially within segment O For each access the EBC compares the current address with all address sele
317. ervice routine but it can also be modified via software to prevent other interrupts from being acknowledged In case an interrupt level 15 has been assigned to the CPU it has the highest possible priority and thus the current CPU operation cannot be interrupted except by hardware traps or external non maskable interrupts For details please refer to Chapter 5 After reset all interrupts are globally disabled and the lowest priority ILVL 0 is assigned to the initial CPU activity The Instruction Pointer IP This register determines the 16 bit intra segment address of the currently fetched instruction within the code segment selected by the CSP register The IP register is not mapped into the C167CS s address space and thus it is not directly accessible by the programmer The IP can however be modified indirectly via the stack by means of a return instruction The IP register is implicitly updated by the CPU for branch instructions and after instruction fetch operations IP Instruction Pointer Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ip r w h Bit Function ip Specifies the intra segment offset from where the current instruction is to be fetched IP refers to the current segment lt SEGNR gt User s Manual 4 19 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The Code Segme
318. ervice routine is executed Note The TRAP instruction does not change the CPU level so software invoked trap service routines may be interrupted by higher requests Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU When IEN is cleared no new interrupt requests are accepted by the CPU Requests that already have entered the pipeline at that time will process however When IEN is set to 1 all interrupt sources which have been individually enabled by the interrupt enable bits in their associated control registers are globally enabled Note Traps are non maskable and are therefore not affected by the IEN bit User s Manual 5 11 V2 0 2000 07 T d nfineon ed technologies Derivatives Interrupt and Trap Functions 5 2 Operation of the PEC Channels The C167CS s Peripheral Event Controller PEC provides 8 PEC service channels which move a single byte or word between two locations in segment 0 data pages 3 0 This is the fastest possible interrupt response and in many cases is sufficient to service the respective peripheral request e g serial channels etc Each channel is controlled by a dedicated PEC Channel Counter Control register PECCx and a pair of pointers for source SRCPx and destination DSTPx of the data transfer The PECC registers control the action that is performed by the respective PEC channel
319. es The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value C1PCIR EF024 X CAN 1 Port Control and Interrupt Register XXXXy C1UARn EFn2y X CAN1 Upper Arbitration Reg msg n UUUU C1UGML EFO8 X CAN1 Upper Global Mask Long UUUU C1UMLM EFOC X CAN1 Upper Mask of Last Message UUUU C2BTR EE04 X CAN Bit Timing Register UUUU C2CSR EEOO X CAN Control Status Register XX014 C2GMS EE06 X CAN Global Mask Short UFUUJ C2LARn EEn4y X CAN Lower Arbitration Register msg n UUUU C2LGML EEOA X CAN2 Lower Global Mask Long UUUUJ C2LMLM EEOE X CAN2 Lower Mask of Last Message UUUU C2MCFGn EEn6y X CAN Message Configuration Register UU msg n C2MCRn EEn0y X CAN Message Ctrl Reg msg n UUUUJ C2PCIR EE02y X CAN2Port Control and Interrupt Register XXXXy C2UARn EEn2y X CAN2 Upper Arbitration Reg msg n UUUU C2UGML EE084 X CAN Upper Global Mask Long UUUUJ C2UMLM EEOC X CAN2 Upper Mask of Last Message UUUU CAPREL FE4A 254 GPT2 Capture Reload Register 0000 CCO FE80 40 CAPCOM Register 0 00004 CCOIC b FF78y BC CAPCOM Register 0 Interrupt Ctrl Reg 00004 CC1 FE82 414 CAPCOM Register 1 0000 CC10 FE94 4A CAPCOM Register 10 00004 CC10IC b FF8C C6 CAPCOM Register 10 Interrupt Ctrl Reg 0000 CC11 FE96 4B
320. es The General Purpose Timer Units Timer 3 in Counter Mode Counter mode for the core timer T3 is selected by setting bit field T3M in register T2CON to 001g In counter mode timer T3 is clocked by a transition at the external input pin TSIN The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T3l in control register T3CON selects the triggering transition see Table 10 5 Edge Select Interrupt Request MCB02030 T3IN P3 6 T3EUD P3 4 T3OUT P3 3 x23 Figure 10 5 Block Diagram of Core Timer T3 in Counter Mode Table 10 5 GPT1 Core Timer T3 Counter Mode Input Edge Selection TSI Triggering Edge for Counter Increment Decrement 000 None Counter T3 is disabled 0 0 1 Positive transition rising edge on T3IN 010 Negative transition falling edge on T3IN 0 1 1 Any transition rising or falling edge on T3IN 1XX Reserved Do not use this combination For counter operation pin T3IN must be configured as input i e the respective direction control bit DPx y must be 0 The maximum input frequency which is allowed in counter mode is fcpy 16 To ensure that a transition of the count input signal which is applied to TSIN is correctly recognized its level should be held high or low for at least 8 fcpy cycles before it changes User s Manual 10 8 V2 0 2000 07 o
321. es Several bus masters can therefore use the same set of resources resulting in compact though powerful systems Note Sharing external resources is useful if these resources are used to a limited amount only The performance of a bus master which relies on these external resources to a great extent e g external code will be reduced by the bandwidth used by the other masters Bus arbitration uses three control signals HOLD HLDA BGR BREQ and can be enabled and disabled via software PSW HLDEN e g in order to protect time critical code sections from being suspended by other bus masters A bus arbiter logic can be designed to determine which of the bus masters controls the external system at a given time Using the specific master and slave modes for bus arbitration saves external glue logic bus arbiter when connecting two devices of the C166 Family Note Bus arbitration does not work if there is no clock signal for the EBC i e during Idle mode and Powerdown mode Signals and Control The upper three pins of Port 6 are used for the bus arbitration interface Table 9 8 summarizes the functions of these interface lines The external bus arbitration is enabled by setting bit HLDEN in register PSW to 1 In this case the three bus arbitration pins HOLD HLDA and BREQ are automatically controlled by the EBC independent of their IO configuration Bit HLDEN may be cleared during the execution of program sequences where t
322. ese options are selected by bits T6UD and T6UDE in control register TEeCON When the up down control is done by software bit T6UDE 0 the count direction can be altered by setting or clearing bit T6 UD When T6UDE 1 pin T6EUD is selected to be the controlling source of the count direction However bit T6UD can still be used to reverse the actual count direction as shown in Table 10 9 If TUD 0 and pin T6EUD shows a low level the timer is counting up With a high level at T6EUD the timer is counting down If TeUD 1 a high level at pin T6EUD specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not Table 10 9 GPT2 Core Timer T6 Count Direction Control Pin TXEUD Bit TXUDE Bit TxUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T6 and for auxiliary timer T5 Therefore the pins and bits are named Tx User s Manual 10 25 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer 6 Output Toggle Latch An overflow or underflow of timer T6 will clock the toggle bit TGOTL in control register T6CON T6OTL can also be set or reset by software Bit T6OE Alternate Output Function Enable in register T6CON enables the sta
323. espective CAPCOM unit In the timing example for this compare mode below the compare values in registers CCx and CCz are not modified Note The pins CCzIO which do not serve for double register compare mode may be used for general purpose IO Contents of Ty FFFF Compare Value CCz Compare Value CCx Reload Value lt TyREL gt 0000 Interrupt Requests i i TyIR CCxIR COxIR TyIR CCxIR CCxIR TyIR State of CCxlO 1 0 time 23 16 7 0 0 1 7 8 31 24 15 8 MCB02023 N lt XxX ou og Figure 16 11 Timing Example for Double Register Compare Mode User s Manual 16 21 V2 0 2000 07 o nfineon e technologies Derivatives The Capture Compare Units 16 6 Capture Compare Interrupts Upon a capture or compare event the interrupt request flag CCxIR for the respective capture compare register CCx is set to 1 This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the interrupt enable bit CCxIE Capture interrupts can be regarded as external interrupt requests with the additional feature of recording the time at which the triggering event occurred see also Section 5 8 Each of the 32 capture compare registers has its own bitaddressable interrupt control register CCOIC CC31IC and its own interrupt vector CCOINT CC31INT These registers are organized the same way as all other interrupt control registers
324. ess on those pins that are selected as segment address lines otherwise the output pins of Port 4 represent the port latch data During Sleep mode the oscillator except for RTC operation and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off During Power Down mode the oscillator except for RTC operation and the clocks to the CPU and to the peripherals are turned off Like in Idle mode all port pins which are configured as general purpose output pins output the last data value which was written to their port output latches When the alternate output function of a port pin is used by a peripheral the state of this pin is determined by the last action of the peripheral before the clocks were switched off Note All pin drivers can be switched off by selecting the general port disable function prior to entering Power Down mode When the supply voltage is lowered in Power Down mode the high voltage of output pins will decrease accordingly User s Manual 21 8 V2 0 2000 07 o nfineon technologies C167CS Derivatives Power Management
325. even parity bit will be set if the modulo 2 sum of the 7 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 8 bit data mode The parity error flag User s Manual 11 5 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 7 1st 2nd Stop Stop Bit Bit MCT04377 Figure 11 3 Asynchronous 8 bit Data Frames 9 bit data frames either consist of 9 data bits D8 DO SOM 100 of 8 data bits D7 DO plus an automatically generated parity bit SOM 111 or of 8 data bits D7 DO plus wake up bit SOM 101 Parity may be odd or even depending on bit SOODD in register SOCON An even parity bit will be set if the modulo 2 sum of the 8 data bits is 1 An odd parity bit will be cleared in this case Parity checking is enabled via bit SOPEN always OFF in 9 bit data and wake up mode The parity error flag SOPE will be set along with the error interrupt request flag if a wrong parity bit is received The parity bit itself will be stored in bit SORBUF 8 In wake up mode received frames are only transferred to the receive buffer register if the 9th bit the wake up bit is 1 If this bit is 0 no receive
326. event or the timer overflow in compare mode 3 directly effects the port output latch In compare mode 1 when a valid compare match occurs the state of the port output latch is read by the CAPCOM control hardware via the line Alternate Latch Data Input inverted and written back to the latch via the line Alternate Data Output The port output latch is clocked by the signal Compare Trigger which is generated by the CAPCOM unit In compare mode 3 when a match occurs the value 1 is written to the port output latch via the line Alternate Data Output When an overflow of the corresponding timer occurs a 0 is written to the port output latch In both cases the output latch is clocked by the signal Compare Trigger The direction of the pin should be set to output by the user otherwise the pin will be in the high impedance state and will not reflect the state of the output latch As can be seen from the port structure below the user software always has free access to the port pin even when it is used as a compare output This is useful for setting up the initial level of the pin when using compare mode 1 or the double register mode In these modes unlike in compare mode 3 the pin is not set to a specific value when a compare match occurs but is toggled instead When the user wants to write to the port pin at the same time a compare trigger tries to clock the output latch the write operation of the user software has priority E
327. f a 4 stage instruction pipeline a 16 bit arithmetic and logic unit ALU and dedicated SFRs Additional hardware is provided for a separate multiply and divide unit a bit mask generator and a barrel shifter Internal i I I SP RAM STKOV SKA Exec Unit Mul Div HW l Instr Ptr Bit Mask Gen General Instr Reg i Purpose 4 Stage 16 bit l ROM Pipeline Registers l P Barrel Shifter 9 l PSW l SYSCON Context Ptr l BUSCON 0 BUSCON 1 ADDRSEL 1 BUSCON 2 ADDRSEL 2 l BUSCON 3 ADDRSEL 3 i BUSCON 4 ADDRSEL 4 I Data Page Ptr Code Seg Ptr I numm MCB02147 Figure 2 2 CPU Block Diagram To meet the demand for greater performance and flexibility a number of areas has been optimized in the processor core Functional blocks in the CPU core are controlled by signals from the instruction decode logic These are summarized below and described in detail in the following sections 1 High Instruction Bandwidth Fast Execution 2 High Function 8 bit and 16 bit Arithmetic and Logic Unit 3 Extended Bit Processing and Peripheral Control 4 High Performance Branch Call and Loop Processing 5 Consistent and Optimized Instruction Formats 6 Programmable Multiple Priority Interrupt Structure User s Manual 2 2 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview 2 1 1 High Instruction Bandwidth Fast Execution Based on the hardware
328. f the C167CS is controlled by the internal CPU clock fcopy Both edges of the CPU clock can trigger internal e g pipeline or external e g bus cycles operations see Figure 6 5 Phase Locked Loop Operation fosc foL foL Joru Direct Clock Drive foL fo foru Prescaler Operation foL fc Jopu SDD Operation foL foL Joru CLKREL 2 Direct Drive foL fc Jopu CLKREL 2 Prescaler MCD04459 Figure 6 5 Generation Mechanisms for the CPU Clock User s Manual 6 5 V2 0 2000 07 o nfineon ed technologies Derivatives Clock Generation Direct Drive When direct drive is configured CLKCFG 011g the C167CS s clock system is directly fed from the external clock input i e fcpy fosc This allows operation of the C167CS with a reasonably small fundamental mode crystal The specified minimum values for the CPU clock phases TCLs must be respected Therefore the maximum input clock frequency depends on the clock signal s duty cycle Prescaler Operation When prescaler operation is configured CLKCFG 001g the C167CS s input clock is divided by 2 to generate then CPU clock signal i e fepy fosc 2 This requires the oscillator or input clock to run on 2 times the intended operating frequency but guarantees a 50 duty cycle for the internal clock system independent of the input clock signal s waveform PLL Operation When PLL operation is configured via CLKCF
329. fered with a shadow register The CPU accesses the PWx register while the hardware compares the contents of the shadow register with the contents of the associated counter PTx The shadow register is loaded from the respective PWx register at the beginning of every new PWM cycle or upon a write access to PWx while the timer is stopped Table 17 2 PWM Module Channel Specific Register Addresses Register Address Register Space Register Address Register Space PWO FE30 18 SFR PTO F030 18 ESFR PW1 FE32 19 SFR PT1 F032 19 ESFR PW2 FE3A 1A SFR PT2 F034 1A ESFR PW3 FE36 1B SFR PT3 F036 1B ESFR PPO F038 1C ESFR PP1 FOSA 1D ESFR Note These registers are not PP2 FO3CUE ESFR bitaddressable PP3 FOSE 1Fy ESFR When the counter value is greater than or equal to the shadow register value the PWM signal is set otherwise it is reset The output of the comparators may be described by the boolean formula PWM output signal PTx 2 PWx shadow latch This type of comparison allows a flexible control of the PWM signal User s Manual 17 11 V2 0 2000 07 o nfineon es technologies Derivatives The Pulse Width Modulation Module PWM Control Register PWMCONO Register PWMCONO controls the function of the timers of the four PWM channels and the channel specific interrupts Having the control bits organized in functional groups allows e g to start or stop all
330. for input DPx y 0 if an external device is driving the pin The input direction is the default after reset If no external device is connected to the pin however one can also set the direction for this pin to output In this case the pin reflects the state of the port output latch Thus the alternate input function reads the value stored in the port output latch This can be used for testing purposes to allow a software trigger of an alternate input function by writing to the port output latch On most of the port lines the user software is responsible for setting the proper direction when using an alternate input or output function of a pin This is done by setting or clearing the direction control bit DPx y of the pin before enabling the alternate function There are port lines however where the direction of the port line is switched automatically For instance in the multiplexed external bus modes of PORTO the direction must be switched several times for an instruction fetch in order to output the addresses and to input the data Obviously this cannot be done through instructions In these cases the direction of the port line is switched automatically by hardware if the alternate function of such a pin is enabled To determine the appropriate level of the port output latches check how the alternate data output is combined with the respective port latch output There is one basic structure for all port lines with only an alternate
331. for one of the two registers in a register pair CCx or CCz the associated interrupt request flag CCxIR or CCzIR is set to 1 and pin CCxlO corresponding to bank 1 register CCx is toggled The generated interrupt always corresponds to the register that caused the match Note If a match occurs simultaneously for both register CCx and register CCz of the register pair pin CCxlO will be toggled only once but two separate compare interrupt requests will be generated one for vector CCxINT and one for vector CCZINT In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in double register compare mode this port pin must be configured as output i e the corresponding direction control bit must be set to 1 With this configuration the output pin has the same characteristics as in compare mode 1 gt Interrupt Request Mode 1 CCMODx Port a 1 CCxIO B Toggle Mode 0 CCMODz Input Clock Interrupt Request X 23 16 7 0 y 0 1 7 8 z 31 24 15 8 MCB02022 Figure 16 10 Double Register Compare Mode Block Diagram User s Manual 16 20 V2 0 2000 07 o nfineon e technologies Derivatives The Capture Compare Units In this configuration example the same timer allocation was chosen for both compare registers but each register may also be individually allocated to one of the two timers of the r
332. for the word data type or 801 for the byte data type the E flag is set to 1 otherwise it is cleared MULIP Flag The MULIP flag will be set to 1 by hardware upon the entrance into an interrupt service routine when a multiply or divide ALU operation was interrupted before completion Depending on the state of the MULIP bit the hardware decides whether a multiplication or division must be continued or not after the end of an interrupt service The MULIP bit is overwritten with the contents of the stacked MULIP flag when the return from interrupt instruction RETI is executed This normally means that the MULIP flag is cleared again after that User s Manual 4 18 V2 0 2000 07 o nfineon e technologies Derivatives The Central Processing Unit CPU Note The MULIP flag is a part of the task environment When the interrupting service routine does not return to the interrupted multiply divide instruction i e in case of a task scheduler that switches between independent tasks the MULIP flag must be saved as part of the task environment and must be updated accordingly for the new task before this task is entered CPU Interrupt Status IEN ILVL The Interrupt Enable bit allows to globally enable IEN 1 or disable IEN 0 interrupts The four bit Interrupt Level field ILVL specifies the priority of the current CPU activity The interrupt level is updated by hardware upon entry into an interrupt s
333. formed the CPU write operation has priority and the increment or reload is disabled to guarantee correct timer operation Timer Mode The bits TxM in SFRs TO1CON and T78CON select between timer or counter mode for the respective timer In timer mode TxM 0 the input clock for a timer is derived from the internal CPU clock divided by a programmable prescaler The different options for the prescaler are selected separately for each timer by the bit fields Txl The input frequencies fr for Tx are determined as a function of the CPU clock as follows where Txl represents the contents of the bit field Txl fopu o Txl 3 Fx 7 When a timer overflows from FFFFy to 0000 it is reloaded with the value stored in its respective reload register TxREL The reload value determines the period Pr between two consecutive overflows of Tx as follows 218 lt TxRELs x 2 Txl 3 P m cPU After a timer has been started by setting its run flag TxR to 1 the first increment will occur within the time interval which is defined by the selected timer resolution All further increments occur exactly after the time defined by the timer resolution When both timers of a CAPCOM unit are to be incremented or reloaded at the same time TO is always serviced one CPU clock before T1 T7 before T8 respectively The timer input frequencies resolution and periods which result from the selected prescaler option in Txl when usi
334. g External Resources Using Slave Mode Slave Mode is selected by intentionally switching pin BREQ to output DP6 7 1 Normally the port direction register bits for the arbitration interface pins retain their reset value which is 0 Clearing bit DP6 7 or preserving the reset value selects Master Mode where the device operates compatible with earlier versions without the slave mode feature Note If the C167CS operates in slave mode and executes a loop out of external memory which fits completely into the jump cache e g JB bitadar its BREQ output may toggle period 2 CPU clock cycles BREQ is activated by the prefetcher that wants to read the next sequential intstruction BREQ is the deactivated because the target of the taken jump is found in the jump cache A loop of a minimum length of 3 words avoids this User s Manual 9 36 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 8 The XBUS Interface The C167CS provides an on chip interface the XBUS interface via which integrated customer application specific peripherals can be connected to the standard controller core The XBUS is an internal representation of the external bus interface i e it is operated in the same way For each peripheral on the XBUS X Peripheral there is a separate address window controlled by a register pair XBCONX XADRSx similar to registers BUSCONx and ADDRSELx As an interface to a per
335. g instruction to decode operands for unimplemented opcodes based on the stacked IP In order to resume processing the stacked IP value must be incremented by the size of the undefined instruction which is determined by the user before a RETI instruction is executed User s Manual 5 34 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions Protection Fault Trap Whenever one of the special protected instructions is executed where the opcode of that instruction is not repeated twice in the second word of the instruction and the byte following the opcode is not the complement of the opcode the PRTFLT flag in register TFR is set and the CPU enters the protection fault trap routine The protected instructions include DISWDT EINIT IDLE PWRDN SRST and SRVWDT The IP value pushed onto the system stack for the protection fault trap is the address of the instruction that caused the trap Illegal Word Operand Access Trap Whenever a word operand read or write access is attempted to an odd byte address the ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap routine The IP value pushed onto the system stack is the address of the instruction following the one which caused the trap Illegal Instruction Access Trap Whenever a branch is made to an odd byte address the ILLINA flag in register TFR is set and the CPU enters the illegal instruction access trap routine The IP
336. g with 16 bit mem addresses must guarantee that the used data page pointer DPPO DPP3 selects data page 3 Accesses via the Peripheral Event Controller PEC use the SRCPx and DSTPx pointers instead of the data page pointers Short 8 bit reg addresses to the standard SFR area do not use the data page pointers but directly access the registers within this 512 Byte area Short 8 bit reg addresses to the extended ESFR area require switching to the 512 Byte extended SFR area This is done via the EXTension instructions EXTR EXTP R EXTS R Byte Write Operations to word wide SFRs via indirect or direct 16 bit mem addressing or byte transfers via the PEC force zeros in the non addressed byte Byte write operations via short 8 bit reg addressing can only access the low byte of an SFR and force zeros in the high byte It is therefore recommended to use the bit field instructions BFLDL and BFLDH to write to any number of bits in either byte of an SFR without disturbing the non addressed byte and the unselected bits Reserved Bits Some of the bits which are contained in the C167CS s SFRs are marked as Reserved User software should never write 1 s to reserved bits These bits are currently not implemented and may be used in future products to invoke new functions In this case the active state for these functions will be 1 and the inactive state will be 0 Therefore writing only 0 s to reserved location
337. ge and form a contiguous address space Power Down Mode If the C167CS enters Power Down mode the XCLK signal will be turned off which will stop the operation of the CAN module Any message transfer is interrupted In order to ensure that the CAN controller is not stopped while sending a dominant level 0 on the CAN bus the CPU should set bit INIT in the Control Register prior to entering Power Down mode The CPU can check if a transmission is in progress by reading bits TXRQ and NEWDAT in the message objects and bit TXOK in the Control Register After returning from Power Down mode via hardware reset the CAN module has to be reconfigured Disabling the CAN Modules When the CAN module is disabled by setting bit CANDISx in register SYSCON3 peripheral management no register accesses are possible Also the module s logic blocks are stopped and no CAN bus transfers are possible After re enabling the CAN module CANDISx 0 it must be reconfigured as after returning from Power Down mode User s Manual 19 31 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Note Incoming message frames can still be recognized not received in this case by monitoring the receive line CANx RXD For this purpose the receive line CANx RXD can be connected to a fast external interrupt via register EXISEL CAN Module Reset The on chip CAN module is connected to the XBUS Reset signal This signal is act
338. ge on any T3 input T3IN or T3EUD 1XX Reserved Do not use this combination User s Manual 10 9 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units The incremental encoder can be connected directly to the C167CS without external interface logic In a standard system however comparators will be employed to convert the encoder s differential outputs e g A A to digital signals e g A This greatly increases noise immunity Note The third encoder output TopO which indicates the mechanical zero position may be connected to an external interrupt input and trigger a reset of timer T3 e g via PEC transfer from ZEROS Signal Encoder Conditioning C167CR TSInput TSInput Interrupt MCS04372 Figure 10 7 Connection of the Encoder to the C167CS For incremental interface operation the following conditions must be met Bitfield T3M must be 110p Both pins T3IN and T3EUD must be configured as input i e the respective direction control bits must be 0 Bit T3UDE must be 1 to enable automatic direction control The maximum counting frequency which is allowed in incremental interface mode is fcpu 16 To ensure that a transition of any input signal is correctly recognized its level should be held high or low for at least 8 fcpy cycles before it changes As in Incremental Interface Mode two input signals with a 90 phase shift are evaluated thei
339. ge Pointers User s Manual 4 24 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The Context Pointer CP This non bit addressable register is used to select the current register context This means that the CP register value determines the address of the first General Purpose Register GPR within the current register bank of up to 16 wordwide and or bytewide GPRs e Pointer SFR FE10 08 Reset Value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 cp 0 r r r r rw r Bit Function cp Modifiable portion of register CP Specifies the word base address of the current register bank When writing a value to register CP with bits CP 11 CP 9 000 bits CP 11 CP 10 are set to 11 by hardware in all other cases all bits of bit field cp receive the written value Note It is the user s responsibility that the physical GPR address specified via CP register plus short GPR address must always be an internal RAM location If this condition is not met unexpected results may occur Do not set CP below the IRAM start address i e 00 FA00 00 F600 00 F2004 referring to an IRAM size of 1 2 3 KByte Do not set CP above 00 FDFE e Be careful using the upper GPRs with CP above 00 FDEO The CP register can be updated via any instruction which is capable of modifying an SFR Note Due to the
340. gh level languages User s Manual 2 5 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview Consistent and Optimized Instruction Formats To obtain optimum performance in a pipelined design an instruction set has been designed which incorporates concepts from Reduced Instruction Set Computing RISC These concepts primarily allow fast decoding of the instructions and operands while reducing pipeline holds These concepts however do not preclude the use of complex instructions which are required by microcontroller users The following goals were used to design the instruction set 1 Provide powerful instructions to perform operations which currently require sequences of instructions and are frequently used Avoid transfer into and out of temporary registers such as accumulators and carry bits Perform tasks in parallel such as saving state upon entry into interrupt routines or subroutines Avoid complex encoding schemes by placing operands in consistent fields for each instruction Also avoid complex addressing modes which are not frequently used This decreases the instruction decode time while also simplifying the development of compilers and assemblers Provide most frequently used instructions with one word instruction formats All other instructions are placed into two word formats This allows all instructions to be placed on word boundaries which alleviates the need for complex align
341. gies Derivatives Table of Contents Page 23 2 CPU General Purpose Registers GPRS luus 23 2 23 3 Special Function Registers Ordered by Name 23 4 23 4 Special Function Registers Ordered by Address 23 14 23 5 Special Notes 2 00 20 aa amagi aeai ald aaa d soaker dene R eae dire 23 24 24 Instruction Set Summary anaa aaa aana 24 1 25 Device Specification anaa aaaea 25 1 26 Keyword IndeX snuaaaaa aae 26 1 User s Manual l 5 V2 0 2000 07 o nfineon ed technologies Derivatives Introduction 1 Introduction The rapidly growing area of embedded control applications is representing one of the most time critical operating environments for today s microcontrollers Complex control algorithms have to be processed based on a large number of digital as well as analog input signals and the appropriate output signals must be generated within a defined maximum response time Embedded control applications also are often sensitive to board space power consumption and overall system cost Embedded control applications therefore require microcontrollers which offer a high level of system integration eliminate the need for additional peripheral devices and the associated software overhead provide system security and fail safe mechanisms provide effective means to control and reduce the device s power consumption With the increasing complexity of emb
342. gister bank ADD SP 10D Release the 5 words of the current system stack User s Manual 22 11 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 4 Table Searching A number of features have been included to decrease the execution time required to search tables First branch delays are eliminated by the branch target cache after the first iteration of the loop Second in non sequentially searched tables the enhanced performance of the ALU allows more complicated hash algorithms to be processed to obtain better table distribution For sequentially searched tables the auto increment indirect addressing mode and the E end of table flag stored in the PSW decrease the number of overhead instructions executed in the loop The two examples below illustrate searching ordered tables and non ordered tables respectively MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc SGT LOOP Test whether target has not been found Note The last entry in the table must be greater than the largest possible target MOV RO BASE Move table base into RO LOOP CMP R1 RO Compare target to table entry JMPR cc NET LOOP Test whether target is not found AND P the end of table has not been reached Note The last entry in the table must be equal to the lowest signed integer 8000p 22 5 Floating Point Support All floating point operations are perfo
343. h algorithm has been incorporated to allow four bits to be multiplied and two bits to be divided per machine cycle Thus these operations use two coupled 16 bit registers MDL and MDH and require four and nine machine cycles respectively to perform a 16 bit by 16 bit or 32 bit by 16 bit calculation plus one machine cycle to setup and adjust the operands and the result Even these longer multiply and divide instructions can be interrupted during their execution to allow for very fast interrupt response Instructions have also been provided to allow byte packing in memory while providing sign extension of bytes for word wide arithmetic operations The internal bus structure also allows transfers of bytes or words to or from peripherals based on the peripheral requirements A set of consistent flags is automatically updated in the PSW after each arithmetic logical shift or movement operation These flags allow branching on specific conditions Support for both signed and unsigned arithmetic is provided through user specifiable branch tests These flags are also preserved automatically by the CPU upon entry into an interrupt or trap routine All targets for branch calculations are also computed in the central ALU A 16 bit barrel shifter provides multiple bit shifts in a single cycle Rotates and arithmetic shifts are also supported Extended Bit Processing and Peripheral Control A large number of instructions has been dedicated to bit process
344. hannel 28 P7 5 CC29lO Capture input compare output channel 29 P7 6 CC30lO Capture input compare output channel 30 P7 7 CC311O Capture input compare output channel 31 User s Manual 7 49 V2 0 2000 07 o nfineon technologies C167CS Derivatives Parallel Ports Port 7 P7 7 P7 6 P7 5 P7 4 P7 3 P7 2 P7 1 P7 0 General Purpose Input Output CC3110 CC30I0 CC2910 CC28lO POUTS POUT2 POUT1 POUTO Alternate Function MCA04362 Figure 7 25 Port 7 IO and Alternate Functions The port structures of Port 7 differ in the way the output latches are connected to the internal bus and to the pin driver see Figure 7 26 and Figure 7 27 Pins P7 3 0 POUTS POUTO of Port 7 XOR the alternate data output with the port latch output which allows to use the alternate data directly or inverted at the pin driver User s Manual 7 50 V2 0 2000 07 o Infineon technologies C167CS Derivatives Parallel Ports Internal Bus gt Port Output Open Drain Latch Latch Pin AltDataOut XOR Dfe Xj Driver Clock Input Latch MCB04363 P7 3 0 Figure 7 26 Block Diagram of Port 7 Pins P7 3 0 User s Manual 7 51 V2 0 2000 07 o Infineon iis technologies Derivatives Parallel Ports Pins P7 7 4 of Port 7 combine internal bus data and alternate data output before the port latch input as do the Port 2 pins Internal Bus
345. hannel ASCO is controlled by its bitaddressable control register SOCON This register contains control bits for mode and error check selection and status flags for error identification SOCON ASCO Control Register SFR FFBO D8 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 soR 90 S0 So _ SO SO SO SO SO SO SO SO SOM LB BRS ODD OE FE PE OEN FEN PEN REN STP w w w mw wh wh wh rw rw rw wh rw rw Bit Function SOM ASCO Mode Control 000 8 bit data synchronous operation 001 8 bit data async operation 010 Reserved Do not use this combination 011 7 bit data parity async operation 100 9 bit data async operation 101 8 bit data wake up bit async operation 110 Reserved Do not use this combination 111 8 bit data parity async operation SOSTP Number of Stop Bits Selection async operation 0 One stop bit 1G Two stop bits SOREN Receiver Enable Bit 0 Receiver disabled 1 Receiver enabled Reset by hardware after reception of byte in synchronous mode SOPEN Parity Check Enable Bit async operation 0 Ignore parity 1G Check parity SOFEN Framing Check Enable Bit async operation 0 Ignore framing errors E Check framing errors SOOEN Overrun Check Enable Bit 0 Ignore overrun errors 1 Check overrun errors User s Manual 11 2 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchron
346. have been made programmable to allow the user the adaption of a wide range of different types of memories and or peripherals Access to very slow memories or peripherals is supported via a particular Ready function For applications which require less than 64 KBytes of address space a non segmented memory model can be selected where all locations can be addressed by 16 bits and thus Port 4 is not needed as an output for the upper address bits Axx A16 as is the case when using the segmented memory model The on chip XBUS is an internal representation of the external bus and allows to access integrated application specific peripherals modules in the same way as external components It provides a defined interface for these customized peripherals The on chip XRAM and the on chip CAN Modules are examples for these X Peripherals User s Manual 2 10 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview 2 3 The On Chip Peripheral Blocks The C166 Family clearly separates peripherals from the core This structure permits the maximum number of operations to be performed in parallel and allows peripherals to be added or deleted from family members without modifications to the core Each functional block processes data independently and communicates information over common buses Peripherals are controlled by data written to the respective Special Function Registers SFRs These SFRs are located either within
347. he external resources are required but cannot be shared with other bus masters or during sequences which need to access on chip XBUS resources but which shall not be interrupted by hold states In this case the C167CS will not answer to HOLD requests from other external masters If HLDEN is cleared while the C167CS is in Hold State code execution from internal RAM ROM this Hold State is left only after HOLD has been deactivated again l e in this case the current Hold State continues and only the next HOLD request is not answered Note The pins HOLD HLDA and BREQ keep their alternate function bus arbitration even after the arbitration mechanism has been switched off by clearing HLDEN All three pins are used for bus arbitration after bit HLDEN was set once User s Manual 9 31 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Table 9 8 Interface Pins for Bus Arbitration Pin Function Direction Operational Description P6 5 HOLD INput The hold request signal requests the external bus system from the C167CS P6 6 HLDA OUTput The hold acknowledge signal acknowledges a hold Master request and indicates to the external partners that the mode C167CS has withdrawn from the bus and another external bus master may now use it BGR INput The bus grant signal indicates to the C167CS slave that Slave the master has withdrawn from the external bus in mode resp
348. he MSB of bit field MCTC selects the READY operation MCTC 3 0 Synchronous READY i e the READY signal must meet setup and hold times MCTC 3 1 Asynchronous READY i e the READY signal is synchronized internally User s Manual 9 18 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface The Synchronous READY provides the fastest bus cycles but requires setup and hold times to be met The CLKOUT signal should be enabled and may be used by the peripheral logic to control the READY timing in this case The Asynchronous READY is less restrictive but requires additional waitstates caused by the internal synchronization As the asynchronous READY is sampled earlier see Figure 9 10 programmed waitstates may be necessary to provide proper bus cycles see also notes on normally ready peripherals below A READY signal especially asynchronous READY that has been activated by an external device may be deactivated in response to the trailing rising edge of the respective command RD or WR Note When the READY function is enabled for a specific address window each bus cycle within this window must be terminated with an active READY signal Otherwise the controller hangs until the next reset A timeout function is only provided by the watchdog timer Combining the READY function with predefined waitstates is advantageous in two cases Memory components with a
349. he intra segment addr as long as at least one of the BUSCON registers selects a demultiplexed external bus even for multiplexed bus cycles Not all addr windows defined via registers ADDRSELx may overlap each other The operation of the EBC will be unpredictable in such a case See Address Window Arbitration on Page 9 27 The addr windows defined via registers ADDRSELx may overlap internal addr areas Internal accesses will be executed in this case For any access to an internal addr area the EBC will remain inactive see Chapter 9 6 User s Manual 9 29 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 6 EBC Idle State When the external bus interface is enabled but no external access is currently executed the EBC is idle As long as only internal resources from an architecture point of view like IRAM GPRs or SFRs etc are used the external bus interface does not change see Table 9 7 Accesses to on chip X Peripherals are also controlled by the EBC However even though an X Peripheral appears like an external peripheral to the controller the respective accesses do not generate valid external bus cycles Due to timing constraints address and write data of an XBUS cycle are reflected on the external bus interface see Table 9 7 The address mentioned above includes PORT1 Port 4 BHE and ALE which also pulses for an XBUS cycle The external CS signals on Port 6 are driven inactive
350. he output toggle latch T3OTL is accessible via software and may be changed if required to modify the PWM signal However this will NOT trigger the reloading of T3 User s Manual 10 18 V2 0 2000 07 e nfineon ed technologies Derivatives The General Purpose Timer Units Reload Register T2 Interrupt Request T2l Input Code Core Timer T3 rsour T30E Up Down Interrupt Request i Interrupt Request Reload Register T4 T4l Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL MCB02037 Figure 10 13 GPT1 Timer Reload Configuration for PWM Generation Note Although it is possible it should be avoided to select the same reload trigger event for both auxiliary timers In this case both reload registers would try to load the core timer at the same time If this combination is selected T2 is disregarded and the contents of T4 is reloaded User s Manual 10 19 V2 0 2000 07 d nfineon e technologies Derivatives The General Purpose Timer Units Auxiliary Timer in Capture Mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 101p In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer s external input pin TxIN The capture
351. he pin is read inverted and then written back to the output latch Compare mode 1 allows several compare events within a single timer period An overflow of the allocated timer has no effect on the output pin nor does it disable or enable further compare events In order to use the respective port pin as compare signal output pin CCxlO for compare register CCx in compare mode 1 this port pin must be configured as output i e the corresponding direction control bit must be set to 1 With this configuration the initial state of the output signal can be programmed or its state can be modified at any time by writing to the port output latch In compare mode 1 the port latch is toggled upon each compare event see Figure 16 7 If compare mode 1 is programmed for one of the registers CCO CC7 or CC16 CC23 the double register compare mode becomes enabled for this register if the corresponding bank 2 register is programmed to compare mode 0 see Double Register Compare Mode on Page 16 19 Note If the port output latch is written to by software at the same time it would be altered by a compare event the software write will have priority In this case the hardware triggered change will not become effective Compare Mode 2 Compare mode 2 is an interrupt only mode similar to compare mode 0 but only one interrupt request per timer period will be generated Compare mode 2 is selected for register CCx by setting bit field CCMOD
352. he ports to input if necessary Of course the required software in this case must be executed from internal memory User s Manual 21 7 V2 0 2000 07 o nfineon e technologies Derivatives Power Management 21 3 1 Status of Output Pins During Power Reduction Modes During Idle mode the CPU clocks are turned off while all peripherals continue their operation in the normal way Therefore all ports pins which are configured as general purpose output pins output the last data value which was written to their port output latches If the alternate output function of a port pin is used by a peripheral the state of the pin is determined by the operation of the peripheral Port pins which are used for bus control functions go into that state which represents the inactive state of the respective function e g WR or to a defined state which is based on the last bus access e g BHE Port pins which are used as external address data bus hold the address data which was output during the last external memory access before entry into Idle mode under the following conditions POH outputs the high byte of the last address if a multiplexed bus mode with 8 bit data bus is used otherwise POH is floating POL is always floating in Idle mode PORT outputs the lower 16 bits of the last address if a demultiplexed bus mode is used otherwise the output pins of PORT1 represent the port latch data Port 4 outputs the segment address for the last acc
353. he use of the RETI return from interrupt instruction to exit from the called routine This instruction restores the system state from the system stack and then branches back to the location where the trap or interrupt occurred User s Manual 22 13 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 8 Unseparable Instruction Sequences The instructions of the C167CS are very efficient most instructions execute in one machine cycle and even the multiplication and division are interruptable in order to minimize the response latency to interrupt requests internal and external In many microcontroller applications this is vital Some special occasions however require certain code sequences e g semaphore handling to be uninterruptable to function properly This can be provided by inhibiting interrupts during the respective code sequence by disabling and enabling them before and after the sequence The necessary overhead may be reduced by means of the ATOMIC instruction which allows locking 1 4 instructions to an unseparable code sequence during which the interrupt system standard interrupts and PEC requests and Class A Traps NMI stack overflow underflow are disabled A Class B Trap illegal opcode illegal bus access etc however will interrupt the atomic sequence since it indicates a severe hardware problem The interrupt inhibit caused by an ATOMIC instruction gets active immediately i e n
354. hen the interrupt system is globally enabled IEN 1 and a PEC service on a priority level higher than the current CPU level is requested and executed Note An interrupt request which is individually enabled and assigned to priority level O will terminate Idle mode The associated interrupt vector will not be accessed however The watchdog timer may be used to monitor the Idle mode an internal reset will be generated if no interrupt or NMI request occurs before the watchdog timer overflows To prevent the watchdog timer from overflowing during Idle mode it must be programmed to a reasonable time interval before Idle mode is entered User s Manual 21 4 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management 21 2 Sleep Mode To further reduce the power consumption the microcontroller can be switched to Sleep mode Clocking of all internal blocks is stopped RTC and selected oscillator optionally the contents of the internal RAM however are preserved through the voltage supplied via the Vpp pins The watchdog timer is stopped in Sleep mode Sleep mode is selected via bitfield SLEEPCON in register SYSCON1 and is entered after the IDLE instruction has been executed and the instruction before the IDLE instruction has been completed Sleep mode is terminated by interrupt requests from any enabled interrupt source whose individual Interrupt Enable flag was set before the Idle mode was entered regardless of b
355. henever this register is updated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDH must be saved along with registers MDL and MDC to avoid erroneous results A detailed description of how to use the MDH register for programming multiply and divide algorithms can be found in Chapter 22 User s Manual 4 30 V2 0 2000 07 d nfineon ed technologies Derivatives The Central Processing Unit CPU The Multiply Divide Low Register MDL This register is a part of the 32 bit multiply divide register which is implicitly used by the CPU when it performs a multiplication or a division After a multiplication this non bit addressable register represents the low order 16 bits of the 32 bit result For long divisions the MDL register must be loaded with the low order 16 bits of the 32 bit dividend before the division is started After any division register MDL represents the 16 bit quotient anodd Low Reg SFR FEOE 07 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mdl rwh Bit Function mdl Specifies the low order 16 bits of the 32 bit multiply and divide reg MD Whenever this register is u
356. her device in the network In this case the previous master and the future master previous slave will have to toggle their operating mode SSCMS and the direction of their port pins see description above User s Manual 12 9 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 2 Half Duplex Operation In a half duplex configuration only one data line is necessary for both receiving and transmitting of data The data exchange line is connected to both pins MTSR and MRST of each device the clock line is connected to the SCLK pin The master device controls the data transfer by generating the shift clock while the slave devices receive it Due to the fact that all transmit and receive pins are connected to the one data exchange line serial data may be moved between arbitrary stations Similar to full duplex mode there are two ways to avoid collisions on the data exchange line e only the transmitting device may enable its transmit pin driver e the non transmitting devices use open drain output and only send ones Since the data inputs and outputs are connected together a transmitting device will clock in its own data at the input pin MRST for a master device MTSR for a slave By these means any corruptions on the common data exchange line are detected where the received data is not equal to the transmitted data Master Device 1 Device 2 Slave Shift Register Shift Regis
357. hich are representable by either 16 bits for word operations 8000 to 7FFF or by 8 bits for byte operations 80 to 7F otherwise the V flag is cleared Note that the result of an integer addition integer subtraction or 2 s complement is not valid if the V flag indicates an arithmetic overflow For multiplication and division the V flag is set to 1 if the result cannot be represented in a word data type otherwise it is cleared Note that a division by zero will always cause an overflow In contrast to the result of a division the result of a multiplication is valid User s Manual 4 17 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU regardless of whether the V flag is set to 1 or not Since logical ALU operations cannot produce an invalid result the V flag is cleared by these operations The V flag is also used as Sticky Bit for rotate right and shift right operations With only using the C flag a rounding error caused by a shift right operation can be estimated up to a quantity of one half of the LSB of the result In conjunction with the V flag the C flag allows evaluating the rounding error with a finer resolution see Table 4 2 For Boolean bit operations with only one operand the V flag is always cleared For Boolean bit operations with two operands the V flag represents the logical ORing of the two specified bits Table 4 2 Shift
358. hich should cause a count trigger see description of TxyCON for the possible selections Note In order to use pin TOIN or T7IN as external count input pin the respective port pin must be configured as input i e the corresponding direction control bit must be cleared DPx y 0 If the respective port pin is configured as output the associated timer may be clocked by modifying the port output latches Px y via software e g for testing purposes The maximum external input frequency to TO or T7 in counter mode is fcpy 16 To ensure that a signal transition is properly recognized at the timer input an external count input signal should be held for at least 8 CPU clock cycles before it changes its level again The incremented count value appears in SFR TO T7 within 8 CPU clock cycles after the signal transition at pin TxIN Reload A reload of a timer with the 16 bit value stored in its associated reload register in both modes is performed each time a timer would overflow from FFFF to 00004 In this case the timer does not wrap around to 0000p but rather is reloaded with the contents of the respective reload register TXREL The timer then resumes incrementing starting from the reloaded value The reload registers TxREL are not bitaddressable User s Manual 16 8 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units 16 2 CAPCOM Unit Timer Interrupts Upon a timer overflow the corresponding t
359. hip Select 9 10 20 18 default 20 20 PLL 6 7 20 19 Reset 20 7 20 12 special modes 20 16 Write Control 20 17 Context Pointer 4 25 Context Switching 5 19 Conversion analog digital 18 1 Auto Scan 18 7 timing control 18 13 Count direction 10 4 10 25 Counter 10 8 10 14 10 29 10 31 17 10 CP 4 25 CPU 2 2 4 1 CRIC 10 38 CSP 4 20 CSR 19 8 D Data Page 4 22 22 14 User s Manual Keyword Index boundaries 3 12 Default startup configuration 20 20 Delay Read Write 9 16 Demultiplexed Bus 9 5 Development Support 1 6 Direct Drive 6 6 Direction count 10 4 10 25 Disable Interrupt 5 16 Peripheral 21 14 Segmentation 4 15 Division 4 30 22 1 Double Register compare 16 19 DPOL DPOH 7 13 DP1L DP1H 7 17 DP2 7 23 DP3 7 28 DP4 7 33 7 42 7 48 DP8 7 53 DPP 4 22 22 14 Driver characteristic ports 7 5 E Early chip select 9 11 Early WR control 9 16 Edge aligned PWM 17 3 Edge characteristic ports 7 6 Emulation Mode 20 14 Enable Interrupt 5 16 Peripheral 21 14 Segmentation 4 15 XBUS peripherals 9 38 Error Detection ASCO 11 10 CAN 19 5 SSC 12 15 EXICON 5 28 EXISEL 5 29 External Bus 2 10 V2 0 2000 07 o nfineon technologies C167CS Derivatives Bus Characteristics 9 12 9 19 Bus Idle State 9 30 Bus Modes 9 3 9 8 Fast interrupts 5 28 Host Mode gt EHM 20 16 Interrupt source control 5 29 Interrupts 5 26 Interrupts during sleep mode 5 30 startup configuration 20 13 F Fast external in
360. hip mode the C167CS operates only with and out of internal resources No external bus is configured and no external peripherals and or memory can be accessed Also no port lines are occupied for the bus interface When running in single chip mode however external access may be enabled by configuring an external bus under software control Single chip mode allows the C167CS to start execution out of the internal program memory Mask ROM OTP or Flash memory Note Any attempt to access a location in the external memory space in single chip mode results in the hardware trap ILLBUS if no external bus has been explicitly enabled by software User s Manual 9 2 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 2 External Bus Modes When the external bus interface is enabled bit BUSACTx 1 and configured bitfield BTYP the C167CS uses a subset of its port lines together with some control lines to build the external bus Table 9 1 Summary of External Bus Modes BTYP External Data Bus Width External Address Bus Mode Encoding 00 8 bit Data Demultiplexed Addresses 0 1 8 bit Data Multiplexed Addresses 10 16 bit Data Demultiplexed Addresses 11 16 bit Data Multiplexed Addresses The bus configuration BTYP for the address windows BUSCONA BUSCON 1 is selected via software typically during the initialization of the system The bus configuration BTYP for the defa
361. ia software This allows each interrupt source to be programmed or modified with just one instruction When accessing interrupt control registers through instructions which operate on word data types their upper 8 bits 15 8 will return zeros when read and will discard written data The layout of the Interrupt Control registers shown below applies to each xxIC register where xx stands for the mnemonic for the respective source User s Manual 5 6 V2 0 2000 07 _ d nfineon ed technologies Derivatives Interrupt and Trap Functions xxIC E SFR yyyyuzzy Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 XxIR xxlE ILVL GLVL wh rw rw Bit Function GLVL Group Level Defines the internal order for simultaneous requests of the same priority 3 Highest group priority 0 Lowest group priority ILVL Interrupt Priority Level Defines the priority level for the arbitration of requests Fu Highest priority level Ou Lowest priority level xxlE Interrupt Enable Control Bit individually enables disables a specific source 0 Interrupt request is disabled 1T Interrupt Request is enabled xxIR Interrupt Request Flag 0 No request pending T This source has raised an interrupt request The Interrupt Request Flag is set by hardware whenever a service request from the respective source occurs It is cleared automatically upon entr
362. ible and efficient addressing modes for high code density e Enhanced boolean bit manipulation with direct addressability of 6 Kbits for peripheral control and user defined flags e Hardware traps to identify exception conditions during runtime e HLL support for semaphore operations and efficient data access Integrated On Chip Memory e 3 KByte internal RAM for variables register banks system stack and code e 8 KByte on chip high speed XRAM for variables user stack and code e 32 KByte on chip ROM not for ROMless devices External Bus Interface Multiplexed or demultiplexed bus configurations Segmentation capability and chip select signal generation e 8 bit or 16 bit data bus Bus cycle characteristics selectable for five programmable address areas User s Manual 1 4 V2 0 2000 07 o nfineon oi technologies Derivatives Introduction 16 Priority Level Interrupt System e 56 interrupt nodes with separate interrupt vectors e 240 180 ns typical interrupt latency 400 300 ns maximum in case of internal program execution Fast external interrupts 8 Channel Peripheral Event Controller PEC e Interrupt driven single cycle data transfer Transfer count option std CPU interrupt after programmable number of PEC transfers Eliminates overhead of saving and restoring system state for interrupt requests Intelligent On Chip Peripheral Subsystems 24 channel 10 bit A D Converter with programmable conversion time
363. ic MCA04369 Compact Two Master Systems Master Slave Mode When two C167CSs or other members of the C166 Family are to be connected in this way the external bus arbitration logic normally required to combine the respective output signals HLDA and BREQ can be left out In this case one of the controllers operates in Master Mode the standard default operating mode DP6 7 0 while the other one must operate in Slave Mode selected with DP6 7 1 In this configuration the master device normally controls the external bus while the slave device gets control of iton demand only In most cases this requires that at least the slave device operates out of internal resources most of the time in order to get an acceptable overall system performance User s Manual 9 35 V2 0 2000 07 e nfineon ed technologies Derivatives The External Bus Interface In Slave Mode the C167CS inverts the direction of its HLDA pin and uses it as the bus grant input BGR while the master s HLDA pin remains an output This permits the direct connection of these two signals without any additional glue logic for bus arbitration The BREQ outputs are mutually connected to the other partners HOLD input see Figure 9 15 C167CR in Master Mode C167CR in Slave Mode Ext Bus MCS04370 The pullups provide correct signal levels during the initialization phase Figure 9 15 Sharin
364. ication flags The time period for an overflow of the watchdog timer is programmable in two ways The input frequency to the watchdog timer can be selected via a prescaler controlled by bits WDTPRE and WDTIN in register WDTCON to be fopu 2 fcpu 4 fcpu 128 or fopy 256 The reload value WDTREL for the high byte of WDT can be programmed in register WDTCON The period Pwpr between servicing the watchdog timer and the next overflow can therefore be determined by the following formula 2 1 lt WDTPRE gt lt WDTIN gt x 6 x 216 _ lt WDTREL gt x 23 PWDT A fopu User s Manual 13 4 V2 0 2000 07 o nfineon e technologies Derivatives The Watchdog Timer WDT Table 13 1 marks the possible ranges depending on the prescaler bits WDTPRE and WDTIN for the watchdog time which can be achieved using a certain CPU clock Table 13 1 Watchdog Time Ranges CPU clock Prescaler Reload value in WDTREL fcPu n Swot FFy 7Fy 00 S250 0 0 fopu 2 42 67 us 5 50 ms 10 92 ms 0 1 4 85 33 S 11 01 ms 21 85 ms 12 MHz fCPU a 1 0 fcpu 128 2 73 ms 352 3 ms 699 1 ms 1 1 fcpu 256 5 46 ms 704 5 ms 1398 ms 0 0 fopu 2 32 00 us 4 13 ms 8 19 ms 0 1 fcpu 4 64 00 us 8 26 ms 16 38 ms 16 MHz 1 0 fcpu 128 2 05 ms 264 2 ms 524 3 ms 1 1 fcpu 256 4 10 ms 528 4 ms 1049 ms 0 0 fopy 2 25 60 us 3 30 ms 6 55 ms 0 1 4 51 20 S 6 61 ms 1
365. ich is allowed in counter mode is fcpy 8 To ensure that a transition of the count input signal which is applied to T6lN is correctly recognized its level should be held high or low for at least 4 fcpy cycles before it changes User s Manual 10 29 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units 10 2 2 GPT2 Auxiliary Timer T5 The auxiliary timer T5 can be configured for timer gated timer or counter mode with the same options for the timer frequencies and the count signal as the core timer T6 In addition the auxiliary timer can be concatenated with the core timer operation in counter mode Its contents may be captured to register CAPREL upon a selectable trigger The individual configuration for timer T5 is determined by its bitaddressable control register T5CON Note that functions which are present in both timers of block GPT2 are controlled in the same bit positions and in the same manner in each of the specific control registers Note The auxiliary timer has no output toggle latch and no alternate output function T5CON Timer 5 Control Register SFR FF46 A34 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5 T5 T5 T5 rw rw rw rw rw rw rw rw rw Bit Function T5l Timer 5 Input Selection Depends on the Operating Mode see respective sections T5M Timer 5 Mode Control Basic Operating Mode 000 Tim
366. imer Input Frequencies Resolution and Periods 20 MHz fcpu 20 MHz Timer Input Selection T2I TS3I TAI 0008 001p 010 011g 1008 101g 1108 111g Prescaler factor 8 16 32 64 128 256 512 1024 Input 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 Frequency MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400 ns 800 ns 1 6 us 3 2 us 6 4 us 12 8 us 25 6 us 51 2 us Period 26 2 ms 52 5 ms 105 ms 210 ms 420 ms 840 ms 1 68s 3 36s Table 10 3 GPT1 Timer Input Frequencies Resolution and Periods 2 25 MHz fcpu 25 MHz Timer Input Selection T2I TS3I TAI 0008 001g 010 011g 100g 101g 110g 111g Prescaler factor 8 16 32 64 128 256 512 1024 Input 3 125 1 56 781 25 390 62 195 3 97 65 48 83 24 42 Frequency MHz MHz kHz kHz kHz kHz kHz kHz Resolution 320 ns 640 ns 1 28 us 2 56 us 5 12 us 10 2 us 20 5 us 41 0 us Period 21 0 ms 41 9 ms 83 9 ms 168 ms 336 ms 671 ms 1 34 s 2 68s Table 10 4 GPT1 Timer Input Frequencies Resolution and Periods 33 MHz fcpu 33 MHz Timer Input Selection T2I T3I TAI 0008 001g 010 011g 100g 101g 110g 111g Prescaler factor 8 16 32 64 128 256 512 1024 Input 4 125 2 0625 1 031 515 62 257 81 128 91 64 45 32 23 Frequency MHz MHz MHz kHz kHz kHz kHz kHz Resolution 242 ns 485 ns 970 ns 1 94 us 3 88 us 7 76 us 15 5 us 31 0 us Period 15 9 ms 31 8 ms 63 6 ms
367. imer interrupt request flag TxIR for the respective timer will be set This flag can be used to generate an interrupt or trigger a PEC service request when enabled by the respective interrupt enable bit TxIE Each timer has its own bitaddressable interrupt control register TxIC and its own interrupt vector TXINT The organization of the interrupt control registers TxIC is identical with the other interrupt control registers eo TO Intr Ctrl Reg SFR FF9C CE Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOIR TOIE ILVL GLVL rh rw rw rw T1IC CAPCOM T1 Intr Ctrl Reg SFR FF9E CFy Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T1IR T1IE ILVL GLVL rh rw rw rw T7IC CAPCOM T7 Intr Ctrl Reg ESFR F17A BEy Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T7IR T7IE ILVL GLVL wh rw rw rw T8IC CAPCOM T8 Intr Ctrl Reg ESFR F17Cj BF Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T8IR T8IE ILVL GLVL wh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 16 9 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units 16 3 Capture C
368. ing These instructions provide efficient control and testing of peripherals while enhancing data manipulation Unlike other microcontrollers these instructions provide direct access to two operands in the bit addressable space without requiring to move them into temporary flags The same logical instructions available for words and bytes are also supported for bits This allows the user to compare and modify a control bit for a peripheral in one instruction Multiple bit shift instructions have been included to avoid long instruction streams of single bit shift operations These are also performed in a single machine cycle In addition bit field instructions have been provided which allow the modification of multiple bits from one operand in a single instruction User s Manual 2 4 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview High Performance Branch Call and Loop Processing Due to the high percentage of branching in controller applications branch instructions have been optimized to require one extra machine cycle only when a branch is taken This is implemented by precalculating the target address while decoding the instruction To decrease loop execution overhead three enhancements have been provided The first solution provides single cycle branch execution after the first iteration of a loop Thus only one machine cycle is lost during the execution of the entire loop In loops which fall
369. ing advantage of this technology is the integrated CAN module The C165 type devices are reduced versions of the C167 which provide a smaller package and reduced power consumption at the expense of the A D converter the CAPCOM units and the PWM module User s Manual 1 2 V2 0 2000 07 j d nfineon oi technologies Derivatives Introduction The C164 type devices and some of the C161 type devices are further enhanced by a flexible power management and form the third generation of the 16 bit controller family This power management mechanism provides effective means to control the power that is consumed in a certain state of the controller and thus allows the minimization of the overall power consumption with respect to a given application A variety of different versions is provided which offer various kinds of on chip program memory Mask programmable ROM Flash memory OTP memory ROMless with no non volatile memory at all Also there are devices with specific functional units The devices may be offered in different packages temperature ranges and speed classes More standard and application specific derivatives are planned and in development Note Not all derivatives will be offered in any temperature range speed class package or program memory variation Information about specific versions and derivatives will be made available with the devices themselves Contact your Infineon representative for up to
370. ing purposes A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers A parity bit can automatically be generated on transmission or be checked on reception Framing error detection allows to recognize data frames with missing stop bits An overrun error will be generated if the last character received has not been read out of the receive buffer register at the time the reception of a new character is complete The SSC supports full duplex synchronous communication at up to 6 25 8 25 Mbaud 25 33 MHz CPU clock It may be configured so it interfaces with serially linked peripheral components A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning For transmission reception and error handling 3 separate interrupt vectors are provided The SSC transmits or receives characters of 2 16 bits length synchronously to a shift clock which can be generated by the SSC master mode or by an external master slave mode The SSC can start shifting with the LSB or with the MSB and allows the selection of shifting and latching clock edges as well as the clock polarity A number of optional hardware error detection capabilities has been included to increase the reliability of data transfers Transmit and receive error supervise the correct handling of the data buffer Phase and baudrate error detect incorrect serial data User s Manual 2 13 V2 0 2
371. ing the start code into the internal RAM of the C167CS via the serial interface ASCO The C167CS will remain in bootstrap loader mode until a hardware reset not selecting BSL mode or a software reset Default The C167CS starts fetching code from location 00 0000 the bootstrap loader is off User s Manual 20 16 V2 0 2000 07 _ d Infineon iiis technologies Derivatives System Reset External Bus Type Pins POL 7 and POL 6 BUSTYP select the external bus type during reset if an external start is selected via pin EA This allows the configuration of the external bus interface of the C167CS even for the first code fetch after reset The two bits are copied into bit field BTYP of register BUSCONO POL 7 controls the data bus width while POL 6 controls the address output multiplexed or demultiplexed This bit field may be changed via software after reset if required Table 20 3 Configuration of External Bus Type POL 7 6 BTYP External Data Bus Width External Address Bus Mode Encoding 00 8 bit Data Demultiplexed Addresses 0 1 8 bit Data Multiplexed Addresses 10 16 bit Data Demultiplexed Addresses 11 16 bit Data Multiplexed Addresses PORTO and PORT1 are automatically switched to the selected bus mode In multiplexed bus modes PORTO drives both the 16 bit intra segment address and the output data while PORT1 remains in high impedance state as long as no demultiplexed bus is selected via one
372. input function Port lines with only an alternate output function however have different structures due to the way the direction of the pin is switched and depending on whether the pin is accessible by the user software or not in the alternate function mode All port lines that are not used for these alternate functions may be used as general purpose IO lines When using port pins for general purpose output the initial output value should be written to the port latch prior to enabling the output drivers in order to avoid undesired transitions on the output pins This applies to single pins as well as to pin groups see examples below User s Manual 7 10 V2 0 2000 07 C167CS Derivatives technologies Parallel Ports OUTPUT ENABLE SINGLE PIN BSET P4 0 Initial output level is high BSET DP4 0 Switch on the output driver OUTPUT_ENABLE_PIN_GROUP BF LDL P4 05H 05H Initial output level is high BF LDL DP4 05H 05H Switch on the output drivers Note When using several BSET pairs to control more pins of one port these pairs must be separated by instructions which do not reference the respective port see Section 4 2 Each of these ports and the alternate input and output functions are described in detail in the following subsections User s Manual 7 11 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports 7 4 PORTO The two 8 bit ports POH and POL represent the higher
373. interrupt enable bit T5IE or T6IE in register TxIC CRIE in register CRIC is set There is an interrupt control register for each of the two timers and for the CAPREL register T5IC Timer 5 Intr Ctrl Reg SFR FF66 B3j Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T5IR T5IE ILVL GLVL rh rw rw R T6IC Timer 6 Intr Ctrl Reg SFR FF68 B44 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6IR T6IE ILVL GLVL rh rw rw RW CRIC CAPREL Intr Ctrl Reg SFR FF6AU B5j Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRIR CRIE ILVL GLVL rh rw rw RW Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 10 38 V2 0 2000 07 j d Infineon iis technologies Derivatives The Asynchronous Synchronous Serial Interface 11 The Asynchronous Synchronous Serial Interface The Asynchronous Synchronous Serial Interface ASCO provides serial communication between the C167CS and other microcontrollers microprocessors or external peripherals The ASCO supports full duplex asynchronous communication up to 781 KBaud 1 03 MBaud and half duplex synchronous communication up to 3 1 4 1 MBaud 25 33 MHz CPU clock In synchronous mode data are
374. interrupt function may either be combined with the pin s main function or may be used instead of it i e if the main pin function is not required Interrupt signals may be connected to e CC31IO CC161O the capture input compare output lines of the CAPCOM2 unit e CC151O CCOIO the capture input compare output lines of the CAPCOM unit e TAIN T2IN the timer input pins CAPIN the capture input of GPT2 For each of these pins either a positive a negative or both a positive and a negative external transition can be selected to cause an interrupt or PEC service request The edge selection is performed in the control register of the peripheral device associated with the respective port pin The peripheral must be programmed to a specific operating mode to allow generation of an interrupt by the external signal The priority of the interrupt request is determined by the interrupt control register of the respective peripheral interrupt source and the interrupt vector of this source will be used to service the external interrupt request Note In order to use any of the listed pins as external interrupt input it must be switched to input mode via its direction control bit DPx y in the respective port direction control register DPx Table 5 8 Pins to be Used as External Interrupt Inputs Port Pin Original Function Control Register P7 7 A CC31 281O CAPCOM register 31 28 capture input CC31 CC28 P1H 7 4 CC27 241O CAPCOM register 27
375. ion of T3OTL is selected to clock the auxiliary timer this concatenation forms a 32 bit or a 33 bit timer counter 32 bit Timer Counter If both a positive and a negative transition of T3OTL is used to clock the auxiliary timer this timer is clocked on every overflow underflow of the core timer T3 Thus the two timers form a 32 bit timer 33 bit Timer Counter If either a positive or a negative transition of T3OTL is selected to clock the auxiliary timer this timer is clocked on every second overflow underflow of the core timer T3 This configuration forms a 33 bit timer 16 bit core timer T3OTL 16 bit auxiliary timer The count directions of the two concatenated timers are not required to be the same This offers a wide variety of different configurations T3 can operate in timer gated timer or counter mode in this case Tyl Sosy Core Timer Ty TyOTL TyR TyOUT Up Down Interrupt r Request Edge Select Interrupt Pd Auxiliary Timer Tx Request TxR Txl Note Line only affected by over underflows of T3 but NOT by software modifications of T3OTL MCB02034 T3OUT P3 3 x 2 4 y 3 n 3 10 Figure 10 11 Concatenation of Core Timer T3 and an Auxiliary Timer User s Manual 10 16 V2 0 2000 07 j d Infineon iiis technologies Derivatives The General Purpose Timer Units Auxiliary Timer in Reload Mode Reload mode for the auxiliary timers T2
376. ion of a stack overflow or underflow Hardware detection of the selected memory space is placed at the internal memory decoders and allows the user to specify any address directly or indirectly and obtain the desired data without using temporary registers or special instructions An 8 KByte 16 bit Wide on chip XRAM arranged in two blocks of 2 KByte and 6 KByte provides fast access to user data variables user stacks and code The on chip XRAM is realized as an X Peripheral and appears to the software as an external RAM Therefore it cannot store register banks and is not bitaddressable The XRAM allows 16 bit accesses with maximum speed For Special Function Registers 1024 Bytes of the address space are reserved The standard Special Function Register area SFR uses 512 Bytes while the Extended Special Function Register area ESFR uses the other 512 Bytes E SFRs are wordwide registers which are used for controlling and monitoring functions of the different on chip units Unused E SFR addresses are reserved for future members of the C166 Family with enhanced functionality An Optional Internal ROM 32 KByte provides for both code and constant data storage This memory area is connected to the CPU via a 32 bit wide bus Thus an entire double word instruction can be fetched in just one machine cycle Program execution from on chip program memory is the fastest of all possible alternatives User s Manual 2 9 V2 0 2000 07 o nfine
377. ions available for this interrupt such as enabling disabling level and group priority and interrupt or PEC service see note below The on chip CAN module is connected to an XBUS interrupt control register As for all other interrupts the node interrupt request flag is cleared automatically by hardware when this interrupt is serviced either by standard interrupt or PEC service Note As a rule CAN interrupt requests can be serviced by a PEC channel However because PEC channels only can execute single predefined data transfers there are no conditional PEC transfers PEC service can only be used if the respective request is known to be generated by one specific source and that no other interrupt request will be generated in between In practice this seems to be a rare case Since an interrupt request of the CAN module can be generated due to different conditions the appropriate CAN interrupt status register must be read in the service routine to determine the cause of the interrupt request The interrupt identifier INTID a number in the Port Control Interrupt Register PCIR indicates the cause of an interrupt When no interrupt is pending the identifier will have the value 00y If the value in INTID is not 00 4 then there is an interrupt pending If bit IE in the control status register is set also the interrupt signal to the CPU is activated The interrupt signal to the interrupt node remains active until INTID gets 00 i e all
378. ionship between the bank 1 and bank 2 register of a pair and the effected output pins for double register compare mode is listed in Table 16 6 Table 16 6 Register Pairs for Double Register Compare Mode CAPCOM Unit CAPCOM2 Unit Register Pair Associated Register Pair Associated Bank 1 Bank 2 Output Pin Bank 1 Bank 2 Output Pin CCO CC8 CCOIO CC16 CC24 CC16lO CC1 CC9 CC1IO CC17 CC25 CC171O CC2 CC10 CC2lO CC18 CC26 CC18lO CC3 CC11 CC3IO CC19 CC27 CC19lIO CC4 CC12 CCAIO CC20 CC28 CC20I0 CC5 CC13 CC5IO CC21 CC29 CC211O CC6 CC14 CC6IO CC22 CC30 CC2210 CC7 CC15 CC7IO CC23 CC31 CC2310 The double register compare mode can be programmed individually for each register pair In order to enable double register mode the respective bank 1 register see Table 16 6 must be programmed to compare mode 1 and the corresponding bank 2 register see Table 16 6 must be programmed to compare mode 0 If the respective bank 1 compare register is disabled or programmed for a mode other than mode 1 the corresponding bank 2 register will operate in compare mode 0 interrupt only mode In the following a bank 2 register programmed to compare mode 0 will be referred to as CCz while the corresponding bank 1 register programmed to compare mode 1 will be referred to as CCx User s Manual 16 19 V2 0 2000 07 o nfineon e technologies Derivatives The Capture Compare Units When a match is detected
379. ip Select Lines Note 11 Five CS4 CSO Default without pull downs 10 None 0 1 Two CS1 CSO 00 Three CS2 CSO Default All 5 chip select lines active CS4 CSO Note The selected number of CS signals can be changed via software after reset see Section 20 4 2 Segment Address Lines Pins POH 4 and POH 3 SALSEL define the number of active segment address lines during reset This allows the selection which pins of Port 4 drive address lines and which are used for general purpose IO The two bits are latched in register RPOH Depending on the system architecture the required address space is chosen and accessible right from the start so the initialization routine can directly access all locations without prior programming The required pins of Port 4 are automatically switched to address output mode Table 20 5 Configuration of Segment Address Lines POH 4 3 SALSEL Segment Address Lines Directly Accessible A Space 1 1 Two A17 A16 256 KByte Default without pull downs 10 Eight A23 A16 16 MByte Maximum 0 1 None 64 KByte Minimum 00 Four A19 A16 1 MByte Even if not all segment address lines are enabled on Port 4 the C167CS internally uses its complete 24 bit addressing mechanism This allows the restriction of the width of the effective address bus while still deriving CS signals from the complete addresses Default 2 bit segment address A17 A1
380. ipheral in many cases is represented by just a few registers the XADRSx registers partly select smaller address windows than the standard ADDRSEL registers As the XBCONx XADRSx register pairs control integrated peripherals rather than externally connected ones they are fixed by mask programming rather than being user programmable X Peripheral accesses provide the same choices as external accesses so these peripherals may be bytewide or wordwide Because the on chip connection can be realized very efficient and for performance reasons X Peripherals are only implemented with a separate address bus i e in demultiplexed bus mode Interrupt nodes are provided for X Peripherals to be integrated Note If you plan to develop a peripheral of your own to be integrated into a C167CS device to create a customer specific version please ask for the specification of the XBUS interface and for further support User s Manual 9 37 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 8 1 Accessing the On chip XBUS Peripherals Enabling of XBUS Peripherals After reset all on chip XBUS peripherals are disabled In order to be usable an XBUS peripheral must be selected via register XPERCON and then enabled via the global enable bit XPEN in register SYSCON XPERCON X Peripheral Control Register ESFR F0244 121 Reset Value 0401 15 14 13 12 11 10 9 8 7 6 9 4 3 2 1 0 X X X X X X X X X X X X X X X X PER
381. ire to save and restore the machine status Each interrupt source is prioritized every machine cycle in the interrupt control block If PEC service is selected a PEC transfer is started If CPU interrupt service is requested the current CPU priority level stored in the PSW register is tested to determine whether a higher priority interrupt is currently being serviced When an interrupt is acknowledged the current state of the machine is saved on the internal system stack and the CPU branches to the system specific vector for the peripheral The PEC contains a set of SFRs which store the count value and control bits for eight data transfer channels In addition the PEC uses a dedicated area of RAM which contains the source and destination addresses The PEC is controlled similar to any other peripheral through SFRs containing the desired configuration of each channel An individual PEC transfer counter is implicitly decremented for each PEC service except forming in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the vector location related to the corresponding source PEC services are very well suited for example to move register contents to from a memory table The C167CS has 8 PEC channels each of which offers such fast interrupt driven data transfer capabilities Memory Areas The memory space of the C167CS is configured in a Von Neumann architecture which means that code memory data memor
382. ires that the slave s baud rate generator is programmed to the same baud rate as the master device This feature detects false additional or missing pulses on the clock line within a certain frame Note If this error condition occurs and bit SSCAREN 1 an automatic reset of the SSC will be performed in case of this error This is done to reinitialize the SSC if too few or too many clock pulses have been detected User s Manual 12 15 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface A Transmit Error Slave mode is detected when a transfer was initiated by the master shift clock gets active but the transmit buffer SSCTB of the slave was not updated since the last transfer This condition sets the error flag SSCTE and when enabled via SSCTEN the error interrupt request flag SSCEIR If a transfer starts while the transmit buffer is not updated the slave will shift out the old contents of the shift register which normally is the data received during the last transfer This may lead to the corruption of the data on the transmit receive line in half duplex mode open drain configuration if this slave is not selected for transmission This mode requires that slaves not selected for transmission only shift out ones i e their transmit buffers must be loaded with FFFFj prior to any transfer Note A slave with push pull output drivers which is not selected for transmis
383. is an independent timer chain which is clocked directly with the oscillator clock and serves for different purposes System clock to determine the current time and date Cyclic time based interrupt 48 bit timer for long term measurements Control Registers Data Registers Counter Registers Interrupt Control SYSCON2 E T14REL E ISNC E XP3IC E SYSCON2 Power Management Control Register RTCH Real Time Clock Register High Word T14REL Timer T14 Reload Register RTCL Real Time Clock Register Low Word T14 Timer T14 Count Register ISNC Interrupt Subnode Control Register XP3IC RTC Interrupt Control Register MCA04463 Figure 14 1 SFRs Associated with the RTC Module The RTC module consists of a chain of 3 divider blocks a fixed 8 1 divider the reloadable 16 bit timer T14 and the 32 bit RTC timer accessible via registers RTCH and RTCL Both timers count up The clock signal for the RTC module is directly derived from the on chip oscillator frequency not from the CPU clock and fed through a separate clock driver It is therefore independent from the selected clock generation mode of the C167CS and is controlled by the clock generation circuitry Table 14 1 RTC Register Location within the ESFR space Register Long Short Reset Notes Name Address Value T14 FOD2y 694 UUUU Prescaler timer generates input clock for RTC register and periodic interrupt T14REL FODO 684 UUUU Timer reloa
384. is port is used for general purpose IO the direction of each line can be configured via the corresponding direction registers DP1H and DP1L P1L PORT1 Low Register SFR FF044 824 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1L PiL PiL P1L PiL P1L P1L P1L i 6 5 4 3 2 x 0 P1H PORT1 High Register SFR FF06 834 Reset Value 001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1H P1H P1H P1H P1H P1H P1H P1H 7 6 5 4 3 2 1 0 rwh rwh rwh rwh rw rw rw rw Bit Function P1X y Port data register P1H or P1L bit y User s Manual 7 16 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports DP1L P1L Direction Ctrl Register ESFR F104 824 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP1 L 7 L 6 L 5 L 4 L 3 L 2 L 1 L O rw rw rw rw rw rw rw rw DP1H P1H Direction Ctrl Register ESFR F106 834 Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DP1 DP1 DP1 DP1 DP1 DP1 DP1 DP H 7 H 6 H 5 H 4 H 3 H 2 H 1 H 0 rw rw rw rw rw rw rw rw Bit Function DP1X y Port direction register DP1H or DP1L bit y DP1X y 0 Port line P1
385. is simply performed by specifying the correct signed or unsigned version of the multiply or divide instruction The result is then stored in register MD The overflow flag V is set if the result from a multiply or divide instruction is greater than 16 bits This flag can be used to determine whether both word halfs must be transferred from register MD The high portion of register MD MDH must be moved into the register file or memory first in order to ensure that the MDRIU flag reflects the correct state The following instruction sequence performs an unsigned 16 by 16 bit multiplication SAVE JNB MDRIU START Test if MD was in use SCXT MDC 0010H Save and clear control register leaving MDRIU set only required for interrupted multiply divide instructions BSET SAVED Indicate the save operation PUSH MDH Save previous MD contents PUSH MDL j Oon system stack START MULU R1 R2 Multiply 16 16 unsigned Sets MDRIU JMPR cc NV COPYL Test for only 16 bit result MOV R3 MDH Move high portion of MD COPYL MOV RA MDL Move low portion of MD Clears MDRIU RESTORE JNB SAVED DONE Test if MD registers were saved POP MDL Restore registers POP MDH POP MDC BCLR SAVED Multiplication is completed program continues DONE User s Manual 22 2 V2 0 2000 07 j d nfineon ed technologies Derivatives System Programming The above save sequence and the restore sequence after C
386. is specified via bitfield CLKREL in register SYSCONe factor lt CLKREL gt 1 When bitfield CLKREL is written during SDD operation the reload counter will output one more clock pulse with the old frequency in order to resynchronize internally before generating the new frequency If direct drive mode is configured clock signal fpp is directly fed to cpy if prescaler mode is configured clock signal fpp is additionally divided by 2 1 to generate fopy see examples below CLKREL Reload Counter fosc l Dog dog og L B ctor 3 Direct Drive MCD04477 Figure 21 3 Slow Down Divider Operation Using e g a 5 MHz input clock the on chip logic may be run at a frequency down to 156 25 kHz or 78 kHz without an external hardware change An implemented PLL may be switched off in this case or kept running depending on the requirements of the application see Table 21 2 Note During Slow Down operation the whole device including bus interface and generation of signals CLKOUT or FOUT is clocked with the SDD clock see Figure 21 3 User s Manual 21 10 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management Table 21 2 PLL Operation in Slow Down Mode Advantage Disadvantage Oscillator Watchdog PLL Fast switching back to PLL add
387. is used for configuration For a reset with external access EA 0 pin RD controls the oscillator watchdog The latched RD level determines the reset value of bit OWDDIS in register SYSCON The default high level on pin RD leaves the oscillator watchdog active OWDDIS 0 while a low level disables the watchdog OWDDIS 1 e g for testing purposes For a true single chip mode reset EA 1 pin RD enables the bootstrap loader when driven low pin ALE is evaluated together with pin RD For standard configuration pin RD should be high or not connected The External Write Strobe WR WRL controls the data transfer from the C167CS to an external memory or peripheral device This pin may either provide an general WR signal activated for both byte and word write accesses or specifically control the low byte of an external 16 bit device WRL together with the signal WRH alternate function of P3 12 BHE During accesses to on chip X Peripherals WR WRL remains inactive high During reset an internal pullup ensures an inactive high level on the WR WRL output The Ready Input READY receives a control signal from an external memory or peripheral device that is used to terminate an external bus cycle provided that this function is enabled for the current bus cycle READY may be used as synchronous READY or may be evaluated asynchronously When waitstates are defined fora READY controlled address window the REA
388. ister XXXXy C2BTR EE04 X CAN Bit Timing Register UUUU C2GMS EE064 X CAN Global Mask Short UFUUJ C2UGML EE084 X CAN Upper Global Mask Long UUUUJ C2LGML EEOA X CAN2 Lower Global Mask Long UUUU C2UMLM EEOCy X CAN 2 Upper Mask of Last Message UUUU C2LMLM EEOE X CAN Lower Mask of Last Message UUUUJ C2MCRn EEn0y X CAN Message Ctrl Reg msg n UUUUJ C2UARn EEn24 X CAN2 Upper Arbitration Reg msg n UUUU C2LARn EEn4y X CAN Lower Arbitration Register msg n UUUU C2MCFGn EEn6y X CAN Message Configuration Register UU msg n C1CSR EF00 X CAN1 Control Status Register XX01 H C1PCIR EFO2y X CAN1 Port Control and Interrupt Register XXXXy C1BTR EF044 X CAN1 Bit Timing Register UUUU C1GMS EF06 X CAN 1 Global Mask Short UFUUJ C1UGML EF08 X CAN1 Upper Global Mask Long UUUUJ C1LGML EFOA X CAN1 Lower Global Mask Long UUUU C1UMLM EFOC X CAN1 Upper Mask of Last Message UUUU C1LMLM EFOE X CAN1 Lower Mask of Last Message UUUU C1MCRn EFnO X CAN 1 Message Ctrl Reg msg n UUUUJ C1UARn EFn24 X CAN1 Upper Arbitration Reg msg n UUUU User s Manual 23 14 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value CiLARn EFn44
389. isters are read for this the respective last RTC value must be available somewhere Note For the majority of applications however the standard accuracy provided by the RTC s structure will be more than sufficient User s Manual 14 4 V2 0 2000 07 o nfineon e technologies Derivatives The Bootstrap Loader 15 The Bootstrap Loader The built in bootstrap loader of the C167CS provides a mechanism to load the startup program which is executed after reset via the serial interface In this case no external memory or an internal ROM OTP Flash is required for the initialization code The bootstrap loader moves code data into the internal RAM but it is also possible to transfer data via the serial interface into an external RAM using a second level loader routine ROM memory internal or external is not necessary However it may be used to provide lookup tables or may provide core code i e a set of general purpose subroutines e g for IO operations number crunching system initialization etc RSTIN POL 4 or RD RxDO CSP IP 32 bytes Int Boot ROM BSL routine User Software BSL initialization time gt 2 us Jopu 20 MHz Zero byte 1 start Bit eight 0 data Bits 1 stop Bit sent by host Identification byte sent by C 167CS 32 bytes of code data sent by host Caution TxDO is only driven a certain time after reception of the zero byte 2 5 us fopy 20 MHz Internal Boot ROM akon
390. it IEN Mainly these are external interrupts and the RTC if running Note The receive lines of serial interfaces may be internally routed to external interrupt inputs see EXISEL All peripherals except for the RTC are stopped and hence cannot generate an interrupt request The realtime clock RTC can be kept running in Sleep mode in order to maintain a valid system time as long as the supply voltage is applied This enables a system to determine the current time and the duration of the period while it was down by comparing the current time with a timestamp stored when Sleep mode was entered The supply current in this case remains well below 1 mA During Sleep mode the voltage at the Vpp pins can be lowered to 2 7 V while the RTC and its selected oscillator will still keep on running and the contents of the internal RAM will still be preserved When the RTC and oscillator is disabled the internal RAM is preserved down to a voltage of 2 5 V Note When the RTC remains active in Sleep mode also the oscillator which generates the RTC clock signal will keep on running of course If the supply voltage is reduced the specified maximum CPU clock frequency for this case must be respected For wakeup input edge recognition and CPU start the power must be within the specified limits however The total power consumption in Sleep mode depends on the active circuitry i e RTC on or off and on the current that flows through the port drivers
391. it shifting ASHR Prioritize Instruction Determination of the number of shift cycles required to normalize a word operand floating point support PRIOR Data Movement Instructions e Standard data movement of a word or byte MOV MOVB Data movement of a byte to a word location with either sign or zero byte extension MOVBS MOVBZ Note The data movement instructions can be used with a big number of different addressing modes including indirect addressing and automatic pointer in decrementing System Stack Instructions Pushing of a word onto the system stack PUSH Popping of a word from the system stack POP e Saving of a word on the system stack and then updating the old word with a new value provided for register bank switching SCXT User s Manual 24 2 V2 0 2000 07 nfineon technologies o C167CS Derivatives Instruction Set Summary Jump Instructions Conditional jumping to an either absolutely indirectly or relatively addressed target instruction within the current code segment JMPA Unconditional jumping to an absolutely addressed target instruction within any code segment JMPS Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit JB Conditional jumping to a relatively addressed target instruction within the current code segment depending on the state of a selectable bit with a post inversion of th
392. ith a factor of 1 4 Watch the different requirements for frequency and duty cycle of the oscillator input clock for the possible selections Oscillator Watchdog Control The on chip oscillator watchdog OWD may be disabled via hardware by externally pulling the RD line low upon a reset similar to the standard reset configuration via PORTO At the end of any reset bit OWDDIS in register SYSCON reflects the inverted level of pin RD at that time The software may again enable the oscillator watchdog by clearing bit OWDDIS before the execution of EINIT Note If direct drive or prescaler operation is selected as basic clock generation mode see above the PLL is switched off whenever bit OWDDIS is set via software or via hardware configuration User s Manual 20 19 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset 20 4 2 For a single chip mode reset indicated by EA 1 the configuration via PORTO is replaced by a fixed configuration value In this case PORTO needs no external circuitry pullups pulldowns and also the internal configuration pullups are not activated The necessary startup modes are configured via pins RD and ALE This fixed default configuration is activated after each Long Hardware Reset and selects a safe worst case configuration The initialization software can then modify these parameters and select the intended configuration for a given application Table 20 7 lists the respectiv
393. ivated when the C167CS s reset input is activated when a software reset is executed and in case of a watchdog reset Activating the CAN module s reset line triggers a hardware reset This hardware reset disconnects the CAN TXD output from the port logic clears the error counters e resets the busoff state e switches the Control Register s low byte to O14 leaves the Control Register s high byte and the Interrupt Register undefined does not change the other registers including the message objects notified as UUUU Note The first hardware reset after power on leaves the unchanged registers in an undefined state of course The value 01 in the Control Registers low byte prepares for the module initialization CAN Module Activation After a reset the CAN module is disabled Before it can be used to receive or transmit messages the application software must activate the CAN module Three actions are required for this purpose General Module Enable globally activates the CAN module This is done by setting bit XPEN in register SYSCON after setting the corresponding selection bit in register XPERCON Pin Assignment selects a pair of port pins that connect the CAN module to the external transceiver This is done via bitfield IPC in register CSR Module Initialization determines the functionality of the CAN module baudrate active objects etc This is the major part of the activation and is described in the following
394. ives The On Chip CAN Interface Message Configuration The Message Configuration Register low byte of MCFGn holds a description of the message within this object Note There is no don t care option for bits XTD and DIR So incoming frames can only match with corresponding message objects either standard XTD 0 or extended XTD 1 Data frames only match with receive objects remote frames only match with transmit objects When the CAN controller stores a data frame it will write all the eight data bytes into a message object If the data length code was less than 8 the remaining bytes of the message object will be overwritten by non specified values MCFGn Message Configuration Reg XReg EFn6j Reset Value UU 15 14 13 12 11 1470 9 8 7 6 5 4 3 2 1 0 Data Byte 0 DLC DIR XTD 0 0 rw rw rw rw r r Bit Function XTD Extended Identifier 0 Standard This message object uses a standard 11 bit identifier Extended This message object uses an extended 29 bit identifier DIR Message Direction 0 Receive Object On TXRQ a remote frame with the identifier of this message object is transmitted On reception of a data frame with matching identifier that message is stored in this message object q1 Transmit Object On TXRQ the respective message object is transmitted On reception of a remote frame with matching identifier the TXRQ and RMTPND bits of
395. l Ports ODP8 P8 Open Drain Ctrl Reg ESFR F1D6 EBy Reset Value 004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ODP8 ODP8 ODP8 ODP8 ODP8 ODP8 ODP8 ODP8 7 6 5 4 3 2 4 0 Bit Function ODP8 y Port 8 Open Drain control register bit y ODP8 y 0 Port line P8 y output driver in push pull mode ODP8 y 1 Port line P8 y output driver in open drain mode Alternate Functions of Port 8 All Port 8 lines P8 7 0 serve as capture inputs or compare outputs CC23lO CC161O for the CAPCOM2 unit see Table 7 10 The usage of the port lines by the CAPCOM unit its accessibility via software and the precautions are the same as described for the Port 2 lines As all other capture inputs the capture input function of pins P8 7 0 can also be used as external interrupt inputs sample rate 16 TCL The CAN interface s can use 2 or 4 pins of Port 8 to interface the CAN Module s to an external transceiver In this case the number of possible CAPCOM IO lines is reduced Table 7 10 Alternate Functions of Port 8 Port 8 Pin Alternate Function P8 0 CC16lO Capture input compare output channel 16 or CAN P8 1 CC171O Capture input compare output channel 17 or CAN P8 2 CC18lO Capture input compare output channel 18 or CAN P8 3 CC19lO Capture input compare output channel 19 or CAN P8 4 CC20lO Capture input compare output channel 20 P8 5 CC211O Capture inp
396. l function Baud Rate Generator Reload register Reading SOBG returns the content of the timer bits 15 13 return zero while writing to SOBG always updates the reload register bits 15 13 are insiginificant An auto reload of the timer with the content of the reload register is performed each time SOBG is written to However if SOR 0 at the time the write operation to SOBG is performed the timer will not be reloaded until the first instruction cycle after SOR 1 Asynchronous Mode Baud Rates For asynchronous operation the baud rate generator provides a clock with 16 times the rate of the established baud rate Every received bit is sampled at the 7th 8th and 9th cycle of this clock The baud rate for asynchronous operation of serial channel ASCO and the required reload value for a given baudrate can be determined by the following formulas E Jopu Async 72 75 LGnBBG AV ZGRBBI 4 16 x 2 lt SOBRS gt x lt SOBRL gt 1 SOBRL LL TRU yy 16 x 2 lt SOBRS gt x Basync lt SOBRL gt represents the content of the reload register taken as unsigned 13 bit integer lt SOBRS gt represents the value of bit SOBRS i e 0 or 1 taken as integer The tables below list various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate for a number of CPU frequencies Note The deviation errors given in the tables below are
397. l initialize all SFRs and ports to their default state but will not change the contents of the internal RAM There are two levels of protection against unintentionally entering Power Down mode First the PWRDN Power Down instruction which is used to enter this mode has been implemented as a protected 32 bit instruction Second this instruction is effective only if the NMI Non Maskable Interrupt pin is externally pulled low while the PWRDN instruction is executed The microcontroller will enter Power Down mode after the PWRDN instruction has completed This feature can be used in conjunction with an external power failure signal which pulls the NMI pin low when a power failure is imminent The microcontroller will enter the NMI trap routine which can save the internal state into RAM After the internal state has been saved the trap routine may then execute the PWRDN instruction If the NMI pin is still low at this time Power Down mode will be entered otherwise program execution continues User s Manual 21 6 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management The initialization routine executed upon reset can check the reset identification flags in register WDTCON to determine whether the controller was initially switched on or whether it was properly restarted from Power Down mode The realtime clock RTC can be kept running in Power Down mode in order to maintain a valid system time as long as the
398. l input stage via register P1DIDIS This avoids undesired cross currents and switching noise while the analog input signal level is between Vi and Vip The functions of the A D converter are controlled by the bit addressable A D Converter Control Register ADCON Its bitfields specify the analog channel to be acted upon the conversion mode and also reflect the status of the converter ADCON ADC Control Register SFR FFAO D0 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD AD AD AD AD ADCTC ADSTC CRQ CIN WR BSY ST ADX ADM ADCH rw rw rwh rw rw wh wh rw rw rw Bit Function ADCH ADC Analog Channel Input Selection Selects the first ADC channel which is to be converted Bit ADX determines if ADCH selects a standard or extension channel ADM ADC Mode Selection 00 Fixed Channel Single Conversion 01 Fixed Channel Continuous Conversion 10 Auto Scan Single Conversion 11 Auto Scan Continuous Conversion ADX ADC Extension Channel Control 0 ADCH selects the standard channels AN15 ANO 1 ADCH selects the extension channels AN23 AN16 ADST ADC Start Bit 0 Stop a running conversion 1 Start conversion s User s Manual 18 3 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter Bit Function ADBSY ADC Busy Flag 0 ADC is idle 1 A conversion is active ADWR ADC Wait
399. latch the least significant address line AO is not relevant for word accesses The upper address lines An A16 are permanently output on Port 4 if segmentation is enabled and do not require latches The EBC initiates an external access by generating the Address Latch Enable signal ALE and then placing an address on the bus The falling edge of ALE triggers an external latch to capture the address After a period of time during which the address must have been latched externally the address is removed from the bus The EBC now activates the respective command signal RD WR WRL WRH Data is driven onto the bus either by the EBC for write cycles or by the external memory peripheral for read cycles After a period of time which is determined by the access time of the memory peripheral data become valid Read cycles Input data is latched and the command signal is now deactivated This causes the accessed device to remove its data from the bus which is then tri stated again Write cycles The command signal is now deactivated The data remain valid on the bus until the next external bus cycle is started Bus Cycle Segment P4 Address ALE N BUS P0 mu Address d Data Instr ES FREE X MCT02060 Figure 9 2 Multiplexed Bus Cycle User s Manual 9 4 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Demultiplexed
400. le is disabled by any means While a peripheral is disabled its output pins remain in the state they had at the time of disabling Software controls this flexible peripheral mangement via register SYSCON3 where each control bit is associated with an on chip peripheral module User s Manual 21 14 V2 0 2000 07 d nfineon ed technologies Derivatives Power Management SYSCONS3 System Control Reg 3 ESFR F1D4 EA Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PCDICANZ2CAN _ _ PPWM _ CC2 CC1 _ _ GPT sSC 2C ADC DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS rw rw rw x rw rw rw rw rw rw rw Bit Function associated peripheral module ADCDIS Analog Digital Converter ASCODIS USART ASCO SSCDIS Synchronous Serial Channel SSC GPTDIS General Purpose Timer Blocks CC1DIS CAPCOM Unit 1 CC2DIS CAPCOM Unit 2 PWMDIS Pulse Width Modulation Unit CANIDIS On chip CAN Module 17 CAN2DIS On chip CAN Module 2 PCDDIS Peripheral Clock Driver also X Peripherals 1 When bit CANxDIS is cleared the CAN module is re activated by an internal reset signal and must then be re configured in order to operate properly Note The allocation of peripheral disable bits within register SYSCONS is device specific and may be different in other derivatives than the C167CS SYSCONS is write protected afte
401. lease refer to the CAN Protocol Specification 1 Bit Time Sync Sync Seg TSeg1 TSeg2 Seg A 1 time quantum Sample Point Transmit Point t MCT04393 Figure 19 4 Bit Timing Definition The bit time is determined by the XBUS clock period t XCLK the Baud Rate Prescaler and the number of time quanta per bit bit time tourna Gag TSegi lTSeg2 19 1 fsync Seg 1x Is TSEG1 1 xt hse C TSEG2 1 xt _ 1 CPS A BRP 1 x 2 bim 19 2 Note TSEG1 TSEG2 and BHP are the programmed numerical values from the respective fields of the Bit Timing Register User s Manual 19 12 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Stink Register XReg EF04 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 TSEG2 TSEG1 SJW BRP r rw rw rw rw Bit Function BRP Baud Rate Prescaler For generating the bit time quanta the CPU frequency fcpy is divided by 2 CPS x BRP 1 See also the prescaler control bit CPS in register CSR SJW Re Synchronization Jump Width Adjust the bit time by maximum SJW 1 time quanta for resynchronization TSEG1 Time Segment before sample point There are TSEG1 1 time quanta before the sample point Valid values for TSEG1 are 2 15 TSEG2 Time Segment after sample point There are TSEG2 1 time quanta after the sample poin
402. levels of PORTO Software can adjust the number of selected segment address lines via register RSTCON The CAN interface s can use 2 or 4 pins of Port 4 to interface the CAN Module s to an external transceiver In this case the number of possible segment address lines is reduced Table 7 6 summarizes the alternate functions of Port 4 depending on the number of selected segment address lines coded via bitfield SALSEL Table 7 6 Alternate Functions of Port 4 Port4 Std Function Altern Function Altern Function Altern Function Pin SALSEL 01 SALSEL 11 SALSEL 00 SALSEL 10 64 KB 256KB 1 MB 16 MB P4 0 Gen purpose IO Seg Address A16 Seg Address A16 Seg Address A16 P4 1 Gen purpose IO Seg Address A17 Seg Address A17 Seg Address A17 P4 2 Gen purpose IO Gen purpose IO Seg Address A18 Seg Address A18 P4 3 Gen purpose IO Gen purpose IO Seg Address A19 Seg Address A19 P4 4 Gen p IO or CAN Gen p IO or CAN Gen p IO or CAN S A A20 or CAN P4 5 Gen p IO or CAN Gen p IO or CAN Gen p IO or CAN S A A21 or CAN P4 6 Gen p IO or CAN Gen p IO or CAN Gen p IO or CAN S A A22 or CAN P4 7 Gen p IO or CAN Gen p IO or CAN Gen p IO or CAN S A A23 or CAN Note Port 4 pins that are neither used for segment address output nor for the CAN interface may be used for general purpose IO If more than one function is selected for a Port 4 pin the CAN inte
403. line that are executed before starting the data transfer including N User s Manual 5 23 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur the minimum PEC response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal code memory or when N is a call return trap or MOV Rn Rm data16 instruction the minimum PEC response time may additionally be extended by 2 state times during internal code memory program execution n case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the PEC response time may additionally be extended by 2 state times The worst case PEC response time during internal code memory program execution adds to 9 state times 18 TCL Any reference to external locations increases the PEC response time due to pipeline related access priorities The following conditions have to be considered e Instruction fetch from an external location Operand read from an external location e Result write back to an external location Depending on where the instructions source and destination operands are located there are a number of combinations Note however that only access conflicts contribute to the delay A few examples illustrate these delays The worst case interrupt
404. lows to put the C167CS into the well defined reset condition either at power up or external events like a hardware failure or manual reset The input voltage threshold of the RSTIN pin is raised compared to the standard pins in order to minimize the noise sensitivity of the reset input In bidirectional reset mode the C167CS s line RSTIN may be driven active by the chip logic e g in order to support external equipment which is required for startup e g flash memory Bidirectional reset reflects internal reset sources software watchdog also to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON and changes RSTIN from a pure input to an open drain IO line When an internal reset is triggered by the SRST instruction or by a watchdog timer overflow or a low level is applied to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence After that it is released and is then controlled by the external circuitry alone The bidirectional reset function is useful in applications where external devices require a defined reset signal but cannot be connected to the C167CS s RSTOUT signal e g an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT The following behavior differences must be observed when using the bi
405. ly performed ALU operation They are set by most of the instructions due to specific rules which depend on the ALU or data movement operation performed by an instruction User s Manual 4 16 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU After execution of an instruction which explicitly updates the PSW register the condition flags cannot be interpreted as described in the following because any explicit write to the PSW register supersedes the condition flag values which are implicitly generated by the CPU Explicitly reading the PSW register supplies a read value which represents the state of the PSW register after execution of the immediately preceding instruction Note After reset all of the ALU status bits are cleared N Flag For most of the ALU operations the N flag is set to 1 if the most significant bit of the result contains a 1 otherwise it is cleared In the case of integer operations the N flag can be interpreted as the sign bit of the result negative N 1 positive N 0 Negative numbers are always represented as the 2 s complement of the corresponding positive number The range of signed numbers extends from 8000 to 7FFFj for the word data type or from 804 to 7F for the byte data type For Boolean bit operations with only one operand the N flag represents the previous state of the specified bit For Boolean bit operations
406. ly when using continuous conversion modes the ADC can be switched to Wait for ADDAT Read Mode by setting bit ADWR in register ADCON If the value in ADDAT has not been read by the time the current conversion is complete the new result is stored in a temporary buffer and the next conversion is suspended ADST and ADBSY will remain set in the meantime but no end of conversion interrupt will be generated After reading the previous value from ADDAT the temporary buffer is copied into ADDAT generating an ADCIR interrupt and the suspended conversion is started This mechanism applies to both single and continuous conversion modes Note While in standard mode continuous conversions are executed at a fixed rate determined by the conversion time in Wait for ADDAT Read Mode there may be delays due to suspended conversions However this only affects the conversions if the CPU or PEC cannot keep track with the conversion rate 3 2 1 wait 0 3 Conversion of Channel Write ADDAT ADDAT Full Temp Latch Full Generate Interrupt Hold Result in Request Temp Latch Read of ADDAT Result of Channel Hy 3 2 1 0 MCA01970 Figure 18 4 Wait for Read Mode Example User s Manual 18 8 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter Channel Injection Mode Channel Injection Mode allows the conversion of a specific analog channel also while the ADC is running in a
407. m the same source to the same destination Note The reserved combination 11 is changed to 10 by hardware However it is not recommended to use this combination The PEC Transfer Count Field COUNT controls the action of a respective PEC channel where the content of bit field COUNT at the time the request is activated selects the action COUNT may allow a specified number of PEC transfers unlimited transfers or no PEC service at all Table 5 5 summarizes how the COUNT field itself the interrupt requests flag IR and the PEC channel action depends on the previous content of COUNT Table 5 5 Influence of Bitfield COUNT Previous Modified IR after PEC Action of PEC Channel COUNT COUNT Service and Comments FFy FFy 0 Move a Byte Word Continuous transfer mode i e COUNT is not modified FEy 024 FDy 014 0 Move a Byte Word and decrement COUNT O14 004 T Move a Byte Word Leave request flag set which triggers another request 004 004 1 No action Activate interrupt service routine rather than PEC channel The PEC transfer counter allows to service a specified number of requests by the respective PEC channel and then when COUNT reaches 00 4 activate the interrupt service routine which is associated with the priority level After each PEC transfer the COUNT field is decremented and the request flag is cleared to indicate that the request has been serviced User s
408. me PB2 B 0 1us 2x 13x1gs 0 2us tolerance for fci 0 3996 Bit Timing Example for Low Baudrate This example makes the following assumptions e XCLK frequency 4 MHz e BRP 01 CPS 0 e Baudrate 100 kbit sec de 1 us 4 X tycLk bus driver delay 200 ns receiver circuit delay 80 ns bus line 40 m delay 220 ns TSuw 4 us 4Xlq fTSegt 5 US Iprop fsJw tTSeg2 4 us Information Processing Time 2 x tq Bit 10uS fSync frSegi frSeg2 i min PBi PB2 toleranceforfxcik 1 58 5773 x bit time PB2 _ __4us__ 2x 13 x 10us 4us User s Manual 19 15 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 2 3 Mask Registers Messages can use standard or extended identifiers Incoming frames are masked with their appropriate global masks Bit IDE of the incoming message determines if the standard 11 bit mask in Global Mask Short GMS is to be used or the 29 bit extended mask in Global Mask Long UGML amp LGML Bits holding a 0 mean don t care i e do not compare the messages identifier in the respective bit position The last message object 15 has an additional individually programmable acceptance mask Mask of Last Message UMLM amp LMLM for the complete arbitration field This allows classes of messages to be received in this object by masking some bits of the identifier Note The Mask of Last Message is ANDed with the Global Mask tha
409. me hints on how to optimize time critical program parts with regard to such pipeline caused timing particularities User s Manual 4 9 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU 4 3 Bit Handling and Bit Protection The C167CS provides several mechanisms to manipulate bits These mechanisms either manipulate software flags within the internal RAM control on chip peripherals via control bits in their respective SFRs or control IO functions via port pins The instructions BSET BCLR BAND BOR BXOR BMOV BMOVN explicitly set or clear specific bits The instructions BFLDL and BFLDH allow to manipulate up to 8 bits of a specific byte at one time The instructions JBC and JNBS implicitly clear or set the specified bit when the jump is taken The instructions JB and JNB also conditional jump instructions that refer to flags evaluate the specified bit to determine if the jump is to be taken Note Bit operations on undefined bit locations will always read a bit value of 0 while the write access will not effect the respective bit location All instructions that manipulate single bits or bit groups internally use a read modify write sequence that accesses the whole word which contains the specified bit s This method has several consequences Bits can only be modified within the internal address areas i e internal RAM and SFRs External locations cannot be used with bit instructions
410. ment Special operating modes to deactivate CPU ports and control logic Idle Sleep Power Down This enables the application i e the programmer to choose the optimum constellation for each operating condition so the power consumption can be adapted to conditions like maximum performance partial performance intermittend operation or standby Power No of act Peripherals MCA04476 Figure 21 1 Power Reduction Possibilities User s Manual 21 1 V2 0 2000 07 o nfineon e technologies Derivatives Power Management Intermittend operation i e alternating phases of high performance and power saving is supported by the cyclic interrupt generation mode of the on chip RTC real time clock These three means described above can be applied independent from each other and thus provide a maximum of flexibility for each application For the basic power reduction modes ldle Power Down there are dedicated instructions while special registers control Sleep mode SYSCONY 1 clock generation SYSCON2 and peripheral management SYSCONS3 Three different general power reduction modes with different levels of power reduction have been implemented in the C167C S which may be entered under software control In Idle Mode the CPU is stopped while the enabled peripherals continue their operation Idle mode can be terminated by any reset or interrupt request In Sleep Mode both the CPU and the peripheral
411. ment Address Lines SALSEL Segment Address Lines Directly accessible Address Space 11 Two A17 A16 256 KByte Default without pull downs 10 Eight A23 A16 16 MByte Maximum 0 1 None 64 KByte Minimum 00 Four A19 A16 1 MByte Note The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select lines If Port 4 is used to output segment address lines in most cases the drivers must operate in push pull mode Make sure that OPD4 does not select open drain mode in this case User s Manual 9 9 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface cs Signal Generation During external accesses the EBC can generate a programmable number of CS lines on Port 6 which allow to directly select external peripherals or memory banks without requiring an external decoder The number of CS lines is selected during reset and coded in bit field CSSEL in register RPOH see Table 9 4 Table 9 4 Decoding of Chip Select Lines CSSEL Chip Select Lines Note 11 Five CS4 CS0 Default without pull downs 10 None Port 6 pins free for IO 0 1 Two CS1 CS0 00 Three CS2 CS0 The CSx outputs are associated with the BUSCONx registers and are driven active low for any access within the address area defined for the respective BUSCON register For any access outside this defined addre
412. ment hardware It also has the benefit of increasing the range for relative branching instructions The high performance offered by the hardware implementation of the CPU can efficiently be utilized by a programmer via the highly functional C167CS instruction set which includes the following instruction classes Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructions Return Instructions System Control Instructions Miscellaneous Instructions Possible operand types are bits bytes and words Specific instruction support the conversion extension of bytes to words A variety of direct indirect or immediate addressing modes are provided to specify the required operands User s Manual 2 6 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview 2 1 2 Programmable Multiple Priority Interrupt System The following enhancements have been included to allow processing of a large number of interrupt sources 1 Peripheral Event Controller PEC This processor is used to off load many interrupt requests from the CPU It avoids the overhead of entering and exiting interrupt or trap routines by performing single cycle interrupt driven byte or word data transfers between any two locations in segment 0 with an option
413. mer 5 ext Up Down Input P5 12 Analog Input AN12 T6IN Timer 6 Count Input P5 13 Analog Input AN13 T5IN Timer 5 Count Input P5 14 Analog Input AN14 T4EUD Timer 4 ext Up Down Input P5 15 Analog Input AN15 T2EUD Timer 2 ext Up Down Input Alternate Function a b P5 15 P5 14 P5 13 P5 12 P5 11 P5 10 P5 9 P5 8 P5 7 P5 6 P5 5 P5 4 P5 3 P5 2 P5 1 P5 0 Port 5 General Purpose Input AN15 AN14 AN13 AN12 AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 ANO A D Converter Input Input T2bEUD T4EUD T5IN T6IN T5EUD T6EUD Timer Control MCA04356 Figure 7 19 Port 51O and Alternate Functions User s Manual 7 39 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Port 5 Digital Input Control Port 5 pins may be used for both digital an analog input By setting the respective bit in register P5DIDIS the digital input stage of the respective Port 5 pin can be disconnected from the pin This is recommended when the pin is to be used as analog input as it reduces the current through the digital input stage and prevents it from toggling while the analog input level is between the digital low and high thresholds So the consumed power and the generated noise can be reduced After reset all digital inputs are enabled P5DIDIS Port 5 Digital Inp Disable Reg SFR FFA4 D2 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P5D
414. mer start value PTx and the pulse width value PWx appropriately the pulse width tw and the optional pulse delay td may be varied in a wide range User s Manual 17 8 V2 0 2000 07 technologies C167CS Derivatives The Pulse Width Modulation Module PPX Period 7 PTx Count Value PWx Pulse Width 4 PPx Period 7 PTx Count Value PWx Pulse Width 4 Set PTRx by LSR Set PTRx by LSR Software PTRx Reset by Software for Hardware Next Pulse PTx stopped NENNEN Retrigger after Pulse has started Write PWx Trigger before Pulse has started Write PWx value value to PTx to PTx Shortens Delay Time tp MCA01952 Figure 17 6 Operation and Output Waveform in Single Shot Mode User s Manual 17 9 V2 0 2000 07 o nfineon en technologies Derivatives The Pulse Width Modulation Module 17 2 PWM Module Registers The PWM module is controlled via two sets of registers The waveforms are selected by the channel specific registers PTx timer PPx period and PWx pulse width Three common registers control the operating modes and the general functions PWMCONO and PWMCON 1 of the PWM module as well as the interrupt behavior PWMIC Up Down Counters PTx Each counter PTx of a PWM channel is clocked either directly with fcpy or with fcpy 64 Bit PTIx in register PWMCONO selects the respective clock source A PWM counter
415. n The duration of an external write access can be shortened by one TCL The WR signal is activated driven low in the standard way but can be deactivated driven high one TCL earlier than defined in the standard timing In this case also the data output drivers will be deactivated one TCL earlier This is especially useful in systems which operate on higher CPU clock frequencies and employ external modules memories peripherals etc which switch on their own data drivers very fast in response to e g a chip select signal Conflicts between the C167CS s and the external peripheral s output drivers can be avoided then by selecting early WR for the C167CS Note Make sure that the reduced WR low time then still matches the requirements of the external peripheral memory Early WR deactivation is controlled via the EWENx bits in the BUSCON registers The WR signal will be shortened if bit EWENx is 1 default after reset is a standard WR signal i e EWENx 0 User s Manual 9 16 V2 0 2000 07 technologies C167CS Derivatives The External Bus Interface Segment ALE BUS PO Bus Cycle Address Data Instr NN nmn yt OK The data drivers from the previous bus cycle should be disabled when the RD signal becomes active N Read Write Delay r8 1 2 Data drivers are disabled in an early write cycle 3 Data drivers are disabled in a demultiplexed normal write
416. n 4 30 22 1 N NMI 5 1 5 34 Noise filter Ext Interrupts 5 30 O ODP2 7 24 7 43 7 49 ODP3 7 29 ODP4 7 34 ODP8 7 54 ONES 4 33 Open Drain Mode 7 4 Oscillator circuitry 6 2 measurement 6 2 Watchdog 6 8 20 19 P POL POH 7 12 P1DIDS 7 19 P1L P1H 7 16 P2 7 23 P3 7 28 P4 7 33 7 42 7 48 P5 7 38 P5DIDIS 7 40 P8 7 53 User s Manual Keyword Index PCIR 19 11 PEC 2 8 3 7 5 12 Response Times 5 23 PECOx 5 12 Peripheral enable on XBUS 9 38 Enable Disable 21 14 Management 21 14 Summary 2 11 Phase Locked Loop gt PLL 6 1 PICON 7 2 Pins 8 1 25 2 in Idle and Power Down mode 21 9 Pipeline 4 3 Effects 4 6 PLL 6 1 20 19 POCONx 7 7 Port 2 14 driver characteristic 7 5 edge characteristic 7 6 input threshold 7 2 Power Down Mode 21 6 Power Management 2 18 21 1 Prescaler 6 6 Protected Bits 2 19 4 10 instruction 24 4 PSW 4 16 5 10 Pulse Width Modulation 2 17 PWM 2 17 PWM Module 17 1 PWMCONO 17 12 PWMCON 17 13 PWMIC 17 14 R RAM extension 3 9 internal 3 4 Read Write Delay 9 16 READY 9 18 Real Time Clock gt RTC 14 1 Registers 23 1 26 4 V2 0 2000 07 o nfineon technologies C167CS Derivatives sorted by address 23 14 sorted by name 23 4 Reserved bits 2 12 Reset 20 1 Bidirectional 20 4 Configuration 20 7 20 12 Hardware 20 2 Output 20 8 Software 20 3 Source indication 13 6 Values 20 5 Watchdog Timer 20 3 RSTCON 20 23 RTC 2 15 14 1 S SOBG 11 11 SOCON 11
417. n ed technologies Derivatives System Programming 22 System Programming To aid in software development a number of features has been incorporated into the instruction set of the C167CS including constructs for modularity loops and context switching In many cases commonly used instruction sequences have been simplified while providing greater flexibility The following programming features help to fully utilize this instruction set Instructions Provided as Subsets of Instructions In many cases instructions found in other microcontrollers are provided as subsets of more powerful instructions in the C167CS This allows the same functionality to be provided while decreasing the hardware required and decreasing decode complexity In order to aid assembly programming these instructions familiar from other microcontrollers can be built in macros thus providing the same names Directly Substitutable Instructions are instructions known from other microcontrollers that can be replaced by the following instructions of the C167CS Table 22 1 Substitution of Instructions Substituted Instruction C167CS Instruction Function CLR Rn AND Rn 04 Clear register CPLB Bit BMOVN Bit Bit Complement bit DEC Rn SUB Rn 14 Decrement register INC Rn ADD Rn 14 Increment register SWAPB Rn ROR Hn 84 Swap bytes within word Modification of System Flags is performed using bit set or bit clear instructions BSET BCLR
418. n ed technologies Derivatives System Reset Single Chip Startup Modes The startup mode operation after reset of the C167CS can be configured during reset In single chip mode this configuration is selected via pins RD and ALE Pin RD selects start or boot mode instead of OWD control pin ALE selects one of two alternatives in each case Table 20 8 Startup Mode Configuration in Single Chip Reset Mode RD ALE Startup Mode Notes 1 0 Standard Start Execution starts at user memory location 00 0000 1 1 Alternate Start Operation not yet defined Do not use 0 0 Standard Bootstrap Load 32 bytes via ASCO Loader 0 1 Alternate Boot Mode Operation not yet defined Do not use User s Manual 20 21 V2 0 2000 07 o nfineon e technologies Derivatives System Reset 20 5 System Configuration via Software The system configuration which is selected via hardware after reset latched pin levels or default value can be changed via software by executing a specific code sequence The respective control bits are located within registers SYSCON BUSCONx and RSTCON Register SYSCON can only be modified before the execution of instruction EINIT while registers BUSCONx and RSTCON using the specific sequence can be modified repeatedly at any time The clock generation mode CLKCFG the segment address width SALSEL and the number of chip select lines CSSEL are controlled by register RPOH RPOH is initiali
419. n interrupt only mode which can be used for software timing purposes Compare mode 0 is selected for a given compare register CCx by setting bit field CCMODx of the corresponding mode control register to 100p In this mode the interrupt request flag CCxIR is set each time a match is detected between the content of compare register CCx and the allocated timer Several of these compare events are possible within a single timer period when the compare value in register CCx is updated during the timer period The corresponding port pin CCxIO is not affected by compare events in this mode and can be used as general purpose IO pin If compare mode 0 is programmed for one of the registers CC8 CC15 or CC24 CC31 the double register compare mode becomes enabled for this register if the corresponding bank 1 register is programmed to compare mode 1 see Double Register Compare Mode on Page 16 19 1 Compare events are detected sequentially where a sequence checking 8 times 2 channels each takes 8 CPU clock cycles Even if more sequences are executed before the timer increments lower timer frequency a given compare value only results in one single compare event Users Manual 16 14 V2 0 2000 07 C167CS Derivatives technologies The Capture Compare Units Interrupt Request gt Toggle Mode 1 Interrupt Request Xx 31 0 not for CC27 CC24 y 0 1 7 8 MCB02016 Figure 16 6 Compa
420. n multiplexed bus modes ALE is activated for every external bus cycle independent of the selected bus mode i e itis also activated for bus cycles with a demultiplexed address bus When an external bus is enabled one or more of the BUSACT bits set also X Peripheral accesses will generate an active ALE signal ALE is not activated for internal accesses i e accesses to ROM OTP Flash if provided the internal RAM and the special function registers In single chip mode i e when no external bus is enabled no BUSACT bit set ALE will also remain inactive for X Peripheral accesses During reset an internal pulldown ensures an inactive low level on the ALE output User s Manual 8 1 V2 0 2000 07 o nfineon e technologies Derivatives Dedicated Pins At the end of a true single chip mode reset EA 1 the current level on pin ALE is latched and is used for configuration together with pin RD Pin ALE selects standard start boot when driven low default or alternate start boot when driven high For standard configuration pin ALE should be low or not connected The External Read Strobe RD controls the output drivers of external memory or peripherals when the C167CS reads data from these external devices During accesses to on chip X Peripherals RD remains inactive high EE During reset an internal pullup ensures an inactive high level on the RD output At the end of reset the current level on pin RD is latched and
421. n the execute phase of the respective instructions In order to maintain fast interrupt responses however the current interrupt prioritization round does not consider these changes i e an interrupt request may be acknowledged after the instruction that disables interrupts via IEN or ILVL or after the following instructions Timecritical instruction sequences therefore should not begin directly after the instruction disabling interrupts as shown in the following examples INTERRUPTS OFF BCLR IEN globally disable interrupts lt Instr non crit gt non critical instruction Instr lst crit gt begin of uninterruptable critical sequence Instr last crit end of uninterruptable critical sequence INTERRUPTS ON BSET IEN globally re enable interrupts CRITICAL SEQUENCE ATOMIC 3 immediately block interrupts BCLR IEN globally disable interrupts ssi here is the uninterruptable sequence BSET IEN globally re enable interrupts Note The described delay of 1 instruction also applies for enabling the interrupts system ie no interrupt requests are acknowledged until the instruction following the enabling instruction User s Manual 4 7 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU External Memory Access Sequences The effect described here will only become noticeable when watching the external memory access sequences on the external bus e g by means of a Logic Anal
422. nal reset EA 0 Pin POL 1 is not evaluated upon a single chip reset EA 1 User s Manual 20 15 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Special Operation Modes Pins POL 5 to POL 2 SMOD select special operation modes of the C167CS during reset see Table 20 2 Make sure to only select valid configurations in order to ensure proper operation of the C167CS Table 20 2 Definition of Special Modes for Reset Configuration P0 5 2 POL 5 2 Special Mode Notes 1111 Normal Start Default configuration Begin of execution as defined via pin EA 1110 Reserved Do not select this configuration 110 1 Reserved Do not select this configuration 1100 Reserved Do not select this configuration 101 1 Standard Bootstrap Load an initial boot routine of 32 Bytes via Loader interface ASCO 1010 Reserved Do not select this configuration 1001 Alternate Boot Operation not yet defined Do not use 1000 Reserved Do not select this configuration 0111 No emulation mode Operation not yet defined Do not use Alternate Start Emulation mode Programming mode for Flash memory via External Host Mode external host EHM 0110 Reserved Do not select this configuration 0101 Reserved Do not select this configuration 0100 Reserved Do not select this configuration 00 XX Reserved Do not select this configuration The On Chip Bootstrap Loader allows mov
423. nal transition will set the interrupt request flag Cl 10g selects a negative transition to set the interrupt request flag and with Cl 11g both a positive and a negative transition will set the request flag When the interrupt enable bit CRIE is set an interrupt request for vector CRINT or a PEC request will be generated Note The non maskable interrupt input pin NMI sample rate 2 TCL and the reset input ASTIN provide another possibility for the CPU to react on an external input signal NMI and RSTIN are dedicated input pins which cause hardware traps User s Manual 5 27 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions Fast External Interrupts The input pins that may be used for external interrupts are sampled every 16 TCL i e external events are scanned and detected in timeframes of 16 TCL 8 TCL for CAPIN The C167CS provides 8 interrupt inputs that are sampled every 2 TCL so external events are captured faster than with standard interrupt inputs The upper 8 pins of Port 2 P2 15 P2 8 can individually be programmed to this fast interrupt mode where also the trigger transition rising falling or both can be selected The External Interrupt Control register EXICON controls this feature for all 8 pins EXICON Ext Interrupt Control Reg ESFR F1C0 E0 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXI7ES EXI6ES EXI5ES EXI4ES EXI3ES EXI2ES EXHES EXIOES
424. ncorrect 7 Unused code may be written by the CPU to check for updates TXOK Transmitted Message Successfully Indicates that a message has been transmitted successfully error free and acknowledged by at least one other node since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK Received Message Successfully This bit is set each time a message has been received successfully since this bit was last reset by the CPU the CAN controller does not reset this bit RXOK is also set when a message is received that is not accepted i e stored EWRN Error Warning Status Indicates that at least one of the error counters in the EML has reached the error warning limit of 96 BOFF Busoff Status Indicates when the CAN controller is in busoff state see EML Note Reading the upper half of the Control Register status partition will clear the Status Change Interrupt value in the Interrupt Register if it is pending Use byte accesses to the lower half to avoid this User s Manual 19 9 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 2 1 CAN Interrupt Handling The on chip CAN module has one interrupt output which is connected through a synchronization stage to a standard interrupt node in the C167CS in the same manner as all other interrupts of the standard on chip peripherals With this configuration the user has all control opt
425. nctions T5CON T6CON P5DIDIS T5IN P5 13 TS5EUD P5 11 T6IN P5 12 T6EUD P5 10 CAPIN P3 2 TeOUT P3 1 ODP3 Port 3 Open Drain Control Register T5 GPT2 Timer 5 Register DP3 Port 3 Direction Control Register T6 GPT2 Timer 6 Register P3 Port 3 Data Register CAPRELGPT2 Capture Reload Register P5 Port 5 Data Register T5ICGPT2 Timer 5 Interrupt Control Register P5DIDIS Port 5 Digital Input Disable Register T6ICGPT2 Timer 6 Interrupt Control Register T5CONGPT2 Timer 5 Control Register CRICGPT2 CAPREL Interrupt Control Register T6CONGPT2_ Timer 6 Control Register MCA04375 Figure 10 15 SFRs and Port Pins Associated with Timer Block GPT2 Timer block GPT2 supports high precision event control with a maximum resolution of 8 TCL It includes the two timers T5 and T6 and the 16 bit capture reload register CAPREL Timer T6 is referred to as the core timer and T5 is referred to as the auxiliary timer of GPT2 Each timer has an alternate input function pin associated with it which serves as the gate control in gated timer mode or as the count input in counter mode The count direction Up Down may be programmed via software An overflow underflow of T6 is indicated by the output toggle bit TEOTL whose state may be output on an alternate function port pin T6OUT In addition T6 may be reloaded with the contents of CAPREL The toggle bit also supports the concatenation of T6 with auxiliary timer T5 while concatenation of T6 with
426. ndary of the external stack These values are then tested in the stack underflow and overflow trap routines when moving data e Set the stack overflow pointer STKOV to the limit of the defined internal stack area plus six words for the reserved space to store two interrupt entries The internal stack will now fill until the overflow pointer is reached After entry into the overflow trap procedure the top of the stack will be copied to the external memory The internal pointers will then be modified to reflect the newly allocated space After exiting from the trap procedure the internal stack will wrap around to the top of the internal stack and continue to grow until the new value of the stack overflow pointer is reached When the underflow pointer is reached while the stack is meptied the bottom of stack is reloaded from the external memory and the internal pointers are adjusted accordingly User s Manual 22 7 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming Linear Stack The C167CS also offers a linear stack option STKSZ 111p where the system stack may use the complete internal RAM area This provides a large system stack without requiring procedures to handle data transfers for a circular stack However this method also leaves less RAM space for variables or code The RAM area that may effectively be consumed by the system stack is defined via the STKUN and STKOV pointers The underflow and
427. nderflow This means the value in register CAPREL represents the time between two underflows of timer T6 now measured in timer T6 increments Since timer T6 runs 8 times faster than timer T5 it will underflow 8 times within the time between two external events Thus the underflow signal of timer T6 generates 8 ticks Upon each underflow the interrupt request flag T6IR will be set and bit T6OTL will be toggled The state of TEOTL may be output on pin T6OUT This signal has 8 times more transitions than the signal which is applied to pin CAPIN The underflow signal of timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units which gives the user the possibility to set compare events based on a finer resolution than that of the external events User s Manual 10 37 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units 10 2 3 Interrupt Control for GPT2 Timers and CAPREL When a timer overflows from FFFF to 0000 when counting up or when it underflows from 0000 to FFFFy when counting down its interrupt request flag T5IR or T6IR in register TxIC will be set Whenever a transition according to the selection in bit field CI is detected at pin CAPIN interrupt request flag CRIR in register CRIC is set Setting any request flag will cause an interrupt to the respective timer or CAPREL interrupt vector TSINT T6INT or CRINT or trigger a PEC service if the respective
428. neral Purpose Byte Reg RHO UU HL 1 CP 2 F2y CPU General Purpose Byte Reg RL1 UU RH1 CP 3 F3y CPU General Purpose Byte Reg RH1 UUyH RL2 CP 4 F4y CPU General Purpose Byte Reg RL2 UU RH2 CP 5 F5 CPU General Purpose Byte Reg RH2 UU RL3 CP 6 F6y CPU General Purpose Byte Reg RL3 UUy RH3 CP 7 F7y CPU General Purpose Byte Reg RH3 UU RL4 CP 8 F8y CPU General Purpose Byte Reg RL4 UUy RH4 CP 9 F9y CPU General Purpose Byte Reg RH4 UUyH RL5 CP 10 FAQ CPU General Purpose Byte Reg RL5 UUy RH5 CP 11 FBy CPU General Purpose Byte Reg RH5 UU RL6 CP 12 FO CPU General Purpose Byte Reg RL6 UUy RH6 CP 13 FDy CPU General Purpose Byte Reg RH6 UU RL7 CP 14 FE CPU General Purpose Byte Reg RL7 UU HH7 CP 15 FFy CPU General Purpose Byte Reg RH7 UU User s Manual 23 3 V2 0 2000 07 o nfineon ed technologies Derivatives The Register Set 23 3 Special Function Registers Ordered by Name Table 23 3 lists all SFRs which are implemented in the C167CS in alphabetical order Bit addressable SFRs are marked with the letter b in column Name SFRs within the extended SFR space ESFRs are marked with the letter E in column Physical Address Registers within on chip X Peripherals are marked with the letter X in column Physical Address Table 23 3 C167CS Registers Or
429. nfiguration and control functions The reset value for register SYSCON depends on the state of the PORTO pins during reset see hardware effectable bits SYSCON System Control Register SFR FF12 894 Reset Value OXX0 15 14 13 12 11 10 9 8 7 6 5 4 38 2 1 0 STKSZ ROM SGT ROM BYT CLK WR CS ud BST XP VISI XPER S1 DIS EN DIS EN CFG CFG DIS EN EN BLE SHARE rw rw rw mwh rwh rw rwh rw wh rw rw rw rw Bit Function XPER SHARE XBUS Peripheral Share Mode Control 0 External accesses to XBUS peripherals are disabled 1 XBUS peripherals are accessible via the external bus during hold mode VISIBLE Visible Mode Control 0 Accesses to XBUS peripherals are done internally 1 XBUS peripheral accesses are made visible on the external pins XPEN XBUS Peripheral Enable Bit 0 Accesses to the on chip X Peripherals and their functions are disabled 1 The on chip X Peripherals are enabled and can be accessed BDRSTEN Bidirectional Reset Enable Bit 0 Pin RSTIN is an input only 1 Pin RSTIN is pulled low during the internal reset sequence after any reset OWDDIS Oscillator Watchdog Disable Bit Depending on reset configuration 0 The on chip oscillator watchdog is enabled and active 1 The on chip oscillator watchdog is disabled and the CPU clock is always fed from the oscillator input CSCFG Chip Select Configuration Control Cleared afte
430. nfineon technologies C167CS Derivatives Parallel Ports Internal Bus P1H 7 4 CCx 2 on Ser Port Output Direction Latch Latch e AltDir AItEN AltDataOut Driver AltDatalN Latch Clock lt j AltDatalN Pin 4 e Input Latch MCD04467 Figure 7 9 Block Diagram of a PORT1 Pin with Address and CAPCOM Function User s Manual 7 20 V2 0 2000 07 j e e Infineon technologies C167CS Derivatives Parallel Ports Internal Bus gt o o P EC Port Output Direction Latch Latch e AltDir 1 1 AItEN r Pin AltDataOut XJ Driver Clock Input Latch MCB04348 P1H 3 0 Figure 7 10 Block Diagram of a PORT1 Pin with Address Function User s Manual 7 21 V2 0 2000 07 eo Infineon technologies C167CS Derivatives Parallel Ports Internal Bus i o o o o 9 o Ec zc Port Output Direction Latch Latch AltDir 1 1 AItEN 0 AtDataOut Pho Driver Pin DiglnputEN Clock 9 ChannelSelect Input Latch Analoglnput lt MCD04468 P1L 7 0 Figure 7 11 Block Diagram of a PORT1 Pin with Address and Analog Input Function Users Manual 7 22 V2 0 2000 07 d nfineon ed technologies Derivatives Parallel Ports 7 6 Port 2 If this 16 bit port is
431. ng a certain CPU clock are listed in Table 16 2 Table 16 4 The numbers for the timer periods are based on a reload value of 0000 Note that some numbers may be rounded to 3 significant digits User s Manual 16 6 V2 0 2000 07 d nfineon ed technologies Derivatives The Capture Compare Units Table 16 2 Timer Input Frequencies Resolution and Period 2 20 MHz fcpu 20 MHz Timer Input Selection Txl 000g 001g 010 011g 100g 101g 110g 111g Prescaler 1 N 8 16 32 64 128 256 512 1024 Input Frequency 2 5 1 25 625 312 5 156 25 78 125 39 06 19 53 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 400 800 1 6 3 2 6 4 12 8 25 6 51 2 ns ns us us us us us us Period 26 52 5 105 210 420 840 1 68 3 36 ms ms ms ms ms ms S S Table 16 3 Timer Input Frequencies Resolution and Period 2 25 MHz fcpu 25 MHz Timer Input Selection Txl 000g 001g 010g 011g 1008s 101g 110g 111g Prescaler 1 N 8 16 32 64 128 256 512 1024 Input Frequency 3 125 1 563 781 25 390 63 195 31 97 656 48 828 24 414 MHz MHz kHz kHz kHz kHz kHz kHz Resolution 320 640 1 28 2 56 5 12 10 24 20 48 40 96 ns ns us us us us us us Period 21 42 84 168 336 672 1 344 2 688 ms ms ms ms ms ms S S Table 16 4 Timer Input Frequencies Resolution and Period 33 MHz fcpu 33 MHz Timer Input Selection Txl 000g 001 010 Olis 1008s 101 11
432. nologies C167CS Derivatives The Capture Compare Units GPT2 Timer T6 Over Underflow coxo 16 Capture Inputs 16 Compare Outputs COxO Tx Input CAPCOM Timer Tx Control Mode Control Capture Reload Reg TxREL Interrupt Request 16 Bit Compare Registers Capture 16 Capture Compare Interrupt Request foru Interrupt GPT2 Timer T6 Control Set Over Underflow X 2 0 1 D n 3 10 Reload Reg TyREL Figure 16 2 CAPCOM Unit Block Diagram Table 16 1 CAPCOM Channel Port Connections Unit Channel Port Capture Compare CAPCOM 1 CCOIO CC15IO P2 0 P2 15 Input Output CAPCOM2 CC16lO CC23lO P8 0 P8 7 Input Output CC24IO CC27IO P1H 4 P1H 7 Input Output CC28lO CC31IO P7 4 P7 7 Input Output X292 X 32 y 32 i Bg User s Manual 16 3 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units 16 1 The CAPCOM Timers The primary use of the timers TO T1 and T7 T8 is to provide two independent time bases 16 TCL maximum resolution for the capture compare registers of each unit but they may also be used independent of the capture compare registers The basic structure of the four timers is identical while the selection of input signals is different for timers TO T7 and timers T1 T8 see Figure 16 3 and Figure 16 4
433. nput The output of the slaves shift register is connected to the external receive line in order to enable the master to receive the data shifted out of the slave The external connections are hard wired the function and direction of these pins is determined by the master or slave operation of the individual device Note The shift direction shown in Figure 12 4 applies for MSB first operation as well as for LSB first operation When initializing the devices in this configuration select one device for master operation SSCMS 1 all others must be programmed for slave operation SSCMS 0 Initialization includes the operating mode of the device s SSC and also the function of the respective port lines see Chapter 12 4 Master Device 1 Device 2 Slave Shift Register Shift Register Device 3 Slave MCS01963 Figure 12 4 SSC Full Duplex Configuration User s Manual 12 7 V2 0 2000 07 d nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface The data output pins MRST of all slave devices are connected together onto the one receive line in this configuration During a transfer each slave shifts out data from its shift register There are two ways to avoid collisions on the receive line due to different slave data Only one slave drives the line i e enables the driver of its MRST pin All the other slaves have to program their MRST pi
434. ns to input So only one slave can put its data onto the master s receive line Only receiving of data from the master is possible The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave The selected slave then switches its MRST line to output until it gets a deselection signal or command The slaves use open drain output on MRST This forms a Wired AND connection The receive line needs an external pullup in this case Corruption of the data on the receive line sent by the selected slave is avoided when all slaves which are not selected for transmission to the master only send ones 1 Since this high level is not actively driven onto the line but only held through the pullup device the selected slave can pull this line actively to a low level when transmitting a zero bit The master selects the slave device from which it expects data either by separate select lines or by sending a special command to this slave After performing all necessary initializations of the SSC the serial interfaces can be enabled For a master device the alternate clock line will now go to its programmed polarity The alternate data line will go to either 0 or 1 until the first transfer will start When the serial interfaces are enabled the master device can initiate the first data transfer by writing the transmit data into register SSCTB This value is copied in
435. nstruction the CSP register is automatically set to zero User s Manual 4 20 V2 0 2000 07 d Infineon Miis technologies Derivatives The Central Processing Unit CPU CSP Register IP Register Code Segment 15 0 15 0 FFFFFF y FE 0000 H l l 0100009 24 20 18 Bit Physical Code Address 0000001 A A MCA02265 Figure 4 5 Addressing via the Code Segment Pointer Note When segmentation is disabled the IP value is used directly as the 16 bit address Users Manual 4 21 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Data Page Pointers DPPO DPP1 DPP2 DPP3 The Central Processing Unit CPU These four non bit addressable registers select up to four different data pages being active simultaneously at run time The lower 10 bits of each DPP register select one of the 1024 possible 16 KByte data pages while the upper 6 bits are reserved for future use The DPP registers allow to access the entire memory space in pages of 16 KBytes each DPPO Data Page Pointer 0 SFR FE00 00 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 a DPPOPN rw DPP1 Data Page Pointer 1 SFR FE02 01 Reset Value 0001 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
436. nt Pointer CSP This non bit addressable register selects the code segment being used at run time to access instructions The lower 8 bits of register CSP select one of up to 256 segments of 64 KBytes each while the upper 8 bits are reserved for future use Es Segment Pointer SFR FE08 0441 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 f f f f fo fe fe SEGNR r w h Bit Function SEGNR Segment Number Specifies the code segment from where the current instruction is to be fetched SEGNR is ignored when segmentation is disabled Code memory addresses are generated by directly extending the 16 bit contents of the IP register by the contents of the CSP register as shown in Figure 4 5 In case of the segmented memory mode the selected number of segment address bits via bitfield SALSEL of register CSP is output on the respective segment address pins of Port 4 for all external code accesses For non segmented memory mode or Single Chip Mode the content of this register is not significant because all code accesses are automatically restricted to segment 0 Note The CSP register can only be read but not written by data operations It is however modified either directly by means of the JMPS and CALLS instructions or indirectly via the stack by means of the RETS and RETI instructions Upon the acceptance of an interrupt or the execution of a software TRAP i
437. nternal RAM IRAM organized as X x 16 and to two 512 Byte blocks of Special Function Registers SFRs The C167CS provides 3 KByte of IRAM OO FFFF OOFFFF IRAM SFR SFR Area 00 F000 X Peripherals XRAM IRAM 00 E000 vee XRAM 00 F200 ESFR Area 00 F000 CAN1 00 EFO0 CAN2 00 EEO0 Reserved 00 E7FF XRAM Data Page 3 Data Page 2 Ext Memory Note New XBUS peripherals will be preferably placed into the shaded areas which now access external memory bus cycles executed 00 8000 00 E000 MCA04424 Figure 3 3 System Memory Map User s Manual 3 4 V2 0 2000 07 o nfineon ed technologies Derivatives Memory Organization Note The upper 256 Bytes of SFR area ESFR area and internal RAM are bit addressable see shaded blocks in Figure 3 3 Code accesses are always made on even byte addresses The highest possible code storage location in the internal RAM is either O0 FDFEj for single word instructions or 00 FDFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal RAM to the SFR area is not supported and causes erroneous results Any word and byte data in the internal RAM can be accessed via indirect or long 16 bit addressing modes if the selected DPP register points to data page 3 Any word data access is made on an even byte address The highes
438. o other instruction will enter the pipeline except the one that follows the ATOMIC instruction and no interrupt request will be serviced in between All instructions requiring multiple cycles or hold states are regarded as one instruction in this sense e g MUL is one instruction Any instruction type can be used within an unseparable code sequence ATOMIC 43 The next 3 instr are locked No NOP requ MOV RO 1234H Instr 1 no other instr enters pipeline MOV R1 45678H Instr 2 MUL RO R1 Instr 3 MUL regarded as one instruction MOV R2 MDL This instruction is out of the scope j Of the ATOMIC instruction sequence Note As long as any Class B trap is pending any of the class B trap flags in register TFR is set the ATOMIC instruction will not work Clear the respective B trap flag at the beginning of a B trap routine if ATOMIC shall be used within the routine 22 9 Overriding the DPP Addressing Mechanism The standard mechanism to access data locations uses one of the four data page pointers DPPx which selects a 16 KByte data page and a 14 bit offset within this data page The four DPPs allow immediate access to up to 64 KByte of data In applications with big data arrays especially in HLL applications using large memory models this may require frequent reloading of the DPPs even for single accesses User s Manual 22 14 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming
439. o the CPU now executes on the new level If a multiplication or division was in progress at the time the interrupt request was acknowledged bit MULIP in register PSW is set to 1 In this case the return location that is saved on the stack is not the next instruction in the instruction flow but rather the multiply or divide instruction itself as this instruction has been interrupted and will be completed after returning from the service routine High Status of Addresses Interrupted Task um dE mE am e e Low Addresses a System Stack before b System Stack after b System Stack after Interrupt Entry Interrupt Entry Interrupt Entry Unsegmented Segmented MCD02226 Figure 5 3 Task Status Saved on the System Stack The interrupt request flag of the source that is being serviced is cleared The IP is loaded with the vector associated with the requesting source the CSP is cleared in case of segmentation and the first instruction of the service routine is fetched from the respective vector location which is expected to branch to the service routine itself The data page pointers and the context pointer are not affected When the interrupt service routine is left RETI is executed the status information is popped from the system stack in the reverse order taking into account the value of bit SGTDIS User s Manual 5 18 V2 0 2000 07 j d nfineon ed technologies Derivatives Interrupt and Tra
440. of Core Timer T6 in Timer Mode User s Manual 10 26 V2 0 2000 07 _ d nfineon ed technologies Derivatives The General Purpose Timer Units The timer input frequencies resolution and periods which result from the selected prescaler option are listed in Table 10 10 This table also applies to the gated timer mode of T6 and to the auxiliary timer T5 in timer and gated timer mode Note that some numbers may be rounded to 3 significant digits Table 10 10 GPT2 Timer Input Frequencies Resolution and Periods 20 MHz fcpu 20 MHz Timer Input Selection T5I T6l 0008 001g 010 011g 1008 101g 1108 111g Prescaler 4 8 16 32 64 128 256 512 Factor Input 5 2 5 1 25 625 312 5 156 25 78 125 39 06 Frequency MHz MHz MHz kHz kHz kHz kHz kHz Resolution 200 ns 400 ns 800 ns 1 6 us 3 2 us 6 4us 12 8ms 25 6 us Period 13ms 26 ms 52 5ms 105 ms 210 ms 420 ms 840 ms 1 68 s Table 10 11 GPT2 Timer Input Frequencies Resolution and Periods 2 25 MHz fcpu 25 MHz Timer Input Selection T5I T6l 0008 001g 010 011 100g 101g 110g 111g Prescaler 4 8 16 32 64 128 256 512 Factor Input 6 25 3 125 1 56 781 25 390 62 195 31 97 66 48 83 Frequency MHz MHz MHz kHz kHz kHz kHz kHz Resolution 160 ns 320 ns 640 ns 1 28 us 2 56 us 5 12 us 10 2 ms 20 5 us Period 10 5 ms 21 ms 42ms 83 9ms 168 ms 336 ms 671 ms 1 34 s
441. of bit INIT and can be done on the fly The message objects should all be configured to particular identifiers or set to not valid before the BSP starts the message transfer however To change the configuration of a message object during normal operation the CPU first clears bit MSGVAL which defines it as not valid When the configuration is completed MSGVAL is set again User s Manual 19 33 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Busoff Recovery Sequence If the device goes busoff it will set bit BOFF and also set bit INIT of its own accord stopping all bus activities To have the CAN module take part in the CAN bus activities again the bus off recovery sequence must be started by clearing the bit INIT via software Once INIT has been cleared the module will then wait for 129 occurrences of Bus idle before resuming normal operation At the end of the busoff recovery sequence the Error Management Counters will be reset This will automatically clear bits BOFF and EWRN During the waiting time after the resetting of INIT each time a sequence of 11 recessive bits has been monitored a BitOError code is written to the Control Register enabling the CPU to check up whether the CAN bus is stuck at dominant or continously disturbed and to monitor the proceeding of the busoff recovery sequence Note An interrupt can be generated when entering the busoff state if bits IE and EIE are set
442. of the BUSCON registers In demultiplexed bus modes PORT1 drives the 16 bit intra segment address while PORTO or POL according to the selected data bus width drives the output data For a 16 bit data bus BHE is automatically enabled for an 8 bit data bus BHE is disabled via bit BYTDIS in register SYSCON Default 16 bit data bus with multiplexed addresses Note If an internal start is selected via pin EA these two pins are disregarded and bit field BTYP of register BUSCONO is cleared Write Configuration Pin POH 0 WRC selects the initial operation of the control pins WR and BHE during reset When high this pin selects the standard function i e WR control and BHE When low it selects the alternate configuration i e WRH and WRL Thus even the first access after a reset can go to a memory controlled via WRH and WRL This bit is latched in register RPOH and its inverted value is copied into bit WRCFG in register SYSCON Default Standard function WR control and BHE User s Manual 20 17 V2 0 2000 07 d nfineon ed technologies Derivatives System Reset Chip Select Lines Pins POH 2 and POH 1 CSSEL define the number of active chip select signals during reset This allows the selection which pins of Port 6 drive external CS signals and which are used for general purpose IO The two bits are latched in register RPOH Table 20 4 Configuration of Chip Select Lines POH 2 1 CSSEL Ch
443. ol Register 004 P6 b FFCC E6 Port 6 Register 8 bits 004 DP6 b FFCE E74 Port6 Direction Control Register 004 P7 b FFDO E84 Port 7 Register 8 bits 004 DP7 b FFD2 E94 Port 7 Direction Control Register 00H P8 b FFD4 EAy Port 8 Register 8 bits 004 DP8 b FFD64 EB Port 8 Direction Control Register 004 1 The system configuration is selected during reset 2 User s Manual The reset value depends on the indicated reset source 23 23 V2 0 2000 07 o nfineon ed technologies Derivatives The Register Set 23 5 Special Notes PEC Pointer Registers The source and destination pointers for the peripheral event controller are mapped to a special area within the internal RAM Pointers that are not occupied by the PEC may therefore be used like normal RAM During Power Down mode or any warm reset the PEC pointers are preserved The PEC and its registers are described in Chapter 5 GPR Access in the ESFR Area The locations 00 F000 00 FO1E within the ESFR area are reserved and allow to access the current register bank via short register addressing modes The GPRs are mirrored to the ESFR area which allows access to the current register bank even after switching register spaces see example below MOV R5 DP3 GPR access via SFR area EXTR 1 MOV R5 ODP3 GPR access via ESFR area Writing Bytes to SFRs All special function registers may be accessed wordwise or bytewise s
444. ome of them even bitwise Reading bytes from word SFRs is a non critical operation However when writing bytes to word SFRs the complementary byte of the respective SFR is cleared with the write operation User s Manual 23 24 V2 0 2000 07 d nfineon e technologies Derivatives Instruction Set Summary 24 Instruction Set Summary This chapter briefly summarizes the C167CS s instructions ordered by instruction classes This provides a basic understanding of the C167CS s instruction set the power and versatility of the instructions and their general usage A detailed description of each single instruction including its operand data type condition flag settings addressing modes length number of bytes and object code format is provided in the Instruction Set Manual for the C166 Family This manual also provides tables ordering the instructions according to various criteria to allow quick references Summary of Instruction Classes Grouping the various instruction into classes aids in identifying similar instructions e g SHR ROR and variations of certain instructions e g ADD ADDB This provides an easy access to the possibilities and the power of the instructions of the C167CS Note The used mnemonics refer to the detailed description Arithmetic Instructions Addition of two words or bytes ADD ADDB e Addition with Carry of two words or bytes ADDC ADDCB e Subtraction of two words or bytes SUB SUB
445. omodate additional masters in a C167CS system The number of chip select signals is selected via bitfield CSSEL in register RPOH During an external reset register RPOH is configured according to the levels of PORTO Software can adjust the number of selected chip select signals via register RSTCON Table 7 8 summarizes the alternate functions of Port 6 depending on the number of selected chip select lines coded via bitfield CSSEL Table 7 8 Alternate Functions of Port 6 Port 6 Pin Altern Function Altern Function Altern Function Altern Function CSSEL 10 CSSEL 01 CSSEL 00 CSSEL 11 P6 0 Gen purpose IO Chip select CSO Chip select CSO Chip select CSO P6 1 Gen purpose IO Chip select CS1 Chip select CS1 Chip select CS1 P6 2 Gen purpose IO Gen purpose IO Chip select CS2 Chip select CS2 P6 3 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CS3 P6 4 Gen purpose IO Gen purpose IO Gen purpose IO Chip select CS4 P6 5 HOLD External hold request input P6 6 HLDA Hold acknowledge output master mode or input slave mode P6 7 BREQ Bus request output User s Manual 7 43 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Alternate Function a FOIS P6 7 BREQ P6 6 HLDA P6 5 HOLD P6 4 CS4 P6 3 CS3 P6 2 CS2 P6 1 CS1 P6 0 CSO General Purpose Input Output MGARSER Figure 7 21 Port 6 10 and Alternate Functions
446. ompare Registers The 16 bit capture compare registers CCO through CC31 are used as data registers for capture or compare operations with respect to timers TO T1 and T7 T8 The capture compare registers are not bitaddressable The functions of the 32 capture compare registers are controlled by 8 bitaddressable 16 bit mode control registers named CCMO CCM7 which are organized identically see description below Each register contains bits for mode selection and timer allocation of four capture compare registers Capture Compare Mode Registers for the CAPCOM1 Unit CCO CC15 CCMO CAPCOM Mode Ctrl Reg 0 SFR FF52 A9 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ccwop3 ASS ccmop2 ASS ccwopi AGC ccmopo rw rw rw rw rw rw rw rw CCM1 CAPCOM Mode Cirl Reg 1 SFR FF544 AAp Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ccmop7 ASS ccwope A C ccwops CC ccmops rw rw rw rw rw rw rw rw CCM2 CAPCOM Mode Ctrl Reg 2 SFR FF56 AB Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ccwopi A C ccmopio 6 C ccmopa AS ccmops rw rw rw rw rw rw rw rw CCM3 CAPCOM Mode Ctrl Reg 3 SFR FF584 ACp Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACC ccMoDis ASC ccwopi4 AGC
447. on ed technologies Derivatives Interrupt and Trap Functions TFR Trap Flag Register SFR FFAC D6 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 nmi STK STK UND PRT ILL ILL ILL OF UF OPC FLT OPA INA BUS rwh rwh rwh Wh rh rwh rwh rwh Bit Function ILLBUS Illegal External Bus Access Flag An external access has been attempted with no external bus defined ILLINA Illegal Instruction Access Flag A branch to an odd address has been attempted ILLOPA Illegal Word Operand Access Flag A word operand access read or write to an odd address has been attempted PRTFLT Protection Fault Flag A protected instruction with an illegal format has been detected UNDOPC Undefined Opcode Flag The currently decoded instruction has no valid C167CS opcode STKUF Stack Underflow Flag The current stack pointer value exceeds the content of register STKUN STKOF Stack Overflow Flag The current stack pointer value falls below the content of reg STKOV NMI Non Maskable Interrupt Flag HEN A negative transition falling edge has been detected on pin NMI Note The trap service routine must clear the respective trap flag otherwise a new trap will be requested after exiting the service routine Setting a trap request flag by software causes the same effects as if it had been set by hardware In the case where e g
448. on oo technologies Derivatives Architectural Overview External Bus Interface In order to meet the needs of designs where more memory is required than is provided on chip up to 16 MBytes of external RAM and or ROM can be connected to the microcontroller via its external bus interface The integrated External Bus Controller EBC allows to access external memory and or peripheral resources in a very flexible way For up to five address areas the bus mode multiplexed demultiplexed the data bus width 8 bit 16 bit and even the length of a bus cycle waitstates signal delays can be selected independently This allows to access a variety of memory and peripheral components directly and with maximum efficiency If the device does not run in Single Chip Mode where no external memory is required the EBC can control external accesses in one of the following external access modes 16 18 20 24 bit Addresses 16 bit Data Demultiplexed 16 18 20 24 bit Addresses 8 bit Data Demultiplexed 16 18 20 24 bit Addresses 16 bit Data Multiplexed 16 18 20 24 bit Addresses 8 bit Data Multiplexed The demultiplexed bus modes use PORT1 for addresses and PORTO for data input output The multiplexed bus modes use PORTO for both addresses and data input output Port 4 is used for the upper address lines A16 if selected Important timing characteristics of the external bus interface waitstates ALE length and Read Write Delay
449. on uncertainty of this measurement implies the first deviation from the real baudrate the next deviation is implied by the computation of the SOBRL reload value from the timer contents The formula below shows the association T6 36 9 forpu SOBRL 75 For a correct data transfer from the host to the C167CS the maximum deviation between the internal initialized baudrate for ASCO and the real baudrate of the host should be below 2 5 The deviation Fg in percent between host baudrate and C167CS baudrate can be calculated via the formula below Fg Econr PHost 4009 Fp 2 59 Contr Note Function Fg does not consider the tolerances of oscillators and other devices supporting the serial communication This baudrate deviation is a nonlinear function depending on the CPU clock and the baudrate of the host The maxima of the function Fg increase with the host baudrate due to the smaller baudrate prescaler factors and the implied higher quantization error see Figure 15 3 User s Manual 15 6 V2 0 2000 07 o nfineon e technologies Derivatives The Bootstrap Loader B Host MCA02260 Figure 15 3 Baudrate Deviation between Host and C167CS The minimum baudrate B pw in Figure 15 3 is determined by the maximum count capacity of timer T6 when measuring the zero byte i e it depends on the CPU clock The minimum baudrate is obtained by using the maximum T6 count 216 in the baudra
450. only Ifthe overrun error detection enable bit SOOEN is set and the last character received was not read out of the receive buffer by software or PEC transfer at the time the reception of a new frame is complete the overrun error flag SOOE is set indicating that the error interrupt request is due to an overrun error Asynchronous and synchronous mode User s Manual 11 10 V2 0 2000 07 o nfineon ed technologies Derivatives The Asynchronous Synchronous Serial Interface 11 4 ASCO Baud Rate Generation The serial channel ASCO has its own dedicated 13 bit baud rate generator with 13 bit reload capability allowing baud rate generation independent of the GPT timers The baud rate generator is clocked with the CPU clock divided by 2 fcpu 2 The timer is counting downwards and can be started or stopped through the Baud Rate Generator Run Bit SOR in register SOCON Each underflow of the timer provides one clock pulse to the serial channel The timer is reloaded with the value stored in its 13 bit reload register each time it underflows The resulting clock is again divided according to the operating mode and controlled by the Baudrate Selection Bit SOBRS If SOBRS 1 the clock signal is additionally divided to 2 3rd of its frequency see formulas and table So the baud rate of ASCO is determined by the CPU clock the reload value the value of SOBRS and the operating mode asynchronous or synchronous Register SOBG is the dua
451. onse to the slave s BREQ The slave may now use the external bus system until the master requests it back P6 7 BREQ OUTput The bus request signal indicates to the bus arbiter logic that the C167CS requires control over the external bus which has been released and is currently controlled by another bus master 1 In slave mode pin HLDA inverts its direction to input The changed functionality is indicated through the different name Arbitration Sequences An external master may request the C167CS s bus via the HOLD input After completing the currently running bus cycle the C167CS acknowledges this request via the HLDA output and will then float its bus lines internal pullups at CSx RD and WR internal pulldown at ALE The new master may now access the peripheral devices or memory banks via the same interface lines as the C167CS During this time the C167CS can keep on executing as long as it does not need access to the external bus All actions that just require internal resources like instruction or data memory and on chip generic peripherals may be executed in parallel Note The XBUS is an internal representation of the external bus interface Accesses to XBUS peripherals use the EBC and therefore also cannot be executed during the bus hold state When the C167CS needs access to its external bus while it is occupied by another bus master it demands it via the BREQ output The arbiter can then remove the c
452. open drain mode Note Due to pin limitations register bit P3 14 is not connected to an IO pin Pins P3 15 and P3 12 do not support open drain mode Alternate Functions of Port 3 The pins of Port 3 serve for various functions which include external timer control lines the two serial interfaces and the control lines BHE WRH and clock output Table 7 5 summarizes the alternate functions of Port 3 Table 7 5 Alternate Functions of Port 3 Port 3 Pin Alternate Function P3 0 TOIN CAPCOM1 Timer TO Count Input P3 1 T6OUT GPT2 Timer T6 Toggle Latch Output P3 2 CAPIN GPT2 Capture Input P3 3 T3OUT GPT1 Timer T3 Toggle Latch Output P3 4 T3EUD GPT1 Timer T3 External Up Down Input P3 5 T4IN GPT1 Timer T4 Count Input P3 6 TSIN GPT1 Timer T3 Count Input P3 7 T2IN GPT1 Timer T2 Count Input P3 8 MRST SSC Master Receive Slave Transmit P3 9 MTSR SSC Master Transmit Slave Receive P3 10 TxDO ASCO Transmit Data Output P3 11 RxDO ASCO Receive Data Input P3 12 BHE WRH Byte High Enable Write High Output P3 13 SCLK SSC Shift Clock Input Output P3 15 CLKOUT System Clock Output FOUT Programmable Frequency Output User s Manual 7 29 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Alternate Function a b P3 15 CLKOUT FOUT No Pin P3 13 SCLK P3 12 BHE RH P3 11 RxDO P3 10 TxDO P3 9 MTSR P3 8 MRST Port 314 y P3 7 T2IN P3 6 TSIN P3 5 T4IN P3 4 T3EUD P3 3 T3OUT P3 2 CAPIN P3 1
453. ort 8 Open Drain Control Register U LMLM Last Message Mask XPOIC CAN1 Interrupt Control Register MCRn Configuration Register of Message n XP11C CAN2 Interrupt Control Register U LARn Arbitration Register of Message n MCA04473 Figure 19 1 Registers Associated with the CAN Module The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud The minimum CPU clock frequency to achieve 1 MBaud is fcpy 2 8 16 MHz depending on the activation of the CAN module s clock prescaler The CAN module uses two pins of Port 4 or of Port 8 to interface to a bus transceiver It provides Full CAN functionality on up to 15 full sized message objects 8 data bytes each Message object 15 may be configured for Basic CAN functionality with a double buffered receive object Both modes provide separate masks for acceptance filtering which allows the acceptance of a number of identifiers in Full CAN mode and also allows disregarding a number of identifiers in Basic CAN mode All message objects can be updated independent from the other objects during operation of the module and are equipped with buffers for the maximum message length of 8 Bytes User s Manual 19 2 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 1 Functional Blocks of the CAN Module The CAN module combines several functional blocks see Figure 19 2 that work in parallel and contribute to the controllers perfo
454. ot within a disabled group can still be accessed Periodic Wakeup from Idle Mode Periodic wakeup from Idle mode combines the drastically reduced power consumption in Idle mode in conjunction with the additional power management features with a high level of system availability External signals and events can be scanned at a lower rate by periodically activating the CPU and selected peripherals which then return to powersave mode after a short time This greatly reduces the system s average power consumption 2 5 Protected Bits The C167CS provides a special mechanism to protect bits which can be modified by the on chip hardware from being changed unintentionally by software accesses to related bits see also Chapter 4 The following bits are protected User s Manual 2 19 V2 0 2000 07 o nfineon technologies C167CS Derivatives Architectural Overview Table 2 1 C167CS Protected Bits Register Bit Name Notes T2IC T3IC TAIC T2IR T3IR T4IR GPT1 timer interrupt request flags T5IC T6IC T5IR T6IR GPT2 timer interrupt request flags CRIC CRIR GPT2 CAPREL interrupt request flag T3CON T6CON T30TL T60TL GPTx timer output toggle latches TOIC T11C TOIR T1IR CAPCOM timer interrupt request flags T7IC T8IC T7IR T8IR CAPCOM timer interrupt request flags SOTIC SOTBIC SOTIR SOTBIR ASCO transmit buffer interrupt request flags SORIC SOEIC SORIR SOEIR ASCO receive error interrupt r
455. ous Synchronous Serial Interface Bit Function SOPE Parity Error Flag Set by hardware on a parity error SOPEN 1 Must be reset by software SOFE Framing Error Flag Set by hardware on a framing error SOFEN 1 Must be reset by software SOOE Overrun Error Flag Set by hardware on an overrun error SOOEN 1 Must be reset by software SOODD Parity Selection Bit 0 Even parity parity bit set on odd number of 1 s in data 1 Odd parity parity bit set on even number of 1 s in data SOBRS Baudrate Selection Bit 0 Divide clock by reload value constant depending on mode 1 Additionally reduce serial clock to 2 3rd SOLB Loopback Mode Enable Bit 0 Standard transmit receive mode LUE Loopback mode enabled SOR Baudrate Generator Run Bit 0 Baudrate generator disabled ASCO inactive 1 Baudrate generator enabled A transmission is started by writing to the Transmit Buffer register SOTBUF via an instruction or a PEC data transfer Only the number of data bits which is determined by the selected operating mode will actually be transmitted i e bits written to positions 9 through 15 of register SOTBUF are always insignificant After a transmission has been completed the transmit buffer register is cleared to 0000 Data transmission is double buffered so a new character may be written to the transmit buffer register before the transmission of the previous character is
456. output signal s shape Driver characteristic influences the signal shape s susceptibility to the external capacitive load Slow Edge High Current Dynamic Fast Edge Low Current Slow Edge Low Current MCD04462 Figure 7 5 User s Manual General Output Signal Waveforms 7 8 V2 0 2000 07 e nfineon technologies 7 3 C167CS Derivatives Alternate Port Functions Parallel Ports In order to provide a maximum of flexibility for different applications and their specific IO requirements port lines have programmable alternate input or output functions associated with them Table 7 3 Summary of Alternate Port Functions Port Alternate Function s Alternate Signal s PORTO Address and data lines when accessing AD15 ADO external resources e g memory PORT Address lines when accessing ext resources A15 AO Capture inputs or compare outputs of the CC271O CC24l0 CAPCOM units Analog input extension channels to the A D AN23 AN16 converter Port2 Capture inputs or compare outputs of the CC151O CCOIO CAPCOM units CAPCOM timer input T7IN Fast external interrupt inputs EXTIN EXOIN Port 3 System clock or programmable frequency CLKOUT FOUT BHE WRH output Optional bus control signal RxDO TxDO MTSR MRST Input output functions of serial interfaces SCLK T2lN T3I
457. p Functions Context Switching An interrupt service routine usually saves all the registers it uses on the stack and restores them before returning The more registers a routine uses the more time is wasted with saving and restoring The C167CS allows to switch the complete bank of CPU registers GPRs with a single instruction so the service routine executes within its own separate context The instruction SCXT CP New Bank pushes the content of the context pointer CP on the system stack and loads CP with the immediate value New Bank which selects a new register bank The service routine may now use its own registers This register bank is preserved when the service routine terminates i e its contents are available on the next call Before returning RETI the previous CP is simply POPped from the system stack which returns the registers to the original bank Note The first instruction following the SCXT instruction must not use a GPH Resources that are used by the interrupting program must eventually be saved and restored e g the DPPs and the registers of the MUL DIV unit User s Manual 5 19 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 5 Interrupt Response Times The interrupt response time defines the time from an interrupt request flag of an enabled interrupt source being set until the first instruction 11 being fetched from the interrupt vector location The
458. p will be entered when the SP value is less than the value in the stack overflow register The contents of the stack pointer are compared to the contents of the underflow register whenever the SP is INCREMENTED either by a RET POP or ADD instruction An underflow trap will be entered when the SP value is greater than the value in the stack underflow register Note When a value is MOVED into the stack pointer NO check against the overflow underflow registers is performed In many cases the user will place a software reset instruction SRST into the stack underflow and overflow trap service routines This is an easy approach which does not require special programming However this approach assumes that the defined internal stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error User s Manual 22 4 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack Only the portion of the system stack currently being used is placed into the internal memory thus allowing a greater portion of the internal RAM to be used for program data or register banking This approach assumes no error but requires a set of control routines see below Circular Virtual Stack This basic technique allows pushing until the overflow boundary of the internal s
459. pdated via software the Multiply Divide Register In Use MDRIU flag in the Multiply Divide Control register MDC is set to 1 The MDRIU flag is cleared whenever the MDL register is read via software When a multiplication or division is interrupted before its completion and when a new multiply or divide operation is to be performed within the interrupt service routine register MDL must be saved along with registers MDH and MDC to avoid erroneous results A detailed description of how to use the MDL register for programming multiply and divide algorithms can be found in Chapter 22 User s Manual 4 31 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The Multiply Divide Control Register MDC This bit addressable 16 bit register is implicitly used by the CPU when it performs a multiplication or a division It is used to store the required control information for the corresponding multiply or divide operation Register MDC is updated by hardware during each single cycle of a multiply or divide instruction MDC Multiply Divide Control Reg SFR FF0E 4 874 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MDR fe fe fe foe foe foe foe Pb pnp Hn ib ng r w h r w h r w h r w h r w h r w h r w h r w h Bit Function MDRIU Multiply Divide Register In Use 0 Cleared when register MDL is read via software 1 Set when
460. plication Interface The on chip CAN modules of the C167CS are connected to the external physical layer i e the CAN bus via two signals each Table 19 4 CAN Interface Signals CAN Signal Port Pin Function CAN1 RXD Controlled via Receive data from the physical layer of the CAN bus 1 CAN1 Txp C PCIR IPC Transmit data to the physical layer of the CAN bus 1 CAN2 RXD Controlled via Receive data from the physical layer of the CAN bus 2 CAN2 TXD C2PCIR IPC Transmit data to the physical layer of the CAN bus 2 Note The two interfaces may be combined on two port pins connecting to one single CAN bus A logic low level 0 is interpreted as the dominant CAN bus level a logic high level 1 is interpreted as the recessive CAN bus level Connection to an External Transceiver The two CAN modules of the C167CS can be connected to an external CAN bus via a CAN transceiver in several ways Separate Buses permit communication on two independent CAN buses e g with different baudrates For this purpose the CAN interface lines must be assigned to separate pairs of port pins A Single Bus can be connected where both modules provide a total of 30 message objects For this purpose the CAN interface lines must be assigned to the same pair of port pins Note Basically it is also possible to connect several CAN modules directly on board without using CAN transceivers The CAN modules may
461. plicity all these various versions are referred to by the term C167CS throughout this manual The complete pro electron conforming designations are listed in the respective data sheets User s Manual 1 1 V2 0 2000 07 o nfineon ed technologies Derivatives Introduction 1 1 The Members of the 16 bit Microcontroller Family The microcontrollers of the Infineon 16 bit family have been designed to meet the high performance requirements of real time embedded control applications The architecture of this family has been optimized for high instruction throughput and minimum response time to external stimuli interrupts Intelligent peripheral subsystems have been integrated to reduce the need for CPU intervention to a minimum extent This also minimizes the need for communication via the external bus interface The high flexibility of this architecture allows to serve the diverse and varying needs of different application areas such as automotive industrial control or data communications The core of the 16 bit family has been developed with a modular family concept in mind All family members execute an efficient control optimized instruction set additional instructions for members of the second generation This allows an easy and quick implementation of new family members with different internal memory sizes and technologies different sets of on chip peripherals and or different numbers of IO pins The XBUS concept opens a straight fo
462. r SP 000g 256 00 FBFE 00 FAO0 Default after Reset SP 8 SP 0 001g 128 O0 FBFE 00 FBOO SP 7 SP 0 010g 64 OO0 FBFE 00 FB80 SP 6 SP 0 011g 32 00 FBFE 00 FBCO SP 5 a SPO 100g 512 00 FBFE 00 F800 not for 1KByte IRAM SP 9 SP 0 101g Reserved Do not use this combination 110g Reserved Do not use this combination 111g 512 00 FDFE 00 FXOO Note No circular stack SP 11 SP 0 1024 00 FX00 represents the lower IRAM limit i e 1536 1 KB 00 FA00 2 KB 00 F600 3 KB 00 F200 User s Manual 22 5 V2 0 2000 07 o nfineon technologies C167CS Derivatives System Programming The virtual stack addresses are transformed to physical stack addresses by concatenating the significant bits of the stack pointer register SP see Table 22 2 with the complementary most significant bits of the upper limit of the physical stack area 00 FBFE This transformation is done via hardware see Figure 22 1 The reset values STKOV FA004 STKUN FC00 SP FCO04 STKSZ 000p map the virtual stack area directly to the physical stack area and allow using the internal system stack without any changes provided that the 256 word area is not exceeded H H FBFE 1111 1011 1 111 FBFE xi du quw FB80 1111 1011 1 000 0000 Phys A FA00 0 0000 0000 FB80 1111 1011 1000 0000 SP F800
463. r software related failures the software fails to do so the Watchdog Timer overflows and generates an internal hardware reset and pulls the RSTOUT pin low in order to allow external hardware components to reset The Watchdog Timer is a 16 bit timer clocked with the CPU clock divided by 2 4 128 or 256 The high byte of the Watchdog Timer register can be set to a prespecified reload value stored in WDTREL in order to allow further variation of the monitored time interval Each time it is serviced by the application software the high byte of the Watchdog Timer is reloaded Thus time intervals between 21 us and 671 ms can be monitored 25 MHz 16 us and 335 ms 33 MHz The default Watchdog Timer interval after reset is 5 2 4 0 ms 25 33 MHz 2 4 Power Management Features The known basic power reduction modes Idle and Power Down are enhanced by a number of additional power management features see below These features can be combined to reduce the controller s power consumption to the respective application s possible minimum Flexible clock generation Flexible peripheral management peripherals can be enabled disabled separately or in groups Periodic wakeup from Idle mode via RTC timer The listed features provide effective means to realize standby conditions for the system with an optimum balance between power reduction i e standby time and peripheral operation i e system functionality Flexible Clock Gene
464. r 0000 CC31IC b F1944 E CA CAPCOM Register 31 Interrupt Ctrl Reg 00004 XP2IC b F1964 E CB Unassigned Interrupt Control Register 0000 SOTBIC b F19C4 E CE4 Serial Channel 0 Transmit Buffer Interrupt 0000 Control Register XP3IC b F19E E CFy RTC PLL OWD Interrupt Control Register 0000 EXICON b F1CO E EO External Interrupt Control Register 0000 ODP2 b F1C2 E El Port 2 Open Drain Control Register 0000 PICON F1C44 E E24 Port Input Threshold Control Register 00004 ODP3 b F1C64 E E34 Port 3 Open Drain Control Register 00004 ODP4 b F1CA E E5 4_ Port 4 Open Drain Control Register 004 ODP6 b FICE E E7 Port 6 Open Drain Control Register 004 SYSCON2 b F1DO E E8j CPU System Configuration Register 2 00004 ODP7 b F1D2 E E9 Port 7 Open Drain Control Register 004 SYSCONS3 b F1D4 E EA CPU System Configuration Register 3 0000 ODP8 b F1D6 E EBy Port 8 Open Drain Control Register 004 EXISEL b F1DA4 E ED External Interrupt Source Select Register 0000 SYSCON1 b F1DC E EE CPU System Configuration Register 1 0000 ISNC b F1DE E EFy Interrupt Subnode Control Register 0000 RSTCON b FiEO4m Reset Control Register 00XX DPPO FE00 00 CPU Data Page Pointer 0 Register 10 bits 0000 DPP1 FE024 014 CPU Data Page Pointer 1 Register 10 bits 00014 DPP2 FE04 02 CPU Data Page Pointer 2 Register 10 bits 0002 DPP3 FE064 034 CPU Data Page Pointer 3 Register 10 bits 0003 User s Manual 23 17
465. r 00004 PECC6 FECC 664 PEC Channel 6 Control Register 00004 PECC7 FECE 674 PEC Channel 7 Control Register 0000 POL b FFOO 804 Port 0 Low Register Lower half of PORTO 004 POH b FF024 814 Port 0 High Register Upper half of PORTO 004 P1L b FF044 82 Port 1 Low Register Lower half of PORT1 004 P1H b FFO6 83 Port 1 High Register Upper half of PORT1 00 BUSCONO b FFOC 864 Bus Configuration Register 0 0000 MDC b FFOE 87 4 CPU Multiply Divide Control Register 0000 PSW b FF10 88 CPU Program Status Word 0000 SYSCON b FF12 89 CPU System Configuration Register N0xx0y BUSCONT1 b FF14 8A Bus Configuration Register 1 00004 BUSCON b FF16j 8B Bus Configuration Register 2 00004 BUSCONS b FF18 8C Bus Configuration Register 3 00004 BUSCON4 b FF1A 18D Bus Configuration Register 4 00004 ZEROS Jb FF1C4 8E Constant Value 0 s Register read only 0000 ONES b FF1E 8F Constant Value 1 s Register read only FFFFy T78CON b FF20 90 CAPCOM Timer 7 and 8 Control Register 0000 CCM4 b FF22 914 CAPCOM Mode Control Register 4 0000 User s Manual 23 20 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 4 C167CS Registers Ordered by Address cont d Name Physical 8 bit Description Reset Address Addr Value CCM5 b FF24 921 CAPCOM Mode Control
466. r 10 3 10 24 Tools 1 6 Traps 5 31 Tri State Time 9 15 U UARn 19 22 UGML 19 17 UMLM 19 18 Unlock Sequence 21 22 Unseparable instructions 22 14 V Visible mode 9 39 W Waitstate Memory Cycle 9 14 Tri State 9 15 XBUS peripheral 9 38 Watchdog 2 18 13 1 after reset 20 5 Oscillator 6 8 20 19 Reset 20 3 WDT 13 2 WDTCON 13 4 X XBUS 2 10 9 37 enable peripherals 9 38 external access 9 40 waitstates 9 38 XPERCON 9 38 XPER Share mode 9 40 XRAM on chip 3 9 status after reset 20 8 xxlC 5 7 User s Manual Keyword Index Z ZEROS 4 33 26 6 V2 0 2000 07 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both constantly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
467. r Down Mode cs nuu ob GR REY nee eee ete oe Hea eee os 21 6 21 3 1 Status of Output Pins During Power Reduction Modes 21 8 21 4 Slow Down Operation 13 0 09 sim 3 BOR ar Cd pacc te ced SCR 21 10 21 5 Flexible Peripheral Management Lulseuess 21 14 21 6 Programmable Frequency Output Signal 005 21 17 21 7 Security Mechanism ausa d aris ra a RO ACE RR aha s LACE e ated 21 22 22 System Programming slllll lees 22 1 22 1 Stack Operations 353 29we tur dA Rx REARREXSUU ME RAS ELE Pd s 22 4 22 2 Register Banking as caida Geese dua auae xa kx Wa e eau y Ba woe ra 22 9 22 3 Procedure Call Entry and Exit coc caves sccs y rs er xA 22 9 22 4 Table Sedsrelitil vs scum aote Ste ace oo Giger 39 e Sa E oca VS ws 22 12 22 5 Floating Point Support xweltagas eua dores Ex Wes pate e rd sues 22 12 22 6 Peripheral Control and Interface llle 22 13 22 7 Trap interrupt Entry and Exit iios ade he Reano 22 13 22 8 Unseparable Instruction Sequences 000 cece eee eee 22 14 22 9 Overriding the DPP Addressing Mechanism 22 14 22 10 Handling the Internal Code Memory suus 22 16 22 11 Pits Traps and Mines a s rere n po Spe ob oed Res meee en ere 22 18 23 The Register Set 22s se vows ex a ario Un xm a re C eee uees 23 1 23 1 Register Description Format 20 000 e eee eee 23 1 User s Manual 4 V2 0 2000 07 o nfineon ed technolo
468. r maximum input frequency can be fcpy 32 In Incremental Interface Mode the count direction is automatically derived from the sequence in which the input signals change which corresponds to the rotation direction of the connected sensor Table 10 7 summarizes the possible combinations Table 10 7 GPT1 Core Timer T3 Incremental Interface Mode Count Direction Level on respective TSIN Input TSEUD Input other input Rising lt Falling Rising Falling High Down Up Up Down Low Up Down Down Up User s Manual 10 10 V2 0 2000 07 C167CS Derivatives technologies The General Purpose Timer Units Figure 10 8 and Figure 10 9 give examples of T3 s operation visualizing count signal generation and direction control It also shows how input jitter is compensated which might occur if the sensor rests near to one of its switching points Forward Jitter Backward Jitter Forward Contents f T3 E Up Down Up Note This example shows the timer behaviour assuming that T3 counts upon any transition on input i e T3I 011 g MCT04373 Figure 10 8 Evaluation of the Incremental Encoder Signals Forward Jitter Backward Jitter Forward Contents ole Up Down Up Note This example shows the timer behaviour assuming that T3 counts upon any transition on input TSIN i e T3I 001
469. r mode User s Manual 20 3 V2 0 2000 07 o nfineon e technologies Derivatives System Reset Bidirectional Reset In a special mode bidirectional reset the C167CS s line RSTIN normally an input may be driven active by the chip logic e g in order to support external equipment which is required for startup e g flash memory RSTIN gt Internal Circuitry Reset Sequence Active BDRSTEN 1 MCS04403 Figure 20 2 Bidirectional Reset Operation Bidirectional reset reflects internal reset sources software watchdog also to the RSTIN pin and converts short hardware reset pulses to a minimum duration of the internal reset sequence Bidirectional reset is enabled by setting bit BDRSTEN in register SYSCON and changes RSTIN from a pure input to an open drain IO line When an internal reset is triggered by the SRST instruction or by a watchdog timer overflow or a low level is applied to the RSTIN line an internal driver pulls it low for the duration of the internal reset sequence After that it is released and is then controlled by the external circuitry alone The bidirectional reset function is useful in applications where external devices require a defined reset signal but cannot be connected to the C167CS s RSTOUT signal e g an external flash memory which must come out of reset and deliver code well before RSTOUT can be deactivated via EINIT The following behavior differences mus
470. r reset 0 Latched CS mode The CS signals are latched internally and driven to the enabled port pins synchronously 1 Unlatched CS mode The CS signals are directly derived from the address and driven to the enabled port pins WRCFG Write Configuration Control Set according to pin POH 0 during reset 0 Pins WR and BHE retain their normal function 1 Pin WR acts as WRL pin BHE acts as WRH User s Manual 4 13 V2 0 2000 07 d nfineon ed technologies Derivatives The Central Processing Unit CPU Bit Function CLKEN System Clock Output Enable CLKOUT cleared after reset 0 CLKOUT disabled pin may be used for general purpose IO 1 CLKOUT enabled pin outputs the system clock signal BYTDIS Disable Enable Control for Pin BHE Set according to data bus width 0 Pin BHE enabled 1 Pin BHE disabled pin may be used for general purpose IO ROMEN Internal ROM Enable Set according to pin EA during reset 0 Internal program memory disabled accesses to the ROM area use the external bus 1 Internal program memory enabled SGTDIS Segmentation Disable Enable Control Cleared after reset 0 Segmentation enabled CSP is saved restored during interrupt entry exit 1 Segmentation disabled Only IP is saved restored ROMS1 Internal ROM Mapping 0 Internal ROM area mapped to segment 0 00 0000 00 7 FFF 1 Internal ROM area mapped to segment 1 01 0000 01 7
471. r run bit PTRx stops the associated counter and leaves the respective output at its current level The individual PWM channel outputs are controlled by comparators according to the formula PWM output signal PTx 2 PWx shadow latch So whenever software changes registers PTx the respective output will reflect the condition after the change Loading timer PTx with a value greater than or equal to the value in PWx immediately sets the respective output a PTx value below the PWx value clears the respective output By clearing or setting the respective Port 7 output latch the PWM channel signal is driven directly or inverted to the port pin Clearing the enable bit PENx disconnects the PWM channel and switches the respective port pin to the value in the port output latch Note To prevent further PWM pulses from occurring after such a software intervention the respective counter must be stopped first User s Manual 17 16 V2 0 2000 07 C167CS Derivatives technologies The Analog Digital Converter 18 The Analog Digital Converter The C167CS provides an Analog Digital Converter with 10 bit resolution and a sample amp hold circuit on chip A multiplexer selects between up to 24 analog input channels 16 standard channels as alternate functions of Port 5 8 extension channels as alternate functions of PORT1 either via software fixed channel modes or automatically auto scan modes To fulfill most requirements of emb
472. r system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered User s Manual V2 0 July 2000 C167CS Derivatives 16 Bit Single Chip Microcontroller Microcontrollers e e Infineon technologies Never stop thinking C167CS Revision History V2 0 2000 07 Previous Version Version 1 0 1999 05 Page Subjects major changes since last revision all Converted to new company layout all Figures have been redrawn XXX Flash descriptions removed 1 1 List of derivatives corrected 4 2 Sleep mode added 6 7 Description of PLL base frequency improved 7 2 Bit P4LIN added 7 8 Description of temperature compensation removed 7 14 Description of PORTO control corrected 7 17f CAPCOM2 output functionality added 7 20 Figure corrected 7 37 Open drain functionality described 7 54 Note corrected 9 6 Note reworked 9 28 Note corrected 9 31f Description of bus arbitration improved 9 38 Table reworked 9 39f Additional information 10 6 10 27 Table enhanced 10 30 Description of T5M corrected 11 13f Tables enhanced 12 5 Description of transmission timing improved 12 13 Baudrate tables improved 13 5 Time range
473. r the execution of EINIT unless it is released via the unlock sequence see Table 21 6 User s Manual 21 15 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management When disabling the peripheral clock driver PCD the following details should be respected The clock signal for all connected peripherals is stopped Make sure that all peripherals enter a safe state before disabling PCD The output signal CLKOUT will remain HIGH FOUT will keep on toggling Interrupt requests will still be recognized even while PCD is disabled No new output values are gated from the port output latches to the output port pins and no new input values are latched from the input port pins Noregister access is possible for generic peripherals register access is possible for individually disabled generic peripherals no register access at all is possible for disabled X Peripherals User s Manual 21 16 V2 0 2000 07 oe nfineon ed technologies Derivatives Power Management 21 6 Programmable Frequency Output Signal The system clock output CLKOUT can be replaced by the programmable frequency output signal four This signal can be controlled via software contrary to CLKOUT and so can be adapted to the requirements of the connected external circuitry The programmability also extends the power management to a system level as also circuitry peripherals etc outside the C167CS can be influenced i e run at a
474. ration The flexible clock generation system combines a variety of improved mechanisms partly user controllable to provide the C167CS modules with clock signals This is especially important in power sensitive modes like standby operation The power optimized oscillator generally reduces the amount of power which is consumed in order to generate the clock signal within the C167CS The clock system efficiently controls the amount of power which is consumed in order to distribute the clock signal within the C167CS User s Manual 2 18 V2 0 2000 07 o nfineon e technologies Derivatives Architectural Overview Slowdown operation is achieved by dividing the oscillator clock by a programmable factor 1 32 resulting in a low frequency device operation which significantly reduces the overall power consumption Flexible Peripheral Management The flexible peripheral management provides a mechanism to enable and disable each peripheral module separately In each situation e g several system operating modes standby etc only those peripherals may be kept running which are required for the respective functionality All others can be switched off It also allows the operation control of whole groups of peripherals including the power required for generating and distributing their clock input signal Other peripherals may remain active e g in order to maintain communication channels The registers of separately disabled peripherals n
475. rations code memory segmentation data memory paging and accesses to the General Purpose Registers and the System Stack The access mechanism for these SFRs in the CPU core is identical to the access mechanism for any other SFR Since all SFRs can simply be controlled by means of any instruction which is capable of addressing the SFR memory space a lot of flexibility has been gained without the need to create a set of system specific instructions Note however that there are user access restrictions for some of the CPU core SFRs to ensure proper processor operations The instruction pointer IP and code segment pointer CSP cannot be accessed directly at all They can only be changed indirectly via branch instructions The PSW SP and MDC registers can be modified not only explicitly by the programmer but also implicitly by the CPU during normal instruction processing Note that any explicit write request via software to an SFR supersedes a simultaneous modification by hardware of the same register Note Any write operation to a single byte of an SFR clears the non addressed complementary byte within the specified SFR Non implemented reserved SFR bits cannot be modified and will always supply a read value of 0 User s Manual 4 12 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The System Configuration Register SYSCON This bit addressable register provides general system co
476. rbitration 0 Bus arbitration disabled P6 7 P6 5 may be used for general purpose IO 1 Bus arbitration enabled P6 7 P6 5 serve as BREQ HLDA HOLD resp IEN Interrupt Enable Control Bit Globally enables disables interrupt requests 0 Interrupt requests are disabled 1 Interrupt requests are enabled ILVL CPU Priority Level Defines the current priority level for the CPU Fu Highest priority level Oy Lowest priority level User s Manual 5 10 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions CPU priority ILVL defines the current level for the operation of the CPU This bit field reflects the priority level of the routine that is currently executed Upon the entry into an interrupt service routine this bit field is updated with the priority level of the request that is being serviced The PSW is saved on the system stack before The CPU level determines the minimum interrupt priority level that will be serviced Any request on the same or a lower level will not be acknowledged The current CPU priority level may be adjusted via software to control which interrupt request sources will be acknowledged PEC transfers do not really interrupt the CPU but rather steal a single cycle so PEC services do not influence the ILVL field in the PSW Hardware traps switch the CPU level to maximum priority i e 15 so no interrupt or PEC requests will be acknowledged while an exception trap s
477. re can control the characteristics of the output driver via the following mechanisms Open Drain Mode The upper push transistor is always disabled Only 0 is driven actively an external pullup is required Driver Characteristic The driver strength static dynamic can be selected Edge Characteristic The rise fall time of an output signal can be selected Open Drain Mode In the C167CS certain ports provide Open Drain Control which allows to switch the output driver of a port pin from a push pull configuration to an open drain configuration In push pull mode a port output driver has an upper and a lower transistor thus it can actively drive the line either to a high or a low level In open drain mode the upper transistor is always switched off and the output driver can only actively drive the line to a low level When writing a 1 to the port latch the lower transistor is switched off and the output enters a high impedance state The high level must then be provided by an external pullup device With this feature it is possible to connect several port pins together to a Wired AND configuration saving external glue logic and or additional software overhead for enabling disabling output signals This feature is controlled through the respective Open Drain Control Registers ODPx which are provided for each port that has this feature implemented These registers allow the individual bit wise selection of the open drain mod
478. re reserved for XRAM accesses Note The 6 KByte XRAM area only covers locations 00 C000 to 00 D7FF The address decoder however reserves 213 KBytes i e locations 00 C000 to 00 DFFF User s Manual 3 9 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization XRAM Access via External Masters In X Peripheral Share mode bit XPER SHARE in register SYSCON is set the on chip XRAM of the C167CS can be accessed by an external master during hold mode via the C167CS s bus interface These external accesses must use the same configuration as internally programmed see above No waitstates are required In X Peripheral Share mode the C167CS bus interface reverses its direction i e address lines PORT1 Port 4 control signals RD WR and BHE must be driven by the external master Note The configuration in register SYSCON cannot be changed after the execution of the EINIT instruction User s Manual 3 10 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization 3 4 External Memory Space The C167CS is capable of using an address space of up to 16 MByte Only parts of this address space are occupied by internal memory areas All addresses which are not used for on chip memory ROM Flash OTP or RAM or for registers may reference external memory locations This external memory is accessed via the C167CS s external bus interface Four memory bank sizes are supported
479. re Mode 0 and 1 Block Diagram Note The port latch and pin remain unaffected in compare mode 0 In the example below the compare value in register CCx is modified from cv1 to cv2 after compare events 1 and 3 and from cv2 to cv1 after events 2 and 4 etc This results in periodic interrupt requests from timer Ty and in interrupt requests from register CCx which occur at the time specified by the user through cv1 and cv2 Contents of Ty FFFF Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000 Interrupt Requests TyIR CCxIR COxIR TyIR CCxIR CCxIR TyIR t Event 1 Event 2 Event 3 Event 4 CCx cv2 CCx cv1 CCx cv2 CCx cv1 Output pin CCxlO only effected in mode 1 No changes in mode 0 x 31 0 y 0 1 7 8 MCB02017 Figure 16 7 Timing Example for Compare Modes 0 and 1 User s Manual 16 15 V2 0 2000 07 _ d nfineon e technologies Derivatives The Capture Compare Units Compare Mode 1 Compare mode 1 is selected for register CCx by setting bit field CCMODx of the corresponding mode control register to 101p When a match between the content of the allocated timer and the compare value in register CCx is detected in this mode interrupt request flag CCxIR is set to 1 and in addition the corresponding output pin CCxIO alternate port output function is toggled For this purpose the state of the respective port output latch not t
480. re that the valid target levels are reached until the end of the reset sequence There is a specific application note to illustrate this User s Manual 20 12 V2 0 2000 07 j Infineon iiis technologies Derivatives System Reset 20 4 1 System Startup Configuration upon an External Reset For an external reset EA 0 the startup configuration uses the pins of PORTO and pin RD The value on the upper byte of PORTO POH is latched into register RPOH upon reset the value on the lower byte POL directly influences the BUSCONO register bus mode or the internal control logic of the C167CS H7 H6 H5 H4 H3 H2 H1 HO L7 L5 L4 L3 L2 L1 CLKCFG CALSEL CSSEL BUSTYP SMOD Internal Control Logic only on Hardware Reset Clock Port 4 Port 6 Generator Logic Logic RD SYSCON BUSCONO Figure 20 4 PORTO Configuration during Reset MCA04484 The pins that control the operation of the internal control logic the clock configuration and the reserved pins are evaluated only during a hardware triggered reset sequence The pins that influence the configuration of the C167CS are evaluated during any reset sequence i e also during software and watchdog timer triggered resets The configuration via POH is latched in register RPOH for subsequent evaluation by software Register RPOH is described in Chapter 9 The following describes the different selections that are offered for reset configuration The d
481. registers are secured by the described unlock sequence Table 21 7 Special Registers Secured by the Unlock Sequence Register Name Description SYSCON1 Controls sleep mode SYSCON2 Controls clock generation SDD and the unlock sequence itself SYSCONS Controls the flexible peripheral management RSTCON Controls the configuration of the C167CS basic clock generation mode CS lines segment address width and the length of the reset sequence Code Examples The code examples below show how the unlock sequence is used to access register SYSCON marked in the comment column in an application in order to change the basic clock generation mode Examples where the PLL Keeps Running E L 1 ENTER SLOWDOWN Currently running on basic clock frequ MOV SYSCON2 ZEROS Clear bits 3 0 no EXTR required here EXTR 44H Switch to ESFR space and lock sequence BFLDL SYSCON2 0FH 09H Unlock sequence step 1 1001B MOV SYSCON2 0003H Unlock sequence step 2 0011B BSET SYSCON2 2 Unlock sequence step 3 0111B Single access to one locked register BFLDH SYSCON2 03H 01H CLKCON 01B SDD frequency PLL on eee EXIT SLOWDOWN Currently running on SDD frequency MOV SYSCON2 ZEROS Clear bits 3 0 no EXTR required here EXTR 44H Switch to ESFR space and lock sequence BFLDL SYSCON2 0FH 09H Unlock sequence step 1 1001B
482. required of course PAPOWO PLLIR eo Interrupt PLLIE Intr Request Intr Enable rs Interrupt oe Controller ode as RTCIR eo Interrupt RTCIE Intr Request Intr Enable Register ISNC Register XP3IC MCA04464 Figure 14 3 RTC Interrupt Logic If T14 interrupts are to be used both stages the interrupt node XP3IE 1 and the RTC subnode RTCIE 1 must be enabled Please note that the node request bit XP3IR is automatically cleared when the interrupt handler is vectored to while the subnode request bit RTCIR must be cleared by software User s Manual 14 3 V2 0 2000 07 o nfineon e technologies Derivatives The Real Time Clock Defining the RTC Time Base The reload timer T14 determines the input frequency of the RTC timer i e the RTC time base as well as the T14 interrupt cycle time Table 14 2 lists the interrupt period range and the T14 reload values for a time base of 1 s and 1 ms for several oscillator frequencies Table 14 2 RTC Interrupt Periods and Reload Values Oscillator RTC Interrupt Period Reload Value A Reload Value B Frequency Minimum Maximum TI4REL Base T14REL Base 32 768 kHz Aux 244 14 us 16 0 s F000 1 000s FFFC 0 977 ms 32 kHz Aux 250 us 16 38 s F060 1 000s FFFC 1 000ms 32 kHz Main 8000 us 524 29s FF83 11 000s 4 MHz Main 64 0 us 4 19 s C2F7 1 000s FFFO 1 024ms 5 MHz Main 51 2 us
483. respective PWM channel is started via software and is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the timer is cleared to 0000 and stopped via hardware i e the respective PTRx bit is cleared The PWM output signal is switched to high level when the timer contents are equal to or greater than the contents of the pulse width shadow register The signal is switched back to low level when the respective timer is cleared i e is below the pulse width shadow register Thus starting a PWM timer in single shot mode produces one single pulse on the respective port pin provided that the pulse width value is between 0000 and the period value In order to generate a further pulse the timer has to be started again via software by setting bit PTRx After starting the timer i e PTRx 1 the output pulse may be modified via software Writing to timer PTx changes the positive and or negative edge of the output signal depending on whether the pulse has already started i e the output is high or not i e the output is still low This multiple retriggering is always possible while the timer is running i e after the pulse has started and before the timer is stopped Loading counter PTx directly with the value in the respective PPx shadow register will abort the current PWM pulse upon the next clock pulse counter is cleared and stopped by hardware By setting the period PPx the ti
484. respective sections T6M Timer 6 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 1XX Reserved Do not use this combination T6R Timer 6 Run Bit 0 Timer Counter 6 stops E Timer Counter 6 runs T6UD Timer 6 Up Down Control T6UDE Timer 6 External Up Down Enable T6OE Alternate Output Function Enable 0 Alternate Output Function Disabled q1 Alternate Output Function Enabled T6OTL Timer 6 Output Toggle Latch Toggles on each overflow underflow of T6 Can be set or reset by software T6SR Timer 6 Reload Mode Enable 0 Reload from register CAPREL Disabled T Reload from register CAPREL Enabled 1 For the effects of bits T6UD and T6UDE refer to the Table 10 9 User s Manual 10 24 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer 6 Run Bit The timer can be started or stopped by software through bit T6R Timer T6 Run Bit If T6R 0 the timer stops Setting T6R to 1 will start the timer In gated timer mode the timer will only run if T6R 1 and the gate is active high or low as programmed Count Direction Control The count direction of the core timer can be controlled either by software or by the external input pin T6EUD Timer T6 External Up Down Control Input which is the alternate input function of port pin P5 10 Th
485. rface lines will override general purpose IO and the segment address User s Manual 7 35 V2 0 2000 07 Infineon o Ce technologies Derivatives Parallel Ports Alternate Function a b Pona P4 7 A23 CAN1_RxD CAN2_TxD P4 6 A22 CAN1_TxD CAN2_TxD P4 5 A21 CAN1_RxD P4 4 A20 CAN2_RxD P4 3 A19 P4 2 A18 P4 1 A17 P4 0 A16 General Purpose Full Segment CAN Interface Input Output Address 16 MB MCA04427 Figure 7 17 Port 410 and Alternate Functions Note The usage of Port 4 pins especially P4 7 for CAN interface lines depends on the chosen assignments for the CAN module s CAN interface lines will override general purpose IO and segment address lines User s Manual 7 36 V2 0 2000 07 C167CS Derivatives technologies Parallel Ports Internal Bus rite Port Output Latch Direction Open Drain Latch Latch l 0 AltDir 3 1 AItEN AltDataOut gt 1 Driver Pin Clock AltDatalN lt o Input Latch MCD04469 P4 7 0 Figure 7 18 Block Diagram of a Port 4 Pin User s Manual 7 37 V2 0 2000 07 d nfineon ed technologies Derivatives Parallel Ports 7 9 Port 5 This 16 bit input port can only read data There is no output latch and no direction register Data written to P5 will be lost P5 Port 5 Data Register SFR FFA2 D1 Reset Value XXXX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
486. rful means to enhance the overall performance and flexibility of a system extreme care must be taken in order to avoid a system crash Instruction memory is the most crucial resource for the C167CS and it must be made sure that it never runs out of it The following precautions help to take advantage of the methods mentioned above without jeopardizing system security Internal code memory access after reset When the first instructions are to be fetched from internal memory EA 1 the device must contain code memory and this must contain a valid reset vector and valid code at its destination Mapping the internal ROM area to segment 1 Due to instruction pipelining any new ROM mapping will at the earliest become valid for the second instruction after the instruction which has changed the ROM mapping To enable accesses to the ROM area after mapping a branch to the newly selected ROM area JMPS and reloading of all data page pointers is required This also applies to re mapping the internal ROM area to segment O Enabling the internal code memory after reset When enabling the internal code memory after having booted the system from external memory note that the C167CS will then access the internal memory using the current segment offset rather than accessing external memory Disabling the internal code memory after reset When disabling the internal code memory after having booted the system from there note that the C167CS will not a
487. ring normal operation however this test mode may lead to undesired behaviour of the device User s Manual V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Bit Function Control Bits LEC Last Error Code This field holds a code which indicates the type of the last error occurred on the CAN bus If a message has been transferred reception or transmission without error this field will be cleared 0 No Error 1 Stuff Error More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed 2 Form Error Wrong format in fixed format part of a received frame 3 AckError The message this CAN controller transmitted was not acknowledged by another node 4 Bit1 Error During the transmission of a message with the exception of the arbitration field the device wanted to send a recessive level 1 but the monitored bus value was dominant 5 BitOError During the transmission of a message or acknowledge bit active error flag or overload flag the device wanted to send a dominant level 0 but the monitored bus value was recessive During busoff recovery this status is set each time a sequence of 11 recessive bits has been monitored This enables the CPU to monitor the proceeding of the busoff recovery sequence indicates that the bus is not stuck at dominant or continously disturbed 6 CRCError The received CRC check sum was i
488. rity and cause immediate system reaction The software trap function is invoked by the TRAP instruction which generates a software interrupt for a specified interrupt vector For all types of traps the current program status is saved on the system stack External Interrupt Processing Although the C167CS does not provide dedicated interrupt pins it allows to connect external interrupt sources and provides several mechanisms to react on external events including standard inputs non maskable interrupts and fast external interrupts These interrupt functions are alternate port functions except for the non maskable interrupt and the reset input User s Manual 5 1 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 1 Interrupt System Structure The C167CS provides 56 separate interrupt nodes that may be assigned to 16 priority levels In order to support modular and consistent software design techniques most sources of an interrupt or PEC request are supplied with a separate interrupt control register and interrupt vector The control register contains the interrupt request flag the interrupt enable bit and the interrupt priority of the associated source Each source request is then activated by one specific event depending on the selected operating mode of the respective device For efficient usage of the resources also multi source interrupt nodes are incorporated These nodes can be activated by se
489. rivatives Please refer to the corresponding descriptions in the data sheets User s Manual 25 1 V2 0 2000 07 C167CS Derivatives technologies Device Specification QQ00 NAANA 8888 88582222 w 3 0OON o OFAN o Ee E E E SE SE S S a a ween TS oe REosodco o0050000 ataacacaataacdce LILL LLILILIILILILILLILAL a SSS RRS 85 Som oO ox ooo loess Sgr zug qc ESO WOES CS Ed NOUWLTANKSGHOHYYTONE a GC ICE LEGE ee gash ot i i oh ee EE 8 92 BEEK arr c 0 0 7 ooooooco 0 0 gt gt xXx nananannunoa aannanaananaaanananananq z LILIL TED LLLLTLTETI Sy O e o co Qo EA A O O 0 r OQ t0 x OWN e e e e sv A A A Nerr rrr ree P6 0 CS0 1 P6 1 CS1 r 2 P6 2 CS243 P6 3 CS3 44 P6 4 CS4 45 POL 4 AD4 P6 5 HOLD r16 POL 3 AD3 P6 6 HLDA C7 102E3 POL 2 AD2 P6 7 BREQ C48 101E3 POL 1 AD1 P8 0 CC16l0 9 100 POL 0 ADO P8 1 CC17lO c10 99 5 EA P8 2 CC18IO E 11 98F ALE P8 3 CC191IO 412 974 READY P8 4 CC2010 413 96 5 WR WRL P8 5 CC2110 14 95E3 RD P8 6 CC2210 415 94 3 Ve P8 7 CC2310 416 93 v POL 7 AD7 POL 6 AD6 POL 5 AD5 C167CS 91 5 P4 6 A22 90 3 P4 5 A21 89 3 P4 4 A20 88p3 P4 3 A19 87 L3 P4 2 A18 P7 1 POUT1 420 P7 2 POUT2 21 P7 3 POUT3 22 P7 4 CC2810 23 86 3 P4 1 A17 P7 5 CC29IO 424 85 3 P4 0 A16 P7 6 CC3010 25 843 N C P7 7 CC3110 426 83 5 Veg P5 0 ANO 427 Von P5 1 AN1 cf28 P3 15 CLKOUT FOUT P5 2 AN2
490. rm 3 word bus accesses e When the above example has the interrupt vector pointing into the internal code memory the interrupt response time is 1 word bus access plus 4 states User s Manual 5 21 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions After an interrupt service routine has been terminated by executing the RETI instruction and if further interrupts are pending the next interrupt service routine will not be entered until at least two instruction cycles have been executed of the program that was interrupted In most cases two instructions will be executed during this time Only one instruction will typically be executed if the first instruction following the RETI instruction is a branch instruction without cache hit or if it reads an operand from internal code memory or if it is executed out of the internal RAM Note A bus access in this context includes all delays which can occur during an external bus cycle User s Manual 5 22 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 6 PEC Response Times The PEC response time defines the time from an interrupt request flag of an enabled interrupt source being set until the PEC data transfer being started The basic PEC response time for the C167CS is 2 instruction cycles Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 FETCH N N 1 N 2 N 2 DECODE N 1 N PEC N
491. rmance These units and the functions they provide are described below Each of the message objects has a unique identifier and its own set of control and status bits Each object can be configured with its direction as either transmit or receive except the last message which is only a double receive buffer with a special mask register An object with its direction set as transmit can be configured to be automatically sent whenever a remote frame with a matching identifier taking into account the respective global mask register is received over the CAN bus By requesting the transmission of a message with the direction set as receive a remote frame can be sent to request that the appropriate object be sent by some other node Each object has separate transmit and receive interrupts and status bits giving the CPU full flexibility in detecting when a remote data frame has been sent or received For general purpose two masks for acceptance filtering can be programmed one for identifiers of 11 bits and one for identifiers of 29 bits However the CPU must configure bit XTD Normal or Extended Frame Identifier for each valid message to determine whether a standard or extended frame will be accepted The last message object has its own programmable mask for acceptance filtering allowing a large number of infrequent objects to be handled by the system The object layer architecture of the CAN controller is designed to be as regular and orthogonal
492. rmed using software Standard multiple precision instructions are used to perform calculations on data types that exceed the size of the ALU Multiple bit rotate and logic instructions allow easy masking and extracting of portions of floating point numbers To decrease the time required to perform floating point operations two hardware features have been implemented in the CPU core First the PRIOR instruction aids in normalizing floating point numbers by indicating the position of the first set bit in a GPR This result can the be used to rotate the floating point result accordingly The second feature aids in properly rounding the result of normalized floating point numbers through the overflow V flag in the PSW This flag is set when a one is shifted out of the carry bit during shift right operations The overflow flag and the carry flag are then used to round the floating point result based on the desired rounding algorithm User s Manual 22 12 V2 0 2000 07 o nfineon ed technologies Derivatives System Programming 22 6 Peripheral Control and Interface All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory or by explicitly addressing the SFRs associated with the specific peripherals After resetting the C167CS all peripherals except the watchdog timer are disabled and initialized to default values A desired configuration of a specific peripheral is programmed using M
493. rrupt code is only displayed if there is no other interrupt request with a higher priority Example message 1 INTID 034 message 14 INTID 10 IPC Interface Port Control reset value 111g i e no port connection The encoding of bitfield IPC is described in Section 19 7 Note Bitfield IPC can be written only while bit CCE is set 1 Bit INTPND of the corresponding message object has to be cleared to give messages with a lower priority the possibility to update INTID or to reset INTID to 00 idle state User s Manual 19 11 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 2 2 Configuration of the Bit Timing According to the CAN protocol specification a bit time is subdivided into four segments Sync segment propagation time segment phase buffer segment 1 and phase buffer segment 2 Each segment is a multiple of the time quantum fg with tq BRP 1 x 2 7 SPS x nor Note The CAN module is connected to the CPU clock signal therefore txc x tcpy The Synchronization Segment Sync Seg is always 1 t long The Propagation Time Segment and the Phase Buffer Segment 1 combined to TSeg1 define the time before the sample point while Phase Buffer Segment 2 TSeg2 defines the time after the sample point The length of these segments is programmable except Sync Seg via the Bit Timing Register BTR Note For exact definition of these segments p
494. rt Nibble x Driver Characteristic Defines the current delivered by the output 00 High Current mode Driver always operates with maximum strength 01 Low Current mode Driver always operates with reduced strength 10 Dynamic Current mode Driver strength is reduced after the target level has been reached 11 Reserved Table 7 2 lists the defined POCON registers and the allocation of control bitfields and port pins User s Manual 7 7 V2 0 2000 07 o nfineon technologies C167CS Derivatives Parallel Ports Table 7 2 Port Output Control Register Allocation Control Location Controlled Pins by POCONx y z Notes Register 15 12 11 8 7 4 3 0 POCON20 F0AA 554 RSTOUT CLKOUT ALE WR RD No associated FOUT BHE WH port POCON8 F0924 49 P8 7 4 P8 3 0 POCON7 F0904 484 P7 7 4 P7 3 0 POCONG FO8E 47 l P6 7 4 P6 3 0 POCON4 FO8C 46 P4 7 4 P43 0 POCONS F08A4 454 P3 15 12 P3 11 8 P3 7 4 P3 3 0 P3 14 is missing POCON2 F0884 44 P2 15 12 P2 11 8 P2 7 4 P2 3 0 POCON1H F0864 434 P1H 7 4 P1H 3 0 POCONIL F084 424 P1L7 4 P1L 3 0 POCONOH F082 414 POH 7 4 POH 3 0 POCONOL F080 404 POL 7 4 POL 3 0 Figure 7 5 summarizes the effects of the driver characteristics Edge characteristic generally influences the
495. rts amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions SSCCON SSCTIC SSCRIC SSCEIC SCLK P3 13 MTSR P3 9 MRST P3 8 ODP3 Port 3 Open Drain Control Register P3 Port 3 Data Register DP3 Port 3 Direction Control Register SSCCON SSC Control Register SSCBR SSC Baud Rate Generator Reload Reg SSCRB SSC Receive Buffer Register SSCTB SSC Transmit Buffer Register SSCRIC SSC Receive Interrupt Control Register SSCTIC SSC Transmit Interrupt Control Register SSCEIC SSC Error Interrupt Control Register MCA04380 Figure 12 1 SFRs and Port Pins Associated with the SSC User s Manual 12 1 V2 0 2000 07 _ d nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface Clock Control Slave Clock Master Clock E SCLK CPU Baud Rate cick Gort Receive Int Request Transmit Int Request Error Int Request SSC Control Block MT Status Control J MTSR Pin Control 16 Bit Shift Register MRST Transmit Buffer Receive Buffer Register SSCTB Register SSCRB Internal Bus MCB01957 Figure 12 2 Synchronous Serial Channel SSC Block Diagram The operating mode of the serial channel SSC is controlled by its bit addressable control register SSCCON This register serves for two purposes during programming SSC disabled by SSCEN 0 it provides access to a set of control bits
496. rward path for the integration of application specific peripheral modules in addition to the standard on chip peripherals in order to build application specific derivatives As programs for embedded control applications become larger high level languages are favored by programmers because high level language programs are easier to write to debug and to maintain The 80C166 type microcontrollers were the first generation of the 16 bit controller family These devices have established the C166 architecture The C165 type and C167 type devices are members of the second generation of this family This second generation is even more powerful due to additional instructions for HLL support an increased address space increased internal RAM and highly efficient management of various resources on the external bus Enhanced derivatives of this second generation provide additional features like additional internal high speed RAM an integrated CAN Module an on chip PLL etc Utilizing integration to design efficient systems may require the integration of application specific peripherals to boost system performance while minimizing the part count These efforts are supported by the so called XBUS defined for the Infineon 16 bit microcontrollers second generation This XBUS is an internal representation of the external bus interface that opens and simplifies the integration of peripherals by standardizing the required interface One representative tak
497. ry IRAM XRAM before normal program operation Once the register bank has been selected by programming the CP register the desired portions of the internal memory can easily be initialized via indirect addressing Interrupt System After reset the individual interrupt nodes and the global interrupt system are disabled In order to enable interrupt requests the nodes must be assigned to their respective interrupt priority levels and be enabled The vector locations must receive pointers to the respective exception handlers The interrupt system must globally be enabled by setting bit IEN in register PSW Care must be taken not to enable the interrupt system before the initialization is complete in order to avoid e g the corruption of internal memory locations by stack operations using an uninitialized stack pointer Watchdog Timer After reset the watchdog timer is active and is counting its default period If the watchdog timer shall remain active the desired period should be programmed by selecting the appropriate prescaler value and reload value Otherwise the watchdog timer must be disabled before EINIT Ports Generally all ports of the C167CS are switched to input after reset Some pins may be automatically controlled e g bus interface pins for an external start TxD in Boot mode etc Pins that shall be used for general purpose IO must be initialized via software The required mode input output open drain push pull input threshold e
498. s Power Management 21 5 Flexible Peripheral Management The power consumed by the C167CS also depends on the amount of active logic Peripheral management enables the system designer to deactivate those on chip peripherals that are not required in a given system status e g a certain interface mode or standby All modules that remain active however will still deliver their usual performance If all modules that are fed by the peripheral clock driver PCD are disabled and also the other functions fed by the PCD are not required this clock driver itself may also be disabled to save additional power This flexibility is realized by distributing the CPU clock via several clock drivers which can be separately controlled and may also be smaller CCD Idle Mode e gt CPU Generation PCD PCDDIS Peripherals d Ports Intr Ctrl ICD Interface gt Peripherals FOUT MCA04479 Figure 21 5 CPU Clock Distribution Note The Real Time Clock RTC is fed by a separate clock driver so it can be kept running even in Power Down mode while still all the other circuitry is disconnected from the clock The registers of the generic peripherals can be accessed even while the respective module is disabled as long as PCD is running the registers of peripherals which are connected to ICD can be accessed even in this case of course The registers of X peripherals cannot be accessed while the respective modu
499. s compare value is continuously compared with the contents of the allocated timer TO T1 or T7 T8 If the current timer contents match the compare value an appropriate output signal which is based on the selected compare mode can be generated at the corresponding output pin CCxIO and the associated interrupt request flag CCxIR is set which can generate an interrupt request if enabled As for capture mode the compare registers are also processed sequentially during compare mode When two or more compare registers are programmed to the same compare value their corresponding interrupt request flags will be set to 1 and the selected output signals will be generated within 8 CPU clock cycles after the allocated timer is incremented to this compare value Further compare events on the same compare value are disabled until the timer is incremented again or written to by software After a reset compare events for register CCx will only become enabled if the allocated timer has been incremented or written to by software and one of the compare modes described in the following has been selected for this register The different compare modes which can be programmed for a given compare register CCx are selected by the mode control field CCMODx in the associated capture compare mode control register In the following each of the compare modes including the special double register mode is discussed in detail Compare Mode 0 This is a
500. s Inputs Outputs Analog Extension Inputs MCA04425 Figure 7 8 User s Manual PORTI1 IO and Alternate Functions 7 18 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports PORTI1 Digital Input Control The pins of P1L may be used for both digital an analog input By setting the respective bit in register P1DIDIS the digital input stage of the respective P1L pin can be disconnected from the pin This is recommended when the pin is to be used as analog input as it reduces the current through the digital input stage and prevents it from toggling while the analog input level is between the digital low and high thresholds So the consumed power and the generated noise can be reduced After reset all digital input stages are enabled P1DIDIS P1L Digital Inp Disable Reg SFR FEA44 524 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 P1D P1D P1D P1D P1D P1D P1D P1D 7 6 5 4 3 2 1 0 Bit Function P1D y Port P1L Bit y Digital Input Control 0 Digital input stage connected to port line P1L y 1 Digital input stage disconnected from port line P1L y When being read or used as alternate input this line appears as 1 Figure 7 9 shows the structure of PORT1 pins The upper 4 pins of PORT1 combine internal bus data and alternate data output before the port latch input User s Manual 7 19 V2 0 2000 07 o I
501. s a different address window than the one controlled by this BUSCON register RDYENx READY Input Enable 0 External bus cycle is controlled by bit field MCTC only q1 External bus cycle is controlled by the READY input signal User s Manual 9 23 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Bit Function CSRENx _ Read Chip Select Enable EN 0 The CS signal is independent of the read command RD q1 The CS signal is generated for the duration of the read command CSWENx Write Chip Select Enable 0 The CS signal is independent of the write cmd WR WRL WRH abe The CS signal is generated for the duration of the write command 1 A BUSCON switch waitstate is enabled by bit BUSCONx BSWOx of the address window that is left Note BUSCONO is initialized with 00CO if pin EA is high during reset If pin EA is low during reset bits BUSACTO and ALECTLO are set 1 and bit field BTYP is loaded with the bus configuration selected via PORTO User s Manual 9 24 V2 0 2000 07 d nfineon ed technologies Derivatives The External Bus Interface ADDRSEL1 Address Select Register 1 SFR FF18 0C Reset Value 00004 15 14
502. s are stopped The real time clock and its selected oscillator may optionally be kept running Sleep mode can be terminated by any reset or interrupt request mainly hardware requests stopped peripherals cannot generate interrupt requests In Power Down Mode both the CPU and the peripherals are stopped The real time clock and its selected oscillator may optionally be kept running Power Down mode can only be terminated by a hardware reset Note All external bus actions are completed before ldle or Power Down mode is entered However Idle or Power Down mode is not entered if READY is enabled but has not been activated driven low during the last bus access In addition the power management selects the current CPU frequency and controls which peripherals are active During Slow Down Operation the basic clock generation path is bypassed and the CPU clock is generated via the programmable Slow Down Divider SDD from the selected oscillator clock signal Peripheral Management disables and enables the on chip peripheral modules independently reducing the amount of clocked circuitry including the respective clock drivers User s Manual 21 2 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management 21 1 Idle Mode The power consumption of the C167CS microcontroller can be decreased by entering Idle mode In this mode all enabled peripherals including the watchdog timer continue to operate normally only the C
503. s common module interrupt is controlled by the PWM Module Interrupt Control register PWMIC The interrupt service routine can determine the active channel interrupt s from the channel specific interrupt request flags PIRx in register PWMCONO The interrupt request flag PIRx of a channel is set at the beginning of a new PWM cycle i e upon latching the shadow registers LSR This indicates that registers PPx and PWx are now ready to receive a new value If a channel interrupt is enabled via its respective PIEx bit also the common interrupt request flag PWMIR in register PWMIC is set provided that it is enabled via the common interrupt enable bit PWMIE Note The channel interrupt request flags PIRx in register PWMCONO are not automatically cleared by hardware upon entry into the interrupt service routine so they must be cleared via software The module interrupt request flag PWMIR is cleared by hardware upon entry into the service routine regardless of how many channel interrupts were active However it will be set again if during execution of the service routine a new channel interrupt request is generated PWMIC PWM Intr Ctrl Reg ESFR F1 7E BFy Reset Value 00H 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWMIPWM IR IE ILVL GLVL rwh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 17 14
504. s either 00 E7FE 00 D7FE for single word instructions or 00 E7FC 00 D7FC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from XRAM to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for XRAM operands Any word data access is made to an even byte address The highest possible word data storage location in the XRAM is 00 E7FE 00 D7FEy For PEC data transfers the XRAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers Note As the XRAM appears like external memory it cannot be used for the C167CS s system stack or register banks The XRAM is not provided for single bit storage and therefore is not bitaddressable The on chip XRAM is accessed with the following bus cycles Normal ALE Nocycle time waitstates no READY control e No tristate time waitstate No Read Write delay 16 bit demultiplexed bus cycles 4 TCL Even if the XRAM is used like external memory it does not occupy BUSCONx ADDRSELx registers but rather is selected via additional dedicated XBCON XADRS registers These registers are mask programmed and are not user accessible With these registers the address areas 00 E000 to 00 E7FF and 00 C000 to 00 DFFF a
505. s in the ALU Additionally the condition flags in the PSW register are updated as specified by the instruction All explicit writes to the SFR memory space and all auto increment or auto decrement writes to GPRs used as indirect address pointers are performed during the execute stage of an instruction too 4th _ WRITE BACK In this stage all external operands and the remaining operands within the internal RAM space are written back A particularity of the C167CS are the so called injected instructions These injected instructions are generated internally by the machine to provide the time needed to process instructions which cannot be processed within one machine cycle They are automatically injected into the decode stage of the pipeline and then they pass through the remaining stages like every standard instruction Program interrupts are performed by means of injected instructions too Although these internally injected instructions will not be noticed in reality they are introduced here to ease the explanation of the pipeline in the following User s Manual 4 3 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU Sequential Instruction Processing Each single instruction has to pass through each of the four pipeline stages regardless of whether all possible stage operations are really performed or not Since passing through one pipeline stage takes at least one machine cycle any isolated in
506. s like a software reset are therefore only executed if the complete instruction is decoded without an error This enhances the safety and reliability of a microcontroller system User s Manual 24 4 V2 0 2000 07 o nfineon e technologies Derivatives Device Specification 25 Device Specification The device specification describes the electrical parameters of the device It lists DC characteristics like input output or supply voltages or currents and AC characteristics like timing characteristics and requirements Other than the architecture the instruction set or the basic functions of the C167CS core and its peripherals these DC and AC characteristics are subject to changes due to device improvements or specific derivatives of the standard device Therefore these characteristics are not contained in this manual but rather provided in a separate Data Sheet which can be updated more frequently Please refer to the current version of the Data Sheet of the respective device for all electrical parameters Note In any case the specific characteristics of a device should be verified before a new design is started This ensures that the used information is up to date Figure 25 1 shows the pin diagram of the C167CS It shows the location of the different supply and IO pins A detailed description of all the pins is also found in the Data Sheet Note Not all alternate functions shown in the figure below are supported by all de
507. s overhead is not critical for low rate requests This node sharing is controlled via the sub node interrupt control register ISNC which provides a separate request flag and enable bit for each supported request source The interrupt level used for arbitration is determined by the node control register IC ISNC Interrupt Sub Node Ctrl Reg ESFR F1DE EF Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PLL PLL RTC RTC IE IR IE IR rw rw rw rw Bit Function xxIR Interrupt Request Flag for Source xx 0 No request from source xx pending ile Source xx has raised an interrupt request xxIE Interrupt Enable Control Bit for Source xx 0 Source xx interrupt request is disabled 1 Source xx interrupt request is enabled Table 5 7 Sub Node Control Bit Allocation Bit pos Interrupt Source Associated Node 15 4 Reserved Reserved 3 2 PLL OWD XP3IC 1 0 HIC XP3IC Note In order to ensure compatibility with other derivatives application software should never set reserved bits within register ISNC User s Manual 5 25 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 8 External Interrupts Although the C167CS has no dedicated INTR input pins it provides many possibilities to react on external asynchronous events by using a number of IO lines for interrupt input The
508. s provides portability of the current software to future devices After read accesses reserved bits should be ignored or masked out User s Manual 2 12 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview Serial Channels Serial communication with other microcontrollers processors terminals or external peripheral components is provided by two serial interfaces with different functionality an Asynchronous Synchronous Serial Channel ASCO and a High Speed Synchronous Serial Channel SSC The ASCO is upward compatible with the serial ports of the Infineon 8 bit microcontroller families It supports full duplex asynchronous communication at up to 780 1030 KBaud and half duplex synchronous communication at up to 3 1 4 1 MBaud 25 33 MHz CPU clock A dedicated baud rate generator allows to set up all standard baud rates without oscillator tuning For transmission reception and error handling 4 separate interrupt vectors are provided In asynchronous mode 8 or 9 bit data frames are transmitted or received preceded by a start bit and terminated by one or two stop bits For multiprocessor communication a mechanism to distinguish address from data bytes has been included 8 bit data plus wake up bit mode In synchronous mode the ASCO transmits or receives bytes 8 bits synchronously to a shift clock which is generated by the ASCO The ASCO always shifts the LSB first A loop back option is available for test
509. s stack access to the user in either the internal or external memory Both stack types grow from high memory addresses to low memory addresses Internal System Stack A system stack is provided to store return vectors segment pointers and processor status for procedures and interrupt routines A system register SP points to the top of the stack This pointer is decremented when data is pushed onto the stack and incremented when data is popped The internal system stack can also be used to temporarily store data or pass it between subroutines or tasks Instructions are provided to push or pop registers on from the system stack However in most cases the register banking scheme provides the best performance for passing data between multiple tasks Note The system stack allows the storage of words only Bytes must either be converted to words or the respective other byte must be disregarded Register SP can only be loaded with even byte addresses The LSB of SP is always 0 Detection of stack overflow underflow is supported by two registers STKOV Stack Overflow Pointer and STKUN Stack Underflow Pointer Specific system traps Stack Overflow trap Stack Underflow trap will be entered whenever the SP reaches either boundary specified in these registers The contents of the stack pointer are compared to the contents of the overflow register whenever the SP is DECREMENTED either by a CALL PUSH or SUB instruction An overflow tra
510. s the same as described for the core timer T3 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch for T2 and T4 Timers T2 and T4 in Incremental Interface Mode When the auxiliary timers T2 and T4 are programmed to incremental interface mode their operation is the same as described for the core timer T3 The descriptions figures and tables apply accordingly User s Manual 10 13 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timers T2 and T4 in Counter Mode Counter mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TXCON to 001g In counter mode timers T2 and T4 can be clocked either by a transition at the respective external input pin TxIN or by a transition of timer T3 s output toggle latch T3OTL Edge Select A Interrupt Auxiliary Timer Tx Request Up Down MCB02221 X224 Figure 10 10 Block Diagram of an Auxiliary Timer in Counter Mode The event causing an increment or decrement of a timer can be a positive a negative or both a positive and a negative transition at either the respective input pin or at the toggle latch T3OTL Bit field Txl in the respective control register TXCON selects the triggering transition see Table 10 8 User s Manual 10 14 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpos
511. s to power Active if not running basic clock source consumption disabled via bit OWDDIS PLL PLL causes no PLL must lock before Disabled off additional power switching back to the consumption basic clock source if the PLL is the basic clock source All these clock options are selected via bitfield CLKCON in register SYSCONO2 A state machine controls the switching mechanism itself and ensures a continuous and glitch free clock signal to the on chip logic This is especially important when switching back to PLL frequency when the PLL has temporarily been switched off In this case the clock source can be switched back either automatically as soon as the PLL is locked again indicated by bit CLKLOCK in register SYSCON2 or manually i e under software control after bit CLKLOCK has become 1 The latter way is preferable if the application requires a defined point where the frequency changes Note When the PLL is the basic clock source and a reset occurs during SDD operation with the PLL off the internal reset condition is extended so the PLL can lock before execution begins The reset condition is terminated prematurely if no stable oscillator clock is detected This ensures the operability of the device in case of a missing input clock signal Switching to Slow Down operation affects frequency sensitive peripherals like serial interfaces timers PWM etc If these units are to be operated in Slow Down mode their precalers or
512. s to switch between different bus modes dynamically i e subsequent external bus cycles may be executed in different ways Certain address areas may use multiplexed or demultiplexed buses or use READY control or predefined waitstates A change of the external bus characteristics can be initiated in two different ways Switching between predefined address windows automatically selects the bus mode that is associated with the respective window Predefined address windows allow to use different bus modes without any overhead but restrict their number to the number of BUSCONSs However as BUSCONO controls all address areas which are not covered by the other BUSCONs this allows to have gaps between these windows which use the bus mode of BUSCONO PORT will output the intra segment address when any of the BUSCON registers selects a demultiplexed bus mode even if the current bus cycle uses a multiplexed bus mode This allows to have an external address decoder connected to PORT1 only while using it for all kinds of bus cycles The usage of the BUSCON ADDRSEL registers is controlled via the issued addresses When an access code fetch or data is initiated the respective generated physical address defines if the access is made internally uses one of the address windows defined by ADDRSEL4 1 or uses the default configuration in BUSCONO After initializing the active registers they are selected and evaluated automatically by interpreting
513. s until it reaches the value 00004 Upon the next count pulse the count direction is reversed again and the count cycle is repeated with the following count pulses The PWM output signal is switched to a high level when the timer contents are equal to or greater than the contents of the pulse width shadow register while the timer is counting up The signal is switched back to a low level when the respective timer has counted down to a value below the contents of the pulse width shadow register So in mode 1 this PWM value controls both edges of the output signal Note that in mode 1 the period of the PWM signal is twice the period of the timer PWM Periodyoge 2 x PPx 1 Figure 17 4 illustrates the operation and output waveforms of a PWM channel in mode 1 for different values in the pulse width register This mode is referred to as Center Aligned PWM because the value in the pulse width shadow register effects both edges of the output signal symmetrically User s Manual 17 5 V2 0 2000 07 technologies C167CS Derivatives The Pulse Width Modulation Module PPx Period 7 PTx Count Value PWx Pulse Width 0 PWx 1 PWx 2 PWx 4 PWx 6 PWx 7 PWx 8 Duty Cycle 100 87 5 7596 50 25 12 5 0 LSR Change Count LSR Latch Shadow Direction Register Interrupt Request MCA01950 Figure 17 4 Operation an
514. sabled and limited access to the internal code memory All code fetches from the internal ROM area 000000 00 7FFF or 01 0000 01 7FFFy if mapped to segment 1 are redirected to the special Boot ROM Data fetches access will access the internal code memory of the C167CS if any is available but will return undefined data on ROMless devices Note Data fetches from a protected ROM will not be executed 15 3 Exiting Bootstrap Loader Mode In order to execute a program in normal mode i e watchdog timer active full access to user memory etc the BSL mode must be terminated first The C167CS exits BSL mode in two ways upon a software reset ignoring the external configuration POL 4 or RD upon a hardware reset not configuraing BSL mode After the non BSL reset the C167CS will start executing out of user memory as externally configured via PORTO or RD ALE depending on EA User s Manual 15 5 V2 0 2000 07 o nfineon e technologies Derivatives The Bootstrap Loader 15 4 Choosing the Baudrate for the BSL The calculation of the serial baudrate for ASCO from the length of the first zero byte that is received allows the operation of the bootstrap loader of the C167CS with a wide range of baudrates However the upper and lower limits have to be kept in order to ensure proper data transfer B MEE C167CS 7 32 SOBRL 1 The C167CS uses timer T6 to measure the length of the initial zero byte The quantizati
515. set condition is prolonged until RSTIN gets inactive indicated as long hardware reset LHWR During a hardware reset the inputs for the reset configuration PORTO RD ALE need some time to settle on the required levels especially if the hardware reset aborts a read operation from an external peripheral During this settling time the configuration may intermittently be wrong For the duration of one internal reset sequence after a reset has been recognized the configuration latches are not transparent i e the new configuration becomes valid earliest after the completion of one reset sequence This usually covers the required settling time When the basic clock is generated by the PLL the internal reset condition is automatically extended until the on chip PLL has locked The input RSTIN provides an internal pullup device equalling a resistor of 50 kO to 250 kO the minimum reset time must be determined by the lowest value Simply connecting an external capacitor is sufficient for an automatic power on reset see b in Figure 20 1 RSTIN may also be connected to the output of other logic gates see a in Figure 20 1 See also Bidirectional Reset on Page 20 4 in this case Note A power on reset requires an active time of two reset sequences 1036 CPU clock cycles after a stable clock signal is available about 10 50 ms depending on the oscillator frequency to allow the on chip oscillator to stabilize User s Manu
516. setting bit SUE User s Manual 20 22 V2 0 2000 07 o nfineon ed technologies Derivatives RSTCON Reset Control System Reset Register mem F1E0 Reset Value 00XX 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CLKCFG SALSEL CSSEL SUE RSTLEN rw rw rw rw rw Bit Function RSTLEN Reset Length Control duration of the next reset sequence to occur 1 00 1024 TCL standard duration corresponds to all other derivatives without control function 01 2048 TCL extended duration may be useful e g to provide additional settling for external configuration signals at high CPU clock frequencies 10 Reserved 11 Reserved SUE Software Update Enable 0 Configuration cannot be changed via software 1 Software update of configuration is enabled CSSEL Chip Select Line Selection Number of active CS outputs 00 SCSlines CS2 CSO 01 2 CS lines CS1 CSO 10 No CS lines atall 11 all CS lines CSx CSO SALSEL Segment Address Line Selection Number of active seg addr outputs 00 4 bit segment address A19 A16 01 No segment address lines at all 10 full segment address Axx A16 11 2 bit segment address A17 A16 CLKCFG Clock Generation Mode Configuration These pins define the clock generation mode i e the mechanism how the the internal CPU clock is generated from the externally applied XTAL1 input clock 0
517. sion will normally have its output drivers switched However in order to avoid possible conflicts or misinterpretations it is recommended to always load the slave s transmit buffer prior to any transfer Register SSCCON Register SSCEIC SSCTEN Transmit Error BODIE SSCREN Receive SSCEIE Error Error SSCRE Interrupt 21 u a SSCEINT SSCPEN Phase Error iniri SSCBEN Baudrate SscoE SSCBE Error ssose MCA01968 Figure 12 6 SSC Error Interrupt Control User s Manual 12 16 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 7 SSC Interrupt Control Three bit addressable interrupt control registers are provided for serial channel SSC Register SSCTIC controls the transmit interrupt SSCRIC controls the receive interrupt and SSCEIC controls the error interrupt of serial channel SSC Each interrupt source also has its own dedicated interrupt vector SCTINT is the transmit interrupt vector SCRINT is the receive interrupt vector and SCEINT is the error interrupt vector The cause of an error interrupt request receive phase baudrate transmit error can be identified by the error status flags in control register SSCCON Note In contrary to the error interrupt request flag SSCEIR the error status flags SSCxE are not reset automatically upon entry into the error interrupt service routine but must be cleared by software
518. software error was due to hardware related failures This prevents the controller from malfunctioning for longer than a user specified time Note When the bidirectional reset is enabled also pin RSTIN will be pulled low for the duration of the internal reset sequence upon a software reset or a watchdog timer reset The watchdog timer provides two registers aread only timer register that contains the current count and e acontrol register for initialization and reset source detection Reset Indication Pins Data Registers Control Registers RSTOUT deactivated by EINIT WDT WDTCON J RSTIN bidirectional reset only MCA04381 Figure 13 1 SFRs and Port Pins Associated with the Watchdog Timer The watchdog timer is a 16 bit up counter which is clocked with the prescaled CPU clock fcpu The prescaler divides the CPU clock by 2 WDTIN 0 WDTPRE 0 or by 4 WDTIN 0 WDTPRE 1 or by 128 WDTIN 1 WDTPRE 0 or by 256 WDTIN 1 WDTPRE 1 User s Manual 13 1 V2 0 2000 07 o nfineon e technologies Derivatives The Watchdog Timer WDT The 16 bit watchdog timer is realized as two concatenated 8 bit timers see Figure 13 2 The upper 8 bits of the watchdog timer can be preset to a user programmable value via a watchdog service access in order to vary the watchdog expire time The lower 8 bits are reset upon each service access WDT
519. specifies counting up and a low level specifies counting down The count direction can be changed regardless of whether the timer is running or not When pin T3EUD P3 4 is used as external count direction control input it must be configured as input i e its corresponding direction control bit DP3 4 must be set to 0 Table 10 1 GPT1 Core Timer T3 Count Direction Control Pin TXEUD Bit TXUDE Bit TxUD Count Direction X 0 0 Count Up X 0 1 Count Down 0 1 0 Count Up 1 1 0 Count Down 0 1 1 Count Down 1 1 1 Count Up Note The direction control works the same for core timer T3 and for auxiliary timers T2 and T4 Therefore the pins and bits are named Tx User s Manual 10 4 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer 3 Output Toggle Latch An overflow or underflow of timer T3 will clock the toggle bit T3OTL in control register T3CON T3OTL can also be set or reset by software Bit T3OE Alternate Output Function Enable in register T3CON enables the state of T3OTL to be an alternate function of the external output pin T3OUT For that purpose a 1 must be written into the respective port data latch and pin TSOUT must be configured as output by setting the corresponding direction control bit to 1 If TSOE 1 pin TSOUT then outputs the state of TSOTL If T3OE 0 pin T3OUT can be used as general purpose IO pin In a
520. ss area the respective CSx signal will go inactive high At the beginning of each external bus cycle the corresponding valid CS signal is determined and activated All other CS lines are deactivated driven high at the same time Note The CSx signals will not be updated for an access to any internal address area i e when no external bus cycle is started even if this area is covered by the respective ADDRSELx register An access to an on chip X Peripheral deactivates all external CS signals Nu A Upon accesses to address windows without a selected CS line all selected CS lines are deactivated The chip select signals allow to be operated in four different modes see Table 9 5 which are selected via bits CSWENx and CSRENXx in the respective BUSCONXx register Table 9 5 Chip Select Generation Modes CSWENx CSRENx _ Chip Select Mode 0 0 Address Chip Select Default after Reset 0 1 Read Chip Select 1 0 Write Chip Select 1 1 Read Write Chip Select User s Manual 9 10 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Read or Write Chip Select signals remain active only as long as the associated control signal RD or WR is active This also includes the programmable read write delay Read chip select is only activated for read cycles write chip select is only activated for write cycles read write chip select is activated for both read and write cycles write cycles
521. ssing and if required restricting CPU accesses to the CAN module until the anticipated updating is complete PCIR Port Control Interrupt Register XReg EF024 Reset Value XXXXy 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved IPC INTID rw rh Bit Function INTID Interrupt Identifier This number indicates the cause of the interrupt if pending 004 Interrupt Idle There is no interrupt request pending 014 Status Change Interrupt The CAN controller has updated not necessarily changed the status in the Control Register This can refer to a change of the error status of the CAN controller EIE is set and BOFF or EWRN change or to a CAN transfer incident SIE must be set like reception or transmission of a message RXOK or TXOK is set or the occurrence of a CAN bus error LEC is updated The CPU may clear RXOK TXOK and LEC however writing to the status partition of the Control Register can never generate or reset an interrupt To update the INTID value the status partition of the Control Register must be read 024 Message 15 Interrupt Bit INTPND in the Message Control Register of message object 15 last message has been set The last message object has the highest interrupt priority of all message objects 02 N Message N Interrupt Bit INTPND in the Message Control Register of message object N has been set N 1 14 Note that a message inte
522. st possible code storage location in the internal Program Memory is either xx xxFE for single word instructions or xx xxFC for double word instructions The respective location must contain a branch instruction unconditional because sequential boundary crossing from internal Program Memory to external memory is not supported and causes erroneous results Any word and byte data read accesses may use the indirect or long 16 bit addressing modes There is no short addressing mode for internal ROM operands Any word data access is made to an even byte address The highest possible word data storage location in the internal ROM is xx xxFEy For PEC data transfers the internal Program Memory can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The internal Program Memory is not provided for single bit storage and therefore it is not bit addressable Note The x in the locations above depend on the available Program Memory and on the mapping The internal ROM may be enabled disabled or mapped into segment 0 or segment 1 under software control Chapter 22 shows how to do this and reminds of the precautions that must be taken in order to prevent the system from crashing User s Manual 3 3 V2 0 2000 07 C167CS Derivatives technologies Memory Organization 3 2 Internal RAM and SFR Area The RAM SFR area is located within data page 3 and provides access to the i
523. start PLL Next access to ESFR space SPLLIE 1 i e 21 24 PLL interrupt enabled V2 0 2000 07 technologies C167CS Derivatives SDD EXIT MANUAL MOV SYSCON2 ZEROS EXTR 44H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 01H USER_CODE CLOCK_OK EXTR 1H MOV SYSCON2 ZEROS EXTR 4H BFLDL SYSCON2 0FH 09H MOV SYSCON2 0003H BSET SYSCON2 2 BFLDH SYSCON2 03H 00H EXTR 1H BSET ISNC 2 User s Manual Currently running on SDD Clear bits 3 0 Switch Unlock sequence Unlock sequence Unlock sequence Single access to CLKCON 01B 5stay on SDD start PLL Power Management T frequency no EXTR required here to ESFR space and lock sequence step 1 1001B step 2 0011B step 3 0111B one locked register Space for any user code that pee must or can be executed before Switching back to basic clock Next access to ESFR space JNB SYSCON2 15 CLOCK_OK Wait until clock OK CLKLOCK 1 Clear bits 3 0 Switch Unlock sequence Unlock sequence Unlock sequence Single access to CLKCON 00B basic frequency uk Next access to ESFR space LLIE 1 i e 21 25 no EXTR required here to ESFR space and lock sequence step 1 1001B step 2 0011B step 3 0111B one locked register PLL interrupt enabled V2 0 2000 07 o nfineo
524. state is controlled in the same way as the waitstate when switching from demultiplexed to multiplexed bus mode see Figure 9 4 BUSCON switch waitstates are enabled via bits BSWCx in the BUSCON registers By enabling the automatic BUSCON switch waitstate BSWOx 1 there is no impact on the system performance as long as the external bus cycles access the same address window Only if the following cycle accesses a different window a waitstate is inserted between the last access to the previous window and the first access to the new window After reset no BUSCON switch waitstates are selected User s Manual 9 7 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface External Data Bus Width The EBC can operate on 8 bit or 16 bit wide external memory peripherals A 16 bit data bus uses PORTO while an 8 bit data bus only uses POL the lower byte of PORTO This saves on address latches bus transceivers bus routing and memory cost on the expense of transfer time The EBC can control word accesses on an 8 bit data bus as well as byte accesses on a 16 bit data bus Word accesses on an 8 bit data bus are automatically split into two subsequent byte accesses where the low byte is accessed first then the high byte The assembly of bytes to words and the disassembly of words into bytes is handled by the EBC and is transparent to the CPU and the programmer Byte accesses on a 16 bit data bus require that the
525. stored in the cache after having been fetched After each repeatedly following execution of the same cache jump instruction the jump target instruction is not fetched from program memory but taken from the cache and immediately injected into the decode stage of the pipeline see Figure 4 4 A time saving jump on cache is always taken after the second and any further occurrence of the same cache jump instruction unless an instruction which has the fundamental capability of changing the CSP register contents JMPS CALLS RETS TRAP RETI or any standard interrupt has been processed during the period of time between two following occurrences of the same cache jump instruction Injection of Cached Injection Target Instruction 1 Machine Cycle Y Y FETCH Inyo TARGET IrARGET To TARGET IrARGET 2 DECODE Cache Jmp insect TARGET Cache Jmp TARGET TIrARGET EXECUTE I Cache Jmp ZNgect I Cache Jmp lancer WRITEBACK oi L Cache Jmp a L Cache Jmp 1st Loop Iteration Repeated Loop Iteration MCT04329 Figure 4 4 Cache Jump Instruction Pipelining User s Manual 4 5 V2 0 2000 07 o nfineon e technologies Derivatives The Central Processing Unit CPU 4 2 Particular Pipeline Effects Since up to four different instructions are processed simultaneously additional hardware has been spent in the C167CS to consider all causal dependencies which ma
526. struction takes at least four machine cycles to be completed Pipelining however allows parallel i e simultaneous processing of up to four instructions Thus most of the instructions seem to be processed during one machine cycle as soon as the pipeline has been filled once after reset see Figure 4 2 Instruction pipelining increases the average instruction throughput considered over a certain period of time In the following any execution time specification of an instruction always refers to the average execution time due to pipelined parallel instruction processing 1 Machine Cycle e FETCH I I I L I A DECODE I I i L i EXECUTE I I L L WRITEBACK i I Time MCT04327 Figure 4 2 Sequential Instruction Pipelining Standard Branch Instruction Processing Instruction pipelining helps to speed sequential program processing In the case that a branch is taken the instruction which has already been fetched providently is mostly not the instruction which must be decoded next Thus at least one additional machine cycle is normally required to fetch the branch target instruction This extra machine cycle is provided by means of an injected instruction see Figure 4 3 1 Machine Cycle Injection a v FETCH BRANCH I n 2 TraRGet TTARGET 1 TTARGET 2 I rARGET 3 DECODE I n BRANCH Insect I RGET TARGET I ARGET 2 EXECUTE
527. supply voltage is applied This enables a system to determine the current time and the duration of the period while it was down by comparing the current time with a timestamp stored when Power Down mode was entered The supply current in this case remains well below 1 mA During power down the voltage at the Vpp pins can be lowered to 2 7 V while the RTC and its selected oscillator will still keep on running and the contents of the internal RAM will still be preserved When the RTC and oscillator is disabled the internal RAM is preserved down to a voltage of 2 5 V Note When the RTC remains active in Power Down mode also the oscillator which generates the RTC clock signal will keep on running of course If the supply voltage is reduced the specified maximum CPU clock frequency for this case must be respected The total power consumption in Power Down mode depends on the active circuitry i e RTC on or off and on the current that flows through the port drivers To minimize the consumed current the RTC and or all pin drivers can be disabled pins switched to tristate via a central control bitfield in register SYSCON2 If an application requires one or more port drivers to remain active even in Power Down mode also individual port drivers can be disabled simply by configuring them for input The bus interface pins can be separately disabled by releasing the external bus disable all address windows by clearing the BUSACT bits and switching t
528. t Valid values for TSEG2 are 1 7 Note This register can only be written if the config change enable bit CCE is set Hard Synchronization and Resynchronization To compensate phase shifts between clock oscillators of different CAN controllers any CAN controller has to synchronize on any edge from recessive to dominant bus level if the edge lies between a Sample Point and the next Synchronization Segment and on any other edge if it itself does not send a dominant level If the Hard Synchronization is enabled at the Start of Frame the bit time is restarted at the Synchronization Segment otherwise the Resynchronization Jump Width SJW defines the maximum number of time quanta by which a bit time may be shortened or lengthened during one Resynchronization The current bit time is adjusted by Note SJW is the programmed numerical value from the respective field of the Bit Timing Register User s Manual 19 13 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Calculation of the Bit Time The programming of the bit time according to the CAN Specification depends on the desired baudrate the XCLK frequency and on the external physical delay times of the bus driver of the bus line and of the input comparator These delay times are summarized in the Propagation Time Segment tp op where tProp S two times the maximum of the sum of physical bus delay the input comparator
529. t 0 Ignore phase errors 1 Check phase errors SSCBEN SSC Baudrate Error Enable Bit 0 Ignore baudrate errors 25 Check baudrate errors SSCAREN SSC Automatic Reset Enable Bit 0 No additional action upon a baudrate error 1 The SSC is automatically reset upon a baudrate error SSCMS SSC Master Select Bit 0 Slave Mode Operate on shift clock received via SCLK 1 Master Mode Generate shift clock and output it via SCLK SSCEN SSC Enable Bit 0 Transmission and reception disabled Access to control bits User s Manual 12 3 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface SSCCON SSC Control Reg Op M SFR FFB24 D9 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SSC SSC SSC SSC SSC SSC SSC EN l MS BSY BE PE RE TE SSOBD rw rw rw rw rw rw rw 5 r Bit Function Operating Mode SSCEN 1 SSCBC SSC Bit Count Field Shift counter is updated with every shifted bit Do not write to SSCTE SSC Transmit Error Flag 1G Transfer starts with the slave s transmit buffer not being updated SSCRE SSC Receive Error Flag q1 Reception completed before the receive buffer was read SSCPE SSC Phase Error Flag i Received data changes around sampling clock edge SSCBE SSC Baudrate Error Flag E More than factor 2 or less than factor 0 5 between Slave s actual
530. t 0 Main oscillator is unstable or PLL is unlocked 5 Main oscillator is stable and PLL is locked Note SYSCON except for bitfield SYSRLS of course is write protected after the execution of EINIT unless it is released via the unlock sequence see Table 21 6 User s Manual 21 12 V2 0 2000 07 o nfineon ed technologies Derivatives Power Management XX y State Transition when writing xx to CLKCON Automatic Transition after clock is stable i e CLKLOCK 1 01 MCA04478 Figure 21 4 Clock Switching State Machine Table 21 3 Clock Switching State Description State PLL fcPu CLK Note Number Status Source CON 1 Locked Basic 00 Standard operation on basic clock frequency 2 Locked SDD 01 SDD operation with PLL On Fast without delay or manual switch back from 5 to basic clock frequency 3 Transient SDD 00 Intermediate state leading to state 1 4 Transient SDD 01 Intermediate state leading to state 2 5 Off SDD 10 SDD operation with PLL Off Reduced power consumption The indicated PLL status only applies if the PLL is selected as the basic clock source If the basic clock source is direct drive or prescaler the PLL will not lock If the oscillator watchdog is disabled OWDDIS 1 the PLL will be off User s Manual 21 13 V2 0 2000 07 o nfineon ed technologies Derivative
531. t Clock CAPCOM Timer Ty gt Request Xx 31 0 y 0 1 7 8 MCB02015 Figure 16 5 Capture Mode Block Diagram In order to use the respective port pin as external capture input pin CCxlO for capture register CCx this port pin must be configured as input i e the corresponding direction control bit must be set to 0 To ensure that a signal transition is properly recognized an external capture input signal should be held for at least 8 CPU clock cycles before it changes its level During these 8 CPU clock cycles the capture input signals are scanned sequentially When a timer is modified or incremented during this process the new timer contents will already be captured for the remaining capture registers within the current scanning sequence Note When the timer modification can generate an overflow the capture interrupt routine should check if the timer overflow was serviced during these 8 CPU clock cycles If pin CCxIO is configured as output the capture function may be triggered by modifying the corresponding port output latch via software e g for testing purposes User s Manual 16 13 V2 0 2000 07 o nfineon ed technologies Derivatives The Capture Compare Units 16 5 Compare Modes The compare modes allow triggering of events interrupts and or output signal transitions with minimum software overhead In all compare modes the 16 bit value stored in compare register CCx in the following also referred to a
532. t Request Mode T2IN Control Interrupt jo Request T3 Toggle FF T3IN Mode JT30UT EXE Control T3EUD Other Timers T4IN e T4 Mode Interrupt om Control GPT1 Timer T4 Peques a Mun U D T4EUD MCT02141 n 3 10 Figure 10 2 GPT1 Block Diagram User s Manual 10 2 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units 10 1 1 GPT1 Core Timer T3 The core timer T3 is configured and controlled via its bitaddressable control register T3CON T3CON Timer 3 Control Register SFR FF424 A1 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T3 T8 T3 T3 7 17 7 oiL OE JUDE uD 3R Tse T3 rwh w rw w rw rw rw Bit Function T3I Timer 3 Input Selection Depends on the operating mode see respective sections T3M Timer 3 Mode Control Basic Operating Mode 000 Timer Mode 001 Counter Mode 010 Gated Timer with Gate active low 011 Gated Timer with Gate active high 100 Reserved Do not use this combination 101 Reserved Do not use this combination 110 Incremental Interface Mode 111 Reserved Do not use this combination T3R Timer 3 Run Bit 0 Timer Counter 3 stops 1 Timer Counter 3 runs T3UD Timer 3 Up Down Control T3UDE Timer 3 External Up Down Enable TSOE Alternate Output Function Enable 0 Alternate Output Function Disable
533. t Threshold Control 0 000 7 2 Output Driver Control 0202 eee eee ee 7 3 Alternate Port Functions leen 7 4 PORTO DEMUPTTPP UT 1 5 PORTI owe 23 nada a cR a ES SERRE d fee ated ea ug sudo 7 6 POM ARP 7 7 POS uai a keeles dx adi ME dus decane urat A tir 7 8 alc n 7 9 POM Snee oe hoe hae we eae TIED 7 10 POM O PP 7 11 POI qe eae ee ee eee ee eee wees 7 12 POMS RP 8 Dedicated Pins 0 0 00 a 9 The External Bus Interface 9 1 Single Chip Mode uiae ward e Ex EE WERE ES 9 2 External Bus Modes 0 0 0 0 ccc eee eae 9 3 Programmable Bus Characteristics 9 4 READY Controlled Bus Cycles Lun 9 5 Controlling the External Bus Controller 9 6 EBC Idle State ssc ks ews cv ne daw le ens aC Kan ER 9 7 External Bus Arbitration lees 9 8 The XBUS Interface llle 9 8 1 Accessing the On chip XBUS Peripherals 9 8 2 External Accesses to XBUS Peripherals 10 The General Purpose Timer Units 10 1 Timer Block GPTT 4 sess ceca Dede REGG RR ER E 10 1 1 GPT1 Core Timer T3 ele 10 1 2 GPT1 Auxiliary Timers T2 and T4 10 1 3 Interrupt Control for GPT1 Timers 10 2 Timer Block GPT2 0 0000 c ee eee eee 10 2 1 GPT2 Core Timer T6 0 0 0 0 cee ee 10 2 2 GPT2 Auxiliary Timer T5
534. t a low level which corresponds to a duty cycle of 0 Figure 17 3 illustrates the operation and output waveforms of a PWM channel in mode 0 for different values in the pulse width register This mode is referred to as Edge Aligned PWM because the value in the pulse width shadow register only effects the positive edge of the output signal The negative edge is always fixed and related to the clearing of the timer User s Manual 17 3 V2 0 2000 07 technologies C167CS Derivatives The Pulse Width Modulation Module PPx Period 7 PTx Count Value PWx Pulse Width 0 PWx 1 PWx 2 PWx 4 PWx 6 PWx 7 PWx 8 Duty Cycle 100 87 5 75 50 25 12 5 0 LSR LSR LSR Latch Shadow Register Interrupt Request MCA01949 Figure 17 3 Operation and Output Waveform in Mode 0 User s Manual 17 4 V2 0 2000 07 o nfineon en technologies Derivatives The Pulse Width Modulation Module Mode 1 Symmetrical PWM Generation Center Aligned PWM Mode 1 is selected by setting the respective bit PMx in register PWMCON1 to 1 In this mode the timer PTx of the respective PWM channel is counting up until it reaches the value in the associated period shadow register Upon the next count pulse the count direction is reversed and the timer starts counting down now with subsequent count pulse
535. t be observed when using the bidirectional reset feature in an application Bit BDRSTEN in register SYSCON cannot be changed after EINIT After a reset bit BDRSTEN is cleared The reset indication flags always indicate a long hardware reset The PORTO configuration is treated like on a hardware reset Especially the bootstrap loader may be activated when POL 4 or RD is low Pin RSTIN may only be connected to external reset devices with an open drain output driver Ashort hardware reset is extended to the duration of the internal reset sequence User s Manual 20 4 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset 20 2 Status After Reset After a reset is completed most units of the C167CS enter a well defined default status This ensures repeatable start conditions and avoids spurious activities after reset Watchdog Timer Operation after Reset The watchdog timer starts running after the internal reset has completed It will be clocked with the internal system clock divided by 2 fcpy 2 and its default reload value is 00 4 so a watchdog timer overflow will occur 131 072 CPU clock cycles 2 x 21 after completion of the internal reset unless it is disabled serviced or reprogrammed meanwhile When the system reset was caused by a watchdog timer overflow the WDTR Watchdog Timer Reset Indication flag in register WDTCON will be set to 1 This indicates the cause of the internal reset to
536. t corresponds to the incoming message GMS Global Mask Short XReg EF06 Reset Value UFUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 1 1 1 1 1 ID28 21 rw r r r r r rw Bit Function ID28 18 Identifier 11 bit Mask to filter incoming messages with standard identifier User s Manual 19 16 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface isse Global Mask Long XReg EF08 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 13 ID28 21 rw rw LGML Lower Global Mask Long XReg EF0A Reset Value UUUU 15 14 13 12 11 10 9 9 7 6 b 4 3 2 3 0 IDA 0 0 0 0 ID12 5 rw r r r rw Bit Function ID28 0 Identifier 29 bit Mask to filter incoming messages with extended identifier User s Manual 19 17 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface UC Mask of Last Message XReg EFOC Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID17 13 ID28 21 rw rw rw LMLM Lower Mask of Last Message XReg EFOE Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDA 0 0 0 0 ID12
537. t is not bitaddressable User s Manual 3 11 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization 3 5 Crossing Memory Boundaries The address space of the C167CS is implicitly divided into equally sized blocks of different granularity and into logical memory areas Crossing the boundaries between these blocks code or data or areas requires special attention to ensure that the controller executes the desired operations Memory Areas are partitions of the address space that represent different kinds of memory if provided at all These memory areas are the internal RAM SFR area the internal ROM Flash OTP if available the on chip X Peripherals if integrated and the external memory Accessing subsequent data locations that belong to different memory areas is no problem However when executing code the different memory areas must be switched explicitly via branch instructions Sequential boundary crossing is not supported and leads to erroneous results Note Changing from the external memory area to the internal RAM SFR area takes place within segment 0 Segments are contiguous blocks of 64 KByte each They are referenced via the code segment pointer CSP for code fetches and via an explicit segment number for data accesses overriding the standard DPP scheme During code fetching segments are not changed automatically but rather must be switched explicitly The instructions JMPS CALLS and RETS will do
538. t possible word data storage location in the internal RAM is 00 FDFE For PEC data transfers the internal RAM can be accessed independent of the contents of the DPP registers via the PEC source and destination pointers The upper 256 Byte of the internal RAM 00 FDOO through 00 FDFF and the GPRs of the current bank are provided for single bit storage and thus they are bitaddressable System Stack The system stack may be defined within the internal RAM The size of the system stack is controlled by bitfield STKSZ in register SYSCON see Table 3 1 Table 3 1 System Stack Size Encoding STKSZ Stack Size words Internal RAM Addresses words 000p 256 00 FBFE 00 FA00 Default after Reset 001p 128 OO0 FBFE 00 FB00 010g 64 00 FBFE 00 FB80 011g 32 00 FBFE 00 FBCO 100p 512 00 FBFE 00 F800 101 Reserved Do not use this combination 110p Reserved Do not use this combination 111 1536 00 FDFE 00 F200 Note No circular stack For all system stack operations the on chip RAM is accessed via the Stack Pointer SP register The stack grows downward from higher towards lower RAM address locations Only word accesses are supported to the system stack A stack overflow STKOV and a stack underflow STKUN register are provided to control the lower and upper limits of the selected stack area These two stack boundary registers can be
539. t routines entered via the software TRAP instruction can be interrupted by all hardware traps or higher level interrupt requests Table 5 2 Hardware Trap Summary Exception Condition Trap Trap Vector Trap Trap Flag Vector Location Number Prio Reset Functions Hardware Reset RESET 00 00004 00 III Software Reset RESET 00 00004 00 I Watchdog Timer Overflow RESET 00 00004 00 4 I Class A Hardware Traps Non Maskable Interrupt NMI NMITRAP 00 00084 02 I Stack Overflow STKOF STOTRAP 00 00104 044 II Stack Underflow STKUF STUTRAP 00 0018 4 06 II Class B Hardware Traps Undefined Opcode UNDOPC BTRAP 00 0028 4 0A Protected Instruction Fault PRTFLT BTRAP 00 0028 OA Illegal Word Operand Access ILLOPA BTRAP 00 0028 0A Illegal Instruction Access ILLINA BTRAP 00 0028 0A Illegal External Bus Access ILLBUS BTRAP 00 0028y 0A Reserved 2Cy 3Cy OBy OFy Software Traps Any Any Current TRAP Instruction 00 0000 004 7F4 CPU 00 01F Cy Priority in steps of 4y User s Manual 5 5 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions Normal Interrupt Processing and PEC Service During each instruction cycle one out of all sources which require PEC or interrupt processing is selected according to its interrupt priority This priority of interrupts and PEC requests is programmable in two levels Each requesting
540. table improved 13 6 Reset source table improved 15 2f Description of BSL entry improved 15 7 Baudrate table added 16 7 Frequency table enhanced 16 14 Description improved 209 paragraph 17 10 Frequency and Resolution table improved 18 1 P1DAIS corrected to P1DIDIS 18 4 Sample time control added 19 2 Port 8 added C167CS Revision History V2 0 2000 07 cont d Previous Version Version 1 0 1999 05 Page Subjects major changes since last revision 19 12 Bit timing section rearranged 20 13 Figure corrected 20 18 Software configuration introduced see notes 20 19 Table enhanced for 33 MHz 20 22 Code example corrected 20 23 Address space for RSTCON corrected 21 2 SYSCON added 3 paragraph 21 15 Flash control bits removed 21 21 Frequency range table improved 21 22ff Description of security mechanism and SW examples reworked 22 5 Linear stack size corrected 23 3 Offset of RH7 corrected 23 Aff C1LAR C2LAR RSTCON added PTCR XADRS5 removed 25 2 Figure corrected pins 64 72 Controller Area Network CAN License of Robert Bosch GmbH We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document mcdocu comments infineon com Please send your proposal including a reference to this document to
541. tack is reached At this point a portion of the stacked data must be saved into external memory to create space for further stack pushes This is called stack flushing When executing a number of return or pop instructions the upper boundary since the stack empties upward to higher memory locations is reached The entries that have been previously saved in external memory must now be restored This is called stack filling Because procedure call instructions do not continue to nest infinitely and call and return instructions alternate flushing and filling normally occurs very infrequently If this is not true for a given program environment this technique should not be used because of the overhead of flushing and filling The basic mechanism is the transformation of the addresses of a virtual stack area controlled via registers SP STKOV and STKUN to a defined physical stack area within the internal RAM via hardware This virtual stack area covers all possible locations that SP can point to i e 00 F000 through 00 FFFEy STKOV and STKUN accept the same 4 KByte address range The size of the physical stack area within the internal RAM that effectively is used for standard stack operations is defined via bitfield STKSZ in register SYSCON see below Table 22 2 Circular Stack Address Transformation STKSZ Stack Size Internal RAM Addresses Words Significant Bits Words of Physical Stack of Stack Pt
542. tc depends on the intended function for a given pin Peripherals After reset the C167CS s on chip peripheral modules enter a defined default state see respective peripheral description where it is disabled from operation In order to use a certain peripheral it must be initialized according to its intended operation in the application This includes selecting the operating mode e g counter timer operating parameters e g baudrate enabling interface pins if required assigning interrupt nodes to the respective priority levels etc After these standard initialization also application specific actions may be required like asserting certain levels to output pins sending codes via interfaces latching input levels etc User s Manual 20 10 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Termination of Initialization The software initialization routine should be terminated with the EINIT instruction This instruction has been implemented as a protected instruction The execution of the EINIT instruction disables the action of the DISWDT instruction disables write accesses to reg SYSCON all configurations regarding reg SYSCON enable CLKOUT stacksize etc must be selected before the execution of EINIT disables write accesses to registers SYSCON2 and SYSCON3 further write accesses to SYSCON2 and SYSCONGS can be executed only using a special unlock mechanism clears the reset source de
543. te formula Baudrates below B ow would cause T6 to overflow In this case ASCO cannot be initialized properly and the communication with the external host is likely to fail The maximum baudrate Byig in Figure 15 3 is the highest baudrate where the deviation still does not exceed the limit i e all baudrates between Bj ow and Byigh are below the deviation limit BHign marks the baudrate up to which communication with the external host will work properly without additional tests or investigations Higher baudrates however may be used as long as the actual deviation does not exceed the indicated limit A certain baudrate marked l in Figure 15 3 may e g violate the deviation limit while an even higher baudrate marked II in Figure 15 3 stays very well below it Any baudrate can be used for the bootstrap loader provided that the following three prerequisites are fulfilled e the baudrate is within the specified operating range for the ASCO e the external host is able to use this baudrate e the computed deviation error is below the limit Table 15 2 Bootstrap Loader Baudrate Ranges fopy MHz 10 12 16 20 25 33 BMAX 312 500 375 000 500 000 625 000 781 250 1 031 250 Buigh 9 600 19 200 19 200 19 200 38 400 38 400 Bstpmin 600 600 600 1 200 1 200 1 200 Bi ow 344 412 550 687 859 1 133 User s Manual 15 7 V2 0 2000 07 o nfineon e technologies Derivatives The Bootstrap Loader Note
544. te a reset signal for the system components besides the controller itself RSTOUT will be driven active low at the begin of any reset sequence triggered by hardware the SRST instruction or a watchdog timer overflow RSTOUT stays active low beyond the end of the internal reset sequence until the protected EINIT End of Initialization instruction is executed see Figure 20 3 This allows the complete configuration of the controller including its on chip peripheral units before releasing the reset signal for the external peripherals of the system Note RSTOUT will float during emulation mode or adapt mode The Internal RAM after Reset The contents of the internal RAM are not affected by a system reset However after a power on reset the contents of the internal RAM are undefined This implies that the GPRs R15 RO and the PEC source and destination pointers SRCP7 SRCPO DSTP7 DSTPO which are mapped into the internal RAM are also unchanged after a warm reset software reset or watchdog reset but are undefined after a power on reset The Extension RAM XRAM after Reset The contents of the on chip extension RAM are not affected by a system reset However after a power on reset the contents of the XRAM are undefined Operation after Reset After the internal reset condition is removed the C167CS fetches the first instruction from the program memory location 00 0000 for a standard start As a rule this first location
545. te of T6OTL to be an alternate function of the external output pin T6OUT For that purpose a 1 must be written into the respective port data latch and pin TOUT must be configured as output by setting the respective direction control bit to 1 If TOE 1 pin TOUT then outputs the state of T6OTL If T6OE 0 pin TOUT can be used as general purpose IO pin In addition TEOTL can be used in conjunction with the timer over underflows as an input for the counter function of the auxiliary timer T5 For this purpose the state of T6OTL does not have to be available at pin TOUT because an internal connection is provided for this option An overflow or underflow of timer T6 can also be used to clock the timers in the CAPCOM units For this purpose there is a direct internal connection between timer T6 and the CAPCOM timers Timer 6 in Timer Mode Timer mode for the core timer T6 is selected by setting bitfield T6M in register TECON to 000p In this mode T6 is clocked with the internal system clock divided by a programmable prescaler which is selected by bit field T6l The input frequency frg for timer T6 and its resolution rrg are scaled linearly with lower clock frequencies fcpy as can be seen from the following formula cPU Pam 4 x 2 lt T6l gt T i Id l 2s fceu MHz fre Txl Interrupt Request o TxOUT MCB02028 T6EUD P5 10 x 6 T6OUT P3 1 n 2 9 Figure 10 17 Block Diagram
546. te through an internal reset procedure When a reset is initiated pending internal hold states are cancelled and the current internal access cycle if any is completed An external bus cycle is aborted except for a watchdog reset see description After that the bus pin drivers and the IO pin drivers are switched off tristate The internal reset procedure requires 516 CPU clock cycles in order to perform a complete reset sequence This 516 cycle reset sequence is started upon a watchdog timer overflow a SRST instruction or when the reset input signal RSTIN is latched low hardware reset The internal reset condition is active at least for the duration of the reset sequence and then until the RSTIN input is inactive and the PLL has locked if the PLL is selected for the basic clock generation When this internal reset condition is removed reset sequence complete RSTIN inactive PLL locked the reset configuration is latched from PORTO RD and ALE depending on the start mode After that pins ALE RD and WR are driven to their inactive levels Note Bit ADP which selects the Adapt mode is latched with the rising edge of RSTIN After the internal reset condition is removed the microcontroller will either start program execution from external or internal memory or enter boot mode C167CR RSTOUT External RSTIN Hardware C161CS JC Jl Voc DOTIN External a A Reset lt ixl e MH Reset 4 b Sources a
547. tection bits in register WDTCON causes the RSTOUT pin to go high this signal can be used to indicate the end of the initialization routine and the proper operation of the microcontroller to external hardware User s Manual 20 11 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset 20 4 System Startup Configuration Although most of the programmable features of the C167CS are selected by software either during the initialization phase or repeatedly during program execution there are some features that must be selected earlier because they are used for the first access of the program execution e g internal or external start selected via EA These configurations are accomplished by latching the logic levels at a number of pins at the end of the internal reset sequence During reset internal pullup pulldown devices are active on those lines They ensure inactive default levels at pins which are not driven externally External pulldown pullup devices may override the default levels in order to select a specific configuration Many configurations can therefore be coded with a minimum of external circuitry Note The load on those pins that shall be latched for configuration must be small enough for the internal pullup pulldown device to sustain the default level or external pullup pulldown devices must ensure this level Those pins whose default level shall be overridden must be pulled low high externally Make su
548. ted upon an external reset EA 0 Pin POL O is not evaluated upon a single chip reset EA 1 User s Manual 20 14 V2 0 2000 07 o nfineon ed technologies Derivatives System Reset Adapt Mode Pin POL 1 ADP selects the Adapt Mode when latched low at the end of reset In this mode the C167CS goes into a passive state which is similar to its state during reset The pins of the C167CS float to tristate or are deactivated via internal pullup pulldown devices as described for the reset state In addition also the RSTOUT pin floats to tristate rather than be driven low The on chip oscillator and the realtime clock are disabled This mode allows switching a C167CS that is mounted to a board virtually off so an emulator may control the board s circuitry even though the original C167CS remains in its place The original C167CS also may resume to control the board after a reset sequence with POL 1 high Please note that adapt mode overrides any other configuration via PORTO Default Adapt Mode is off Note When XTAL 1 is fed by an external clock generator while XTAL2 is left open this clock signal may also be used to drive the emulator device However if a crystal is used the emulator device s oscillator can use this crystal only if at least XTAL2 of the original device is disconnected from the circuitry the output XTAL2 will be driven high in Adapt Mode E Adapt mode can only be activated upon an exter
549. ter Common Transmit Receive Device 3 MCS01965 Figure 12 5 SSC Half Duplex Configuration User s Manual 12 10 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 3 Continuous Transfers When the transmit interrupt request flag is set it indicates that the transmit buffer SSCTB is empty and ready to be loaded with the next transmit data If SSCTB has been reloaded by the time the current transmission is finished the data is immediately transferred to the shift register and the next transmission will start without any additional delay On the data line there is no gap between the two successive frames E g two byte transfers would look the same as one word transfer This feature can be used to interface with devices which can operate with or require more than 16 data bits per transfer It is just a matter of software how long a total data frame length can be This option can also be used e g to interface to byte wide and word wide devices on the same serial bus Note Of course this can only happen in multiples of the selected basic data width since it would require disabling enabling of the SSC to reprogram the basic data width on the fly User s Manual 12 11 V2 0 2000 07 o nfineon ed technologies Derivatives The High Speed Synchronous Serial Interface 12 4 The SSC uses three pins of Port 3 to communicate with the e
550. ter MSGVAL 1 XTD application cpecific Initialization Process Start Process message contents NEWDAT 0 gt Process v A Process End Restart process 0 Reset 1 Set MCA04399 Figure 19 10 CPU Handling of the Last Message Object User s Manual 19 29 V2 0 2000 07 C167CS Derivatives The On Chip CAN Interface technologies Reset CPU releases Buffer 2 CPU releases Buffer 1 Buffer 1 Released Buffer 2 Released CPU access to Buffer 2 Store received CPU allocates Buffer 2 message into Buffer 1 Buffer 1 Released Buffer 1 Allocated Buffer 2 Allocated Buffer 2 Released CPU access to Buffer 2 CPU access to Buffer 1 Store received Store received message message into Buffer 1 into Buffer 2 Buffer 1 Allocated Buffer 1 Allocated Buffer 2 Allocated Buffer 2 Allocated CPU access to Buffer 2 CPU access to Buffer 1 Store received CPU releases CPU releases Store received message into Buffer 2 Buffer 1 message into Buffer 1 Buffer 2 MSGLST is set MSGLST is set Allocated NEWDAT 1 or RMTPND 1 Released NEWDAT 0 and RMTPND 0 MCA04400 Figure 19 11 Handling of the Last Message Object s Alternating Buffer User s Manual 19 30 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 4 Controlling the CAN Module The
551. ter DSTPx on the higher word address x 7 0 00 FD00 H 00FCFE H 00FCFE H O0 FCFC H OOF CEO p 00 FCDE y PEC Source and Destination Internal Pointers RAM i 00 F600 H OFE h 00 FCEO 4 MCD03903 Figure 3 4 Location of the PEC Pointers Whenever a PEC data transfer is performed the pair of source and destination pointers which is selected by the specified PEC channel number is accessed independent of the current DPP register contents and also the locations referred to by these pointers are accessed independent of the current DPP register contents If a PEC channel is not used the corresponding pointer locations area available and can be used for word or byte data storage For more details about the use of the source and destination pointers for PEC data transfers see Chapter 5 User s Manual 3 7 V2 0 2000 07 d nfineon oo technologies Derivatives Memory Organization Special Function Registers The functions of the CPU the bus interface the IO ports and the on chip peripherals of the C167CS are controlled via a number of so called Special Function Registers SFRs These SFRs are arranged within two areas of 512 Byte size each The first register block the SFR area is located in the 512 Bytes above the internal RAM 00 FFFFy 00 FE00 the second register block the Extended SFR ESFR area is located in the 512 Bytes below the internal RAM 00 F1FFj 00 FO00 Speci
552. ter 2 User s Manual 4 10 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU 4 4 Instruction State Times Basically the time to execute an instruction depends on where the instruction is fetched from and where possible operands are read from or written to The fastest processing mode of the C167CS is to execute a program fetched from the internal code memory In that case most of the instructions can be processed within just one machine cycle which is also the general minimum execution time All external memory accesses are performed by the C167CS s on chip External Bus Controller EBC which works in parallel with the CPU This section summarizes the execution times in a very condensed way A detailed description of the execution times for the various instructions and the specific exceptions can be found in the C166 Family Instruction Set Manual Table 4 1 shows the minimum execution times required to process a C167CS instruction fetched from the internal code memory the internal RAM or from external memory These execution times apply to most of the C167CS instructions except some of the branches the multiplication the division and a special move instruction In case of internal ROM program execution there is no execution time dependency on the instruction length except for some special branch situations The numbers in the table are in units of CPU clock cycles and assume no waitsta
553. ter the target signal level is reached In Low Noise Mode both transistors are activated at the beginning of a signal transition When the target signal level is reached the driver strength is reduced by switching off the strong transistor The weak transistor will keep the specified output level while the susceptibility for noise is reduced In Low Current Mode only the weak transistor is activated while the strong transistor remains off This results in smooth transitions with low current peaks and reduced susceptibility for noise on the cost of increased transition times i e slower edges depending on the capacitive load User s Manual 7 5 V2 0 2000 07 o nfineon ed technologies Derivatives Parallel Ports Edge Characteristic This defines the rise fall time for the respective output i e the output transition time Slow edges reduce the peak currents that are drawn when changing the voltage level of an external capacitive load For a bus interface however fast edges may still be required Edge characteristic effects the pre driver which controls the final output driver stage Open Drain Control Driver Control Edge Control Pin Data Signal 9 Control Signal Driver Control Logic Driver Stage MCD04461 Figure 7 4 Structure of Two Level Output Driver with Edge Control Table 7 1 Output Transistor Operation Driver Mode Low Current Mode Dynamic
554. terpret these 2 bit fields Table 19 1 MCR Bitfield Encoding Value Function on Write Meaning on Read 00 reserved reserved 01 Reset element Element is reset 10 Set element Element is set 11 Leave element unchanged reserved User s Manual 19 19 V2 0 2000 07 o nfineon technologies MCRn Message Control Register C167CS Derivatives The On Chip CAN Interface XReg EFn0jj Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MSGLST RMTPND TXRQ CPUUPD NEWDAT MSGVAL TXIE RXIE INTPND rw rw rw rw rw rw rw rw Bit Function INTPND Interrupt Pending Indicates if this message object has generated an interrupt request see TXIE and RXIE since this bit was last reset by the CPU or not RXIE Receive Interrupt Enable Defines if bit INTPND is set after successful reception of a frame TXIE Transmit Interrupt Enable Defines if bit INTPND is set after successful transmission of a frame MSGVAL Message Valid Indicates if the corresponding message object is valid or not The CAN controller only operates on valid objects Message objects can be tagged invalid while they are changed or if they are not used at all NEWDAT New Data Indicates if new data has been written into the data portion of this message object by CPU transmit objects or CAN controller receive objec
555. terrupts 5 28 Flags 4 16 4 19 FOCON 21 18 Frequency output signal 21 17 Full Duplex 12 7 G GMS 19 16 GPR 3 6 4 25 23 2 GPT 2 16 GPT1 10 1 GPT2 10 22 H Half Duplex 12 10 Hardware Reset 20 2 Traps 5 31 Hold State Entry 9 33 Exit 9 34 l Idle Mode 21 3 State Bus 9 30 Incremental Interface 10 9 Indication of reset source 13 6 Input threshold 7 2 Instruction 22 1 24 1 Bit Manipulation 24 2 Branch 4 4 User s Manual Keyword Index Pipeline 4 3 protected 24 4 Timing 4 11 unseparable 22 14 Interface CAN 2 14 19 1 External Bus 9 1 serial async gt ASCO 11 1 serial sync gt SSC 12 1 Internal RAM 3 4 Interrupt CAPCOM 16 22 during sleep mode 5 30 Enable Disable 5 16 External 5 26 Fast external 5 28 Handling CAN 19 10 Node Sharing 5 25 Priority 5 8 Processing 5 1 5 6 Response Times 5 20 RTC 14 3 source control 5 29 Sources 5 2 System 2 7 5 2 Vectors 5 2 IP 4 19 IRAM 3 4 status after reset 20 8 ISNC 5 25 L LARn 19 22 Latched chip select 9 11 LGML 19 17 LMLM 19 18 M Management Peripheral 21 14 Power 21 1 Master mode External bus 9 35 26 3 V2 0 2000 07 _ e nfineon technologies C167CS Derivatives MCFGn 19 23 MCRn 19 20 MDC 4 32 MDH 4 30 MDL 4 31 Memory 2 8 bit addressable 3 4 Code memory handling 22 16 External 3 11 RAM SFR 3 4 ROM area 3 3 Tri state time 9 15 XRAM 3 9 Memory Cycle Time 9 14 Multiplexed Bus 9 4 Multiplicatio
556. tes Table 4 1 Minimum Execution Times Instruction Fetch Word Operand Access Memory Area Word Doubleword Read from Write to Instruction Instruction Internal code memory 2 2 2 Internal RAM 6 8 0 1 0 16 bit Demux Bus 2 4 2 2 16 bit Mux Bus 3 6 3 3 8 bit Demux Bus 4 8 4 4 8 bit Mux Bus 6 12 6 6 Execution from the internal RAM provides flexibility in terms of loadable and modifyable code on the account of execution time Execution from external memory strongly depends on the selected bus mode and the programming of the bus cycles waitstates Users Manual 4 11 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The operand and instruction accesses listed below can extend the execution time of an instruction e Internal code memory operand reads same for byte and word operand reads e Internal RAM operand reads via indirect addressing modes Internal SFR operand reads immediately after writing e External operand reads e External operand writes Jumps to non aligned double word instructions in the internal ROM space Testing Branch Conditions immediately after PSW writes 4 5 CPU Special Function Registers The core CPU requires a set of Special Function Registers SFRs to maintain the system state information to supply the ALU with register addressable constants and to control system and bus configuration multiply and divide ALU ope
557. th pins TXDO and RXDO will go high the transmit interrupt request flag SOTIR is set and serial data transmission stops Pin TXDO must be configured for alternate data output i e the respective port output latch and the direction latch must be 1 in order to provide the shift clock Pin RXDO must also be configured for output output direction latch 1 during transmission Synchronous reception is initiated by setting bit SOREN 1 If bit SOR 1 the data applied at pin RXDO are clocked into the receive shift register synchronous to the clock which is output at pin TXDO After the 8th bit has been shifted in the content of the receive shift register is transferred to the receive data buffer SORBUF the receive interrupt request flag SORIR is set the receiver enable bit SOREN is reset and serial data reception stops Pin TXDO must be configured for alternate data output i e the respective port output latch and the direction latch must be 1 in order to provide the shift clock Pin RXDO must be configured as alternate data input i e the respective direction latch must be 0 Synchronous reception is stopped by clearing bit SOREN A currently received byte is completed including the generation of the receive interrupt request and an error interrupt request if appropriate Writing to the transmit buffer register while a reception is in progress has no effect on reception and will not start a transmission
558. the standard SFR area 00 FEOO OO FFFFy or within the extended ESFR area 00 FOOO 00 F1FF These built in peripherals either allow the CPU to interface with the external world or provide functions on chip that otherwise were to be added externally in the respective system The C167CS generic peripherals are Two General Purpose Timer Blocks GPT1 and GPT2 Two Serial Interfaces ASCO and SSC e A Watchdog Timer Two 16 channel Capture Compare units CAPCOM1 and CAPCOM2 A 4 channel Pulse Width Modulation unit A 10 bit Analog Digital Converter A Real Time Clock Nine IO ports with a total of 111 IO lines Each peripheral also contains a set of Special Function Registers SFRs which control the functionality of the peripheral and temporarily store intermediate data results Each peripheral has an associated set of status flags Individually selected clock signals are generated for each peripheral from binary multiples of the CPU clock Peripheral Interfaces The on chip peripherals generally have two different types of interfaces an interface to the CPU and an interface to external hardware Communication between CPU and peripherals is performed through Special Function Registers SFRs and interrupts The SFRs serve as control status and data registers for the peripherals Interrupt requests are generated by the peripherals based on specific events which occur during their operation e g operation
559. the timers of the CAPCOM units is provided through a direct connection Triggered by an external signal the contents of T5 can be captured into register CAPREL and T5 may optionally be cleared Both timer T6 and T5 can count up or down and the current timer value can be read or modified by the CPU in the non bitaddressable SFRs T5 and T6 User s Manual 10 22 V2 0 2000 07 technologies C167CS Derivatives The General Purpose Timer Units T5EUD D Sopu T5 Mode T5IN e Control U D nterrupt GPT2 Timer T5 Clear Capture edv Request Interrupt CTS GPT2 CAPREL Request Interrupt T6IN B GPT2 Timer T6 gt Request JT60UT U D n Other fopu ode gt Timers Control T6EUD a MCB03999 n 2 9 Figure 10 16 GPT2 Block Diagram User s Manual 10 23 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units 10 2 1 GPT2 Core Timer T6 The operation of the core timer T6 is controlled by its bitaddressable control register T6CON T6CON Timer 6 Control Register SFR FF48y A44 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T6 T6 T6 T6 T6 SR OTL OE uDE UD TER TON 791 rw mh w rw rw rw rw rw Bit Function T6l Timer 6 Input Selection Depends on the Operating Mode see
560. this message object are set DLC Data Length Code Defines the number of valid data bytes within the data area Valid values for the data length are 0 8 Note The first data byte occupies the upper half of the message configuration register User s Manual 19 23 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Data Area The data area occupies 8 successive byte positions after the Message Configuration Register i e the data area of message object n covers locations O0 EFn7 through 00 EFnEy Location 00 EFnFy is reserved Message data for message object 15 last message will be written into a two message alternating buffer to avoid the loss of a message if a second message has been received before the CPU has read the first one Handling of Message Objects The following diagrams summarize the actions that have to be taken in order to transmit and receive messages over the CAN bus The actions taken by the CAN controller are described as well as the actions that have to be taken by the CPU i e the servicing program The diagrams show e CAN controller handling of transmit objects e CAN controller handling of receive objects CPU handling of transmit objects e CPU handling of receive objects CPU handling of last message object Handling of the last message s alternating buffer User s Manual 19 24 V2 0 2000 07 technologies C167CS Derivatives
561. tifiers have bits ID17 0 filled with 0 the data length code DLC and the data bytes valid bytes indicated by DLC This is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used When the CAN controller accepts a remote frame the corresponding transmit message object 1 14 remains unchanged except for bits TXRQ and RMTPND which are set of course In the last message object 15 which cannot start a transmission the identifier bits corresponding to the don t care bits of the Last Message Mask are copied from the received frame Bits corresponding to the don t care bits of the corresponding global mask are not copied i e bits masked out by the global and the last message mask cannot be retrieved from object 15 Tii Arbitration Register XReg EFn2 Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID20 18 ID17 13 ID28 21 rw rw LARn Lower Arbitration Register XReg EFn4j Reset Value UUUU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IDA 0 0 0 0 ID12 5 rw r r r rw Bit Function ID28 0 Identifier 29 bit Identifier of a standard message ID28 18 or an extended message ID28 0 For standard identifiers bits ID17 0 are don t care User s Manual 19 22 V2 0 2000 07 o nfineon ed technologies Derivat
562. timer can be turned on or off by software using bit T6R The timer will only run if T6R 1 and the gate is active It will stop if either T6R 0 or the gate is inactive Note A transition of the gate signal at pin T6IN does not cause an interrupt request User s Manual 10 28 V2 0 2000 07 o nfineon e technologies Derivatives The General Purpose Timer Units Timer 6 in Counter Mode Counter mode for the core timer T6 is selected by setting bit field T6M in register TeCON to 001g In counter mode timer T6 is clocked by a transition at the external input pin T6IN which is an alternate function of P5 12 The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at this pin Bit field T6l in control register T6CON selects the triggering transition see Table 10 13 Edge Select Interrupt Request MCB02030 T6IN P5 12 T6EUD P5 10 T6OUT P3 1 x 6 Figure 10 19 Block Diagram of Core Timer T6 in Counter Mode Table 10 13 GPT2 Core Timer T6 Counter Mode Input Edge Selection T6l Triggering Edge for Counter Increment Decrement 000 None Counter T6 is disabled 001 Positive transition rising edge on T6IN 010 Negative transition falling edge on T6IN 011 Any transition rising or falling edge on T6IN 1XX Reserved Do not use this combination The maximum input frequency wh
563. timer or counter mode or may be concatenated with another timer of the same block The auxiliary timers of GPT1 may optionally be configured as reload or capture registers for the core timer In the GPT2 block the additional CAPREL register supports capture and reload operation with extended functionality and its core timer T6 may be concatenated with timers of the CAPCOM units TO T1 T7 and T8 Each block has alternate input output functions and specific interrupts associated with it 10 1 Timer Block GPT1 From a programmer s point of view the GPT1 block is composed of a set of SFRs as summarized below Those portions of port and direction registers which are used for alternate functions by the GPT1 block are shaded Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions T2CON T3CON Co T4CON P5DIDIS T2IN P3 7 T2EUD P5 15 TSIN P3 6 T3EUD P3 4 T4IN P3 5 TAEUD P5 14 T30UT P3 3 P5 Port 5 Data Register P5DIDIS Port 5 Digital Input Disable Register ODP3 Port 3 Open Drain Control Register T2 GPT1 Timer 2 Register DP3 Port 3 Direction Control Register T3 GPT1 Timer 3 Register P3 Port 3 Data Register T4 GPT1 Timer 4 Register T2CON GPT1 Timer 2 Control Register T2IC GPT1 Timer 2 Interrupt Control Register T3CON GPT1 Timer 3 Control Register T3IC GPT1 Timer 3 Interrupt Control Register T4CON GPT1 Timer 4 Control Register T4IC GPT1 Timer 4 Interrupt Control Register MC
564. tion The interrupt request flag ADEIR in register ADEIC will be set either if a conversion result overwrites a previous value in register ADDAT error interrupt in standard mode or if the result of an injected conversion has been stored into ADDAT2 end of injected conversion interrupt This interrupt request may be used to cause an interrupt to vector ADEINT or it may trigger a PEC data transfer DC an Intr Ctrl Reg SFR FF98 CC Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARG ATG ILVL GLVL wh rw rw rw ADEIC ADC Error Intr Ctrl Reg SFR FF9Ap CDp Reset Value 00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADE ADE ILVL GLVL rwh rw rw rw Note Please refer to the general Interrupt Control Register description for an explanation of the control fields User s Manual 18 15 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 The On Chip CAN Interface Note The C167CS incorporates two CAN modules CAN1 and CAN2 As the structure of the two modules is identical this chapter mainly describes the functionality and the operation of module CAN1 The differences between modules CAN1 and CAN are described in a special section at the end of this chapter The Controller Area Network CAN bus with its associated protocol allows communication between a number of sta
565. tions which are connected to this bus with high efficiency Efficiency in this context means Transfer speed Data rates of up to 1 Mbit sec can be achieved Data integrity The CAN protocol provides several means for error checking e Host processor unloading The controller here handles most of the tasks autonomously Flexible and powerful message passing The extended CAN protocol is supported The integrated CAN module handles the completely autonomous transmission and reception of CAN frames in accordance with the CAN specification V2 0 part B active i e the on chip CAN module can receive and transmit Standard frames with 11 bit identifiers as well as Extended frames with 29 bit identifiers Note The CAN module is an XBUS peripheral and therefore requires bit XPEN in register SYSCON to be set in order to be operable User s Manual 19 1 V2 0 2000 07 C167CS Derivatives The On Chip CAN Interface technologies Control Registers Object Registers Core Registers within each module within each module Interrupt Control SYSCON CSR X SYSCONS E PCIR X SYSCON System Configuration Register CSR Control Status Register SYSCONS3 Peripheral Management Control Reg PCIR Port Control Interrupt Register DP4 Port 4 Direction Control Register BTR Bit Timing Register ODP4 Port 4 Open Drain Control Register GMS Global Mask Short DP8 Port 8 Direction Control Register U LGML Global Mask Long ODP8 P
566. to Bitfields CHNR and CHX of register ADDAT2 are loaded by the CPU to select the analog channel which is to be injected User s Manual 18 4 V2 0 2000 07 d nfineon e technologies Derivatives The Analog Digital Converter ADDAT ADC Result Register SFR FEA0 50 Reset Value 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR CHX ADRES rwh mh rwh ADDAT2 ADC Chan Inj Result Reg ESFR F0A04 504 Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CHNR CHX ADRES rw rw rwh Bit Function ADRES A D Conversion Result The 10 bit digital result of the most recent conversion CHX Channel Extension Indicator 0 CHNR refers to a standard channel AN15 ANO JE CHNR referes to an extension channel AN23 AN16 CHNR Channel Number identifies the converted analog channel Refers to standard or extension channels see bit CHX User s Manual 18 5 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter A conversion is started by setting bit ADST 1 The busy flag ADBSY will be set and the converter then selects and samples the input channel which is specified by the channel selection field ADCH in register ADCON The sampled level will then be held internally during the conversion When the conversion of this channel is complete
567. to set up local subroutine register frames This enables subroutines to dynamically allocate local variables as needed within two machine cycles A local frame is allocated by simply subtracting the number of required local registers from the SP and then moving the value of the new SP to the CP This operation is supported through the SCXT switch context instruction with the addressing mode reg mem Using this instruction saves the old contents of the CP on the system stack and moves the value of the SP into CP see example below Each local register is then accessed as if it was a normal register Upon exit from the subroutine first the old CP must be restored by popping it from the stack and then the number of used local registers must be added to the SP to restore the allocated local space back to the system stack Note The system stack is growing downwards while the register bank is growing upwards User s Manual 22 10 V2 0 2000 07 C167CS Derivatives technologies System Programming Old Stack Area Newly Allocated Register Bank Old CPContents New Stack Area MCA04409 Figure 22 2 Local Registers The software to provide the local register bank for the example above is very compact After entering the subroutine SUB SP 10D Free 5 words in the current system stack SCXT CP SP Set the new register bank pointer Before exiting the subroutine POP CP Restore the old re
568. to an interrupt service routine in order to service an interrupt requesting device The current program status IP PSW in segmentation mode also CSP is saved on the internal system stack A prioritization scheme with 16 priority levels allows the user to specify the order in which multiple interrupt requests are to be handled Interrupt Processing via the Peripheral Event Controller PEC A faster alternative to normal software controlled interrupt processing is servicing an interrupt requesting device with the C167CS s integrated Peripheral Event Controller PEC Triggered by an interrupt request the PEC performs a single word or byte data transfer between any two locations in segment 0 data pages 0 through 3 through one of eight programmable PEC Service Channels During a PEC transfer the normal program execution of the CPU is halted for just 1 instruction cycle No internal program status information needs to be saved The same prioritization scheme is used for PEC service as for normal interrupt processing PEC transfers share the 2 highest priority levels Trap Functions Trap functions are activated in response to special conditions that occur during the execution of instructions A trap can also be caused externally by the Non Maskable Interrupt pin NMI Several hardware trap functions are provided for handling erroneous conditions and exceptions that arise during the execution of an instruction Hardware traps always have highest prio
569. to the shift register which is assumed to be empty at this time and the selected first bit of the transmit data will be placed onto the MTSR line on the next clock from the baudrate generator transmission only starts if SSCEN 1 Depending on the selected clock phase also a clock pulse will be generated on the SCLK line With the opposite clock edge the master at the same time latches and shifts in the data detected at its input line MRST This exchanges the transmit data with the receive data Since the clock line is connected to all slaves their shift registers will be shifted synchronously with the master s shift register shifting out the data contained in the registers and shifting in the data detected at the input line After the preprogrammed number of clock pulses via the data width selection the data transmitted by the master is contained in all slaves shift registers while the master s shift register holds the data of the selected slave In the master and all slaves the content of the shift register is copied into the receive buffer SSCRB and the receive interrupt flag SSCRIR is set A slave device will immediately output the selected first bit MSB or LSB of the transfer data at pin MRST when the content of the transmit buffer is copied into the slave s shift register It will not wait for the next clock from the baudrate generator as the master does The reason for this is that depending on the selected clock phase
570. transfer via the on chip Peripheral Event Controller PEC System errors detected during program execution so called hardware traps or an external non maskable interrupt are also processed as standard interrupts with a very high priority In contrast to other on chip peripherals there is a closer conjunction between the watchdog timer and the CPU If enabled the watchdog timer expects to be serviced by the CPU within a programmable period of time otherwise it will reset the chip Thus the watchdog timer is able to prevent the CPU from going totally astray when executing erroneous code After reset the watchdog timer starts counting automatically but it can be disabled via software if desired Beside its normal operation there are the following particular CPU states Reset state Any reset hardware software watchdog forces the CPU into a predefined active state IDLE state The clock signal to the CPU itself is switched off while the clocks for the on chip peripherals keep running SLEEP state All of the on chip clocks are switched off RTC clock selectable wake up via external interrupts or RTC POWER DOWN state All of the on chip clocks are switched off RTC clock selectable all inputs are disregarded A transition into an active CPU state is forced by an interrupt if being in IDLE or SLEEP or by a reset if being in POWER DOWN mode The IDLE SLEEP POWER DOWN and RESET states can be entered by particular C
571. transmitted or received synchronous to a shift clock which is generated by the C167CS In asynchronous mode 8 or 9 bit data transfer parity generation and the number of stop bits can be selected Parity framing and overrun error detection is provided to increase the reliability of data transfers Transmission and reception of data is double buffered For multiprocessor communication a mechanism to distinguish address from data bytes is included Testing is supported by a loop back option A 13 bit baud rate generator provides the ASCO with a separate serial clock signal Ports amp Direction Control Data Registers Control Registers Interrupt Control Alternate Functions SOTIC SORIC SOCON SOEIC RXDO P3 11 SOTBIC E TXDO P3 10 ODP3 Port 3 Open Drain Control Register P3 Port 3 Data Register DP3 Port 3 Direction Control Register SOCON ASCO Control Register SOBG ASCO Baud Rate Generator Reload Reg SORBUF ASCO Receive Buffer Register read SOTBUF ASCO Transmit Buffer Register only SOTIC ASCO Transmit Interrupt Control Register SORIC ASCO Receive Interrupt Control SOTBIC ASCO Transmit Buffer Interrupt Ctrl Reg Register SOEIC ASCO Error Interrupt Control Register MCA04376 Figure 11 1 SFRs and Port Pins Associated with ASCO User s Manual 11 1 V2 0 2000 07 nfineon technologies C167CS Derivatives The Asynchronous Synchronous Serial Interface The operating mode of the serial c
572. troducing wait states during the access see Figure 9 7 During these memory cycle time wait states the CPU is idle if this access is required for the execution of the current instruction The memory cycle time wait states can be programmed in increments of one CPU clock 2 TCL within a range from 0 to 15 default after reset via the MCTC fields of the BUSCON registers 15 lt MCTC gt waitstates will be inserted User s Manual 9 14 V2 0 2000 07 d nfineon ed technologies Derivatives The External Bus Interface Programmable Memory Tri state Time The C167CS allows the user to adjust the time between two subsequent external accesses to account for the tri state time of the external device The tri state time defines when the external device has released the bus after deactivation of the read command RD a Bus Cycle Segment X Address 7 1 0 T X MTTC Wait State MCT02065 Figure 9 8 Memory Tri state Time The output of the next address on the external bus can be delayed for a memory or peripheral which needs more time to switch off its bus drivers by introducing a wait state after the previous bus cycle see Figure 9 8 During this memory tri state time wait state the CPU is not idle so CPU operations will only be slowed down if a subsequent external instruction or data fetch operation is required during the next instruction cycle The memory tri
573. ts since this bit was last reset or not 2 MSGLST Message Lost This bit applies to receive objects only Indicates that the CAN controller has stored a new message into this object while NEWDAT was still set i e the previously stored message is lost CPUUPD CPU Update This bit applies to transmit objects only Indicates that the corresponding message object may not be transmitted now The CPU sets this bit in order to inhibit the transmission of a message that is currently updated or to control the automatic response to remote requests TXRQ Transmit Request Indicates that the transmission of this message object is requested by the CPU or via a remote frame and is not yet done TXRQ can be disabled by CPUUPD User s Manual 19 20 V2 0 2000 07 C167CS Derivatives The On Chip CAN Interface technologies Bit Function RMTPND Remote Pending Used for transmit objects Indicates that the transmission of this message object has been requested by a remote node but the data has not yet been transmitted When RMTPND is set the CAN controller also sets TXRQ RMTPND and TXRQ are cleared when the message object has been successfully transmitted 1 n message object 15 last message these bits are hardwired to 0 inactive in order to prevent transmission of message 15 When the CAN controller writes new data into the message object unused message bytes will be overwritten by non specifie
574. ual 9 6 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface multiplexed bus modes the address is also required on PORTO In this special case the address on PORTO is delayed by one CPU clock cycle which delays the complete multiplexed bus cycle and extends the corresponding ALE signal see Figure 9 4 This extra time is required to allow the previously selected device via demultiplexed bus to release the data bus which would be available in a demultiplexed bus cycle Demultiplexed Bus Cycle n NO T Mies Segment P4 Address Address ALE N N BUS P0 gt X Data Instr Data Instr X Multiplexed Bus Cycle Idle State MCD02234 Figure 9 4 Switching from Demultiplexed to Multiplexed Bus Mode Switching between external resources e g different peripherals may incur a problem if the previously accessed resource needs some time to switch of its output drivers after a read and the resource to be accessed next switches on its output drivers very fast In systems running on higher frequencies this may lead to a bus conflict the switch off delays normally are independent from the clock frequency In such a case an additional waitstate can automatically be inserted when leaving a certain address window i e when the next cycle accesses a different window This wait
575. ue is used at least one instruction must be inserted between a DPPn changing instruction and a subsequent instruction which implicitly uses DPPn via a long or indirect addressing mode as shown in the following example Ts MOV DPPO 4 select data page 4 via DPPO Us hae eas must not be an instruction using DPPO lai 2 MOV DPPO 0000B Ri move contents of Rl to address location 01 00004 in data page 4 supposed segment is enabled User s Manual 4 6 V2 0 2000 07 o Infineon technologies C167CS Derivatives The Central Processing Unit CPU Explicit Stack Pointer Updating None of the RET RETI RETS RETP or POP instructions is capable of correctly using a new SP register value which is to be updated by an immediately preceding instruction Thus in order to use the new SP register value without erroneously performed stack accesses at least one instruction must be inserted between an explicitly SP writing and any subsequent of the just mentioned implicitly SP using instructions as shown in the following example Is MOV SP 40FAA40H select a new top of stack Ta oqies must not be an instruction popping operands from the system stack la d SEP OP RO pop word value from new top of stack into RO Note Conflicts with instructions writing to the stack PUSH CALL SCXT are solved internally by the CPU logic Controlling Interrupts Software modifications implicit or explicit of the PSW are done i
576. uld also set TXRQ which should otherwise be left alone User s Manual 19 35 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface Configuration Example of a Reception Object This object shall be configured for reception A receive interrupt shall be generated each time new data comes in From time to time the CPU sends a remote request to trigger the sending of this data from a remote node MCR Message object is idle i e waiting for a frame to be received 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01 01 01 01 10 01 10 01 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND MCR A data frame was received NEWDAT 1 INTPND 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 01 01 01 10 10 01 10 10 RMTPND TXRQ MSGLST NEWDAT MSGVAL TXIE RXIE INTPND To process the message the CPU should clear INTPND and NEWDAT process the data and check that NEWDAT is still clear after that If not the processing should be repeated To send a remote frame to request the data simply bit TXRQ needs to be set This bit will be cleared by the CAN controller once the remote frame has been sent or if the data is received before the CAN controller could transmit the remote frame User s Manual 19 36 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19
577. ult address range BUSCONDO is selected via PORTO during reset provided that pin EA is low during reset Otherwise BUSCONO may be programmed via software just like the other BUSCON registers The 16 MByte address space of the C167CS is divided into 256 segments of 64 KByte each The 16 bit intra segment address is output on PORTO for multiplexed bus modes or on PORT1 for demultiplexed bus modes When segmentation is disabled only one 64 KByte segment can be used and accessed Otherwise additional address lines may be output on Port 4 addressing up to 16 MByte and or several chip select lines may be used to select different memory banks or peripherals These functions are selected during reset via bitfields SALSEL and CSSEL of register RPOH respectively Note Bit SGTDIS of register SYSCON defines if the CSP register is saved during interrupt entry segmentation active or not segmentation disabled User s Manual 9 3 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Multiplexed Bus Modes In the multiplexed bus modes the 16 bit intra segment address as well as the data use PORTO The address is time multiplexed with the data and has to be latched externally The width of the required latch depends on the selected data bus width i e an 8 bit data bus requires a byte latch the address bits A15 A8 on POH do not change while POL multiplexes address and data a 16 bit data bus requires a word
578. upled from VDD and VSS The Power Supply pins VDD and VSS provide the power supply for the digital logic of the C167CS The respective VDD VSS pairs should be decoupled as close to the pins as possible For best results it is recommended to implement two level decoupling e g the widely used 100 nF in parallel with 30 40 pF capacitors which deliver the peak currents Note All VDD pins and all VSS pins must be connected to the power supply and ground respectively User s Manual 8 4 V2 0 2000 07 e nfineon ed technologies Derivatives The External Bus Interface 9 The External Bus Interface Although the C167CS provides a powerful set of on chip peripherals and on chip RAM and ROM OTP Flash except for ROMless versions areas these internal units only cover a small fraction of its address space of up to 16 MByte The external bus interface allows to access external peripherals and additional volatile and non volatile memory The external bus interface provides a number of configurations so it can be tailored to fit perfectly into a given application system Ports amp Direction Control Address Registers Mode Registers Control Registers Alternate Functions POL POH P1L P1H BUSCONO SYSCON ADDRSEL1 BUSCON1 RPOH ADDRSEL2 BUSCON2 ADDRSEL3 BUSCONS ADDRSEL4 BUSCON4 PORTO EA PORT1 RSTIN ALE READY RD ____ WR WRL BHE WRH POL POH PORTO Data Register ADDRSELx Address Range Select Register 1
579. upper and lower half of the memory can be accessed individually In this case the upper byte is selected with the BHE signal while the lower byte is selected with the AO signal So the two bytes of the memory can be enabled independent from each other or together when accessing words When writing bytes to an external 16 bit device which has a single CS input but two WR enable inputs for the two bytes the EBC can directly generate these two write control signals This saves the external combination of the WR signal with AO or BHE In this case pin WR serves as WRL write low byte and pin BHE serves as WRH write high byte Bit WRCFG in register SYSCON selects the operating mode for pins WR and BHE The respective byte will be written on both data bus halfs When reading bytes from an external 16 bit device whole words may be read and the C167CS automatically selects the byte to be input and discards the other However care must be taken when reading devices that change state when being read like FIFOs interrupt status registers etc In this case individual bytes should be selected using BHE and AO Table 9 2 Bus Mode versus Performance Bus Mode Transfer Rate System Requirements Free IO Speed factor for Lines byte word dword access 8 bit Multiplexed Very low 1 5 3 6 Low 8 bit latch byte bus P1H P1L 8 bit Demultipl Low 1 2 4 Very low no latch byte bus POH 16 bit Multiplexed High 1 5
580. upt Ctrl Reg 0000 CC3 FE86 434 CAPCOM Register 3 0000 CC30 FE7C 3Ey4 CAPCOM Register 30 00004 CC30IC b F18C4 E C64 CAPCOM Register 30 Interrupt Ctrl Reg 00004 CC31 FE7E 3Fy CAPCOM Register 31 0000 CC31IC b F1944 E CA CAPCOM Register 31 Interrupt Ctrl Reg 0000 CC3IC b FF7E BF CAPCOM Register 3 Interrupt Ctrl Reg 0000 CC4 FE88 444 CAPCOM Register 4 0000 CC4IC b FF80 CO CAPCOM Register 4 Interrupt Ctrl Reg 0000 CC5 FE8A 454 CAPCOM Register 5 0000 CC5IC b FF82 C14 CAPCOM Register 5 Interrupt Ctrl Reg 00004 CC6 FE8C 464 CAPCOM Register 6 00004 CC6IC b FF84 C2 CAPCOM Register 6 Interrupt Ctrl Reg 0000 CC7 FE8E 474 CAPCOM Register 7 0000 CC7IC b FF86 C34 CAPCOM Register 7 Interrupt Ctrl Reg 00004 CC8 FE904 48 CAPCOM Register 8 00004 CC8IC b FF88 C44 CAPCOM Register 8 Interrupt Ctrl Reg 0000 CC9 FE92 49 CAPCOM Register 9 0000 CC9IC b FF8A C54 CAPCOM Register 9 Interrupt Ctrl Reg 00004 CCMO b FF52 A9 CAPCOM Mode Control Register 0 0000 CCM1 b FF54 AA CAPCOM Mode Control Register 1 0000 CCM2 b FF564 AB CAPCOM Mode Control Register 2 00004 CCM3 b FF58y ACy CAPCOM Mode Control Register 3 0000 CCM4 b FF22 914 CAPCOM Mode Control Register 4 00004 CCM5 b FF24 924 CAPCOM Mode Control Register 5 0000 CCM6 b FF26 93 CAPCOM Mode Control Register 6 0000 CCM7 b FF284 944 CAPCOM Mode Control Register 7 00004 User s M
581. upt request flag during the last state of an instruction cycle When the interrupt request flag is set during the first state of an instruction cycle the minimum interrupt response time under these conditions is 6 state times 12 TCL The interrupt response time is increased by all delays of the instructions in the pipeline that are executed before entering the service routine including N User s Manual 5 20 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions When internal hold conditions between instruction pairs N 2 N 1 or N 1 N occur or instruction N explicitly writes to the PSW or the SP the minimum interrupt response time may be extended by 1 state time for each of these conditions When instruction N reads an operand from the internal code memory or when N is a call return trap or MOV Rn Rm data16 instruction the minimum interrupt response time may additionally be extended by 2 state times during internal code memory program execution n case instruction N reads the PSW and instruction N 1 has an effect on the condition flags the interrupt response time may additionally be extended by 2 state times The worst case interrupt response time during internal code memory program execution adds to 12 state times 24 TCL Any reference to external locations increases the interrupt response time due to pipeline related access priorities The following conditions hav
582. urrent master from the bus This is indicated to the C167CS by deactivating its HOLD input The C167CS responds by deactivating its HLDA signal and then taking control of the external bus itself Of course also the request signal BREQ is deactivated after getting control of the bus back User s Manual 9 32 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface Entering the Hold State Access to the C167CS s external bus is requested by driving its HOLD input low After synchronizing this signal the C167CS will complete a current external bus cycle or XBUS cycle if any is active release the external bus and grant access to it by driving the HLDA output low During hold state the C167CS treats the external bus interface as follows Address and data bus es float to tri state ALE is pulled low by an internal pulldown device BEEN Command lines are pulled high by internal pullup devices RD WR CSx outputs are driven high for 1 TCL and then pulled high in push pull mode or float to tri state in open drain mode Should the C167CS require access to its external bus or XBUS during hold mode it activates its bus request output BREQ to notify the arbitration circuitry BREQ is activated only during hold mode It will be inactive during normal operation HOLD nd para EA Other dm 222 EE este Signals La MCD02238 Figure 9 12 External
583. used not only for protection against data destruction but also allow to implement a circular stack with hardware supported system stack flushing and filling except for option 111 The technique of implementing this circular stack is described in Chapter 22 User s Manual 3 5 V2 0 2000 07 o nfineon oo technologies Derivatives Memory Organization General Purpose Registers The General Purpose Registers GPRs use a block of 16 consecutive words within the internal RAM The Context Pointer CP register determines the base address of the currently active register bank This register bank may consist of up to 16 Word GPRs RO R1 R15 and or of up to 16 Byte GPRs RLO RHO RL7 RH7 The sixteen Byte GPRs are mapped onto the first eight Word GPRs see Table 3 2 In contrast to the system stack a register bank grows from lower towards higher address locations and occupies a maximum space of 32 Byte The GPRs are accessed via short 2 4 or 8 bit addressing modes using the Context Pointer CP register as base address independent of the current DPP register contents Additionally each bit in the currently active register bank can be accessed individually Table 3 2 Mapping of General Purpose Registers to RAM Addresses Internal RAM Address Byte Registers Word Register CP 1Ey R15 lt CP gt 1Cy R14 CP 1Ay R13 CP 184 R12
584. ut compare output channel 21 P8 6 CC2210 Capture input compare output channel 22 P8 7 CC23lO Capture input compare output channel 23 Note CAN interface lines will override general purpose IO and CAPCOM lines User s Manual 7 b4 V2 0 2000 07 technologies C167CS Derivatives Parallel Ports Port 8 Alternate Function P8 7 P8 6 P8 5 P8 4 P8 3 P8 2 P8 1 P8 0 General Purpose Input Output a CC23lO CC221O CC2110 CC20lO CC19IO CC18lO CC171O CC16lO CAPCOM Input Output b CAN1 TxD CAN2 TxD CAN1 RxD CAN2 RxD CAN1 TxD CAN2 TxD CAN1 RxD CAN2 RxD CAN Interface MCA04429 Figure 7 28 Port 81O and Alternate Functions User s Manual 7 55 V2 0 2000 07 e Infineon iis technologies Derivatives Parallel Ports The pins of Port 8 combine internal bus data and alternate data output before the port latch input as do the Port 2 pins Internal Bus Read Write Read Write Read Port Output Latch Direction Open Drain Latch Latch Pin t 1 1 Driver AltDataln Latch 4 Clock AltDataln Pin 4 amp Input Latch MCB04366 P8 7 4 Figure 7 29 Block Diagram of Port 8 Pins with Alternate CAPCOM IO Function User s Manual 7 56 V2 0 2000 07 o Infineon o Ce technologies Derivatives Parallel Ports Internal Bus CCx Write Read
585. value for a given baudrate B fcPu fcPU SSC 2 x lt SSCBR gt 1 GxBaudratessc SSCBR represents the content of the reload register taken as an unsigned 16 bit integer Table 12 2 list some possible baud rates together with the required reload values and the resulting bit times for different CPU clock frequencies Table 12 2 SSC Bit Time Calculation Bit time for fcpy Reload Val 16 MHz 20 MHz 25 MHz 33 MHz SSCBR Reserved SSCBR must be 0 0000 250 ns 200 ns 160 ns 121 ns 00014 3 5 ns 300 ns 240 ns 182 ns 00024 500 ns 400 ns 320 ns 242 ns 00034 625 ns 500 ns 400 ns 303 ns 00044 1 00 us 800 ns 640 ns 485 ns 00074 1 25 us 1 us 800 ns 606 ns 00094 10 us 8 us 6 4 us 4 8 us 004F4 12 5 us 10 us 8 Ls 6 1 us 0063 15 6 us 125 us 10 us 7 6 us 007Cy 20 6 us 165 us 13 2 us 10 us 00A4 User s Manual 12 13 V2 0 2000 07 o nfineon technologies C167CS Derivatives The High Speed Synchronous Serial Interface Table 12 2 SSC Bit Time Calculation cont d Bit time for fcpy Reload Val 16 MHz 20 MHz 25 MHz 33 MHz SSCBR 1 ms 800 us 640 us 485 us 1FSFy 1 25 ms 1 ms 800 us 606 us 270Fu 1 56 ms 1 25 ms 1 ms 758 us 30D3 8 2 ms 6 6 ms 5 2 ms 4 0 ms FFFFy Table 12 3 SSC Baudrate Calculation Baud Rate for fcpy Reload Val 16 MHz 20 MHz 25 MHz
586. ve output toggle latches TxOTL which change their state on each timer over flow underflow The state of these latches may be output on port pins TxOUT or may be used internally to concatenate the core timers with the respective auxiliary timers resulting in 32 33 bit timers counters for measuring long time periods with high resolution Various reload or capture functions can be selected to reload timers or capture a timer s contents triggered by an external signal or a selectable transition of toggle latch TXOTL The maximum resolution of the timers in module GPT1 is 8 CPU clock cycles 16 TCL With their maximum resolution of 4 CPU clock cycles 8 TCL the GPT2 timers provide precise event control and time measurement User s Manual 2 16 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview Capture Compare CAPCOM Units The two CAPCOM units support generation and control of timing sequences on up to 32 channels with a maximum resolution of 8 CPU clock cycles The CAPCOM units are typically used to handle high speed IO tasks such as pulse and waveform generation pulse width modulation PWM Digital to Analog D A conversion software timing or time recording relative to external events Four 16 bit timers TO T1 T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several prescaled values of the
587. veral source requests e g as different kinds of errors in the serial interfaces However specific status flags which identify the type of error are implemented in the serial channels control registers The C167CS provides a vectored interrupt system In this system specific vector locations in the memory space are reserved for the reset trap and interrupt service functions Whenever a request occurs the CPU branches to the location that is associated with the respective interrupt source This allows direct identification of the source that caused the request The only exceptions are the class B hardware traps which all share the same interrupt vector The status flags in the Trap Flag Register TFR can then be used to determine which exception caused the trap For the special software TRAP instruction the vector address is specified by the operand field of the instruction which is a seven bit trap number The reserved vector locations build a jump table in the low end of the C167CS s address space segment 0 The jump table is made up of the appropriate jump instructions that transfer control to the interrupt or trap service routines which may be located anywhere within the address space The entries of the jump table are located at the lowest addresses in code segment O of the address space Each entry occupies 2 words except for the reset vector and the hardware trap vectors which occupy 4 or 8 words Table 5 1 lists all sources that ar
588. vers The operating clock signal fcpy is distributed to the controller hardware via several clock drivers which are disabled under certain circumstances The real time clock RTC is clocked via a separate clock driver which delivers the prescaled oscillator clock contrary to the other clock drivers Table 6 2 summarizes the different clock drivers and their function especially in power reduction modes Table 6 2 Clock Drivers Description Clock Driver Clock Active Idle Power Connected Circuitry Signal Mode Mode Down andSleep Mode CCD cPU ON Off Off CPU CPU internal memory modules Clock Driver IRAM ROM OTP Flash ICD cPU ON ON Off ASCO WDT SSC Interface interrupt detection Clock Driver circuitry PCD Jepu Controlvia Controlvia Off X Peripherals timers Peripheral PCDDIS PCDDIS etc except those driven Clock Driver by ICD interrupt controller ports RCD fRTC ON ON Controlvia Realtime clock RTC PDCON Clock Driver SLEEP CON Note Disabling PCD by setting bit PCDDIS stops the clock signal for all connected modules Make sure that all these modules are in a safe state before stopping their clock signal The port input and output values will not change while PCD is disabled ASCO and SSC will still operate if active CLKOUT will be high if enabled Please also respect the hints given in section Section 21 5 User s Manual 6 9 V2 0 2000 07 o nfineon ed technologies
589. ves The External Bus Interface Visible Mode The C167CS can mirror on chip access cycles to its XBUS peripherals so these accesses can be observed or recorded by the external system This function is enabled via bit VISIBLE in register SYSCON Accesses to XBUS peripherals also use the EBC Due to timing constraints the address bus will change for all accesses using the EBC Note As XBUS peripherals use demultiplexed bus cycles the respective address is driven on PORT1 in visible mode even if the external system uses MUX buses only If visible mode is activated accesses to on chip XBUS peripherals including control signals RD WR and BHE are mirrored to the bus interface Accesses to internal resources program memory IRAM GPRs do not use the EBC and cannot be mirrored to outside If visible mode is deactivated however no control signals RD WR will be activated i e there will be no valid external bus cycles Note Visible mode can only work if the external bus is enabled at all User s Manual 9 39 V2 0 2000 07 o nfineon ed technologies Derivatives The External Bus Interface 9 8 2 External Accesses to XBUS Peripherals The on chip XBUS peripherals of the C167CS can be accessed from outside via the external bus interface under certain circumstances In emulation mode the XBUS peripherals are controlled by the bondout chip During normal operation this external access is accomplished selecting the XPER
590. with two operands the N flag represents the logical XORing of the two specified bits C Flag After an addition the C flag indicates that a carry from the most significant bit of the specified word or byte data type has been generated After a subtraction or a comparison the C flag indicates a borrow which represents the logical negation of a carry for the addition This means that the C flag is set to 1 if no carry from the most significant bit of the specified word or byte data type has been generated during a subtraction which is performed internally by the ALU as a 2 s complement addition and the C flag is cleared when this complement addition caused a carry The C flag is always cleared for logical multiply and divide ALU operations because these operations cannot cause a carry anyhow For shift and rotate operations the C flag represents the value of the bit shifted out last If a shift count of zero is specified the C flag will be cleared The C flag is also cleared for a prioritize ALU operation because a 1 is never shifted out of the MSB during the normalization of an operand For Boolean bit operations with only one operand the C flag is always cleared For Boolean bit operations with two operands the C flag represents the logical ANDing of the two specified bits V Flag For addition subtraction and 2 s complementation the V flag is always set to 1 if the result overflows the maximum range of signed numbers w
591. x of the corresponding mode control register to 110p When a match is detected in compare mode 2 for the first time within a timer period the interrupt request flag CCxIR is set to 1 The corresponding port pin is not affected and can be used for general purpose IO However after the first match has been detected in this mode all further compare events within the same timer period are disabled for compare register CCx until the allocated timer overflows This means that after the first match even when the compare register is reloaded with a value higher than the current timer value no compare event will occur until the next timer period User s Manual 16 16 V2 0 2000 07 C167CS Derivatives technologies The Capture Compare Units In the example below the compare value in register CCx is modified from cv1 to cv2 after compare event 1 Compare event 2 however will not occur until the next period of timer Ty Compare Reg CCx p diui S Port an Mode 3 Latch COxO Reset Input leapenQuM Tema Interrupt Clock Request not for CC27 CC24 X 31 0 y 0 1 7 8 MCB02019 Figure 16 8 Compare Mode 2 and 3 Block Diagram Note The port latch and pin remain unaffected in compare mode 2 Contents of Ty FFPE Compare Value cv2 Compare Value cv1 Reload Value lt TyREL gt 0000 Interrupt Requests TyIR CCxIR Ty
592. xample module indicator is C1 CAN module 1 specific name is Control Status Register CSR unique register name is C1CSR Note The address map shown below lists the registers which are part of the CAN controller There are also C167CS specific registers that are associated with the CAN module User s Manual 19 6 V2 0 2000 07 technologies C167CS Derivatives The On Chip CAN Interface EF00 General Registers Control Status EF00 EF10 Message Object 1 Register CSR EF20 Message Object 2 Interrupt Register EF02 4 EF30 Message Object 3 in EF40 Message Object 4 Bit Timing Register EF04 EFS0 Message Object 5 BTR EF60 Message Object 6 Global Mask Short EF06j EF70 Message Object 7 GMS EF80 Message Object 8 EF08 Global Mask Long EF90 Message Object 9 EFA0 Message Object 10 LGML EFBO Message Object 11 UGML EFCO Message Object 12 Mask of Last EFOC EFDO Message Object 13 Message EFEO Message Object 14 LMLM EFFO Message Object 15 UMLM CAN Address Area General Registers MCA04392 Figure 19 3 CAN Module Address Map User s Manual 19 7 V2 0 2000 07 o nfineon ed technologies Derivatives The On Chip CAN Interface 19 2 The Control Status Register CSR accepts general control settings for the module and provides general status information General Functional Description
593. xiliary timer T5 is programmed to timer mode or gated timer mode its operation is the same as described for the core timer T6 The descriptions figures and tables apply accordingly with one exception There is no output toggle latch for T5 Timer T5 in Counter Mode Counter mode for the auxiliary timer T5 is selected by setting bit field T5M in register T5CON to 001g In counter mode timer T5 can be clocked either by a transition at the external input pin T5IN or by a transition of timer T6 s output toggle latch T6OTL i e timer concatenation User s Manual 10 31 V2 0 2000 07 o nfineon ed technologies Derivatives The General Purpose Timer Units Interrupt Auxiliary Timer Tx Request Up Down TxUDE MCB02221 x25 Figure 10 20 Block Diagram of Auxiliary Timer T5 in Counter Mode The event causing an increment or decrement of the timer can be a positive a negative or both a positive and a negative transition at either the input pin or at the toggle latch T6OTL Bitfield T5I in control register T5CON selects the triggering transition see Table 10 14 Table 10 14 GPT2 Auxiliary Timer Counter Mode Input Edge Selection T5I Triggering Edge for Counter Increment Decrement X00 None Counter T5 is disabled 0 0 1 Positive transition rising edge on T5IN 010 Negative transition falling edge on T5IN 0 1 1 Any transition rising or falling edge on T5IN 101 Positiv
594. xt lower channel ADCIR will be set after each completed conversion After conversion of channel O channel 16 the current sequence is complete In Single Conversion Mode the converter will automatically stop and reset bits ADBSY and ADST In Continuous Conversion Mode the converter will automatically start a new sequence beginning with the conversion of the channel specified in ADCH ADX When bit ADST is reset by software while a conversion is in progress the converter will complete the current sequence including conversion of channel O channel 16 and then stop and reset bit ADBSY 3 2 1 0 3 2 ammi Edd T T T T be dhe he de tm ha Y Write ADDAT ix 3 2 1 0 3 ADDAT Ful LLCO p p rF Generate Interrupt Request ADDAT Full Read of ADDAT Channnel 0 Result of Channel x 3 2 1 Result Lost 3 Overrun Error Interrupt Request MCA02241 Figure 18 3 Auto Scan Conversion Mode Example User s Manual 18 7 V2 0 2000 07 o nfineon e technologies Derivatives The Analog Digital Converter Wait for ADDAT Read Mode If in default mode of the ADC a previous conversion result has not been read out of register ADDAT by the time a new conversion is complete the previous result in register ADDAT is lost because it is overwritten by the new value and the A D overrun error interrupt request flag ADEIR will be set In order to avoid error interrupts and the loss of conversion results especial
595. xternal world Pin P3 13 SCLK serves as the clock line while pins P3 8 MRST Master Receive Slave Transmit and P3 9 MTSR Master Transmit Slave Receive serve as the serial data input output lines The operation of these pins depends on the selected operating mode master or slave In order to enable the alternate output functions of these pins instead of the general purpose IO operation the respective port latches have to be set to 1 since the port latch outputs and the alternate output lines are ANDed When an alternate data output line is not used function disabled it is held at a high level allowing IO operations via the port latch The direction of the port lines depends on the operating mode The SSC will automatically use the correct alternate input or output line of the ports when switching modes The direction of the pins however must be programmed by the user as shown in the tables Using the open drain output feature helps to avoid bus contention problems and reduces the need for hardwired hand shaking or slave select lines In this case it is not always necessary to switch the direction of a port pin Table 12 1 summarizes the required values for the different modes and pins Port Control Table 12 1 SSC Port Control Pin Master Mode Slave Mode Function Port Latch Direction Function Port Latch Direction SCLK Serial P3 132 1 DP3 13 1 Serial P3 132 x DP3 13 0 Clock Clock Output
596. y CAPCOM Register 11 00004 CC11lIC b FF8E C74 CAPCOM Register 11 Interrupt Ctrl Reg 0000 CC12 FE98 4Cy CAPCOM Register 12 00004 CC121C b FF90 C8 CAPCOM Register 12 Interrupt Ctrl Reg 00004 CC13 FE9A 4D CAPCOM Register 13 0000 CC13IC b FF92 C94 CAPCOM Register 13 Interrupt Ctrl Reg 0000 CC14 FE9C 4E CAPCOM Register 14 0000 User s Manual 23 5 V2 0 2000 07 o nfineon technologies C167CS Derivatives The Register Set Table 23 3 C167CS Registers Ordered by Name cont d Name Physical 8 bit Description Reset Address Addr Value CC14lC b FF94 CAy CAPCOM Register 14 Interrupt Ctrl Reg 0000 CC15 FE9E 4Fy CAPCOM Register 15 00004 CC15lIC b FF96 CBy CAPCOM Register 15 Interrupt Ctrl Reg 0000 CC16 FE60 304 CAPCOM Register 16 00004 CC16IC bj F160 E BO CAPCOM Register 16 Interrupt Ctrl Reg 0000 CC17 FE62y 314 CAPCOM Register 17 00004 CC17IC b F162 E Bip CAPCOM Register 17 Interrupt Ctrl Reg 0000 CC18 FE64 324 CAPCOM Register 18 0000 CC18IC b F1644 E B2 CAPCOM Register 18 Interrupt Ctrl Reg 0000 CC19 FE66 334 CAPCOM Register 19 0000 CC19IC b F1664 E B3 CAPCOM Register 19 Interrupt Ctrl Reg 00004 CC1IC b FF7Ay BD CAPCOM Register 1 Interrupt Ctrl Reg 0000 CC2 FE84 424 CAPCOM Register 2 00004 CC20 FE68 344 CAP
597. y Register ZEROS can be used as a register addressable constant of all zeros i e for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ZEROS Zeros Register SFR FF1Cj 8bE Reset Value 00004 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 r r r r r r r r r r r r r r r r The Constant Ones Register ONES All bits of this bit addressable register are fixed to 1 by hardware This register can be read only Register ONES can be used as a register addressable constant of all ones i e for bit manipulation or mask generation It can be accessed via any instruction which is capable of addressing an SFR ONES Ones Register SFR FF1Ep 8Fp Reset Value FFFF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 r r r r r r r r r r r r r r r r User s Manual 4 33 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions 5 Interrupt and Trap Functions The architecture of the C167CS supports several mechanisms for fast and flexible response to service requests that can be generated from various sources internal or external to the microcontroller These mechanisms include Normal Interrupt Processing The CPU temporarily suspends the current program execution and branches
598. y This allows to access a physical stack within the internal RAM of the C167CS A virtual stack usually bigger can be realized via software This mechanism is supported by registers STKOV and STKUN see respective descriptions below The SP register can be updated via any instruction which is capable of modifying an SFR Note Due to the internal instruction pipeline a POP or RETURN instruction must not immediately follow an instruction updating the SP register SP Stack Pointer Register SFR FE12 09 Reset Value FC00 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 1 1 sp 0 r r r r rwh r Bit Function sp Modifiable portion of register SP Specifies the top of the internal system stack User s Manual 4 27 V2 0 2000 07 o nfineon ed technologies Derivatives The Central Processing Unit CPU The Stack Overflow Pointer STKOV This non bit addressable register is compared against the SP register after each operation which pushes data onto the system stack e g PUSH and CALL instructions or interrupts and after each subtraction from the SP register If the content of the SP register is less than the content of the STKOV register a stack overflow hardware trap will occur Since the least significant bit of register STKOV is tied to 0 and bits 15 through 12 are tied to 1 by hardware the STKOV register can only contain values from F000 to FFFEj
599. y registers and IO ports are organized within the same linear address space which covers up to 16 MBytes The entire memory space can be accessed bytewise or wordwise Particular portions of the on chip memory have additionally been made directly bit addressable A 3 KByte 16 bit wide internal RAM IRAM provides fast access to General Purpose Registers GPRs user data variables and system stack The internal RAM may also be used for code A unique decoding scheme provides flexible user register banks in the internal memory while optimizing the remaining RAM for user data User s Manual 2 8 V2 0 2000 07 o nfineon oo technologies Derivatives Architectural Overview The CPU has an actual register context consisting of up to 16 wordwide and or bytewide GPRs at its disposal which are physically located within the on chip RAM area A Context Pointer CP register determines the base address of the active register bank to be accessed by the CPU at a time The number of register banks is only restricted by the available internal RAM space For easy parameter passing a register bank may overlap others A system stack of up to 1536 words is provided as a storage for temporary data The system stack is also located within the on chip RAM area and it is accessed by the CPU via the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared against the stack pointer value upon each stack access for the detect
600. y a separate request flag When a hardware trap occurs the corresponding request flag in register TFR is set to 1 The reset functions hardware software watchdog may be regarded as a type of trap Reset functions have the highest system priority trap priority Ill Class A traps have the second highest priority trap priority II on the 3 d rank are class B traps so a class A trap can interrupt a class B trap If more than one class A trap occur at a time they are prioritized internally with the NMI trap on the highest and the stack underflow trap on the lowest priority All class B traps have the same trap priority trap priority 1 When several class B traps get active at a time the corresponding flags in the TFR register are set and the trap service routine is entered Since all class B traps have the same vector the priority of service of simultaneously occurring class B traps is determined by software in the trap service routine A class A trap occurring during the execution of a class B trap service routine will be serviced immediately During the execution of a class A trap service routine however any class B trap occurring will not be serviced until the class A trap service routine is exited with a RETI instruction In this case the occurrence of the class B trap condition is stored in the TFR register but the IP value of the instruction which caused this trap is lost User s Manual 5 32 V2 0 2000 07 o nfine
601. y exist on instructions in different pipeline stages without a loss of performance This extra hardware i e for forwarding operand read and write values resolves most of the possible conflicts e g multiple usage of buses in a time optimized way and thus avoids that the pipeline becomes noticeable for the user in most cases However there are some very rare cases where the circumstance that the C167CS is a pipelined machine requires attention by the programmer In these cases the delays caused by pipeline conflicts can be used for other instructions in order to optimize performance Context Pointer Updating An instruction which calculates a physical GPR operand address via the CP register is mostly not capable of using a new CP value which is to be updated by an immediately preceding instruction Thus to make sure that the new CP value is used at least one instruction must be inserted between a CP changing and a subsequent GPR using instruction as shown in the following example Ts SCXT CP 0FCO0Oh select a new context Ij 1 must not be an instruction using a GPR IQ 2 MOV RO dataX write to GPR 0 in the new context Data Page Pointer Updating An instruction which calculates a physical operand address via a particular DPPn n 0 to 3 register is mostly not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction Thus to make sure that the new DPPn register val
602. y into the interrupt service routine or upon a PEC service In the case of PEC service the Interrupt Request flag remains set if the COUNT field in register PECCx of the selected PEC channel decrements to zero This allows a normal CPU interrupt to respond to a completed PEC block transfer Note Modifying the Interrupt Request flag via software causes the same effects as if it had been set or cleared by hardware The Interrupt Enable Control Bit determines whether the respective interrupt node takes part in the arbitration cycles enabled or not disabled The associated request flag will be set upon a source request in any case The occurrence of an interrupt request can so be polled via xxIR even while the node is disabled Note In this case the interrupt request flag xxIR is not cleared automatically but must be cleared via software User s Manual 5 7 V2 0 2000 07 o nfineon ed technologies Derivatives Interrupt and Trap Functions Interrupt Priority Level and Group Level The four bits of bit field ILVL specify the priority level of a service request for the arbitration of simultaneous requests The priority increases with the numerical value of ILVL so 0000g is the lowest and 1111g is the highest priority level When more than one interrupt request on a specific level gets active at the same time the values in the respective bit fields GLVL are used for second level arbitration to select one request for being serviced
603. yzer Different pipeline stages can simultaneously put a request on the External Bus Controller EBC The sequence of instructions processed by the CPU may diverge from the sequence of the corresponding external memory accesses performed by the EBC due to the predefined priority of external memory accesses 15 Write Data ond Fetch Code gid Read Data Initialization of Port Pins Modifications of the direction of port pins input or output become effective only after the instruction following the modifying instruction As bit instructions BSET BCLR use internal read modify write sequences accessing the whole port instructions modifying the port direction should be followed by an instruction that does not access the same port see example below PORT_INIT_WRONG BSET DP3 13 change direction of P3 13 to output BSET P3 9 7P3 13 is still input rd mod wr reads pin P3 13 PORT_INIT_RIGHT BSET DP3 13 change direction of P3 13 to output NOP any instruction not accessing port 3 BSET P3 9 P3 13 is now output rd mod wr reads P3 13 s output latch Note Special attention must be paid to interrupt service routines that modify the same port as the software they have interrupted Changing the System Configuration The instruction following an instruction that changes the system configuration via register SYSCON e g the mapping of the internal ROM segmentation stack size cannot use the new resources e g ROM or sta
604. zed according to the selected reset mode pins or default The respective configuration bitfields can be copied from register RSTCON upon entering Slow Down Divider mode if enabled by bit SUE 1 The following steps must be taken to change the current configuration see also SW example Write intended configuration value to RSTCON Enter SDD mode e Return to basic clock mode CHANGE CLOCK CONFIGURATION RSTCON is a mem address no SFR MOV R15 11100001xxxxxxxxB Load a GPR with the target value MOV RSTCON R15 Enable update with PLL factor 4 EXTR 2 ESFR access to SYSCON2 MOV SYSCON2 0100H SDD mode PLL on factor 1 RSTCON 15 9 is copied to RPOH 15 9 MOV SYSCON2 40400H Switch to basic clock mode System will run on PLL factor 4 after PLL has locked Note This software example assumes execution before EINIT Otherwise the unlock sequence has to be executed prior to each access to HSTCON SYSCON2 Entering SDD mode temporarily ensures a correct clock signal synchronization in cases where the clock generation mode e g PLL factor is changed If the target basic clock generation mode uses the PLL the C167CS will run in direct drive mode until the PLL has locked Software modification of system configuration values is protected by the following features e SYSCON is locked after EINIT RSTCON requires the unlock sequence after EINIT Copying RSTCON to RPOH must be explicitly enabled by

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