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IP470A User`s Manual

1. 4 UNPACKING AND 4 CARD CAGE CONSIDERATIONS 4 BOARD CONFIGURATION ax 4 CONNECTORS 3 iere pro neath 4 IP Field Connector 2 4 Noise and Grounding Considerations 5 IP Logic Interface Connector 1 5 3 0 PROGRAMMING 5 ADDRESS 5 5 Standard Default Mode Memory Map n 6 Enhanced Mode Memory 6 REGISTER 8 THE EFFECTOR onere 12 IP470A PROGRAMMING 12 Basic I O 12 Enhanced Operating 12 Event Sense Inputs 12 Change Of State Detection 13 Debounce Control eene 13 Interrupt 13 Programming 13 4 0 THEORY 15 IP470A 15 LOGIC POWER 15 KNOWN DIFF BETWEEN THE 470 AND IP470A 15 5 0 SERVICE AND 15 SERVICE AND REPAIR ASSISTAN
2. Debounce Duration Reg 1 Register 2 3 All Reads Writes 0 state 4 SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS REGISTER DEFINITIONS STANDARD MODE REGISTERS Port Registers Standard Mode Ports 0 5 Read Write Six Registers are provided to control monitor 48 possible I O points Data is read from or written to one of six groups Ports 0 5 of eight I O lines as designated by the address read and write signals Each port assigns the least significant data line DO to the least significant I O line of the port grouping e g 1 000 for port 0 Thus a write to this register controls the state of the open drain output low level true A read of this register returns the status ON OFF of the point A Mask Register is used to disable writes to I O ports designated as input ports That is when a port group of 8 lines is used as input port writes to this port must be blocked masked to prevent contention between the output circuitry and any external device driving this input line Outputs are open drain mosfets with pull ups installed Thus on power up or reset the port registers are reset to 0 forcing the outputs to be set high OFF Write Mask Register amp Enhanced Mode Select Register Standard Mode Port 7 Read Write This register is used to mask the ability to write data to the six ports Writing a
3. 5 9 _ o4 4 t os 28 o 2 s P ioo 15 Cos 39 1 o voto a o3 38 R 18 R 10 37 71 T wo 12 t wos 35 1 30 4 3 rors 09 P 25 P Wot 34 o wot 2 o 04 21 R _ 45 _ T 290 wot 44 2 18 5 42 5V OUT Note COMMON 1 By default pin 49 of P2 is connected to the 5 supply of the IP module but may be optionally connected to common or opened by repositioning surface mount resistor R72 see Drawing 4502 057 for location The 5V connection is in series with fuse F1 2A Littelfuse 245002 or equivalent Note that the points of this module are assembled in groups of eight Each group of eight I O lines is referred to as a port Registers at port addresses 0 5 control and monitor I O lines 00 47 Individual I O ports may be masked from writes to the port when the port is used for input This helps prevent contention errors Further event polarities may be defined as positive low to high or negative high to low for individual nibbles groups of 4 lines or half ports Outputs of this device are open drain and operate using low level true active low logic The pinouts of P2 are arranged to be compatible with SERIES IP470A INDUSTRIAL PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS similar industry models
4. 03 READ WRITE Port 2 voRegsteruoi6 i0z0 06 READ WRITE Port 3 voRegsteruozs io31_ or Register Port 1 I O Points 8 15 READ Port 2 Event Sense Status Reg Port 2 I O Points 16 23 WRITE Port 2 Event Sense Clear Register Port 2 I O Points 16 23 READ Port 3 Event Sense Status Reg Port 3 I O Points 24 31 WRITE Port 3 Event Sense Clear Register Port I O Points 24 31 READ Port 4 Event Sense Status Reg Port 4 I O Points 32 39 WRITE Port 4 Event Sense Clear Register Port 4 I O Points 32 39 READ Port 5 Event Sense Status Reg Port 5 I O Points 40 47 WRITE Port 5 Event Sense Clear Register Port 5 I O Points 40 47 READ WRITE Port 6 Not Driven NOT USED READ Port 7 Not Driven READ MASK REGISTER Not Driven WRITE MASK REGISTER Also Bank Select Register Event Sense Status Reg Port 0 I O Points 0 7 WRITE Port 0 Not Driven Port 0 I O Points 0 7 READ Port 1 Not Driven Event Sense Status Reg Event Sense Clear Not Driven 07 owe READ WRITE Port 4 Not Driven Register 032 1 039 READ WRITE Port 5 Not Driven Register 1 040 47 Also Current Bank Status WRITE Port 7 ENHANCED MODE REGISTER BANK 1 DEFINITION READ Port 0 Not Driven Event Sense Clear Register Port 1 I O Points 8 15 WRITE Port 1 oen M BILE ee Table 3 1B continued Base MS
5. 1 to bits 0 5 of the Mask Register will mask ports 0 5 from write control respectively A read of this register will return the status of the mask A Mask Register is used to disable writes to I O ports designated as input ports Thus when a port group of 8 lines is used for input writes to this port must be blocked masked to prevent contention between the output circuitry open drain and any external devices driving this port Standard Mode Write Mask Register Port 7 0 Porto Write Mask Port O Write 6 NOTUSED NOTUSED Bits 6 amp 7 of this register are not used On power up reset this register defaults to the unmasked clear state allowing writes to the output ports This register is also used to select the Enhanced Mode of operation To switch to Enhanced Mode four unique bytes must be written to port 7 in consecutive order without doing any reads or writes to any other port and with interrupts disabled The data pattern to be written is 07H ODH 06H and 12H in order and this must be written immediately after reset or power up ENHANCED MODE BANK 0 REGISTERS Port I O Registers Enhanced Mode Bank 0 Ports 0 5 Read Write Six I O Registers are provided to control monitor 48 possible I O points Data is read from or written to one of six groups Ports 0 5 of eight I O lines as designated by the address read and write signals Each port assigns the least significant
6. addresses in the I O Interrupt and ID spaces and produces the chip selects control signals and timing required by the control registers as well as the acknowledgement signal required by the carrier board per the IP specification It also stores the interrupt vector and controls whether event interrupts will drive the carrier board interrupt request line The ID Space read only is implemented in the FPGA and provides the identification for the individual module per the IP specification The ID Space amp configuration and control registers are all accessed through an 8 bit data bus interface to the carrier board KNOWN DIFFERENCES BETWEEN THE 470 AND IP470A Due to changes in the field I O circuitry the IP470A no longer has any measurable input hysteresis Additional specifications have also been added that were not defined on the original 470 including maximum slew rate output turn on and turn off time and input response time These specifications can be found in section 6 0 of this manual In addition further enhancements to the device include precision debounce no longer contains 25 error and a decrease in input capacitance In addition all IP read and write requests are acknowledged preventing a possible lock up of the bus The original 470 did not respond Ack to Not Used Registers and any system response would be defined by the carrier e g IP timeout Not Used registers always read as zero unless otherwi
7. on each of the Industrial I O Pack modules Field signals are accessed via screw terminal strips The terminal strip markings on the termination panel 1 50 correspond to P2 pins 1 50 on the Industrial I O Pack IP Each Industrial I O Pack IP has its own unique P2 pin assignments Refer to the IP module manual for correct wiring connections to the termination panel Schematic and Physical Attributes See Drawing 4501 464 Field Wiring 50 position terminal blocks with screw clamps Wire range 12 to 26 AWG Connections to Acromag non intelligent carrier boards P1 50 pin male header with strain relief ejectors Use Acromag 5025 550 x or 5025 551 x cable to connect panel to VME board Keep cable as short as possible to reduce noise and power loss Mounting Termination panel is snapped on the DIN mounting rail Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 C to 100 C Storage Temperature 40 to 100 C Shipping Weight 1 25 pounds 0 6kg packed TRANSITION MODULE MODEL TRANS GP Type Transition module for AVME9630 9660 boards Application To repeat field I O signals of IP modules A through D for rear exit from VME card cages This module is available for use in card cages which provide rear exit for I O connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6
8. 48 49 50 P1 12 34 5 6 7 8 9 10 111213 14 15 16 17 18 19 20 21 22 2324 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 MODEL 5025 552 TERMINATION PANEL SCHEMATIC X HIrrssrrsuPrrUTIUEENPSUUNNNDEJPA HAL BIN MOUNTING SHOWN DIN EN 50055 32mm ZA PANEL ACROMAG PART S NUMBER 4001 040 U RAIL DIN MOUNTING 3 032 MU SHOWN HERE 77 0 gt DIN EN 50022 35mm TB1 ies 2 4 Be em SLOT FOR m 5 345 A REMOVAL FROM T RAIL 135 0 TOP VIEW SIDE VIEW NOTES 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 DIMENSIONS ARE IN INCHES MILLIMETERS TOLERANCE 40 020 0 5 1 3 5 7 9 1113 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 ams
9. 58 5 FRONT VIEW MODEL 5025 552 TERMINATION PANEL 4501 464A C D 123 48 49 50 123 48 49 50 1253 48 49 50 123 48 49 50 CONNECTORS ON PC BOARD MODEL TRANS GP MODULE SCHEMATIC 123 48 49 50 123 48 49 50 123 48 49 50 123 48 49 50 CONNECTOR ON FRONT PANEL C D TOP VIEW 9 19 233 4 gt E W xj i L IU us q q 3 15 lt Te o lS 3 35 e wi dee X L HL 85 1 1 a Y Y B lt x lo EE a h FRONT VIEW 19 8 99 99 lt 10 31 261 9 NOTE DIMENSIONS ARE IN INCHES MILLIMETERS TRANS GP MECHANICAL DIMENSIONS AND SIMPLIFIED SCHEMATIC 4501 465 20
10. Application Used to connect Model 5025 552 termination panel to carrier board 50 pin field connectors Length Last field of part number designates length in feet 4 7 or 10 feet standard It is recommended that this length be kept to a minimum to reduce noise and power loss Cable 50 wire flat ribbon cable 28 gage Non Shielded cable model uses Acromag Part 2002 211 3M Type C3365 50 or equivalent Shielded cable model uses Acromag Part 2002 261 3M Type 3476 50 or equivalent Headers Both Ends 50 pin female header with strain relief Header Acromag Part 1004 512 3M Type 3425 6600 or equivalent Strain Relief Acromag Part 1004 534 3M Type 3448 3050 or equivalent Keying Headers at both ends have polarizing key to prevent improper installation Schematic and Physical Attributes For Shielded cable model see Drawing 4501 463 Shipping Weight 1 0 pound 0 5Kg packed TERMINATION PANEL MODEL 5025 552 Type Termination Panel For IP Carrier Boards Application To connect field I O signals to the Industrial I O Pack IP Termination Panel Acromag Part 4001 040 Phoenix Contact Type FLKM 50 The 5025 552 termination panel facilitates the connection of up to 50 field I O signals and connects to the AVME9630 9660 9668 or APC8620 21 17 non intelligent carrier boards via a flat ribbon cable Model 5025 550 x or 5025 551 x The A E connectors on the carrier board connect the field I O signals to the P2 connector
11. OHM 1 023 1 016 PULLUP PORT 2 MODEL IS SHIPPED WITH ONLY R7 INSTALLED 5V TO P2 PIN 49 R4 A R4 H 4 7K OHM 1 051 1 024 PULLUP PORT 5 3 FUSE F1 TIES P2 49 5V THROUGH 0 OHM RESISTOR R7 F1 IS 2 AMP R5 A R5 H 4 7K OHM 1 039 1 032 PULLUP PORT 4 LITTELFUSE 466003NR OR EQUIVALENT ACROMAG PART 1430 005 4 7K 1 047 1 04 PULLUP 4502 057 PIN 5 OF P1 amp P2 CONNECT TO 2 GROUND SHIELD P1 so 50 P2 P1 49 49 TO TO 48 48 AVME9630 9660 m MODEL 5025 552 47 47 CARRIER BOARD d 1 0 TERMINATION 46 46 P3 OR P4 P5 P6 PANEL 45 45 44 44 43 43 je x gt 42 42 41 41 FEET 40 40 TOP VIEW 39 39 38 38 37 37 36 36 35 E 34 34 STRAIN 50 PIN EA RELIEF RIBBON CABLE BLACK LINE ON CABLE CONNECTOR ET 1004 534 2002 261 INDICATES PIN 50 1004 512 30 30 29 29 28 28 27 27 26 26 25 25 24 24 23 25 22 22 POLARIZING 21 21 KEY 20 20 19 19 18 18 17 17 V 16 16 15 15 14 14 z 9 WY 11 11 50 19 10 CONNECTOR PIN 1 ON CABLE 5 2 NO MARKINGS STRAIN RELIEF 7 7 1004 534 FRONT VIEW 4 NOTE SEVEN DIGIT PART NUMBERS ARE 2 2 ACROMAG PART NUMBERS XXXX XXX 1 1 MODEL 5025 551 SCHEMATIC MODEL 5025 551 x SIGNAL CABLE SHIELDED 4501 463A SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS 125456 7 8 9 10111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 53 34 35 36 37 38 39 40 41 42 43 44 45 46 47
12. Pack IP Series IP470A module provides 48 channels of general purpose digital inputs and outputs for interfacing to the VMEbus or PCI bus according to your carrier board Four units may be mounted on a single carrier board to provide up to 192 I O points per system slot Inputs and outputs of this module are CMOS and TTL compatible Each of the I O lines can be used as either an input an output or an output with readback capability Each I O line has built in event sense circuitry with programmable polarity and interrupt support The inputs may also operate as independent event sense inputs without interrupts Outputs are open drain and may sink up to 15mA each A 4 7K pull up is provided for each drain and is installed in sockets on the board SIP resistors for easy removal or replacement Inputs include hysteresis and programmable debounce Interrupt event and debounce functionality applies to all 48 channels of this model The IP470A utilizes state of the art Surface Mounted Technology SMT to achieve its wide functionality and is an ideal choice for a wide range of industrial I O applications that require a high density highly reliable high performance interface at a low cost MODEL OPERATING TEMPERATURE RANGE IP470A 0 to 70 C 40 to 85 C KEY IP470A FEATURES e High Channel Count Provides programmable monitor and control of 48 I O points Four units mounted on a carrier board provide 192 I O points in a s
13. REQUIRED NOTE THAT OHM RESISTOR R7 TIES P2 PIN 49 TO 5V HOWEVER IT MAY BE REMOVED AND OHM RESISTOR R8 INSERTED TO TIE MODEL IP470 COMPONENT SIDE PARTIAL VIEW P2 PIN 49 TO SIGNAL COMMON 1 gt COM 2 AN RESISTOR SIPS ARE MOUNTED IP470A PARTIAL VIEW age ul gt IN SOCKETS AND CAN BE HR 1 RS PIN REMOVED IF REQUIRED HH r EB RESISTOR SIPS ARE H DIVIDED AS SHOWN ls 3 E gt gt BH BB 1 8 COMMON PIN RESISTOR SIPS ARE GROUPS OF EIGHT H 2 RESISTORS WITH COMMON 9 PINS MI BH PIN 1 POSITION IS IDENTIFIED BY A DOT B ille HH silo COMMON PINS OF ellg THE RESISTOR SIPS B 1 CONNECTED TO 5V TIF gt H Hg B lc ES DETAL E MODULE IS SHIPPED WITH ALL OTES CONCERNING PULLUP RESISTORS R1 R6 ZERO OHM RESISTORS R7 R8 AND FUSE F1 SIP RESISTORS INSTALLED 1 ALL 1 0 POINTS INCLUDE OPEN DRAIN OUTPUT CIRCUITRY WITH 4 7K OHM PULLUP RESISTORS TO 5V IN THE FORM OF SIP RESISTORS AS SHOWN THESE SIP RESISTORS ARE INSTALLED IN SOCKETS AND MAY SIP RESISTOR IDENTIFICATION BE MODIFIED AS REQUIRED SIP VALUE FUNCTION PORT 2 ZERO OHM RESISTOR R7 TIES P2 PIN 49 TO 5V THROUGH FUSE F1 R1 A R1 H 4 7K OHM 1 007 1 000 PULLUP PORT 2 ALTERNATELY R7 CAN BE REMOVED AND R8 CAN BE INSERTED TO TIE P2 PIN 49 R2 A R2 H 4 7K OHM 1 015 1 008 PULLUP PORT 1 TO GROUND R7 AND R8 ARE 0805 OHM RESISTORS ACROMAG PART 1400 214 R3 A R3 H 4 7K
14. and are directly compatible with industry accepted I O panels termination panels and relay racks Consult the factory for information on compatible products Noise and Grounding Considerations The IP470A is non isolated between the logic and field I O grounds since output common is electrically connected to the IP module ground Consequently the field connections are not isolated from the carrier board and backplane Special care has been taken in the design of this module to help minimize the negative effects of ground bounce impedance drops and Switching transients However care should be taken in designing installations without isolation to avoid noise pickup and ground loops caused by multiple ground connections This device is capable of switching many channels at high total currents Additionally the nature of the IP interface is inherently inductive channels have special circuitry to help protect the device from ESD over voltage and switching transients within limitations However when switching inductive loads it is important that careful consideration be given to the use of snubber devices to shunt the reverse emf that develops when the current through an inductor is interrupted Filtering and bypassing at the load may also be necessary Additionally proper grounding with thick conductors is essential Interface cabling and ground wiring should be kept as short as possible For outputs of this device the 4
15. other port and with interrupts disabled The data pattern to be written is 07H 06H and 12H and this must be written immediately after reset or power up In Enhanced Mode there are three groups or banks of eight registers or ports The first group bank 0 provides register functionality similar to Standard Mode The second group bank 1 provides monitor and control of the event sense inputs The third group bank 2 is used to configure the debounce circuitry for each input while in the Enhanced Mode Event Sense Inputs The IP470A has event sense logic built in for all 48 digital I O lines 1 000 through 1 047 Event sensing may be configured to generate an interrupt to the carrier or merely reflect the interrupt SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS internally Event sensing is enabled in Enhanced Mode only Inputs can be set to detect positive or negative events on a nibble by nibble group of 4 I O lines basis The event sensing is enabled on an individual channel basis You can combine event sensing with the built in debounce control circuitry to obtain glitch free edge detection of incoming signals To program events determine which I O lines are to have events enabled and which polarity is to be detected high to low level transitions negative or low to high level transitions positive Set each half port nibble to the desired polarity and then enable each of
16. the AVME9670 AVME9660 9630 APC8620A 21A ACPC8630 35 and ACPC8625 The software is implemented as a library of C functions which link with existing user code to make possible simple control of all Acromag PCI boards IP MODULE QNX SOFTWARE Acromag provides a software product sold separately consisting of board QNX software This software Model IPSW API QNX is composed of QNX real time operating system libraries for all Acromag IP modules and carriers including the 9670 AVME9660 9630 APC8620A 21A 8630 35 and ACPC8625 The software supports X86 PCI bus only and is implemented as library of C functions These functions link with existing user code to make possible simple control of all Acromag IP modules and carriers SERIES IP470A INDUSTRIAL PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS 2 0 PREPARATION FOR USE UNPACKING AND INSPECTION Upon receipt of this product inspect the shipping carton for evidence of mishandling during transit If the shipping carton is badly damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons
17. the event inputs to be detected Optionally load the interrupt vector register and enable the interrupt request line Note that all I O event inputs are reset set to negative events and disabled after a power up or software reset has occurred Note that no events will be detected until enabled via the Event Sense Status amp Clear Register Further interrupts will not be reported to the carrier board unless control of Interrupt Request Line 0 has been configured via the Interrupt Enable Register Change Of State Detection Change of State signal detection requires that both a high to low and low to high signal transition be detected On the IP470A if change of state detection for an input signal is desired two channels connected to the same input signal would be required one sensing positive transitions one sensing negative transitions Since channel polarity is programmable on a nibble basis group of four the first nibble of a port could be configured for low to high transitions the second nibble for high to low transitions As such up to 24 change of state detectors may be configured Debounce Control Debounce control is built into the on board digital FPGA employed by the IP470A and is enabled in the Enhanced Mode only You can combine debounce with event sensing to obtain glitch free edge detection of incoming signals for all 48 channels That is the debounce circuitry will automatically filter out glitches or tr
18. the port 7 address to mask writes to port 0 Read 01H from the port 7 address to verify bank 0 access bits 6 amp 7 0 and port 0 write masking bit O is 1 OPTIONAL Write your interrupt vector to the Interrupt Vector Register Address Note that this register operates independent of the current bank since it does not reside at any of the bank addresses OPTIONAL Write O1H to the Interrupt Enable Register IER address location to enable IP control of the IP Interrupt Request 0 line IntReqO When change of state is detected IntReqO will be pulled low if the event sense detection circuitry has been enabled and IER bit 0 1 In response the host will execute an Interrupt Select cycle and the contents of the Interrupt Vector Register will be provided To enable further interrupts to occur for an event that has already occurred for an point the Event Sense Status Register must be written with a 1 to reenable event sensing for subsequent events but only after first writing O to the corresponding bit position to clear the event sense flip flop Note that the state of the inputs on off can be determined by reading the corresponding port address while in bank 0 of the Enhanced Mode However the event sense status can only be read by reading the corresponding port address while in bank 1 of the Enhanced Mode Remember the event sense status is a flag that is raised when a specific positive or negative transition h
19. 0 has been enabled via the Interrupt Enable register IP Identification PROM Read Only 32 Odd Byte Addresses Each IP module contains an identification ID PROM that resides in the ID space per the IP module specification This area of memory contains 32 bytes of information at most Both fixed and variable information may be present within the ID PROM Fixed information includes the identifier model number and manufacturer s identification codes Variable information includes unique information required for the module The IP470A ID PROM does not contain any variable e g unique calibration information ID PROM bytes are addressed using only the odd addresses in a 64 byte block on the Big Endian VMEbus Even addresses are used on the Little Endian PC bus The IP470A ID PROM contents are shown in Table 3 2 Note that the base address for the IP module ID space see your carrier board instructions must be added to the addresses shown to properly access the ID PROM Execution of an ID PROM Read requires 0 wait states SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS Table 3 2 IP470A ID Space Identification ID PROM Hex Offset From ID PROM Base Address ASCII Character Equivalen Numeric Value Hex Field Description All IP s have IPAC 1 __ AcromagID Code 08 IPModelCode Not Used Revision 0 00 Reseved Not Used Driv
20. 2 amp 1 006 to the third and 1 003 amp 1 007 to the fourth Any change of state detected on these input signals will cause an interrupt to be generated SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS 1 After power up or reset the module is placed in the Standard Operating Mode To switch to Enhanced Mode execute four consecutive write cycles to port 7 with the following data 07H first followed by ODH followed by 06H then 12H At this point you are in Enhanced Mode bank 0 Port 7 would be used to access register banks 1 amp 2 Write 80H to the port 7 address to select register bank 2 where debounce will be configured for our port 0 input channels At this point you are in Enhanced Mode Bank 2 where access to the debounce configuration registers is obtained For our example we want use the 8MHz system clock to generate our debounce time By default the debounce clock is taken from 1 047 pin 41 of P2 Select the 8MHz system clock as the debounce clock by writing 01H to the port 3 address of this bank Debounce Clock Select Register The default debounce duration is 4us with the 8MHz clock selected in step 3 Write 01H to the port 1 address of this bank to select a 64us debounce time Debounce Duration Register 0 An incoming signal must be stable for the entire debounce time before it will be recognized as a valid input transition Note that Debounce Duration Register 1 p
21. 55 C to 105 C Shipping Weight 1 25 pounds 0 6Kg packed SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS M2 x 6 gt FLAT HEAD SCREW HREADED M2 gt SPACER NONE SIDE OF IP MODULE 8 COMPONENT SIDE OF CARRIER BOARD Ra P1 CONNECTOR FRONT 9 CONNECTOR Og 19 6 PAN HEAD SCREW ASSEMBLY PROCEDURE 1 THREADED SPACERS ARE PROVIDED IN TWO DIFFERENT LENGTHS THE SHORTER LENGTH IS FOR USE WITH AVME 9638 9660 CARRIER BOARDS SHOWN CHECK YOUR CARRIER BOARD TO DETERMINE ITS REQUIREMENTS MOUNTING HARDWARE PROVIDED MAY NOT BE COMPATIBLE WITH ALL TYPES OF CARRIER BOARDS 2 INSERT FLAT HEAD SCREWS ITEM A THROUCH SOLDER SIDE OF P MODULE AND INTO HEX SPACERS ITEM 8 AND TIGHTEN 4 P ACES UNTIL HEX SPACER IS COMPLETELY SEATED 3 CAREFULLY ALIGN IP MODULE TO CARRIER BOARD AND PRESS TOGETHER UNT ONNECTORS AND RS ARE SEATED 4 INSERT PAN HEAD REWS I EM C Ri 5 R SIDE OF CARRIER BOARD AND INTO HEX SPACERS ITEM B AND TIGHTEN 4 PLACES 5 IP47 A BLOCK DIAGRAM LOGIC Vo NTERFACE 52 1 DIN 49 3 3V VOLTAGE FPGA SIMPLIFIED V 3 3V 5V
22. 7 pull up resistors provide only limited digital drive capability Likewise outputs are intended to sink only 15mA or less As such the use of an interposing device may be required for controlling or isolating the load or to provide additional system protection The output pull up resistor SIP s are installed in sockets on the board allowing their values to be adjusted for greater drive capability if required see Drawing 4502 057 The signal ground connection at the I O ports is common to the IP interface ground which is typically common to safety chassis ground when mounted on a carrier board and inserted in backplane As such be careful not to attach I O ground to safety ground via any device connected to these ports or a ground loop will be produced and this may adversely affect operation IP Logic Interface Connector P1 P1 of the IP module provides the logic interface to the mating connector on the carrier board The pin assignments of P1 are standard for all IP modules according to the Industrial Specification see Table 2 2 This connector is a 50 pin female receptacle header which mates to the male connector of the carrier board This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 Screws and spacers are supplied with the IP module to provide additional stability for harsh environments see Drawing 4501 434 for assembly details Field and logi
23. Acromag 4 Series IP470A Industrial Pack 48 Channel Digital I O Module With Interrupts USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 Copyright 2006 Acromag Inc Printed in the USA Data and specifications are subject to change without notice 8500 793 A06E000 SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS The information contained in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update or keep current the information contained in this manual No part of this manual may be copied or reproduced in any form without the prior written consent of Acromag Inc Table of Contents Page 1 0 GENERAL 2 KEY IP470A 2 INDUSTRIAL I O PACK INTERFACE FEATURES 3 SIGNAL INTERFACE 3 INDUSTRIAL I O PACK 3 2 0 PREPARATION FOR
24. B LSB Base Addr 015 D08 D07 00 Addr ENHANCED MODE REGISTER BANK 1 DEFINITIONS READ Port 6 Event Status for Ports 0 5 and Interrupt Status Reg WRITE Port 6 Event Polarity Control Register for Port 0 3 READ Port 7 Event Polarity Control for Ports 4 amp 5 and Current Bank Status Reg WRITE Port 7 Event Polarity Control for Not Driven oc Not Driven Not Driven Ports 4 amp 5 and Bank Select Register ENHANCED MODE REGISTER BANK 2 DEFINITION READ WRITE Port 0 Not Driven Debounce Control Register for Ports 4 amp 5 WRITE ONLY Port 3 NOT USED 21 F READ WRITE Not Driven Interrupt Vector Register The Interrupt Vector Register also decodes at base address 6FH due to simplified address decoding READ WRITE Interrupt Enable Register enables INTREQO amp Software Reset Generator NOT USED for Ports 0 5 READ WRITE Port 1 BL Not Driven Debounce Clock Select 8MHz or 1 047 07 30 31 4 NOT USED 1 Notes Table 3 1 Debounce Duration Reg 0 for Ports 0 3 READ WRITE Port 2 08 Port 4 5 6 09 V Not Driven NOT USED Y READ WRITE Port 7 Not Driven Bank Status Select INDEPENDENT FIXED FUNCTION REGISTERS 1 The upper 8 bits of these registers are not driven and pull ups on the carrier data bus will cause these bits to read high 1 s The IP will return 0 for all addresses that are Not Used
25. CE i 15 PRELIMINARY SERVICE PROCEDURE 15 6 0 5 16 GENERAL SPECIFICATIONS m 16 16 DIGITAL INPUTS reir er ne pee descended eerte 16 DIGITAL 0000000 16 INDUSTRIAL I O PACK 17 APPENDIX CABLE MODEL 5025 550 amp 5025 551 17 TERMINATION PANEL MODEL 5025 552 17 TRANSITION MODULE MODEL TRANS GP 17 DRAWINGS Page 4501 434 MECHANICAL ASSEMBLY 18 4502 047 BLOCK 18 4502 057 PULLUP RESISTOR LOCATIONS 19 4501 463 CABLE 5025 551 SHIELDED 19 4501 464 TERMINATION PANEL 5025 552 20 4501 465 TRANSITION MODULE TRANS GP 20 IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ satisfactory overall system design It is agreed between the Buyer and that this is the Buyer s responsibility 1 0 GENERAL INFORMATION The Industrial I O
26. EBOUNCE CLOCK DO NOT SET THE 5 AN ACTIVE OUTPUT VIA THE PORT REGISTERS SETTING 1 047 AS AN ACTIVE OUTPUT MAY CAUSE A BUS CONFLICT Bank Select Write amp Status Read Register 2 Enhanced Mode Bank 2 Port 7 Read and Write Bits 0 5 of this register are not used Bits 6 amp 7 of this register are used to indicate read or select write the bank of registers to be addressed In Enhanced Mode three banks banks 0 1 amp 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of inputs Bits 7 and 6 select indicate the bank as follows Bank Select Write amp Status Read Register Bit7 Bit6 BANK OF REGISTERS 00 Bank 0 Read Write 1 Bank 1 Event Status Clear Bank 2 Debounce Control Clock amp Duration INVALID DO NOT WRITE 11 INDEPENDENT FIXED FUNCTION CONTROL REGISTERS Interrupt Enable amp Software Reset Register Read Write Bit 0 of this register specifies if the internal event sense interrupts are to be reported to the carrier or not i e whether they drive INTREQO or not This bit defaults to 0 interrupt request disabled and event interrupts are only flagged internally That is you would have to poll the Event Status Register to determine if an interrupt had occurred or not and the INTREQO line would not be driven I
27. OT USED Bank Select Bit 0 WRITE 1 POSITIVE Positive Events on Port 4 1 032 through 1 035 Positive Events on Port 4 1 036 through 1 039 Positive Events on Port 5 1 040 through 1 043 Positive Events on 7 Bank Select Bit 1 Bits 6 amp 7 of this register are used to select monitor the bank of registers to be addressed In Enhanced Mode three banks banks 0 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows Bank Select Register Write Bit 7 Bit6 BANK OF REGISTERS 00 Bank 0 Read Write 1 Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration INVALID DO NOT WRITE Bank Select Status Register 1 Enhanced Mode Bank 1 Port 7 Read Only Bits 0 5 of this register are not used Bits 6 amp 7 of this register are used to indicate the bank of registers to be addressed In Enhanced Mode three banks banks 0 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows 10 Bank Selected Status Register Read Bit7 Bit6 BANK OF REGISTER
28. PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS Turn On 125 5 Typical Turn Off Time 4 7K pull ups 2uS Typical INDUSTRIAL 1 0 PACK COMPLIANCE This device meets or exceeds all written Industrial Pack specifications per ANSI VITA 4 1995 for 8MHz operation Electrical Mechanical Interface Single Size IP Module Space IOSEL 16 bit or 8 bit read write of low byte ID Space IDSEL 8 bit read Supports Type 1 32 bytes per IP Consecutive odd byte address Interrupt Space INTSEL 8 bit read of Interrupt Vector Register contents Memory Space MEMSELY Not Used Power Up Initialization Time 200 5 Max During this time the IP module will ignore all signals Access Times 8MHz Clock All Read Write Cycles 0 wait states 250ns cycle APPENDIX CABLE MODEL 5025 550 x Non Shielded MODEL 5025 551 x Shielded Type Flat Ribbon Cable 50 wires female connectors at both ends The cables are available in 4 7 or 10 feet lengths Custom lengths 12 feet maximum are available upon request Choose shielded or unshielded cable according to model number The unshielded cable is recommended for digital I O while the shielded cable is recommended for optimum performance with precision analog I O applications Application
29. RANSLATION O BUFFER DEVIGE o 6E P 5V 4 3 3V FIELD PROGRAMMABLE GATE ARRAY I 5V to 3 3V P CONTROL BUS 4 7K 47 5k 25 DEBOUCE CHANGE OF 3 3V to 5V STATE INTERRUPT t CONTROL REGISTERS VOLTAGE ACKNOWLEDGE TRANSLATION U DEVICES m 7 5 1 0 CONTRO NTERRUPT LINE REGISTERS 5 E mm R i 5 52 5 2 gt NTERRUPT ENABLE DATA BUS 0 07 T NT REGISTER T P 547 35k TENE ADDRESS BUS ADDRESS BUS 047 Hi T 4750 VECTOR REGISTER 5 MET D SPACE INDIVIDUAL 1 0 LINES lt UDE ADDITIONAL ESD amp C OVER VOLTAGE PROTECTION 5V CIRCUITRY NOT SHOWN ION 5 3 FILTERING M 4 7K RESISTORS ARE S ED i 2 SUPPLY M GND N N 50 4502 047 18 SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS 19 PULLUP RESISTOR LOCATION DRAWING FOR REMOVAL AND REPLACEMENT WHERE
30. S 00 BankO0 Read Write 1 Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration INVALID DO NOT WRITE BANK 2 REGISTERS Debounce Control Register Enhanced Mode Bank 2 Port 0 Read Write This register is used to control whether each individual port is to be passed through the debounce logic before being recognized by the circuitry A 0 disables the debounce logic and a 1 enables the debounce logic Debounce is applied to both inputs and event sense inputs and only in Enhanced Mode Debounce Control Register BIT DEBOUNCE 0 00 07 Debounce Duration Register 0 Enhanced Mode Bank 2 Port 1 Read Write Debounce Duration Register 1 Enhanced Mode Bank 2 Port 2 Read Write These registers control the duration required by each input signal before it is recognized by each individual input in the Enhanced Mode both inputs and event inputs Register 0 controls debounce for ports 0 3 Register 1 controls debounce for ports 4 amp 5 If the debounce clock selected is the 8MHz IP clock see Debounce Clock Select Register then the debounce times are selected as shown below to within 250nS Alternately the debounce clock may be input on 1 047 and other values configured see Debounce Clock Select Register but this reduces the effective number of input channels to 47 Debounce Duration Register 0 0 Port 0 Debounce Value Bit 0 2 3 Duratio
31. U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to Acromag termination panel 5025 552 from the rear of the card cage and to AVME9630 9660 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Schematic and Physical Attributes See Drawing 4501 465 Field Wiring 50 pin header male connectors 3M 3433 D303 or equivalent employing long ejector latches and 30 micron gold in the mating area MIL G 45204 Type II Grade C Connects to Acromag termination panel 5025 552 from the rear of the card cage or to AVME9630 9660 9668 boards within card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Connections to AVME9630 9660 50 pin header male connectors 3M 3433 1302 or equivalent employing long ejector latches and 30 micron gold in the mating area per MIL G 45204 Type II Grade C Connects to 9630 9660 boards within the card cage via flat 50 pin ribbon cable cable Model 5025 550 X or 5025 551 X Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Mounting Transition module is inserted into a 6U size single width slot at the rear of the VMEbus card cage Printed Circuit Board Military grade FR 4 epoxy glass circuit board 0 063 inches thick Operating Temperature 40 to 85 C Storage Temperature
32. WRITE Port 7 WRITE MASK REGISTER Also Enhanced Mode Not Driven Select Register 10 11 y NOT USED 1 upper 8 bits of these registers not driven and pull ups on the carrier data bus will cause these bits to read high 1 s 2 The IP will return 0 for all addresses that are Not Used Enhanced Mode Memory Maps The following table shows the memory maps used for the Enhanced Mode of operation Enhanced Mode includes the same functionality of Standard Mode but allows each I O port s event sense input and debounce logic to be enabled Thus the Enhanced Mode allows input event triggered interrupts to occur In Enhanced Mode a memory map is given for each of 3 memory banks The first memory bank bank 0 has the same functionality as the Standard Mode Additionally its port 7 register is used to select which bank to access similar to Standard Mode where port 7 was used to select the Enhanced Mode Bank 1 provides read write access to the 48 event sense inputs Bank 2 provides access to the registers used to control the debounce circuitry applied to the event sense inputs SERIES IP470A INDUSTRIAL PACK 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Table 3 1B IP470A R W Space Address Hex Memory Map Base MSB LSB Base Addr D15 D08 D07 00 Addr memes ioveegiterioosror or Not Driven Register 00 07 READ WRITE Port 1
33. abled via the Event Sense Status Register Writing 0 to the corresponding event sense bit in the Event Sense Status Register will clear the event sense flip flop Successive interrupts will only occur if the event channel has been reset by writing a 1 to the corresponding event sense bit in the Event Sense Status Register after writing O to clear the event sense flip flop Interrupts may be reflected internally and reported by polling the module or optionally reported to the carrier by enabling control of the Interrupt Request line IntreqO Control of this line is initiated via bit O of the Interrupt Enable Register IER After pulling the IntReqO line low and in response to an Interrupt Select cycle the module will provide its 8 bit interrupt vector The interrupt vector is written to the Interrupt Vector Register The IP module will thus execute a read of the Interrupt Vector Register in response to an interrupt select cycle The IntReqO line will be released as soon as the conditions generating the interrupt have been cleared or return to normal and the event sense flip flop has been cleared by writing O to the corresponding bit position of the Event Sense Status Register or until the Interrupt Enable Register bit is cleared Zero wait states are required to complete an interrupt select cycle Note that the state of the inputs on off can be determined by reading the corresponding port address while in bank O of the Enhanced Mode Howev
34. and packing material be saved for future use in the event the product must be shipped This board is physically protected with packing material and electrically protected with an anti static bag during shipment However it is recommended that the board be visually inspected for evidence of mishandling prior to applying power CAUTION SENSITIVE ELECTRONIC DEVICES DO NOT SHIP OR STORE NEAR STRONG ELECTROSTATIC ELECTROMAGNETIC MAGNETIC OR RADIOACTIVE FIELDS The board utilizes static sensitive components and should only be handled at a static safe workstation CARD CAGE CONSIDERATIONS Refer to the specifications for loading and power requirements Be sure that the system power supplies are able to accommodate the power requirements of the carrier board plus the installed IP modules within the voltage tolerances specified IMPORTANT Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature The dense packing of the IP modules to the carrier board restricts airflow within the card cage and is cause for concern Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature and to prolong the life of the electronics If the installation is in an industrial environment and the board is exposed to environmental air careful consideration should be given to air filtering BOARD CONFIGURATION Power should be remov
35. ansients that can occur on received signals for error free edge detection and increased noise immunity With debounce an incoming signal must be stable for the entire debounce time before it is recognized by the or event sense logic Debounce is applied to both inputs and event sense inputs and only in Enhanced Mode The debounce circuitry can be configured to use the 8MHz carrier clock or a clock signal present on 1 047 to determine the debounce times see the Debounce Clock Select register If the debounce clock is taken from 1 047 then the effective number of inputs is reduced to 47 If the IP470A is configured to use the 8MHz carrier clock recommended a debounce value of 4us 64us 1ms or 8ms may be selected see the Debounce Duration Register As such an incoming signal must be stable for the debounce time before it is recognized by the pin or event sense logic A slower clock may be used to provide even longer debounce times this clock would have to be provided on 1 047 Upon initialization of the debounce circuitry be sure to delay at least the programmed debounce time before reading any of the 13 input ports or event signals to ensure that the input data is valid prior to being used by the software Interrupt Generation This model provides control for generation of interrupts on positive or negative events for all 48 channels Interrupts are only generated in the Enhanced Mode for event channels when en
36. as designated by the address and read and write signals A Mask Register is used to disable writes to I O ports designated as inputs to prevent possible contention between an external input signal and the output mosfet Enhanced Mode includes the same functionality of Standard Mode but adds access to 48 additional event sense inputs connected to each I O point of ports 0 5 Thus the Enhanced Mode allows event triggered interrupts to be generated Selectable hardware debounce may also be applied in Enhanced Mode for noise free edge detection of incoming signals Memory is organized and addressed in separate banks of eight registers or ports eight ports to a bank The Standard Mode of operation addresses the first group of 8 registers or ports ports 0 5 for reading writing 1 00 47 Port 6 which is not used SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS and Port 7 which is the Mask Register If the Enhanced Mode is selected then 3 additional banks of 8 registers are accessed to cover the additional functionality in this mode The first bank of the Enhanced Mode bank 0 is similar in operation to the Standard Mode The second bank bank 1 provides event sense and interrupt control The third bank is used to configure the debounce circuitry to be applied to input channels in the Enhanced Mode Two additional registers are provided to enable the interrupt request line generate a software reset and sto
37. as occurred for a given point while the state refers to its current level SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 4 0 THEORY OF OPERATION This section provides a description of the basic functionality of the circuitry used on the board Refer to the Drawing 4502 047 as you review this material IP470A OPERATION The IP470A is built around a Field Programmable Gate Array FPGA IC The device provides the control interface necessary to operate the module the IP identification space all registers and provides interface and configuration functions The FPGA monitors and controls the functions of the 48 digital I O used by this model It also provides debounce control and event sensing functions Electronic protection array circuitry is also installed on board for increased ESD and overvoltage protection of each I O line I O lines are pulled up to 5V via 4 7KQ SIP resistors installed in sockets on the board However weak internal pull ups of 47 5KQ nominal are always present on these lines with the SIP resistors removed LOGIC POWER INTERFACE The logic interface to the carrier board is made through connector P1 refer to Table 2 2 P1 also provides 5V to power the module the 12V lines not used Not all of the IP logic P1 pin functions are used The FPGA installed on the IP Module provides the control signals required to operate the board It decodes the selected
38. c side connectors are keyed to avoid incorrect assembly Table 2 2 Standard Logic Interface Connections P1 Pin Description Number Pin Description Number Doa 5 DwAReqg 30 D2 6 7 _ __ 32 o4 8 33 5 9 34 26 10 os 35 Do 11 REsERVED 2o 12 37 029 13 DMAEnd 38 no 14 a 39 0271 15 ERROR 4 012 16 a Lbs _ 42 _ HEN j e _ 5__ RESERVED GND An Asterisk is used to indicate an active low signal BOLD ITALIC Logic Lines are NOT USED by this IP Model 43 44 45 46 oar 48 49 50 3 0 ADDRESS MAPS This board is addressable in the Industrial Pack I O space to control the input output configuration control and status monitoring or 48 digital channels Each of the points can be configured as either an input an output or an output with readback capability Interrupt event and debounce capability applies to all 48 channels This board operates in two modes Standard Mode and Enhanced Mode Standard Mode provides simple monitor and control of 48 digital I O lines In Standard Mode each line is configured as either an input an output or an output with readback capability Data is read from or written to one of eight groups ports
39. carrier board see Interrupt Enable Register Event Interrupt Status Register For Ports 0 5 0 Porto Interrupt Status 0 7 6 NOTUSE Event Polarity Control Register For Ports 0 3 Enhanced Mode Bank 1 Port 6 Write Only A write to this register controls the polarity of the input sense event for nibbles of ports 0 3 channels 0 31 four channels at a time A 0 written to a bit in this register will cause the corresponding event sense input lines to flag negative events high to low transitions A 1 will cause positive events to be sensed low to high transitions The polarity of the event sense logic must be set prior to enabling the event input logic Note that no events will be detected until enabled via the Event Sense Status amp Clear Register Further interrupts will not be reported to the carrier board unless control of Interrupt Request Line 0 has been configured via the Interrupt Enable Register Event Polarity Control Register WRITE 0 NEGATIVE WRITE 1 POSITIVE Bir Port 0 1 00 through 1 03 Port 0 1 00 through 1 03 Port 0 1 04 through 1 07 Port 0 1 04 through 1 07 Port 1 1 08 through 1 011 Port 1 1 08 through 1 011 Negative Events on Port 1 1 012 through 1 015 Negative Events on Port 2 1 016 through 1 019 Negative Events on Port 2 1 020 through 1 023 Negative Events on Port 3 1 024 through 1 027 Negative Events on Port 1 028 through 1 031 P
40. data line DO to the least significant I O line of the port grouping e g 1 000 for port 0 A write to this register controls the state of the open drain output low level true A read of this register returns the status ON OFF of the point A Mask Register is used to disable writes to I O ports designated as input ports That is when port group of 8 I O lines is used as an input port writes to this port must be blocked masked to prevent contention between the output circuitry and any external devices driving this port Outputs are open drain mosfets with pull ups installed Thus on power up or reset the port registers are reset to 0 forcing the outputs to be set high OFF Write Mask Register And Bank Select Register 0 Enhanced Mode Bank 0 Port 7 Read Write This register is used to mask the ability to write data to the six ports in Enhanced Mode Writing a 1 to bits 0 5 of the Mask Register will mask ports 0 5 from write control respectively A read of this register will return the status of the mask A Mask Register is used to disable writes to I O ports designated as input ports Thus when a port group of 8 I O lines is used for input writes to this port must be blocked masked to prevent contention between the output circuitry and any external devices driving this port Enhanced Mode Write Mask Register Port 7 0 PortOWriteMask Port O Write 6 Bank SelectBito Bank Stat
41. e input is left floating Each line is in the form of an open drain signal Thus data written to any port used as an input must be masked or always false zero to avoid contention errors between the output circuitry and an input signal from an external device All 48 I O lines are placed into the false high output state following power up or a system reset The 4 7KQ pull up resistor SIP s installed in sockets on the board provide only limited digital high drive capability for the output signals You may need to adjust these pull up values for your application see Drawing 4502 057 for SIP resistor location Enhanced Operating Mode In the Enhanced Mode of operation each port signal has an associated event sense input and debounce logic circuit The event sense inputs are used to sense high to low level or low to high level transitions on digital input lines at CMOS thresholds Interrupts may also be triggered by events The optional debounce logic can act as a filter to glitches or transients present on the received signals Individual ports may be masked from writes to the port when the port is used for input This helps prevent contention errors Further event polarities may be defined as positive or negative for individual nibbles in groups of 4 I O lines or half ports The Enhanced Mode is entered by writing four unique bytes to the Port 7 register in consecutive order without doing any reads or writes to any
42. ed from the board when installing IP modules cables termination panels and field wiring Refer to Mechanical Assembly Drawing 4501 434 and your IP module documentation for configuration and assembly instructions Model IP470A digital I O boards have no hardware jumpers or switches to configure However 4 7KQ pull up resistor SIP s are installed in sockets on the board and these may be easily changed or removed where required see Drawing 4502 057 CONNECTORS IP Field I O Connector P2 P2 provides the field I O interface connections for mating IP modules to the carrier board P2 is a 50 pin female receptacle header which mates to the male connector of the carrier board AMP 173280 3 or equivalent This provides excellent connection integrity and utilizes gold plating in the mating area Threaded metric M2 screws and spacers are supplied with the module to provide additional stability for harsh environments see Mechanical Assembly Drawing 4501 434 The field and logic side connectors are keyed to avoid incorrect assembly P2 pin assignments are unique to each IP model see Table 2 1 and normally correspond to the pin numbers of the field I O interface connector on the carrier board you should verify this for your carrier board Table 2 1 IP470A Field I O Pin Connections P2 Pin Description Number Pin Description Number woo 8 P 7 _ voz 31 o woo 3
43. er ID Low Byte ILE E ID High Byte 15 Total Number of __ O ED CRC 19to3F _ __ NotUsed Notes Table 3 2 1 The IP model number is represented by a two digit code within the ID PROM the IP470A model is represented by 08 Hex THE EFFECT OF RESET Power up or bus initiated software reset will set the outputs to the false high state and place the module in the Standard Operating Mode thus disabling debounce and event detection Pull ups on the I O lines ensure a false high input signal for inputs left floating i e reads as 0 A reset will also clear the mask register and enable writes to the I O ports Further all I O event inputs are reset set to negative events and are disabled following reset The Interrupt Enable Register IER and Interrupt Vector Register IVR are also cleared except for IER generated software resets Another form of software reset IER register initiated acts similar to a carrier or power up reset except that it is not driven by the carrier and only resets the digital ASIC chip installed on the module As such the Interrupt Vector Register and Interrupt Enable Register are not cleared for a software reset initiated in this manner writing a 1 to the bit 1 position of the IER Register will cause this type of software reset to occur Reset in this manner has been provided for use with some ISA carriers which do not implement the bus re
44. er the event sense status can only be read by reading the corresponding port address while in bank 1 of the Enhanced Mode Remember the event sense status is a flag that is raised when a specific positive or negative transition has occurred for a given point while the state refers to its current level Note that the Interrupt Enable Register and Interrupt Vector Register are cleared following a power up or bus initiated Software reset but not a software reset initiated via writing a one to bit 1 of the Interrupt Enable Register Keep this in mind when you wish to preserve the information in these two registers following a reset PROGRAMMING EXAMPLE The following example outlines the steps necessary to configure the IP470A for Enhanced Mode operation to setup event generated interrupts configure debounce and read and write inputs It is assumed that the module has been reset and no prior non default configuration exists For this example we will configure port 0 I O points as a four channel change of state detector For change of state detection both positive and negative polarities must be sensed and thus two channels are required to detect a change of state on a single input signal 1 000 003 will be used to detect positive events low to high transitions 1 004 07 will be used to detect negative events high to low transitions 1 000 and 1 004 will be tied to the first input signal 1 001 amp 1 005 to the second 1 00
45. f bit O of this register is set to 1 then interrupts will drive the INTREQO line and permit Interrupt Select Cycles INTSEL to occur This bit is cleared following a system reset but not a software reset see below Writing a 1 to the bit 1 position of this register will cause a Software reset to occur be sure to preserve the current state of bit 0 when conducting a software reset This bit is not stored and merely acts as a trigger for software reset generation this bit will always readback as 0 The effect of a software reset is similar to a carrier reset except that it is not driven by the carrier and it only resets the digital ASIC chip that provides the field interface functions Likewise the Interrupt Vector Register or the Interrupt Enable Bit of this register is not cleared in response to a Software reset these are not stored in the ASIC It is useful for use with some carriers which do not implement the bus reset control Bits 2 7 of this register are not used and will always read high 1 s Interrupt Vector Register Read Write This 8 bit read write register is used to store the interrupt vector Interrupts are driven by events in the Enhanced Mode In response to an interrupt select cycle the IP module will execute a read of this register This register is cleared following a system reset but not a software reset Note that interrupts will not be reported to the carrier board unless control of Interrupt Request Line
46. from the card cage It is available for use in card cages which provide rear exit for connections via transition modules transition modules can only be used in card cages specifically designed for them It is a double height 6U single slot module with front panel hardware adhering to the VMEbus mechanical dimensions except for shorter printed circuit board depth Connects to AVME9630 9660 boards via a flat 50 pin ribbon cable within the card cage cable Model 5025 550 X or 5025 551 X IP MODULE Win32 DRIVER SOFTWARE Acromag provides a software product sold separately to facilitate the development of Windows 98 2000 applications accessing Industry Pack modules installed on Acromag PCI Carrier Cards and CompactPCI Carrier Cards This software Model IPSW API WIN consists of low level drivers and Windows 32 Dynamic Link Libraries DLLS that are compatible with a number of programming environments including Visual Visual Basic Borland Builder and others The DLL functions provide a high level interface to the carriers and IP modules eliminating the need to perform low level reads writes of registers and the writing of interrupt handlers IP MODULE VXWorks SOFTWARE Acromag provides a software product sold separately consisting of board VxWorks software This software Model IPSW API VXW is composed of VxWorks real time operating System libraries for all Acromag IP modules and carriers including
47. imes for all data transfer cycles are described in terms of wait states 0 wait states are required for all read and write operations of this model See Specifications section for detailed information SIGNAL INTERFACE PRODUCTS This IP module will mate directly to any industry standard IP carrier board Acromag s AVME9630 9668 3U 6U non intelligent VMEbus carrier boards and Acromag s APC862x series PCI bus carrier boards are supported A wide range of other Acromag IP modules are available to serve your signal conditioning and interface needs Cables Model 5025 551 X Shielded Cable or Model 5025 550 X Non Shielded Cable A Flat 50 pin cable with female connectors at both ends for connecting to the AVME9630 9660 other compatible carrier boards or Model 5025 552 termination panels The shielded cable is recommended for optimum performance with precision analog I O applications while the unshielded cable is recommended for digital I O The cables available in 4 7 or 10 feet lengths Custom lengths 12 feet maximum are available upon request Termination Panel Model 5025 552 DIN rail mountable panel provides 50 screw terminals for universal field I O termination Connects to Acromag AVME9630 9668 or other compatible carrier boards via flat 50 pin ribbon cable Model 5025 550 X or 5025 551 X Transition Module Model TRANS GP This module repeats field connections of IP modules A through D for rear exit
48. ingle VMEbus or PCI bus System slot e High Speed 0 Wait States No wait states are required for all read write cycles all cycles complete in 250ns and hold states are supported Programmable Polarity Event Interrupts all 48 channels Interrupts are software programmable for positive low to high or negative high to low input level transitions on all 48 channels Using two channels per input signal change of state transitions may also be configured for up to 24 inputs Programmable Debounce all 48 channels The event sense input circuitry includes programmable debounce times for all 48 channels Debounce time is the duration of time that must pass before the input transition is recognized as valid This helps prevent false events and increases noise immunity CMOS TTL Compatible Input threshold is at TTL levels and includes hysteresis circuitry uses CMOS technology As such output levels are CMOS compatible even while sinking high current see Specifications Section SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS Output Readback Function Readback buffers are provided that allow the output port registers to be read back e High Output Sink Capability All outputs may sink up to 15mA with a voltage drop x 0 5V e Outputs are Glitch Free Unlike some competitive units the outputs of this device do not glitch momentarily turn on upon power
49. l I O per European Norm EN50082 1 Surge Immunity Electric Fast Transient Immunity Complies with EN61000 4 4 Level 2 0 5KV at field I O terminals and European Norm EN50082 1 Meets or exceeds European Norm EN50081 1 for class equipment Shielded cable with connections in shielded enclosure are required to meet compliance Radiated Emissions DIGITAL INPUTS Input Channel Configuration Interrupts Input Voltage Range Input Low Voltage Range Input High Voltage Range Input transition rise of fall time Input Response Time Input Threshold Input Output Capacitance Input Leakage Current Debounce 16 Debounce Debounce Register Setting Count 00 32 01 512 10 8000 11 64000 DIGITAL OUTPUTS Output Channel Configuration Output Low Voltage Output High Voltage Output Current Range Output Ras ON Resistance Output Pullups 48 buffered inputs For DC voltage applications only observe proper polarity Input Debounce Each input includes debounce circuitry with variable debounce times Debounce times are programmable and derived from a clock signal present on 47 or the 8MHz sy
50. mm Board Thickness 0 062 inches 1 59 mm Max Component Height 0 314 inches 7 97 mm Connectors 1 amp 2 aco IP logic P1 amp field P2 interface connectors 50 pin female receptacle header Power 5 Volts 5 85 Typical all outputs active 35mA Typical all outputs inactive 160mA Maximum 12 Volts 5 from P1 Maximum Not Used ENVIRONMENTAL Operating Temperature 0 to 70 C 40 to 85 C E Versions Relative Humidity 5 95 non condensing Storage Temperature 55 C to 150 C Non Isolated Logic and field commons have a direct electrical connection Radiated Field Immunity RFI Complies with EN61000 4 3 10V m 80 to 1000MHz AM amp 900MHz keyed and European Norm EN50082 1 with no digital upsets Conducted RF Immunity CRFI Complies with EN61000 4 6 3V rms 150KHz to 80MHz and European Norm EN50082 1 with no digital upsets Electromagnetic Interference Immunity EMI No digital upset under the influence of EMI from Switching solenoids commutator motors and drill motors Electrostatic Discharge Immunity ESD Complies with EN61000 4 2 Level 3 8KV enclosure port air discharge and Level 2 4KV enclosure port contact discharge and European Norm EN50082 1 Not required for signa
51. n 8MHz 5 ort 2 Debounce Value Bit 1 Port 3 Debounce Value Bit 0 Port 3 Debounce Value Bit 1 2 3 P i 5 P i 6 i SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS Debounce Duration Register 1 DEBOUNCE CONTROL 0 Port4 Debounce Value Bit 0 Port 4 Debounce Value Bit 1 Port 5 Debounce Value Bit 0 Port 5 Debounce Value Bit 1 4 5 6 7 NOT USED Note that with 8MHz clock a debounce value of 00 sets nominal value of 4us 01 sets 64us 10 sets 1ms and 11 sets 8ms The default value is 00 setting a 4us debounce period for an 8MHz debounce clock When using 1 047 as the debounce clock the effective debounce can be calculated by taking the clock period in seconds and multiplying it by the appropriate constant shown in the table below The debounce will have an error of 2 clock periods Debounce Duration Debounce Selection Count Constant 12 8000 64000 Debounce Clock Select Register Enhanced Mode Bank 2 Port 3 Write Only This register selects the source clock for the event sense input debounce circuitry If bit O of this register is O default value then the debounce source clock is taken from 1 047 pin 41 of P2 thus reducing the effective number of inputs to 47 If bit O is set to 1 then the 8MHz IP bus clock is used recommended Bits 1 7 of this register are not used and will always read as zero WARNING IF USING 1 047 AS THE D
52. ort address 2 would be used to configure debounce durations for I O points of ports 4 amp 5 Enable the debounce circuitry for port 0 inputs by setting bit 0 of the Debounce Control Register Write 01H to the Port 0 address of this bank Debounce Control Register If the module had been configured earlier you would first read this register to check the existing settings of debounce enable for the other ports of this module with the intent of preserving their configuration by adjusting the value written above Write 40H to the port 7 address to select register bank 1 where the event polarity requirements of our application will be configured At this point you are in Enhanced Mode Bank 1 where access to the event polarity status registers is obtained For change of state detection both positive and negative polarities must be sensed As such two channels are required to detect a change of state on a single input signal For our example 1 000 003 will be used to detect positive events low to high transitions 1 004 07 will be used to detect negative events high to low transitions Write 01H to the port 6 address to set 1 000 1 03 to positive edge detection and 1 004 07 to negative edge detection Port 4 and 5 I O channels would use the Port 7 address Note that this port address has a dual function depending on whether a read or write is being executed As such if the current polarity configuration for the other ports mu
53. ositive Events on Port 1 1 012 through 1 015 Positive Events on Port 2 1 016 through 1 019 Positive Events on Port 2 1 020 through 1 023 Positive Events on Port 3 1 024 through 1 027 Positive Events on Port 3 1 028 through 1 031 SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS Event Polarity Control For Ports 4 amp 5 amp Bank Select Register Enhanced Mode Bank 1 Port 7 Read Write A write to this register controls the polarity of the input sense event for nibbles of ports 4 amp 5 channels 32 47 four channels at atime A 0 written to a bit in this register will cause the corresponding event sense input lines to flag negative events high to low transitions A 1 will cause positive events to be sensed low to high transitions The polarity of the event sense logic must be set prior to enabling the event input logic Note that no events will be detected until enabled via the Event Sense Status amp Clear Register Further interrupts will not be reported to the carrier board unless control of Interrupt Request Line 0 has been configured via the Interrupt Enable Register Event Polarity Control Register WRITE 0 NEGATIVE Negative Events on Port 4 1 032 through 1 035 Negative Events on Port 4 1 036 through 1 039 Negative Events on Port 5 1 040 through 1 043 Negative Events on Port 5 1 044 through Port 5 1 044 through 1 047 1 047 NOT USED N
54. ower up or system reset Standard Mode provides simple monitor and control of 48 digital I O lines In Standard Mode each I O line is configured as either an input or an output with readback capability but not both Data is read from or written to one of eight groups ports as designated by the address and read and write signals A Mask Register is used to disable writes to ports designated as input ports That is when a port group of 8 lines is used as an input port writes to this port must be blocked masked to prevent contention between the output circuitry and any external device driving this line To switch to Enhanced Mode four unique bytes must be written to port 7 in consecutive order without doing any reads or writes to any other port and with interrupts disabled This is usually done immediately after power up or reset The data pattern to be written is 07H ODH 06H and 12H and this must be written after reset or power up Table 3 1A IP470A R W Space Address Hex Memory Map Base MSB LSB Base Addr D15 D08 D07 00 Addr READ WRITE Port 0 iOegservoDuo Jor noon Not Driven Register 8 015 es Not Driven Register 1 016 23 ENTIER 5 Not Driven Register 1 024 31 07 a rone Not Driven Register 032 1 039 ENTE XP Not Driven Register 1 040 47 READ WRITE Port 6 Not Driven NOT USED READ
55. re the interrupt vector The space be as large as 64 16 bit words 128 bytes using address lines A1 A6 but the IP470A uses only a portion of this space The I O space address map for the IP470A is shown in Table 3 1 Note the base address for the IP module space see your carrier board instructions must be added to the addresses shown to properly access the space All accesses are performed on an 8 bit byte basis DO D7 This manual is presented using the Big Endian byte ordering format Big Endian is the convention used in the Motorola 68000 microprocessor family and is the VMEbus convention In Big Endian the lower order byte is stored at odd byte addresses Thus byte accesses are done on odd address locations The Intel x86 family of microprocessors use the opposite convention or Little Endian byte ordering Little Endian uses even byte addresses to store the low order byte As such use of this module on a PCI bus PC carrier board will require the use of the even address locations to access the 8 bit data while a VMEbus carrier will require the use of odd address locations Note that some functions share the same register address For these items the address lines are used along with the read and write signals to determine the function required Standard Default Mode Memory Map The following table shows the memory map for the Standard Mode of operation This is the Default mode reached after p
56. rresponding event sense input after it is cleared Reading ports 0 5 of Enhanced Mode bank 1 returns the current event sense flip flop status Port 0 Event Sense Status Register Ports 1 5 Similar READ PORT WRITE 0 WRITE 1 2 Port 0 1 00 Event Status Port 0 1 01 Event Status Port 0 1 2 Event Status Port 0 1 03 Event Status Port 0 1 04 Event Status Port 0 5 Event Status Port 0 1 6 Event Status Port 0 1 7 Event Status Clear 1 00 Event Sense Flip Flop Clear 1 01 Event Sense Flip Flop Clear 1 02 Event Sense Flip Flop Clear 1 03 Event Sense Flip Flop Clear 1 04 Event Sense Flip Flop Clear 1 05 Event Sense Flip Flop Clear l O6 Event Sense Flip Flop Clear 1 7 Event Sense Flip Flop Re enable 1 00 Event Sense Re enable 1 01 Event Sense Re enable 1 02 Event Sense Re enable 1 03 Event Sense Re enable 1 04 Event Sense Re enable 1 05 Event Sense Re enable 1 06 Event Sense Re enable Event Sense Event Interrupt Status Register For Ports 0 5 Enhanced Mode Bank 1 Port 6 Read Only Reading this register will return the event interrupt status of I O ports 0 5 bits 0 5 and the interrupt status flag bit 7 Bit 7 of this register indicates an event sense was detected on any of the 6 event sense ports 1 interrupt asserted event sensed Note that the interrupt status flag may optionally drive the Interrupt Request Line of the
57. se noted in this manual The jumper J1 on the IP470 has been replaced with two 0 Ohm resistors in the IP470A J1 was used to select either 5V or 15 Ground for Pin 49 of the Field I O That selection now requires removing a zero ohm resistor and replacing it with another Furthermore the SIP resistors though located in similar places on the board may pull up different signals See Acromag drawing 4205 057 for further details on both issues One additional difference is the power on initialization time for the IP470A has increased to 200ms maximum The module will not respond to any signal for up to 200ms following power up For further details on the differences between the models please contact Acromag 5 0 SERVICE AND REPAIR SERVICE AND REPAIR ASSISTANCE Surface Mounted Technology SMT boards are generally difficult to repair It is highly recommended that a non functioning board be returned to Acromag for repair The board can be damaged unless special SMT repair and service tools are used Further Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair PRELIMINARY SERVICE PROCEDURE Before beginning repair be s
58. set control or when the interrupt vector and interrupt enable information must be preserved following reset Basic Operation Note that the I O lines of this module are assembled in groups of eight Each group of eight I O lines is referred to as a port Ports 0 5 control and monitor I O lines 0 47 Additionally ports are grouped eight to a bank There are four banks of ports used for controlling this module Standard Mode plus Enhanced 12 Mode Banks 0 1 and 2 plus 2 additional registers for enabling the interrupt request line generating a software reset and storing the interrupt vector In both the Standard and Enhanced operating modes each group of eight parallel input lines port are gated to the data bus 07 lines These input signals are inverted when an output is ON set to 417 the transistor sinks current and drives the output low this is readback as a 1 Inputs include hysteresis Further each input port is connected such that the current status of a given output port can be read back via the corresponding input port Individual ports may also be masked from writes to the port when the port is intended for input only and this helps prevent contention errors Each port I O line includes an integrated 47 5KQ nominal pull up resistor to 5V Additional 4 7KQ pull up resistor SIP s are also installed in sockets on the board For inputs the pull ups provide a low false 0 input indication if th
59. st be preserved then it must be remembered since it cannot be read back 14 10 11 12 13 To enable event sensing for the port 0 I O points write to the Event Sense Status Register for port 0 I O points at the port 0 address in this bank Note that writing a 1 to a bit position enables the event sense detector while writing a O clears the event sensed without enabling further event sensing Write to the port 7 address to select register bank 0 where the port 0 input channels may be write masked Note that the port 7 address bank selection only operates from bits 6 amp 7 of this register while bits 0 3 are used to select the event polarity for port 4 amp 5 channels Keep this in mind when switching banks so as not to inadvertently change the polarity configuration of port 4 amp 5 input channels in the process of switching register banks Likewise this register has a dual function depending on whether a read or write is executed As such the polarity settings cannot be read back and must be remembered if they are to be preserved for successive writes At this point you are in Enhanced Mode Bank 0 where access to the write mask register is obtained For our example port 0 I O points to be used for inputs only and writes to this port should be masked to prevent the possibility of data contention between the built in output circuitry and the devices driving these inputs Write 01H to
60. stem clock in combination with the debounce duration register value Note that if the debounce clock is delivered on 1 047 then this effectively reduces the number of inputs to 47 As such use of the 8MHz system clock is recommended 48 channels of interrupts may be configured for high to low low to high and change of state two inputs required event types Ground 0 25V to 5 Volt supply 0 25V 0 8V Maximum to 0 25V below Common Ground 2 2V Minimum to Supply 0 25V Maximum 3mS V Maximum 250nS Typical 1 5V Typical 20pF Maximum 10pF Typical 10uA Typical The Input debounce is implemented using a counter The debounce time can be calculated by taking the clock period in seconds and multiplying it by the debounce count given in the table on the left Note that all debounce times including the internal 8MHz clock have a tolerance of 2 clock periods The default 8MHz has debounce times of 4us 64us 1ms or 8ms with an error of 250ns 48 open drain CMOS outputs For DC voltage applications only observe proper polarity 0 1VDC Typical 0 4VDC Maximum at 12mA Supply 0 2V at 10uA 0 to 15mA DC for x0 5V 330 Maximum 25 4 7KQ pull ups are installed in Sockets on the board Even with these pull ups removed weak integrated 47 5KQ nominal pull ups are always present See Drawing 4502 057 for resistor locations SERIES IP470A INDUSTRIAL I O
61. up or power down for steady and safe control Open Drain Outputs Include Pull ups All outputs include 4 7K pull ups to 5V in the form of resistor SIP s installed in sockets on the board for convenient removal or replacement e Overvoltage Protection Individual I O channels include over voltage clamps for increased ESD amp transient protection e High Impedance Inputs High impedance inputs minimize input current and loading of the input source No Configuration Jumpers or Switches All configuration is performed through software commands with no internal jumpers to configure or switches to set e Industry Compatible P2 Pinouts the field side P2 pinout configuration of this module is common to similar models and directly compatible with industry accepted digital I O cards screw termination panels and electromechanical amp solid state relay boards consult factory for recommendations INDUSTRIAL 1 PACK INTERFACE FEATURES e High density Single size industry standard IP module footprint Four units mounted on a carrier board provide up to 128 isolated input points in a single system slot Both VMEbus and PCI bus carriers are supported e LocalID Each IP module has its own 8 bit ID ROM which is accessed via data transfers in the ID Read space e 38 bit I O Port register Read Write is performed through 8 bit data transfer cycles in the IP module space High Speed with No Wait States Access t
62. ure that all of the procedures in Section 2 Preparation For Use have been followed Also refer to the documentation of your carrier board to verify that it is correctly configured Verify that there are no blown fuses Replacement of the carrier and or IP with one that is known to work correctly is a good technique to isolate a faulty board CAUTION POWER MUST BE TURNED OFF BEFORE REMOVING OR INSERTING BOARDS WHERE TO GET HELP If you continue to have problems your next step should be to visit the Acromag worldwide web site at http www acromag com Our web site contains the most up to date product and software information Go to the Support tab to access e X Application Notes Frequently Asked Questions FAQ s Product Knowledge Base Tutorials Software Updates Drivers An email question can also be submitted from within the Knowledge Base or directly from the Contact Us tab Acromag s application engineers can also be contacted directly for technical assistance via telephone or FAX through the numbers listed below When needed complete repair services are also available Phone 248 624 1541 Fax 248 624 9234 Email solutions acromag com SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL I O MODULE WITH INTERRUPTS 6 0 SPECIFICATIONS GENERAL SPECIFICATIONS Physical Configuration Single Industrial Pack Module iiem 3 880 inches 98 5 mm Width etate 1 780 inches 45 2
63. us Bito Bits 6 amp 7 of this register are used to select monitor the bank of registers to be addressed In Enhanced Mode three banks banks 0 2 of eight registers may be addressed Bank 0 is similar to the Standard Mode bank of registers Bank 1 allows the 48 event inputs to be monitored and controlled Bank 2 registers control the debounce circuitry of the event inputs Bits 7 and 6 select the bank as follows SERIES IP470A INDUSTRIAL I O PACK 48 CHANNEL DIGITAL MODULE WITH INTERRUPTS Enhanced Mode Bank Select Bit7 Bit6 BANK OF REGISTERS 00 Bank 0 Read Write 1 Bank 1 Event Status Clear 10 Bank 2 Event Debounce Control Clock and Duration INVALID DO NOT WRITE On power up reset the device is put into the Standard Mode and this register defaults to the unmasked state allowing writes to the output ports and bank 0 Default BANK 1 REGISTERS Event Sense Status amp Clear Registers For 1 00 47 Enhanced Mode Bank 1 Ports 0 5 Read Write Each I O line of each port includes an event sense input Reading each port will return the status of each port sense line Writing 0 for a bit position of each port will clear the event on the corresponding line When writing ports 0 5 of Enhanced Mode bank 1 each data bit written with logic O clears the corresponding event sense flip flop Each data bit of ports 0 5 must be written with a 1 to re enable or initially enable the co

IP470A User`s Manual

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