VDIP2 Vinculum VNC1L Module Datasheet
Contents
1. 3 6 3 SPI Slave Data Timing Diagrams SPICLK S SPICS SPI DATA IN a T6 T4 T5 SPI DATA OUT Figure 3 5 SPI Slave Data Timing Diagrams Time SPICLK Period SPICLK High 83 20 z 10 10 2 Ti T2 T3 T4 T5 T6 T7 Table 3 7 SPI Slave Status Register ADD 1 Copyright 2009 Future Technology Devices International Limited 12 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 T4 FTDI Document Reference No FT 000017 2 Clearance No FTDI 145 Chip 3 7 Signal Descriptions Parallel FIFO Interface The Parallel FIFO interface I O pin description of the VNC1L device is shown in Table 3 8 P Descipio OS inne meme me ee eee is o wo O fi fos 5 5 yo moomemasa ooo E Hie paese eEEEE yo FIFO Data Bus Bit 7 When high do not read data from the FIFO When low there is data available in the FIFO which can be read by stro bing RD low then high PEE OUTPUT in When high do not write data into the FIFO When low data can be FEE OUTPUT written into the FIFO by strobing WR high then low Enables the current FIFO data byte on DO D7 when low Fetched the next FIFO data byte if avail able fro m the recei ve FIFO buffer w hen INPUT RD goes fro m high to low Writes the data byte on the DO D7 pins into the transmit FIFO buffer 27 WR INPUT when WR goes from high to low Table 3 8 Default Interface I O Pin Configuration Option Para2. Taiwan R O C Tel 886 0 2 8791 3570 Fax 886 0 2 8791 3576 E mail Sales tw salesiQftdichip com E mail Support tw support1 ftdichip com E mail General Enquiries tw admini ftdichip com Web Site URL http www ftdichip com Branch Office Hillsboro Oregon USA Future Technology Devices International Limited USA 7235 NW Evergreen Parkway Suite 600 Hillsboro OR 97123 5803 USA Tel 1 503 547 0988 Fax 1 503 547 0987 E Mail Sales us salesQftdichip com E Mail Support us support ftdichip com E Mail General Enquiries us admin Gftdichip com Web Site URL http www ftdichip com Branch Office Shanghai China Future Technology Devices International Limited China Room 408 317 Xianxia Road ChangNing District ShangHai China Tel 86 21 62351596 Fax 86 21 62351595 E Mail Sales cn sales ftdichip com E Mail Support cn support ftdichip com E Mail General Enquiries cn adminiQftdichip com Web Site URL http www ftdichip com Distributor and Sales Representatives Document Reference No FT_000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Clearance No FTDIZ 145 Please visit the Sales Network page of the FTDI Web site for the contact details of our distributor s and sales representative s in your country Copyright 2009 Future Technology Devices International Limited 19 zg FTDI Document Reference No FT 000017 VDIP2 Vinculum
3. UM VinculumFirmware V205 pdf Copyright 2009 Future Technology Devices International Limited 16 Document Reference No FT_000017 Ta FTDI VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 A Clearance No FTDIZ 145 Chip Mechanical Dimensions 60 60mm 17 78mm Figure 5 1 VDIP2 Dimensions Top View 25 00mm 254mm Figure 5 2 VDIP2 Dimensions Side View Copyright 2009 Future Technology Devices International Limited 17 FTDI Document Reference No FT 000017 d VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 i a e Clearance No FTDI 145 Chip 6 Schematic Diagram JILVIN3HOS CdIG A WATANA GWEIN OR RRR RRR RRR lB R RR Rl RR Rl RRR R Figure 6 1 Schematic Diagram Copyright 2009 Future Technology Devices International Limited 18 48 FTDI Chip 7 Contact Information UN Y 4 Head Office Glasgow UK Future Technology Devices International Limited Unit 1 2 Seaward Place Centurion Business Park Glasgow G41 1HH United Kingdom Tel 44 0 141 429 2777 Fax 44 0 141 429 2758 E mail Sales sales1 ftdichip com E mail Support supporti ftdichip com E mail General Enquiries admini ftdichip com Web Site URL http www ftdichip com Web Shop URL http www ftdichip com Branch Office Taipei Taiwan Future Technology Devices International Limited Taiwan 2F No 516 Sec 1 NeiHu Road Taipei 114
4. VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDIZ 145 rm m Appendix A References http www vinculum com documents fwspecs UM VinculumFirmware V205 pdf Copyright 2009 Future Technology Devices International Limited 20 Document Reference No FT_000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Clearance No FTDI 145 Appendix B List of Figures and Tables List of Figures Figure 1 4 VDIDA os okolo seem osla nues UR VAGA Ex aha tera gale aon dv Slo OR ase E Fri Reman MA IAS Al a A Ne Ee 1 Figure 3 1 VDIP2 Module Pin Out Top View 4 Figure 3 2 VDIP2 On Board Jumper Pin Configuration cccceeeeee settee ee eee eee emen nemen 7 Figure 3 3 SPI Slave Data Read Cycle sex eegen sees anoda E dE RR KOH SEENEN ENNEN KENA EE KE KA Kea 10 Figure 3 4 SPI Slave Data Write Cycle 1 4 scies eene ten e nk nn hne ENEE ko Ra na KANA ER RD RR AX SERES RA EEN 11 Figure 3 5 SPI Slave Data Timing Diagrams sss menememememesememeh nie eene ese sene 12 Figure 3 6 FIFO Read CYC e te ita kase nar sena nn ne Han aka dana kagan arte RF UR ERU E RH KA KARA YRIERRYR KRKA K Y 14 Fig re 3 7 FIFO Write Cycles zzz intake died k ka kk Baia deed e Nee ee ia Ehud Ada a Za ie a 15 Figure 5 1 VDIP2 Dimensions Top View 17 Figure 5 2 VDIP2 Dimensions Side View excess esr sranani ANEREN dx ER ENEE SNE EEN 17 Fig re 7 1 Schematic Diagrami coiere ient ipie dee ina a RANNER KA A
5. no external supply necessary development module e Auxiliary 3 3 V 200 mA power output to e Schematics and firmware files available for external logic download from the Vinculum website Copyright 2009 Future Technology Devices International Limited 3 4 FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chi Clearance No FTDIZ 145 p ppr P 7 y A 7 HAS Tm Sp 3 Pin Out and Signal Description 3 1 Module Pin Out 1 AD6 JE LE ADS 20 AD7 M LE AD4 ACO By ii D3 AC1 MZ LJ AD2 AC2 By LJ AD1 GND By di GND AC3 Ma ii ADO AC4 vc GND ACS Ma dii GND RS By Ji BC3 PGH JE Aa BC2 3v3 E i SVO BDO E a BC BD1 EKZ cl BCO BD2 Hy LH BD7 BD3 EKZ Aa LED2 BD4 EKZ A LED 3v3 E E vo 3v3 JE i SVO 40 NC e CH NC USB1 USB2 Figure 3 1 VDIP2 Module Pin Out Top View Copyright 2009 Future Technology Devices International Limited 4 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 T4 FTDI Document Reference No FT 000017 2 Clearance No FTDI 145 Chip 3 2 Pin Signal Description GEG L On P gt 2 5V0 5V0 PWR Input 5 0 V module supply pin This pin provides the 5 0V output on the USB A type socket and also the 3 3V supply to VNCL2 via an on board 3 3 V L D O 3 5V0 5V0 PWR Input 5 0 V module supply pin This pin provides the 5 0V output on the USB A type socket and also the 3 3V supply to VNCL2 via an on boar
6. DIP2 s on board 3 3V L D 0 PWR Output 3 3V output from VDIP2 s on board 3 3V L D O NC eg No Connect Table 3 1 Pin Signal Descriptions Copyright 2009 Future Technology Devices International Limited 6 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 4 FTDI Document Reference No FT 000017 m H Clearance No FTDI 145 Ne Chip 3 3 I O Configuration Using The Jumper Pin Header Two three way jumper pin headers are provided to allow for simple configuration of the I O on data and control bus pins of the VDIP2 This is done by a combination of pulling up or pulling down the VNC1L ACBUS5 pin 46 and ACBUS6 pin 47 The relevant portion of the VDIP2 module schematic is shown in Figure 3 2 VNC1L 1A ACBUSS5 ACBUS6 GND Figure 3 2 VDIP2 On Board Jumper Pin Configuration ACBUS6 ACBUS5 I O Mode VNC1L pin 47 VNCIL pin 46 Pull Up Pull Up Serial UART UART Pull Down Pull Up Parallel FIFO Pull Down Pull Down Serial UART Table 3 2 VDIP2 Port Selection Jumper Pins Copyright 2009 Future Technology Devices International Limited 7 Document Reference No FT_000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Clearance No FTDI 145 3 4 Default Interface I O Pin Configuration The VNCiL device is pre programmed with default settings for the I O pins however they can be easily changed to suit a designers needs The default interface I O pin configuration of the VNCI1L devi
7. HS KE Red Ee ki rara P Eed EENS 18 List of Tables Table 3 1 Pin Signal Descriptions oisi etes a sa ku sa sas KME a da ESK ka RAN KENE ANERER riga Ra oe 5 Table 3 2 VDIP2 Port Selection Jumper Pins ccece cece eee 7 Table 3 5 Data and Control Bus Signal Mode Options SPI Slave Interface 10 Table 3 6 SPI Slave Data Timing iiie nenas ER KAR BA KA a spia sa a R BE RNA ESRB GA DAR ERR ANERE ee s a 12 Table 3 7 SPI Slave Status Register ADD 1 0 cece cece nner K K K K KK 12 Table 3 8 Default Interface I O Pin Configuration Option Paralle FIFO Interface 13 Table 3 9 FIFO Read Cycle Timing zas sad nd rk ee Ne dE se tonne suse xd qe ERR e ka ei Ga de Ee EES K EN 14 Table 3 10 FIFO Write Cycle TIMING NEE KEE nare ruth az ae x nrw ERR uen prune ENER RA apre a IX Tre Reg eier 15 Copyright 2009 Future Technology Devices International Limited 21 v FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDI 145 4 PU m a Appendix C Revision History Version 0 90 Initial Datasheet Created March 2007 Version 0 91 Datasheet Updated table 4 5 and 8 April 2007 Version 1 0 Datasheet Updated Reformatted 08 March 2010 Datasheet Updated Mechanical Drawings Added Appendix A and B Added schematic Copyright 2009 Future Technology Devices International Limited 22
8. Hold Time from WR 2 Mm Max fe Pu pum OTS s ns wr active to vaia Data La jm o fe NE Copyright 2009 Future Technology Devices International Limited 15 Z FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDI 145 LN A 4 Firmware 4 1 1 Firmware Support There are currently 6 standard firmware versions available for VDIP2 module which can be downloaded from the FTDI website e VDAP Firmware USB Host for single Flash Disk and General Purpose USB peripherals Selectable UART FIFO or SPI interface command monitor e VDPS Firmware USB Host for single Flash Disk and General Purpose USB peripherals USB Slave port connection for connecting to host PC Selectable UART FIFO or SPI interface command monitor e VDFC Firmware USB Host for two Flash Disks Selectable UART FIFO or SPI interface command monitor e VCDC Firmware USB Host for automatic connection to USB Communications Class Devices UART interface command monitor e VDIF Firmware USB Host for single Flash Disk and General Purpose USB peripherals Selectable UART FIFO SPI or USB interface command monitor 4 1 2 Firmware Upgrades The VDIP2 module is supplied pre loaded with the VDAP firmware There are two methods of upgrading the firmware on the VDIP2 These methods are described in a Vinculum Firmware manual please refer to http www vinculum com documents fwspecs
9. V VINCULUM BINDING USB TECHNOLOGIES Future Technology Devices International Ltd VDIP2 Vinculum VNC1L Module Datasheet Document Reference No FT 000017 Version 1 0 Issue Date 2010 03 08 Future Technology Devices International Ltd FTDI Unit 1 2 Seaward Place Centurion Business Park Glasgow G41 1HH United Kingdom Tel 44 0 141 429 2777 Fax 44 0 141 429 2758 E Mail Support supporti ftdichip com Web http www vinculum com Neither the whole nor any part of the information contained in or the product described in this manual may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder This product and its documentation are supplied on an as is basis and no warranty as to their suitability for any particular purpose is either made or implied Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product Your statutory rights are not affected This product or any variant of it is not intended for use in any medical appliance device or system in which the failure of the product might reasonably be expected to result in personal injury This document provides preliminary information that may be subject to change without notice No freedom to use patents or other intellectual property rights is implied by the publication of this document Future Technology Devices International Lt
10. a control bus AC bit 3 a UW a a a N Eh o lt BE z 5 z gt a z 5V safe bidirectional N co VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 T4 FTDI Document Reference No FT 000017 2 Clearance No FTDI 145 Chip 3 5 Signal Descriptions UART Interface The UART interface I O pin description of the VNC1L device are shown in Table 3 4 mmwo me me bee O Lim Transmit asynchronous data output RTS Request To Send Control Output Handshake signal CTS Clear To Send Control Input Handshake signal me DTR Data Terminal Ready Control Output Handshake signal a p DSR Data Set Ready Control Input Handshake signal Lus l Data Carrier Detect Control Input Ring Indicator Contro Input When the RemoteakeW up option is enabled in pe oe E RI Geet can be used to resume the PC Input B Ho TXDEN Enable Transmit Data for RS485 designs Table 3 4 Default I O Pin Configuration UART Interface Copyright 2009 Future Technology Devices International Limited 9 zg FTDI Document Reference No FT 000017 A VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 a Clearance No FTDIZ 145 5 Chip 3 6 Signal Descriptions Serial Peripheral Interface SPI The SPI I O pin description of the VNC1L device are shown in Table 3 5 GE e ORM snu N SCLK baat digs E spo Lama sp1 Serial Data Outpt cs mw menge ies Table 3 5 Data and Control Bus Signal Mode Optio
11. appui ap up 5vsa e bidirectional data control bus AD bit1 17 ADBUS2 AD2 VO Le safe bidirectional data control bus AD bt AD3 VO 5vsafe bidirectional data control bus AD DZ ADBUS4 ap uo Tou safe bidirectional data control bus ADbit4 20 ADBUSS ans yo 5V safe bidirectional data control bus AD bit 5 AD6 1yo __ 5V safe bidirectional data control bus AD bit6 ES 31 32 Can be used by an external device to reset the VNC1L This pin can be used in combi nation with PROG and the UART i o program firmware into the 30 RESET Input SK arallel FIFO SPI interface t r gt gt This pin is used in combination with the RESET pin and the PROG PG Input ART parallel FIFO Table 3 1 Pin Signal Descriptions Copyright 2009 Future Technology Devices International Limited 5 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDI 145 a aoe 38 C2 1 MO OF 33 BDBUSO Bo O yo 5V safe bidirectional data control bus BD bit 0 BDBUS1 ee 5V safe bidirectional data control bus BD bit 1 BDBUS2 Bp2 yo 5V safe bidirectional data control bus BD bit 2 T4 FTDI Document Reference No FT 000017 A a BDBUS3 ooo GEN safe bidirectional data control bus BD bit 3 BDBUS4 un sv 5V safe bidirectional data control bus BDbit4 bidirectional data control bus BD bit 4 E TE PWR Output 3 3V output from V
12. ce are shown in Table 3 3 Data and Control Bus Configuration i Options Description UART Parallel SPI Slave I O Port Interface FIFO Interface Interface ADBUSO SCLK PortADO ADBUS1 PortAD1 ADBUS2 PortAD2 ADBUS3 PortAD3 ADBUS4 PortAD4 ADBUS5 PortAD5 ADBUS6 PortAD6 data control bus ADBUS7 AD bit 7 PortAD7 5V safe bidirectional data control bus TXDEN ACBUSO AC bit 0 PortACO ACBUS1 PortAC1 ACBUS2 PortAC2 ACBUS3 PortAC3 data control bus ACBUS4 AC4 AC bit 4 PortAC4 Table 3 3 Default Interface I O Pin Configuration Copyright 2009 Future Technology Devices International Limited 8 5V safe bidirectional data control bus AD bit 0 A gt o 4 U 5V safe bidirectional data control bus AD bit 1 a gt F HH lt Ke O O Uu Ln 5V safe bidirectional data control bus AD bit 2 gt p el N LD o 5V safe bidirectional data control bus AD bit 3 el GA a a 5V safe bidirectional data control bus AD bit 4 A A z 5V safe bidirectional data control bus AD bit 5 gt Wu o ei Wu 5V safe bidirectional data control bus AD bit 6 N F gt a m z 5V safe bidirectional gt N gt U lt N N O N A lt z m and z N LA lt 5V safe bidirectional data control bus AC bit 1 2 gt N A N N N KA N ul o z gt z 5V safe bidirectional data control bus AC bit 2 z gt z 5V safe bidirectional dat
13. d Unit 1 2 Seaward Place Centurion Business Park Glasgow G41 1HH United Kingdom Scotland Registered Number SC136640 Copyright 2010 Future Technology Devices International Limited FA FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 H Clearance No FTDI 145 Chip 1 Introduction The VDIP2 module is an MCU to embedded USB host controller development module for the VNC1L I C device The VDIP2 is supplied on a PCB designed to fit into a 40 pin DIP socket and provides access to the UART parallel FIFO and SPI interface pins on the VNC1L device via its AD and AC bus pins All other Vinculum I O pins are also accessable Not only is it ideal for developing and rapid prototyping of VNC1L designs but also an attractive quantity discount structure makes this module suitable for incorporation into low and medium volume finished product designs Figure 1 1 VDIP2 The Vinculum VNCIL is the first of FTDI s Vinculum family of Embedded USB host controller integrated circuit devices Not only is it able to handle the USB Host Interface and data transfer functions but owing to the inbuilt MCU and embedded Flash memory Vinculum can encapsulate the USB device classes as well When interfacing to mass storage devices such as USB Flash drives Vinculum also transparently handles the FAT File structure communicating via UART SPI or parallel FIFO interfaces via a simple to implement command set Vi
14. d 3 3 V L D O LED1 LD1 Output USB port 1 traffic activity indicator LED This pin is hard wired to a green LED on board the PCB It is also brought out onto this pin which allows for the possibility of bring ing out an additiona LED traffic indicator out of the VDIP2 board For example if the VDIP2 USB connector is brought out onto an instrument front panel an activity LED could be mounted along side it 5 LED2 LD2 Output USB port 2 traffic activity indicator LED This pin is hard wired to a green LED on board the PCB It is also brought out onto this pin which allows for the possibility of bring ing out an additiona LED traffic indicator out of the VDIP2 board For example if the VDIP2 USB connector is brought out onto an instrument front panel an activity LED could be mounted along side it 6 BDBUS7 BDBUS7 ep vyo 5V safe bidirectional data control bus BD bit 7 BCBUSO Bon yo 5V safe bidirectional data control bus BC bit 0 BCBUS1 Ba vyo 5V safe bidirectional data control bus BC bit 1 aa 5V safe bidirectional data control bus BCbit1 5 0 V module supply pin This pin provides the 5 0V output on 5V0 5V0 PWR Input the USB A type Socket and also the 3 3V supply to VNC1L via 11 BCBUS3 BC3 VO 5vsa e bidirectional data control bus BCbit3 Module ground supply pin 14 ADBUSO apo 1o Le safe bidirectional data control bus ADbitO 15 Module ground supply pin 16
15. e No FTDI 145 Sw Chip 3 6 2 SPI Slave Data Write Cycle When in SPI mode the timing of a write operation is shown in RIWIADD D7 D6 DS D4 D3 D2 D1 Do DEET SE EE SPI Data In SPI Data Out Start Status Figure 3 4 SPI Slave Data Write Cycle From Start SPI CS must be held high for the entire write cycle and must be taken low for at least one clock period after t he write is co mpletedThe first bit on SPI Data In is the R W bit inputting a 0 here a llows data to be written to the chip The next bit is the address bit ADD which is used to indicate whether the data register 0 or the status register 1 is written to During the SPI write cycle a byte of data can be input to SPI Data In on the next clock cycle after t he address bit MSBAfterfirst t he data has been clocked in to the chip t he status of SPI Data Out should be checked to see if the data read was accepted A 0 level on SPI Data Out means that the data write was accepted A 1 indicates that the internal buffer is full and the write should be repeated Remember that CS must be held low for at least one clock period before being taken high again to continue with the next read or write cycle Copyright 2009 Future Technology Devices International Limited 11 v FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDI 145 3 p b gt
16. lle FIFO Interface Copyright 2009 Future Technology Devices International Limited 13 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Ze FTDI Document Reference No FT 000017 Clearance No FTDI 145 Chip 3 7 1 Timing Diagram Parallel FIFO Read Transaction When in parallel FIFO interface mode the timing of a read is shown in Figure 3 6 and Table 3 9 T6 RXF rs RD T1 Figure 3 6 FIFO Read Cycle Time Feet Mm Mex Unit m Ro Active Pulse win so ns T ROH to RDF Pre charge Time so Te ns T amp Vaia Date Ho time rom ROE o s m pormaeen o 25 e Ret inactive ater Ro yae so ns Table 3 9 FIFO Read Cycle Timing Load 30pF Copyright 2009 Future Technology Devices International Limited 14 V 3 py Z FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDIZ 145 NEN 3 7 2 Timing Diagram Parallel FIFO Write Transaction When in parallel FIFO interface mode the timing of a write operation is shown in Figure 3 7 and Table 3 10 T12 T11 TXE 17 wur T8 d WR T9 i T10 d Figure 3 7 FIFO Write Cycle Time WR Active Pulse Width T7 T8 WR to WR Pre Charge Time T9 i i T 8 T11 WR Inactive to TXE Ti TXE Inactive After WR Cycle Table 3 10 FIFO Write Cycle Timing 10 Data
17. nculum provides a new cost effective solution for providing USB Host capability into products that previously did not have the hardware resources available The VNC1L is available in Pb free RoHS compliant compact 48 Lead LQFP package Copyright 2009 Future Technology Devices International Limited 1 o F DI Document Reference No FT_000017 1 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 m a A Chip Clearance No FTDI 145 Table of Contents LO d e Un d EN dk EH Eege ege S Pin Out and Signal Description d St Module Pin OW eege eege eege deed EE Eege 4 3 2 Pin Signal Description seu vueee NN RENE VEER n nn nan ER EK E KEREN EE 5 3 3 I O Configuration Using The Jumper Pin Header 7 3 4 Default Interface I O Pin Configuration 8 3 5 Signal Descriptions UART Interface ee KN ENEE ENEE En 9 3 6 Signal Descriptions Serial Peripheral Interface SPI 10 3 6 1 SPI Slave Data Read Cycle ENNEN 10 3 6 2 SPI Slave Data Write Cvcle NENNEN 11 SPI Slave Data Timing Diagrams cece eect ee eee teeta eee eee ea nena nae 12 3 6 3 12 3 7 Signal Descriptions Parallel FIFO Interface 13 3 7 1 Timing Diagram Parallel FIFO Read Transachon 14 3 7 2 Timing Diagram Parallel FIFO Write Transachon 15 Prima BL uicsssEELIAMEIF IRL PEU IM MEUSE PEE MU EMEN NM A FU DNE E EM MEE UE 16 4 1 1 Fi
18. ns SPI Slave Interface 3 6 1 SPI Slave Data Read Cycle When in SPI mode the timing of a read operation is shown in Figure 3 3 RIW ADD D7 D6 D5 D4 D3 D2 D1 An m ANN LT Tt SPI Data In n VV VV SPI Data Out Start Status Figure 3 3 SPI Slave Data Read Cycle From Start SPI CS must be held high for the entire read cycle and must be taken low for at least one clock period after t he read is co mpleted The first bit on SPI Data In is the R W bit inputting a 1 here a llows data to be read fro m the chip The next bit is the address bit ADD which is used to indicate whether the data register 0 or the status register 1 is read from During the SPI read cycle a byte of data will start being output on SPI Data Out on the next clock cycle after t he address bit MSBAfterfirst t he data has been clocked out of the chip t he status of SPI Data Out should be checked to see if the data read is new data A 0 level here on SPI Data Out means that the data read is new data A 1 indicates that the data read is old data and the read cycle should be repeated to get new data Remember that CS must be held low for at least one clock period before being taken high again to continue with the next read or write cycle Copyright 2009 Future Technology Devices International Limited 10 74 FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 2 H Clearanc
19. rmware Support oue IRAN PDA REDE EON EON eta ER CEERVECE VE ORVERELEERVER LEER 16 4 1 2 Firmware Upgrades As aseene A De ee De EE ua ERI PIE ERI PR 16 Mechanical Dimensions 2 KENE E RENE KREE KREE Ku 17 Schematic Diagram eebe KEE ENEE EE enne nnnm nnns LO Contact Information sek K NEE EEN KEE KREE Ee une LO Appendix A References KRKKR KEREN EER KREE KE KKK EEK REENEN KKK RR 20 Appendix B List of Figures and Tables ees 21 RT AA HI 21 List OF Ta DIGS ege gege egge ge gege Eege EEN ge Eege 21 Appendix C Revision History e ENEE KEE KEE KEE KREE nnne 22 Copyright 2009 Future Technology Devices International Limited 2 Z FTDI Document Reference No FT 000017 VDIP2 Vinculum VNC1L Module Datasheet Version 1 0 Chip Clearance No FTDI 145 UN p 4 gt m 2 Features The VDIP2 has the following features e Uses FTDI s VNC1L embedded dual USB host Program or update firmware via USB Flash controller IC device disk or via UART Parallel FIFO SPI interface e Two vertically mounted USB A type USB e Power and traffic indicator LED s Socket to interface with USB peripheral devices s VNCIL firmware programming control pins e Jumper selectable UART parallel FIFO or SPI PROG and RESET brought out onto jumper MCU interfaces interface e Single 5V supply input from USB connection e VDIP2 is a Pb free RoHS complaint
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