Monza X-2K Dura Datasheet 3-24-14
Contents
1. El e E H 40 4Fn LOCK KLL 1 0 LOCK ACCESS 1 0 LOCK EPC 1 0 LOCK USER 1 0 BLOCK PERMALOCK 0 5 30n 3Fh ACCESS PASSWORD 15 0 3 20 2F ACCESS PASSWORD 31 16 2 RW 10 1F KILL PASSWORD 15 0 1 RW 00 0F KILL PASSWORD 31 16 0 RW Legends ROM Reged NVM Figure 8 I2C Interface Memory Map in a Word Wise format 2 5 DC Control of Monza X 2K Dura Behavior The DC interface can control Monza X 2K Dura behavior by writing to bytes 8 or 9 20 or 21 and 22 or 23 The following sections describe how control bits in these words change the behavior 2 6 Monza X 2K Dura I2C and Gen2 Lock Bits The lock bits for the kill password LOCK_KILL 1 0 the access password LOCK_ACCESS 1 0 the EPC memory bank LOCK_EPC 1 0 and the USER memory bank LOCK_ USER 1 0 are in byte eight of memory In each of these lock bit pairs bit one corresponds to pwd write or pwd read write and bit zero corresponds to the permalock bit Note that the I2C can always change the state of these bits and that their permissions only apply to the RF Gen interface Table 2 1 Lock Bit field functionality Associated memory bank is writeable from either the open or secured states Associated memory bank is permanently writeable from either the open or secured states and may never be locked Associated memory bank is writeable from the secured state but not from2. 23 Tape and REG CCI AION wa ahaa 24 Efrata a aiess 25 Introducing ImpinjO Monza X 8K Dura Error Bookmark not defined Ordern e Informations sssaaa ae rige edges eres eir trad cor Ue qal b pa na 27 Notices 28 Copyright O 2013 Impinj Inc 1 Monza X 2K Dura Datasheet Impinj 1 Introduction 1 4 Scope This datasheet defines the physical and logical specifications for Gen 2 compliant Monza X 2K Dura tag chip a reader talks first radio frequency identification RFID component operating in the UHF frequency range 1 2 Reference Documents EPC Radio Frequency Identity Protocols Class 1 Generation 2 UHF RFID Protocol for Communications at 860 MHz 960 MHz Version 1 2 0 Gen 2 Specification The conventions used in the Gen 2 Specification normative references terms and definitions symbols abbreviated terms and notation were adopted in the drafting of this Monza X 2K Dura Tag Chip Datasheet Users of this datasheet should familiarize themselves with the Gen 2 Specification EPC Tag Data Standards Specification EPCglobal Interoperability Test System for EPC Compliant Class 1 Generation 2 UHF RFID Devices v 1 2 4 August 4 2006 Monza X 2K Dura tag chips are compliant with this Gen 2 interoperability standard I2C Specification Rev 03 June 19 2007 NXP Doc UM10204 Copyright O 2013 Impinj Inc 2 w Par
3. _ x9 a L 32 E 3 BE G 34 38 xx TM A 40 39 BS A c ma BEN ra Em Bee ale 8 9 M E ex oon l gl 5 im Si as a Say IET TAG Figure 7 I2C Interface Memory Map in a Byte Wise format Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 8 Part Order IPJ P6001 Q2AT Impinj MEM 12C BANK NAME BIT ADDR ATOnATFn TID SERAL 47 32 AG0 AGFh TOTS 15 0 0x2000 A50n A5Fh TID DESIGNER 3 0 0001 TID MODEL 11 0 000101000000 Gen2 model number is address 14 to 1Fk AMs MFs CLASS ID 7 0 11100010 XIID 1 TID DESIGNER 10 4 0000000 Gen2 mask designer is address 08 to 13 A30 AF QT EPC 15 0 A20 A2F QT EPC 31 16 ATO ATE QT EPC 47 32 A00 A0F QT EPC 63 48 SF0 9FF QT EPC 79 64 SE0 9EF QT EPC 95 80 9D0 9DF TID SERAL 15 0 9C0 9CF TID SERAL 31 16 9B0 9BF USER 15 0 9A0 9AF USER 31 16 TID 102 User 112 150n 15F n USER 2159 2144 1401 14Fn USER 2175 2160 1304 13F EPC 15 0 120 12Fi EPC 31 16 110n 11F EPC 47 32 100 10Fn EPC 63 48 FOn FFn EPC 79 64 EO EF EPC 95 80 DOn DFh EPC 111 96 COn CFh EPC 127 112 BOn BFh EPC LENGTH 4 0 NSI 8 0 Numbering System Identifier default 0000000002 QT MEM JDCI RF EN RF DIS 1 0
4. 2175 2160 RFS EPC 15 0 RFS EPC 31 16 RFS EPC 47 32 RFS EPC 63 48 RFS EPC 79 64 RFS EPC 95 80 TID SERIAL 15 0 TID SERIAL 31 16 TID SERIAL 47 32 TDTS 15 0 0x2000 TID DESIGNER 3 0 0001 TID MODEL 12 0 0001010000002 Gen2 model number is address 14 to 1F CLASS ID 7 0 11100010 TID DESIGNER 10 4 0000000 Gen2 mask designer is address 08 to 134 EPC 15 0 EPC 31 16 TID 102 EPC 111 96 EPC 127 112 EPC LENGTH 4 0 NSI 8 0 Numbering System Identifier default 0000000002 EPC CRC 15 0 iir a ne SS ETT E TOs TFn LOCK _KILL 1 0 LOCK ACCESS 1 0 LOCK EPC 1 0 LOCK USER 1 0 BLOCK PERMALOCK 0 5 CONFIG 1 0 ACCESS PASSWORD 15 0 ACCESS PASSWORD 31 16 KILL PASSWORD 15 0 KILL PASSWORD 31 16 Reserved 002 Legends ReadOnly Memory Read Write Memory Figure 2 Gen2 Interface Memory Map 2 2 Support for Optional Gen 2 Commands Following optional Gen 2 commands are supported Command Details Access 11000110 BlockWrite 11000111 Accepts valid one word commands Accepts valid two word commands if pointer is an even value Returns error code 000000002 if it receives a valid two word command with an odd value pointer Returns error code 000000002 if it receives a command for more than two words Does not respond to bl
5. the open state tasheet Copyright 2013 Impinj Inc 9 Associated memorv bank is not writeable from anv state pwd AYA ermalock Description Associated password location is readable and writeable from either the open or secured states 1 Associated password location is permanently readable and writeable from either the open or secured states and may never be locked 1 Associated password location is readable and writeable from the secured state but not from the open state Associated password location is not readable or writeable from any state 2 7 Monza X 2K Dura I2C and Gen2 BlockPermalock Monza X 2K Dura will segments user memory into five blocks Blocks zero through four may be blockpermalocked from either the Gen2 interface or the I2C interface A blockpermalocked block allows reads but not writes to the block Blockpermalocking is permanent for blocks one through four and may not be unlocked from either interface The blockpermalock may be undone for block zero from the I2C interface and I2C ignores the blockpermalock permission for block zero The five blocks as seen from the I2C interface are shown in Figure 9 The five blocks in the User memory bank as seen from the Gen2 interface are e Block 0 bit address 0 to bit address 512 bit block size e Block 1 bit address 512 to bit address 1023 512 bit block size e Block 2 bit address 1024 to bit address 1535 512 bit block size e Block 3 bit address 1536
6. 5 6 7 IO aa 2 APA A 2 Reference DI UA 2 Functional DeSCHDIOlB ii 3 Reader Communications Gen2 RF Commands essen 3 Support for Optional Gen 2 CORDES uiae etis pss tenentur ena e Rn soar teo ei Beda 4 I2C Interface SDA SCL DCI Pins eeeesseeeseeeeeeeeneneeneren ener nennen enters 5 PC Memory MA si i aa 7 I2C Control of Monza X 2K Dura Behavior nn enennnnnnnennnnnnnnnnnenanznananza 9 Monza X 2K Dura I2C and Gen2 Lock Bits enennenennennnnnennnnnenanznanaz sa 9 Monza X 2K Dura I2C and Gen2 BlockPermalock eene 10 Monza X 2K Dura I2C Control of Config 1 0 Bits nee nn nn 11 Monza X 2K Dura Control of the QT Function eese 11 Monza X 2K Dura I2C Control of Gen2 Response to Ack Command 11 RE Ace Li se eorura dt a bcn ld ees abes A duet QE dua Dads 12 Gg IAEA rbit U s oe ese intera tamdiu rapto nfi tard EREE EEA M Dis EE 12 Write Wakeup MOJA T X 14 Chip BI ers ak sie ib is d ib d band ab a bb b ad 15 Physical Chaani ia 15 Absolute Maximum Rani ia 16 Reflow Temperature Profile iia 17 Electrical t batatterni sua tii rat aa 17 Memory Charge pe istis e a nS DM s MEE 20 RE Punctiona ura P 21 PC Brite ur ils ERE 21 NVM Usage Model miwa 22 Environmental Compliance s dead aa d ae 22 Product Del vers Spe i i Ga o i oue e E E E a tea 23 Marking Specification 1
7. Gen2 interface When the bit is set Monza X 2K Dura is in public mode user memory bank is hidden TID serialization is hidden and uses its QT EPC in the EPC bank When the bit is cleared Monza amp X 2K Dura is in private mode and all of its memory is exposed The memory map in Figure 2 shows the Monza X 2K Dura memory in private mode The DCI EN RF EN bit and the RF DIS 1 0 bits in byte 21 are covered in the section on RF access control 2 10 Monza X 2K Dura I2C Control of Gen2 Response to Ack Command The length field in byte 22 may be written from I2C The length field specifies the number of words backscattered in response to a Gen2 Ack command Byte 22 also contains an NVM space Copyright O 2013 Impinj Inc 11 for the UMI bit which may be read or written from I2C The NVM bit is not used since it is automatically calculated per the Gen2 specification The Gen2 UMI bit is calculated from the bitwise or of bits five through zero in byte 40 2 11 RF Access Control Monza X 2K Dura provides three levels of control over RF access as follows 1 Setting either or both the RFI DIS or RF2 DIS bits in byte 21 of the NVM disables RF access on the corresponding RF port These bits are accessible only to I2C not RF The factory defaults are 0 enabling RFI and RF2 2 Setting the DCI RF EN bit to 0 in byte 21 of the NVM inhibits all RF access when DCI voltage is present This takes precedence over the state of the RFI DIS RF2 DIS
8. SLEEP DCI 44 4ms gt SCL RF GEN2 RF WRITE CMD Figure 11 Monza X 2K Dura write wake up mode schematic and timing diagram Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc 14 EE Part Orders IPJ P6001 Q2AT Impinj 3 Chip Characteristics 3 1 Physical Characteristics Parameter Description Condition Min Nom Max Units Comments IC package Chip package XQEN 8L 1 65x1 65x0 35mm 2 Port RF 2 Port2 RF 2 DCI gnd 2 DC SDA SCL Pin count Package pins 2x SIs Tz Mena Figure 12 Packing Dimensions Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 15 3 2 Absolute Maximum Ratings Parameter Description Condition Min Max Units Comments From the I2C spec the max DC voltage p beolute UA Al is 3 3V 20 max maximum except operating voltage pin voltage 0 5V for survivability voltage on any chip pin DCI See Read Write Operating Temperature for full Sensitivity for specified performance temperature ranges in Temperature Section 3 4 Persistence Temperature for Gen2 i decns Temperature flag persistence for flag persistence Storage Temperature for 10 yr See Impinj s NVM temperature NVM retention usage model Peak temp of Temperature for reflow JEDEC MO255 for soldering
9. interrupt Monza X 2K Dura in Idle or RF Receive by this means the RC port exercises priority over the RF port and may not be locked out Note that RC is locked out when Monza X 2K Dura transitions to Internal Control to execute the command In certain operating states and under certain conditions Monza X 2K Dura may appear unresponsive to an I2C master for up to 20 milliseconds During a slow Gen2 backscatter This datasheet recommends that an I2C master have a retry algorithm that can accommodate Monza X 2K Dura being busy Internal Control IDLE or RF Receive Figure 10 Monza X 2K Dura operating states Monza X sheet Copyright 2013 Impinj Inc 13 2 13 Write Wakeup Mode Monza X 2K Dura has a wake up feature that is tied to writes being performed over the Gen2 interface In order to enable this feature the I2C master must set the WWU bit bit 6 of byte 21 to one Then the master must set the Monza X 2K Dura s DCI pin to 0V Sleep mode The SCL and SDA lines must remain high but draw no current A reader may continue to interact with Monza X 2K Dura on the RF ports If a reader performs a write operation and the wake up mode is set Monza amp X 2K Dura will assert the SCL IO pulling the SCL line low for the duration of the write operation approximately 4ms This transition may then be detected by the sleeping master and used to wake up the system I2C BUS Pullup Resistor Monza X 2K ACTIVE
10. to bit address 2047 512 bit block size e Block 4 bit address 2048 to bit address 2175 128 bit block size Please see the Gen2 specification for details on how a reader may lock the memory via BlockPermaLock command The mechanism for a microprocessor permalocking over I2C is as follows Execute a one word 2 byte write to bytes eight and nine word address four There are five blockpermalock bits in byte nine that control the write permission to the five user memory blocks Monza X 2K Dura will bitwise OR each of the current permalock bits with the four bits corresponding to blocks one through four and write the updated word into NVM Block zero may be unlocked via the I2C interface Monza X 2K Dura does not allow unlocking of blockpermalocked memory in blocks one through four via either the Gen2 interface or I2C interface To control the Gen2 interface access to the BlockPermalock command the I2C interface will have a BlockPermalock command enable bit that only it can write to When the bit is set Monza X 2K Dura will execute valid BlockPermalock commands and when it is cleared it will ignore all BlockPermalock commands The location of the BPL EN bit is in bit five of byte 21 Copyright O 2013 Impinj Inc 10 Part Order IPJ P6001 Q2AT Impinj Gen2 GEN2 I2C l I2C Block ke I BYTE BIT ADDRESS in BYTE Pema ais NAME ADDR Lockable ma 7 6 5 4 3 2 1 0 Lockable USER Block 3 USER Block 3 USER Black 2 USER Blo
11. 01 Q2AT Impinj 7 Ordering Information Part Number User Memory Package Size Monza X 2K Dura IPJ P6001 02AT 2 176 bits 1 6x 1 6x 0 35 mm Monza X 8K Dura IPJ P6005 X2AT 8 192 bits 2 0 x 2 0 x 0 35 mm Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 27 Notices Copyright 2013 Impinj Inc All rights reserved Impinj gives no representation or warrantv express or implied for accuracv or reliabilitv of information in this document Impinj reserves the right to change its products and services and this information at anv time without notice EXCEPT AS PROVIDED IN IMPINJ S TERMS AND CONDITIONS OF SALE OR AS OTHERWISE AGREED IN A VALID WRITTEN INDIVIDUAL AGREEMENT WITH IMPINJ IMPINJ ASSUMES NO LIABILITY WHATSOEVER AND IMPINJ DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATED TO SALE AND OR USE OF IMPINJ PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY PATENT COPYRIGHT MASK WORK RIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT IS GRANTED BY THIS DOCUMENT Impinj assumes no liability for applications assistance or customer product design Customers should provide adequate design and operating safeguards to minimize risks Impinj products are not designed warranted or authorized for use in any product or application where a malfunction may reasonably be expected to cause personal inju
12. Part Order f IPJ P6001 02AT Impinj Impinj Monza X 2K Dura Datasheet Rev 1 51 March 24 2014 Monza X 2K Dura is a UHF Gen2 RFID IC product with 2176 bits of Non Volatile Memory NVM and an I2C interface As an I2C device Monza amp X 2K Dura operates as a standard I2C EEPROM The contents of this EEPROM can also be accessed wirelessly via the UHF Gen2 RFID Protocol DCI Features e EPCglobal and ISO 18000 63 compliant Gen2V2 compliant 2176 bits of user NVM e 4 One Time Programmable OTP RFIP RFIN SCL blocks 1664 2160 bits via blockpermalock feature supported bv both I2C and EPC Gen2 interface 1 6kQ IpF Differential RF Input re e QT for read control and data privacy on RE link Port 1 17 dBm single n l port sensitivitv P p d Differential RF Input 19 5 dBm True3D write c Port 2 sensitivity e l7dBm typical read sensitivity when using a single RF antenna port 24dBm DC Input 1 6 3 6V with DC input I2C Clock Input VIH L 70 30 e 19 5dBm typical read sensitivity when DCI using dual RF antenna ports I2C Data Input IOL 6mA 04V e I2dBm typical write sensitivity when using a single RF antenna port I2C control of RF access Write wakeup mode Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc i Impinj Monza X 2K Dura Datasheet Table of Contents 2 10 2 11 2 12 2 13 3 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 4 1 4 2
13. X 2K Dura is only changed during a write transaction R W 0 During a read transaction Monza X 2K Dura ignores the A8 bit in the first byte and there is no following byte A master only writes a memory address and future read transactions use the previously written address A diagram of a transaction that writes the memory address is shown in Figure 3 All bit positions are explicitly shown so the boundary between the I2C device address and the Monza X 2K Dura memory address is clear Subsequent diagrams do not explicitly show these address bits Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc 5 Acknowledge Acknowledge I2C Device Address from slave from slave Y Y Y Sos 5i 53 02 Di 50 T vA TT A6 5 Ai Ab Ab Ai A A TP A A Start R W A Stop Memorv Address Bvte Aligned Figure 3 Addressing the device and setting the memorv address When performing an NVM write a master transmits data after the memory address Monza X 2K Dura s NVM is organized as 16 bit words Writes must align on word boundaries The NVM allows one or two word writes equivalent to two or four byte writes When executing a one word write Monza X 2K Dura ignores the LSB A0 of the memory address When executing a two word write Monza amp X 2K Dura ignores the two LSBs Al AO of the memory address If the write transaction is valid then Monza X 2K Dura begins the NVM write after receiving a stop from the I2C master Monza amp X 2K Du
14. assembly lead free soldering Assembly survival temp According to MO RNC IPC JEDEC s J STD Sensitivity Classification 20 Moisture Sensitivity Level Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc 16 Part Order IPJ P6001 Q2AT o Impinj 3 3 Reflow Temperature Profile t 1493 y 261 52 SAAR C Channel 1 lal a 300 vi B El 200 m 100 0 Sec 1 200 1300 1 400 1 500 1 600 1 700 3 4 Electrical Characteristics De ptio onditio 0 0 RF Performance 17 No DC Input dBm Matched RF Input With DC Lou Read Sensitivity Input at 0 C 24 dBm DRM M 4 DRTE l Using DC With DC nput Monza X 2K Dura can Input at 0 C 20 dBm beussd in to 25 C Battery 12 Assisted No DC Input dBm Passive mode to increase f read write Matched RF Input With DC range Swn Write Sensitivity Input at 0 C 24 dBm DRM M 4 to 85 C With DC Input at 0 C 20 dBm to 25 C Parallel Equivalent At Rp Real Input Impedance Sensitivity 1500 Ohms Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 17 Parameter Description Condition Min Max Units Comments Parallel Equivalent RF Input Capacitance Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc 18 Part Order IPJ P6001 Q2AT Parameter Description Condition Min Nom Max om Impinj Units Comments DCI Input Voltage I2C Reference These DCI
15. bit in 1 above This bit is also only accessible from I2C not RF This bit is set by factory default to 0 Thus by default there is RF access to RFI RF2 when DCI voltage is NOT present and no RF access when DCI voltage is present The specification VgroN determines the DCI voltage that inhibits RF 3 Setting the KILL bit 2 in byte 9 of the NVM will inhibit all RF access This bit can be set from RF using a Gen2 KILL command or by writing from I2C This is the normal mechanism for a reader to disable a chip This KILL bit takes precedence over both 1 and 2 above I2C can re write this bit back to O and thus reverse and RF KILL command The factory default for KILL is 0 The factories defaults are set so Monza X 2K Dura operates like any other RFID tag when DCI voltage is not present When DCI voltage is present the default behavior through mechanism 2 above is to inhibit all RF access The KILL bit is always set to O at the factory by Gen2 definition In conventional RFID chips once this bit is set to 1 a chip is dead and can never be resurrected Monza X 2K Dura having a hard wired D2C interface allows un doing the KILL operation from I2C 2 12 Gen2 I2C Arbitration If the DCI RF EN bit is set to one then Monza X 2K Dura has three different operating states as shown in Figure 10 The states are Internal Control I2C Control and Idle or RF Receive If the DCI RF EN bit is set to zero then Monza X 2K Dura will not respond
16. ck 1 USER Block 1 USER Block 1 USER Block 2 USER Block 0 Figure 9 BlockPermaLock blocks as seen from the I2C interface 30 MN 296 295 D e 233 232 231 x 1 Se Block 2 Yes Yes me 105 104 D s l 4 40 2 8 Monza X 2K Dura I2C Control of Config 1 0 Bits The CONFIG 1 0 bits contain important configuration that must be preserved Users must take care not to accidentally reprogram them when writing to bytes 8 and 9 The I2C master must read bytes 8 and 9 Then apply the values for CONFIG 1 0 to the new data that is written The following logic operation for the word to be sent over the I2C bus will achieve this SENT WORD OLD WORD amp 0x0003 NEW WORD amp OxFFFC 2 9 Monza X 2K Dura Control of the QT Function The QT SR and QT MEM bits control in byte 21 control the QT functionality of Monza X 2K Dura They have no effect on RC operation and only change RF Gen2 behavior The two bits operate independently from each other The QT SR bit turns on Monza X 2K Dura s short range mode when it is set When Monza X 2K Dura is in short range operations in OPEN or SECURED states are required to be close to the reader Note however that if the Monza X 2K Dura antenna has a gain 9dBi there will be no OPEN or SECURED access through the RF port when the QT SR bit is set The QT MEM bit controls how Monza X 2K Dura s memory appears to the
17. continue to the end of memory at which point Monza X 2K Dura will cease exchanging data over I2C Monza X 2K Dura will send all ones if the master continues to read beyond the end of the memory To read from a new location the master Copyright O 2013 Impinj Inc 6 e Part Order IPJ P6001 Q2AT Impinj must send a new address The master may halt the read at a byte boundary and later initiate a new read transaction starting from that byte For completeness the combined write transaction then read transaction is shown in Figure 6 Acknowledge Acknowledge Acknowledge Acknowledge Nack from slave from slave from slave from master from master Y Y Y Y SBC ADDR Top MEM ADDR TAJE 2C ADDR TAL DATA TAL DATA AP A Start R W Repeated Start R W Stop Auto increment byte address after each byte sent Figure 6 Write transaction to set address followed by repeated start and read transaction Monza X 2K Dura ignores all Gen2 Lock Kill permissions when reading writing over I2C The I2C port has read access to the entire NVM The I2C port has write access to most but not all of the NVM Monza amp X 2K Dura precludes a master from writing its manufacturing calibration fields shown as Reserved in the I2C memory map of Figure 7 these locations are read only 2 4 MBC Memory Map Gen 2 and I2C have different views on how a memory map is organized In I2C everything is done according to bytes One uses byte addressing byte wr
18. iting and byte reading In Gen2 things are done in terms of bits or 16 bit words Monza X 2K Dura is a hybrid of these two approaches It forces I2C to do one word or two word writes but allows for byte wise reading and addressing When reading via I2C the first bit read is always bit seven within the byte The next byte read is at the next higher I2C byte address The I2C memory map in byte wise format is shown in Figure 7 An additional memory map that shows bit addressing from I2C in a word wise format is shown in Figure 8 Copyright 2013 Impinj Inc 7 GEN2 12C BANK BIT ADDRESS in BYTE NAME ADDR To amp L 4 3 0 zZ 3 X TID SERIAL Byte 1 TID SERIAL Byte 0 ce x2 TID MODEL 7 0 201000000 TID DESIGNER 3 0 00012 TID MODEL 11 8 0001 TID DESIGNER 10 4 00000002 Gen2 mask designer is address 08 to 13 CLASS ID 7 0 11100010 QT EPC QT EPC QT EPC QT EPC TID SERIAL Byte 5 TID SERIAL Byte 4 TID SERIAL Byte 3 TID SERIAL Byte 2 USER USER USER USER USER e E u e EPC EPC EPC NSI 7 0 EPC LENGTH 4 0 X 0 JjNSI 8 PRFU 0 wwu IEPLENI ar SR arwEM po ReEN REDS 1 0 RFU WRITE as 00000000 BLOCK PERMALOCK 0 4 LOCK ACCESS 1 0 LOCK EPC 1 0 LOCK USER 1 0 ACCESS PASSWORD ACCESS PASSWORD ACCESS PASSWORD ACCESS PASSWORD KILL PASSWORD KILL PASSWORD KILL PASSWORD KILL PASSWORD 335 A EN 39 33
19. locks RF NVM Settable bit 3 7 DC Characteristics Parameter PC port Description Number of ports Condition Min Nom Max Units Option to allow the presence of DC to disable both RF ports Comments Slave DC SCL SDA I2C functionality Compatible with I2C bus specification and user manual Rev 03 19 June 2007 An external device can R W memory Supported I2C features Features Start condition Stop condition Acknowledge T bit slave address Slave Configuration mandatory mandatory mandatory mandatory DC write size Word size for I2C write Writes are on word addresses and not byte addresses DC read size Word size for I2C read May read data 8bits at a time where N is limited by start address and bank size I2C memory arbitration RF I2C port priority RF I2C arbitrate for NVM access I2C Address Monza X I2C Device Address 2K Dura Datasheet 110111M Copyright 2013 Impinj Inc 21 Parameter Description Condition Min om Max Units Comments rates rates Monza R X 2K Dura operates like most I2C EEPROM devices in that the LSB of the 7 bit I2C device address is the MSB of the NVM address The 8 LSBs of the NVM address are sent in the next I2C byte 3 8 NVM Usage Model Condition Writes per row Total writes Power on time A 5 yr l yr 2k hou
20. n When writing from the I2C block the cache for the PC length field is not properly updated after I2C writes The part must be power cycled to have the cache updated If QT features are changed from I2C then the changes don t take effect until power is cycled Specifically Monza X 2K Dura does not recache the RFS_MEM 1 Monza X 2K Dura is using the alternate EPC or RFS_SR 1 tag is in short range when written from I2C It needs to be power cycled for the change to take effect Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 25 6 Footprint Compatibility with Impinj amp Monza X 2K Dura Monza X 8K Dura Part Order IPJ P6005 X2AT is a higher memory capacity version of Monza X 2K Dura Monza X 8K Dura is designed to have 8192 bits of user NVM enabling more OTP blocks Its package dimensions are 2 0x2 0x0 35 mm It is designed to be a drop in replacement for Monza X 2K Dura if the layout footprint recommended below is used For more details about the Monza X 8K Dura including product availability please contact Impinj 8K 2K ki 7 M 0 40 a 0 12 0 15 3E JE 0 39 Du E zl rr oo co to a EE ERUNT 0 15 U 0 24 a ri PIN 1 1 D _ C 0 15x45deg peliin Chip outline NN All dimesions in mm Figure 13 Recommended common layout footprint for Monza X 2K Dura and Monza X 8K Dura Copyright O 2013 Impinj Inc 26 Part Order IPJ P60
21. ock write commands of zero words Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc ye __ Part Order IPJ P6001 Q2AT Impinj Command Code Length Details BlockPermalock 11001001 266 Five blocks Four 512 bits in size One 128 bits in size Command can be disabled through I2C 2 3 DC Interface SDA SCL DCI Pins I2C is a standard two wire interface clock and data that supports multiple addressable chips on a bus Monza X 2K Dura only supports slave capability Monza X 2K Dura s I2C features are compatible with the industry standard I2C bus Specifically Monza X 2K Dura is compatible with I2C specification I2C Rev 0 03 June 19 2007 NXP Doc UM10204 Monza X 2K Dura implements the following I2C capabilities I2C slave I2C Start Condition I2C Repeated Start Condition I2C Stop Condition I2C Acknowledge I2C 7 bit slave address 110111M Fast mode transfer rates of 0 400kbits second The DCI voltage provides I2C bus VOH VOL reference and power When an I2C master addresses Monza X 2K Dura it must format its write transactions as described here In addition to the I2C device address Monza X 2K Dura has a memory address that a master writes on every write transaction This 9 bit memory address specifies which memory byte the master is addressing The MSB of the memory address replaces the LSB of the I2C device address bit M in the device ID The memory address stored in Monza
22. ra will not respond to subsequent I2C transactions for the duration of the NVM write operation The write time for one and two word write operations is the same A one word NVM write transaction is shown in Figure 4 Monza X 2K Dura may observe several types of invalid NVM write transactions If a master sends one or three data bytes then Monza amp X 2K Dura will not perform the write recall that Monza X 2K Dura writes 16 bit words If a master sends more than two words then Monza X 2K Dura will not perform the write Monza X 2K Dura also checks the memory address and will not perform a write if the address is invalid but note that Monza X 2K Dura updates its memory address even if the address is invalid Acknowledge Acknowledge Acknowledge Acknowledge from slave from slave from slave from slave Y Y Y Y I2C ADDR JOJA MEM ADDR DATA DATA ATP A E 4 Start R W Stop Figure 4 One word Monza X 2K Dura write transaction Figure 5 shows a read transaction The read starts from the stored address Monza X 2K Dura increments the address as it sends each data byte Monza X 2K Dura ignores the MSB of the memory address when the R W 1 Acknowledge Acknowledge Acknowledge Nack from slave from master from master from master v Y Y Y S E ADDR T DATA TA DATA TA DATA JAP A pA A Start R W Auto increment byte address after each byte sent Stop Figure 5 Monza X 2K Dura read transaction Reads start from the stored address and
23. rs 3 9 Environmental Compliance Requirement Comments RoHS Monza X 2K Dura is RoHS compliant It meets the directive 2002 95 EC RoHS RoHS declaration letter is available upon request REACH Monza X 2K Dura does not to our current knowledge contain substances above the legal threshold that are on the Candidate List of Substances of Very High Concern SVHC Our company s intention is that all products sold to our EU and EEA customers by our legal entities in Europe are compliant with REACH regulatory requirements REACH declaration letter is available upon request Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 22 Part Order IPJ P6001 Q2AT Impinj 4 Product Delivery Specifications 4 1 Marking Specification Pin 1 dot Y Year of production 1 2011 2 2012 WW z Work Week of production X2 Product Code Monza X 2K Dura Copyright 2013 Impinj Inc 23 4 2 Tape and Reel Specification 4 00 0 10 1 50 10 pore 0 10 4 00 0 10 ri 8 00 4 30 3 50 05 10 1 0 0 25 NS 204 ui p 32 MAX ka ii 32 MAX 1 75 0 05 0 55 0 05 K 5 Parts per reel Minimum order quantity 3000 Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 24 Part Order IPJ P6001 Q2AT Impinj 5 Errata The following table lists the known issues in Monza X 2K Dura Issue Number Descriptio
24. ry or death or property or environmental damage hazardous uses or for use in automotive environments Customers must indemnify Impinj against any damages arising out of the use of Impinj products in any hazardous or automotive uses Impinj Monza QT and True3D are trademarks of Impinj Inc All other product or service names are trademarks of their respective companies The Powered by Impinj shield is your assurance of RFID integrity Copyright O 2013 Impinj Inc 28
25. t Order IPJ P6001 Q2AT Impinj 2 Functional Description Monza X 2K Dura chips enable users to communicate wirelessly with the processor inside electronic devices using standard Gen 2 RFID readers unlocking many new benefits for consumer electronics manufacturers retailers and end users Monza X 2K Dura connects to the processor of an electronic device through a standard I2C bus This enables the processor to read and write the Monza X chip memory with information that is accessible to UHF Gen 2 RFID readers even when the electronic device is powered off By enabling electronic devices to communicate with RFID readers Monza X chips deliver a wide range of extended capabilities such as theft deterrence in the supply chain and device configuration upgrades at point of sale and beyond LOOP DIPOLE 2C BUS RFI_P RF2_P RFILN RF2_N MONZA 2X DCI GND Figure 1 Monza X 2K Dura connects with microprocessor through I2C bus 2 1 Reader Communications Gen2 RF Commands A reader communicates with Monza X 2K Dura using standard Gen2 RFID commands Please see the EPCglobal Class 1 Generation 2 UHF RFID Air Interface Protocol V 1 2 0 for details The Gen 2 memory map is shown in Figure 2 Fields in blue text are read only Reserved memory bank words 4 10 are read only Monza X 2K Dura Datasheet Copyright 2013 Impinj Inc 3 8701 87Fn USER 15 0 8601 86F1 USER 31 16 10 1F USER 2159 2144 00 0F USER
26. to RF commands when in the dle or RF Receive state Internal Control Monza amp X 2K Dura is in Internal Control when 1 executing an initialization sequence 2 writing the NVM or 3 backscattering a response to an RF command When in Internal Control Monza X 2K Dura ignores I2C transactions or RF commands PC Control Monza amp X 2K Dura is in 2C Control when a master is issuing commands to Monza X 2K Dura over the I2C bus I2C Control starts when Monza X 2K Dura detects a matching device ID and is not under nternal Control The I2C bus master releases control of Monza X 2K Dura either by ending a transaction with a stop bit or by issuing a subsequent start with a non matching device ID If Monza X 2K Dura was commanded to perform an NVM write then it moves to nternal Control otherwise it returns to idle When in 2C Control Monza X 2K Dura ignores all RF commands Note that the master may stall the I2C bus by holding SCL low in the middle of a transaction and prevent RF access until releasing the bus Idle or RF Receive Monza X 2K Dura is in Idle or RF Receive when receiving an RF command or when idle After receiving a command Monza X 2K Dura transitions to Internal Copyright O 2013 Impinj Inc 12 R Part Order IPJ P6001 Q2AT Impinj Control to execute the command Executing a command may cause Monza X 2K Dura to 1 backscatter a reply 2 write to NVM or 3 change internal states An I2C transaction may
27. ues of 5K or more are typical in low power applications 3 5 Memory Characteristics Parameter EPC memory Description EPC NVM Condition In private mode only Min Nom Max Units Comments User writeable This memorv is hidden over RF when QT is enabled User memorv Total user NVM In private mode only User defined memorv space This memorv is hidden over RF when QT is enabled QT alternative EPC Alternative EPC presented during RF singulation In public mode only A user can switch the tag s RF QUERY ACK response from EPC to alternative EPC using the QT command Kill Access Passwords Password NVM Access required Standard 32 bit Gen2 access and kill passwords TID mfg serial TID ROM In private mode only TID serial number is hidden over RF when QT is enabled Total Memory Monza Total memory size Memory write time 16 or 32 bits X 2K Dura Datasheet Copyright O 2013 Impinj Inc 20 Part Order IPJ P6001 Q2AT 3 6 RF Functionality Parameter Air protocol Description Gen2 V1 2 0 Condition Min Nom Max Units Impinj Comments No recommissioning no blockerase RF ports Number of RF ports Dual differential RF ports RF Port Disable NVM Settable bit per port The operation of one or both RF ports may be disabled by setting NVM bits through the I2Cport DC B
28. voltages are with a 100mV tolerance Current drawn by chip during write 1 6 lt Vpci lt 2 0 2 0 lt Vpci lt 3 6 Nominal 80uA at 1 6V Current drawn bv chip during read or idle 1 6 lt Vpci lt 2 0 2 0 lt Vpci lt 3 6 Power Up Time Time from Vpci applied until I2C accepts transactions NOTE DC will not interrupt a write operation This could delay I2C access up to 20ms if RF is writing Max Vdd for which RF will always be enabled Applies if the DCI RF EN bit Min Vdd for which RF will always be disabled is set to 0 I2C Vin E All 70 V pci Vu LOW level input All 30 From the voltage V pci section 6 of the I2Cspecification 0 1 Vuys Input hysteresis All V Monza X 2K Dura Datasheet Copyright O 2013 Impinj Inc 19 Parameter Description LOW level output current Condition VoL 0 4 Units Comments Output Fall Time Bus C 40 400pf Pin Capacitance Total capacitive load on the SDA SCL pins SCL SDA Input Leakage Current Vin 3 7V 0V Vpcerc 7V Exceeds I2C spec of 10uA or is tested with worst case minimum pull up resistance value of 536 ohms at 2v Applications should use as high pull up resistance as possible consistent with the bus capacitance for the application See the I2C specification for choosing pull up resistor values Val
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