ISL45041 Datasheet
Contents
1. m0 D LaS SIDE VIEW 0 2 REF iG oO Cc I L 02 NOM 05 MAX fo 0 DETAIL X NOTES 1 Dop gt gt Dimensions are in millimeters Dimensions in for Reference Only Dimensioning and tolerancing conform to ASME Y14 5m 1994 Unless otherwise specified tolerance Decimal 0 05 Dimension applies to the metallized terminal and is measured between 0 15mm and 0 20mm from the terminal tip Tiebar shown if present is a non functional feature The configuration of the pin 1 identifier is optional but must be located within the zone indicated The pin 1 identifier may be either a mold or mark feature Compliant to JEDEC MO 229 WEEC 2 except for the foot length Submit Document Feedback 8 intersil FN6189 5 October 30 20142. interii DATASHEET TFT LCD I7C Programmable VCOM Calibrator ISL45041 The Vcom voltage of an LCD panel needs to be adjusted to remove flicker This part provides a digital interface to control the sink current output that attaches to an external voltage divider The increase in output sink current lowers the voltage on the external divider which is applied to an external Vcom buffer amplifier The desired Veg setting is loaded from an external source via a standard 2 wire I2C serial interface At power up the part automatically comes up at the last programmed EEPROM setting An external resistor attaches to the SET pin and sets the full scale sink current that determines the lowest voltage of the external voltage divider The ISL45047 is available in an 8 Ld 3mmx3mm TDFN package with a maximum thickness of 0 8mm for ultra thin LCD panel design An evaluation kit complete with software to control the DCP from a computer is available Reference Application Note AN1275 and Ordering Information on page 2 1 C INTERFACE DAC REGISTERS 1SL45041 Features e 128 step adjustable sink current output e 2 25V to 3 6V logic supply voltage operating range 2 6V minimum programming voltage 4 5V to 18V analog supply voltage operating range 10 8V minimum programming voltage 12C interface with addresses 100111x and 100110x On chip 7 Bit EEPROM Output adjustment SET pin e Output guaranteed monotoni
3. 1 Moved Block Diagram to page 1 Moved the Pin Configurations and Ordering Information to page 2 Added Pad to Pin Descriptions on page 2 In Table 1 on page 5 updated typo in first row VOUT value from 5 486 to 5 468 and added V units to header Added revision history and About Intersil sections About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions The company s products address some of the largest markets within the industrial and infrastructure mobile computing and high end consumer markets For the most updated datasheet application notes related documentation and related parts please see the respective product information page found at www intersil com You may report errors or suggestions for improving this datasheet by visiting www intersil com ask Reliability reports are also available from our website at www intersil com support For additional products see www intersil com en products htm Intersil products are manufactured assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www intersil com en support qualandreliability html Intersil products are sold by description only Intersil Corporation reserves the right to make changes in circuit design software and or specifications at any time without notice Accordingly the reader is cautioned to verify
4. is designed for static control It has an internal pull down current sink To avoid the possibly overwriting the EEPROM contents no frequency above 1Hz should be applied to this input Care should be taken to avoid any glitches on the input When removing or applying mechanical jumpers always ensure the Vpp power is off A high to low transition on the WP pin results in the register contents being loaded with EEPROM data 4 GND Supply Ground connection 5 VDD Supply Digital power supply input Bypass to GND with 0 1yF capacitor 6 SDA In Out 12C Serial Data Input and Output 7 SCL Input 12C Clock Input 8 SET Analog Maximum Sink Current Adjustment Point Connect a resistor from SET to GND to set the maximum adjustable sink current of the OUT pin The maximum adjustable sink current is equal to AVpp 20 divided by RSET Pad Power Thermal pad Electrically connected to GND Connect to ground plane on PCB to maximize thermal performance Ordering Information PART NUMBER PART RANGE PACKAGE PKG Notes 4 2 3 MARKING C Pb Free DWG ISL450411RZ 041Z O to 85 8 Ld 3x3 TDFN L8 3x3A ISL45041EVAL1Z Evaluation Board NOTES 1 Add T suffix for tape and reel Please refer to TB347 for details on reel specifications 2 These Intersil Pb free plastic packaged products employ special Pb free material sets molding compounds die attach materials and 100 matte tin plate plus anneal e3 termination finis
5. 09 90 3 936 Do not remove VDD or AVDD within 100ms of the start of the 100 3 764 EEPROM programming cycle Removing power before the EEPROM programming cycle is completed may result in 110 3 592 corrupted data in the EEPROM 128 3 282 Submit Document Feedback 5 intersil FN6189 5 October 30 2014 YTOZ OE 4990190 yoeqneey JuauIno0g Wugns Sasa Qu SG 68TONJ I7c Bus Format ISL45041 I C WRITE FORMAT 6 BIT ADDRESS ISL45041 C READ FORMAT d _ _ BYTE gt 6 BIT ADDRESS lt BYTE 1 H BYTE2 ACK DATA PROGRAM R W 0 WRITE R W 1 READ WHEN R W 0 P 0 EEPROM PROGRAMMING P 1 REGISTER WRITE Jt BYE _ MSB 7c Addressing LSB MSB LSB R W 0 WRITE R W 1 READ FIGURE 4 ISL45041 12C READ AND WRITE FORMAT The ISL45044 will respond identically to either of two I2C address 1001110x and 1001111x 100111x is the preferred address To prevent bus conflicts ensure that there are no other devices on the IC bus with either of the above addresses TrvOSsrisi ISL45041 Revision History The revision history provided is for informational purposes only and is believed to be accurate but not warranted Please go to the web to make sure that you have the latest revision DATE REVISION CHANGE October 30 2014 FN6189 5 Updated datasheet to Intersil s new standards Added related Literature on page
6. 17 Data Hold Time tspH 900 ns 12c SDA SCL Input Rise Time tICR Dependent on Load Note 10 20 0 1 Cb 1000 ns 1c SDA SCL Input Fall Time tick Note 10 20 0 1 Cb 300 ns 12C Bus Free Time Between Stop and Start tBUF 200 us 12C Repeated Start Condition Set up tsTs 0 6 us 12C Repeated Start Condition Hold tsTH 0 6 us 12C Stop Condition Set up tsps 0 6 us 12C Bus Capacitive Load Cb 400 pF SDA Pin Capacitance Cspa 10 pF SCL Pin Capacitance Cs 10 pF EEPROM Write Cycle Time tw 100 ms NOTES 6 Compliance to datasheet limits is assured by one or more methods production test characterization and or design 7 Ipp current may increase to 2mA for 45ms or less during each EEPROM programming operation 8 lavpp current may increase to 1mA for 30ms or less during each EEPROM programming operation 9 Simulated and Determined via Design and NOT Directly Tested 10 Simulated and Designed According to 12c Specifications 11 A typical Current of 20pA is Calculated using AVpp 10V and Rsgr 24 9KQ Reference Rsgr Resistor in Figure 3 12 Minimum value of Rsgr resistor guaranteed when AVpp 15V Vpp 3 0V and when voltage on the VOUT pin is greater than 2 5V Reference Equation 2 on page 5 with Setting 128 Submit Document Feedback 4 intersil FN6189 5 October 30 2014 ISL45041 Application Information This device provides the ability to reduce the flicker of an LCD panel by adjustment of the Vcom voltage during production test
7. and alignment A 128 step resolution is provided under digital control which adjusts the sink current of the output The output is connected to an external voltage divider so that the device will have the capability to reduce the voltage on the output by increasing the output sink current AVDD 9 AVDD ISL45041 SET FIGURE 2 OUTPUT CONNECTION CIRCUIT EXAMPLE The adjustment of the output is provided by the 2 wire 12C serial interface Expected Output Voltage The ISL45041 provides an output sink current which lowers the voltage on the external voltage divider Vcomp output voltage Equations 1 and 2 can be used to calculate the output current lout and output voltage Vout values The setting is the register value 1 with a value between 1 and 128 _ Setting AVpp lout 428 B0 Age aa R R 2 _ Setting 1 Vout r A o 128 Pee EQ 2 Table 1 gives the calculated value of Voyrz using the resistor values of Rget 24 9kQ R1 200kQ Ro 243k and AVpp 10V Rser Resistor The external Refz resistor sets the full scale sink current Isgr maximum that determines the lowest voltage of the external voltage divider R4 and Ro Figure 2 The voltage difference between the OUT pin and SET pin Figure 3 which are also the drain and source of the output transistor must be greater than 1 75V This will keep the output transistor in its saturation region to ma
8. c over temperature Thin 8 Ld 3mmx3mm DFN 0 8mm max Pb free ROHS compliant Applications e LCD panels Related Literature e AN1208 LCD screens don t flicker or do they AN1244 ISL45041 and ISL29001 Flicker Control User s Manual e AN1275 ISL45041EVAL1Z User s Manual ANALOG DCP AND CURRENT SINK ouT GND FIGURE 1 BLOCK DIAGRAM October 30 2014 1 CAUTION These devices are sensitive to electrostatic discharge follow proper IC Handling Procedures FN6189 5 1 888 INTERSIL or 1 888 468 3774 Copyright Intersil Americas LLC 2005 2007 2010 2014 All Rights Reserved Intersil and design is a trademark owned by Intersil Corporation or one of its subsidiaries All other trademarks mentioned are the property of their respective owners ISL45041 Pin Configuration Pin Descriptions ISL45041 8 LD TDFN TOP VIEW OUT SET AVDD SCL WP SDA GND VDD PIN PIN NUMBER NAME TYPE PULL U D FUNCTION 1 OUT Output Adjustable Sink Current Output Pin The current that sinks into the OUT pin is equal to the DAC setting times the maximum adjustable sink current divided by 128 See SET pin function description for the maximum adjustable sink current setting 2 AVDD Supply High Voltage Analog Supply Bypass to GND with 0 1yF capacitor 3 WP Input Pull Down Write Protect Active Low To enable programming connect to 0 7 Vpp supply or greater The WP pin
9. h which is ROHS compliant and compatible with both SnPb and Pb free soldering operations Intersil Pb free products are MSL classified at Pb free peak reflow temperatures that meet or exceed the Pb free requirements of IPC JEDEC J STD 020 3 For Moisture Sensitivity Level MSL please see device information page for ISL45041 For more information on MSL please see Technical Brief TB363 Submit Document Feedback 2 intersil FN6189 5 October 30 2014 ISL45041 Absolute Maximum Ratings VDD t GND ive sities ieee e beta hehe resto ae le Input Voltages to GND ESD Rating Human Body Model Device Tested per JESD22 A114E Input Pins SCL SDA Tested per JESD22 A114E Operating Conditions Temperature Range 0 0 c cece eee eee 0 3V to 4V 0 3V to 20V 0 3V to Aypp 0 C to 85 C Thermal Information Thermal Resistance Typical Oja C W Oje C W 8 Ld TDFN Package Notes 4 5 53 11 Moisture Sensitivity see Technical Brief TB363 All Packages a eci serie seis cananan a er deca 6 s Wal alee ade ea ne Level 2 Maximum Junction Temperature Plastic Package 150 C Maximum Storage Temperature Range 65 C to 150 C Pb free reflow profile 0 00 c cece eee eee eee see TB493 CAUTION Do not operate at or near the maximum ratings listed for extended periods of time Exposure to such conditions may adversely impact p
10. intain linear operation over the full range of register values Expected current settings and 7 bit accuracy occurs when the output MOS transistor is operating in the saturation region Figure 3 shows the internal connection for the output MOS transistor The value of the AVpp supply sets the voltage at the source of the output transistor This voltage is equal to Setting 128 x AVpp 20 The Isgr current is therefore equal to Setting 128 x AVpp 20 x Rser The drain voltage is calculated using Equation 2 The values of R4 and Ro Equation 2 should be determined using loyr maximum setting equal to 128 so the minimum value of Voyt is greater than 1 75V AVpp 20 AVpp 15V T PIN DD SETTING 4Ypp ou 128 20 N Ry AVDD R2 SET PIN FIGURE 3 OUTPUT CONNECTION CIRCUIT EXAMPLE Ramp Up of the VDD Power Supply The ramp up from 10 Vpp to 90 Vpp level must be achieved in 10ms or less to ensure that the EEPROM and power on reset circuits are synchronized and the correct value is read from the EEPROM Memory Power Supply Sequence TABLE 1 The recommended power supply sequencing is shown in Vout Figure 3 When applying power VDD should be applied before or SETTING VALUE v at the same time as AVDD The minimum time for tys is Ops 1 5 468 When removing power the sequence of VDD and AVDD is not 10 5 313 important 20 5 141 30 4 969 40 4 797 50 4 625 60 4 453 t ts 70 4 281 FIGURE 3 POWER SUPPLY SEQUENCE 80 4 1
11. pp 10V ISET Through Reet Note 11 20 yA SET External Resistance SETeR To GND AVpp 18V 5 200 kQ To GND AVpp 4 5V 2 25 45 kQ To GND AVpp 15V Vpp 3V 1 0 200 kQ Vour gt 2 5V Note 12 AVpp to SET Voltage Attenuation AVDD to Note 9 1 20 V V SET OUT Settling Time OUTsr To 0 5 LSB Error Band 8 us Note 9 OUT Voltage Range VouT Vset 0 5V 13 V SET Voltage Drift SETyp 25 C lt T lt 55 C Note 9 lt 10 mV Submit Document Feedback 3 intersil FN6189 5 October 30 2014 ISL45041 Electrical Specifications test Conditions Vpp 3 3V AVpp 18V Rser 5KO R1 10KO R2 10kQ See Figure 2 Unless otherwise specified Typicals are at Ty 25 C Boldface limits apply across the operating temperature range 0 C to 85 C Continued PARAMETER SYMBOL TEST CONDITIONS pers TYP iat UNITS SDA SCL Input Logic High 1 CViH 0 7 Vpp vV SDA SCL Input Logic Low 12CViL 0 55 V SDA SCL Hysteresis Note 9 260 mV SDA Output Logic High VOHs Vpp 0 4 V SDA Output Logic Low VOLs at 3mA 0 4 Vv WP Input Logic High Vin 0 7 Vpp v WP Input Logic Low ViL 0 3 Vpp V WP hysteresis Note 9 0 14Vpp v WP Input Current ILWPN 0 20 35 HA 12C Timing SCL Clock Frequency fscL 0 400 kHz 12C Clock High Time tscH 0 6 us 12C Clock Low Time tscL 1 3 us 17C Spike Rejection Filter Pulse Width tpsp 0 50 ns 1 C Data Set Up Time tsps 100 ns
12. roduct reliability and result in failures not covered by warranty NOTES 4 Oja is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features See Tech Brief TB379 5 For jc the case temp location is the center of the exposed metal pad on the package underside Electrical Specifications test Conditions Vpp 3 3V AVpp 18V Rser 5KO R1 10KO R2 10kQ See Figure 2 Unless otherwise specified Typicals are at Ty 25 C Boldface limits apply across the operating temperature range 0 C to 85 C PARAMETER SYMBOL TEST CONDITIONS pina TYP pent UNITS POWER SUPPLY CHARACTERISTICS Vpp Supply Range Supporting EEPROM Programming VDD 2 6 3 6 V AVpp Supply Range Supporting EEPROM Programming AVpp 10 8 18 Vv Vpp Supply Range for Wide supply Operation VDD 2 25 3 6 V not supporting EEPROM programming AVpp Supply Range for Wide supply Operation AVpp 2 6V lt Vpp lt 3 6V 4 5 18 Vv not supporting EEPROM programming 2 25V lt Vpp lt 2 6V 45 13 v Vpp Supply Current Ipp Note 7 65 HA AVpp Supply Current lavpp Note 8 38 pA DC CHARACTERISTICS SET Voltage Resolution SETyr 7 7 7 Bits SET Differential Nonlinearity SETpn Monotonic Over temperature 1 LSB SET Zero scale Error SETZsE 3 LSB SET Full scale Error SETFse 8 LSB SET Current Rser 24 9kQ and AV
13. that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidiaries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see www intersil com Submit Document Feedback 7 intersil FN6189 5 October 30 2014 ISL45041 Package Outline Drawing L8 3x3A 8 LEAD THIN DUAL FLAT NO LEAD PLASTIC PACKAGE Rey 4 2 10 ac A PIN 1 INDEX AREA 3 00 4X a 0 15 1 TOP VIEW 2X 1 950 PIN 1 1 INDEX AREA DW A a 6X 0 65 8X 0 30 0 10 1 50 0 10 8X 0 30 0 05 A 0 100 Cc A m 2 30 0 10 BOTTOM VIEW m 2 30 gt m 1 95 2 90 l B 8X 0 50 1 50 PIN 1 6x 0 65 41 8 X 0 30 TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL X 0 75 0 05 fees 0 10 C
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