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NXP P89LPC915, P89LPC916, P89LPC917 User`s Manual

1. 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 10 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table 4 P89LPC917 pin description Symbol Pin Type Description P1 0toP1 5 3 6 7 8 I O Port 1 Port 1 is a 6 bit I O port with user configurable outputs During reset Port 1 9 10 P1 0 4 latches are configured in the input only mode with the internal pull up disabled The I P1 5 operation of the outputs depends upon the port configuration selected Refer to Section 5 1 for details P1 2 and P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 10 0 P1 0 Port 1 bit 0 O TxD Serial port transmitter data 9 1 0 P1 1 Port 1 bit 1 RxD Serial port receiver data 8 O P1 2 Port 1 bit 2 Open drain when used as an output O TO Timer counter 0 external count input overflow or PWM output o SCL I C serial clock input output 7 o P1 3 Port 1 bit 3 Open drain when used as an output 0 INTO External interrupt 0 input O SDA I C serial data input output 6 0 P1 4 Port 1 bit 4 1 O INT1 External interrupt 1input 3 P1 5 Port 1 bit 5 Input only R
2. Symbol Pin Type Description P1 0 to P1 3 3 7 8 9 I O Port 1 Port 1 is a 5 bit I O port with user configurable outputs During reset Port 1 P1 5 10 P1 2 latches are configured in the input only mode with the internal pull up disabled The I P1 5 operation of the P1 2 input and outputs depends upon the port configuration selected Refer to Section 5 1 for details P1 2 is an open drain when used as an output P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 10 1 O P1 0 Port 1 bit 0 O TxD Serial port transmitter data 9 1 O P1 1 Port 1 bit 0 RxD Serial port receiver data 8 O P1 2 Port 1 bit 2 Open drain when used as an output O TO Timer counter 0 external count input overflow output or PWM output O SCL I C serial clock input output 7 V O P1 3 Port 1 bit 2 Open drain when used as an output 0 INTO External interrupt 0 input O SDA IC serial data input output 3 P1 5 Port 1 bit 5 Input only RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force In System Programming mode P2 2toP2 5 2 5 6 11 I O P
3. E P89LPC915 916 917 User manual pok _____ 77 overflow Tn bi or 1 TFn gt interrupt p C T 1 control 8 bits toggle TRn Gate INTn pin ENTn 002aaag21 Fig 21 Timer counter 0 or 1 in Mode 2 8 bit auto reload PCLK kkn T overflow n TFO interrupt TO pin O CA i control 8 bits toggle TRO or O To pin Gate P1 2 open drain INTO pin ENTO AUXR1 4 overflow Osc 2 on THO TF1 interrupt control 8 bits toggle TRI oT O T1 pin P0 7 ENT1 AUXR1 5 002aaa922 Fig 22 Timer counter 0 Mode 3 two 8 bit counters Get tin overflow PCLK om n TFn interrupt control 8 bits reload THn on falling transition and 25 oe on rising transition toggle TRn or L Tn pin Gate THn INTn pin 8 bits ENTn 002aaag23 Fig 23 Timer counter 0 or 1 in Mode 6 PWM auto reload 8 6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 57 of 125 Philips Semiconductors U M1 01 07 L P89LPC915 916 917 User manual control bits ENTO and ENT1 in the AUXR1 register and apply to Timer 0 and Timer
4. 108 Periodic wake up from power down without an external oscillator 108 Additional features 108 Software reset nnen 109 Dual Data Pointers 109 Flash memory 00sec eee eee 110 General description 110 Features ene 110 Flash programming and erase 110 Using Flash as data storage IAP Lite 110 In circuit programming ICP a an 114 Power on reset code execution 114 Flash write enable 115 Configuration byte protection 115 User configuration bytes 115 User security bytes 116 Boot Vector register 117 Boot status register 118 Instruction set ennen 119 Disclaimers 123 P89LPC915 916 917 User manual 20 LICCNSCS ii iid waaar ieee wee maden 123 Koninklijke Philips Electronics N V 2004 All rights are reserved Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner The information presented in this document does not form part of any quotation or contract is believed to be accurate and reliable and may be changed without notice No liability will be accepted by the publisher for any consequence of its use Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights Date of release 15 July 2004 Document order number 9397 750 13316 Published in the U S
5. SS if SSIG bit 0 l l _ _ 002aaa937 1 Not defined Fig 44 SPI master transfer format with CPHA 1 12 8 SPI clock prescaler select The SPI clock prescaler selection uses the SPR1 SPRO bits in the SPCTL register see Table 74 13 Analog comparators Two analog comparators are provided on the P89LPC915 916 917 Input and output options allow use of the comparators in different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes 13 1 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 and are shown in Table 80 Please note that the OE1 bit in CMP1 does not exist on the P89LPC915 916 917 devices and that the OE2 bit in CMP2 does not exist on the P89LPC916 device 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 97 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual The overall connections to both comparators are shown in Figure 45 There are eight possible configurations for compara
6. 59 Changing RTCS1 RTCSO 59 Real time clock interrupt wake up 59 Reset sources affecting the Real time clock 59 UART unranked ek Seles erences 60 Mode Os zaan one i oaren aeta ae 61 MOAB 1e arorarr annet erneer warden bande a Arde 61 Mode 2 sis oeren ner Ti ede eee ware dee 61 Mode Bierna eine hs neten es 61 SFR SPACE i ppi da rn ee ae et 61 Baud Rate generator and selection 62 Updating the BRGR1 and BRGRO SFRs 62 Framing error 63 Break detect 63 More about UART Mode 0 65 More about UART Mode 1 65 More about UART Modes 2 and3 66 Framing error and RI in Modes 2 and 3 with SM2 1 ears a eke an ed ee de 66 Break detect 67 Double buffering 67 Double buffering in different modes 67 Transmit interrupts with double buffering enabled Modes 1 2 and3 005 67 The 9th bit bit 8 in double buffering Modes 1 2 QNG 3 ar a nd eden oop eee a Kd 68 Multiprocessor communications 69 Automatic address recognition 70 PC Interface wise aanne See cae wee 71 I2 C Data register nanana nunun 72 2C Slave Address register 72 2C Control register noona nnnaaan 73 2C Status register 74 continued gt gt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 124 of 125 Philips Semiconductors UM101
7. CLKIN gt KBI5 gt CMPREF gt CLKOUT lt KBI7 gt Ti gt Fig 3 P89LPC917 logic symbol PORT 0 Voo Vss O O 1 gt TxD hd RxD 4 gt TO gt SCL 4 kb e gt P89LPC917 E NTO SDA gt 4 RST i lt gt PORT 2 002aaa830 1 2 Product comparison Table 1 highlights the differences between these devices For a complete list of device features please refer to the P89LPC915 916 917 data sheet Table 1 Product comparison Type Comp 2 SPI T1 PWM CLKOUT INT1 number output output P89LPC915 X X P89LPCI16 X P89LPC917 X x X 1 3 Pin Configuration CIN2B KBI1 AD10 P0 1 O P0 2 CIN2A KBI2 AD11 KBIO CMP2 P0 0 P0 3 CIN1B KBI3 AD12 RST P1 5 P0 4 CIN1A KBI4 AD13 DAC1 Vss LPC915 P0 5 CMPREF KBI5 CLKIN INT1 P1 4 Voo SDA INTO P1 3 P1 0 TXD SCL TO P1 2 P1 1 RXD 002aaa825 Fig 4 P89LPC915 TSSOP14 pin configuration 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 4 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Fig 5 CIN2B KBI1 AD10 P0 1 O 55 P2 4 RST P1 5 Vss LPC916 MISO P2 3 MOSI P2 2 SDA INTO P1 3 SCL TO P1 2 002aaa826 P89LPC916 TSSOP16 pin configuration P0 2 CIN2A KBI2 AD1 1 P0 3 CIN1B KB13 AD12 P0 4 CIN1A KBI4 AD13 DAC1 P0O 5 CMPREF KBI5 CLKIN VDD P2 5 S
8. P0 2 Port 0 bit 2 CIN2A Comparator 2 positive input A KBI2 Keyboard input 2 AD11 A D channel 1 input 1 P0 3 Port 0 bit 3 CIN1B Comparator 1 positive input B KBI3 Keyboard input 3 AD12 A D channel 1 input 2 P0 4 Port 0 bit 4 CIN1A Comparator 1 positive input A KBI4 Keyboard input 4 AD13 A D channel 1 input 3 DAC1 Digital to analog converter 1 output P0 5 Port 0 bit 5 CMPREF Comparator reference negative input KBI5 Keyboard input 5 CLKIN External clock input Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 6 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table2 P89LPC915 pin description Symbol Pin Type Description P1 0toP1 5 3 5 6 7 I O Port 1 Port 1 is a 6 bit I O port with user configurable outputs During reset Port 1 8 9 P1 2 latches are configured in the input only mode with the internal pull up disabled The I P1 5 operation of the inputs and outputs depends upon the port configuration selected Refer to Section 5 1 for details P1 2 is an open drain when used as an output P1 5 is input only All pins have Schmitt triggered inputs Port 1 also provides various special functions as described below 9
9. get pointer into RO write data to page register point to next byte do until count is zero else erase amp program the page copy status for return read status save only four lower bits clear error flag if good sand return set error flag sand return A C language routine to load the page register and perform an erase program operation is shown below include lt REG915 H gt unsigned char idata dbytes 16 data buffer unsigned char Fm stat status result bit PGM USER unsigned char unsigned char bit prog fail void main prog fail PGM USER 0x07 0xC0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 113 of 125 Philips Semiconductors U M1 01 07 175 17 6 P89LPC915 916 917 User manual bit PGM USER unsigned char page hi unsigned char page lo define LOAD0x00 clear page register enable loading define EP0x68 erase amp program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page hi FMADRL page lo write my page address to addr regs for i 0 1 lt 64 i i 1 FMDATA dbytes i FMCON EP erase amp prog page command Fm stat FMCON read the result status if Fm stat amp 0x0F 0 prog fail 1 else prog fail 0 return prog fail In circuit programming ICP In Circuit Programming is a method intended to allow commercial
10. lt gt PORT 1 CONFIGURABLE I Os PORT 0 CONFIGURABLE I Os KEYPAD INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER T CPU CLOCK external clock input ON CHIP RC OSCILLATOR CLKOUT lt LS L_ c EN Fe 2 S a ADC1 DAC1 _ gt REAL TIME CLOCK SYSTEM TIMER TIMER 0 gt TIMER 1 ANALOG COMPARATORS POWER MONITOR POWER ON RESET BROWNOUT RESET Fig 9 P89LPC917 block diagram 002aaa824 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 14 of 125 Philips Semiconductors U M1 01 07 E P89LPC915 916 917 User manual 1 4 Special function registers Remark Special Function Registers SFRs accesses are restricted in the following ways e User must not attempt to access any SFR locations not defined e Accesses to any defined SFR locations must be strictly for the functions for the SFRs e SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 0 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read
11. 111 Reserved User must not configure to this mode 5 7 reserved Mode 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 19 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either TnGATE 0 or INTn 1 Setting TNGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Table 43 The TnGATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 19 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and TLn are used See Figure 20 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 54 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 8 3 8 4 8 5 P89LPC915 916 917 User manual Mode 2 Mode 2 configur
12. 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 15 of 125 jenuew asn rooz inr SL 10 AeY Sel JO OL 9LEEL OSZ L6E6 pamasa SIUBU IV POO A N 5910049913 sdijlud O PUIUOY Table 5 indicates SFRs that are bit addressable P89LPC915 Special function registers Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H ENBI1 ENADCI TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 1 ADINS A D input select A3H ADI13 ADI12 ADI11 ADI10 00 00000000 ADMODA A D mode register A COH BNDI1 BURST1 SCC1 SCAN1 00 00000000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 7 BSA1 3 00 000x0000 AD1BH A D_1 boundary high register C4H FF 11111111 AD1BL A D_1 boundary low register BCH 00 00000000 AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D_1 data register 2 D7H 00 00000000 AD1DAT3 A D_1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENTO SRST 0 DPS 00 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGROZ Baud rate generator rate low BEH 00 00000000 BRGR1 Baud rate generator rate high BFH 00
13. CMP2 md 1 TxD AD10 KBI1 gt CIN2B gt lt 1 4 RxD AD11 gt KBI2 gt CIN2A gt o gt gt lt gt TO gt SCL AD12 gt KBI3 gt CIN1IB k pgoLpco15 bE lt INTO gt SDA DAC1 AD13 gt KBI4 gt CINIA gt O EP O INTI CLKIN KBI5 gt CMPREF gt gt RST 002aaa828 Fig 1 P89LPC915 logic symbol Voo Vss had TxD AD10 KBI1 CIN2B gt lt RxD AD11 gt KBI2 gt CIN2A gt gt E lt gt TO lt gt SCL AD12 gt KBI3 gt CINIB gt 5 gt on INTO lt gt SDA DAC1 4 AD13 gt KBI4 gt CINIA gt A 4 lt gt CLKIN gt KBI5 CMPREF gt lt gt P89LPC916 lt RST gt a gt MOSI gt lt gt MISO gt O 55 4 gt gt 4 gt SPICLK 002aaa829 Fig 2 P89LPC916 logic symbol 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 Philips Semiconductors UM10107 P89LPC915 916 917 User manual AD10 gt KBI1 gt AD11 gt KBI2 gt AD12 gt KBI3 gt DAC1 4 AD13 KBIO CMP2 lt CIN2B gt CIN2A gt CIN1B gt gt KBI4 gt CINIA gt
14. e The 2C bus may be used for test and diagnostic purposes A typical 1 C bus configuration is shown in Figure 30 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus e Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte e Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 1 C bus will not be released The P89LPC915 916 917 device provides a byte oriented 12C interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode The P89LPC915 916 917 CPU interfaces with the I C bus through six Special Function Registers SFRs I2CON I C Control Register I2
15. P89LPC915 916 917 User manual Table 108 Instruction set summary Mnemonic Description Bytes Cycles Hex code MOVX A Ri Move external data A8 to A 1 2 E2 to E3 MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX DPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2 CO POP dir Pop direct byte from stack 2 2 DO XCH A Rn Exchange A and register 1 1 C8 to CF XCH A dir Exchange A and direct byte 2 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 XCHD A Ri Exchange A and indirect memory 1 1 D6 to D7 nibble BOOLEAN Mnemonic Description Bytes Cycles Hex code CLR C Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPLC Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long
16. Philips Semiconductors UM10107 9397 750 13316 17 10 Table 99 P89LPC915 916 917 User manual Flash User Configuration Byte UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks on page 29 for additional 1 FOsCc1 information Combinations other than those shown in Table 100 are reserved for ______________ future use should not be used 2 FOSC2 3 reserved 4 WDSE Watchdog Safety Enable bit Refer to Table 89 for details 5 BOE Brownout Detect Enable see Section 6 1 Brownout detection on page 47 6 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin Note During a power up sequence the RPE selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit 7 WDTE Watchdog timer reset enable When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 89 for details Table 100 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on CLKIN 100 Watchdog Oscillator 400 kHz 20 30 tol
17. UM10107 9397 750 13316 P89LPC915 916 917 User manual 17 12 Boot status register Table 106 Boot Status BOOTSTAT bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DDCP CWP AWP BSB Factory default 0 0 0 0 0 0 0 1 value Table 107 Boot Status BOOTSTAT bit description Bit Symbol 0 BSB 1 4 Description Boot Status Bit If programmed to logic 1 the P89LPC915 916 917 will always start execution at an address comprised of OOH in the lower eight bits and BOOTVEC as the upper bits after a reset See Section 7 1 Reset vector on page 52 reserved 5 AWP Activate Write Protection bit When this bit is cleared the internal Write Enable flag is forced to the set state thus writes to the flash memory are always enabled When this bit is set the Write Enable internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands to FMCON 6 CWP Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to logic 1 the writes to these registers are disabled If programmed to logic 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA 7 DDCP Disable Clear Configuration Protection command If
18. All rights reserved User manual Rev 01 15 July 2004 79 of 125 Philips Semiconductors UM10107 Table 69 Master Transmitter mode P89LPC915 916 917 User manual Status code Status of the Application software response Next action taken by 2 I2STAT 1C hardware eem to I2CON 12C hardware I2DAT STA STO SI AA 08H A START Load SLA W x 0 0 x SLA W will be condition has transmitted ACK bit will been be received transmitted 10H A repeat Load SLA W x 0 0 x As above SLA W will START or be transmitted 1 C condition has Load SLA R switches to Master been Receiver mode transmitted 18h SLA W has Load data 0 0 0 x Data byte will be been byte or transmitted ACK bit will transmitted be received ACKhasbeen no 12DAT 1 0 0 x Repeated START will be received action or transmitted no l2DAT 0 1 0 x STOP condition will be action or transmitted STO flag will be reset no I2DAT 1 1 0 x STOP condition followed action by a START condition will be transmitted STO flag will be reset 20h SLA W has Load data 0 0 0 x Data byte will be been byte or transmitted ACK bit will transmitted be received NOT ACKhas no I2DAT 1 0 0 x Repeated START will be been received action or transmitted no I2DAT 0 1 0 x STOP condition will be action or transmitted STO flag will be reset no l2DAT 1 1 0 x STOP condition followed action by a START condition will be transmitted STO flag will be reset 2
19. User manual Rev 01 15 July 2004 102 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual 15 1 Watchdog function The user has the ability using the WDCON and UCFG1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see Section 15 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WDSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to the Table 89 for details Figure 49 shows the watchdog timer in Watchdog mode It consists of a programmable 13 bit prescaler and an
20. any time without interrupting code execution Low power select The P89LPC915 916 917 is designed to run at 12 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower 3 A D converter 9397 750 13316 The P89LPC915 916 917 has an 8 bit 4 channel multiplexed successive approximation analog to digital converter module ADC1 and one DAC module DAC1 A block diagram of the A D converter is shown in Figure 12 The A D consists of a 4 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in combination with the successive approximation register SAR drives a digital to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 31 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual 002aaa783 Fig 12 A D converter block diagram 3 1 Features e An 8 bit 4 channel multiplexed input successive approximation A D converter e Four A D result registers e Six operating modes Fixed channel single conversion mode F
21. it will clear STO bit automatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatically 5 STA Start Flag STA 1 l C bus enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits fora STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When the 12C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the 12C interface is in an addressed slave mode STA 0 no START condition or repeated START condition will be generated 6 I2EN 12C Interface Enable When set enables the C interface When clear the C function is disabled 7 reserved C Status register This is a read only register It contains the status code of IC interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined 12C states When any of these states entered the SI bit will be set Refer to Table 69 to T
22. 0 0 0 0 0 0 0 0 Table 35 Power Control register A PCONA address B5h bit description Bit Symbol Description 0 reserved 1 SPD Serial Port UART Power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit reserved I2PD 12C Power down When logic 1 the internal clock to the 1 C bus is disabled Note that in either Power down mode or Total Power down mode the 12C clock will be disabled regardless of this bit reserved 5 VCPD Analog Voltage Comparators Power down When logic 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit 6 reserved RTCPD Real time Clock Power down When logic 1 the internal clock to the Real time Clock is disabled Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 50 of 125 Philips Semiconductors U M1 01 07 7 Reset P89LPC915 916 917 User manual 9397 750 13316 The P1 5 RST pin can function as either an active low reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to logic 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Note During a power on sequence The RPE selection is overridden and this pin will alway
23. 0 P1 0 Port 1 bit O O TxD Serial port transmitter data 8 1 O P1 1 Port 1 bit O RxD Serial port receiver data 7 O P1 2 Port 1 bit 2 Open drain when used as an output O TO Timer counter 0 external count input overflow output or PWM output o SCL I C serial clock input output 6 1 O P1 3 Port 1 bit 2 Open drain when used as an output O INTO External interrupt 0 input O SDA IC serial data input output 5 1 O P1 4 Port 1 bit 2 1 O INT1 External interrupt 1input 3 P1 5 Port 1 bit 5 Input only RST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force In System Programming mode Vss 4 Ground 0 V reference Vpp 10 Power Supply This is the power supply voltage for normal operation as well as Idle and Power down modes 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 7 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table 3 P89LPC916 pin description Symbol Pin Type PO 1toP0 5 1 13 14 I O 15 16 Description Port 0 Port 0 is a 5 bit I O port with user configurable outputs During reset Port 0 latches are co
24. 00000000 BRGCON Baud rate generator control BDH SBRGS BRGEN 002 xxxxxx00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 CO1 CMF1 oo xx000000 CMP2 Comparator 2 control register ADH CE2 CP2 CN2 OE2 CO2 CMF2 oo xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer high 83H 00 00000000 DPL Data pointer low 82H 00 00000000 FMADRH Program Flash address high E7H gt 5 00 00000000 FMADRL Program Flash address low E6H 00 00000000 SIOJONPUODIWIAS Sdijiud jenuew 19S 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Sel JO ZL 9LEEL OSZ L6E6 pense SIUBU IV POO A N 010049913 Sdiliyd exlipjuiuoy Table 5 P89LPC915 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMCON Program Flash Control E4H BUSY HVA HVE SV Ol 70 01110000 Read Program Flash Control Write FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD 7 6 5 4 3 2 1 0 FMDATA Program Flash data E5H 00 00000000 I2ADR 12C slave address register DBH I2ADR 6 I2ADR 5 I2ADR4 I2ADR3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 00000000 Bit address DF DE DD DC DB DA D9 D8 I2CON I2C control register D8H I2EN STA STO Sl AA CRSEL 00 x00000x0 I2DAT
25. 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer Timer 1 toggle output is available only on the P89LPC917 device Timer 0 toggle output is available on the P89LPC915 P89LPC916 and P89LPC917 devices 9 Real time clock system timer The P89LPC915 916 917 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 24 The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock CCLK or an external clock input There are three SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 The Real time clock system timer can be enabled by setting the RTCEN RTCCON 0 bit The Real time Clock is a 23 bit down counter initialized to all O s when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 0 s the counter will be reloaded again with RTCH RTCL 1111111 and a flag RT
26. 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SM1 With SMO defines the Serial port mode see Table 53 7 SMO FE The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the Serial port mode If SMODO 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMODO is logic 0 default mode on any reset 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 63 of 125 Philips Semiconductors U M1 01 07 E P89LPC915 916 917 User manual Table 53 Serial Port modes SM0 SM1 UART mode UART baud rate 00 Mode 0 shift register CCLKy default mode on any reset 01 Mode 1 8 bit UART Variable see Table 48 10 Mode 2 9 bit UART CCLKy 5 or CCLKY 6 11 Mode 3 9 bit UART Variable see Table 48 Table 54 Serial Port Status register SSTAT address BAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset X xX X x xX X 0 0 Table 55 Serial Port Status register SSTAT address BAh bit description Bit Symbol Description 0 STINT St
27. 12 5 Typical connections are shown in Figure 38 to Figure 40 Table 73 SPI Control register SPCTL address E2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO Reset 0 0 0 0 1 0 0 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 88 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual Table 74 SPI Control register SPCTL address E2h bit description Bit Symbol Description 0 SPRO SPI clock rate select 1 SPR1 SPR1 0 SPI clock rate 00 CCLK 4 01 CCLK 16 10 CCLK 64 11 CCLK 128 2 CPHA SPI Clock PHAse select see Figures 41 to 44 When logic 1 data is driven on the leading edge of SPICLK and is sampled on the trailing edge When logic 0 data is driven when SS is low SSIG 0 and changes on the trailing edge of SPICLK and is sampled on the leading edge Note If SSIG 1 the operation is not defined 3 CPOL SPI Clock POLarity see Figures 41 to 44 When 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge When logic 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge 4 MSTR Master Slave mode Select see Table 78 5 DORD SPI Data ORDer When logic 1 the LSB of the data word is transmitted first When logic 0 the MS
28. 12C data register DAH I2SCLH Serial clock generator SCL DDH 00 00000000 duty cycle register high I2SCLL Serial clock generator SCL DCH 00 00000000 duty cycle register low I2STAT 12C status register D9H STA4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 11111000 Bit address AF AE AD AC AB AA A9 A8 IENO Interrupt enable 0 A8H EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EST EC EKBI El2c ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority O B8H PWDRT PBO PS PSR PT1 PX1 PTO PXO joo x0000000 IPOH Interrupt priority O high B7H PWDRT PBOH PSH PT1H PX1H PTOH PXOH ooll x0000000 H PSRH Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PAD PST 8 z PC PKBI PI2C 00 00x00000 IP1H Interrupt priority 1 high F7H PADH PSTH PCH PKBIH PI2CH lool 00x00000 KBCON Keypad control register 94H PATN KBIF OO xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H 00 00000000 register KBPATN Keypad pattern register 93H FF 11111111 Bit address 87 86 85 84 83 82 81 80 SIOJONPUODIWIAS Sdijiud renueul Jas 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Sel JO SL 9LEEL OSZ L6E6 pamasa SIUBU IV 00 A N 91U049913 Sdiliyd O PUILOY Table 5 P89LPC915 Special function registers indicates SFRs t
29. 4 For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the P89LPC915 916 917 data sheet for specifications Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 47 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table 30 Brownout options BOE PMOD1 0 BOPD BOI EBO EA IEN0 7 Description UCFG1 5 PCON 1 0 PCON 5 PCON 4 IENO 5 0 erased XX X X X X Brownout disabled Vpp 4 11 total IX X X X operating range is 2 4 V to programmed power down 3 6 V 11 any mode 1 brownout X X X Brownout disabled Vpp other than total detect operating range is 2 4 V to power down powered 3 6 V However BOPD is down default to logic 0 upon power up O brownout 0 brownout X X Brownout reset enabled Vpp detect active detect operating range is 2 7 V to generates 3 6 V Upon a brownout reset reset BOF RSTSRC 5 will be set to indicate the reset source BOF can be cleared by writing logic 0 to the bit 1 brownout 1 enable 1 global Brownout interrupt enabled detect brownout interrupt Vpp operating range is 2 7 V generates an interrupt enable to 3 6 V Upon a brownout interrupt interrupt BOF RSTSRC 5 will be set BOF can be cleared by writing logic 0 to the bit 0 X Both brownout reset and x 0 interrupt disabled Vpp operating range is 2 4 V to
30. 9398 393 40011 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 123 of 125 Philips Semiconductors UM10107 21 Contents P89LPC915 916 917 User manual Introduction v eeeen nen 3 Logic symbols 3 Product comparison nn 4 Pin Configuration en 4 Special function registers 15 Memory organization 28 tl CN 29 Enhanced CPU cee eaee 29 Clock definitions n n aaa na anuanua 29 Clock output P89LPC917 29 On chip RC oscillator option 29 Watchdog oscillator option 30 External clock input option 30 Oscillator Clock OSCCLK wake up delay 31 CPU Clock CCLK modification DIVM register 00 ee eaee 31 Low power select 31 A D converter 2 2 2c cece eee ee 31 Feature S se Ardennen denten Gene ete aot etna 32 A D operating modes 33 Fixed channel single conversion mode 33 Fixed channel continuous conversion mode 33 Auto scan single conversion mode 33 Auto scan continuous conversion mode 33 Dual channel continuous conversion mode 34 Single step ennen en 34 Conversion mode selection bits 34 Trigger modes 35 Timer triggered start 35 Start immediately 0 0 0 5 35 Edge triggered 020005 35 Bound
31. A
32. CIN1B AD12 P0 4 POM1 4 POM2 4 KBI4 CIN1A AD13 DAC1 P0 5 POM1 5 POM2 5 KBI5 CMPREF P0 7 POM1 7 POM2 7 KBI7 T1 P1 0 P1M1 0 P1M2 0 TxD P1 1 P1M1 1 P1M2 1 RxD P1 2 P1M1 2 P1M2 2 TO SCL input only or open drain P1 3 P1M1 3 P1M2 3 INTO SDA input only or open drain P1 4 P1M1 4 P1M2 4 INT1 P1 5 P1M1 5 P1M2 5 RST P2 2 P2M1 2 P2M2 2 MOSI P2 3 P2M1 3 P2M2 3 MISO P2 4 P2M1 4 P2M2 4 SS P2 5 P2M1 5 P2M2 5 SPICLK Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 46 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual 6 Power monitoring functions 6 1 9397 750 13316 The P89LPC915 916 917 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect Brownout detection The Brownout Detect function determines if the power supply voltage drops below a certain level The default operation for a Brownout Detection is to cause a processor reset However it may alternatively be configured to generate an interrupt by setting the BOI PCON 4 bit and the EBO IENO 5 bit Enabling and disabling of Brownout Detection is done via the BOPD PCON 5 bit bit field PMOD1 0 PCON 1 0 and user configuration bit BOE UCFG1 5 If BOE is in an unprogrammed state brownout is disabled rega
33. Conversion mode bits BURST1 SCC1 Scani ADC1 conversion BURSTO SCCO Scand ADCO conversion mode mode 0 0 0 single step 0 0 0 single step 0 0 1 fixed channel 0 0 1 fixed channel single single auto scan single auto scan single 0 1 0 fixed channel 0 1 0 fixed channel continuous continuous dual channel dual channel continuous continuous 1 0 0 auto scan 1 0 0 auto scan continuous continuous Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 34 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 3 3 3 3 1 3 3 2 3 3 3 3 3 4 3 4 3 5 3 6 P89LPC915 916 917 User manual Trigger modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all A D operating modes This mode is selected by the TMM1 bit and the ADCS11 and ADCS10 bits See Table 16 Start immediately Programming this mode immediately starts a conversion This start mode is available in all A D operating modes This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register See Table 16 Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the convers
34. DAC1 PCLK OSCILLATOR peripheral clock 400 kHz PCLK Y BAUD RATE 2c GENERATOR Fig 11 Block diagram of oscillator control 002aaa831 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 30 of 125 Philips Semiconductors U M1 01 07 2 7 2 8 2 9 P89LPC915 916 917 User manual Oscillator Clock OSCCLK wake up delay The P89LPC915 916 917 has an internal wake up timer that delays the clock until it stabilizes This delay is 224 OSCCLK cycles plus 60 us to 100 us CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK N is the value of DIVM Since N ranges from 0 to 255 the CCLK frequency can be in the range of fose tO fosc 210 for N 0 CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events that allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode The value of DIVM may be changed by the program at
35. High voltage abort Set if either an interrupt or a brown out is detected during a program or erase cycle Also set if the brown out detector is disabled at the start of a program or erase cycle FMCMD 3 W Command byte bit 3 4 7 R reserved 4 7 FMCMD 4 W Command byte bit 4 4 7 FMCMD 5 W Command byte bit 5 4 7 FMCMD 6 W Command byte bit 6 4 7 FMCMD 7 W Command byte bit 7 An assembly language routine to load the page register and perform an erase program operation is shown below 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 112 of 125 Philips Semiconductors UM10107 9397 750 13316 P89LPC915 916 917 User manual gedek dek ede dek ded eee eek pgm user code PRR RRR RRR RR RE RRR ERR KERR RRR RRR eek ok 1 Inputs id R3 number of bytes to program byte R4 page address MSB byte R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs 7 R7 status byte C clear on no error set on error PRR RR ERR REE EER RR RRR EERE EE EERE ERE kkk LOAD EP PGM USER OV OV OV OV OV LOAD_PAGE OV INC OV BAD mam Ww DJNZ 00H 68H FMCON LOAD FMADRH R4 FMADRL R5 A R7 R0 A FMDAT R0 RO R3 LOAD PAGE FMCON EP R7 FMCON A R7 A 0FH BAD c load command clears page register get high address get low address
36. Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 82 of 125 Philips Semiconductors U M1 01 07 Zz P89LPC915 916 917 User manual Table 71 Slave Receiver mode Siatus code Status ofthe Application software response Next action taken by I2C I2STAT PC hardware to from to I2CON hardware I2DAT ST ST SI AA A 0O 70H General call No I2DAT X 0 0 0 Data byte will be received address 00H action or and NOT ACK will be has been returned received no I2DAT x 0 0 1 Data byte will be received ACK has action and ACK will be returned been returned 78H Arbitration no I2DAT x 0 0 0 Data byte will be received lost in action or and NOT ACK will be SLA R W as returned master no I2DAT x 0 0 1 Data byte will be received General call action and ACK will be returned address has been received ACK bit has been returned 80H Previously Read data x 0 0 0 Data byte will be received addressed byte or and NOT ACK will be with own SLA returned address Data read data byte x 0 0 1 Data byte will be received has been ACK bit will be returned received ACK has been returned 88H Previously Read data 0 0 0 0 Switched to not addressed addressed byte or SLA mode no recognition of with own SLA own SLA or general address address Data read data byte 0 0 0 1 Switched to not addressed has been or SLA mode Own SLA will be received recognized general call NACK
37. Mfg id Id 1 Id2 size size vector P89LPC915 2kBx8 7FFh 15h DDh 17h 256x8 16x8 00h P89LPC916 2kBx8 7FFh 15h DDh 18h 256x8 16x8 00h P89LPC917 2kBx8 7FFh 15h DDh 20h 256x8 16x8 00h 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 114 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual 17 7 Flash write enable 17 8 17 9 This device has hardware write enable protection This protection applies to IAP Lite mode and applies to both the user code memory space and the user configuration bytes UCFG1 BOOTVEC and BOOTSTAT This protection does not apply to ICP programmer mode If the Activate Write Enable AWE bit in BOOTSTAT 7 is a logic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit is a logic 1 then the state of the internal WE flag can be controlled by the user The WE flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA MOV FMCON 08H MOV FMDATA 96H The WE flag is CLEARED by writing the Clear Write Enable OBH command to FMCON followed by a key value 96H to FMDATA or by a reset MOV FMCON 0BH MOV FMDATA 96H Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be
38. P2M2 Port 2 output mode 2 A5H P2M2 5 P2M2 4 P2M2 3 P2M2 2 oot 00000000 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD I2PD SPPD SPD ool 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00000x RSTSRC Reset source register DFH BOF POF R_BK R_WD R_SF R_EX BI RTCCON Real time clock control D1H RTCF RTCS1 RTCSO z 5 a ERTC RTCEN 6o 011xxx00 RTCH Real time clock register HIGH D2H oole 00000000 RTCL Real time clock register LOW D3H ool 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H XX XXXXXXXX Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SIOJONPUODIWIAS Sdijiud Jenuew 13SN 216 916 SL69d 168d ZOLOLINN jenuew asn rooz Aint SL 10 AeY Gel JO Z 9LEEL OSZ L6E6 pamasa SIUBU IV 00 A N soluon0e d Sdiliyd exlipjuiuoy Table 6 P89LPC916 Special function registers indicates SFRs that are bit addressable Nam
39. P89LPC915 916 917 User manual Table 9 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIMS TRIM4 TRIM3 TRIM 2 TRIM 1 TRIM O Reset 0 0 Bits 5 0 loaded with factory stored value during reset Table 10 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbol Description 0 TRIM O Trim value Determines the frequency of the internal RC oscillator During 1 TRIM 1 reset these bits are loaded with a stored factory calibration value When writing to either bit 6 or bit 7 of this register care should be taken to preserve the 2 TRIM 2 current TRIM value by reading this register modifying bits 6 or 7 as required 3 TRIM 3 and writing the result to this register 4 TRIM4 5 TRIM 5 6 ENCLK when 1 CCLK is output on the XTAL2 pin provided the crystal oscillator is not being used 7 RCCLK when 1 selects the RC Oscillator output as the CPU clock CCLK Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz This oscillator can be used to save power when a high clock frequency is not needed External clock input option In this configuration the processor clock is derived from an external source driving the PO 5 pin The rate may be from 0 Hz up to 12 MHz RTCS1 0 XCLK gt RCCLK T CLKOUT CLKIN B CPU RCCLK B RC OSCILLATOR EUT gt ADC1
40. Programmed to logic 1 the Clear Configuration Protection CCP command is disabled in IAP Lite mode This command can still be used in ICP mode If programmed to logic 0 the CCP command can be used in all programming modes This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command in ICP mode Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 118 of 125 Philips Semiconductors UM10107 18 Instruction set P89LPC915 916 917 User manual Table 108 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD A dir Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC A dir Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with 1 1 36 to 37 carry ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with 1 1 98 to 9F borrow SUBB A dir Subtract direct byte from A with 2 1 95 borrow SUBB A Ri Subtract indirect memory from A 1 1 96 to 97 with borrow SUBB A data Subtract immediate from A with 2 1 94 borrow INC A Increment A 1 1 04 INC Rn Incre
41. STOP bit bit Break detect A break is detected when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 and 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to force the device to execute code using the Boot vector This occurs if the UART is enabled and the EBRR bit AUXR1 6 is set and a break occurs Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the Tx interrupt is gen
42. When logic 1 the internal comparator reference Vref is selected as the negative comparator input 4 CPn Comparator positive input select When logic 0 CINnA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 CEn Comparator enable When set the corresponding comparator function is enabled Comparator output is stable 10 microseconds after CEn is set 6 7 reserved Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 98 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual Comparator 1 P0 4 CIN1A P0 3 CIN1B _ CO1 P0 5 CMPREF VREF Change Detect ens P0 2 CIN2A P0 1 CIN2B Fig 45 Comparator input and output connections Change Detect CP2 Comparator 2 or CMP2 P0 0 TS co2 P89LPC915 917 OE2 CN2 annann0 13 2 13 3 13 4 9397 750 13316 Internal reference voltage An internal reference voltage Vref may supply a default reference when a single comparator input pin is used Please refer to the P89LPC915 916 917 data sheet for specifications Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by soft
43. and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 70 of 125 Philips Semiconductors U M1 01 07 zz P89LPC915 916 917 User manual reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 11 I2C interface The C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features e Bidirectional data transfer between masters and slaves e Multimaster bus no central master e Arbitration between simultaneously transmitting masters without corruption of serial data on the bus e Serial clock synchronization allows devices with different bit rates to communicate via one serial bus e Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
44. and 254 and e The high period of the TFn is always 256 THn e Loading THn with 00h will force the Tx pin high loading THn with FFh will force the Tx pin low Note that interrupt can still be enabled on the low to high transition of TFn and that TFn can still be cleared in software like in any other modes This mode is available on Timer 0 on the P89LPC915 916 917 devices and Timer 1 on the P89LPC917 device Table 42 Timer Counter Control register TCON address 88h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset 0 0 0 0 0 0 0 0 Table 43 Timer Counter Control register TCON address 88h bit description Bit Symbol Description 0 ITO Interrupt 0 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software 2 IT1 Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts P89LPC915 917 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 55 of 125 Philips Semiconductors U M1 01 07 T P89LPC915 916 917 User manual Table 43 Timer Counter Control register TCON address 88h bit description Bit Symbol Description 3 IE1 Interrupt 1 Edge flag Set
45. be configured as an input P2M2 4 P2M1 4 00 or quasi bidirectional P2M2 4 P2M1 4 01 In this case another master can drive this pin low to select this device as Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 92 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 12 6 12 7 P89LPC915 916 917 User manual an SPI slave and start sending data to it To avoid bus contention the SPI becomes a slave As a result of the SPI becoming a slave the MOSI and SPICLK pins are forced to be an input and MISO becomes an output The SPIF flag in SPSTAT is set and if the SPI interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master the user must set the MSTR bit again otherwise it will stay in slave mode Write collision The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is complete The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for b
46. be transmitted when the bus becomes free Table 70 Master Receiver mode Status code Status of the Application software response Next action taken by I2C I2STAT C hardware ESR to I2CON hardware I2DAT ST IST si ST A O A 08H A START Load SLA R x 0 0 x SLA R will be transmitted condition has ACK bit will be received been transmitted 10H A repeat Load SLA R x 0 0 x As above START or condition has Load SLA W SLA W will be transmitted been 2C bus will be switched to transmitted Master Transmitter mode 38H Arbitration lost no I2DAT 0 0 0 x _ C bus will be released it in NOT ACK action or will enter a slave mode bit no I2DAT 1 0 0 xX A START condition will be action transmitted when the bus becomes free 40h SLA R has no I2DAT 0 0 0 Databyte will be received been action or NOT ACK bit will be returned transmitted no I2DAT 0 0 0 1 Data byte will be received ACK has action or ACK bit will be returned been received Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 81 of 125 Philips Semiconductors UM10107 9397 750 13316 Table 70 Master Receiver mode P89LPC915 916 917 User manual Status code Status of the Application software response Next action taken by I2C I2STAT C hardware TTG to I2CON hardware abe ST IST si ST A O A 48h SLA R has No I2DAT 1 0
47. is again converted and its result stored in the third result register The second channel is again converted and its result placed in the fourth result register See Table 13 An interrupt is generated if enabled after every set of four conversions two conversions per channel This mode is selected by setting the SCC1 bit in the ADMODA register Table 13 Result registers and conversion results for dual channel continuous conversion mode Result register Contains AD1DATO First channel first conversion result AD1DAT1 Second channel first conversion result AD1DAT2 First channel second conversion result AD1DAT3 Second channel second conversion result Single step This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed in the result register which corresponds to the selected input channel See Table 11 May be used with any of the start modes This mode is selected by clearing the BURST1 SCC1 and SCAN1 bits in the ADMODA register Conversion mode selection bits The A D uses three bits in ADMODA to select the conversion mode These mode bits are summarized in Table 14 below Combinations of the three bits other than the combinations shown are undefined Table 14
48. is requested When the microcontrollers wishes to become the bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the I C bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 78 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual logic 0 write logic 1 read from Master to Slave O from Slave to Master Fig 35 Format of Slave Transmitter mode NEE ENEN a Sim L data transferred _ n Bytes acknowledge A acknowledge SDA LOW A not acknowledge SDA HIGH S START condition P STOP condition 002aaa933 8 NS gt T ADDRESS REGISTER Uy o a a lt INPUT z FILTER Li H P1 3 SDA Z OUTPUT STAGE BIT COUNTER ARBITRATION CCLK INPUT AND SYNC LOGIC TIMING FILTER AND NTROL P1 2 SCL en 5 SERIAL CLOCK OUTPUT INTERRUPT STAGE GENERATOR TIMER 1 EE OVERFLOW I2CON CONTROL REGISTERS AND RARs I2SCLH SCL DUTY CYCLE REGISTERS l2SCLL STATUS STATUS BUS DECODER I2STAT STATUS REGISTER D 002aaa421 N Fig 36 I2C serial interface block diagram 9397 750 13316 Koninklijke Philips Electronics N V 2004
49. least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first Watchdog oscillator PCLK WDCON A7H WDL C1H MOV WFEED1 0A5H b N MOV WFEED2 05AH 32 RESET see note 1 PRESCALER A A A CONTROL REGISTER A A SHADOW REGISTER FOR WDCON Peace re eao Lou woror woour 002aaa423 Fig 48 Watchdog timer in Watchdog mode WDTE 1 9397 750 13316 15 4 Watchdog timer in Timer mode Figure 49 shows the watchdog timer in Timer mode In this mode any changes to WDCON are written to the shadow register after one watchdog clock cycle A watchdog underflow will set the WDTOF bit If IENO 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic 0 to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 107 of 125 Philips Semiconductors U M1 01 07 P89LP
50. on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power up condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both BOF and this bit will be set while the other flag bits are cleared 5 BOF Brownout Detect Flag When Brownout Detect is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Note Ona Power on reset both POF and this bit will be set while the other flag bits are cleared 6 7 reserved Reset vector Following reset the P89LPC915 916 917 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address 00h The Boot address will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 8 Timers 0 and 1 9397 750 13316 The P89LPC915 916 917 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both timers of the P89LPC917 can be configured to operate either as timers or event counters see Table 39 Timer 0 of the P89LPC915 and P89LPC916 can be configured to operate either as a timer or an event counter see Table 39 Timer 1 of the P89LPC915 and P89LPC916 devices may only function as a timer An option to automatically toggle the Tx pin up
51. or SLA mode Own slave address will be recognized General call address will be recognized if I2ADR O 1 no l2DAT 1 0 0 0 Switched to not addressed action or SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no l2DAT 1 0 0 1 Switched to not addressed action SLA mode Own slave address will be recognized General call address will be recognized if I2ADR O 1 A START condition will be transmitted when the bus becomes free 12 Serial Peripheral Interface SPI P89LPC916 9397 750 13316 The P89LPC916 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master or Slave mode It has a Transfer Completion Flag and Write Collision Flag Protection Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 87 of 125 Philips Semiconductors U M1 01 07 iz P89LPC915 916 917 User manual CPU clock DIVIDER BY 4 16 64 128 Lle 8 BIT SHIFT REGISTER READ DATA BUFFER EEZ SPI clock master O SPI CONTROL 4 SPI STATUS REGISTER PIN CONTROL LOGIC SPR1 SPR SPIF DORD MSTR CPHA CPOL SPR1 SPRO w
52. read n Bytes acknowledge A acknowledge SDA LOW CO from Master to Slave A not acknowledge SDA HIGH O from Slave to Master S START condition 002aaa930 Fig 32 Format of Master Receiver mode After a repeated START condition the l C bus may switch to the Master Transmitter mode ENEN NE logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW 1 from Master to Slave A not acknowledge SDA HIGH LJ from Slave to Master S START condition P STOP condition SLA slave address RS repeat START condition 002aaa931 Fig 33 A Master Receiver switches to Master Transmitter after sending Repeated Start 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 77 of 125 Philips Semiconductors U M1 01 07 11 6 3 11 6 4 9397 750 13316 P89LPC915 916 917 User manual Slave Receiver mode In the Slave Receiver mode data bytes are received from a master transmitter To initialize the Slave Receiver mode the user should write the slave address to the Slave Address Register I2ADR and the 12C Control Register I2CON should be configured as follows Table 68 1 C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0 I2EN STA STO SI AA CRSEL value 1 0 0 0 1 CRSEL is not used for slave mode I2EN must be set 1 to enable I2C function AA bit mu
53. reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred Care should be taken when writing to AUXR1 to avoid accidental software resets Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A DPTR Move data byte the accumulator to data memory relative to DPTR MOVX DPTR A Move data byte from data memory relative to DPTR to the accumulator Also any instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC915 916 917 since the part doe
54. s T1M2 a S TOM2 Reset X X Xx 0 x X X 0 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 53 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 8 1 8 2 P89LPC915 916 917 User manual Table 41 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 TOM2 Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the Timer 0 mode see Table 41 1 3 reserved 4 T1iM2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 41 P89LPC917 The following timer modes are selected by timer mode bits TnM 2 0 000 8048 Timer TLn serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter THn and TLn are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TLn when it overflows Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 8 5
55. scheme Table 57 Slave 0 1 examples Example 1 Example 2 Slave 0 SADDR 11000000 Slave 1 SADDR 11000000 SADEN 1111 1101 SADEN 1111 1110 Given 1100 00X0 Given 1100000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Table 58 Slave 0 1 2 examples Example 1 Slave 0 SADDR SADEN Given 9397 750 13316 Example 2 Example 3 1100 0000 Slave 1 SADDR 11100000 Slave 2 SADDR 1100 0000 1111 1001 SADEN 1111 1010 SADEN 1111 1100 I ll 1100 OXXO Given 1110 0X0X Given 1110 00XX In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0
56. standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and read programmed erased under control of the end application e Programming and erase over the full operating voltage range e Any flash program operation in 2 ms 4 ms for erase program e Programmable security for the code in the Flash for each sector e gt 100 000 typical erase program cycles for each byte e 10 year minimum data retention Flash programming and erase The P89LPC915 91 6 917 program memory consists 256 byte sectors Each sector can be further divided into 16 byte pages In addition to sector erase and page erase a 16 byte page register is included which allows from 1 to 16 bytes of a given page to be programmed at the same time substantially reducing overall programming time Two methods of programming this device are available e In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite functions Any byte in a non secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for one or
57. the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive it simply tracks the input pin level If an external interrupt is enabled when the P89LPC915 916 917 is put into Power down or Idle mode the interrupt occurrence will cause the processor to wake up and resume operation Refer to Section 6 3 Power reduction modes for details External Interrupt pin glitch suppression Most of the P89LPC915 916 917 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC915 916 917 data sheet Dynamic characteristics for glitch filter specifications However pins SDA INTO P1 3 and SCL TO P1 2 do not have the glitch suppression circuits Therefore INT1 has glitch suppression while INTO does not Table 24 Summary of interrupts P89LPC915 P89LPC917 Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt 0 IEO 0003h EXO IENO 0 IPOH O IPO 0 1 highest Yes Timer 0 interrupt TFO 000Bh ETO IENO 1 IPOH 1 IPO 1 4 No External interrupt 1 IE1 0013h EX1 IENO 2 IPOH 2 IPO 2 7 Yes Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IPO 3 10 No Serial port Tx and Rx Tl and RI 0023h ES ESR IENO 4 IPOH 4 IP0 4 13 No S
58. there is any more data following 10 19 Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit SM2 in SCON One way to use this feature in multiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be logic 0 in Mode 1 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 69 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual 10 20 Au
59. tied low at all times This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line Additional considerations for a master In SPI transfers are always initiated by the master If the SPI is enabled SPEN 1 and selected as master writing to the SPI data register by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT Note that the master can select a slave by driving the SS pin of the corresponding device low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enabled ESPI or IEN1 3 1 The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave data is also shifted in the opposite direction simultaneously This means that during one shift cycle data in the master and the slave are interchanged Mode change on ss If SPEN 1 SSIG 0 and MSTR 1 the SPI is enabled in master mode The SS pin can
60. 0 0 Quasi bidirectional 0 1 Push pull 1 0 Input only high impedance 1 1 Open drain Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 42 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual 5 2 Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high it is weakly driven allowing an external device to pull the pin low When the pin is driven low it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under these conditions the external device has to s
61. 0 x Repeated START will be been action or transmitted transmitted ho 2DAT 0 1 0 x STOP condition will be NOTACKhas action or transmitted STO flag will be been received reset no I2DAT 1 1 0 x STOP condition followed by action or a START condition will be transmitted STO flag will be reset 50h Data byte has Read data 0 0 0 0O Data byte will be received been byte NOT ACK bit will be returned received ACK read data byte 0 0 0 1 Data byte will be received has been ACK bit will be returned returned 58h Data byte has Read data 1 0 0 x Repeated START will be been byte or transmitted received readdatabyte 0 1 0 x STOP condition will be NACK has or transmitted STO flag will be been returned reset read data byte 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset Table 71 Slave Receiver mode Status code Status ofthe Application software response Next action taken by I2C I2STAT 12C hardware TT to I2CON hardware I2DAT ST st SI AA A JO 60H Own SLA W no I2DAT X 0 0 0 Data byte will be received has been action or and NOT ACK will be received returned ACK has no I2DAT x 0 0 1 Data byte will be received been received action and ACK will be returned 68H Arbitration No I2DAT X 0 0 0 Data byte will be received lost in action or and NOT ACK will be SLA R Was returned master OWN no I2DAT x 0 0 1 Data byte will be received SLA W has action and ACK will be returned been received ACK returned
62. 00 RTCH Real time clock register HIGH D2H ool l 00000000 RTCL Real time clock register LOW D3H ool 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H XX XXXXXXXX Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SP Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH 3 T1M2 TOM2 00 XXXOXXXO Bitaddress 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 00000000 SIOJONPUODIWIAS Sdijiud jenuew 13SN 216 916 S169d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO Ze 9LEEL OSZ L6E6 pamasa SIUBU IV POO A N SWORE Sdiliyd O PUILOY Table 7 P89LPC917 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary THO Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TLO Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H TIGATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK ENCLK TRIM 5 TRIM4 TRIM3 TRIM 2 TRIM 1 TRIM O 5 6 WDC
63. 0000 I2ADR 12C slave address register DBH I2ADR 6 I2ADR 5 I2ADR4 I2ADR3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 00000000 Bit address DF DE DD DC DB DA D9 D8 I2CON I2C control register D8H I2EN STA STO Sl AA CRSEL 00 x00000x0 I2DAT 12C data register DAH I2SCLH Serial clock generator SCL DDH 00 00000000 duty cycle register HIGH I2SCLL Serial clock generator SCL DCH 00 00000000 duty cycle register LOW I2STAT 2C status register D9H STA4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 11111000 Bit address AF AE AD AC AB AA A9 A8 IENO Interrupt enable 0 A8H EA EWDRT EBO ES ESR ET1 EX1 ETO EXO 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EST EC EKBI El2c ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority O B8H PWDRT PBO PS PSR PT1 PX1 PTO PXO 00 _x0000000 IPOH Interrupt priority 0 HIGH B7H PWDRT PBOH PSH PT1H PX1H PTOH PXOH 00 x0000000 H PSRH Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PAD PST PC PKBI PI2C dl 00x00000 IP1H Interrupt priority 1 HIGH F7H PADH PSTH PCH PKBIH PI2CH 00f 00x00000 KBCON Keypad control register 94H PATN KBIF OO _ xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H 00 00000000 register KBPATN Keypad pattern register 93H FF 11111111 SIOJONPUODIWIAS Sdijiud jenuew J9SN 216 916 SL60d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO 92 9LEEL OSZ L6E6 pamasa SIUBU IV 00 A N
64. 02FFh DIRECT AND INDIR ADDR pagan SECTOR 2 4 REG BANKS R 7 0 01FFh 00h SECTOR 1 data memory 0100h DATA IDATA OOFFh SECTOR 0 000h 2 kB Flash code memory space 002aaa913 Fig 10 P89LPC915 916 917 memory map The various P89LPC915 916 917 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space OOh FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC915 916 917 has 2 kB of on chip Code memory Table 8 Data RAM arrangement Type Data RAM Size bytes DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 28 of 125 Philips Semiconductors U M1 01 07 2 Clocks P89LPC915 916 917 User manual 9397
65. 07 11 5 11 6 11 6 1 11 6 2 11 6 3 11 6 4 12 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 13 13 1 13 2 13 3 13 4 13 5 14 15 15 1 15 2 15 3 15 4 15 5 15 6 16 16 1 16 2 17 17 1 17 2 17 3 17 4 17 5 17 6 17 7 17 8 17 9 17 10 17 11 17 12 18 19 12C SCL duty cycle registers I2SCLH and I2SGLL 5 or ocen cedee dart a eland 75 I2C operation modes 76 Master Transmitter mode 76 Master Receiver mode 77 Slave Receiver mode 78 Slave Transmitter mode 78 Serial Peripheral Interface SPI P89LPC916 87 Typical SPI configurations 90 Configuring the SPI nananana 91 Additional considerations for a slave 92 Additional considerations for a master 92 Mode change on SS 0 005 92 Write collision eens 93 Data mode aiee d eee eee 93 SPI clock prescaler select 97 Analog comparators 2 0200085 97 Comparator configuration 97 Internal reference voltage 99 Comparator interrupt 99 Comparators and power reduction modes 99 Comparators configuration example 100 Keypad interrupt KBI aasa sanannnna 101 Watchdog timer 20 0 e cence 102 Watchdog function s sasa auauua 103 Feed sequence 104 Watchdog clock source 106 Watchdog timer in Timer mode 107 Power down operation
66. 1 0 Symbol KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 KBPATN O Reset 1 1 1 1 1 1 1 1 Table 82 Keypad Pattern register KBPATN address 93h bit allocation P89LPC916 Bit 7 6 5 4 3 2 1 0 Symbol KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 Reset 1 1 1 1 1 1 1 1 Table 83 Keypad Pattern register KBPATN address 93h bit allocation P89LPC917 Bit 7 6 5 4 3 2 1 0 Symbol KBPATN 7 KBPATN 5 KBPATN 4 KBPATN 3 KBPATN 2 KBPATN 1 KBPATN O Reset 1 1 1 1 1 1 1 1 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 101 of 125 Philips Semiconductors U M1 01 07 T P89LPC915 916 917 User manual Table 84 Keypad Pattern register KBPATN address 93h bit description Bit Symbol Access Description 0 7 KBPATN 7 0 R W Pattern bit 0 bit 7 Table 85 Keypad Control register KBCON address 94h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PATN_SEL KBIF Reset xX xX x xX xX xX 0 0 Table 86 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 _KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing 0 1 PATN SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not eq
67. 3 6 V However BOF RSTSRC 5 will be set when Vpp falls to the Brownout Detection trip point BOF can be cleared by writing logic 0 to the bit 6 2 Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing logic 0 to the bit Note that if BOE UCFG1 5 is programmed BOF RSTSRC 5 will be set when POF is set If BOE is unprogrammed BOF is meaningless 6 3 Power reduction modes The P89LPC915 916 917 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 31 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 48 of 125 Philips Semiconductors U M1 01 07 Table 31 P89LPC915 916 917 User manual Power reduction modes PMOD1 PCON 1 0 PMODO PCON 0 0 Description Normal mode default no power reduction 0 1 Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The P89LPC915 916 917 exits Power down mode via any reset or certain inte
68. 397 750 13316 P89LPC915 916 917 User manual Table 33 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction mode see Section 6 3 PMOD1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or written by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt When logic 0 Brownout Detection will cause a reset 5 BOPD Brownout Detect Power down When logic 1 Brownout Detect is powered down and therefore disabled When logic 0 Brownout Detect is enabled Note BOPD must be logic 0 before any programming or erasing commands can be issued Otherwise these commands will be aborted 6 SMODO Framing Error Location e When logic 0 bit 7 of SCON is accessed as SMO for the UART e When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 Table 34 Power Control register A PCONA address B5h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD VCPD I2PD SPD 7 Reset
69. 750 13316 2 1 2 2 2 3 2 4 Enhanced CPU The P89LPC915 916 917 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clock definitions The P89LPC915 916 917 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of three clock sources and can also be optionally divided to a slower frequency see Figure 11 and Section 2 8 CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output PCLK Clock for the various peripheral devices and is CCK The P89LPC915 916 917 provides user selectable oscillator options This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the FLASH is programmed and include an on chip watchdog oscillator an on chip RC oscillator or an external clock source Clock output P89LPC917 The P89LPC917 supports a user selectable clock output function on the CLKOUT pin This allows external devices to synchronize to the P89LPC917 This output is enab
70. 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK or the watchdog oscillator selected by the WDCLK bit in the WDCON register Note that switching of the clock sources will not take effect immediately see Section 15 3 The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a watchdog reset occurs the internal reset is active for at least one watchdog clock cycle PCLK or the watchdog oscillator clock If CCLK is still running code execution will begin immediately after the reset cycle If the processor was in Power down mode the watchdog reset will start the oscillator and code execution will resume after the oscillator is stable Table 89 Watchdog timer configuration WDTE WDSE FUNCTION UCFG1 7 UCFG1 4 0 x The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect 1 0 The watchdog reset is enabled The user can set WDCLK to choose the clock source 1 1 The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once 3 WDRUN is forced to 1 Koni
71. 8h Data byte in Load data 0 0 0 x Data byte will be I2DAT has byte or transmitted been ACK bit will be received transmitted ACKhasbeen I2DAT 1 0 0 xX Repeated START will be received action or transmitted no I2DAT 0 1 0 x STOP condition will be action or transmitted STO flag will be reset no l2DAT 1 1 0 x STOP condition followed action by a START condition 9397 750 13316 will be transmitted STO flag will be reset Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 80 of 125 Philips Semiconductors UM10107 9397 750 13316 P89LPC915 916 917 User manual Table 69 Master Transmitter mode Status code Status of the Application software response Next action taken by I2STAT PC hardware to from to I2CON 12C hardware I2DAT STA sTO SI AA 30h Data byte in Load data 0 0 0 x Data byte will be I2DAT has byte or transmitted been ACK bit will be received transmitted NOT ACK has no l2DAT 1 0 0 x Repeated START will be been received action or transmitted no I2DAT 0 1 0 x STOP condition will be action or transmitted STO flag will be reset no l2DAT 1 1 0 x STOP condition followed action by a START condition will be transmitted STO flag will be reset 38H Arbitration lost No l2DAT 0 0 0 x 12C bus will be released in SLA R W action or not addressed slave will or data bytes be entered No I2DAT 1 0 0 xX A START condition will action
72. B of the data word is transmitted first 6 SPEN TSPI Enable If set 1 the SPI is enabled If cleared 0 the SPI is disabled and all SPI pins will be port pins 7 SSIG SS IGnore If set 1 MSTR bit 4 decides whether the device is a master or slave If cleared 0 the SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 78 Table 75 SPI Status register SPSTAT address Eth bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SPIF WCOL s 2 2 Reset 0 0 x x x x x x Table 76 SPI Status register SPSTAT address Eth bit description Bit Symbol Description 0 5 Reserved 6 WCOL SPI Write Collision Flag The WCOL bit is set if the SPI data register SPDAT is written during a data transfer see Section 12 6 The WCOL flag is cleared in software by writing logic 1 to this bit 7 SPIF SPI Transfer Completion Flag When a serial transfer finishes the SPIF bit is set and an interrupt is generated if both the ESPI IEN1 3 bit and the EA bit are set If SS is an input and is driven low when SPI is in master mode and SSIG 0 this bit will also be set see Section 12 5 The SPIF flag is cleared in software by writing logic 1 to this bit Table 77 SPI Data register SPDAT address E3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MSB LSB Reset 0 0 0 0 0 0 0 0 Koninklijke Philips Electronics N V 2004 All right
73. C915 916 917 User manual Watchdog oscillator MOV WFEED1 0A5H pe A MOV WFEED2 05AH TR 8 BIT DOWN PRESCALER re COUNTER gt Interrupt PCLK WDCON A7H A A A i i SHADOW AAA CALO Fig 49 Watchdog timer in Timer mode WDTE 0 002aaa939 15 5 15 6 Power down operation The WDT oscillator will continue to run in power down consuming approximately 50 uA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see Section 15 3 Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 uA Whenever the WDT underflows the device will wake up 16 Additional features 9397 750 13316 The AUXR1 register contains several special purpose control bits that relate t
74. CF RTCCON 7 will be set Power on reset XTAL2 XTAL1 LOW FREQ MED FREQ 7 bit prescaler HIGH FREQ CCLK internal oscillators Wake up from power down De RIGE Le RTCS1 RTCS2 ee RTC underflow flag RTC enable RTC clk select shared with WDT ERTC Fig 24 Real time clock system timer block diagram 23 bit down counter 002aaag24 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 58 of 125 Philips Semiconductors U M1 01 07 E P89LPC915 916 917 User manual 9 1 Real time clock source RTCS1 RTCS0 RTCCON 6 5 are used to select either the external clock input or CCLK as the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CCLK If CCLK is derived from the external clock input on P0 5 then the RTC can use CCLK external clock input DIVM or the external input as its clock source 9 2 Changing RTCS1 RTCSO RTCS1 RTCSO cannot be changed if the RTC is currently enabled RTCCON O0 1 Setting RTCEN and updating RTCS1 RTCSO may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 RTCSO 9 3 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IENO 7 are set to logic 1 RTCF can be used as an interrupt source This interrupt vector is shared wi
75. CMF2 0043h EC IEN1 2 IPOH O IPO 0 11 Yes SPI SPIF 004Bh ESP IEN1 3 IP1H 3 1P1 3 14 No Serial port Tx TI 006Bh EST IEN1 6 IPOH 0 IPO 0 12 No ADC ADCI1 BNDI1 0073h EAD IEN1 7 IP1H 7 IP1 7 15 lowest No 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 40 of 125 Philips Semiconductors U M1 01 07 T P89LPC915 916 917 User manual IEO EXO ZA ni IE1 P89LPC915 917 4 j BOPD ie RTCF gt KBIF WAKE UP ERTC ne e IF IN POWER DOWN RTCCON 1 WDOVF gt EWDRT j gt CMF2 CMF1 EC _ EA IEO 7 1s oes Il ETO TF1 Z ET1 w en ES ESR TI Z INTERRUPT EST TO CPU a j H El2C Pastroste SPT ESPI a D ADCI1 BNDI1 EAD 002aaa833 Fig 13 Interrupt sources interrupt enables and power down wake up sources 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 41 of 125 Philips Semiconductors U M1 01 07 5 I O ports P89LPC915 916 917 User manual 9397 750 13316 5 1 The P89LPC915 has two I O ports Port 0 and Port 1 Ports 0 and 1 are 6 bit ports The P89LPC916 has three I O ports Port 0 Port 1 and Port 2 Ports 0 is a 5 bit port Port 1 is a 5 bit port and Port 2 is a 4 bit port The P89LPC917 has three I O ports Port 0 Port 1 and Port 2 P
76. D Control register 1 ADCON1 address 97h bit description Bit Symbol Description 0 ADCS10 A D start mode bits 11 10 1 ADCS11 00 Timer Trigger mode when TMM1 1 Conversions starts on overflow of Timer 0 Stop mode when TMM1 0 no start occurs 01 Immediate Start mode Conversions starts immediately 10 Edge Trigger mode Conversion starts when edge condition defined by bit EDGE1 occurs 2 ENADC1 Enable A D channel 1 When set 1 enables ADC1 Must also be set for D A operation of this channel 3 ADCI1 A D Conversion complete Interrupt 1 Set when any conversion or set of multiple conversions has completed Cleared by software 4 EDGE1 When 0 an Edge conversion start is triggered by a falling edge on P1 4 When 1 an Edge conversion start is triggered by a rising edge on P1 4 5 TMM1 Timer Trigger mode 1 Selects either stop mode TMM1 0 or timer trigger mode TMM1 1 when the ADCS11 and ADCS10 bits 00 6 ENADCI1 Enable A D Conversion complete Interrupt 1 When set will cause an interrupt if the ADCI1 flag is set and the A D interrupt is enabled 7 ENBI1 Enable A D boundary interrupt 1 When set will cause an interrupt if the boundary interrupt 1 flag BNDI1 is set and the A D interrupt is enabled Table 17 A D Mode Register A ADMODA address COh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BNBI1 BURST1 SCC1 SCAN1 p Reset 0 0 0 0 0 0 0 0 Koninkl
77. DAT I C Data Register I2STAT 1 C Status Register IZADR 12C Slave Address Register I2SCLH SCL Duty Cycle Register High Byte and I2SCLL SCL Duty Cycle Register Low Byte 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 71 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 11 1 P89LPC915 916 917 User manual Rp Rp woe P1 3 SDA P1 2 SCL l SDA SCL OTHER DEVICE OTHER DEVICE WITH I2C BUS INTERFACE WITH I2C BUS P89LPC915 916 917 INTERFACE 002aaa834 Fig 30 F C bus configuration I2C Data register I2DAT register contains the data to be transmitted or the data received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte Thus this register should only be accessed when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 59 C Data register I2DAT address DAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 2DAT 7 I2DAT 6 I2DAT5 I2DAT 4 I2DAT 3 I 2DAT 2 I2DAT 1 I2DAT O Reset 0 0 0 0 0 0 0 0 PC Slave Address register I2ADR register is readable and writable and is only used when t
78. DAT3 AD13 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result registers Table 12 An interrupt if enabled will be generated after every four conversions Additional conversion results will again cycle through the four result registers overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the SCC1 bit in the ADMODA register Auto scan single conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 11 An interrupt if enabled will be generated after all selected channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode This mode is selected by setting the SCAN1 bit in the ADMODA register Table 12 Result registers and conversion results for fixed channel continuous conversion mode Result register Contains AD1DATO Selected channel first conversion result AD1DAT1 Selected channel second conversion result AD1DAT2 Selected channe
79. ER 0 INTERRUPT D D TIMER 1 Ed COMPARATORS POWER MONITOR POWER ON RESET BROWNOUT RESET Fig 7 P89LPC915 block diagram 002aaa822 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 12 of 125 Philips Semiconductors UM10107 9397 750 13316 P89LPC915 916 917 User manual P89LPC916 PORT 2 CONFIGURABLE I Os PORT 1 CONFIGURABLE I Os PORT 0 CONFIGURABLE I Os external clock input ON CHIP RC OSCILLATOR ACCELERATED 2 CLOCK 80C51 CPU ZN 2 kB CODE FLASH INTERNAL 256 BYTE Bue DATA RAM 2 1 fe gt UART me i LN KEYPA _ INTERRUPT WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER cpu V CLOCK REAL TIME CLOCK SYSTEM TIMER gt y TIMER 0 TIMER 1 jee EE le SPI WH TTT ANALOG COMPARATORS POWER MONITOR POWER ON RESET BROWNOUT RESET Fig 8 P89LPC916 block diagram 002aaa823 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 13 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual P89LPC917 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU 2 kB CODE FLASH INTERNAL 256 BYTE BYS DATA RAM PORT 2 mmm CONFIGURABLE I Os
80. H PSTH PSPIH PCH PKBIH PI2CH oo 00x00000 KBCON Keypad control register 94H PATN KBIF OO _ xxxxxx00 _SEL KBMASK Keypad interrupt mask 86H 00 00000000 register KBPATN Keypad pattern register 93H FF 11111111 SIOJONPUODIWIAS Sdijiud jenuew J9SN 216 916 SL60d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO ZZ 9LEEL OSZ L6E6 pamasa SIUBU IV 00 A N 91U049913 Sdiliyd afu oy Table 6 P89LPC916 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 87 86 85 84 83 82 81 80 PO Port 0 80H CMPREF CINIA CIN1B CIN2A CIN2B 0l KBI5 KBI4 KBI3 KBI2 KBI1 Bit address 97 96 95 94 93 92 91 90 P1 Port 1 90H RST INTO TO SCL RXD TXD 1 SDA Bit address 97 96 95 94 93 92 91 90 P2 Port 2 AOH SPICLK ss MISO MOSI u POM1 Port 0 output mode 1 84H POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 FFU 11111111 POM2 Port 0 output mode 2 85H POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 oof 00000000 P1M1 Port 1 output mode 1 91H P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3 11x1xx11 P1M2 Port 1 output mode 2 92H P1M2 3 P1M2 2 P1M2 1 P1M2 0 OOL 00x0xx00 P2M1 Port 2 output mode 1 A4H P2M1 5 P2M1 4 P2M1 3 P2M1 2 FFU 11111111
81. I2EN STA STO SI AA CRSEL value 1 0 0 0 x bit rate CRSEL defines the bit rate I2EN must be set to logic 1 to enable the 2C function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The C bus will enter Master Transmitter Mode by setting the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh
82. L A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 62 XRL dir data Exclusive OR immediate to 3 2 63 direct byte CLRA Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 RRC A Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Rn dir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct 2 2 86 to 87 byte MOV dir data Move immediate to direct byte 3 75 MOV Ri A Move A to indirect memory 1 F6 to F7 MOV Ri dir Move direct byte to indirect 2 2 A6 to A7 memory MOV Ri data Move immediate to indirect 2 1 76 to 77 memory MOV DPTR data Move immediate to data pointer 3 90 MOVC A A DPTR Move code byte relative DPTRto 1 93 A MOVC A A PC Move code byte relative PC toA 1 2 94 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 120 of 125 Philips Semiconductors UM10107
83. LO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Goto3 Fig 29 Transmission with and without double buffering e l f f t ae f f Single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown OTE T tit if j Double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown no ending Tx interrupt DBISEL SSTAT 4 0 TxD write to SBUF Tx interrupt TxD write to SBUF 1 1 1 1 Tx interrupt f f f Double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown with ending Tx interrupt DBISEL SSTAT 4 1 i 002aaa928 9397 750 13316 10 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the Tx interrupt Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 68 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation describ
84. N Reset 0 1 1 x x x 0 0 Table 46 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WOTE UCFG1 7 is logic 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt 24 reserved RTCSO Real time Clock source select see Table 44 6 RTCS1 7 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software 9397 750 13316 The P89LPC915 916 917 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC915 916 917 does include an independent Baud Rate Generator The baud rate can be selected from CCLK divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect aut
85. NNOT be erased in IAP Lite mode 3 7 reserved Table 103 Effects of Security Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed X Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 17 11 Boot Vector register Table 104 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 0 0 1 1 1 value Table 105 Boot Vector BOOTVEC bit description Bit Symbol Description 0 2 BOOTV 0 2 Boot vector If the Boot Vector is selected as the reset address the P89LPC915 916 917 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 3 7 reserved 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 117 of 125 Philips Semiconductors
86. ON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK 4 6 WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2_ Watchdog feed 2 C3H 1 All ports are in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC915 916 917 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 4 After reset the value is 111001x1 i e PRE 2 0 are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset source that affects these SFRs is power on reset SIOJONPUODIWIAS Sdijiud jenuew J9SN 216 916 S169d 168d ZOLOLINN Philips Semiconductors U M1 01 07 zz P89LPC915 916 917 User manual 1 5 Memory organization 07FFh ozoon SECTOR 7 O6FFh osoon SECTOR 6 O5FFh IDATA incl DATA FFh SECTOR 5 SPECIAL FUNCTION 128 BYTES ON CHIP 0500h REGISTERS DATA MEMORY STACK ie SERT DIRECTLY ADDRESSABLE AND INDIR ADDR nn DATA 7Fh O3FFh SECTORS 128 BYTES ON CHIP 0300h DATA MEMORY STACK
87. P89LPC915 916 917 User manual 10 6 Baud Rate generator and selection The P89LPC915 916 917 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 25 Note that Timer T1 is further divided by 2 if the SMOD1 bit PCON 7 is set The independent Baud Rate Generator uses CCLK 10 7 Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the result is unpredictable Table 48 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON 1 Receive transmit baud rate for UART SM0 SM1 SMOD1 SBRGS 0 0 x x CCLK g 0 1 0 0 COLK 556 TH1 64 1 0 COCLK o56 TH1 32 X 1 CCLK BRGR1 BRGRO 16 1 0 0 X COL 1 X CCLKy 6 1 1 0 0 COLK 556 TH1 64 1 0 CCL 56 TH1 32 X 1 CCLK BRaR1 BRGRO 16 Table 49 Baud Rate Generator Control register BRGCON address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS BRGEN Reset xX x xX x x xX 0 0 Table 50 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol Description 0 B
88. PICLK P1 0 TXD P1 1 RXD Fig 6 CIN2B KBI1 AD10 P0 1 O KBIO CMP2 P0 0 RST P1 5 Vss LPC917 MOSI P2 2 INT1 P1 4 SDA INTO P1 3 SCL TO P1 2 002aaa827 P89LPC917 TSSOP pin configuration P0 2 CIN2A KBI2 AD1 1 P0 3 CIN1B KB13 AD12 P0 4 CIN1A KBI4 AD13 DAC1 P0 5 CMPREF KBI5 CLKIN VDD PO 7 T1 KBI7 CLKOUT P1 0 TXD P1 1 RXD 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 5 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table2 P89LPC915 pin description Symbol P0 0 to P0 5 9397 750 13316 Pin 1 2 11 12 13 14 Type I O Description Port 0 Port 0 is a 6 bit I O port with user configurable outputs During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below P0 0 Port 0 bit 0 CMP2 Comparator 2 output KBIO Keyboard input 0 P0 1 Port 0 bit 1 CIN2B Comparator 2 positive input B KBI1 Keyboard input 1 AD10 A D channel 1 input 0
89. RGEN Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and 3 see Table 48 for details 2 7 reserved SMOD1 1 Timer 1 Overflow SBRGS 0 j AA PCLK based o 1 Baud Rate Modes 1 and 3 SMOD1 0 SBRGS 1 Baud Rate Generator CCLK based 002aaa419 Fig 25 Baud rate generation for UART Modes 1 3 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 62 of 125 Philips Semiconductors U M1 01 07 Zz P89LPC915 916 917 User manual 10 8 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SSTAT In addition if SMODO PCON 6 is 1 framing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMODO is logic 0 10 9 Break detect A break detect is reported in the status register SSTAT A break is detected when any 11 consecutive bits are sensed low Since a break condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit ha
90. RR AUXR1 6 __ Brownout detect reset BOPD PCON 5 e Fig 18 Block diagram of reset 002aaa918 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 51 of 125 Philips Semiconductors U M1 01 07 7 1 P89LPC915 916 917 User manual Table 36 Reset Sources register RSTSRC address DFh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOF POF RBK RWD RSF REX Reset x x 1 1 0 0 0 0 1 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 37 Reset Sources register RSTSRC address DFh bit description Bit Symbol Description 0 R_EX external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic 0 to the bit or a Power on reset If RST is still asserted after the Power on reset is over R_EX will be set 4 R_SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 R_WD Watchdog timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset Note UCFG1 7 must be 1 3 R BK break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset 4 POF Power
91. S is selected and is driven low The MSTR bit will be cleared to logic 0 when SS becomes low 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 91 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual Table 78 SPI master and slave selection SPEN SSIG SS pin MSTR Masteror MISO MOSI SPICLK Comments slave mode N 1 Master input Hi Hi Z MOSI and SPICLK are at high impedance to idle avoid bus contention when the MAster is idle The application must pull up or pull down SPICLK depending on CPOL SPCTL 3 to avoid a floating SPICLK Master output output MOSI and SPICLK are push pull when the active Master is active 1 1 P2 40 0 Slave output input input 1 1 P2 40 1 Master input output output 1 Selected as a port function 2 The MSTR bit changes to logic 0 automatically when SS becomes low in input mode and SSIG is logic 0 9397 750 13316 12 3 12 4 12 5 Additional considerations for a slave When CPHA equals zero SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte If the SPDAT register is written while SS is active low a write collision error results The operation is undefined if CPHA is logic 0 and SSIG is logic 1 When CPHA equals one SSIG may be set to logic 1 If SSIG 0 the SS pin may remain active low between successive transfers can be
92. ST External Reset input during power on or if selected via UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force In System Programming mode P2 2 5 O Port 2 Port 2 2 is a single bit I O port with a user configurable output During reset the Port 2 2 latch is configured in the input only mode with the internal pull up disabled The operation of the output depends upon the port configuration selected Refer to Section 5 1 and details This pin has a Schmitt triggered input Vss 4 Ground 0 V reference Vpp 12 Power Supply This is the power supply voltage for normal operation as well as Idle and Power down modes 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 11 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual external clock input tf P89LPC915 HIGH PERFORMANCE ACCELERATED 2 CLOCK 80C51 CPU gt ANALOG WATCHDOG TIMER AND OSCILLATOR PROGRAMMABLE OSCILLATOR DIVIDER ON CHIP RC CPU CLOCK OSCILLATOR 2 kB gt ART a Ke INTERNAL 256 BYTE BUS DATA RAM gt PORTI mmm CONFIGURABLE I Os ADC1 DAC1 PORT 0 CONFIGURABLE I Os REAL TIME CLOCK SYSTEM TIMER KEYPAD TIM
93. Solu0n09 Sdiliyd OxPUILOY Table 7 P89LPC917 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address 87 86 85 84 83 82 81 80 PO Port 0 80H T1 KBI7 CMPREF CINIA CIN1B CIN2A CIN2B CMP2 0l CLKOUT KBI5 KBI4 KBI3 KBI2 KBI1 KBIO Bitaddress 97 96 95 94 93 92 91 90 P1 Port 1 90H RST INT1 INTO TO SCL RXD TXD dl SDA POM1 Port 0 output mode 1 84H POM1 7 POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFE 11111111 POM2 Port 0 output mode 2 85H POM2 7 POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 joo 00000000 P1M1 Port 1 output mode 1 91H P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D3E 11x1xx11 P1M2 Port 1 output mode 2 92H P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 00 00x0xx00 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD I2PD SPD ool 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV F1 P 00 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00000x RSTSRC Reset source register DFH BOF POF R_BK R_WD R_SF R_EX BI RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN 60L1I 61 011xxx
94. UM10107 P89LPC915 916 917 wee 8 bit microcontrollers with two clock 80C51 core and 8 bit A D Rev 01 15 July 2004 User manual El Document information Info Content Keywords P89LPC915 P89LPC916 P89LPC917 Abstract Technical information for the P89LPC915 P89LPC916 and P89LPC917 devices Philips Semiconductors U M1 01 07 ze P89LPC915 916 917 User manual Revision history Rev Date Description 01 20040715 Initial version 9397 750 13316 Contact information For additional information please visit http www semiconductors philips com For sales office addresses please send an email to sales addresses www semiconductors philips com 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 2 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual 1 Introduction The P89LPC915 916 917 are single chip microcontrollers designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC915 916 917 is based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC915 916 917 in order to reduce component count board space and system cost 1 1 Logic symbols Voo Vss KBIO
95. UXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGRO Baud rate generator rate BEH 00 00000000 LOW BRGR1 2 Baud rate generator rate BFH 00 00000000 HIGH BRGCON Baud rate generator control BDH SBRGS BRGEN OOR xxxxxx00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 CO1 CMF1 00 4 xx000000 CMP2 Comparator 2 control register ADH CE2 CP2 CN2 OE2 CO2 CMF2 oo xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer HIGH 83H 00 00000000 DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H z 5 5 00 00000000 SIOJONPUODIWIAS Sdijiud jenuew JSN 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO GZ 9LEEL OSZ L6E6 pamasa SIUBU IV 002 A N 91U049913 sdijlud afu oy Table 7 P89LPC917 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control E4H BUSY 5 HVA HVE SV Ol 70 01110000 Read Program Flash Control Write FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD 7 6 5 4 3 2 1 0 FMDATA Program Flash data E5H 00 0000
96. XXXXXXXX l Bit address 9F 9E 9D 9C 9B 9A 99 98 SCON Serial port control 98H SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 00000000 SSTAT Serial port extended status BAH DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 00000000 register SP Stack pointer 81H 07 00000111 TAMOD Timer 0 and 1 auxiliary mode 8FH 7 7 7 TOM2 00 XXXOXXXO Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 00000000 THO Timer 0 high 8CH 00 00000000 SIOJONPUODIWIAS Sdijiud Jenuew 13SN 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Sel JO 6L 9LEEL OSZ L6E6 pamasa SIUBU IV 002 A N Solu0n09 3 Sdiliyd exlpjuiuoy Table 5 P89LPC915 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary TH1 Timer 1 high 8DH 00 00000000 TLO Timer 0 low 8AH 00 00000000 TL1 Timer 1 low 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK 5 TRIM 5 TRIM 4 TRIM3 TRIM2 TRIM 1 TRIM O STO WDCON Watchdog control register A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK 4 WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H 1 All ports are in input only high impedance state after power up value is xx110000 reset
97. able 72 for details Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 74 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 11 5 P89LPC915 916 917 User manual Table 64 C Status register I2STAT address D9h bit allocation Bit 7 6 5 4 3 2 1 Symbol STA 4 STA 3 STA 2 STA 1 STA 0 0 0 0 Reset 0 0 0 0 0 0 0 0 Table 65 1 C Status register I2STAT address D9h bit description Bit Symbol Description 0 2 Reserved are always set to logic 1 3 7 STA 0 4 C Status code PC SCL duty cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the 12C interface by setting CRSEL 0 in the I2CON register the user must set values for registers I2SCLL and I2SCLH to select the data rate I2SCLH defines the number of PCLK cycles for SCL high I2SCLL defines the number of PCLK cycles for SCL low The frequency is determined by the following formula Bit Frequency fpcuk 2 I2ZSCLH I2SCLL Where fpcix is the frequency of PCLK The values for l2SCLL and I2SCLH do not have to be the same the user can give different duty cycle s for SCL by setting these two registers However the value of the register must ensure that the data rate is in the I C bus data rate range of 0 to 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommend
98. are described later in this section Table 38 Timer Counter Mode register TMOD address 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 39 Timer Counter Mode register TMOD address 89h bit description Bit Symbol Description 0 TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD 1 TOM1 register to determine the Timer 0 mode see Table 41 2 TOC T Timer or Counter selector for Timer 0 Cleared for Timer operation input from CCLKk Set for Counter operation input from TO input pin 3 TOGATE Gating control for Timer 0 When set Timer Counter is enabled only while the INTO pin is high and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set 4 T1MO Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD 5 TiM1 register to determine the Timer 1 mode see Table 41 6 T1C T Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLKk Set for Counter operation input from T1 input pin 7 T1GATE Gating control for Timer 1 When set Timer Counter is enabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set Table 40 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol
99. ared by writing logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to logic 1 3 4 reserved Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 105 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual Table 91 Watchdog timer Control register WDCON address A7h bit description Bit Symbol Description 5 PREQ 6 PRE1 Clock Prescaler Tap Select Refer to Table 92 for details 7 _PRE2 Table 92 Watchdog timeout vales PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK 2 Watchdog Nominal Clock 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms 100 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 101 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms 110 0 2 049 5 12 ms 341 5 us 255 524 289 1 31 s 87 4 ms 111 0 4097 10 2 ms 682 8 us 255 1 048 577 2 62 s 174 8 ms 15 3 Watchdog clock source The watchdog timer system h
100. ary limits interrupt 35 DAC output to a port pin with high impedance 35 Clock divider 20 000e 0 eee 35 I O pins used with A D converter functions 35 Power down and idle mode 36 Interrupts snars nnen nen nnn cae 38 Interrupt priority structure 38 External Interrupt pin glitch suppression 39 WO POMS sonen meenen er rens dd 42 Port configurations s sanaan annaa 42 Quasi bidirectional output configuration 43 Open drain output configuration 44 Input only configuration 44 Push pull output configuration 45 Port 0 analog functions 45 I O pins used with analog functions 46 9397 750 13316 10 10 10 11 10 12 10 13 10 14 10 15 10 16 10 17 10 18 10 19 10 20 11 11 1 11 2 11 3 11 4 Power monitoring functions 47 Brownout detection 055 47 Power on detection 055 48 Power reduction modes 48 PROS OU erranaren aR alae wt Soe lhe ate wale 2 51 Reset VECTOR a sheds eraan Poa eae 52 Timers 0 and 1 00 e cece eee eee 52 Mode 0 ee 54 MOAB Taig ca der ade der iare bemad Eleme a 54 Mode 2 eee 55 MOAB B ren ern aten de Ga dh Blabla dd 55 Mode 6 v eee 55 Timer overflow toggle output 57 Real time clock system timer 58 Real time clock source
101. as an on chip 400 KHz oscillator The watchdog timer can be clocked from either the watchdog oscillator or from PCLK refer to Figure 47 by configuring the WDCLK bit in the Watchdog Control Register WDCON When the watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU After changing WDCLK WDCON 0 switching of the clock source will not immediately take effect As shown in Figure 49 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as two old clock source counts plus two new clock cycles 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 106 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at
102. atus Interrupt Enable When set 1 FE BR or OE can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 FE BR OE cannot cause an interrupt Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to logic 1 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is still set Cleared by software 2 BR Break Detect flag A break is detected when any 11 consecutive bits are sensed low Cleared by software 3 FE Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end INTLO 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all tran
103. by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is processed or by software P89LPC915 917 TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 TFO Timer 0 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in Mode 6 where it is cleared in hardware 6 TRI Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in Mode 6 see above when it is cleared in hardware c C T 0 overflow PCLK Tn bi on TEn interrupt n pin C T 1 control L Sbits toggle TRn a L Tn pin Gate INTn pin ENTn 002aaa919 Fig 19 Timer counter 0 or 1 in Mode 0 13 bit counter C T 0 overflow PCLK Th bi on AED Thin interrupt n pin D CT 1 control 8 bits 8 bits toggle TRn Gate INTn pin ENTn 002aaa920 Fig 20 Timer counter 0 or 1 in Mode 1 16 bit counter 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 56 of 125 Philips Semiconductors U M1 01 07
104. cation Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 4 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL 7 4 are used to select a page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the program idle state is exited FMCON will contain status information for the cycle If an interrupt occurs during an erase programming cycle the e
105. cleared to 0 and P2 4 SS configured in quasi bidirectional mode When a device initiates a transter it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 12 5 to slave Master Slave c 1 R 1 MISO MISO 8 BIT SHIFT Tt gt 8 BIT SHIFT REGISTER _ MOSI MOSI _ REGISTER SPICLK h aa SPI CLOCK 002aaa499 ji l l l l l ji l l SPICLK SPI CLOCK T l T l l l l l f l l f l l l Fig 40 SPI single master multiple slaves configuration In Figure 40 SSIG SPCTL 7 bits for the slaves are logic 0 and the slaves are selected by the corresponding SS signals The SPI master can use any port pin including P2 4 SS to drive the SS pins Configuring the SPI Table 78 shows configuration for the master slave modes as well as usages and directions for the modes Table 78 SPI master and slave selection SPEN SSIG SSpin MSTR Masteror MISO MOSI SPICLK Comments slave mode 0 x P2 4 x SPI P2 3l P2 20 P2 50 SPI disabled P2 2 P2 3 P2 4 P2 5 are used Disabled as port pins 1 0 0 Slave output input input Selected as slave 1 1 0 Slave Hi Z input input Not selected MISO is high impedance to avoid bus contention 1 0 0 gt Slave output input input P2 4 SS is configured as an input or 0 2 quasi bidirectional pin SSIG is 0 Selected externally as slave if S
106. ctively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to 0 s to enable the digital functions I O pins used with analog functions After power up all pins are in Input only mode Please note that this is different from the LPC76x series of devices e After power up all I O pins except P1 5 may be configured by software e Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC915 916 917 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC915 916 917 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times Table 29 Port output configuration Port pin Configuration SFR bits PxM1 y PxM2 y Alternate usage Notes P0 0 POM1 0 POM2 0 KBIO CMP2 PO 1 POM1 1 POM2 1 KBI1 CIN2B AD10 Refer to Section 5 6 Port 0 P0 2 POM1 2 POM2 2 KBI2 CIN2A AD11 amp aalog functions for usage as analog inputs P0 3 POM1 3 POM2 3 KBI3
107. ddressed action SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Table 72 Slave Transmitter mode Status code Status ofthe Application software response Next action taken by I2C I2STAT 12C hardware nem to I2CON hardware I2DAT ST ST SI JAA A 0O A8h Own SLA R Load data x 0 0 0 Last data byte will be has been byte or transmitted and ACK bit will received be received ACK has load data byte x 0 0 1 Data byte will be been returned transmitted ACK will be received BOh Arbitration Load data x 0 0 0 Last data byte will be lost in byte or transmitted and ACK bit will SLA R W as be received master Own load data byte x 0 0 1 Data byte will be SLA R has transmitted ACK bit will be been received received ACK has been returned Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 85 of 125 Philips Semiconductors UM10107 9397 750 13316 P89LPC915 916 917 User manual Table 72 Slave Transmitter mode Status code Status ofthe Application software response Next action taken by I2C I2STAT IC hardware AET to I2CON hardware I2DAT ST ST SI JAA A O B8H Data byte in Load data X 0 0 0 Last data byte will be I2DAT has byte or transmitted and ACK bit will been be received transmitted load data byte x 0 0 1 Data byte will be ACK ha
108. de 0 a write to SBUF will initiate a transmission At the end of the transmission TI SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and RI will be set again at the end of the transfer When RI is cleared the reception of the next character will begin Refer to Figure 26 s1 srofst 16 s1 stefst stefst stofst stofsr stelst stefsr S16 s1 t6 s1 16 s1 stelst sel write to SBUF shift LIL ILL SN transmit RXD data out do X Di X 22 X D3 X D4 X D5 X DE XK 7 DO Ghiftelo LF LLL TI WRITE to SCON clear RI S To RI shift l l l l l l RXD DO D1 TD D2 T D3 T D4 D5 D6 D7 data in TxD shift clock receive 002aaa925 Fig 26 Serial Port Mode 0 double buffering must be disabled 10 11 More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RxD RxD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit ti
109. dition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 38 of 125 Philips Semiconductors UM10107 4 2 P89LPC915 916 917 User manual These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 or ITO in Register TCON If ITn 0 external interrupt n is triggered by a low level detected at the INTn pin If ITn 1 external interrupt n is edge triggered In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input high or low level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin high for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If
110. dog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC915 916 917 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructions to disable and re enable interrupts may be removed In Watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 MOV ACC WDCON get WDCON SETB ACC 2 set WD RUN 1 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 104 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual MOV WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt MOV WDCON ACC write back to WDCON after the watchdog is enabled a feed must occur immediately MOV WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the con
111. e Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary SP Stack pointer 81H 07 00000111 SPCTL SPI control register E2H SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 00000100 SPSTAT SPI status register E1H SPIF WCOL 00 00xXXXXXX SPDAT SPI data register E3H 00 00000000 TAMOD Timer 0 and 1 auxiliary mode 8FH TOM2 00 XXXOXXXO Bit address 8F 8E 8D 8C 8B 8A 89 88 TCON Timer 0 and 1 control 88H TF1 TR1 TFO TRO IEO ITO 00 00000000 THO Timer 0 HIGH 8CH 00 00000000 TH1 Timer 1 HIGH 8DH 00 00000000 TLO Timer 0 LOW 8AH 00 00000000 TL1 Timer 1 LOW 8BH 00 00000000 TMOD Timer 0 and 1 mode 89H T1GATE T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 00000000 TRIM Internal oscillator trim register 96H RCCLK TRIM 5 TRIM4 TRIM3 TRIM2 TRIM 1 TRIM O Bi WDCON Watchdog control register A7H PRE2 PRE1 PREO 5 WDRUN WDTOF WDCLK 4 WDL Watchdog load C1H FF 11111111 WFEED1 Watchdog feed 1 C2H WFEED2_ Watchdog feed 2 C3H 1 All ports are in input only high impedance state after power up 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC915 916 917 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is xx110000 4 After reset the value is 111001x1 i e PRE 2 0 are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is l
112. e of initializing one comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs outputs the comparator result to the CMP1 pin and generates an interrupt when the comparator output changes CMPINIT MOV PTOAD 030h Disable digital INPUTS on pins CIN1A CMPREF ANL POM2 0CFh Disable digital OUTPUTS on pins that are used ORL POM1 030h for analog functions CIN1A CMPREF MOV CMP1 020h Turn on comparator 1 and set up for Positive input on CINIA Negative input from CMPREF pin CALL delayl0us start up for at least 10 microseconds before use ANL CMP1 0FEh Clear comparator 1 interrupt flag SETB EC Enable the comparator interrupt The priority is left at the current value 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 100 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual SETB EA Enable the interrupt system if needed RET Return to caller The interrupt routine used for the comparator must clear the interrupt flag CMF 1 in this case before returning 14 Keypad interrupt KBI The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks T
113. ed The values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended Table 66 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373MHz 3 6865MHz 1 8433MHz 12 MHz 6 MHz I2SCLH 6 0 z 307 154 j 7 0 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 75 of 125 Philips Semiconductors U M1 01 07 L P89LPC915 916 917 User manual Table 66 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 Kbpsto 1 8 Kbpsto 0 9 Kbpsto 5 86 Kbpsto 2 93 Kbps to 922 Kbps 461 Kbps 230 Kbps 1500 Kbps 750 Kbps Timer 1 in Timer 1 in Timer 1 in Timer 1 in Timer 1 in mode 2 mode 2 mode 2 mode 2 mode 2 11 6 1 C operation modes 11 6 1 Master Transmitter mode In this mode data is transmitted from master to slave Before the Master Transmitter mode can be entered I2CON must be initialized as follows Table 67 1 C Control register I2CON address D8h Bit 7 6 5 4 3 2 1 0
114. ed by the user in 8 bit auto reload mode Mode 2 Data rate of 12C Timer overflow rate 2 PCLK 2 256 reload value If fosc 12 MHz reload value is 0 to 255 so I C data rate range is 11 72 Kbit sec to 3000 Kbit sec When CRSEL 0 the 12C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 The STA bit is START flag Setting this bit causes the I2C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the I2C interface to transmit a STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then a STOP condition is transmitted to the I C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 62 1 C Control register I2CON address D8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2EN STA STO SI AA CRSEL Reset x 0 0 0 0 0 x 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 73 of 125 Philips Semiconductors UM10107 9397 750 13316 11 4 P89LPC915 916 917 User manual Table 63 12C Control register I2CON address D8h b
115. ed in the Section 10 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 on page 67 becomes as follows The double buffer is empty initially The CPU writes to TB8 The CPU writes to SBUF The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately A WW ND 5 If there is more data go to 7 else continue on 6 6 If there is no more data then If DBISEL is logic 0 no more interrupt will occur If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether
116. er manual Rev 01 15 July 2004 99 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual in order to obtain fast switching times while in Power down mode The reason is that with the clock stopped the temporary strong pull up that normally occurs during switching ona quasi bidirectional port pin does not take place Comparators consume power in Power down and Idle modes as well as in the normal operating mode This should be taken into consideration when system power consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode CINnA CINnA COn CMPREF O Qon CMPREF O CMPD 002aaa618 002aaa620 a CPn CNn OEn 0 00 b CPn CNn OEn 0 01 CINnA CINnA COn VREF 1 23V con VREF 1 23 V SMER 002aaa621 002aaa622 c CPn CNn OEn 0 1 0 d CPn CNn OEn 0 1 1 CINnB CINnB COn CMPREF Gon CMPREF DME 002aaa623 002aaa624 e CPn CNn OEn 1 00 f CPn CNn OEn 1 01 CINnB CINnB COn VREF 1 23V gon VREF 1 23 V SMER 002aaa625 002aaa626 g CPn CNn OEn 110 h CPn CNn OEn 1 1 1 Fig 46 Comparator configurations 13 5 Comparators configuration example The code shown below is an exampl
117. erance 011 Internal RC oscillator 7 373 MHz 2 5 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 12 MHz User security bytes This device has three security bits associated with each of its eight sectors as shown in Table 101 Table 101 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 116 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table 102 Sector Security Bytes SECx bit description Bit Symbol 0 MOVCDISx Description MOVC Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte in a MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and sector x are erased by either a sector erase command I IAP Lite ICP or a global erase command ICP 2 EDISx Erase Disable ISP Disables the ability to perform an erase of sector x in IAP mode When programmed this bit and sector x can only be erased by a global erase command using ICP This bit and sector x CA
118. erated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue 5 If there is no more data then If DBISEL is logic 0 no more interrupts will occur Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 67 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following 6 If there is more data the CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INT
119. erial port Rx RI Brownout detect BOF 002Bh EBO IENO 5 IPOH 5 IPO 5 2 Yes Watchdog timer Real time WDOVF RTCF 0053h EWDRT IENO 6 IPOH 6 IPO 6 3 Yes clock 12C interrupt Sl 0033h El2C IEN1 0 IPOH 0 IPO 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IPOH 0 IPO 0 8 Yes Comparators 1 2 interrupts CMF1 CMF2 0043h EC IEN1 2 IPOH 0O IPO 0 11 Yes Serial port Tx Tl 006Bh EST IEN1 6 IPOH 0 IP0 0 12 No ADC ADCH BNDI1 0073h EAD IEN1 7 IP1H 7 IP1 7 15 lowest No 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 39 of 125 Philips Semiconductors UM10107 Table 25 Summary of interrupts P89LPC916 P89LPC915 916 917 User manual Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt 0 IEO 0003h EXO IENO 0 IPOH 0 IPO 0 1 highest Yes Timer 0 interrupt TFO 000Bh ETO IENO 1 IPOH 1 IPO 1 4 No Timer 1 interrupt TF1 001Bh ET1 IENO 3 IPOH 3 IPO 3 10 No Serial port Tx and Rx TI and RI 0023h ES ESR IENO 4 IPOH 4 IP0 4 13 No Serial port Rx RI Brownout detect BOF 002Bh EBO IENO 5 IPOH 5 IP0 5 Yes Watchdog timer Real time WDOVF RTCF 0053h EWDRT IENO 6 IPOH 6 IP0 6 Yes clock 12C interrupt Sl 0033h El2C IEN1 0 IPOH 0O IPO 0 5 No KBI interrupt KBIF 003Bh EKBI IEN1 1 IPOH 0 IPO 0 8 Yes Comparators 1 2 interrupts CMF1
120. es the Timer register as an 8 bit Counter TLn with automatic reload as shown in Figure 21 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 Mode 3 When Timer 1 is in Mode 3 it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 22 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC915 916 917 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 23 Its structure is similar to Mode 2 except that e TFn n 0 and 1 for Timers 0 and 1 respectively is set and cleared in hardware e The low period of the TFn is in THn and should be between 1
121. eset Port 0 PO 7 13 14 15 latches are configured in the input only mode with the internal pull up disabled The 16 operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below 2 0 P0 0 Port 0 bit 0 CMP2 Comparator 2 output KBIO Keyboard input 0 1 O P0 1 Port 0 bit 1 CIN2B Comparator 2 positive input B KBI1 Keyboard input 1 AD10 A D channel 1 input 0 16 0 P0 2 Port 0 bit 2 CIN2A Comparator 2 positive input A KBI2 Keyboard input 2 AD11 A D channel 1 input 1 15 0 P0 3 Port 0 bit 3 CIN1B Comparator 1 positive input B KBI3 Keyboard input 3 AD12 A D channel 1 input 2 14 O P0 4 Port 0 bit 4 CIN1A Comparator 1 positive input A KBI4 Keyboard input 4 AD13 A D channel 1 input 3 O DAC1 Digital to analog converter 1 output 13 I O P0 5 Port 0 bit 5 CMPREF Comparator reference negative input KBI5 Keyboard input 5 CLKIN External clock input 11 O P0 7 Port 0 bit 7 T1 Timer counter 1 external count input overflow output or PWM output KBI7 Keyboard input 7 CLKOUT Clock output
122. has address will be recognized if been returned I2ADR 0 1 read databyte 1 0 0 0 Switched to not addressed or SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 83 of 125 Philips Semiconductors UM10107 9397 750 13316 P89LPC915 916 917 User manual Table 71 Slave Receiver mode Status code Status ofthe Application software response Next action taken by I2C I2STAT 12C hardware GE to I2CON hardware I2DAT ST st SI AA A O 90H Previously Read data X 0 0 0 Data byte will be received addressed byte or and NOT ACK will be with General returned call Data has tead data byte x 0 0 1 Databyte will be received been and ACK will be returned received ACK has been returned 98H Previously Read data 0 0 0 0 Switched to not addressed addressed byte SLA mode no recognition of with General own SLA or General call call Data has address been f read data byte 0 0 0 1 Switched to not addressed received SLA mode Own slave NACK has address will be recognized been returned General call addre
123. hat are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary PO Port 0 80H CMPREF CINIA CIN1B CIN2A CIN2B CMP2 il KBI5 KBI4 KBI3 KBI2 KBI1 KBIO Bit address 97 96 95 94 93 92 91 90 Pi Port 1 90H RST INT1 INTO TO SCL RXD TXD y SDA POM1 Port 0 output mode 1 84H POM1 5 POM1 4 POM1 3 POM1 2 POM1 1 POM1 0 FFE 11111111 POM2 Port 0 output mode 2 85H POM2 5 POM2 4 POM2 3 POM2 2 POM2 1 POM2 0 00l 00000000 P1M1 Port 1 output mode 1 91H P1M1 4 P1M1 3 P1M1 2 P1M1 1 P1M1 0 D30 11x1xx11 P1M2 Port 1 output mode 2 92H P1M2 4 P1M2 3 P1M2 2 P1M2 1 P1M2 0 ooll 00x0xx00 PCON Power control register 87H SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO 00 00000000 PCONA Power control register A B5H RTCPD VCPD ADPD l2PD SPD ool 00000000 Bit address D7 D6 D5 D4 D3 D2 D1 DO PSW Program status word DOH CY AC FO RS1 RSO OV Fi P 00 00000000 PTOAD Port 0 digital input disable F6H PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 xx00000x RSTSRC Reset source register DFH BOF POF R_BK R_WD R_SF R_EX 3 RTCCON Real time clock control D1H RTCF RTCS1 RTCSO ERTC RTCEN 6o16 011xxx00 RTCH Real time clock register high D2H 0018 00000000 RTCL Real time clock register low D3H oole 00000000 SADDR Serial port address register A9H 00 00000000 SADEN Serial port address enable B9H 00 00000000 SBUF Serial Port data buffer register 99H XX
124. he 12C interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Table 60 C Slave Address register IZADR address DBh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol I2ADR 6 I2ADR 5 I2ADR 4 I2ADR3 I2ADR 2 I2ADR 1 I2ADR 0 GC Reset 0 0 0 0 0 0 0 0 Table 61 1 C Slave Address register I2ADR address DBh bit description Bit Symbol Description 0 GC General call bit When set the general call address OOH is recognized otherwise it is ignored 1 7 I2ADR1 7 7 bit own slave address When in master mode the contents of this register has no effect Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 72 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual 11 3 2C Control register The CPU can read and write this register There are two bits are affected by hardware the SI bit and the STO bit The Sl bit is set by hardware and the STO bit is cleared by hardware CRSEL determines the SCL source when the I2C bus is in master mode In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master 12C device When CRSEL 1 the 12C interface uses the Timer1 overflow rate divided by 2 for the I2C clock rate Timer 1 should be programm
125. here are three SFRs used for this function The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN_SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN_SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Table 81 Keypad Pattern register KBPATN address 93h bit allocation P89LPC915 Bit 7 6 5 4 3 2
126. ial function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary FMADRL Program Flash address LOW E6H 00 00000000 FMCON Program Flash Control E4H BUSY 5 HVA HVE SV Ol 70 01110000 Read Program Flash Control Write FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD FMCMD 7 6 5 4 3 2 1 0 FMDATA Program Flash data E5H 00 00000000 I2ADR 12C slave address register DBH I2ADR 6 I2ADR 5 I2ADR4 I2ADR3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 00000000 Bit address DF DE DD DC DB DA D9 D8 I2CON 2C control register D8H I2EN STA STO SI AA gt CRSEL 00 x00000x0 I2DAT 12C data register DAH I2SCLH Serial clock generator SCL DDH 00 00000000 duty cycle register HIGH I2SCLL Serial clock generator SCL DCH 00 00000000 duty cycle register LOW I2STAT 2C status register D9H STA4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 11111000 Bit address AF AE AD AC AB AA A9 A8 IENO Interrupt enable 0 A8H EA EWDRT EBO ES ESR ET1 ETO EXO 00 00000000 Bit address EF EE ED EC EB EA E9 E8 IEN1 Interrupt enable 1 E8H EAD EST ESPI EC EKBI El2c ool 00x00000 Bit address BF BE BD BC BB BA B9 B8 IPO Interrupt priority O B8H PWDRT PBO PS PSR PT1 PTO PXO ool x0000000 IPOH Interrupt priority 0 HIGH B7H PWDRT PBOH PSH PT1H PTOH PXOH 00 x0000000 H PSRH Bit address FF FE FD FC FB FA F9 F8 IP1 Interrupt priority 1 F8H PAD PST PSPI PC PKBI PI2C dl 00x00000 IP1H Interrupt priority 1 HIGH F7H PAD
127. if the slave mode was enabled setting AA logic 1 The appropriate action to be taken for each of these status codes is shown in Table 69 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 76 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual ENNE EE logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW 1 from Master to Slave A not acknowledge SDA HIGH C from Slave to Master S START condition P STOP condition 002aaag2g Fig 31 Format in the Master Transmitter mode 11 6 2 Master Receiver mode In the Master Receiver mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to I C Data Register I2DAT The SI bit must be cleared before the data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 71 for details EE ENNE NE logic 0 write data transferred _ logic 1
128. ift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF TX clock write to SBUF Ue i he S transmit tart oo we A Do XD XD XC De XD XD Xe XD XC TBB Y stop bit me INTLO 0 INTLO 1 RX star a 16 reset gt _bit A DO X Di X D2 X D3 X D4 X D5 X DE X D7 X RBE stop bit receive sg TER SMODO 0 SMODO 1 002aaa927 Fig 28 Serial Port Mode 2 or 3 only single transmit buffering case is shown 10 13 Framing error and RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 66 of 125 Philips Semiconductors U M1 01 07 10 14 10 15 10 16 10 17 9397 750 13316 P89LPC915 916 917 User manual Table 56 FE and RI when SM2 1 in Modes 2 and 3 Mode PCON 6 RB8 Rl FE SMODO 2 0 0 No RI when RB8 0 Occurs during STOP bit 1 Similar to Figure 28 with SMODO 0 RI Occurs during STOP occurs during RB8 one bit before FE bit 3 1 0 No RI when RB8 0 Will NOT occur 1 Similar to Figure 28 with SMODO 1 RI Occurs during STOP occurs during
129. iguration The open drain output configuration turns off all pull ups and only drives the pull down transistor of the port pin when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi bidirectional mode The open drain port configuration is shown in Figure 15 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC915 916 917 data sheet Dynamic characteristics for glitch filter specifications port A pin port latch n data input data o lt o lt glitch rejection 002aaa915 Fig 15 Open drain output 5 4 Input only configuration The input port configuration is shown in Figure 16 It is a Schmitt triggered input that also has a glitch suppression circuit 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 44 of 125 Philips Semiconductors U M1 01 07 T P89LPC915 916 917 User manual Please refer to the P89LPC915 916 917 data sheet Dynamic characteristics for glitch filter specifications input port data pin glitch rejection 002aaa916 Fig 16 Input only 5 5 Push pull output configuration The push pull output configuration has the same pull down structu
130. ijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 36 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual Table 18 A D Mode Register A ADMODA address COh bit description Bit Symbol Description 0 3 reserved 4 SCAN1 when 1 selects single conversion mode auto scan or fixed channel for ADC1 5 SCC1 when 1 selects fixed channel continuous conversion mode for ADC1 6 BURST1 when 1 selects auto scan continuous conversion mode for ADC1 7 BNBI1 ADC1 boundary interrupt flag When set indicates that the converted result from ADC1 is outside of the range defined by the ADC1 boundary registers Table 19 A D Mode Register B ADMODB address Ath bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLK2 CLK1 CLKO ENDAC1 BSA1 Reset 0 0 0 0 0 0 0 0 Table 20 A D Mode Register B ADMODB address Ath bit description Bit Symbol Description 0 reserved 1 BSA1 ADC1 Boundary Select All When 1 BNDI1 will be set if any ADC1 input exceeds the boundary limits When 0 BNDI1 will be set only if the AD10 input exceeded the boundary limits 2 reserved ENDAC1 When 1 selects DAC mode for ADC1 when 0 selects ADC mode de reserved CLKO Clock divider to produce the ADC clock Divides CCLK by the CLK1 value indicated below The resulting ADC clock should be 3 3 MHz or less A m
131. inimum of 0 5 MHz is required to maintain A D CLK2 accuracy A D start mode bits CLK2 0 divisor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ND oO A Table 21 A D Input Select register ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AIN13 AIN12 AIN11 AIN10 5 Reset 0 0 0 0 0 0 0 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 37 of 125 Philips Semiconductors U M1 01 07 4 Interrupts P89LPC915 916 917 User manual Table 22 A D Input Select register ADINS address A3h bit description Bit Symbol Description 0 3 reserved 4 AIN10 when set enables the AD10 pin for sampling and conversion 5 AIN11 when set enables the AD11 pin for sampling and conversion 6 AIN12 when set enables the AD12 pin for sampling and conversion 7 AIN13 when set enables the AD13 pin for sampling and conversion 9397 750 13316 4 1 The P89LPC915 916 917 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC915 916 917 s many interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individuall
132. ink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage The third pull up is referred to as the strong pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port latch changes froma logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high The quasi bidirectional port configuration is shown in Figure 14 Although the P89LPC915 916 917 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC915 916 917 data sheet Dynamic characteristics for glitch filter specifications Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 43 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual 2 CPU CLOCK DELAY weak P P P strong very weak port latch data input data id glitch rejection 002aaa914 Fig 14 Quasi bidirectional output 5 3 Open drain output conf
133. ion has completed The edge triggered start mode is available in all A D operating modes This mode is selected by setting the ADCS11 and ADCS10 bits in the ADCON1 register See Table 16 Boundary limits interrupt The A D converter has both a high and low boundary limit register After the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion are outside the limit an interrupt will be generated if enabled If the conversion result is within the limits the boundary limits will again be compared after all 8 bits have been converted An interrupt will be generated if enabled if the result is outside the boundary limits The boundary limit may be disabled by clearing the boundary limit interrupt enable DAC output to a port pin with high impedance The ADODATS register is used to hold the value fed to the DAC After a value has been written to ADODATS3 the DAC output will appear on the DACO pin The DAC output is enabled by the ENDACO bit in the ADMODB register See Table 20 Clock divider The A D converter requires that its internal clock source be in the range of 500 kHz to 3 3 MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose See Table 20 I O pins used with A D converter functions The analog input pins used with for the A D converter have a digital input and output f
134. ister A COH BNDI1 BURST1 SCC1 SCAN1 00 00000000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 BSA1 00 000x0000 AD1BH A D_1 boundary HIGH C4H FF 11111111 register AD1BL A D_1 boundary LOW BCH 00 00000000 register AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D 1 data register 2 D7H 00 00000000 AD1DAT3 A D 1 data register 3 F5H 00 00000000 AUXR1 Auxiliary function register A2H CLKLP EBRR ENTO SRST 0 DPS 00 000000x0 Bit address F7 F6 F5 F4 F3 F2 F1 FO B B register FOH 00 00000000 BRGRO Baud rate generator rate BEH 00 00000000 LOW BRGR1 2 Baud rate generator rate BFH 00 00000000 HIGH BRGCON Baud rate generator control BDH SBRGS BRGEN 002 xxxxxx00 CMP1 Comparator 1 control register ACH CE1 CP1 CN1 CO1 CMF1 oo l xx000000 CMP2 Comparator 2 control register ADH CE2 CP2 CN2 OE2 CO2 CMF2 00 xx000000 DIVM CPU clock divide by M 95H 00 00000000 control DPTR Data pointer 2 bytes DPH Data pointer HIGH 83H 00 00000000 DPL Data pointer LOW 82H 00 00000000 FMADRH Program Flash address HIGH E7H z 5 5 00 00000000 SIOJONPUODIWIAS Sdijiud jenuew 13SN 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO Le 9LEEL OSZ L6E6 pamasa SIUBU IV 00 A N 5910049913 Sdiliyd OxPUIUOY Table 6 P89LPC916 Spec
135. it description Bit Symbol Description 0 CRSEL SCL clock selection When set 1 Timer1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values of I2SCLH and I2SCLL reserved 2 AA The Assert Acknowledge Flag When set to logic 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The own slave address has been received 2 The general call address has been received while the general call bit GC in I2ADR is set 3 A data byte has been received while the 12C interface is in the Master Receiver Mode 4 A data byte has been received while the 12C interface is in the addressed Slave Receiver Mode When cleared to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 A data byte has been received while the 12C interface is in the Master Receiver Mode 2 A data byte has been received while the 1 C interface is in the addressed Slave Receiver Mode 3 Sl 12C Interrupt Flag This bit is set when one of the 25 possible 2C bus states is entered When EA bit and El2C IEN1 0 bit are both set an interrupt is requested when Sl is set Must be cleared by software by writing 0 to this bit 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the 2C bus When the bus detects the STOP condition
136. ixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode e Three conversion start modes Timer triggered start Start immediately Edge triggered e 8 bit conversion time of gt 3 9 us at an ADC clock of 3 3 MHz e Interrupt or polled operation e Boundary limits interrupt e DAC output to a port pin with high output impedance e Clock divider e Power down mode 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 32 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 3 2 3 2 1 3 2 2 3 2 3 3 2 4 P89LPC915 916 917 User manual A D operating modes Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel See Table 11 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCAN1 bit in the ADMODA register Table 11 Input channels and Result registers for fixed channel single auto scan single and autoscan continuous conversion modes Result register Input channel Result register Input channel AD1DATO AD10 AD1DAT2 AD12 AD1DAT1 AD11 AD1
137. jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 121 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual Table 108 Instruction set summary Mnemonic Description Bytes Cycles Hex code JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne 3 2 B4 relative CJNE Rn d rel Compare register inmediate jne 3 2 B8 to BF relative CJNE Ri d rel Compare indirect immediate jne 3 2 B6 to B7 relative DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz 3 2 D5 relative MISCELLANEOUS NOP No operation 1 1 00 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 122 of 125 Philips Semiconductors UM10107 19 Disclaimers Life support These products are not designed for use in life support appliances devices or systems where malfunction of these products can reaso
138. l third conversion result AD1DAT3 Selected channel forth conversion result Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 11 An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 33 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 3 2 5 3 2 6 3 2 7 P89LPC915 916 917 User manual conversion results will again cycle through the result registers of the selected channels overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the BURST1 bit in the ADMODA register Dual channel continuous conversion mode Any combination of two of the four input channels can be selected for conversion The result of the conversion of the first channel is placed in the first result register The result of the conversion of the second channel is placed in the second result register The first channel
139. led by the ENCLK bit in the TRIM register The frequency of this clock output is 1 2 that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of bits 5 0 of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register On chip RC oscillator option The P89LPC915 916 917 has a TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 Note the initial value is better than 1 please refer to the P89LPC915 916 917 data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the oscillator frequency Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 29 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 2 5 2 6
140. me is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 65 of 125 Philips Semiconductors U M1 01 07 E P89LPC915 916 917 User manual TX clock write to SBUF shift l j j n i j i n jl transmit tart TxD w Lo XO X DeX De X Dt X X e X Y stop bn 9 INTLO 0 INTLO 1 RX clock l l l l l l l l l l l l l l start shift RI receive 002aaa926 Fig 27 Serial Port Mode 1 only single transmit buffering case is shown 10 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final sh
141. ment register 1 1 08 to OF INC dir Increment direct byte 2 1 05 INC Ri Inerement indirect memory 1 1 06 to 07 DEC A Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DA A Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 119 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table 108 Instruction set summary Mnemonic Description Bytes Cycles Hex code ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 to 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to 1 1 66 to 67 A XR
142. more bytes within a page to be erased and programmed in a single operation without the need to erase or program any Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 110 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 P89LPC915 916 917 User manual other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 16 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are e FMCON Flash Control Register When read this is the status register When written this is acommand register Note that the status bits are cleared to logic Os when the command is written e FMDATA Flash Data Register Accepts data to be loaded into the page register e FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory The page register consists of 16 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the update flag for that location will be set FMADRL will auto increment to the next lo
143. nably be expected to result in personal injury Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits standard cells and or software described or contained herein in order to improve design and or performance When the product is in full production status Production relevant changes will be communicated via a Customer Product Process Change Notification CPCN Philips Semiconductors assumes no responsibility or liability for the use of any of these products conveys no license or title under any patent copyright or mask work right to these 9397 750 13316 P89LPC915 916 917 User manual products and makes no representations or warranties that these products are free from patent copyright or mask work right infringement unless otherwise specified 20 Licenses Purchase of Philips I2C bus components Purchase of Philips I2 C bus components Sy conveys a license under the Philips ms I2C bus patent to use the components in BUS the I2C bus system provided the system conforms to the C bus specification defined by Koninklijke Philips Electronics N V This specification can be ordered using the code
144. nfigured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt triggered inputs Port 0 also provides various special functions as described below 1 I O P0 1 Port 0 bit 1 CIN2B Comparator 2 positive input B KBI1 Keyboard input 1 AD10 A D channel 1 input 0 P0 2 Port 0 bit 2 CIN2A Comparator 2 positive input A KBI2 Keyboard input 2 AD11 A D channel 1 input 1 P0 3 Port 0 bit 3 CIN1B Comparator 1 positive input B KBI3 Keyboard input 3 AD12 A D channel 1 input 2 P0 4 Port 0 bit 4 CIN1A Comparator 1 positive input A KBI4 Keyboard input 4 AD13 A D channel 1 input 3 DAC1 Digital to analog converter 1 output P0 5 Port 0 bit 5 CMPREF Comparator reference negative input KBI5 Keyboard input 5 9397 750 13316 CLKIN External clock input Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 8 of 125 Philips Semiconductors UM10107 P89LPC915 916 917 User manual Table3 P89LPC916 pin description
145. nklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 103 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual Watchdog PRE2 PRE1 PREO oscillator PCLK WDCLK after a Watchdog feed DECODE Fig 47 Watchdog Prescaler TO WATCHDOG DOWN COUNTER after one prescaler count delay 002aaa938 9397 750 13316 15 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 48 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control register and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow To feed the watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as follows CLR EA disable interrupt MOV WFEED1 0A5h do watch
146. not saved The baud rate is programmable to either 46 or 1 2 of the CCLK frequency as determined by the SMOD1 bit in PCON Mode 3 11 bits are transmitted through TxD or received through RxD a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 62 In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 SFR space The UART SFRs are at the following locations Table 47 UART SFR addresses Register Description SFR location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate Generator Rate High Byte BFH BRGRO Baud Rate Generator Rate Low Byte BEH BRGCON Baud Rate Generator Control BDH Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 61 of 125 Philips Semiconductors U M1 01 07 T
147. o several chip features AUXR1 is described in Table 94 Table 93 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 x 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 108 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 16 1 16 2 P89LPC915 916 917 User manual Table 94 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC915 916 917 as if a hardware reset occurred 4 ENTO When set the P1 2 pin is toggled whenever Timer 0 overflows The output frequency is therefore one half of the Timer 0 overflow rate Refer to the Timer Counters section for details 5 ENTI When set the PO 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to the Timer Counters section for details P89LPC917 6 EBRR UART Break Detect Reset Enable If logic 1 UART Break Detect will cause a chip reset and force the device into ISP mode 7 CLKLP Clock Low Power Select When set
148. ogic 1 after Watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset source that affects these SFRs is power on reset SIOJONPUODIWIAS Sdijiud Jenuew 13SN 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO pe 9LEEL OSZ L6E6 pamasa SIUBU IV POO A N 91U049913 sdiilud afu oy Table 7 P89LPC917 Special function registers indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H ENBI1 ENADCI TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 1 ADINS A D input select ASH ADI13 ADI12 ADI11 ADI10 00 00000000 ADMODA A D mode register A COH BNDI1 BURST1 SCC1 SCAN1 00 00000000 ADMODB A D mode register B A1H CLK2 CLK1 CLKO ENDAC1 BSA1 00 000x0000 AD1BH A D_1 boundary HIGH C4H FF 11111111 register AD1BL A D_1 boundary LOW BCH 00 00000000 register AD1DATO A D_1 data register 0 D5H 00 00000000 AD1DAT1 A D_1 data register 1 D6H 00 00000000 AD1DAT2 A D_1 data register 2 D7H 00 00000000 AD1DAT3 A D 1 data register 3 F5H 00 00000000 A
149. omatic address recognition selectable double buffering and several interrupt options The UART can be operated in four modes as described in the following sections Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 60 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 10 1 10 2 10 3 10 4 10 5 P89LPC915 916 917 User manual Mode 0 Serial data enters and exits through RxD TxD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 1 46 of the CPU clock frequency Mode 1 10 bits are transmitted through TxD or received through RxD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 10 6 Baud Rate generator and selection on page 62 Mode 2 11 bits are transmitted through TxD or received through RxD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is
150. omparators disabled e Real time Clock System Timer unless RTCPD i e PCONA 7 is logic 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wake up options supported e Watchdog timer if WOCLK WDCON 0 is logic 1 Could generate Interrupt or Reset either one can wake up the device e External interrupts INTO INT1 e Keyboard Interrupt e Real time Clock System Timer unless RTCPD i e PCONA 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequency clock when the Real time Clock is running during power down 9397 750 13316 Table 32 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO BOPD BOI GF1 GFO PMOD1 PMODO Reset 0 0 0 0 0 0 0 0 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 49 of 125 Philips Semiconductors U M1 01 07 9
151. on timer overflow has been added In the Timer function the timer is incremented every PCLK Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 52 of 125 Philips Semiconductors U M1 01 07 L P89LPC915 916 917 User manual In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 P89LPC917 The external input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes 2 machine cycles 4 CPU clocks to recognize a 1 to 0 transition the maximum count rate is 14 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs TnM1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating modes
152. oot SPI CONTROL REGISTER SPI internal interrupt 4 data request bus 002aaa497 Fig 37 SPI block diagram The SPI interface has four pins SPICLK MOSI MISO and SS e SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions e SS is the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected The SS is ignored if any of the following conditions are true lf the SPI system is disabled i e SPEN SPCTL 6 0 reset value If the SPI is configured as a master i e MSTR SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits Ifthe SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if P2 4 is configured as input and SSIG 0 Should this happen the SPIF bit SPSTAT 7 will be set see Section
153. ort 2 Port 2 is a 4 bit I O port having user configurable output types During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the P2 input and outputs depends upon the port configuration selected Refer to Section 5 1 for details All pins have Schmitt triggered inputs Port 2 also provides various special functions as described below 6 1 O P2 2 Port 2 bit 2 O MOSI SPI master out slave in When configured as a master this pin is an output When configured as a slave this pin is an input 5 1 O P2 3 Port 2 bit 3 MISO SPI master in slave out When configured as a master this pin is an input When configured as a slave this pin is an output 2 O P2 4 Port 2 bit 4 0 SS SPI Slave select 11 O P2 5 Port 2 bit 5 O SPICLK When configured as a master this pin is an output When configured as a slave this pin is an input Vss 4 Ground 0 V reference Vpo 12 Power Supply This is the power supply voltage for normal operation as well as Idle and Power down modes 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 9 of 125 Philips Semiconductors U M1 01 07 T P89LPC915 916 917 User manual Table 4 P89LPC917 pin description Symbol Pin Type Description P0 0 to P0 5 1 2 11 O Port 0 Port 0 is a 7 bit I O port with user configurable outputs During r
154. orts 0 is a 7 bit port Port 1 is a 6 bit port and Port 2 is a 1 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 26 and Table 27 Table 26 Number of I O pins available P89LPC915 Clock source Reset option Number of I O pins On chip oscillator or watchdog No external reset except during power up 12 oscillator External RST pin supported 11 External clock input No external reset except during power up 11 External RST pin supported 10 Table 27 Number of I O pins available P89LPC916 917 Clock source Reset option Number of I O pins On chip oscillator or watchdog No external reset except during power up 14 oscillator External RST pin supported 13 External clock input No external reset except during power up 13 External RST pin supported 12 Port configurations All but three I O port pins on the P89LPC915 916 917 may be configured by software to one of four types on a pin by pin basis as shown in Table 28 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Table 28 Port output configuration settings PxM1 y PxM2 y Port output mode
155. oth a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will initiate a transfer and therefore collision can occur For receiving data received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character However the received character must be read from the Data Register before the next character has been completely shifted in Otherwise the previous data is lost WCOL can be cleared in software by writing logic 1 to the bit Data mode Clock Phase Bit CPHA allows the user to set the edges for sampling and changing data The Clock Polarity bit CPOL allows the user to set the clock polarity Figures 41 to 44 show the different settings of Clock Phase bit CPHA Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 93 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual Clock cycle 1 i SPICLK CPOL 0 SPICLK CPOL 1 TO LW MOSI input DORD 0 MSB V LSB miso fount oerz A1 Me Ma Me Me Me Muo A SS if SSIG bit 0 002aaa934 1 Not defined Fig 41 SPI slave transfer format with CPHA 0 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights
156. programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC915 916 917 through a two wire serial interface Philips has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vpp Vss P0 5 P0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature Power on reset code execution The P89LPC915 916 917 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC915 916 917 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location OOOOH which is the normal start address of the user s application code When the Boot Status Bit is set to a one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to OOH The factory default settings for these devices are show in Table 97 below A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Table 97 Boot loader address and default Boot vector Product Flash size End Signature bytes Sector Page Default Boot address
157. rase programming cycle will be aborted and the Ol flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the Ol flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps e Write the LOAD command OOH to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 111 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual e Write the address within the page register to FMADRL Since the loading the page register uses FMADRL 3 0 and since the erase program command uses FMADRH and FMADRL 7 4 the user can write the byte location within the page register FMADRL 3 0J and the code memory page address FMADRH and FMADRL 7 4 at this time e Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page regi
158. rdless of PMOD1 0 and BOPD If BOE is in a programmed state PMOD1 0 and BOPD will be used to determine whether Brownout Detect will be disabled or enabled PMOD1 0 is used to select the power reduction mode If PMOD1 0 11 the circuitry for the Brownout Detection is disabled for lowest power consumption BOPD defaults to logic 0 indicating brownout detection is enabled on power on if BOE is programmed If Brownout Detection is enabled the operating voltage range for Vpp is 2 7 V to 3 6 V and the brownout condition occurs when Vpp falls below the Brownout trip voltage Vao see P89LPC915 916 917 data sheet Static characteristics and is negated when Vpp rises above Vego If Brownout Detection is disabled the operating voltage range for Vpp is 2 4 V to 3 6 V If the P89LPC915 916 917 device is to operate with a power supply that can be below 2 7 V BOE should be left in the unprogrammed state so that the device can operate at 2 4 V otherwise continuous brownout reset may prevent the device from operating If Brownout Detect is enabled BOE programmed PMOD1 0 11 BOPD 0 BOF RSTSRC 5 will be set when a brownout is detected regardless of whether a reset or an interrupt is enabled BOF will stay set until it is cleared in software by writing logic 0 to the bit Note that if BOE is unprogrammed BOF is meaningless If BOE is programmed and a initial power on occurs BOF will be set in addition to the power on flag POF RSTSRC
159. re as both the open drain and the quasi bidirectional output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 17 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC915 916 917 data sheet Dynamic characteristics for glitch filter specifications VDD strong port N t t pin input data Aaa glitch rejection 002aaa917 port latch data Fig 17 Push pull output 5 6 Port 0 analog functions The P89LPC915 916 917 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the Input only mode as described in the Port Configurations section see Figure 16 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 45 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 5 7 P89LPC915 916 917 User manual Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins P0 1 through P0 5 of Port 0 respe
160. reserved User manual Rev 01 15 July 2004 94 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual Clock cycle 1 i SPICLK CPOL 0 SPICLK CPOL 1 US LE LU MOSI input DORD 0 MSB V LSB MISO output DORD 1 LSB MSB SS if SSIG bit 0 002aaa935 1 Not defined Fig 42 SPI slave transfer format with CPHA 1 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 95 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual Clock cycle 1 i SPICLK CPOL 0 srow cro n BESSEN n MOSI input DORD 0 MSB LSB DORD 1 LSB MSB l l MISO output SS if SSIG bit 0 l l T 002aaa936 1 Not defined Fig 43 SPI master transfer format with CPHA 0 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 96 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual Clock cycle 1 SPICLK CPOL 0 SPICLK CPOL 1 SUL l MOSI input BSN S L B DORD 1 B SB MISO output
161. rrupts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 256 CPU clocks after start up for the internal RC or external clock input configurations Some chip functions continue to operate and draw power during Power down mode increasing the total power used during power down These include Brownout Detect e Watchdog timer if WOCLK WDCON 0 is logic 1 e Comparators Note Comparators can be powered down separately with PCONA 5 set to logic 1 and c
162. s been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 Table 51 Serial Port Control register SCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO FE SMi SM2 REN TB8 RB8 TI RI Reset xX X x X x X 0 0 Table 52 Serial Port Control register SCON address 98h bit description Bit Symbol Description 0 RI Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 it is set near the middle of the stop bit see SM2 SCON 5 for exceptions Must be cleared by software 1 Tl Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit see description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 5 SM2 Enables the multiprocessor communication feature in Modes 2 and 3 In Mode 2 or 3 if SM2 is set to logic
163. s functions as a reset input An external circuit connected to this pin should not hold this pin low during a Power on sequence as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit Note During a power cycle Vpp must fall below Vpor see P89LPC915 916 917 data sheet Static characteristics before power is reapplied in order to ensure a power on reset Reset can be triggered from the following sources see Figure 18 e External reset pin during power on or if user configured via UCFG1 e Power on Detect e Brownout Detect e Watchdog timer e Software reset e UART break detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a logic 0 to the corresponding bit More than one flag bit may be set e During a power on reset both POF and BOF are set but the other flag bits are cleared e For any other reset any previously set flag bits that have not been cleared will remain set RPE UCFG1 6 RST pin WDTE UCFG1 7 Watchdog timer reset nn J Software reset SRST AUXR1 3 SS oe chip reset Power on detect UART break detect EB
164. s not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data XDATA memory Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 109 of 125 Philips Semiconductors U M1 01 07 P89LPC915 916 917 User manual Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 17 Flash memory 9397 750 13316 17 1 17 2 17 3 17 4 General description The P89LPC915 916 917 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash sector 256 bytes or page 16 bytes The Chip Erase operation will erase the entire program memory Two Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC915 916 917 Flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms The P89LPC915 916 917 uses Vpp as the supply voltage to perform the Program Erase algorithms Features e In Circuit serial Programming ICP with industry
165. s reserved User manual Rev 01 15 July 2004 89 of 125 Philips Semiconductors U M1 01 07 fz P89LPC915 916 917 User manual 12 1 Typical SPI configurations Master Slave fe ee ee 1 EE aa 1 MISO MISO 8 BIT SHIFT HE REGISTER MOSI l MOS SPICLK SPICLK SPICLOCK hooo GENERATOR PORT l Ss 002aaa435 I Fig 38 SPI single master single slave configuration In Figure 38 SSIG SPCTL 7 for the slave is logic 0 and SS is used to select the slave The SPI master can use any port pin including P2 4 SS to drive the SS pin I l Master Slave I r 1 MISO MISO 8 BIT SHIFT 7774 14 REGISTER MOSI l MOS P i SPICLK i SPICLK SPI CLOCK f7 id Dt GENERATOR port SS I I l i l Slave I F 1 I MISO t7 8 BIT SHIFT MOSI _ REGISTER SPICLK pole port SS gt 002aaa437 Fig 39 SPI dual device configuration where either can be a master or a slave 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 90 of 125 Philips Semiconductors UM10107 12 2 P89LPC915 916 917 User manual Figure 39 shows a case where two devices are connected to each other and either device can be a master or a slave When no SPI operation is occurring both can be configured as masters MSTR 1 with SSIG
166. s transmitted ACK will be been received received COH Data byte in No l2DAT 0 0 0 0 Switched to not addressed I2DAT has action or SLA mode no recognition of been own SLA or General call transmitted address NACK has no I2DAT 0 0 0 1 Switched to not addressed been received action or SLA mode Own slave address will be recognized General call address will be recognized if I2ADR O 1 no l2DAT 1 0 0 0 Switched to not addressed action or SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no l2DAT 1 0 0 1 Switched to not addressed action SLA mode Own slave address will be recognized General call address will be recognized if I2ADR O 1 A START condition will be transmitted when the bus becomes free Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 86 of 125 Philips Semiconductors UM10107 Table 72 Slave Transmitter mode P89LPC915 916 917 User manual Status code Status of the I2STAT IC hardware C8H Last data byte in I2DAT has been transmitted A A 0 ACK has been received Application software response Next action taken by I2C to from to I2CON hardware I2DAT ST st si JAA A O No l2DAT 0 0 0 0 Switched to not addressed action or SLA mode no recognition of own SLA or General call address no l2DAT 0 0 0 1 Switched to not addressed action
167. s will not affect WDTOF The only reset source that affects these SFRs is power on reset 2 BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable 3 The RSTSRC register reflects the cause of the P89LPC915 916 917 reset Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset On power on reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register 4 After reset the value is 111001x1 i e PRE 2 0 are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after Watchdog reset and is logic 0 after power on reset Other SIOJONPUODIWIAS Sdijiud Jenuew 19S 216 916 SL69d 168d ZOLOLINN jenuew asn rooz inr SL 10 AeY Gel JO 02 9LEEL OSZ L6E6 penis SIUBU IV 002 A N 91U049913 Sdiliyd afu oy Table 6 indicates SFRs that are bit addressable P89LPC916 Special function registers Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary Bit address E7 E6 E5 E4 E3 E2 E1 E0 ACC Accumulator EOH 00 00000000 ADCON1 A D control register 1 97H ENBI1 ENADCI TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 00 00000000 1 ADINS A D input select ASH ADI13 ADI12 ADI11 ADI10 00 00000000 ADMODA A D mode reg
168. separately write protected These configuration bytes include UCFG1 BOOTVEC and BOOTSTAT This protection applies to IAP Lite mode and does not apply to ICP mode If the Configuration Write Protect Writ CWP bit in BOOTSTAT 6 is a logic 1 writes to the configuration bytes are disabled If the Configuration Write Protect Writ CWP bit in BOOTSTAT 6 is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection function in IAP Lite The Clear Configuration Protection command can be disabled in IAP Lite mode by programming the Disable Clear Configuration Protection DCCP bit in BOOTSTAT 7 to a logic 1 When DCOP is set the CCP command may still be used in ICP programming mode This bit is cleared by writing the Clear Configuration Protection command in ICP mode User configuration bytes A number of user configurable features of the P89LPC915 916 917 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 shown in Table 99 Table 98 Flash User Configuration Byte UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol WDTE RPE BOE WDSE FOSC2 FOSC1 FOSCO Unprogrammed 0 1 1 0 0 0 1 1 value Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 115 of 125
169. smit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written 5 CIDIS Combined Interrupt Disable When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80C51 UART This bit is reset to logic 0 to select combined interrupts 6 INTLO Transmit interrupt position When cleared 0 the Tx interrupt is issued at the beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode When set 1 enables double buffering Must be logic 0 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 64 of 125 Philips Semiconductors U M1 01 07 T P89LPC915 916 917 User manual 10 10 More about UART Mode 0 In Mo
170. ss will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 84 of 125 Philips Semiconductors UM10107 9397 750 13316 P89LPC915 916 917 User manual Table 71 Slave Receiver mode Status code Status ofthe Application software response Next action taken by I2C I2STAT 12C hardware GE to I2CON hardware I2DAT ST sT SI AA A 0O AOH A STOP No I2DAT 0 0 0 0 Switched to not addressed condition or action SLA mode no recognition of repeated own SLA or General call START address condition has ng j2DAT 0 0 0 1 Switched to not addressed been i eceived action SLA mode Own slave while still address will be recognized addressed as General call address will be SLAREC or recognized if I2ADR 0 1 SLA TRX no I2DAT 1 0 0 0 Switched to not addressed action SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT 1 0 0 1 Switched to not a
171. st be set 1 to acknowledge its own slave address or the general call address STA STO and Sl are cleared to 0 After I2ADR and I2CON are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0 W If the direction bit is 1 R it will enter Slave Transmitter mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register l2STAT Refer to Table 72 for the status codes and actions logic 0 write L data transferred _ logic 1 read n Bytes acknowledge A acknowledge SDA LOW TJ from Master to Slave A not acknowledge SDA HIGH S START condition P STOP condition RS repeated START condition 002aaa932 O from Slave to Master Fig 34 Format of Slave Receiver mode Slave Transmitter mode The first byte is received and handled as in the Slave Receiver mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application the 1 C bus may operate as a master and as a slave In the slave mode the 12C hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt
172. ster e Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented All bytes to be programmed must be within the same page e Write the data for the next byte to be programmed to FMDATA e Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 4 if not previously included when writing the page register address to FMADRL 3 0 e Write the erase program command 68H to FMCON starting the erase program cycle e Read FMCON to check status If aborted repeat starting with the LOAD command Table 95 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R J z HVA HVE SV Ol Symbol W FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 Reset 0 0 0 0 0 0 0 0 Table 96 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 Ol R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCMD 1 W Command byte bit 1 2 HVE R High voltage error Set when an error occurs in the high voltage generator FMCMD 2 W Command byte bit 2 3 HVA R
173. th the watchdog timer It can also be a source to wake up the device 9 4 Reset sources affecting the Real time clock Only power on reset will reset the Real time Clock and its associated SFRs to their default state Table 44 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 000 X XX undefined undefined 001 010 011 0 00 External clock input Internal RC oscillator 01 DIVM 10 11 Internal RC oscillator DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator 100 0 00 External clock input Watchdog oscillator 01 DIVM 10 11 Watchdog oscillator DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator 101 x XX undefined undefined 110 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 59 of 125 Philips Semiconductors U M1 01 07 10 UART P89LPC915 916 917 User manual Table 44 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 111 0 00 External clock input External clock input DIVM 01 10 11 External clock input DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator Table 45 Real time Clock Control register RTCCON address D1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCF RTCS1 RTCSO ERTC RTCE
174. tomatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit VART modes mode 2 and mode 3 the Receive Interrupt flag RI will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this
175. tor 2 and six for comparator 1 as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 46 Note Not all combinations are available on all devices When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service Table 79 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CEn CPn CNn OEn COn CMFn Reset x X 0 0 0 0 0 0 Table 80 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This output is asynchronous to the CPU clock 3 _CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input
176. trol register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs The number of watchdog clocks before timing out is calculated by the following equations telks QP PEP WDL 1 1 1 where PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of watchdog load register which can be the range of 0 to 255 The minimum number of tclks is telks 2 04 1 1 33 2 The maximum number of tclks is 5 7 tclks 2 255 1 1 1048577 3 Table 92 shows sample P89LPC915 916 917 timeout values Table 90 Watchdog timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO WDRUN WDTOF WDCLK Reset 1 1 1 X x 1 1 0 1 Table 91 Watchdog timer Control register WDCON address A7h bit description Bit Symbol Description 0 WDCLK Watchdog input clock select When set the watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the watchdog is disabled if WDCLK 0 see Section 15 5 Note If both WDTE and WDSE are set to logic 1 this bit is forced to 1 Refer to Section 15 3 for details 1 WDTOF Watchdog timer Time Out Flag This bit is set when the 8 bit down counter underflows In Watchdog mode a feed sequence will clear this bit It can also be cle
177. ual to the value of KBPATN register to generate the interrupt 2 7 reserved Table 87 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBMASK 7 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 3 KBMASK 2 KBMASK 1 KBMASK O Reset 0 0 0 0 0 0 0 0 Table 88 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol Description KBMASK 0 When set enables P0 0 as a cause of a Keypad Interrupt KBMASK 1 When set enables P0 1 as a cause of a Keypad Interrupt KBMASK 2 When set enables P0 2 as a cause of a Keypad Interrupt KBMASK 3 When set enables P0 3 as a cause of a Keypad Interrupt KBMASK 4 When set enables P0 4 as a cause of a Keypad Interrupt KBMASK 5 When set enables P0 5 as a cause of a Keypad Interrupt KBMASK 6 User should program to 0 KBMASK 7 When set enables P0 7 as a cause of a Keypad Interrupt Ni olal pn win Oo 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 15 Watchdog timer The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset 9397 750 13316 Koninklijke Philips Electronics N V 2004 All rights reserved
178. unction In order to give the best analog performance pins that are being used with the ADC or DAC should have their digital outputs and inputs disabled and have the 5 V tolerance disconnected Digital outputs are disabled by putting the port pins into the Input only mode as described in the Port Configurations section see Table 28 Koninklijke Philips Electronics N V 2004 All rights reserved User manual Rev 01 15 July 2004 35 of 125 Philips Semiconductors U M1 01 07 9397 750 13316 3 7 P89LPC915 916 917 User manual Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and the A D or DAC has been enabled Pins selected in ADINS will be 3 V tolerant provided that the A D is enabled and the device is not in power down otherwise the pin will remain 5 V tolerant Power down and idle mode In idle mode the A D converter if enabled will continue to function and can cause the device to exit idle mode when the conversion is completed if the A D interrupt is enabled In Power down mode or Total power down mode the A D does not function If the A D is enabled it will consume power Power can be reduced by disabling the A D Table 15 A D Control register 1 ADCON1 address 97h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBI1 ENADCI TMM1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 1 Reset 0 0 0 0 0 0 0 0 Table 16 A
179. ware or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator Comparators and power reduction modes Either or both comparators may remain enabled when power down or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode Koninklijke Philips Electronics N V 2004 All rights reserved Us
180. y programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 24 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Interrupt priority structure Table 23 Interrupt priority level Priority bits IPxH IPx Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in IPx and IPXH x 0 1 and can therefore be assigned to one of four levels as shown in Table 23 The P89LPC915 916 917 has two external interrupt inputs in ad

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