RPX Lite (RPXL_CW), Programmer`s Firmware Manual
Contents
1. At Processor Pin Name Defined Function Additional comments Expansion Socket SIZ0 REG SIZO and REG Y BDIP GPLBS5 BDIP Unused Y RSV IRQ2 IRQ2 Unused Y KR RETRY IRQ4 SPKROUT RETRY Unused Y 1 PROTEST Can be redefined for DP 0 3 for an DP1 IRQ4 IRQ 3 6 Expansion Card that requires Parity Y DP2 IRQS Use IRQ7 or one of the Port C pins i for interrupt capability DP3 IRQ6 FRZ IRQ6 FRZ N CS6 CE1B CS6 or CE1B See OP2 below Y CS7 CE2B CS7 or CE2B See OP2 below Y GPLAO UPM Output Enable Y GPLA 1l GPCM Output Enable Y GPLA2 CS2 GPLA2 Only used at I O Expansion Socket Y GPLA3 Unused Y UPWAITA GPLA4 UPWAITA Unused Pulled Down N UPWAITB GPLB4 2 UPWAITB Unused Pulled Down N GPLAS Unused Y ALEB DSCK AT1 ALEB PCMCIA Slot B ALE signal N OP2 MODCK1 STS 2 OP2 PCMCIA Slot B Buffer Enable N 0 Enable Buffers Disable CS6 CS7 at I O Header 1 Disable Buffers Enable CS6 CS7 at I O Header MODCK1 reset rising 0 OP3 MODCK2 DSDO OP3 PCMCIA Slot B Reset Signal N MODCK2 reset rising 0 i Programmed in SIUMCR 2 Programmed in MAMR 3 Hard Reset Configuration and SIUMCR Page 16 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 B PCMCIA Interface Pins The hard reset word configures the following pins to function as PCMCIA signals Table 14 PCMC2. Note OP2 in PGCRB has a dual function in that it either enables the buffers for PCMCIA Slot B or enables the buffers which allow the CS6 and CS7 signals to be active at the I O Header If Bit 24 CBOE 0 then PCMCIA Slot B Buffers Enabled and CS6 CS7 not active at I O Header If Bit 24 CBOE 1 then PCMCIA Slot B Buffers Disabled and CS6 CS7 active at I O Header Page 13 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 E Option Register Mask Table Table 11 OR Mask A 0 12 in OR s F800 0 128MBytes FC00 0 64MBytes FE00 0 32MBytes FF00 0 16MBytes FF80 0 8MBytes FFCO 0 4MBytes FFEO 0 2MBytes FFFO 0 1MByte FFF8 0 512KBytes FFFC 0 256KBytes mmmm m in Table above FFFE 0 128KBytes FFFF 0 64KBytes FFFF 8 32KBytes Page 14 of 20 VI rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Interrupt Structure Table 12 Interrupt Structure for the RPX Lite Entity Interrupt Code Function IRQO 00 Power Fail IRQ1 08 Temperature and Thermal Monitor STTM IRQ2 10 IRQ3 18 Availability depends on configuration On I O Header Fxteimal pin multiplexes IRQ3 with DPARO Interrupt IRQ4
3. including refresh have 1 clock between accesses C 40MHZ Single Beat Read 4 clocks 2 wait states Single Beat Write 4 clocks 2 wait states Burst Read 10 clocks 2 2 2 2 cycle Burst Write 10 clocks 2 2 2 2 cycle Refresh 4 clocks Back to Back Accesses including refresh have 1 clock between accesses D 50MHZ Single Beat Read 5 clocks 3 wait states Single Beat Write 5 clocks 3 wait states Burst Read 11 clocks 3 2 2 2 cycle Burst Write 10 clocks 3 2 2 1 cycle Refresh 5 clocks Back to Back Accesses including refresh have 1 clock between accesses Page 19 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 E 66MHZ Single Beat Read 6 clocks 2 wait states Single Beat Write 6 clocks 2 wait states Burst Read 18 clocks 2 4 4 4 cycle Burst Write 10 clocks 1 2 2 2 cycle Refresh 6 clocks Back to Back Accesses including refresh have 2 clocks between accesses F 81IMHZ Single Beat Read 8 clocks 4 wait states Single Beat Write 8 clocks 4 wait states Burst Read 20 clocks 4 4 4 4 cycle Burst Write 20 clocks 4 4 4 4 cycle Refresh 8 clocks Back to Back Accesses including refresh have 2 clocks between accesses Page 20 of 20
4. 1 1110 R W Register 1 xxx0 0000 R W Register 2 1000 Oxxx RO Register 3 xxxx 11xx UU first four bits dipswitch setting 1 1 NVRAM Battery status RTC Battery Status Table 4 BCSRO Register Byte Number Address Function Bit Mnemonic Definition 0 Disable Transceiver 0 ETHEN 1 Enable Transceiver 0 Disable Transceiver Loop Back Test a oe 1 Enable Transceiver Loop Back Test Control 2 COLTEST 0 Enable collision testing on Transceiver 0 1 Disable collision testing on Transceiver 3 FULLDPLX 0 Enable full duplex mode of operation R W FA40 1 Disable full duplex mode of operation 0000 LEDS LED4 0 LED on reset value 5 LEDS 1 LED off anata 0 Disable on board NVRAM and CS4 6 ENNVRAM Enable CS4 at I O Receptacle Control 1 Enable on board NVRAM and Disable CS4 at I O Receptacle Monitor i l XVCR 7 ENMONXCVR 0 Disable Monitor Port Transceiver Control 1 Enable Monitor Port Transceiver Page 8 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Table 5 BCSR1 pies Pee Function Bit Mnemonic Definition 8 Unused 9 Unused 10 0 BVD2 SPKR signal routed to IPB5 EDS HR 1 INPACK DREQ signal routed to IPB5 Defines VCC_SLOT voltage on PCMCIA Slot B 12 PCVCTL4 GND _ 5 0V_ 3 3V_ GND 0 0 1 1 0 1 0 1 R W PAAU 13
5. 12 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 C System Integration Timers Table 9 TBSCR RTCSC and PISCR Value Bits 0 15 Mnemonic Internal Address Dera value Function TBSCR 200 VVC3 VV User Specified Interrupt Level 00C3 Time Base and Decrementer Enabled but Stopped on FRZ RTCSC 220 VVCI VV User Specified Interrupt Level 00C1 RTC Enabled but not stopped on FRZ PISCR 240 VV83 VV User Specified Interrupt Level 0083 Periodic Timer Enabled but Stopped on FRZ and Periodic Timer Interrupt Disable Note These registers powered by the KAPWR pin Battery Backed Circuits They will only be reset on POR when battery voltage is not available or applied for the first time and the system powers up The RPX Lite requires an external battery for back up operation D PCMCIA Control Registers PCMCIA port A is not implemented on the MPC823 or MPC850 family Table 10 PGCRA and PGCRB Value Bits 0 15 Mnemonic Internal Address Default Value Function PGCRA OEO Reserved not implemented in the MPC850 MPC823 PGCRB OE4 VVLL 0080 VV User Specified Interrupt Level for PCMCIA Card LL User Specified Interrupt Level for Status Change 0000 0080 Internal DMA request disabled Buffers for Card B disabled OP2 deasserted and CS6 CS7 valid at I O Header Reset signal active OP3 asserted
6. 20 Availability depends on configuration On I O Header pin multiplexes IRQ4 with DPAR 1 IRQS 28 Availability depends on configuration On I O Header pin multiplexes IRQ5 with DPAR2 IRQ6 30 Availability depends on configuration On I O Header pin multiplexes IRQ6 with DPAR3 IRQ7 38 From Header NMI From Watchdog Timer or IRQO Level 0 04 Level 1 oC Dn a Routing from interrupt sources below Actual Internal bevels Le pes depended e application Level 4 24 Level 5 2C Level 6 34 Level 7 3C DEC TB SIU PIT Each source is software routed to any Level RIC Each source has unique vector PCMCIA Port C Pins SCC 1 4 Timer 1 4 DMA 32 sources combined into one interrupt CPM RISC Timer which is software routed to any Level I2C Each source has unique vector SPI SMCI SMC2 USB Page 15 of 20 VIL rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Processor Pin Assignments The following sections define the function that is associated with certain processor pins Many of the processor pins have multiple functions most of which are programmable by the FW This section will detail the functionality associated with the respective processor pins and must be used by the firmware software to correctly configure the system A Bus Interface Pins Table 13 Bus Interface Multiple Function Pins
7. 999 2000 I Overview The RPX Lite is a highly integrated SBC based on the Motorola MPC850 and MPC823 The MPC850 versions are targeted for the tel com industries while the MPC823 version is targeted for the industrial controls market Support is available for several commonly used RTOSs The functions included on the RPX Lite that are related to FW are listed as follows Table 1 Overview of FW Related Functions Entity Function Processor MPC850 SR DC DH etc or MPC823 DRAM 4MB or 16MB FLASH 2MB 4MB 8MB or 16MB NVRAM OKB 32KB 128KB 512KB 10Base T Ethernet SCC2 Monitor Port SMCI Serial EEPROM we Serial Temp amp Thermal Monitor I2C BCSR BCSRO 1 2 and 3 The PCMCIA Port and the USB Port are supported in hardware but it is the responsibility of the end user to develop the driver application required for any given PCMCIA card or USB peripheral Support for some PCMCIA Cards such as ATA will occur at a later date A future release of the RPX Utility Program will support testing of the PCMCIA and USB hardware Expansion Boards will be supported as they are designed T1 E1 xDSL Video etc For Hardware Setup information see the RPX Lite User s Manual Page 4 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 II Chip Select Mapping Table 2 Chip Select Ma
8. D25 D 2427 defines DipSwitch Settings SW 26 D26 D24 is MSb D27 is LSb 3 D24 position 0 on switch 27 D27 R only 28 RPXL Reserved reads back 1 TEA FA40 Flash 29 RDY BSY 0 Flash operation executing and busy 0003 1 Flash operation complete 1 0 NVRAM Battery is low dae Nvram 30 BWNVR 1 NVRAM Battery is good or no NVRAM installed xxxx 11xx 0 Real Time Clock Battery is low or RTC 31 BWRTC H no External Battery is attached 1 Real Time Clock Battery is good Page 10 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 V RC Devices Addressing The board contains two devices on the I2C bus These two devices are a Serial EEPROM SEP and a Serial Temperature amp Thermal Monitor STTM The I2C bus also routes to the Expansion Header for possible use on Expansion board designs The LC interface pin SDA from the processor must be programmed as open drain The I2C interface pin SCL from the processor does not necessarily have to be programmed as an open drain signal because presently there are no other master I2C devices that reside on the I2C bus If a master I2C device where designed onto an expansion card then the SCL signal must also be programmed for open drain operation The RPX Lite board sets both I2C signals to open drain operation Table 8 RC Address Map Device Function 12C Addressing SEP Configura
9. IA Multiple Function Pins Processor Pin PCMCIA ae a Name Econ Additional comments Expansion Socket IPBO VSI IPB1 VS2 IPB2 WP or IOCS 16 or DREQ Function depends on memory or I O Card IPB3 CD2 IPB4 CD1 IPB5 BVD1 or SPKR or DREQ Function depends on memory or I O Card see Note 1 IPB6 BVD2 or STSCHG Function depends on memory or I O Card No IPB7 RDY or IRQ Function depends on memory or I O Card WAITB Wait States OP3 Reset Signal OP2 Buffer Enable Disable Used to enable or disable the on board Control buffers that isolate the PCMCIA bus from the Processor bus amp In addition this signal also enables or disables CS6 CS7 chip selects 6 and 7 from the I O Header When Enable Disable the Buffers are enabled CS6 and CS7 are Control disabled When the Buffers are disabled CS6 and CS7 are enabled Note 1 The PCMCIA signal INPACK is not required by the MPC8XX and as such not supported Some PCMCIA type DMA cards route the DREQ signal on the INPACK pin To support these cards Control Register 2 bit 19 allows routing of the INPACK DREQ signal to IPBS Note 2 BCSRI1 bits 12 15 also controls the operation of the PCMCIA interface voltages to socket Page 17 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 C I O Port Interface Pins Refer to the pinouts document for pinout a
10. PCVCTL5 reset value 0001 xxx0 0000 PC Slot B Defines VPP_SLOT voltage on Control PCMCIA Slot B 14 PCVCTL6 GND Note1 Note2 HI Z 0 0 1 1 0 1 0 1 Note 1 Hi Z if VCC_SLOT GND else 12 0V Note 2 Hi Z if VCC_SLOT GND else VCC_SLOT Voltage 15 PCVCTL7 Page 9 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Table 6 BCSR2 Register Byte ee Number dies Function Bit Mnemonic Definition 0 Enable USB Transceiver 1 PRERUSA 1 Disable USB Transceiver 0 Low Speed 6MHZ USB clock sl USESED 1 High Speed 48MHZ USB clock 2 USB 0 Disable 5 0V power to USB connector 18 USBPWREN 1 Enable 5 0V power to USB connector R W Control r DA FA40 do not enable if 3V power option is used 0002 0 Disable USB clock to PAS a VLE 19 ENUSBCLK _ Enable USB clock to PAS al 0 Disable PAS at P2 Receptacle 1000 0 de a0 ee 1 Enable PAS at P2 Receptacle 21 Unused 22 Unused 23 Note The USB clock can be fed to both PAS and the P2 Receptacle The USB clock is currently set for 6MHZ and 48MHZ Via special this USB Clock can be set to any realizable frequency as provided for by the on board CY2071A clock synthesizer Table 7 BCSR3 Register Byte A TE Nabe Adie Function Bit Mnemonic Definition 24 D24 75
11. Processor Pin Assignments 00000 e eee eee 16 A Bus Interface Pins sesser A 16 B PCMCIA Interface Pins vesical 17 C T O Port Interface Pins secar lada 18 VI Performances oven ceo tiue toed ae e E E EEE 19 A 20 AAA Hole Re Ae aoe EE 19 B A cate ad E E R adhe 19 Page 1 of 20 moo 40MHZ 50MHZ 66MHZ 81IMHZ rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Page 2 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 List of Tables Overview of FW Related Functions 0 0 cece eee eee eee 4 Chip Select Mapp ING ul A eave etd aes 5 Code Location 1x32 FLASH a a pose diene Seon Gta aS iea wore 6 BCSRO sus ER A A eon A eee eae es 8 BESA A A ean awe Pats 9 GS TA a A eR Re eR et Ls To 10 BCSRS e pe a AAS ee RYE ee AA e 10 126 Address Map A AS aes AT A ae ew ae eee 11 TBSCR RICSC and PISCR cis da e ER aoe ado 13 PGCRA and POCRB iS amp ORS AWRY MAAS S PAS SA 13 OR Mask costuras beige tebe ric hades serio EE ba AS 14 Interrupt Structure for the RPX Lite o oooooocooomoomoomoom 15 Bus Interface Multiple Function Pins 0 0 0 eee eee eee 16 PCMCIA Multiple Function Pins 0 0 0 eee eee eee 17 Page 3 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1
12. SP or RTOS FLASH intensive RTOSs will require a larger block of memory Table 3 Code Location in x32 FLASH FLASH Memory Option Address Block 2MByte 4MBytes 8MBytes 16MBytes Range Size 29LV400 29LV800 29LV 160 29LV320 FFFF FFFF FEF8 0000 512KB User User User User FFF7 FFFF FFFO 0000 512KB BSP BSP BSP BSP FFEF FFFF FFE8 0000 512KB FFE7 FFFF FFEO 0000 512KB FEDF FFFF FFD8 0000 512KB FFD7 FFFF FFDO 0000 512KB FFCF FFFF FFC8 0000 512KB FFC7 FFFF FFCO 0000 512KB FFBF FFFF FFB8 0000 512KB FFB7 FFFF FFBO 0000 512KB FFAF FFFF FFA8 0000 512KB FFA7 FFFF FFAO 0000 512KB FF9F FFFF FF98 0000 512KB FF97 FFFF FF90 0000 512KB FF8F FFFF FF88 0000 512KB FF87 FFFF FF80 0000 512KB FF7F FFFF FF78 0000 512KB FF77 FFFF FF70 0000 512KB FF6F FFFF FF68 0000 512KB FF67 FFFF FF60 0000 512KB FF5F FFFF FF58 0000 512KB FF57 FFFF FF50 0000 512KB FF4F FFFF FF48 0000 512KB FF47 FFFF FF40 0000 512KB FF3F FFFF FF38 0000 512KB FF37 FFFF FF30 0000 512KB FF2F FFFF FF28 0000 512KB FF27 FFFF FF20 0000 512KB FFIF FFFF FF18 0000 512KB FF17 FFFF FF10 0000 512KB FFOF FFFF FF08 0000 512KB FF07 FFFF FFOO 0000 512KB Page 6 of 20 D 2 3 rpxl_fw_cw_basic fm Pr
13. ogrammer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Reset vector FFFO 0100 but for A 0 3 4 7 8 11 A 0 10 X for 2MBytes A 0 9 X for 4MBytes A 0 8 X for 8MBytes A 0 7 X for 16MBytes where X don t care i e the address lines defined by X are not connected to the FLASH memory The actual on board FLASH memory size is mirrored throughout the entire address space excluding internal processor address spaces until ORO is written Flash base address is remapped to FE00 0000 when BRO ORO is written Page 7 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 IV Board Status and Control Registers BSCRs There exists on board control and status registers These registers are configured as a x32 port and can be accessed via byte word or longword The registers are defined as shown in the Table below All registers are read modify write capable except register 3 which is read only Upon power up HRESET the default value configured in the registers after masking anding with FF 1F F8 FF is longword 3E 00 80 UU i e if the first access to the BCSR after reset is a longword read the value read after masking with FF 1F F8 FF will be 3E 00 80 UU where UU is as defined below Register values at reset values in binary and x undefined or determined by function R W Register 0 001
14. pping Chip Select Port Function Corne Number Size Address CSOH x32 FLASH x32 Reset Vector IP 0 FFFO 0000 FE0O Vector set at IP 0 in hardware BRO set at FEOO CS1 x32 DRAM x32 4 or 16MBytes 0000 CS2 Expansion Header Routed to Expansion Receptacle UUUU CS3 x32 Control amp Status Registers Byte and or word accessible FA40 CS4 x8 NVRAM or SRAM OK 32K 128K or 512KBytes Also available at Expansion Receptacle FA00 CS5 Expansion Header Routed to Expansion Receptacle UUUU CS6 x16 PCMCIA Slot B Chip Select Even Bytes 1 OP2 in MPC850 PCMCIA Control or or Register selects mode U Chip Select 6 to I O Header L PCMCIA Slot B enabled UUUU H CS6 to Expansion Header Enabled CS7 x16 PCMCIA Slot B Chip Select Odd Bytes 1 OP2 in MPC850 PCMCIA Control or or Register selects mode U Chip Select 7 to I O Header L PCMCIA Slot B enabled UUUU H CS7 to I O Expansion Header Enabled IMMR x32 Value at reset FFOO 0000 then set to FA20 0000 Address maps are recommended values for the RPX Lite but other mappings can be utilized for any given application U User or Application Defined Page 5 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 III BSP Code Location At start up the code for the RPX Lite is always located in the second to highest 512K block of memory This 512K block of memory is reserved for the B
15. rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 Embedded Planet LLC 3Jan00 RPX Lite Programmer s FW Manual For Rev CW boards Programming and FW Requirements for the RPXL This document contains confidential information and is intended for the sole purpose of the end user to develop applications on the RPX Lite product offered by Embedded Planet Neither the document nor reproductions of it nor information derived from it is to be given to others nor used for any other purpose other than for RPX Lite applications No use is to be made of it which is or may be injurious to Embedded Planet and no use is to be made of it other than for RPX Lite applications Revision Control 15SEP99 First Release Table of Contents I OVV EW ois a wise Pa ae Mee Se eee WS a ees 4 IH Chip Select Mapping ss isidro coe eseas 5 MHI BSP Code Locas cara ev tee ke ees 6 IV Board Status and Control Registers BSCRs 8 V IDC Devices Addressin vicawe e s eevee toad der vere Seeds 11 A SEP Format Interface Structure c ciVinicacaran ara 11 B STTM Format Interface Structure o o o ooooooooooooo 12 C System Integration Timers oooooooooococoro re 13 D PCMCIA Control Registers s ccpncepdveengesdeante lt ades 13 E Option Register Mask Table 22 22 0c2c0secnieensesecas us 14 VI Interrupt Structure epi secede edde wad cetew ses 15 VII
16. ssignments 3 Any of the port signals that are used for on board functions can be used on an Expansion Card if the respective on board function is disabled via the BCSRs 4 Port C pins can also be defined as interrupt signals to the processor core Each Port C pin that is configured as an interrupt pin has a unique vector associated with it and each pin can be defined as edge or low level active This allows Expansion Cards to use Port C pins as interrupt lines to the processor if needed Check the P1_P2 x1s spreadsheet for available Port C pins and also see note 3 above 5 The I2C bus PB26 and PB27 pins is used on board but also routed to the I O Header See the I2C section above for used I2C addresses Page 18 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 VIII Performance See Clocks and Reset Registers section for the exact frequency that processor is running at A 20 or 25MHZ Single Beat Read 3 clocks 1 wait states Single Beat Write 2 clocks 0 wait states Burst Read 7 clocks 1 1 2 1 cycle Burst Write 5 clocks 0 1 1 1 cycle Refresh 2 clocks Back to Back Accesses including refresh have 1 clock between accesses B 33MHZ Single Beat Read 3 clocks 1 wait states Single Beat Write 3 clocks 1 wait states Burst Read 9 clocks 1 2 2 2 cycle Burst Write 5 clocks 0 1 1 1 cycle Refresh 3 clocks Back to Back Accesses
17. tion Information A8h A9h for 1K 2K devices 128 256 x 8 A8h ABh for 4K device 512 x 8 A8h AFh for 8K device 1K x 8 STTM Serial Temperature and Thermal Monitor 90h 91h 8 bytes in device A SEP Format Interface Structure Data is stored in the EEPROM device as a series of ASCII records Each record is terminated with the NEWLINE character ASCII hex 0x0A and the last record is terminated with two NEWLINE characters All data bytes after the double NEWLINE of the last record have the binary value OxFF Each record consists of a name and a value which are separated by an character A name identifies the meaning of the value which follows it For example the record HZ 50 declares the system frequency in MHZ to be 50 For more information on the names used in records please read the section or appendix on EEPROM data formats in the RPX Utility Software Manual Page 11 of 20 rpxl_fw_cw_basic fm Programmer s FW Manual Proprietary and Confidential All Rights Reserved 1998 1999 2000 B STTM Format Interface Structure The driver for the STTM sets the interrupt out for low true operation Interrupt mode is selected but is not enabled at the processor IRQ1 The driver returns the temperature of the device and also a calibrated temperature for reporting ambient air temperature The calibration parameter is programmed into the SEP and is used to extrapolate ambient air temperature Page
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