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TDA5150 Data Sheet

1. infin eon TDA5150 Applications Table 5 Bill of Materials Infineon Evaluation Board V2 Position ID Value Package Tol Type Manufacturer Notes 1 C1 see Table 6 0603 Table 6 Johanson Technology 2 C2 see Table 6 0603 Table 6 Johanson Technology 3 C3 see Table 6 0603 Table 6 Johanson Technology 4 C4 100 pF 0603 20 Johanson Technology 5 C5 100 nF 0603 20 6 C6 8 2pF 0603 see crystal manufacturer specifications for load capacitor value 7 C7 100 nF 0603 20 8 C8 100 nF 0603 20 9 C9 10 uF 0603 20 not placed 10 C10 notch filter value depends on harmonics order not placed 11 C11 100 pF 0603 20 not placed 12 D1 BAS40 06 SOT 23 Low High band switch Infineon Technologies not placed 13 IC1 TDA5150 10 pin Tx chip Infineon Technologies TSSOP 14 IC2 25AA04A 6 pin SPI 4Kbit Microchip Ltd SOT23 EEPROM 15 JP1 jumper 100 mil 16 JP2 jumper 100 mil 17 JP3 jumper 100 mil 18 L1 see Table 6 0603 Table 6 0603CS Coilcraft 19 L2 see Table 6 0603 Table 6 0603CS Coilcraft 20 L3 0603 notch filter value depends on harmonics order not placed 21 Q1 13 000 MHz TSS 5032 10 ppm EXSO00A NDK model ID 1 recommended CS01623 NX5032SD for 13 MHz value 2 NDK specification nmb 22 R1 0603 not placed used only for system tests 23 R2 560 Ohm 0603 10 not placed 24 R3 OR 0603 25 R4 0603 not placed 26 R5 OR 0603 27 R6 0603 not placed 28 R7 OR 0603 29 SV c
2. ADDR 0x07 BDRDIV Bit rate Divider Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV w 1 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Bit lt 7 0 gt BDRDIV BDRDIV divider bit lt 7 0 gt 2 4 6 Sigma Delta fractional N PLL Block The Sigma Delta fractional N PLL contained on chip is the key piece for the transmitter s RF functionality The advantage of a fractional N PLL is that not only integer multiples of the crystal frequencies can be generated N fxra but also values of N multiples plus a fractional part yielding significantly more freedom in terms of reference frequency choice Part of the PLL is a VCO Voltage Controlled Oscillator operating at a center frequency of around 1 8 GHz The VCO frequency is divided at first by 2 in a prescaler block with fixed division ratio It is then further either divided by 1 2 or 3 in the band select divider block the resulting frequency at this block s output equaling the transmitter s RF operating frequency Data Sheet 34 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description This RF signal is then further divided by a multimodulus divider block down to a frequency which is in same range as that of the reference signal s This last is input from the reference oscillator i e generated by the crystal oscillator block The reference oscillator s frequency and the VCO s sub
3. ADDR 0x1B POWCFG1 PA Output Power Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POUT2 POUT2 POUT2 POUT2 POUT1 POUT1 POUT1 POUT1 w 0 wi wl w O wl wl wl w 0 Bit lt 7 4 gt POUT2 Output power setting 2 bit lt 3 0 gt Bit lt 3 0 gt POUT1 Output power setting 1 bit lt 3 0 gt POUT2 PA output power setting 2 4 bits defines the number of enabled PA stages Range from 0x0 POUT2 0 to OxB POUT2 11 gt 0xB POUT2 11 DOUT PA output power setting 1 4 bits defines the number of enabled PA stages Range from 0x0 POUT1 0 to OxB POUT1 11 gt 0xB POUT1 11 Data Sheet 78 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x1C FDEV Frequency Deviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FDEVSCALE FDEVSCALE FDEVSCALE FDEV FDEV FDEV FDEV FDEV w 1 w 1 wl w 1 w 1 w 1 w 1 w 1 Bit 7 5 FDEVSCALE Frequency deviation scaling bit 2 07 Bit 4 0 FDEV Frequency deviation bit 4 07 FDEVSCALE Scaling of the frequency deviation 3 bits 000 001 010 011 divide by 64 divide by 32 divide by 16 divide by 8 100 101 110 111 divide by 4 divide by 2 divide by 1 multiply by2 FDEVSCALE lue alue 64 FDEV Frequency deviation value 5 bits defines the multiplication value for the output data from the
4. PLLBWTRIM kHz 150 175 230 270 335 1375 410 CPTRIM pA 5 7 5 12 5 17 5 25 32 5 40 Data Sheet 84 V 1 1 June 2012 Cinfineon ae TDA5150 Functional Description ADDR 0x26 RES3 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O reserved reserved reserved reserved reserved reserved reserved reserved w 1 w 1 w 0 w 0 w 0 w 0 w 0 w 0 Bit lt 7 0 gt reserved Reserved set bits lt 7 6 gt to 1 and bits lt 5 0 gt to 0 ADDR 0x27 ENCCNT Encoding start bit counter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Bit lt 7 0 gt ENCCNT Encoding start bit counter bit lt 7 0 gt ENCCNT Sets the number of bits on start of a telegram which shall be sent unencoded or unscrambled before encoder scrambler is switched on This feature is used e g to be able to send unscrambled synchronization patterns first Data Sheet 85 V 1 1 June 2012 Cinfineon TDA5150 3 Applications In this chapter 3 application examples are listed The first one is a basic version demonstrating in terms of simplicity the advantages of transmitter systems built around the TDA5150 The second and third examples are the more elaborate Evaluation Board versions V2 and V1 1 allowing a higher degree of fl
5. Data Sheet 36 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 6 4 PLL Dividers RF Carrier Frequency The divider chain contains a fixed divider by 2 prescaler a band select divider dividing by 1 for the 915 and 868 MHz bands by 2 for the 434 MHz band and by 3 for the 315 MHz band The divider ratio of this block is controlled by the field SMBO 1 of SFR TXCFGO0 0x04 3 2 This band selection block is followed by the Multi Modulus Divider which is controlled by the Sigma Delta Modulator The RF frequency is set in the PLL Integer and PLL Fractional SFRs Up to 4 different frequencies may be preconfigured in the same band Frequency Registers A B C D and finally the active channel selected through the Transmit Command This allows fast channel switching or hopping without the need of downloading the complete reconfiguration data content into the corresponding SFRs i e the new PLL settings The RF frequency fpr is derived from the crystal frequency fnr fxosc PLLINT lt 6 0 gt PELERACS MUT eT 2 5 2 us For the 315 MHz and 433 MHz bands ISMB lt 1 gt 0 PLLINT bit 6 is not used and only values from 15 to 43 are valid For the 868 MHz and 915 MHz bands ISMB lt 1 gt 1 all PLLINT bits are used and values between 54 and 84 are valid 2 4 6 5 SFRs related to Sigma Delta fractional N PLL Block ADDR 0x04 TXCFG0 Transmitter Configuration Register
6. 2 TDA5150 Functional Description 2 1 PIN Configuration Pin out EN H 100 SDIO DATA XTAL 2 9 SCK TDA 5150 GND 13 8 CLKOUT VREG 4 70 GNDPA VBAT 15 6j PAOUT 2 2 Pin Definition and Pin Functionality Pin Name Pin Equivalent 1 0 Schematic Function No Type 1 EN Digital Enable 3 wire bus Input MESE EE e EE f F 250k GNDD GNDD 2 XTAL Analog Crystal Oscillator Input VREG La LN t 0 9Vde KH leo0 t XGND SS NM Bypass N Dr ao wu XGND Data Sheet 12 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description Pin Name Pin Equivalent 1 0 Schematic Function No Type 3 GND Supply Power supply XGND 4 o ground 4 gt A GND 4 GNDD Triple bond 4 VREG Analog Voltage Regulator Output output VBAT gt 1 Oo cm erred i i GNDD VREG VREG u Ge Double bond pl E GNDD VDDA Ze E GNDA 5 VBAT Supply Power supply VBAT Oo perd VREG HB m Oo Data Sheet 13 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description Pin Name Pin Equivalent 1 0 Schematic Function No Type 6 PAOUT RF PA RF Power Output Amplifier Output open drain PAOUT ET n cf GNDPA GNDPA 7 GNDPA Analog
7. Figure 13 Bit Rate Divider In Asynchronous Transmission Mode the bitrate clock can be routed to CLKOUT pin and used by the uC as timer signal for bitrate generation In Synchronous Transmission Mode the bitrate clock is in addition used internally for synchronization of the incoming bitstream The bitrate or chiprate is calculated according to the formula fxosc bitrate DRESCALE x BDRDIV 1 x 2x AFTERSCALE Data Sheet 32 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 5 2 The Clock Output The TDA5150 offers a clock output signal CLKOUT derived from the crystal frequency It can be used as source for system clock of a uC or as bit chip clock to control the data rate as already described Different stages of the bit rate divider can be routed to CLKOUT as well as the output of the XTAL 16 divider according to following rules f SDIO 0 when EN goes High the output clock chosen as XTAL 16 by default If SDIO 1 when EN goes High the output clock is selected as imposed by settings of SFR CLKOUTCFG 0x06 This is the configurator register for Clock pre and afterscaler Detailed description of the bit fields is given in next Chapter 2 4 5 3 SFRs related to Crystal Oscillator and Clock Divide If enabled the CLKOUT starts toggling when the swing amplitude on crystal oscillator output reaches a certain threshold This small delay is related to the oscillator startup time
8. AP SDIO D Figure 11 PRBS9 Generator and Data Scrambler Data Sheet 28 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description The feedback branches within the PRBS9 generator are fixed as shown above but the PRBS generation can be influenced by SFR configuration in the following manner Astart value for the PRBS9 Generator can be programmed in SFR PRBS Start Value 0x08 The reset value is OxAB 10101011 Choice of 0x00 as start value is not allowed because the output of PRBS9 Generator should lock and will never go to High The PRBS Start Value is loaded into the PRBS9 Generator at the start of each transmission e If the Data Scrambler is used the start of scrambling can be configured in SFR ENCONT 0x27 If ENCCNT is 0 already the first bit is XOR ed with PRBS9 If for example ENCCNT 0x10 the first 16 bits stay unscrambled This is necessary if a data frame should have always the same wake up and synchronization part but the payload should be pseudo random for sensitivity measurements or to enhance the clock recovery on the receiver side Data Sheet 29 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description 2 4 4 2 SFRs related to Transmitter Configuratio
9. 8 V PA PS bit2 stage 11 1 PA PS bit1 stage 10 PA PS bitO stages 9 1 PAout 40 PA amp SLOPDIV Kl ASK Sloping control W E from SDPLL PA PS bt2 Figure 17 PA Core with Output Power Control Data Sheet 44 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description Two independent PA power level settings can be configured With the Transmit Command the PA power level is selected together with the modulation setting This means either power level 1 AND modulation type 1 or power level 2 AND modulation type 2 are selected according to Modulation Setting 1 or Modulation Setting 2 field in the Transmit Configuration byte The 3 PA Blocks are enabled by PA PS1 and PA PS2 bits within SFR POWCFGO 0x1A The bits PA PS1 do enable the PA blocks for power level 1 and bits PA PS2 are used for power level 2 Enabling the 3 PA Blocks offers following typical PA ranges note that the PA output power depends also on the external matching circuit at a quite large extent PA PS bit0 1 5 dBm matched Pout 5 dBm down to 10 dBm 9 PA Stages PA_PS biti 1 8 dBm matched Pout 8 dBm down to 10 dBm 10 PA Stages PA PG bit2 1 10 dBm matched Pout 10 dBm down to 10 dBm 11 PA Stages In addition to enabling the PA Blocks the 11 PA stages have to be configured This is achieved by setting the bit fields
10. Table 3 SFR Register List Register Name Register Description Address SPICHKSUM SPI Checksum register 0x00 TXSTAT Transmitter status register 0x01 TXCFGO Transmitter configuration register 0 0x04 TXCFG1 Transmitter configuration register 1 0x05 CLKOUTCFG Clock pre and after scaler 0x06 BDRDIV BDRDIV divider 0x07 PRBS PRBS start value 0x08 PLLINTA PLL MM integer value Channel A 0x09 PLLFRACAO PLL fractional division ratio Channel A byte 0 0x0A Data Sheet 62 V 1 1 June 2012 infineon TDA5150 TDA5150 Functional Description PLLFRACA1 PLL fractional division ratio Channel A byte 1 0x0B PLLFRACA2 PLL fractional division ratio Channel A byte 2 0x0C PLLINTB PLL MM integer value Channel B 0x0D PLLFRACBO PLL fractional division ratio Channel B byte 0 OxOE PLLFRACB1 PLL fractional division ratio Channel B byte 1 OxOF PLLFRACB2 PLL fractional division ratio Channel B byte 2 0x10 PLLINTC PLL MM integer value Channel C 0x11 PLLFRACCO PLL fractional division ratio Channel C byte 0 0x12 PLLFRACC1 PLL fractional division ratio Channel C byte 1 0x13 PLLFRACC2 PLL fractional division ratio Channel C byte 2 0x14 PLLINTD PLL MM integer value Channel D 0x15 PLLFRACDO PLL fractional division ratio Channel D byte 0 0x16 P
11. 62 Digital Control SFR Registers 62 SFR Register LISE 324 eek EE ena a ohne er due 62 SFR Detailed Descriptions 66 Applications crece EELER rto goa ETS RUE S 86 Simple application schematics example 86 Infineon Evaluation Board V2 87 Infineon Evaluation board V1 1 95 Electrical Characteristics 104 Absolute Maximum Ratings 104 Operating Range 22 cuo s eo D Eie n LL RC eens 105 AC DC Characteristics 106 SPI Characteristics 2238284 veka eas aduer ae tee eed Rr E Fa dor 111 Package Outline 114 5 V1 1 June 2012 Cinfineon Water Product Description 1 Product Description 1 1 Overview The TDA5150 is a low cost multi channel ASK FSK GFSK RF transmitter for the 300 320 MHz 433 450 MHz 863 928 MHz frequency bands with low power consumption and programmable RF output power of up to 10 dBm Radio systems built around this transmitter are easy to be designed and to be implemented The IC offers a high level of integration and needs only a few external components such as a crystal blocking capacitors and the necessary matching elements between the power amplifier output and the antenna An integrated high r
12. 64 Afrr fyosc a L 2 0 5 Note that the FSK deviation is referenced to the center frequency This means that the spacing between the two FSK frequencies is twice the FSK deviation The pulse shaping Gaussian Filter used for GFSK can be disabled if regular FSK is used In ASK mode the filter is always switched off For ASK mode a power sloping mechanism is available and described in detail in Chapter 2 4 8 Power Amplifier ASK Modulator Data Sheet 40 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description The Gaussian shaping is defined as a number of fixed frequency steps transitions between the 2 FSK frequencies corresponding to Low and High or 0 and 1 on the modulator input It is understood that the steps are counted over one edge of the data chip Ideally these 16 steps are distributed over the complete data chip length which means there are 16 gaussian filter steps per chip or Nae 16 Selecting Nor gt 16 will reduce the shaping effect and selecting Noe lt 16 will cause a reduction of signal information with minimal positive effect on the obtained RF spectrum meer eneen p hoe ree 6 d rs esse Geer eee nn Ke Site Data chip 16 steps chip 25 steps chip 11 steps chip ideal gaussian Figure 15 Influence of the Gaussian Divider on Data Shaping The content of GFDIV is calculated as follows xosc FDIV S chiprate x Non 1 It is recommended to program the GFDIV r
13. Attention There should be no more than 4 consecutive channel hops without VCO Auto Calibration during transmissions If bit B of the Transmit Command is set the RF power amplifier will stay active until the time out condition is reached i e for a duration of 65536 f corresponding to 5 ms for a 13 MHz reference clock Data Sheet 61 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description 2 4 11 4 SFRs related to Channel Hopping ADDR 0x1E GFXOSC Gaussian Filter Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FHBLANK reserved reserved reserved GFBYP GFDIV GFDIV GFDIV wi w 1 w 1 w 1 w 1 w 0 wi w 0 Bit 7 FHBLANK Frequency Hopping VAC Disable FHBLANK Frequency Hopping enable disable VCO Auto Calibration for Channel Hopping 0 enable VCO Auto Calibration 1 Skip VCO Auto Calibration for default frequency hops lt 1 MHz 2 5 Digital Control SFR Registers 2 5 1 SFR Register List The SFRs Special Function Registers are used to configure TDA5150 and to read out certain information e g the transmitter status There are complete GERS as well as register bits in SFRs called Reserved These SFRs and register bits used in the production process The SFRs and bits have to be configured with their default value as shown in the Chapter 2 5 2 SFR Detailed Descriptions
14. Moar IN Voltage digital 0 3 input pins Data Sheet 104 V 1 1 June 2012 Cinfineon TDA5150 Electrical Characteristics Parameter Symbol Values Unit Note min max Test Condition A10 Maximum Current Jess 4 mA Note 1 into digital input and output pins A11 Maximum Input VinxtaL 70 3 VREG Note 2 Voltage XTAL pin 0 3 pin 2 Attention It is not allowed to apply higher voltages than specified by A9 even if the current is limited to values below threshold listed in line A10 The voltage limiting effect of the internal ESD structures shall not be used as level shifter by interconnection s to digital logic with higher output voltage Note VE is the output voltage of the internal voltage regulator accessible on pin 4 designated as VREG 4 2 Operating Range Table 10 Supply Voltage Operating Range and Temperature Operating Range Parameter Symbol Values Unit Note min typ max Test Condition B1 Supply Voltage Veat 19 l 36 JV 40 85 C B2 Operating Tamb 40 l 85 C Temperature Data Sheet 105 V 1 1 June 2012 Cinfineon nid Electrical Characteristics 4 2 1 ACIDC Characteristics Supply voltage Vaar 1 9 V 3 6 V Ambient temperature T 40 85 C unless otherwise specified Maximum 10 pF capacitive load at CLKOUT pin 8 Clock frequency on CLKO
15. gt 4 OO aN Wd PAS VA ere We la y Applications MIDAS N50 D I ef Infineon Evaluation Board V1 1 copper layer on top side 97 V 1 1 June 2012 Cinfineon e Applications Figure 32 Infineon Evaluation Board V1 1 top side solder mask Data Sheet 98 V 1 1 June 2012 Infineon ZE Applications Figure 33 Infineon Evaluation Board V1 1 copper layer on bottom side Data Sheet 99 V 1 1 June 2012 Cinfineon e Applications Figure 34 Infineon Evaluation Board V1 1 bottom side solder mask Data Sheet 100 V 1 1 June 2012 WEE en e TDA5150 Infineon Applications DOOR t MOOS X dia 0 4mm 2P B FOOL IT II III P it dia 0 8mm 4 4 4 4 4 x X dia 1 0mm x Rd a 0M ao x x E Eum GEN x X A X amp dia 3 2mm A web ES a d x pq d xl X x i x LN mem W x x HB D xX MXM mp ei DIDI XIX M nx Cy Dia f x RR xx X x D d X x A 5 x x i pa M X E P x x xl x x MS 2 xq qx xw ow Figure 35 Infineon Evaluation Board V1 1 drill map and tool list Data Sheet 101 V 1 1 June 2012 Infineon TERI Applications Table 7 Bill of Materials Infineon Evaluation Board V1 1 Position ID Value Package Tol Type Manufacturer Notes 1 C1 see Table 8 0603 Table
16. Data Sheet 17 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description The data encoder synchronizes the bitstream to be transmitted with the internal bit clock It supports different types of Manchester and Bi Phase encodings and is able to generate PRBS9 pseudo random patterns The internal data encoder can be bypassed allowing transmissions in direct transparent mode The core element of the transmitter is the sigma delta fractional N PLL Synthesizer used for carrier frequency control and as part of the digital modulator as well It covers the frequency bands 300 320 MHz 433 450 MHz and 863 928 MHz with outstanding frequency resolution Only one fixed frequency crystal e g 13 MHz is required for reference frequency generation The synthesizer is characterized by short settling time It is also used as direct FSK modulator and together with a Gaussian filter implemented by means of lookup table offers the functionality of a direct GFSK modulator The integrated Power Amplifier is able to deliver up to 10 dBm output power into a 50 O load usually the antenna via an external impedance matching network In addition there are integrated capacitors connected between GND and the RF PA output over SFR controlled on off switches These capacitors are elements of a software controlled antenna tuner They may be used to fine tune adjust the PA output to Load matching network impedance and thus to maintain good VSWR v
17. If disabled no clock signal is output on CLKOUT but it delivers a rising edge pulse after a reset event and stays high signalizing that the crystal oscillator output already reached a stable level Note If the CLKOUT line is used as system clock for a uC keep in mind that in Synchronous Transmission Mode the delivered frequency is not highly stable in phase it is affected by jitter due to the fact that the related counters are synchronized with each Transmit Command The reasons for this and the synchronization procedure itself are explained in Chapter 2 4 11 2 Synchronous Transmission Data Sheet 33 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 5 3 SFRs related to Crystal Oscillator and Clock Divide ADDR 0x06 CLKOUTCFG Clock Pre and Post scaler Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O CLKSRC CLKSRC AFTERSCAIE AFTERSCALE PRESCALE PRESCALE PRESCALE CLKOUTENA w 0 w 0 w 0 w 0 w 1 w 0 w 0 w 1 Bit 7 6 CLKSRC Clock source selection bit 1 0 00 after prescaler 01 after BRDIV counter 10 after BRDIV counter inverted 11 after afterscaler Bit 5 4 AFTERSCALE Afterscaler selection bit 1 0 divide by 22AFTERSCALE Bit 3 1 PRESCALE Prescaler selection bit 2 0 divide by 22PRESCALE Bit O CLKOUTENA 0 if CLKOUT disabled In this case CLKOUT goes High after crystal oscillator achieves stable level 1 if clock output enabled
18. 1 n u LBD 2V1 LBD_2V4 VAC FAIL BROUTERR PARERR PLLLDER r 0 HO c 0 c 1 c 0 c 0 Bit 7 1 Set to 1 mandatory Bit 5 LBD 2V1 battery low detected threshold at 2 1 V Bit 4 LBD 2VA battery low detected threshold at 2 4 V Bit 3 reserved reserved Bit 2 BROUTERR Brown out event Bit 1 PARERR Parity error Bit O PLLLDER PLL lock detector error Comments LBD 2V1 Battery voltage drop below 2 1 V detected if 1 In standby mode this bit is invalid LBD 2V4 Battery voltage drop below 2 4 V detected if 1 In standby mode this bit is invalid BROUTERR Brownout event detected if 1 PARERR Parity error detected if 1 PLLLDERR PLL lock error detected if 1 2 4 3 Digital Control 3 wire SPI Bus The control interface is a 3 wire Serial Peripheral Interface SPI which is used for device control and data transmission 2 4 3 1 SPI Pin Description EN enable input with embedded pull down resistor High level on EN input enables the SPI transmission The rising edge of the EN signal triggers the selection of the active SCK edge for the consequent data transfer until the EN line goes again in low state and transmission sampling of data between the device and the microcontroller can start For details refer to Figure 6 and Figure 7 SDIO 3 state input output This bidirectional line is used for data transfer between the TDA5150 and external host usually a uC On chip pull down resistor is connected to this pin The load drive capabi
19. 4 bits Individual switch of 0 1 capacitor banks switched off Switched on Bit 0 gt Bit 1 gt Bit 2 gt Bit 3 gt 60 fF 120 fF 240 fF 480 fF ADDR 0x20 RES1 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u reserved reserved reserved reserved reserved reserved reserved w 1 w 0 w 0 w 1 w 1 w 0 w 0 Bit lt 7 0 gt reserved Reserved set bits lt 6 3 2 gt to 1 and bits lt 5 4 1 0 to 0 Data Sheet 82 V 1 1 June 2012 infineon TDA5150 TDA5150 Functional Description ADDR 0x21 VACO VAC Configuration 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VAC_CTR VAC_CTR VAC_CTR VAC_CTR VAC_CTR VAC_CTR VAC_CTR VAC_CTR w 1 w 1 w 0 wi w 1 wi w 0 w 0 Bit 7 0 VAC_CTR VAC frequency counter value bit 7 0 VAC CTR VCO autocalibration FAST counter 7100 MHz compare value 9 bits bits 7 0 gt ADDR 0x22 VAC1 VAC Configuration 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u reserved reserved reserved reserved reserved reserved VAC_CTR w 1 w 0 wi w 0 wi w 0 w 0 Bit 7 n u Not used Bit lt 6 1 gt reserved Reserved set bit 6 to 1 bits lt 5 1 gt to 0 Bit O VAC_CTR VAC frequency counter value bit 8 VAC_CTR VCO autocalibration FAST counter 100 MHz compare value 9 bits bit 8 ADDR 0x23 RES2 Bit 7 Bit 6 Bit 5 Bit 4 Bi
20. ADDR 0x0E PLLFRACBO PLL Fractional Division Ratio Channel B byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO w 0 w 0 w 0 w 0 wi wi w 0 wi Bit 7 0 PLLFRACBO Fractional division ratio bit 7 0 PLLFRACBO Synthesizer channel frequency value 21 bits bits lt 7 0 gt fractional division ratio for Channel B Data Sheet 72 V 1 1 June 2012 dnfinenn fes TDA5150 Functional Description ADDR 0x0F PLLFRACB1 PLL Fractional Division Ratio Channel B byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 w 0 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Bit lt 7 0 gt PLLFRACB1 Fractional division ratio bit lt 15 8 gt PLLFRACB1 Synthesizer channel frequency value 21 bits bits lt 15 8 gt fractional division ratio for Channel B ADDR 0x10 PLLFRACB2 PLL Fractional Division Ratio Channel B byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u reserved PLLFRACB2 PLLFRACB2 PLLFRACB2 PLLFRACB2 PLLFRACB2 wi w 1 w 0 w 0 w 0 w 0 Bit 5 reserved Set to 0 Users are advised to leave the state of this bit unchanged Bit lt 4 0 gt PLLFRACB2 Fractional division ratio bit lt 20 16 gt PLLF
21. generates an internal reset whenever the voltage drops below the specific threshold The brownout error flag is set to allow recognition of a brownout event The flag can be read via SPI bus Parity Error There is a single parity bit for each SFR register which is updated each time the SFR register is written Following this update the parity for each register is calculated and checked against this bit continuously If there is a mismatch in any of the registers the error flag is set The content of all SFRs is monitored and the parity checked even during STANDBY state PLL Lock Error is monitored after the transmission start If the PLL loses the phase locked state during transmission the related flag is set The Fail Safe status of the chip is stored and available via the SFR Transmitter Status Register 0x01 If a failure condition occurs a flag is set and latched via previously mentioned SFR Even if the condition which led to the event occurrence is no longer true the set state of the Fail Safe bits is kept and cleared only by the Transmitter Status Register read operation See also Chapter 2 5 2 for detailed SFR register map Preservation of above described Fail Safe Flag bits in SFR Transmitter Status Register provides a feedback to user about the failure root cause if any error occurred If the Transmit Fail Safe bit FSOFF in SFR TXCFGO 0x04 is enabled set to 0 and one of the Fail Safe flags goes in active state th
22. nominal values of 31 96 35 96 39 and 43 96 can be programmed If disabled the default value of 5096 applies for Duty Cycle The Duty Cycle Control is accessible through the DCCCONF bits 0x1F 5 4 of SFR ANTTDCC Ox1F see DCCCONF paragraph for details In the 315 MHz band the DCCCONF and DCCDISABLE bits are ignored A predefined and optimized value of 33 is superimposed instead of a programable Duty Cycle Data Sheet 46 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 8 4 Antenna Tuning A block of 4 switchable capacitors connected in parallel with the PA output may be used for antenna tuning This option may be useful for fine tuning the RF PA to Load matching network and thus to obtain enhanced radiated power performance in a wider frequency band However retuning is required only in those multichannel applications where the channels are at considerable frequency offset one from the other i e not for ISM bands The tuning capacitors can be switched ON OFF individually the control of the respective switches is implemented in SFR TUNETOP 0x1F rr A VBAT k l l l TDA 5150 3 I Antenna Choke PA IN PA 2 Gi pi C2 Se e ma parastie from dr l Ant TT TTI Tune Lil d tl X 1 Ctrl E E E A J Figure 18 PA Antenna Tuning and Matching The 4 switched capacitors have different value
23. the mentioned blocks is the same Therefore minimum deviation is expected between the performance figures of the two mentioned boards and both may be regarded as equivalents in terms of RF performance Data Sheet 88 V 1 1 June 2012 Cinfineon TOASTEN Applications x3 4 g X8 Ext Supply d Eun EU E FORSE ERE Y O gt GND GND GND 1 Clos L WR e SLL RF OUT R2 TDAS15 EB 2 0 Figure 25 Component placement on Infineon Evaluation Board V2 top side At bottom left corner the contour of the uW Link Motherboard is drawn Data Sheet 89 V 1 1 June 2012 dOnfineon ZE Applications Figure 26 Infineon Evaluation Board V2 top side assembly Data Sheet 90 V 1 1 June 2012 dnfinenn TBASISO Applications DAS 159 29 Figure 27 Infineon Evaluation Board V2 top side metal Data Sheet 91 V 1 1 June 2012 Infineon ZE Applications O O FOROSMO IIEEEECEEEEERERCEY de PAS KA OKO ORO ORO OXO Se Figure 28 Infineon Evaluation Board V2 bottom side metal Data Sheet 92 V 1 1 June 2012
24. 0 to OXFF BDRDIV 255 Formula to calculate the bitrate bitrate EE ee el PRESCALE x BDRDIV 1 x 2x AFTERSCALE ADDR 0x08 PRBS PRBS Start Value Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS w 1 w 0 w 1 w 0 w 1 w 0 w 1 w 1 Bit 7 0 PRBS PRBS start value bit 7 0 PRBS PRBS start value 8 bits the PRBS generator uses this as a starting value after each transmission beginning Data Sheet 70 V 1 1 June 2012 infineon TDA5150 TDA5150 Functional Description ADDR 0x09 PLLINTA PLL MM Integer Value Channel A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u PLLINTA PLLINTA PLLINTA PLLINTA PLLINTA PLLINTA PLLINTA w 1 wi w 0 wi w 0 wi w 0 Bit lt 6 0 gt PLLINTA Integer division ratio bit lt 6 0 gt PLLINTA Multi modulus divider integer offset value 7 bits for Channel A ADDR 0x0A PLLFRACAO PLL Fractional Division Ratio Channel A byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO w 0 w 0 wl wl wl wl w O w 0 Bit lt 7 0 gt PLLFRACAO Fractional division ratio bit lt 7 0 gt PLLFRACAO Synthesizer channel frequency value 21 bits bits lt 7 0 gt fractional division ratio for Channel A ADDR 0x0B PL
25. 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O GO2STDBY reserved reserved FSOFF ISMB ISMB reserved reserved cw 0 w 0 w 0 w 0 w 0 w 1 w 1 w 0 Bit 7 GO2STDBY 1 activate STANDBY Bit 4 FSOFF 0 activate FAILSAFE Bit 3 2 ISMB RF frequency band bits ISMB ISM band selection 2 bits 00 MHz 01 MHz 10 MHz 11 MHz 300 320 433 450 863 870 902 928 Data Sheet 37 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x09 0x0D PLLINTn PLL MM Integer Value Channel A B C D 0x11 0x15 n Channel A B C D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u PLLINTn PLLINTn PLLINTn PLLINTn PLLINTn PLLINTn PLLINTn w 1 wl w 0 wl w 0 w O w 0 Bit lt 6 0 gt PLLINTn Integer division ratio bit lt 6 0 gt PLLINTn Multi modulus divider integer offset value 7 bits for Channel A B C and D ADDR 0x0A OxOE PLLFRACn0 PLL Fractional Division Ratio 0x12 0x16 n Channel A B C D byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACn0 PLLFRACnO PLLFRACnO PLLFRACn0 PLLFRACnO PLLFRACn0 PLLFRACn0 PLLFRACn0 wi w 0 wi wi wi wi w 0 w 0 Bit 7 0 PLLFRACn0 Fractional division ratio bit lt 7 0 gt PLLFRACn0 Synthesizer channel frequency value 21 bits bits lt 7 0 gt Fr
26. 0 GO2SLEEP ASKFSK2 ASKFSK1 ASKSLOPE INVERT ENCMODE ENCMODE ENCMODE cw 0 w 0 w 1 w 0 wl w 1 w 0 w 1 Bit 7 GO2SLEEP Go to Sleep Bit 6 5 ASKFSK2 1 ASK FSK setting 2 and ASK FSK setting 1 Bit4 ASKSLOPE ASK sloping enable Bit 3 INVERT Data inversion Bit lt 2 0 gt ENCMODE Encoding mode bit lt 2 0 gt GO2SLEEP Set the chip into SLEEP mode look at the detailed state diagram cleared after 1 is written ASKFSK2 1 ASK FSK modulation switch setting 2 and ASK FSK modulation switch setting 1 0 ASK 1 FSK ASKSLOPE ASK sloping enable 0 disable 1 enable INVERT Encoded data inversion enable 0 data not inverted 1 data inverted ENCMODE Encoding mode code selection 3 bits 000 010 100 110 Manchester Biphase Miller Scrambling Space Delay PRBS 001 011 101 111 Differential Biphase NRZ not used Manchester Mark data 70 Data Sheet 68 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description ADDR 0x06 CLKOUTCFG Clock Pre and Post scaler Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLKSRC CLKSRC AFTERSCALE AFTERSCALE PRESCALE PRESCALE PRESCALE CLKOUTENA w 0 w 0 wl w O w 1 w O wl w 1 Bit 7 6 CLKSRC Clock source selection bit 1 0 Bit 5 4 AFTERSCALE Post scaler selection bi
27. 1 1 June 2012 me Cinfineon oe Applications Table 8 Frequency and RF output power dependent component values Infineon Evaluation Board V1 1 Frequency band and C C C3 Ly L Note RF output power 315 MHz band 918 5 dBm 2 7pF 100pF 15pF 72nH 100 nH Board version orderable over ISAR 315 8 dBm 2 7pF 100pF 10pF 72nH 100 nH 315 10 dBm 2 7pF 100pF 5 6pF 72nH 100 nH 434 MHz band 434 5 d m 1 5pF 33pF 12 pF 51 nH 51nH m Board version orderable over ISAR 434 8 dBm 1 5pF 33pF 6 8pF 51nH 51nH 434 10 d m 1 5pF 33pF 47pF 51nH 51nH Board version orderable over ISAR 868 MHz band 868 5 dBm 868 8 dBm 868 10 d m 2 2pF 68pF 5 6pF 10nH 9 5nH m Board version orderable over ISAR 915 MHz band 915 5 dBm 915 8 dBm 1 5pF 68pF 4 7pF 9 5nH 8 7 nH Board version orderable over ISAR Attention for the capacitors listed in Table 8 the COG type is recommended Avoid the usage of XR7 type for those components as the tolerances and value of thermal coefficient may be rather high Note the layout of components and tracks included in reference oscillator block and RF matching network is practically the same on the two Evaluation Board versions V2 and V1 1 At the same time the nominal value of the components included in the mentioned blocks is the same Therefore minimum deviation is expected betw
28. Gaussian filter 0 31 Data Sheet 79 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x1D GFDIV Gaussian Filter Divider Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV w 0 w 0 wi w 0 w 1 w 0 wi w 0 Bit lt 7 0 gt GFDIV Gaussian filter divider bit lt 7 0 gt GFDIV Gaussian filter clock divider value 11 bits bits lt 7 0 gt defines the sampling ratio of the Gaussian filter typically this value is set such that the GF divider Ncr is 16 x chip rate for ideal Gaussian filtering GFDIV Jxosc chiprate x NGF Note it is recommended to program the GFDIV register in such way that the GF divider Ncr is 16 times the chip rate This allows optimum Gaussian filtering Data Sheet 80 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x1E GFXOSC Gaussian Filter Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FHBLANK reserved reserved reserved GFBYP GFDIV GFDIV GFDIV w 0 w 1 w 1 w 1 w 1 wi w 0 w 0 Bit 7 FHBLANK Frequency Hopping VAC Disable Bit lt 6 4 gt reserved Reserved set all bits to 1 Bit 3 GFBYP Gaussian filter bypass Bit lt 2 0 gt GFDIV Gaussian filter divider bits lt 10 8 gt FHBLANK Frequency Hopping enable disable VCO A
29. PLLBWTRIM PLLBWTRIM PLLBWTRIM reserved reserved reserved reserved RES3 0x26 reserved reserved reserved reserved reserved reserved reserved reserved ENCCNT j0x27 ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT Data Sheet 65 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description 2 5 2 SFR Detailed Descriptions ADDR 0x00 SPICHKSUM SPI Checksum Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 Bit lt 7 0 gt SPICHKSUM SPI checksum bit lt 7 0 gt SPICHKSUM Readout and clear the SPI checksum 8 bits generated by each write to SFR register ADDR 0x01 TXSTAT Transmitter Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 n u LBD 2V1 LBD 2V4 VAC FAIL BROUTERR PARERR PLLLDER r 0 r 0 c 0 c 1 c 0 c 0 Bit 7 1 Mandatory to keep set 1 Bit 5 LBD 2V1 battery low detected at 2 1 V Bit 4 LBD 2V4 battery low detected at 2 4 V Bit 3 reserved Don t care Bit 2 BROUTERR Brown out detector error Bit 1 PARERR Parity error Bit 0 PLLLDER PLL lock detector error LBD 2V1 Battery voltage drop below 2 1 V detected if 1 NOTE bit invalid in standby mode LBD_2V4 Battery voltage drop below 2 4 V detec
30. POUT1 0x1B 3 0 for power level 1 and POUT2 0x1B 7 4 for power level 2 in SFR POWCFG7 0x1B POUTn 0 means that the PA is effectively OFF The output impedance of the PA depends on the number of PA stages used The external antenna matching must be done for the impedance related to the highest number of used PA stages or in other words for the use case of highest RF output power If the desired output power is 10 dBm for instance the antenna should be matched for the case of all the11 PA Stages active In the same way if the output power requirement is for 5 dBm the antenna should be matched assuming that 9 PA Stages are used and active Supposed the matching network have been set up for the PA impedance bound to 10 dBm output power all 11 PA Stages active it is reasonable to expect some degree of mismatch and efficiency loss by operation in 5 dBm RF power mode 2 4 8 2 ASK Modulation and ASK Sloping The ASK or FSK modulation is selected by SFR TXCFG7 0x05 There are two possible setups designated ModulationSetting1 and ModulationSetting2 The bit D of Transmit Command Byte selects the active setting This allows switching between the two modulation setups without any further register configuration See also Chapter 2 4 3 4 Transmit Command ASK modulation is realized by switching the PA Stages ON and OFF in accordance with data signal to be transmitted On chip ASK Sloping capability is provided within TDA5150 This means th
31. Time from adj channel C27 SSB Phase 86 80 dBc Hz 10 kHz offset Noise 27 C 315 434 MHz 86 80 dBc Hz 100 kHz offset PLLBW 150 27 C kHz 105 100 dBc Hz m 1 MHz offset 27 C 135 120 dBc Hz g 10 MHz offset 27 C Data Sheet 109 V 1 1 June 2012 Cinfineon TDA5150 Electrical Characteristics Parameter Symbol Limit Values Unit 2 Test Conditions amp Remarks o 0 ke min typ max C28 SSB Phase 80 75 dBc Hz 10 kHz offset Noise 27 C 868 915MHz 80 75 dBc Hz 100 kHz offset PLLBW 150 27 C kHz 105 100 dBc Hz g 1 MHz offset 27 C 135 120 dBc Hz 10 MHz offset 27 C Data Sheet 110 V 1 1 June 2012 infineon 4 3 TDA5150 SPI Characteristics Electrical Characteristics Attention Test Status W denotes that the parameter is not subject to production test It was verified by design and or characterization Table 12 SPI Timing Characteristics Parameter Symbol Values Unit Note min typ max w Test Condition 2 I o D o E D1 Clock Frequency fo S ME 18 D2 Clock High Time t 150 ns D3 Clock Low Time t 150 ns D4 Active SetUp Time tssu 20 ns a D5 Not Active Hold Time ten 20 ns a D6 Active Hold Time tsHo 20 ns B D7 Not Active 20 Bs SetUp
32. by integer N type synthesizers are no longer required and this is a significant advantage for systems based on the TDA5150 transmitter chip However by choice of crystal frequency the phenomenon known as occurrence of fractional N spurs shall be considered and the reference frequency selected in such way to avoid it The phenomenon and the countermeasures which should be taken are described in detail in Chapter 2 4 6 1 Fractional Spurs The PLL allows a direct and highly accurate G FSK digital modulation This leads to reduction of spurs and harmonics versus performance of legacy transmitters devices which are mainly using crystal frequency pulling in order to achieve FSK modulation Synthesizer resolution down to 7 Hz for carrier frequency generation makes possible accurate adjustments and fine tuning It allows at least the partial correction and reduction of inherent frequency tolerances which are due to crystal manufacturing process In the same way it is possible to cancel the effects of temperature dependent frequency drift introduced by the crystal used for reference frequency generation and a temperature dependent retune process could be applied by means of small frequency Steps at the carrier frequency level Note the correction of the temperature related frequency drift caused by the quartz crystal assumes the availability of a temperature measurement sensor in the host system Data Sheet 8 V 1 1 June 2012 Cinfineo
33. is used e g for send of unscrambled synchronization patterns first followed by encoded payload 2 4 5 Crystal Oscillator and Clock Divider The Crystal Oscillator is a single pin negative impedance converter type oscillator NIC and provides the reference frequency for the phase locked loop and clock signal for the sigma delta modulator m XTAL Q1 m VREG 13 00 MHz C1 8 2 pF Figure 12 Oscillator Circuit The allowed crystal frequencies are in the 12 MHz to 14 MHz range A load capacitor C1 is connected in series with the crystal The value of the load capacitor depends on crystal parameters and to some extent even the parasitic capacitance of the PCB layout track and load capacitor pad has a slight but measurable influence The shown values are exemplifications and valid for the crystal used on IFX evaluation board Please refer also to the crystal oscillator parameters listed in Chapter 4 Electrical Characteristics to select a suitable crystal type Attention Theoretically any crystal frequency within the frequency range specified above can be used In practice this freedom is limited by the potential occurrence of so called Fractional Spurs see Chapter 2 4 6 1 Fractional Spurs for details Data Sheet 31 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description To avoid this unwanted effect the crystal frequency must be chosen in such way that the division r
34. logical 1 of the already encoded data and a negative frequency deviation for a logical 0 if the data inversion bit INVERT in SFR TXCFG1 0x05 3 is 0 inversion OFF If the inversion function is active INVERT bit is set to 1 the frequency shift directions are inverted i e negative frequency deviation for logical 1 of input data and positive deviation for 0 for the same NRZ data stream Note If an encoding scheme other then NRZ is chosen then data bits are decomposed in elementary chips as shown in Figure 10 and above two statements regarding input data inversion state on off versus frequency shift direction are true but apply instead of input data bit to the resulting chips The two frequencies corresponding to positive and negative frequency shift are directly associated with specific divider numbers The modulation is achieved by switching between these two divider numbers and it takes effect under the control of data signal state and encoding scheme if other then NRZ The above described divider ratio switching method is called direct FSK modulation With direct FSK modulation a well controlled frequency shift can be achieved and the pullability of the crystal in the reference frequency oscillator circuit is no issue anymore like by the classical FSK where usually a reactance does pull the crystal frequency Data shaping is realized in the digital domain as Gaussian filtered FSK GFSK It can be enabled by s
35. 011 0000 0001 0000 0010 After writing into the registers content of checksum SFR SPICHKSUM 0x00 will be 0x02 Data Sheet 23 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 3 3 Command Byte Structure First byte of each SPI sequence is the Command Byte with the following structure Function Code Command Byte Configuration C1 co Address D D A5 A4 A3 A2 A1 AO The first 2 bits C1 CO of the Command Byte are the function code field They define the command to be performed according to the following table C1 co Function Code Configuration Bits 0 0 Write data into SFR register lt A5 A0 gt field contains the SFR register s address There are 2 possible write modes controlled by state of EN line 1 write to a single address 2 burst mode write with address auto increment 0 1 Read data from SFR lt A5 A0 gt points to register address 0 Reserved do not use 1 1 Transmit Command Byte Bits lt A5 A0 gt within this byte define the transmission parameters see Chapter 2 4 3 4 Transmit Command for command fields The Write Read Command bytes are used for device control Bit fields lt A5 A0 gt within Command Byte are used to specify the addressed SFR register An overview and register map is given in Chapter 2 5 1 SFR Register List There are two ways to program the SFR registers 1 by sending Write commands indi
36. 150 Evaluation Board C10 CLKOUT f eikouT 14 MHz For divider ratio Output calculations see Frequency Chapter 2 4 5 1 C11 Voltage Vngc 2 1 V 100 nF decoupling Regulator 2 on VREG pin Output Voltage No external DC load allowed 1 Veat 3V 27 C 2 Vga7 gt 2 2 V for effective regulator operation C12 Supply Current Lee 0 49 2 5 uA 1 by T 27 C Sleep Mode 2 by Tmax 85 C C13 Supply Current Leet 0 5 62 yA 1 by T 27 C Standby Mode 2 by Tmax 85 C C14 Low Battery Vuen an 20 2 2 monitored V part Detector Threshold Vieo24 23 le 25 C15 Brownout Vbop 1 7 1 8 in Active Mode Detector monitored Vpec Voltage Vao 07 17 v in Standby Mode Threshold monitored Vrec and Vaar C16 Supply Current lpienabie 63 8 mA Moar 3 V PLL is ON PA is OFF 315 434 MHz Data Sheet 107 V 1 1 June 2012 Cinfineon TDA5150 Electrical Characteristics Parameter Symbol Limit Values Unit 2 Test Conditions amp Remarks o 0 E min typ max C17 Supply Current lpienabie 6 6 18 5 mA Moar 3 V PLL is ON PA is OFF 868 915 MHz C18 Supply Current lrsdbm 9 12 mA D 1 P ut 5 8 10 Transmit Mode 11 14 mA dBm measured with T8dbm 2 315 434 MHz 50 Ohms load T10dbm 13 16 mA 2 59V C19 Supply Current Itsqpm 11 14 mA D 1 Pou 5 8 10 Transmit Mode dBm measured with L
37. 2 4 6 3 2 4 6 4 2 4 6 5 Product Description 6 OVEFVIBW 2 311 keke pepe dE yop R E EEN Pier P Rer dee n 6 qz PIE 6 AppliGatiOns D annee nai obtenant rene nent 7 Order Information 7 Key Features overview 7 Typical Application Circuit 7 Sigma Delta fractional N PLL with High Resolution 8 Reduction of Spurs and Occupied Bandwidth 9 Asynchronous and Synchronous Transmission 9 Integrated Data Encoder 10 Fail Safe Mechanism 10 TESEUS Configuration and Evaluation Tool 11 TDA5150 Functional Description 12 PIN Configuration Pin out 12 Pin Definition and Pin Functionality 12 Functional Block Diagram 17 Functional Description 18 Special Function Registers 18 Power Supply Circuit 18 Brownout Detector 19 Low Battery Detector 20 SFRs related to Supply Voltage monitoring 21 Digital Con
38. 50 Functional Description 2 4 11 3 Channel Hopping TDA5150 offers the possibility for usage of up to 4 preconfigured RF channels designated as frequency channel A B C and D The preconfiguration assumes the proper programming of the following PLL registers e Multi Modulus Integer Value registers A B C D 0x09 0x0D 0x11 0x15 and e Fractional Division Ratio registers A B C D 0x0A 0x0C OxOE 0x10 0x12 0x14 0x16 0x18 Bit fieled lt E F gt in Transmit Command is used for frequency channel selection Thus it is possible to switch quickly between RF frequency channels without time consuming reconfiguration assuming that the channels intended for transmission have been preconfigured in advance Any frequency hop within the frequency band requires a new Transmit Command and up to 100 us idle time for the PLL to perform the VCO Auto Calibration and to settle i e to achieve phase locked state For hops to new frequencies less then1 MHz apart from the frequency on which the VCO Auto Calibration was performed it is possible to skip the VCO Auto Calibration process and thus to reduce the PLL settling time to around 20 us instead of 100 us In this case it is allowed to start the transmission triggered by the rising edge of signal on the SCK line by waiting for only 20 us after the Transmit Command have been completed The VCO Auto Calibration process can be skipped by setting the FHBLANK bit 0x1E 7 in SFR GFXOSC 0x1E to 1
39. 8 Johanson Technology 2 C2 see Table 8 0603 Table 8 Johanson Technology 3 C3 see Table 8 0603 Table 8 Johanson Technology 4 C4 100 pF 0603 20 Johanson Technology 5 C5 100 nF 0603 20 6 C6 8 2 pF 0603 see crystal manufacturer specifications for load capacitor 7 C7 100 nF 0603 20 8 C8 100 nF 0603 20 9 C9 10 uF 0603 20 not placed 10 C10 0603 notch filter value depends on harmonics order not placed 11 IC1 TDA5150 10 pin Tx chip Infineon Technologies TSSOP 12 JP1 jumper 100 mil 13 JP2 jumper 100 mil Test Bridge for TDA5150 current 14 JP3 jumper 100 mil Test Bridge for RF PA current 15 L1 see Table 8 0603 Table 8 0603CS Coilcraft 16 L2 see Table 8 0603 Table 8 0603CS Coilcraft 17 L3 0603 notch filter value depends on harmonics order not placed 18 Q1 13 000 MHz TSS 5032 10 ppm EXSO00A NDK model ID 1 recommended CS01623 NX5032SD for 13 MHz value only for system test 2 NDK not specification nmb distribution version EXSO00A NX5032SA for 13 560 MHz CS0264 7 13 56 MHz 19 R1 0603 not placed only for system test 20 R4 0603 not placed 21 X1 connector SMA RF port 22 X2 connector SMA not placed only for system test 23 X3 connector 100 mil 2 pins External supply 24 X6 connector 100 mil 6 pins GND for probes 25 X7 connector 100 mil 8 pins Test points 26 X8 connector 2x20 pin SIB connector Note RF output power and frequency band dependent component values are listed in Table 8 Data Sheet 102 V
40. ACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC2 0x14 n u n u reserved PLLFRACC2 PLLFRACC2 PLLFRACC2 PLLFRACC2 PLLFRACC2 PLLINTD 0x15 n u PLLINTD PLLINTD PLLINTD PLLINTD PLLINTD PLLINTD PLLINTD PLLFRACDO 0x16 PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACD1 0x17 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD2 0x18 n u n u reserved PLLFRACD2 PLLFRACD2 PLLFRACD2 PLLFRACD2 PLLFRACD2 SLOPEDIV Gig SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV POWCFGO Dx1A PA PS2 PA PS2 PA PS2 PA PS1 PA PS1 PA PS1 SLOPEDIV SLOPEDIV POWCFG1 Oil POUT2 POUT2 POUT2 POUT2 POUT1 POUT1 POUT1 POUT1 FDEV _0x1C FDEVSCALE FDEVSCALE FDEVSCALE FDEV FDEV FDEV FDEV FDEV GFDIV Dx1D GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFXOSC 0x1E FHBLANK reserved reserved reserved GFBYP GFDIV GFDIV GFDIV ANTTDCC GO DCCVBYP DCCDISABLE DCCCONF DCCCONF TUNETOP TUNETOP TUNETOP TUNETOP RES1 0x20 n u reserved reserved reserved reserved reserved reserved reserved VACO 0x21 VAC_CTR VAC CTR VAC CTR VAC CTR VAC CTR VAC CTR VAC CTR VAC CIR VAC1 0x22 n u VAC NXOSC VAC NXOSC VAC NXOSC VAC NXOSCVAC NXOSCVAC NXOSQ VAC CTR RES2 0x23 reserved reserved reserved reserved reserved reserved reserved reserved CPCFG 0x24 n u reserved reserved reserved CPTRIM CPTRIM CPTRIM CPTRIM PLLBW Ob reserved
41. CFG1 0x05 7 to 1 This bit will be cleared automatically on WAKEUP i e on exiting the SLEEP state There is a small latency after the trailing edge of signal on EN pin of 2 f cycles the time taken to close down internal blocks SLEEP mode is left if the EN line is set to High level and there is clock activity at least 3 pulses on the SCK line The conjunction of these 2 conditions will wake up the transmitter and thus SLEEP Mode will be exited In SLEEP mode Onlythe low power voltage regulator is ON e Only the SPI interface is powered e POR is ON BOD is in low power mode inaccurate threshold All other blocks are OFF Power supply for digital core and SFR data is disconnected As a consequence SFR register content is lost 2 4 9 2 STANDBY Mode Data Retention Mode STANDBY is a low power mode but with higher consumption as SLEEP mode due to the fact that the SFRs are still supplied in this mode STANDBY is entered whenever the EN line is low no SPI communication and the time out count of 65536 f periods have been elapsed after a GO2STANDBY command execution setting the GO2STANDBY bit in SFR TXCFGO 0x04 7 followed by taking the EN pin to Low EN 0 In STANDBY Mode Only the low power voltage regulator is ON SPI SFR container and System Controller are supplied data can be read into and from the chip POR is ON BODisin low power mode inaccurate threshold Data consisten
42. DIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV w 1 w 0 wi w 0 wl w 0 w 0 w 0 Bit lt 7 0 gt SLOPEDIV ASK sloping clock divider bit lt 7 0 gt SLOPEDIV ASK sloping clock division ratio 10 bits bits lt 7 0 gt defines the timing of the ASK signal shaping using PA power stage switching Range from 0x000 to Ox3FF SLOPEDIV 1 SLOPEDIV 1024 Data Sheet 49 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x1A POWCFG0 PA Output Power Configuration Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA_PS2 PA_PS2 PA_PS2 PA_PS1 PA_PS1 PA PS1 SLOPEDIV SLOPEDIV w 0 wi wl w O wl wl wl w 0 Bit lt 7 5 gt PA_PS2 PA output blocks setting 2 bit lt 2 0 gt Bit lt 4 2 gt PA PS1 PA output blocks setting 1 bit lt 2 0 gt Bit lt 1 0 gt SLOPEDIV ASK sloping clock divider bit lt 9 8 gt PA_PS2 Individual control of the 3 PA blocks setting 2 3 bits 0 disabled 1 enabled Bit 0 gt Bit 1 gt Bit 2 gt PA block 0 PA block 1 PA block 2 PA PS1 Individual control of the 3 PA blocks setting 1 3 bits 0 disabled 1 enabled Bit 0 gt Bit 1 gt Bit 2 gt PA block 0 PA block 1 PA block 2 SLOPEDIV ASK sloping clock division ratio 10 bits bits lt 9 8 gt defines the fr
43. DRDIV Failsafe Mechanism PRBS Start Value 5 ono 10 CLKOUT kHz 512 500 Unscrambled Jg Resulting Bitrate kbps j Bit Count Resulting Chiprate kbps 5 295 Frequency Hopping Enabled 1 Disabled r Voltage Supply SIB Parameters Voltage Regulator Vbat from SIB V 3 0 VregIVE Pi SCK Frequency kHz 50 0 Q Brownout Error Q Battery Voltage Drop under 2 AN eo PLL Lock Error S Read Status Registers vco Autocalibration Failure Q Battery Voltage Drop under 2 1V Q Parity Error 1055150 detected o Interface Board connected Update Registers Figure 3 TESEUS First Tab of User Interface screen TESEUS is a user friendly comfortable tool suitable for generation of TDA5150 configurations and testing them using a TDA5150 Evaluation Board Configurations can be automatically converted into register lists and implemented in C code The pattern to be transmitted is written into a datagram or TX file A commented example TX file can be generated by TESEUS This file might be edited using a standard text file editor if changes of the transmit parameters and data patterns are required Note for further details please consult the TESEUS User s Manual document downloadable from Infineon Technologies AG web page free of charge Data Sheet 11 V 1 1 June 2012 dnfinenn uet TDA5150 Functional Description
44. EEIEL EEEEEEEE TRANSMIT data EN 1000us if TX issue d from STDBY else determined by SCK speed 100u gt Jidd Command Configuration L Data to transmit La gt SDIO E 1XAIBICIDOLEIF d1 d2 d3 d4 d5 Figure 9 Timing Diagrams of 3 wire SPI Note In order to minimize cross talk between SDIO and SCK lines it is recommended to keep the SCK either Low or High but avoid transitions during RF transmission Previous Chapter 2 4 3 4 Transmit Command gives an in depth overview of Transmit Command structure Data Sheet 26 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 4 Data Encoder The Data Encoder is used in the so called Synchronous Transmission Mode A description of this transmission mode is found in Chapter 2 4 11 2 Synchronous Transmission In Synchronous Transmission Mode the Encoder has to be used If no specific encoding of SDIO data shall be done select NRZ as encoding scheme Definition bit rate is the number of transmitted bits per second and expressed in bits sec Besides NRZ all the other implemented encoding methods split a single bit into two elementary parts the so called chips Therefore we also talk about a chip rate which is an n multiple of the data rate For NRZ which means no extra encoding n 1 data rate chip rate and for all other implemented encoding metho
45. K FSK GFSK RF transmitter for the 300 320 MHz 433 450 MHz and 863 928 MHz frequency bands The input datastream applied to the digital SDIO line is transposed and appears as modulated RF signal at the output of the integrated RF power amplifier Signal encoding and spectrum is in accordance with the chosen modulation type i e ASK FSK or GFSK and encoding scheme TDA5150 contains following major blocks which extend the functionality compared to legacy RF transmitters An on chip voltage regulator is delivering 2 1 V nominal supply voltage for the transmitter s functional units In addition the battery voltage is monitored and battery low and brown out flags are set if a critical supply voltage drop event occurs For avoidance of erroneous transmissions the brownout flag is coupled with the RF Power Amplifier state control If a brownout or critical voltage drop event occurs the RF Power Amplifier is automatically switched off as part of the Fail Safe philosophy The mechanism is explained in detail in Chapter 2 4 8 5 The crystal oscillator and the associated clock divider s generate the required clock signals There is an output line CLKOUT which may be used to clock a host uC or for bit rate generation A digital control logic accessible for user via the SPI bus allows flexible and fast re configuration At the same time it offers a simple but powerful Fail Safe mechanism which enhances the reliability of the transmissions
46. K low at rising edge of EN If SCK is high during occurrence of rising edge on EN incoming SDIO data is sampled with the rising edge on SCK and output by falling edge of SCK as illustrated in Figure 7 Data Sheet 22 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description EN SCK level sampled i ten tssu F7 MUN I SDIO B Figure 7 SPI Timing SCK high at rising edge of EN 2 4 8 2 SPI XOR Checksum The SPI block includes a safety feature for checksum calculation This is achieved by means of XOR operation between the address and the data during write operation of SFR registers The checksum is in fact the XOR of the data 8 bitwise after every 8 bits of the SPI write command The calculated checksum value is then automatically written into SFR SPICHKSUM 0x00 and can be compared with the expected value By executing a read operation of SFR SPICHKSUM 0x00 the register content is automatically cleared after read Read access to any of the other readable SFRs does not influence the SFR SPICHKSUM enable every 8 bit Y SPI shift register x08 Checksum SFR read clear lae SE F Figure 8 Generating the Checksum of SFRs block diagram Example Write to SFR address 0x04 data 0x02 address 0x05 data 0x01 Bytes transmitted via SPI Result in Checksum Register 0000 0100 0000 0100 0000 0010 0000 0110 0000 0101 0000 0
47. LFRACA1 PLL Fractional Division Ratio Channel A byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACA1 PLLFRACA1 PLLFRACA1 PLLFRACA1 PLLFRACA1 PLLFRACA1 PLLFRACA1 PLLFRACA1 w 0 wi w 0 wl w O w 0 wl w 0 Bit 7 0 PLLFRACA1 Fractional division ratio bit 15 8 PLLFRACA1 Synthesizer channel frequency value 21 bits bits 15 8 gt fractional division ratio for Channel A Data Sheet 71 V 1 1 June 2012 infineon TDA5150 TDA5150 Functional Description ADDR 0x0C PLLFRACA2 PLL Fractional Division Ratio Channel A byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O n u n u reserved PLLFRACA2 PLLFRACA2 PLLFRACA2 PLLFRACA2 PLLFRACA2 w 0 w 1 w 0 w 0 wi w 0 Bit 5 reserved Set to 0 Users are advised to leave the state of this bit unchanged Bit lt 4 0 gt PLLFRACA2 Fractional division ratio bit lt 20 16 gt PLLFRACA2 Synthesizer channel frequency value 21 bits bits lt 20 16 gt fractional division ratio for Channel A ADDR 0x0D PLLINTB PLL MM Integer Value Channel B Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O n u PLLINTB PLLINTB PLLINTB PLLINTB PLLINTB PLLINTB PLLINTB w 1 wl wl w 0 w 0 wl w 0 Bit 6 0 PLLINTB Integer division ratio bit 6 0 PLLINTB Multi modulus divider integer offset value 7 bits for Channel B
48. LLFRACD1 PLL fractional division ratio Channel D byte 1 0x17 PLLFRACD2 PLL fractional division ratio Channel D byte 2 0x18 SLOPEDIV ASK sloping clock divider low 0x19 POWCFGO PA output power configuration register 0 Ox1A POWCFG1 PA output power configuration register 1 0x1B FDEV Frequency deviation 0x1C GFDIV Gaussian filter divider value 0x1D GFXOSC Gaussian filter configuration 0x1E ANTTDCC Antenna tuning and Duty Cycle configurations Ox1F RES1 Reserved 0x20 VACO VAC configuration 0 0x21 VAC1 VAC configuration 1 0x22 VACERRTH VCA error threshold 0x23 CPCFG Charge pump configuration 0x24 PLLBW PLL bandwidth configuration 0x25 RES2 Reserved 0x26 ENCCNT Encoding start bit counter 0x27 Data Sheet 63 V 1 1 June 2012 TDA5150 Cinfineon TDA5150 Functional Description Register address CH Table 7 ADDR 0x01 Transmitter status register Register name ADDR 0x01 TXSTAT Transmitter status register Register bit position Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 e Register bit Register bit command 1 nu LBD_2V1 LBD 2V4 VAC FAIL BROUTERR PARERR PLLLDER ane and reset value gt l Dy m EN ci do EN Bit 7 1 fixed to logic 1 for safety reasons Bit6 nu not used Bit5 LBD 2V1 low battery detected at 2 1 V Bit4 LBD 2V4 low battery detected at 2 4 V Register bits Bit3 VAC FAIL VAC failed description Bit2 BR
49. MB 1 2 3 for ISMB 0 gt delay 0 ps 00 4396 01 39 10 3596 11 3196 69 35 33 207 104 9 346 173 484 242 ps 8 ps 164 ps 230 ps TUNETOP Antenna tuning top capacitor selection 4 bits Individual switch of 0 1 capacitor banks switched off Switched on Bit 0 gt Bit 1 gt Bit 2 gt Bit 3 gt 60 fF 120 fF 240 fF 480 fF 2 4 9 Operating Modes TDA5150 has 3 main operating modes SLEEP STANDBY TRANSMIT and 2 temporary modes XOSC_ENABLE and PLL_ENABLE 2 4 9 1 SLEEP Mode SLEEP is the lowest power consumption mode Most of the internal blocks excepting the SPI interface are powered down and consequently the content of SFRs is going lost Therefore the SFR bank requires a full reprogramming after exiting SLEEP mode The SPI interface stays active and is supplied via the Low Power Voltage Regulator while in SLEEP mode The SPI interface is able to detect bus non idle conditions and it will wake up the transmitter if the EN pin is taken high and at least 3 pulses are applied to SCK pin Data Sheet 51 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description Observe that this last wake up condition is automatically fulfilled during communication over the transmitter s SPI bus assuming a standard SPI bus protocol is used SLEEP mode is entered aftera GO2SLEEP command execution i e by taking the EN pin to Low preceded by setting of the GO2SLEEP bit in SFR TX
50. OUTERR Brown out event Bit 1 PARERR Parity error Bit 0 PLLLDER PLL lock detector error LBD 2V1 Battery voltage drop below 2 1 V detected if 1 In standby mode this bit is invalid LBD_2V4 Battery voltage drop below 2 4 V detected if 1 In standby mode this bit is invalid BROUTERR Brownout event detected if 1 PARERR Parity error detected if 1 PLLLDERR PLL lock error detected if 1 2 4 11 RF Data Transmission The procedure of RF Transmission is started by the rising edge of the control signal applied to the chip enable pin EN pin 1 Thus STANDBY or SLEEP Mode are exited followed by start of the crystal oscillator which would require maximum 1 ms to start up if the crystal types indicated in Table 5 and Table 7 or similar models are used Note the startup time of an oscillator using a quartz crystal as frequency stabilizing element is at great extent a function of oscillator gain and the crystal s equivalent motional parameters L C4 R and C Especially motional inductance L has a high degree of influence but also Ry the equivalent series resistance and those parameter have to be carefully examined during crystal selection During this time the TDA5150 can be already reconfigured because the SPI block does not require the system clock Data Sheet 56 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description Before start of a transmission the T
51. OUTERR brown out detector error Bit1 PARERR parity error BitO PLLLDER PLL lock detecor error 1 Fixed to 1 for safety reasons LBD 2V1 Battery voltage drop below 2 1 V detected if 1 in standby mode bit is invalid LBD 2V4 Battery voltage drop below 2 4 V detected if 1 in standby mode bit is invalid 3 VCO autocalibration fail detected if 1 Registers VAC_FAIL i values BROUTERR Brownout error detected if 1 PARERR Parity error detected if 1 PLLLDERR PLL lock error detected if 1 Figure 22 Register Terminology Register bit command terminology r read register 0 default to 0 M default to 1 w write register 0 default to 0 M default to 1 c clear after write 0 default to 0 after M default to 1 after register clear clear Important notice It is mandatory to maintain the default values as specified in the respective register tables for all reserved Special Function Registers SFR reserved bits reserved bit fields Data Sheet 64 V 1 1 June 2012 Infineon Mailen TDA5150 Functional Description Table 4 Register Bit Map Configuration Register Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPICHKSUM 0x00 SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM SPICHKSUM TXSTAT 0x01 1 n u LBD_2V1 LBD_2V4 VAC_FAIL BROUTERR PARERR PLLLDERR TXCFGO _ 0x04 GO2STDBY reserved reserved FSOFF ISMB ISMB reserved reserved TXCFG1 _ 0x05 GO2SLEEP ASKFSK2 ASKFSK1 A
52. RACB2 Synthesizer channel frequency value 21 bits bits lt 20 16 gt fractional division ratio for Channel B ADDR 0x11 PLLINTC PLL MM Integer Value Channel C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u PLLINTC PLLINTC PLLINTC PLLINTC PLLINTC PLLINTC PLLINTC w 1 w 0 wi w 0 w 0 wi wi Bit 6 0 PLLINTC Integer division ratio bit 6 0 PLLINTC Multi modulus divider integer offset value 7 bits for Channel C Data Sheet 73 V 1 1 June 2012 Cinfineon nes TDA5150 Functional Description ADDR 0x12 PLLFRACCO PLL Fractional Division Ratio Channel C byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO w 0 w 0 wi w 0 w 0 wi w 0 wi Bit 7 0 PLLFRACCO Fractional division ratio bit 7 0 PLLFRACCO Synthesizer channel frequency value 21 bits bits lt 7 0 gt fractional division ratio for Channel C ADDR 0x13 PLLFRACC1 PLL Fractional Division Ratio Channel C byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 w 0 w 0 w O w 0 w 0 w 0 w 0 w 0 Bit lt 7 0 gt PLLFRACC1 Factional division ratio bit lt 15 8 gt PLLFRACC1 Synthesizer channel frequency value 21 bits bits lt 15 8 gt fractional division ratio
53. RF Power GND Amplifier Ground return Data Sheet 14 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description Pin Name Pin Equivalent 1 0 Schematic Function No Type 8 CLKOUT Digital Programmable Output Divided Clock VBat o 19 36V VBat CLKOUT e ur N I E Data Zei 500 GNDD e analog signals je Data Sheet 15 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description Pin Name Pin Equivalent 1 0 Schematic Function No Type 9 SCK Digital Clock 3 wire bus Input VBat ZN NK SCK a f LN 250k GNDD GNDD 10 SDIO Digital Data 3 wire bus Input Output d SC ut N 500 DE SDIO DATA J Daa l P Enable A 250k j GNDD GNDD GNDD Data Sheet 16 V 1 1 June 2012 Cinfineon nes TDA5150 Functional Description 2 3 Functional Block Diagram VREG O E Voltage B Internal O Regulator Veat Supply ZA Fractional N PLL Power Antenna Digita d Data D Digital ASK FSK T Q PAOUT Control Encoder Amplifier Tuning Modulator Crystal sd Clock GND i Oscillator m Divider O CLKOUT Figure 4 TDA5150 Block Diagram TDA5150 is an SPI configurable fully integrated AS
54. SKSLOPE INVERT ENCMODE ENCMODE ENCMODE CLKOUTCFG 0x06 CLKSRC CLKSRC AFTERSCALEAFTERSCALE PRESCALE PRESCALE PRESCALE CLKOUTENA BDRDIV _ 0x07 BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV PRBS 0x08 _ PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS PLLINTA 0x09 n u PLLINTA PLLINTA PLLINTA PLLINTA PLLINTA PLLINTA PLLINTA PLLFRACAO 0x0A PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACAO PLLFRACA1 0x0B PLLFRACA1 PLLFRACA1 PLLFRACA1 PLLERACA1 PLLFRACA1 PLLFRACAt1 PLLFRACA1 PLLFRACA1 PLLFRACA2 Px0C n u n u reserved PLLFRACA2 PLLFRACA2 PLLFRACA2 PLLFRACA2 PLLFRACA2 PLLINTB xOD n u PLLINTB PLLINTB PLLINTB PLLINTB PLLINTB PLLINTB PLLINTB PLLFRACBO DxOE PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO PLLFRACBO RACBO PLLFRACB1 OxOF PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 PLLFRACB1 RACB1 PLLFRACB2 0x10 n u n u reserved PLLFRACB2 PLLFRACB2 PLLFRACB2 PLLFRACB2 PLLFRACB2 PLLINTC 0x11 n u PLLINTC PLLINTC PLLINTC PLLINTC PLLINTC PLLINTC PLLINTC PLLFRACCO 0x12 PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACCO PLLFRACC 1 0x13 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFRACC1 PLLFR
55. Sheet 113 V 1 1 June 2012 Cinfineon ann Package Outline 5 Package Outline x 5 S LL 3 18 IL O eio E ul I E Z 0 5 d io lt 0 22 A eo ui TT 0 0 amp w A B Marking Notes All dimensions are in mm 1 Does not include plastic or metal protrusion of max 0 15 mm per side 2 Does not include plastic or metal protrusion of max 0 25 mm per side Figure 36 Green Package TSSOP 10 outline III 3 5 5 5 0 5 ULL Figure 37 Footprint TSSOP 10 package You can find all of our packages types of packing and other information on the Infineon Internet Page Products http www infineon com products HLG09617 SMD Surface Mounted Device Data Sheet 114 V 1 1 June 2012
56. Time NEN D8 Deselect Time t 150 ns B D9 Input Data SetUp Time ipsu 50 ns m D10 Input Data Hold ge toho 50 ns a D11 Clock to Output Data Valid tcopv 150 jns m 20pF Load D12 Output Data Rise Time topi 25 ns 8 20pF Load D13 Output Data Fall Time 20pF tonsa 25 ns m Load Data Sheet 111 V 1 1 June 2012 Qin TDA5150 Electrical Characteristics Parameter Symbol Values Unit Note min typ max a Test Condition E 5 o o E D14 Input Data Tristate Setup tipzs 0 ns Time D15 Output Data Disable Time uo 150 ns m Data Sheet 112 V 1 1 June 2012 Cinfineon TDA5150 Electrical Characteristics Table 13 SPI Electrical Characteristics Parameter Symbol Values Unit Note min typ max E Test Condition 5 o ke E1 Input Low Pins EN SCK Voltage Vi ME G 6 SDIO E2 Input High V Veat Veat V Pins EN SCK Voltage H 0 4 0 2 SDIO E3 Output Low Pins SDIO Voltage Von Ge CLKOUT E4 Output High V Maar V Pins SDIO Voltage OH 0 5 CLKOUT ER SPIO pin current source drive capability Voy 750 Ohm mW Vaq7 3 6 V and 85 C Tamb EG SPIO pin current sink drive capability Vo 500 Ohm mW Var 3 6 V and 85 C Tamb E7 Parasitic capacitance Cpad 2 pF E8 Internal Pull down Resistor Raown 175 250 360 kOhm m Data
57. UT pin 8 is ferkout Las 16 as specified by after reset state Attention Test Status W denotes that the parameter is not subject to production test It was verified by design and or characterization Table 11 ACIDC Characteristics Parameter Symbol Limit Values Unit 2 Test Conditions w Remarks o 0 ke min typ max C1 Transmit fix 300 320 MHz Frequency 433 450 MHz Bands 863 928 MHz C2 Modulation ASK OOK FSK CPFSK GFSK Types C3 Encoding Manchester differential Manchester Miller Modes Biphase mark Biphase space scrambled NRZ C4 Chip Rate 0 5 100 kchip s g See Chapter 2 4 4 for chip rate definition C5 Carrier fstep 7 Hz E fcrysta 2exp 21 Frequency Step C6 Frequency fev 1 64 kHz m See Chapter 2 4 7 Deviation for frequency shift programming and calculations C7 Crystal fxraL 12 14 MHz m Total max capacity Frequency incl parasitics Range between XTAL and GND pins max 4 pF C8 Crystal Osc Rsrarr 500 Ohm 1 ferystal 13 56 MHz Margi Tamb 25 ZER Lose 1385155 715 uH g sep Data Sheet 106 V 1 1 June 2012 Cinfineon TDA5150 Electrical Characteristics Parameter Symbol Limit Values Unit 2 Test Conditions amp Remarks o 0 E min typ max C9 XTAL Startup txraL 1 ms with crystal Time NDK NX5032SA on TDA5
58. V1 1 June 2012 392 pg rege RSR TDA5150 Multichannel Multiband Transmitter Multichannel Multiband RF Transmitter for 300 928 MHz bands On chip high resolution fractional N synthesizer and Sigma Delta modulator with ASK FSK GFSK options Wireless Control Cinfineon Never stop thinking Edition June 2012 Published by Infineon Technologies AG Am Campeon 1 12 85579 Neubiberg Germany 2007 Infineon Technologies AG All Rights Reserved Attention please The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics Terms of delivery and rights to technical change reserved We hereby disclaim any and all warranties including but not limited to warranties of non infringement regarding circuits descriptions and charts stated herein Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office in Germany or the Infineon Technologies Companies and Infineon Technologies Representatives worldwide www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies Components may be used in life support devices or systems only with the express written approval of Infi
59. VCO a VCO Auto Calibration mechanism VAC is implemented and runs automatically during each start up of the PLL First a fixed internal voltage is applied to the VCO and the generated RF frequency is divided by 4 or 8 for 868 915 MHz bands The positive transitions are then counted during 32 system clock cycles The result is compared to a configured number derived from the desired RF frequency value as the formula shows The VCO is then automatically fine tuned before an RF transmission starts PLLINT lt 6 0 gt PLLERACS20 0 gt 0 5 2 us VAC_CTR lt 8 0 gt 7 QUSMB I5 1 x4 x VAC_NXOSC lt 5 0 gt where e VAC_CTR lt 8 0 gt has to be calculated according the formula above It contains the optimal number of positive transitions to which the VAC counter result is compared Data Sheet 35 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description e PLLINT 6 0 and PLLFRAC 20 0 PLL divider SFRs used to define the desired RF frequency SMB 1 MSB of SFR register ISMB lt 1 0 gt for band selection e VAC NXOSC 5 0 always set to 32 decimal or 0x20 number of elapsed system clocks cycles used for VAC counting i e total duration of counting 2 4 6 3 Loop Filter Bandwidth In order to provide a high grade of flexibility by choice of modulation parameters a PLL with programable bandwidth have been implemented in the TDA5150 The damping resistor s part of the active Loop Filter in the PLL can be
60. a P ra d2 d3 d4 gt SDIO Y1 1C AX BY CX DX EX F ax X X lt X s gt Transmitted di E d2 x d3 x d4 X d5 Data Figure 20 Asynchronous Transmission Setting the EN line pin 1 to low terminates the RF transmission 2 4 11 2 Synchronous Transmission In the Synchronous Transmission Mode the transmit data is latched with the falling edge of the internal bit clock and thus synchronized The bit clock at the CLKOUT has to be used by the uC to time the bits which are transmitted e g on interrupt basis The Encoder has to be enabled If the bits shall not be encoded select NRZ as generic Encoder scheme See Chapter 2 4 4 Data Encoder Data Sheet 59 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description TRANSMIT data Synchronous Transmission SS gt 1000 us if TX issued from STDBY else determined by SCK speed 100 us I o Idee 4 spio y Na eX ex xX le sa ttl Li cit Ye pay sort OX XXX Figure 21 Synchronous Transmission d2 d3 d4 d5 Synchronous transmission is the recommended user mode Encoding can be used and this mode is preferred especially for GFSK At the same time SW implementation is easier because the delivery of the next data bit over the SDIO line is triggered by interrupt mapped to CLKOUT line and timing inaccuracie
61. actional division ratio for Channel A B C and D ADDR 0x0B OxOF PLLFRACn1 PLL Fractional Division Ratio 0x13 0x17 n Channel A B C D byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACn1 PLLFRACn1 PLLFRACn1 PLLFRACn1 PLLFRACn1 PLLFRACn1 PLLFRACn1 PLLFRACn1 w 0 wi w 0 w 0 wl w 0 wl w 0 Bit 7 0 PLLFRACn1 Fractional division ratio bit lt 15 8 gt PLLFRACn1 Synthesizer channel frequency value 21 bits bits 15 8 gt fractional division ratio for Channel A B C and D Data Sheet 38 V 1 1 June 2012 Cinfineon nes TDA5150 Functional Description ADDR 0x0C 0x10 PLLFRACn2 PLL Fractional Division Ratio 0x14 0x18 n Channel A B C D byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u n u reserved PLLFRACn2 PLLFRACn2 PLLFRACn2 PLLFRACn2 PLLFRACn2 w 0 w 1 w O w 0 wl w 0 Bit 5 reserved Set to 0 Users are advised to leave the state of this bit unchanged Bit lt 4 0 gt PLLFRACn2 Fractional division ratio bit lt 20 16 gt PLLFRACn2 Synthesizer channel frequency value 21 bits bits lt 20 16 gt fractional division ratio for Channel A B C and D 2 4 7 Digital FSK GFSK Modulator The TDA5150 uses an integrated direct FSK Modulator for generation of RF signals By this method and assuming NRZ data encoding a positive frequency deviation relative to nominal carrier frequency occurs for a
62. actional division ratio for Channel D Data Sheet 75 V 1 1 June 2012 Cinfineon nes TDA5150 Functional Description ADDR 0x17 PLLFRACD1 PLL Fractional Division Ratio Channel D byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 PLLFRACD1 wi w 0 wi w 0 wi w 0 wi wi Bit 7 0 PLLFRACD1 Fractional division ratio bit 15 8 PLLFRACD1 Synthesizer channel frequency value 21 bits bits lt 15 8 gt fractional division ratio for Channel D ADDR 0x18 PLLFRACD2 PLL Fractional Division Ratio Channel D byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O n u n u reserved PLLFRACD2 PLLFRACD2 PLLFRACD2 PLLFRACD2 PLLFRACD2 wi w 1 w 0 w 0 wi w 0 Bit 5 reserved Set to 0 Users are advised to leave the state of this bit unchanged Bit lt 4 0 gt PLLFRACD2 Fractional division ratio bit lt 20 16 gt PLLFRACD2 Synthesizer channel frequency value 21 bits bits lt 20 16 gt fractional division ratio for Channel D Data Sheet 76 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x19 SLOPEDIV ASK Sloping Clock Divider Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 B
63. alues over a wider frequency band This is particularly useful if the transmitter is operated not only on a single frequency but in multichannel mode with considerable spread between the channels 2 4 Functional Description 2 4 1 Special Function Registers TDA5150 is configurable by programming the Special Function Register bank abbreviated SFRs via the SPI interface Terminology and notations related to TDA5150 SFR set list of symbols and programming restrictions are given in Chapter 22 Register Terminology Detailed description of SFR map programming usage and content explanations are found in Chapter 2 4 Functional Description and Chapter 2 5 Digital Control SFR Registers 2 4 2 Power Supply Circuit An internal voltage regulator generates a constant supply voltage 2 1 V nominal for most of the analog and digital blocks An external capacitor 100 nF nominal value connected between VREG pin 4 and GND pin 3 is necessary to guarantee stable functionality of the regulator Data Sheet 18 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description The regulated voltage on VREG pin is not adjustable by user and it is not allowed to connect any additional external loads to this pin but the above mentioned decoupling capacitor In STANDBY state a special low power voltage regulator is activated which is supplying only the SPI bus interface the SFR registers and the system controller In order to further r
64. anchester Bi Phase and Miller encoding on chip PRBS9 scrambler Continuous checking of chip status by Fail Safe mechanism Transparent and synchronized RF modulation mode Programmable clock divider output Configurable output power level from 10 dBm to 10 dBm in 2 dB nominal steps Supply voltage range 1 9 V 3 6 V 2 low battery detection thresholds preset to 2 4 V and 2 1 V Low supply current Sleep Mode lt 0 8 pA RF transmission 9 mA 5 dBm ESD protection up to 4 kV at all pins Operating temperature range 40 C to 85 C Green Package TSSOP 10 Data Sheet 6 V 1 1 June 2012 Cinfineon Water Product Description 1 3 Applications Shortrange wireless data transmission Remote keyless entry transmitters e Remote control units Wireless alarm systems Remote metering Garage door openers 1 4 Order Information TDA5150 SP000300415 PG TSSOP 10 1 5 Key Features overview 1 5 1 Typical Application Circuit VBAT uC clocked by TDA5150 SPI bus controlled by nC Antenna spo VBAT PAOUT I sc I M EN C3 C4 10 pF oN 5 pF XTAL TIM IRQ Le cLkout TDA5150 H H XTAL GNDPA C1 8 2 pF l VREG qup Remarks values valid for 433 MHz and the given antenna geometry Q1 7K C2 13 00 MHz 100 nF Figure 1 Minimum com
65. at instead of Switching all PA Stages at the same time they are switched ON one after the other in a configurable time sequence The power sloping is controlled by SFR SLOPDIV register 0x19 7 0 Data Sheet 45 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description The register content is equal with the number of reference oscillator cycles elapsed until the next PA stage is switched ON or OFF Note For optimum shaping effect it is recommended to match the number of sloping steps to the required maximum output power and consequently to the maximum number of stages which might be used 2 4 8 3 Duty Cycle Control The control of Duty Cycle leads to control of the averaged RF output power by changing the conductive angle of the RF power amplifier and contributes to further reduction of the current consumption It is worth to be noted that decreasing conduction angle values lead to decrease of power consumption but at the same time due to the short and high amplitude current pulses the level of RF harmonics on n fcarrier frequencies will tend to rise An adequate lowpass or bandpass filter is required therefore between the power amplifier and the load and quite often this filter is merged into one block with the impedance matching network i e the impedance matching network is able to reject some harmonics of the carrier frequency especially those with potentially high level If Duty Cycle control option is enabled
66. ate 13 16 mA 868 915 MHz 50 Ohms load T10dbm 16 19 mA 2 Vear 3V C20 Power Level P varsdbm 1 Referenced to Tolerance vs P 1 5 1 5 dB 1 Var 3V 27 C nominal value BM 5 not including Puartodbm matching network Puarsdbm 2 comp tolerance P asas 2 2 dB 2 E z 1 315 amp 434 MHz Partodbm band 2 868 amp 915 MHz band C21 Power Level Pyarsdbm 1 5 1 5 dB W Tamb 40 85 C Variation vs Vaar 3 Volt temperature Pvergdbm 1 5 1 5 dB E RF P measured on P ous 1 5 1 5 dB Evaluation Board C22 Power Level E stsdb 55 7 dB Veat 11 9 3 6 V Variation vs RF P measured on battery voltage P var amp dbm 5 5 7 dB IFX Evaluation Puartodbm 55 7 dB Boards C23 Power Level Paetta step 1 2 3 dB maximum 10 steps Step Size Data Sheet 108 V 1 1 June 2012 Cinfineon ues Electrical Characteristics Test Conditions Remarks Parameter Symbol Limit Values Unit Test Status min typ max C24 PLL bandwidth 150 410 kHz 1 the PLL bandwidth is programable SFR CPTRIM 0x24 3 0 controls the chargepump current and SFR PLLBW TRIM 0x25 6 4 fis the selector for loop filter damping resistor value 150 kHz is the smallest and 410 kHz the largest nominal PLL BW See Table2 for PLL recommended settings C25 Band Switching thanaswitch 100 us jump between band Time end frequencies frin ss fax C26 Channel Lonswitch 20 us m 1 MHz hop away Switching
67. atio PLL division factor RF carrier frequency crystal frequency shall give a fractional part the part behind the decimal point between 0 1 and 0 9 For example a 13 56 MHz crystal should not be used for the carrier frequency of 868 MHz resulting PLL division factor is 64 012 and the fractional part of 0 012 is smaller than 0 1 Note In multichannel systems prior to settling for a reference oscillator frequency each individual transmit frequency shall be checked for the PLL division factor which must be within the 0 1 0 9 range in order to avoid the occurrence of fractional Spurs In addition the RF frequencies used for the FSK deviation are not allowed to cross the PLL division factor integer line as in this case the lower and the higher FSK frequencies would have different integer part of PLL division ratio However this 2nd criterion is automatically fulfilled if the rule for the fractional part range stated above is fulfilled 2 4 5 4 The Bit Rate Generator The TDA5150 is able to generate a bit or chip clock by dividing the signal frequency output by the crystal oscillator ne SDIO PWRUP Divide by 12 4 8116 32 64 128 Divide by 1 to 256 Divide by 2 Divide by 1 2 4 8 XTAL Prescaler KE gt 50 50 gt Afterscaler Bitrate clock i 4 o 3 8 2 D 4 g g S S E d a m o x
68. capacitors listed in Table 6 the COG type is recommended Avoid the usage of XR7 type for those components as the tolerances and value of thermal coefficient may be rather high Data Sheet 94 V 1 1 June 2012 TDA5150 Applications Infineon Evaluation board V1 1 Infineon o 3 3 Lex TOL we UOOT T EX so 89 fiddns 1x3 SE 5 qas Lean O 3an E deat O Lee aN I TS ed T3 B zac 2 mus Ing A S Leg 8 OO Lee 2 REN IX za ZC ES Lear es He e BE ES T 0 O BZ Z ba pdr L T E a ugat 4 Z zt Te Go UT yaen L 149 ivan SI bz E 5 AO ul rt ws Nr SS zpa gt 2 i zu res ee E St St Lag Ir QNS bb ee at eebe wx gE sta E t T r s190 0005 N3 CS S ana seqoad 40 INS qd LL 8 7 9x STS aL il 5 Fol 99 gan zZ T TO Na V 1 1 June 2012 95 Schematics of Infineon Evaluation board V1 1 Figure 29 Data Sheet Cinfineon TDA5150 Applications X6 GND GND GND O RF OUT ALa c2 S Kei Match In VBat1 PA TDA5150 EB 1 1 O Figure 30 Data Sheet Component placement on Infineon Evaluation Board V1 1 top side 96 V 1 1 June 2012 Figure 31 Data Sheet TDA5150 CENTER i Jo 0101010101010 A OO
69. cy of SFR container is monitored by means of parity bits All other blocks are OFF Data Sheet 52 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description 2 4 9 3 TRANSMIT Mode This mode is automatically entered during a transmit command PLL and PA are active in this mode TRANSMIT is left with the falling edge of the EN line when bit B in the Transmit Command is 0 Otherwise TDA5150 remains in the transmit mode with PA and PLL in ON state until the time out of 65536 f occurs around 5 ms for a 13 MHz reference clock Normal voltage regulator is ON PORis ON BODis ON XOSC is ON PLLis ON PAis ON 2 4 9 4 XOSC ENABLE Mode This is a temporary mode after power up entered whenever SLEEP or STANDBY mode is left by a rising edge of the EN line This mode is automatically entered while SFRs are programmed XOSC ENABLE is left by GO2SLEEP GO2STANDBY commands by the 5 ms time out to enter automatically STANDBY or by a transmit command Normal voltage regulator is ON PORis ON BODis ON XOSC is ON e Clock divider is ON PLL and PA are OFF 2 4 9 5 PLL ENABLE Mode This is a temporary mode during a transmit command when the PLL is already activated but the PA is not switched ON yet Normal voltage regulator is ON PORis ON BODis ON XOSC is ON PLLis ON PA is OFF Data Sheet 53 V 1 1 June 2012 infineon TDA5150 TDA5150 Functional Description Powe
70. divided frequency input from multimodulus divider are compared in a phase detector At the output of the phase detector an error signal proportional to the phase difference of the two above mentioned signals is obtained The phase error signal is converted to a bipolar current by the charge pump and then fed into the loop filter integrator The output of this integrator controls the VCO frequency via the tuning voltage and so closing the loop The multimodulus divider is able to switch between different dividing factors Thus it is possible e g to divide by 2 5 by first dividing by 2 than by 3 followed by 2 again and so on The dividing factor is defined by the Sigma Delta Modulator 2 4 6 4 Fractional Spurs Due to the behavior of Sigma Delta PLLs spurs are generated at frequencies close to the integer multiples of the reference frequency These spurs are named Fractional Spurs It is therefore recommended to use PLL division ratios output RF frequency divided by crystal oscillator frequency with fractional parts between 0 1 and 0 9 or in other words the crystal frequency should be chosen in such way to yield for fractional part of the PLL division ratio values between 0 1 and 0 9 2 4 6 2 Voltage Controlled Oscillator VCO The Voltage Controlled Oscillator runs at approximately 1 8 GHz This is 2 4 or 6 times the desired RF output frequency dependent on the frequency band settings To trim out production tolerances of the
71. ds n 2 or the chip rate is twice the bit rate The TDA5150 supports the following encoding schemes Manchester code Differential Manchester code Bi phase space code Bi phase mark code Miller code Delay modulation NRZ Scrambling PRBS9 generator All encoded bitstreams can be level inverted as part of the encoding option Data 1 0 1 0 0 1 1 0 Clock LT I NRZ EN L manchester L MUMAN Differential Manchester JAFHETLELELLE UU Biphase Space L Biphase Mark Miller E UI PRBS Scrambling LI Figure 10 Coding Schemes Data Sheet 27 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description The Data Encoder option is enabled by bit C of Transmit Command Data Encoder enabled if bit C 1 See also Chapter 2 4 3 4 Transmit Command for command structure If the Data Encoder is enabled bit A must to be set for Synchronous Transmission Mode as well Bit A 1 and Bit C 1 this last to enable encoding The selection of encoding mode is done via bits ENCODE 0x05 2 0 of SFR TXCFG1 0x05 At the same time bit INVERT 0x05 3 of the same SFR enables the inversion of an already encoded bit stream The encoding activation entry point can be configured in SFR ENCCNT 0x27 By initializing the SFR ENCCNT 0x27 with 0x00 already the first bit is encoded If for example ENCCNT 0x10 the firs
72. e bits 10 8 are contained in GFXOSC register 0x1E Data Sheet 42 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x1E GFXOSC Gaussian Filter Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FHBLANK reserved reserved reserved GFBYP GFDIV GFDIV GFDIV w 0 w 1 w 1 w 1 w 1 w 0 wi w 0 Bit 7 FHBLANK Bit 3 GFBYP Gaussian filter bypass Bit lt 2 0 gt GFDIV Gaussian filter divider bit lt 10 8 gt sampling ratio of the Gaussian filter typically this value is set such that the GF divider is 16 x chip rate for ideal Gaussian filtering Note bits lt 7 0 gt are contained in GFDIV register 0x1D FHBLANK Frequency Hopping disable defines the jump from the TX TIMEOUT state 0 enable jump to TX ON state see also GFXOSC register description 0x1E 1 disable jump to PLL ON state GFBYP Gaussian filter bypass 0 GF enabled 1 GF bypassed GFDIV Gaussian filter clock divider value 11 bits bits 10 8 gt defines the 2 4 8 Power Amplifier ASK Modulator The RF signal generated by VCO and under the control of the Sigma Delta fractional N PLL is fed to a group of class C Power Amplifier stages and amplified before being transmitted The Power Amplifier PA includes an output power control ASK sloping switchable capacitors for antenna fine tuning and an auto switch off mechanism as pa
73. e PA is disabled thus preventing further transmission The after reset state for Fail Safe is active bit FSOFF set to 0 It is highly recommended to read the SFR Transmitter Status Register 0x01 before and after a transmission clear error flags if any and check for error free transmission 2 4 10 2 Low Battery Monitor The low battery detector monitors the supply voltage on Pin 5 VBAT If the voltage drops below 2 4 V a corresponding flag is set and the threshold is switched automatically to 2 1 V If this new threshold is also reached due to further voltage drop the 2 1 V flag bit is set in addition to the 2 4 V flag These Fail Safe flags are automatically cleared after each transmission start and content is not preserved like for Brownout Error Parity Error and PLL Lock Error bits Summary LBD 2VA set if battery voltage drops below 2 4 V LBD_2V1 set if battery voltage drops below 2 1 V Data Sheet 55 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description 2 4 10 3 SFRs related to Supply Voltage monitoring ADDR 0x01 TXSTAT Transmitter Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 n u LBD 2V1 LBD_2V4 VAC FAIL BROUTERR PARERR PLLLDER r 0 r 0 c 0 c 1 c 0 c 0 Bit 7 1 Set to 1 mandatory Bit 5 LBD_2V1 Low battery detected at 2 1 V Bit 4 LBD_2V4 Low battery detected at 2 4 V Bit 3 reserved Don t care Bit 2 BR
74. educe the current consumption and keeping in mind that leakage currents can steeply increase by high temperatures an additional low power state denoted SLEEP was defined In this state most of the digital part is disconnected from the regulator VREG Only the SPI bus interface remains active As a consequence further power saving is achieved but register content is lost by entering this mode See Chapter 2 4 9 Operating Modes for further informations 2 4 2 4 Brownout Detector A Brownout Detector abbreviated BOD is integrated into the TDA5150 transmitter Brownout is a condition where the supply voltage drops below a certain threshold level By brownout events the integrity of SFRs can not be guaranteed even if the dropout s duration is very short During active states BOD monitors the VREG pin during STANDBY it monitors VBAT and VREG supply lines Table 1 BOD Thresholds Description Monitored min max Brownout Detection VBDR VREG 1 7V 1 8V Level Active State Brownout Detection VPDBR VREG amp VBAT 0 7V 1 7V Level StandBy State If the BOD detects a brownout the Power Amplifier is switched off and the SFRs are reset The device is then forced to restart from the Power Up Reset condition This ensures that the device is always in a well defined logic state Data Sheet 19 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description VREG RESETN Figure 5 P
75. een the performance figures of the two mentioned boards and both may be regarded as equivalents in terms of RF performance Data Sheet 103 V 1 1 June 2012 Cinfineon mue Electrical Characteristics 4 Electrical Characteristics 4 1 Absolute Maximum Ratings Attention Stresses above the maximum values listed below may cause permanent damage to the device Exposure to absolute maximum rating conditions for extended periods may affect device reliability Maximum ratings are absolute ratings exceeding even one single of the values may cause irreversible damage to the integrated circuit Table 9 Absolute Maximum Ratings Parameter Symbol Values Unit Note min max Test Condition A1 Supply voltage VaaT 0 3 4 V A2 Junction T 40 125 C Temperature 40 150 1 Max 24 hrs by Tmax accumulated over lifetime 2 Vbar 73 6 V A3 Storage Ts 50 150 C Max 1000 hours Temperature by Tmax or Tmin A4 Transient Tian 175 C Max 180 sec Temperature 10 x Tcycles over lifetime A5 ESD HBM integrity Vuen 4 4 kV Acc to JEDEC all pins except EIA JESD22 pin 6 RF PA output A114 B A6 ESD HBM integrity Vigmrr 4 4 kV Acc to JEDEC pin 6 EIA JESD22 A114 B A7 ESD SDM integrity Vspy 500 500 V All pins except corner pins 750 750 V All corner pins A8 Latch up liu 100 mA AEC Q100 transient current A9 Maximum Input Vin 0 3
76. egister in such way that the GF divider NGF is 16 times the chip rate This allows optimum Gaussian filtering Data Sheet 41 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description 2 4 7 1 SFRs related to digital FSK GFSK Modulator ADDR 0x1C FDEV Frequency Deviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FDEVSCALE FDEVSCALE FDEVSCALE FDEV FDEV FDEV FDEV FDEV w 1 w 1 wl w 1 w 1 w 1 w 1 w 1 Bit 7 5 FDEVSCALE Frequency deviation scaling bit 2 07 Bit 4 0 FDEV Frequency deviation bit 4 07 FDEVSCALE Scaling of the frequency deviation 3 bits 000 001 010 011 divide by 64 divide by 32 divide by 16 divide by 8 100 101 110 111 divide by 4 divide by 2 divide by 1 multiply by2 FDEV Frequency deviation value 5 bits defines the multiplication value for the output data from the Gaussian filter 0 31 ADDR 0x1D GFDIV Gaussian Filter Divider Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV GFDIV w O w 0 w 0 w 0 w 1 w 0 w 0 w O Bit 7 0 GFDIV Gaussian filter divider bit 7 0 GFDIV Gaussian filter clock divider value 11 bits bits lt 7 0 gt defines the sampling ratio of the Gaussian filter typically this value is set such that the GF divider Ncr is 16 x chip rate for ideal Gaussian filtering Not
77. el C selected 3 11 frequency channel D selected for description of programming the frequency channels A D consult Chapter 2 4 11 3 Channel Hopping Note After the last configuration bit for a new transmission was sent a break of at least 100 us must be provided in order to achieve PLL settling and lock on the selected channel frequency 2 4 8 5 Timing Diagrams In the following timing diagrams the 4 possible SPI commands are shown The examples are valid for the case of SCK is low when EN line goes from Low to High rising edge Data Sheet 25 V 1 1 June 2012 Cinfineon bus TDA5150 Functional Description Therefore the incoming SDIO data is sampled at the falling edge of SCK and data is output on SDIO line by the rising edge of SCK signal WRITE SFR 0 j o sx MEHN immand Address Data Byte I lt pl gt 0 A5 J A4 A3 X A2 J A1 A0 4 D7 JD6D5 X D4 D3I D2 D1 DO X SDIO READ SFR EN eo MEUUUUUX 0 vtt Data Byte CS Comman d Address 7 gt it La e SDIO 0 1 XASXA4 A3 A2 A1 X AO CW NENH NENG BURST write SFR o RAT RAIA H EEEE Ld uuu Address Data Byte 0 Data Byte 1 8 E Ke a mand 27 EEEEEEEEEEEEEEEEIEI
78. equency of the ASK signal shaping using PA power stage switching Range from 0x000 to Ox3FF SLOPEDIV 1 SLOPEDIV 1024 ADDR 0x1B POWCFG1 PA Output Power Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 POUT2 POUT2 POUT2 POUT2 POUT1 POUT1 POUT1 POUT1 wi w 0 wi w 0 wi wi w 0 w 0 Bit lt 7 4 gt POUT2 Output power setting 2 bit lt 3 0 gt Bit lt 3 0 gt POUT1 Output power setting 1 bit lt 3 0 gt POUT2 PA output power setting 2 4 bits defines the number of enabled PA stages Range from 0x0 POUT2 0 to OxB POUT2 11 gt 0xB POUT2 11 POUT1 PA output power setting 1 4 bits defines the number of enabled PA stages Range from 0x0 POUT1 0 to OxB POUT1 11 gt 0xB POUT1 11 Data Sheet 50 V 1 1 June 2012 Cinfineon nes TDA5150 Functional Description ADDR 0x1F ANTTDCC Antenna Tuning and Duty Cycle Configurations Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reserved DCC DCCCONF DCCCONF TUNETOP TUNETOP TUNETOP TUNETOP DISABLE w 0 w 0 w 1 wl w 0 w 0 w 0 w O Bit 7 reserved Always use 0 Bit 6 DCCDISABLE Duty cycle control disable Bit 5 4 DCCCONF Duty cycle control delay configuration bit 1 0 Bit 3 0 TUNETOP Antenna tuning top capacitor bit 3 0 DCCDISABLE Duty cycle control disable must be 0 for ISMB 0 0 enabled 1 disabled delay Ops DCCCONF Duty cycle control delay configuration IS
79. esolution fractional N PLL synthesizer interconnected with a sigma delta modulator covers all of the above listed frequency bands using the same crystal for reference frequency and Baud rate generation All the major functions of the chip are controlled over SFR registers which at their turn are accessible over a 3 wire SPI bus Serial Peripheral Interface The user configurable digital modulator allows precise settings of FSK modulation parameters and Gaussian shaping GFSK which directly contributes to reduction of occupied bandwidth and efficient spectrum usage The output power of the integrated C class RF power amplifier is controlled over SFR registers and if necessary the power can be downsized reduced in digital steps The ASK shaping option contributes to reduced harmonics and minimized spectral splatter On chip antenna tuning capacitors are available the capacitor bank switching for antenna tuning is accomplished over SFR registers The data encoder supports NRZ Manchester Bi Phase and Miller encoding 1 2 Features High resolution Sigma Delta fractional N PLL synthesizer frequency step size down to 7 Hz e Multiband Multichannel capability for the 300 320 MHz 433 450 MHz and 863 928 MHz bands Modulation types ASK OOK with ASK shaping FSK CPFSK and GFSK Multi channel and channel hopping capability 4 register banks for fast Tx frequency switching Configurable via 3 wire serial interface bus SPI M
80. etting the GFBYP bit of SFR GFXOSC 0x1E 3 to 0 Data Sheet 39 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description The GFSK modulation scheme can further reduce the occupied RF bandwidth versus FSK modulation The ASK or FSK modulation type is selected by a bit field in SFR TXCFG1 0x05 There are two possible setups denoted ModulationSetting1 and ModulationSetting2 A field within Transmit Command byte referenced as bit D in Transmit Command byte selects one of the two settings as active This allows for fast commutation between modulation parameters without additional re configuration and repeated register downloads See also Chapter 2 4 3 4 Transmit Command for details RBW 10 kHz RF Att 30 dB Ref Lvl VBH 10 kHz Mixer 20 dBm 10 dBm SHT 54 ns Unit dBm oo Viens reese ee al rss E h V W _ ewes V ss N A uh W t ae Mit m 40l Center 434 02 MHz 0 kHz Span SOO kHz Figure 14 Spectrum for FSK and Gaussian FSK GFSK modulated RF signals both with 20 kbit s datarate and 35 kHz FSK deviation Blue plot corresponds to FSK and green plot to GFSK modulation The frequency deviation is configured using the bits FDEF 4 0 and FDEVSCALE lt 2 0 gt in the SFR FDEV 0x1C 7 0 and is calculated as follows o FDEVSCALE 2 07 190 x FDEV lt 4 0 gt x 9 5
81. exibility and freedom in setup and configuration if used as evaluation or reference system by customers Applications 3 1 Simple application schematics example VBAT XTAL TIM IRQ uC clocked by TDA5150 SPI bus controlled by pC C1 a or C2 13 00 MHz 100 nF lieu TDA5150 ZE XTAL 82pF VREG Antenna GNDPA GND Remarks values valid for 433 MHz and the given A antenna geometry EN SDIO DATA XTAL SCK GND CLKOUT VREG 3 0mm GNDPA VBAT rt 3 0mm l L l I U l Le 4 9mm Figure 23 Simple application example with reduced Bill of Materials list Data Sheet 86 V 1 1 June 2012 TDA5150 Ineon infir Applications Infineon Evaluation Board V2 3 2 T EX fitddns 1x3 QNS sas ivan d 2 I Le nas T deu 90 8 Sug 6a 82 Tdf NOLIURILOS HOTON tran zu 1 M E EEN al Heat legal E de le ata 3 ino a O t Fc 98 O O S z3 1 Ee ut Be deu ud I HUS edt ra ea ugar A T 23 3 zx ts ivan bgt gaan eit oa mme SE
82. for Channel C Data Sheet 74 V 1 1 June 2012 infineon TDA5150 TDA5150 Functional Description ADDR 0x14 PLLFRACC2 PLL Fractional Division Ratio Channel C byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O n u n u reserved PLLFRACC2 PLLFRACC2 PLLFRACC2 PLLFRACC2 PLLFRACC2 w 0 w 1 w 0 w 0 wi wi Bit 5 reserved Set to 0 Users are advised to leave the state of this bit unchanged Bit 4 0 PLLFRACC2 Factional division ratio bit 20 16 PLLFRACC2 Synthesizer channel frequency value 21 bits bits 20 16 gt fractional division ratio for Channel C ADDR 0x15 PLLINTD PLL MM Integer Value Channel D Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u PLLINTD PLLINTD PLLINTD PLLINTD PLLINTD PLLINTD PLLINTD w 1 w 0 w 0 w 0 w 0 wl w 0 Bit lt 6 0 gt PLLINTD Integer division ratio bit lt 6 0 gt PLLINTD Multi modulus divider integer offset value 7 bits for Channel D ADDR 0x16 PLLFRACDO PLL Fractional Division Ratio Channel D byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO PLLFRACDO w 0 w 0 wi w 0 wi w 0 wi w 0 Bit lt 7 0 gt PLLFRACDO Fractional division ratio bit lt 7 0 gt PLLFRACDO Synthesizer channel frequency value 21 bits bits lt 7 0 gt fr
83. ion of Evaluation Board V2 added see Infineon Evaluation Board V2 Description of former board version moved to subchapter Schematics of Infineon Evaluation board V1 1 Values in Table PLLBW TRIM on Page 84 and associated Note on same page updated in accordance with the PLL settings listed in Table 2 Range of nominal PLL Bandwidth values PLLBW Listed in Datasheet V1 0 90 120 150 180 210 240 270 kHz Listed in Datasheet V1 1 150 175 230 270 335 375 410 kHz by chargepump current of 5 7 5 12 5 17 5 25 32 5 40 pA Note 1 chargepump current values are unchanged and the same in both Datasheets 2 no changes operated in Table 2 regarding the PLL bandwidth or chargepump current settings Data regarding load drive capability of SDIO pin added Data regarding load drive capability of SDIO pin added to Table 13 We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or missing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to wirelesscontrol infineon com E Cinfineon cca 1 1 1 1 2 1 3 1 4 1 5 1 5 1 1 5 2 1 5 3 1 5 4 1 5 5 1 5 6 1 5 7 2 2 1 2 2 2 3 2 4 2 4 1 2 4 2 2 4 2 1 2 4 2 2 2 4 2 3 2 4 3 2 4 3 1 2 4 3 2 2 4 3 3 2 4 3 4 2 4 3 5 2 4 4 2 4 4 1 2 4 4 2 2 4 5 2 4 5 1 2 4 5 2 2 4 5 3 2 4 6 2 4 6 1 2 4 6 2
84. it 2 Bit 1 Bit 0 SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV SLOPEDIV w 1 w 0 wl w 0 wl wl wl w 0 Bit lt 7 0 gt SLOPEDIV ASK sloping clock divider bit lt 7 0 gt SLOPEDIV ASK sloping clock division ratio 10 bits bits lt 7 0 gt defines the slope of the ASK signal shaping using PA power stage switching Range from 0x000 to Ox3FF SLOPEDIV 1 SLOPEDIV 1024 ADDR 0x1A POWCFG0 PA Output Power Configuration Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA_PS2 PA_PS2 PA_PS2 PA PS1 PA PS1 PA PS1 SLOPEDIV SLOPEDIV w 0 w 0 wi w 0 wi w 0 wi w 0 Bit lt 7 5 gt PA_PS2 PA output blocks setting 2 bit lt 2 0 gt Bit lt 4 2 gt PA PS1 PA output blocks setting 1 bit lt 2 0 gt Bit lt 1 0 gt SLOPEDIV ASK sloping clock divider bit lt 9 8 gt PA_PS2 Individual control of the 3 PA blocks setting 2 3 bits 0 disabled 1 enabled Bit 0 gt Bit 1 gt Bit 2 gt PA block 0 PA block 1 PA block 2 PA_PS1 Individual control of the 3 PA blocks setting 1 3 bits 0 disabled 1 enabled Bit 0 gt Bit 1 gt Bit 2 gt PA block 0 PA block 1 PA block 2 SLOPEDIV ASK sloping clock division ratio 10 bits bits lt 9 8 gt defines the frequency of the ASK signal shaping using PA power stage switching Range from 0x000 to Ox3FF SLOPEDIV 1 SLOPEDIV 1024 Data Sheet 77 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description
85. lity is listed in Table 4 3 Data Sheet 21 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description e SCK clock input pin with embedded pull down resistor If SCK is at low level while EN goes high the incoming SDIO data is sampled by falling edge of the SCK and the output SDIO data is set by the rising edge of SCK Contrariwise If SCK is at high level when EN goes high the SDIO data is sampled with the rising edge of the SCK clock and output on SDIO by falling edge of the SCK clock For details refer to Figure 6 and Figure 7 SPI commands are started by the rising edge on the EN line and terminated by the falling edge on EN The available Burst Write mode allows configuration of several SFRs within one block access without cycling the EN line Low High Low for each individual byte By keeping the EN line at High level subsequent bytes could be sent and the byte address counter is autoincremented thus speeding up the transfer on the SPI bus A self explaining diagram is found here Chapter 9 Timing Diagrams of 3 wire SPI The active edge of SCK during SPI commands is programmable and it is determined by the level on SCK line at the moment of activation of the EN line rising edge on EN If SCK is low at that moment the incoming SDIO data will be sampled with the falling edge of SCK and output by rising edge of SCK see Figure 6 below EN SCK SDIO Figure 6 SPI Timing SC
86. n Water Product Description 1 5 3 Reduction of Spurs and Occupied Bandwidth The direct FSK modulation and in addition the Gaussian FSK GFSK reduces spurs and occupied bandwidth Bandwidth reduction is exemplified below RBW 10 kHz RF Att 30 dB Ref Lvl VBH 10 kHz Mixer 20 dBm 10 dBm SHT 54 ns Unit dBm E ek 10 AT A Tu diee Mets 4d Center 434 02 MHz SO kHz Span SOO kHz Figure 2 Spectrum of RF signals with equal frequency deviations 35kHz same 20 kBit s datarate and encoding NRZ Blue plot corresponds to FSK modulation and green to GFSK Observe the difference in terms of occupied bandwidth between the signals 1 5 4 Asynchronous and Synchronous Transmission TDA5150 offers a simple asynchronous transmission mode transparent modulation whereby after the configuration word is downloaded into the transmitter s SFRs via SPI bus the data bitstream is output on the SDIO line and fed into the transmitter s RF modulator The CLKOUT signal can be used either as clock line for host uC or alternatively as timer base flag for bitrate generator this last function have to be implemented in the uC In this mode the bitrate is solely imposed and controlled by the uC software GFSK modulation and ASK shaping options are allowed in Asynchronous Mode In Synchronous Transmission Mode the bitra
87. n and Data Encoding ADDR 0x05 TXCFG1 Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GO2SLEEP ASKFSK2 ASKFSK1 ASKSLOPE INVERT ENCMODE ENCMODE ENCMODE cw 0 w 0 w 1 w 0 wl w 1 w 0 w 1 Bit 3 INVERT Data inversion Bit lt 2 0 gt ENCMODE Encoding mode bit lt 2 0 gt INVERT Encoded data inversion enable 0 data not inverted 1 data inverted ENCMODE Encoding mode code selection 3 bits 000 010 100 110 Manchester Biphase Miller Scrambling Space Delay PRBS 001 011 101 111 Differential Biphase NRZ not used Manchester Mark data 7 0 ADDR 0x08 PRBS PRBS Start Value Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRBS PRBS PRBS PRBS PRBS PRBS PRBS PRBS w 1 w 0 w 1 w 0 w 1 w 0 w 1 w 1 Bit 7 0 PRBS PRBS start value bit 7 0 PRBS PRBS start value 8 bits The PRBS generator uses this value as a starting value after begin of each transmission Data Sheet 30 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description ADDR 0x27 ENCCNT Encoding start bit counter Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT ENCCNT w 0 wi w 0 w O w 0 wl wl w 0 Bit lt 7 0 gt ENCCNT Encoding start bit counter bit 7 0 ENCCNT Sets the number of bits on start of a telegram which shall be sent unencoded or unscrambled before encoder scrambler is Switched on This feature
88. neon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered TDA5150 Revision History V1 1 Previous Version V1 0 issued July 2009 433 MHz band lower 433 MHz frequency band lower limit min referred in several limit changed paragraphs changed from previous value of 425 MHz to 433 MHz recent value Chapter 2 4 5 Detailed explanations about avoidance of fractional spurs added to Crystal Oscillator and Clock Divider subchapter Chapter 2 4 11 2 Detailed description of chip internal synchronization mechanism added to Synchronous Transmission subchapter Table 4 four individual bits in synthesizer register bank SFRs reassigned to reserved class Four bits previously referenced as FRACCOMPx reassigned to reserved class Notes 1 The affected bits are 0x0C 5 0x10 5 0x14 5 and 0x18 5 2 The change has no impact on chip functionality 3 After reset state of all four above mentioned bits is O i e no change versus previous Datasheet V1 0 Description of Evaluation Board V2 added to Chapter 3 2 Descript
89. odulated RF signal without regard on the state of SCLK line which could be Low or High To keep crosstalk between SCLK and SDIO at minimum level it is recommended to keep SCLK at a steady level instead of toggling it usually by the uC 2 4 11 1 Asynchronous Transmission In Asynchronous Transmission Mode also referred as Transparent Mode the data on SDIO is directly input into modulator and converted into RF carrier There is no internal Data Sheet 58 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description synchronization with the bit rate clock The CLKOUT programmed to the proper bit rate or a multiple of it may be used by the host to time and shift into SDIO line the bits to be transmitted The Encoder and Scrambler can not be used and are automatically bypassed It is not recommended to use GFSK in conjunction with Asynchronous Transmission Mode as the frequency steps are timed with 1 16 of the bit rate chip rate clock Timing differences between the internal bit rate clock and the uC clock may cause unwanted jitter in the transmission GFSK modulation is intended to be used rather in conjunction with Synchronous Transmission Mode TRANSMIT data Asynchronous Transmission EN gt 1000 us if TX issued from STDBY else determined by SCK speed 100us fi H o SCK VIVIVIVIVIViy Y A Comman Configuration Data to transmit L
90. onnector 100 mil 12 pin connection to uW Link Motherboard 1 30 SV connector 100 mil 12 pin connection to uW Link Motherboard 2 31 X1 connector SMA RF port 32 X2 connector SMA not placed used only for system tests 33 X3 connector 100 mil 2 pins External supply 34 X6 connector 100 mil 6 pins GND for probes 35 X7 connector 100 mil 8 pins Test points 36 X8 connector 2x20 pin SIB connector Note RF output power and frequency band dependent component values are listed in Table 6 Data Sheet 93 V 1 1 June 2012 me Cinfineon oe Applications Table 6 Frequency and RF output power dependent component values Infineon Evaluation Board V2 Frequency band and C C5 C3 L L Note RF output power 315 MHz band 918 5 dBm 2 7pF 100pF 15pF 72nH 100 nH Board version orderable over ISAR 315 8 dBm 2 7pF 100pF 10pF 72nH 100 nH 315 10 dBm 2 7pF 100pF 5 6pF 72nH 100 nH 434 MHz band 434 5 d m 1 5pF 33pF 12 pF 51 nH 51nH m Board version orderable over ISAR 434 8 dBm 1 5pF 33pF 6 8pF 51nH 51nH 434 10 d m 1 5pF 33pF 47pF 51nH 51nH Board version orderable over ISAR 868 MHz band 868 5 dBm 868 8 dBm 868 10 d m 2 2pF 68pF 5 6pF 10nH 9 5nH m Board version orderable over ISAR 915 MHz band 915 5 dBm 915 8 dBm 1 5pF 68pF 4 7pF 9 5nH 8 7 nH Board version orderable over ISAR Attention for the
91. ower on Reset Brownout Detector Brownout is indicated by bit BROUTERR 0x01 2 within SFR TXTSTAT 0x01 Note The BOD itself can not be used to guarantee the correct operation of analog sections where the minimum operating voltage is defined to be 1 9 V as this is larger than the maximum BOD voltage In other words in case of a supply voltage drop the voltage region which is critical for reliable operation of the analog sections min 1 9V is reached before the brownout detector triggers between 1 8 1 7V See also Chapter 4 2 for operating voltage limits 2 4 2 2 Low Battery Detector TDA5150 has an embedded Low Battery Detector LBD block In active modes LBD monitors the voltage on VBAT supply line pin 5 LBD has two activation thresholds set to 2 4 V and 2 1 V The status regarding supply voltage below threshold events can be updated by reading from SFR TXSTAT bits 4 and 5 0x01 5 4 These LBD flags are cleared after every transmission start The LBD might be used as early warning for low battery voltage state but before the battery voltage is dropping below the critical value which renders normal operation capability Data Sheet 20 V 1 1 June 2012 Cinfineon ae TDA5150 Functional Description 2 4 2 3 SFRs related to Supply Voltage monitoring ADDR 0x01 TXSTAT Transmitter Status Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
92. ponent count application circuit The TDA5150 application circuit shown demonstrates the ease and simplicity of an intelligent transmitter implementation The uC configures the TDA5150 via 3 wire SPI the SDIO line is used at the same time to transfer data on SPI bus and as digital data input into the RF modulator The CLKOUT line may be used as clock source for the uC or as a timer for bitrate generation Data Sheet 7 V 1 1 June 2012 Cinfineon Water Product Description The matching shown is an example for a loop antenna application Different antenna types electrical monopole or dipole magnetic loop etc as well as different layout versions might require component values which can differ from those given in above example The antenna geometry has a major influence on the antenna impedance and consequently on the component values in the matching network 1 5 2 Sigma Delta fractional N PLL with High Resolution This type of PLL offers a multitude of advantages compared to fixed integer division ratio PLLs In the reference oscillator circuit the same crystal can be used for all of the RF bands and channel frequencies for example 13 MHz and alternatively 13 56 MHz crystals are listed in the Evaluation Board descriptions Chapter 3 2 Infineon Evaluation Board V2 and Chapter 3 3 Infineon Evaluation board V1 1 for all versions independently of intended operating frequency band Thus dedicated crystals for each carrier frequency like
93. r On Reset EN 1 amp Activity on SCK gt clock pulses Transmit command XOSC_ENABLE PLL_ENABLE PA OFF Timeout 1 or GO2STDBY 1 PA OFF during frequency hop SCK edge detected EN 0 and TXCFGB 0 STANDBY TRANSMIT PA ON PA ON during Timeout 1 frequency hop and TXCFGB 1 Figure 19 Simplified State Diagram of the TDA5150 2 4 9 6 SFRs related to Operating Modes ADDR 0x04 TXCFG0 Transmitter Configuration Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GO2STDBY reserved reserved FSOFF ISMB ISMB reserved reserved cw 0 w 0 w 0 w 0 w 0 w 1 w 1 w 0 Bit 7 GO2STDBY 1 go to StandBy cleared after 1 is written ADDR 0x05 TXCFG1 Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O GO2SLEEP ASKFSK2 ASKFSK1 ASKSLOPE INVERT ENCMODE ENCMODE ENCMODE cw 0 w 0 w 1 w 0 w 0 w 1 w 0 w 1 Bit 7 GO2SLEEP 1 go to Sleep Note after execution of this command all SFR content is lost Data Sheet 54 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 10 Fail Safe Mechanism and Status Register 2 4 10 1 Fail Safe Flags The status of the TDA5150 is continuously monitored during active state by the integrated Fail Safe mechanism which includes Brownout Error
94. ransmitter Status Register 0x01 should be read in order to clear bits set by previous errors if any Every transmission starts with a Transmit Command C1 CO Transmit Command Configuration Bit Function Value description 1 1 A Data sync 0 off 1 on at the same time Bit C Encoding must be set also to 1 gt Int Encoding 1 1 B PA mode 0 PA off at the falling edge of EN synchronized with bit rate if bit A is high 1 SDIO DATA is latched at the falling edge of EN PA stays on TX data are kept constant After the time out of 65536 f which is 5 ms for a 13 MHz crystal PA and PLL are switched off 1 1 C Encoding 0 off 1 on selects SFR register for encoding Bit A must be also set to1 gt Data sync 1 1 D Pwr level 0 selects PowerLevel Modulation Setting1 ModSetting 1 selects Power Level Modulation Setting2 1 1 lt E F gt Frequency 0 00 selects frequency channel A selection 1 01 selects frequency channel B 2 10 selects frequency channel C 3 11 selects frequency channel D For description of frequency channels A D programming procedure please see Chapter 2 4 11 3 Channel Hopping The Transmit Command byte is sent via SPI and identified by the first two bits designated CO and C1 These two bits are mandatory set to 1 The following 6 bits designated bit A bit F specify the transmission details e A Synchronous 1 or asynchronous 0
95. rity bits belonging to SFR content are continuously recalculated and compared against the stored values Changes in the contents of writable SFRs without write command generate an SFR error event and an error flag is set To prevent erroneous transmissions on wrong frequency or with erroneous modulation parameters the activation of Fail Safe mechanism is coupled with deactivation switching off of the RF Power Amplifier stages This additional feature inhibits the transmission if errors occur thus preventing the transmission of erroneous datagrams or on false frequency For details see the associated SFR description and their interaction with the Fail Safe Mechanism as described in Chapter 2 4 10 Data Sheet 10 V 1 1 June 2012 Cinfineon dx Product Description 1 5 7 TESEUS Configuration and Evaluation Tool V TESEUS for TDA5150 sl A File Edit Mode Help General XOSC Encoding SIB Jeu PA Modulation Transmission o XTAL Settings p CLKOUT Settings 4 TX Configuration Registers g Xtal Freq MHz 13 000 CLKOUT LS Disabled 0 1 Enabled Ge2sieep a CLKOUT Selection 5 sits Prescaler Counter S S CLKOUT XTAL 16 Goto Standby Encoding Mode ofo J 1 Standby 5 nez d Calculator E Afterscaler CLK Div Power Down XOSC amp Bypass Enable 0 J 1 Power Down DEEE Prescaler CLK Div NENNEN Not Inverted 0 J 1 Inverted B
96. rt of the Fail Safe system If critical supply voltage drop or frequency error events occur the Fail Safe mechanism switches the PA off thus preventing erroneous transmissions Data Sheet 43 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description eege SR matching from SDPLL PA network external ASK sloping ASK data J Figure 16 Transmitter Blocks In FSK or GFSK mode the PA is always ON during the transmission s duration By ASK mode the SDPLL delivers a continuous RF signal to the PA The PA is switched ON and OFF according to the data signal to be transmitted Additionally there is an ASK sloping mechanism which switches the different power stages ON and OFF in a well determined sequence correlated with the transitions on data signal line This power ramping procedure minimizes out of band transients and spectral splatter 2 4 8 1 PA Output Power Programming The PA comprises 11 elementary cells in parallel Each one is a class C amplifier The cells are grouped in three PA blocks PA Block 0 is composed of 9 stages PA Block 1 and PA Block 2 are strong single stages Each PA Block can be individually enabled and disabled to optimize power consumption and efficiency in an output power subrange The overall 11 PA stages allow control of the RF output power in 11 steps over a range of 20 dB The PA can be switched OFF by disabling all the 11 stages
97. s caused for example by interrupt reaction latency are compensated neutralized by the synchronization If Synchronous Mode will be used the following aspects have to be kept in mind The data sampling is being done always on the falling edge of the internal baudrate clock Theinitialization of the internal baudrate clock at the SCLK edge is working properly starting with 0 only if the prescaler is set to division by 1 in all other cases the baudrate clock begins with the opposite phase 1 and therefore there is a half bit delay caused by data sampled on falling edge The initial phase of the CLKOUT is determined by the CLKOUT state and internal baudrate clock at SCLK edge invert CLKOUT SCLK If the prescaler is not set to division by 1 the initial CLKOUT phase is additionally depending on the timing between the clock generated by the prescaler and SCLK edge if prescaler clock generated SCLK edge additional CLKOUT inversion is done This means that the minimum baudrate with prescaler ratio at division by 1 at which the baudrate clock is generated properly is BDR f_xosc 256 2 8 which yields for 13 MHz reference frequency 3 173 kB s where PRESCALE 1 BDRDIV 255 and AFTERSCALE 8 Therefore it is advisable to avoid lower datarates in this mode A workaround is described in the Application Note AN Programming the TDA5150 V2 0 pdf Data Sheet 60 V 1 1 June 2012 Cinfineon fouet TDA51
98. s of typically 60 fF 120 fF 240 fF and 480 fF giving an overall maximum capacitance of about 0 9 pF Note Due to the low Q Factor of the switched capacitors at the higher frequencies the current consumption of the device tends to increase if this tuning option is used in the higher frequency bands 868 MHz and 915 MHZ 2 4 8 5 Fail Safe PA Switch Off To prevent erroneous transmissions on wrong frequency or with erroneous modulation parameters altered payload etc the activation of Fail Safe mechanism is coupled with deactivation switching off of the RF Power Amplifier stages If critical errors occur the Fail Safe mechanism incorporated in the TDA5150 is activated provided the detection enable bit is armed i e bit FSOFF in SFR TXCFGO 0x04 4 is 0 Observe that this corresponds to the after reset state In other words by exiting the reset state the Fail Safe detection is already armed but it can be deactivated anytime by Data Sheet 47 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description changing its control bit state to High bit FSOFF 1 0x04 4 or rearmed by setting it to Low If the detection is armed RF Power Amplifier drivers are automatically switched OFF in case of an error to prevent erroneous transmissions This happens if at least one of the following events occurs Parity error in the SFRs Brownout event event sensed by the brown out detector BOD PLL lock failure is detected e
99. selected by means of a 3 bit control field designated PLLBWTRIM in the SFR register PLLBW 0x25 6 4 Aiming the minima of RF energy leaking into the adjacent channel s and or out of band transmissions the PLL bandwidth should be set as narrow as possible but not less then 1 5 2 times the chip rate if FSK or GFSK modulation is used For NRZ encoding the chip rate and data and bit rate are the same For all other encoding schemes like Manchester or Bi Phase etc each bit is represented by two chips Therefore the chip rate is the double of the bit rate for all encoding schemes implemented in the TDA5150 encoder excepting NRZ The chip rate is not influenced by the fact whether the encoding is done by the on chip Data Encoder or is realized externally In order to maintain the PLL loop stability and for optimum performance the chargepump and loop filter settings as listed in Table 2 have to be used Note current settings and associated loop filter damping factors are correlated Table 2 PLL recommended settings Loop filter Chargepump settings Resulting Notes damping resistor and resulting current nominal selection PLL BW PLLBW TRIM CPTRIM CP current kHz Bit2 Bit1 BitO Bits Bit2 Bit1 BitO uA 0 0 0 KR j not recommended 0 0 1 1 1 1 1 40 410 0 1 0 1 1 0 0 32 5 375 0 1 1 1 0 0 1 25 335 1 0 0 0 1 1 0 17 5 270 1 0 1 0 1 0 0 12 5 230 1 1 0 0 0 1 0 7 5 175 1 1 1 0 0 0 1 5 150
100. settings steered by bit field value D 0 or D 1 with choice between ASK and FSK modulation The settings are not coupled i e one bank could be set for ASK modulation and the other for FSK for example Further if FSK is chosen as modulation type enabling of Gaussian filtering is another option but not mandatory See also Chapter 2 4 4 2 SFRs related to Transmitter Configuration and Data Encoding RF PA block activation controlled by bit fields PA PS1 0x1A 4 2 respectively PA PS2 0x1A 7 5 of the SFR Output Power Configuration Register 0 0x1A for the two transmission settings RF PA output power selection controlled by the bit fields POUT1 0x1B 3 0 respectively POUT2 0x1B 7 4 of the SFR Output Power Configuration Register 1 0x1B for the two transmission settings If D 0 following fields are selected ASKFSK1 together with PA PS1 and POUT1 If D 1 following fields are selected ASKFSK2 together with PA PS2 and POUT2 E F RF Frequency selection as configured in PLL MM Integer Value registers A B C D 0x09 0x0D Ox11 0x15 and the PLL Fractional Division Ratio registers A B C D 0x0A 0x0C OxOE 0x10 0x12 0x14 0x16 0x18 After the transmit command have been sent the SCLK line has to stay low for at least 100 us i e settling time of the PLL A rising edge of the SCLK line after this break activates the PA and starts the transmission The digital data is input into the transmitter via the SDIO line and transposed into m
101. t Digital FSK GFSK Modulator 39 SFRs related to digital FSK GFSK Modulator 42 Power Amplifier ASK Modulator 43 PA Output Power Programming 44 ASK Modulation and ASK Sloping 45 Duty Cycle Control 46 Antenna Tuning 47 Fail Safe PA Switch Off 47 SFRs related to RF Power Amplifier and ASK Modulator 49 Operating MOdeS scr eek Re eme Ep t nd RR RR Ra E S 51 SLEEP MOde us Ki e tente eed ELE Eea EE ee Bek ane 51 STANDBY Mode Data Retention Mode 52 TRANSMIT Mode 244 Gun dk bing nee EE re PIRE Pam Eas 53 XOSC ENABLE Mode 53 PLL ENABLE Mode 2 me dangers 53 SFRs related to Operating Modes 54 Fail Safe Mechanism and Status Register 55 Fail Safe Flags 55 Low Battery Monitor 55 SFRs related to Supply Voltage monitoring 56 RF Data Transmission 56 Asynchronous Transmission 58 Synchronous Transmission 59 Channel HOPPING 22 perse x ILE Remb ES Ends 61 SFRs related to Channel Hopping
102. t 1 07 Bit 3 1 PRESCALE Pre scaler selection bit 2 0 Bit O CLKOUTENA Enable clock output CLKSRC Clock output selection 2 bits 00 01 10 11 prescaler BDRDIV inverted afterscaler clock counter BDRDIV clock clock counter clock AFTERSCALE Post scaler clock divider selection 2 bits 00 01 10 11 divide by 1 divide by 2 divide by 4 divide by 8 PRESCALE Pre scaler clock divider selection 3 bits 000 001 010 011 divide by 1 divide by 2 divide by 4 divide by 8 100 101 110 111 divide by 16 divide by 32 divide by 64 divide by 128 CLKOUTENA Clock output enable 0 disable instead of clock the Crystal 1 enabled Oscillator stable signal causes a rising edge on CLKOUT Enabled also automatically when default clocking fsys 16 is used when the SDI input is low at the rising edge of the EN after power up Data Sheet 69 V 1 1 June 2012 Cinfineon alae TDA5150 Functional Description ADDR 0x07 BDRDIV Bit rate Divider Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV BDRDIV w 1 w 0 w 0 w 0 w 0 w 0 w 0 w 0 Bit lt 7 0 gt BDRDIV BDRDIV divider bit lt 7 0 gt BRDRDIV Along with the pre scaler and the post scaler Bitrate clock divider value 8 bits defines the data bit rate according to following formula Range from 0x00 BDRDIV
103. t 16 bits should remain unencoded This method allows to keep the first N bits unencoded within a datagram in fact plain NRZ followed by encoded bits of the same datagram The encoding scheme is selected by bit field ENCMODE 0x05 2 0 of SFR TXCFG1 2 4 4 1 PRBS9 Generator Data Scrambler TDA5150 contains a PRBS9 generator suitable for generation of pseudo random NRZ data patterns The PRBS9 datastream satisfies in general lines the requirements for random distribution even if longer PRBS polynomials come closer to true random distribution and therefore it may be useful for Transmitter RF tests for instance by measurement of the Occupied RF Bandwidth test case In addition the generated PRBS9 pattern can be XOR ed with a real data pattern sent by the microcontroller and this way scramble this data pattern Attention The data scrambling functionality is intended to enhance the clock recovery performance of the Receiver Station It is not suitable as stand alone encryption method for security applications PRBS9 is a well known standard in the class of pseudo random patterns and is implemented within the TDA5150 by a subpart with following block diagram 0 PRBS Start value loaded start of TX 3 2 BDR CLK t t t to BM S 4 i S gt modulator S A SE n 4 o o E v
104. t 3 Bit 2 Bit 1 Bit 0 reserved reserved reserved reserved reserved reserved reserved reserved wi w 0 wi w 0 wi w 0 wi wi Bit 7 0 reserved Reserved set to 0 Data Sheet 83 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x24 CPCFG Charge Pump Configurations Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 n u reserved reserved reserved CPTRIM CPTRIM CPTRIM CPTRIM w 0 w 1 wl w 0 w 1 wl w 0 Bit lt 6 4 gt reserved Reserved Bit lt 3 0 gt CPTRIM Charge pump current trimming bit lt 3 0 gt CPTRIM Charge pump current trimming 4 bits Range from 0x0 to OxF step current 2 5 pA current 40 pA 2 5 uA Note CPTRIM bits must be set correlated with PLLBW bits otherwise loop instability may occur ADDR 0x25 PLLBW PLL Bandwidth Configuration Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reserved PLLBW PLLBW PLLBW reserved reserved reserved reserved TRIM TRIM TRIM w 1 w 1 w 0 w 1 w 1 w 0 wi wi Bit 7 reserved reserved Bit 6 4 PLLBWTRIM Trim bandwidth of the PLL loop filter bit 2 07 Bit 3 0 reserved reserved PLLBWTRIM Trim bandwidth of the PLL loop filter 3 bits Range from 0x1 to 0x7 Typical BW 410 kHz BW 150 kHz step 43 kHz Note PLLBW must be set together with CPTRIM according to following table
105. te is solely under the transmitter s control and fully timed by the TDA5150 The CLKOUT is used to alert the uC about the request for next data bit The uC may have a higher allowable processing delay tolerance typically the duration of 1 2 bit before sending the corresponding bit via SDIO line to transmitter Usage of data encoding option is allowed in Synchronous Mode Data Sheet 9 V 1 1 June 2012 Cinfineon Water Product Description 1 5 5 Integrated Data Encoder TDA5150 comprises a Data Encoder which automatically generates encoded data from a regular NRZ bitstream The supported data encoding modes are Manchester code Differential Manchester code Bi phase space code Bi phase mark code Miller code Delay modulation NRZ Scrambling PRBS9 generator All the encoded bitstreams can be level inverted as part of the encoding option The scrambling module PRBS9 generator is intended to be used for generation of pseudo random data patterns rather for Tx test scopes or for basic level data encryption 1 5 6 Fail Safe Mechanism The Transmitter Status Register reports about failures such as Brownout event PLL lock error VCO auto calibration error and Register Parity error The Register Parity is a special safety feature Each SFR Special Function Register has an extra parity bit which is automatically calculated and stored during a SFR write operation During transmitter active state these pa
106. ted if 1 NOTE bit invalid in standby mode BROUTERR Brownout error detected if 1 PARERR Parity error detected if 1 PLLLDERR PLL lock error detected if 1 Data Sheet 66 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description ADDR 0x04 TXCFG0 Transmitter Configuration Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GO2STDBY reserved reserved FSOFF ISMB ISMB reserved reserved cw 0 wl w 0 w 0 w 0 w 1 w 1 w 0 Bit 7 GO2STDBY Go to StandBy Bit 6 reserved Reserved set 0 Bit 5 reserved Reserved set to 0 Bit 4 FSOFF Fail Safe mechanism turned off Bit 3 2 ISMB RF frequency band bit 1 0 Bit 1 reserved Reserved set to 1 Bit O reserved Reserved set to 0 GO2STDBY Put the chip in STDBY mode look at the detailed state diagram cleared after 1 is written FSOFF Fail Safe mechanism 0 on 1 off ISMB ISM band selection 2 bits 00 MHz 01 MHz 10 MHz 11 MHz 300 320 433 450 863 870 902 928 Important notice It is mandatory to maintain the default values as specified in the respective register tables for all reserved Special Function Registers SFR reserved bits reserved bit fields Data Sheet 67 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x05 TXCFG1 Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit
107. the transmitter part tested under control of software provided by Infineon Technologies AG while the firmware for the final application Host is still in development Total current consumption of the transmitter may be monitored by replacing the jumper JP2 with a milliampermeter The current drained by the RF power amplifier stage can be measured in a similar manner if jumper JP3 is replaced with a milliampermeter Infineon Technologies AG delivers a software tool designated TESEUS which may be used in conjunction with TDA5150 systems for initialization transmission parameter setup frequency modulation mode transmission speed encoding etc and generation of data frames The specific settings may be stored retrieved and exported in several formats C header or Special Function Register list as text file and are displayed in a user friendly Graphical User Interface GUI module For details about TESEUS tool please refer to Chapter 1 5 7 The complete documentation of the TDA5150 Evaluation Board V2 including schematics and layout as pdf file eBOM spreadsheet and Gerber files of the printed circuit board can be downloaded free of charge from the following link http www infineon com TDA5150 Note the layout of components and tracks included in reference oscillator block and RF matching network is practically the same on the two Evaluation Board versions V2 and V1 1 At the same time the nominal value of the components included in
108. transmission details are described later in this chapter B If 0 the PA is switched off by the falling edge of the EN line If 1 the SDIO line is latched with the falling edge of EN the PA stays active continuing to transmit according to the latched SDIO state After a time out duration of 65536 fsys 5 ms for a 13 MHz reference clock both the PA and PLL are switched off if no other SPI command starts a new transmission This feature helps to keep the transmitter Data Sheet 57 V 1 1 June 2012 Cinfineon fouet TDA5150 Functional Description sending despite the fact that the EN line is pulled to Low state normally a stop condition for Transmitter Pulling the EN line to Low in between SPI command blocks is required by SPI protocol if commands are not sent in burst mode C If C 0 the Encoder is not used If C 1 the Encoder is used as configured in the Transmitter Configuration Register 1 bits ENCMODE 0x05 2 0 D Switch between two subsets of transmission parameters referenced as PowerLevel Modulation Setting n Each subset contains 3 bit fields for control of modulation type ASK or FSK RF PA block activation 3 blocks are available may be switched ON OFF individually RF PA output power Modulation type ASK or FSK is controlled by bit field ASKFSK1 2 0x05 6 5 of the SFR Transmitter Configuration Register 1 0x05 The modulation mode selection is done individually for each of the two transmission
109. trol 3 wire SPI Bus 21 SPI Pin Description 21 SPI XOR Checksum 23 Command Byte Structure 24 Transmit Command 22 9 56 pu rp rr E ERE 25 Timing Diagrams 42244330 pE dave Served aa kes oe meee 25 Data Encoder x32 ses bb dw ache Sone Rue dn Bike ohn ee 27 PRBS9 Generator Data Gcrambler 00a 28 SFRs related to Transmitter Configuration and Data Encoding 30 Crystal Oscillator and Clock Divider 31 The Bit Rate Generator 32 The Clock Output 33 SFRs related to Crystal Oscillator and Clock Divide 34 Sigma Delta fractional N PLL Block 34 Fractional Spurs d s eee pg re Xe oru un etai 35 Voltage Controlled Oscillator VCO 35 Loop Filter Bandwidth 36 PLL Dividers RF Carrier Frequency 37 SFRs related to Sigma Delta fractional N PLL Block 37 Data Sheet 4 V1 1 June 2012 Cinfineon pu 2 4 7 2 4 7 1 2 4 8 2 4 8 1 2 4 8 2 2 4 8 3 2 4 8 4 2 4 8 5 2 4 8 6 2 4 9 2 4 9 1 2 4 9 2 2 4 9 3 2 4 9 4 2 4 9 5 2 4 9 6 2 4 10 2 4 10 1 2 4 10 2 2 4 10 3 2 4 11 2 4 11 1 2 4 11 2 2 4 11 3 2 4 11 4 2 5 2 5 1 2 5 2 3 3 1 3 2 3 3 4 4 1 4 2 4 2 1 4 3 5 Data Shee
110. uto Calibration for Channel Hopping 0 enable VCO Auto Calibration 1 Skip VCO Auto Calibration for default frequency hops lt 1MHz GFBYP Gaussian filter bypass 0 GF enabled 1 GF bypassed GFDIV Gaussian filter clock divider value 11 bits bits lt 10 8 gt defines the sampling ratio of the Gaussian filter typically this value is set such that the GF divider is 16 x chiprate for ideal Gaussian filtering GFDIV 2x0sC__ chiprate x 16 Data Sheet 81 V 1 1 June 2012 Cinfineon TDA5150 TDA5150 Functional Description ADDR 0x1F ANTTDCC Antenna Tuning and Duty Cycle Configurations Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 reserved DCC DCCCONF DCCCONF TUNETOP TUNETOP TUNETOP TUNETOP DISABLE wi w 0 w 1 w 0 wl wl wl w 0 Bit 7 reserved Reserved set to 0 Bit 6 DCCDISABLE Duty cycle control disable Bit 5 4 DCCCONF Duty cycle control delay configuration bit 1 0 Bit3 0 TUNETOP Antenna tuning top PAOUT pin bit 3 0 DCCDISABLE Duty cycle control disable must be 0 for ISMB 0 0 enabled 1 disabled delay Ops DCCCONF Duty cycle control delay configuration ISMB 1 2 3 for ISMB 0 gt delay 0 ps 00 4396 01 39 10 3596 11 3196 69 35 33 207 104 346 173 484 242 ps 98 ps 164 ps 230 ps TUNETOP Antenna tuning top capacitor selection
111. vent sensed by the lock detector LD If the detection is disabled the error flags in Transmitter Status Register 0x01 still keep track of error status i e they are set if an error occurs but the RF Power Amplifier is not switched off by the error flag s set condition i e the RF PA continues to transmit despite error until the transmission is terminated as a normal error free one Refer to Transmitter Status Register 0x01 description and Fail Safe Flags explained in next Chapter 2 4 8 6 SFRs related to RF Power Amplifier and ASK Modulator Data Sheet 48 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 8 6 SFRs related to RF Power Amplifier and ASK Modulator ADDR 0x04 TXCFG0 Transmitter Configuration Register 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GO2STDBY reserved reserved FSOFF ISMB ISMB reserved reserved cw 0 w 0 wi w 0 wi w 1 w 1 w 0 Bit 4 FSOFF Fail Safe mechanism 0 enabled 1 turned off ADDR 0x05 TXCFG1 Transmitter Configuration Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GO2SLEEP ASKFSK2 ASKFSK1 ASKSLOPE INVERT ENCMODE ENCMODE ENCMODE cw 0 w 0 w 1 w 0 wi w 1 wi w 1 Bit 4 ASKSLOPE ASK sloping 0 disable 1 enable ADDR 0x19 SLOPEDIV ASK Sloping Clock Divider Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SLOPEDIV SLOPE
112. vidually for each register which should be written 2 by sending a Burst Write command which allows sequential programming of registers found at subsequent addresses Attention Writing to the address space beyond the valid SFR address range 0x04 0x27 is prohibited as it may lead to system malfunction Data Sheet 24 V 1 1 June 2012 Cinfineon uet TDA5150 Functional Description 2 4 3 4 Transmit Command The Transmit Command Byte is used for data transmission It precedes the datagram to be transmitted The Transmit Command Byte format is described in the following table C1 CO Transmit Command Configuration Bit Function Value description 1 1 A Data sync 0 off 1 on at the same time Bit C Encoding must be set also to 1 gt Int Encoding 1 1 B PA mode 0 PA off at the falling edge of EN synchronized with bit rate if bit A is high 1 SDIO DATA is latched at the falling edge of EN PA stays on TX data are kept constant After the time out of 65536 f which is 5 ms for a 13 MHz crystal PA and PLL are switched off 1 1 C Encoding 0 off 1 on selects SFR register for encoding Bit A must be also set to1 gt Data sync 1 1 D Pwr level 0 selects PowerLevel Modulation Setting1 ModSetting 1 selects Power Level Modulation Setting2 1 1 lt E F gt Frequency 0 00 frequency channel A selected selection 1 01 frequency channel B selected 2 10 frequency chann
113. x Ce ES UO EH Ter vLlvd olas Na T H ous de Gu ersch H F GZ Y dIH2OU2IH SES Zar Laan ier f gan Infineon Evaluation Board V2 schematics Figure 24 87 V 1 1 June 2012 Data Sheet Cinfineon Weer Applications The schematics of a more elaborate solution the TDA5150 Evaluation Board V2 is shown in Figure 24 The board can be steered by the System Interface Board TDA5150 SIB V1 2 just in the same way as the TDA5150 Evaluation Board V1 1 with the control signals and voltage supply lines applied over connector X8 or by an uW Link Motherboard which is a general propose interface device used in conjunction with Infineon Technologies AG products The control and supply lines are applied in this case over the connectors designated as SV1 and SV2 An on board serial EEPROM device IC2 is used for module recognition and parameter storage All of the control and supply lines are routed to X7 a 100mil pitch standard connector The user may dock on this connector for signal visualization bus traffic monitoring or for taking control of an external system built around a TDA5150 transmitter and using the uW Link Motherboard or TDA5150 SIB V1 2 interface the as a Host This is a really practical solution in early development state of customer projects as the hardware platform may be developed and

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