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S3FI1BG User`s Manual

1. 0 08MAX 80 TQFP 1212 14 00 0 20 0 45 0 75 0 07 gt 0 20 0 03 03 0 08MAX 4 0 05 0 15 4 gt 1 00 0 05 1 20 NOTE Dimensions in Millimeters Figure 22 1 80TQFP Package Dimension SAMSUNG ELECTRONICS 290 er S3Fl1BG_USER S MANUAL_REV1 00 22 MECHANICAL DATA SAMSUNG ELECTRONICS 291 er
2. Figure 18 9 COM SEG Signal in 1 4 Duty and 1 3 Bias Mode SAMSUNG ELECTRONICS 252 en S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 18 6 REGISTER DESCRIPTION SUMMARY Name Ada mw oeio NOTE These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 253 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER LCON 0xFE20 Name ek Rw Desn vw eee DUTY 0 1 2 duty 1 1 3 duty 2 1 4 duty Display Enable BISRURN 0 Disable 1 Enable LCNST 0xFE21 me Rw Contrast Level 0 1 16 step dimmest level CNST LEVEL Tren oseb 14 15 16 step 15 16 16 step brightest level ore s mw tocwwesembem Normal Diminish LCD dividing resistor 0 Normal 1 Diminish resistor enable mw w m mew LCKSEL 0xFE22 Mme s mw np __ FRAME Clock Select F Refer to FRAME FREQUENCY description SAMSUNG ELECTRONICS 254 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO GENERAL PURPOSE GPIO 19 1 OVERVIEW The S3FI1BG has 61 programmable I O ports I O port mode registers select either function s port or GPIO This section also describes how to change the functionality of multiplexed pins These pins can function at the system level as a GPIO si
3. 69 4 2 u uu 69 4 3 Operation M OoO 70 4 3 1 Reset Management Mea edd Rete red da DR e AREA ea da EAR Ya RUE 70 4 3 2 Glock Management uuu tee e i ecce et a ee eee 73 4 3 3 Power etie dicetis evade epa ai dea ga REPRE Rada du Yd 78 4 4 Register D esorptighu E 82 5 Interrupt Structur eee 90 DA 90 5 2 uu 90 5 3 interrupt Handling u uu a 93 5 4 Register 95 CODEC 99 6 1 99 6 2 100 6 2 1 Voice Encoding Compressing Sequence Using Power 100 62 2 File Format project ull 101 SAMSUNG ELECTRONICS qo 10 11 6 2 3 Decoding the compressed voice uu 104 6 2 4 Using Interrupt Servi
4. 1 8V Regulator EVE CLKCON Y Serial Flash Up to 1Gbit Figure 1 1 S3FI1BG Block Diagram SAMSUNG ELECTRONICS 16 er 1 INTRODUCTION 80D8 80D7 80D6 80D5 80D4 80D3 80D2 GP00 SEG12 180D14 GP53 SEG11 180D13 GP52 SEG10 180D12 GP51 SEG9 I80D11 GP50 SEG8 I80D10 GP47 SEG7 I80D9 GP46 SEG6 GP45 SEG5 GP44 SEG4 GP43 SEG3 GP42 SEG2 GP41 SEG1 GP40 SEGO GP67 COM3 I80D1 GP66 COM2 I80D0 GP65 COM1 IBORS 64 GP16 UTXD 911081 61935 1049 SrdS axan 91 4081 71935 049 9 2 21 4081 91535 8049 2 9d9 200 1A NQu08l 10 191938 7049 1 001 4 201 935 4049 09d4S 0q9 1W1 nO1Stuu A1nOLL dvOLL 8L93S 90d49 d5 Od L 1 61935 049 195 02935 8 9 Led9 SIN L OSINS L2D4S SSd9 0 d5 MOL ISOWS 22D4S 9Sd9 9 0 NSOS EZDAS ZSd9 bd O ENIW LNOOL dVOOL 01 2935 0 49 L 139 82935 14 9 OLdS ENIV 1nOc L dvOc L 1 929 5 2 49 M 10n 2293S Ld9 e8d9 SNIV ELNIA axun 8eeo3S r 49 1 62945 9 49 06935 9 49 9035 4749 SSAV 495 849 8SnSSA 1212 S3FI1BG TQFP 80 PV180UT SMISO GP85 SMOSI GP86 SCSN GP87 EINTS CLKOUT GP14 EINT6 BSCLK GP34 EI
5. 277 20 4 277 20 2 Features re dex ra tetas eret en CUR 278 ZEEecu p 278 20 4 Register ertt Deed Dre Doe v voa P 279 aN ugebsope 282 22 Mechanical Data u 290 SAMSUNG ELECTRONICS en 18 5 Operation arti deeded 243 Figure Number Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 4 10 Figure 4 11 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 6 1 Figure 6 2 Figure 6 3 Figure 6 4 Figure 6 5 Figure 7 1 Figure 7 2 Figure 7 3 Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 List of Figures Title Page Number Block Diagtatm a awa ineo 16 80TQFP Pin Assignmeht uuu u S ee 17 Memory Organization of the S3FI1BG 26 Code
6. 245 GPIO O Contiguration 257 GPIO 1 Config raltioh 257 GPIO 3 Contiguration 258 GPIO 4 258 GPIO 5 258 e dieser uri chau bapa 258 GPIO 7 Configuration E 259 GPIO 8 Configuration 1 2 ritiene inert perdete e d eiat ev ted d Prada Fai Rea d rd 259 Absolute Maximum Ratings aceites cere 282 DC Electrical 282 AC Electrical 285 Input Output 286 A D Converter Electrical 286 D A Converter Electrical 287 Internal Oscillator 288 SAMSUNG ELECTRONICS Table 21 8 Low Voltage Reset Electrical Characteristics Table 21 9 LCD Contrast Control
7. BMISO Command X Figure 7 2 Timing Diagram of read operation from external serial Flash SAMSUNG ELECTRONICS 121 er S3Fl1BG_USER S MANUAL_REV1 00 7 SERIAL FLASH CONTROLLER SFDMA Serial Flash Read DMA The SFCON supports a dedicated DMA to read data from external serial flash to XRAM This feature is absolutely useful to continuously read data up to 256 bytes during voice playback SFDMA can transfer data without CPU intervention from external serial flash to XRAM In this case SFDMA operation has no relation to sampling rate of voice playback The usage of BRDMA is as follows Set SFDMA_START_ADRL MI H TSIZE and X BASE BRDMA CTRL 0x3 While BRDMA CTRL amp 0x01 Trasfer to XRAM is done cup RISC cpu H Voice S W Delay Decoder Voice Data SP Data Delay by Internal B voice Data Read RAM B Data Read 1 Byte Figure7 3 Application of voice Playing SAMSUNG ELECTRONICS 122 en S3Fl1BG_USER S MANUAL_REV1 00 7 SERIAL FLASH CONTROLLER 7 5 REGISTER DESCRIPTION SUMMARY Name SFDMA RXBUF OxFF26 R SFDMA Rx Buffer SFDMA TSIZE OxFF27 SFDMA Transfer Size SFDMA X BASE L OxFF28 SFDMA Target XRAM Base Address Low SFDMA X BASE H OxFF29 SFDMA Target XRAM Base Address High SFCTRL2 OxFF2A SF Control register 2 NOTE These registers have to be accessed using MOVX ins
8. SAMSUNG ELECTRONICS 244 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER LCD VOLTAGE DRIVING METHOD Voltage Generator or based on positive supply voltage applied V it generates the voltage levels for the timing and control logic to produce the COM and SEG waveforms The LCD display is turned on only when the voltage difference between the common and segment signals is greater than Vi cp The LCD display is turned off when the difference between the common and segment signal voltage is less than V cp The turn on voltage Vi cp or cp is generated only when both signals are the selected signals of the bias Table 18 4 shows LCD drive voltages for static mode 1 2 bias and 1 3 bias Table 18 4 LCD Drive voltage Values wo woe VLCD3 _____ 1 2 VLCD 1 3 VLCD NOTE The LCD panel display may deteriorate if a DC voltage is applied that lies between the common and segment signal voltage Therefore always drive the LCD panel with AC voltage SAMSUNG ELECTRONICS 245 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER VDD LCON O Contrast Controller LCNST 3 lt 1 3 BIAS VDD LCON 0 LCON 0 Contrast Controller Controller LCNST 3 o LCNST 3 1 2BIAS
9. ADDR_H BRDMA Start Address SFDMA RXBUF 0xFF26 This is used for CPU mode ew ew SFDMA TSIZE 27 RW TSIZE 7 0 TSIZE 1 bytes are transferred to XRAM from Serial Flash SFDMA_XBASE_L 0xFF28 SEDMA_XBASE_H 0xFF29 XRAM base lower address Undef XRAM base higher address Undef B 2 BASE_H B SFCTRL2 2 a into ASW _ SF 4BYTE_ADDR When this bit is set to 1 serial flash address is 4 bytes Bank address for 128Mbits 16Mbytes blocks SF BANK ADDR 34 RW This bits are used when the serial flash greater than 128Mbits is needed These bits are valid only when SF 4BYTE ADDR bit is set This bit selects the speed of SPI clock SF FAST MODE RW 1 SF clock Fsys 0 SF clock Fsyg 2 SAMSUNG ELECTRONICS 125 S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER BRJPEG DECODER 8 1 OVERVIEW The S3FI1BG has a BRJPEG decoder to decode graphic image bit streams which are encoded by own PC based software encoder 8 2 FEATURES e Embedded own DCT based image decoder 128x128 10 frame decoding 12MHz 192x192 10 frame decoding 24MHz e Built in processing engines for image decoding Variable length decoding VLD engine Inverse discrete cosine transform IDCT engine e Variable length decoding VLD engine Bit processing Huffman decod
10. Int TnCAP I I I Capture trigger Capture trigger Capture trigger Capture trigger Figure 11 4 Example of Timer Operation in Capture Mode SAMSUNG ELECTRONICS 168 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS 11 6 REGISTER DESCRIPTION SUMMARY me Aa Rw Deep NOTE These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 169 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS TnCON OxFE00 8 T2CON OxFE10 Name s mw Deep Timer n counting clock select TnCLK SEL 74 RA TnCLK 2072 n 0 10 When 11 TnCLK External Timer clock lt Fsys 2 TnMOD_SEL 3 2 R W 00 Interval Mode 01 Toggle Mode 10 PWM Mode 11 Capture Rising Mode Timer n Interrupt Pending If the IETn in the IEO and IE1 register is enabled and GIE is enabled an TnINTPEND 1 RW a A i interrupt is requested when this bit is set to 1 User can clear this bit by writing 1 to this bit 0 RW 0 DisableTimern 1 Enable Timern TnRUN TnDATAO TODATAO 1 T1DATAO 0 09 T2DATAO OxFE11 0 Disable Timer n 1 Enable Timer n Timer 0 1 2 reference data value TnDATA1 7 0 THDATAO 7 0 Description TnDATAO 7 W Timer 0 1 2 reference data register 0 OxFF z TnDATA1 TODATA1 0xFE02 TIDATA1 0xFE0A T2DATA1 0xFE12
11. VDMA DST ADDR H Bits 11 8 of the destination area starting address SAMSUNG ELECTRONICS 222 er S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA VDMA BG WIDTH 8 VDMA BG WIDTH 9 VDMA BG WIDTH 8 0 register keeps the horizontal image frame width of the background source ee VDMA BG H WIDTH L 0 of the horizontal width of the background source RVO VDMA BG H WIDTH RA Bitf8 of the horizontal width of the background source frame VDMA BG ADDR 0xFFEA VDMA_BG_ADDR_M 0xFFEB VDMA_BG_ADDR_H 0xFFEC VDMA BG ADDR 23 0 register is the background source image address Name BG Bits 7 0 of the background source area starting address Name Bt RW Pespion VDMA BG ADDR M Bits 15 8 of the background source area starting address Name Bespio VDMA BG ADDR H Bits 23 16 of the background source area starting address VDMA FG H OFFSET Nme RW VDMA FG H OFFSET Horizontal offset of the foreground area VDMA FG V OFFSET 0xFFF1 Name ___ VDMA FG V OFFSET Vertical offset of the foreground area VDMA FG H LEN 0xFFF2 ek mw VDMA FG H LEN Horizontal length 1 for foregr
12. 4 mw 0 Disable UART RX Erorintrupt 1 Enable UART RXEmormemu 0 3 o Disable UART Receive interrupt 1 Enable UART Receive merus 0 mw o Disable UART Transmtinterupt 1 Enable UART Transmit inerupt 0 71 RW JPEG _____ rable JPEGintorupt Jo o Rw o Disabe Ter 2 nterupt 1 Enable Timer 2interupt o IP1 0x95 Name IPEXT2 3 0 Lower priority level 1 Higher priority level IPI80LCD 6 RW 0 Lower priority level 1 Higher priority level IPVDMA 0 Lower priority level 1 Higher priority level IPURXERR 0 Lower priority level 1 Higher priority level IPURX 0 Lower priority level 1 Higher priority level IPUTX 0 Lower priority level 1 Higher priority level IPBRJPEG 0 Lower priority level 1 Higher priority level IPT2 RW 0 Lower priority level 1 Higher priority level 4 IE2 0x96 Name Sr Rw 0 Disable USB reset suspend resume interrupt IEUSBRST 7 R amp usemsr 7 1 Enable USB reset suspend resume interrupt IERTCALM 6 RW 0 Disable RTC ALARM interrupt 1 Enable RTC ALARM interrupt IERTCPRI 0 Disable RTC Periodic interrupt 1 Enable RTC Periodic interrupt o exe a Aw Disable Exemalinterupt9 1 Enable Extemainterupt9 Aw 0 Disabie Exermali
13. omo 7 s aro Jj omes e om oseiro ems aPosisecraicapmiour Gros Paor aporisecroracaprraour 3 oma crwsecmsuk arse J e roms eesegmwso ams 3 sesseemswos SAMSUNG ELECTRONICS 19 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION i ums gsm RESET RESET e aw Pop osoen amo en Fem crase m en res ems m ems Gee pun m e Pu Gm Geasuk Pulp 1 SAMSUNG ELECTRONICS 20 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION Misellaneous Clock Input Output Max 12 2 Connect these oscillation pins to crystal oscillators m 32 768 KHz clock Input Output Chip Reset Signal active Low This PnRESET pin contains an internal pull up resistor 250k Setting this to low
14. GP50 GP50 Input GP50 Output SEG8 180010 Table 19 6 GPIO 6 Configuration SAMSUNG ELECTRONICS 258 S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO PORT 6 Selectable Functions Shared Function o 0 GP67 I80D1 B GP66 I80DO B GP65 8085 O GP64 I80CSN O GP63 I80WRN O GP62 I80RDN O GP61 GP60 Table 19 7 GPIO 7 Configuration PORT 7 Selectable Functions Shared Function UE Table 19 8 GPIO 8 Configuration PORT 8 Selectable Functions Shared Function em GeEma GPOwu Gr _ _ som ENTA SAMSUNG ELECTRONICS 259 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 19 5 REGISTER DESCRIPTION SUMMARY Aad Rw ow _________________ 000 P o 6 m Rw General 06 External Interrupt Control Register 3 for 8 9 SAMSUNG ELECTRONICS 260 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO P5MOD1 OxFE58 GP54 GP57 Mode Control Register 1 P5PUR PORT 5 Pull Up Control Register 0 P6MODO GP60 GP63 Mode Control Register 0 P6MOD1 GP64 GP67 Mode Control Register 1 P6PUR PORT 6 Pull Up Control Register
15. USB Enable Register 0x00 USBCONF oxDF USB Configuration Register 0x00 Unde Undef oc 0848 USBNAKCONI oxDC USB Control oo 0x00 0800 0x00 Read W Write S SET Clear SAMSUNG ELECTRONICS 194 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER USBFA 0xB1 ei GPU USE Deep USB Address Update The CPU sets this bit whenever it updates the USB Function Address USBAUP 7 5 R C Field in this register The USBFAF is used after the Status phase of Control transfer which is signaled by the clearing of the DEND bit in the Endpoint 0 CSR USB Function Address Field Peer The CPU writes the address to these bits USBPM 0xB2 Name si ceu uss ISO Update Used for ISO mode only set USB waits for SOF token from the USBISOU 7 RW time USBINRDY was set to send the packet If an IN token is received before a SOF token then a zero length data packet will be sent s ne 7171 ReSeT The USB set this bit if reset signaling is received from the host This USBRST 3 5 bit remains set as long as reset signaling persists on the bus 0 Normal operation 1 Reset received state SUSpend Mode This bit is set by the USB when it enters suspend mode It is cleared under the following conditions The CPU clears the USB RESUM bit bit2 of this reg
16. 145 4 Wire SPI Slave Timing SCKPHA 1 n asas 146 UART Block tatit tator endet teh eret 152 UART Interrupt Timing Diagram u uuu aaa enne nnne nnn nnne nnne 154 Baud Rate Generator 155 IrDA Function Block Diagram 156 SAMSUNG ELECTRONICS qo Figure 10 5 Figure 10 6 Figure 10 7 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 13 1 Figure 13 2 Figure 14 1 Figure 14 2 Figure 15 1 Figure 15 2 Figure 16 1 Figure 16 2 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 Figure 17 6 Figure 17 7 Figure 17 8 Figure 18 1 Figure 18 2 Figure 18 3 Figure 18 4 Figure 18 5 Figure 18 6 Figure 18 7 Figure 18 8 Figure 18 9 Figure 19 1 Figure 20 1 Figure 21 1 Figure 21 2 Figure 21 3 Figure 22 1 UART Frame Struclure 156 Infrared Tx Timing u u u u tte ette 157 Infrared Rx Timing Diagram cies tke 157 Timers EET 165 Example of Timer Operation in PWM 166 Example of Timer Operation in Interval and Toggle 167 Example of Timer Operation in Capture Mode sse 168
17. Disable txemarnemupr4 Enabe fieusesor o Rw 0 Disable Extemalinterupts Enabe IP3 Ox9A aw rs Reed SCS i s Ra 0 Lower evel 4 0 Lower priory teve 1 Higher priory ev IPUSBEP2 s Raw O Lower priory tevel 1 Higher pronty 2 raw O Lower priory tevel 1 Higher Raw O Lower priory tevel 1 Higher o Raw Lower priory vel Jo SAMSUNG ELECTRONICS 98 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC CODEC S3FI1BG has Audio decoder encoder Embedded hardwired ADPCM based Voice Codec 6 1 FEATURES e 3 4 bit decoder e 3 4 bit encoder e 3 up interpolation filter e DMA for internal e FLASH and external serial FLASH e Sampling Frequency Generation by DCO Digital Controller Oscillator SAMSUNG ELECTRONICS 99 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 OPERATION 6 2 1 VOICE ENCODING COMPRESSING SEQUENCE USING POWER STUDIO All the voice data to be played should be stored in flash memory The voice data can be stored into internal flash memory e FLASH or external serial flash memory Each of flash memory can be distinguished by the value of DATA_SRC in BRAC_CTRL2 register Before playing the voice data in the
18. n 5 4 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection External interrupt request input for GP34 2 0 filtering off 1 filtering on R 5 50 1 0 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection EINTMOD3 0xFE44 en Deep ese vw 7 aw peed SSC External interrupt request input for GP37 6 0 filtering off 1 filtering on R 84 5 4 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection External interrupt request input for GP36 2 0 filtering off 1 filtering on R T iii 1 0 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection SAMSUNG ELECTRONICS 264 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO EINTENO OxFE45 Name RW Description Reset pred mw Sincere Ps mc E aee a Enable external Interrupt 3 0 Disable 1 Enable Enable external Interrupt 2 EIN TSEN 0 Disable 1 Enable Enable external Interrupt 1 0 Disable 1 Enable RW Enable external Interrupt 0 0 Disable 1 Enable NOTE Must clear each pending bit before setting this register EINTEN1 0xFE46 Enable external Interrupt 9 ESSE 0 Disable 1 Enable EINTOE
19. 12 1 Bleck Diagrql uuu 16 1 3 PIMSASSIQMIMONM LT 17 1 4 Pin ER 18 2 Memory Organization SR S u 25 2 1 CODE MEMO paasaalaaau 27 2 2 DATA MEMO MEE 29 30 2 4 SFR Special Function Register 31 3 Instruction Sel UI tess eee em 49 3 1 Register Description For L en eA ee et 50 3 2 E seek gent leaden eee shade 52 Bo ELE 53 3 31 Data Transfer Instructions t ite eni e seats Y Ren 54 2 1 6 e 56 3 3 3 Unconditional Branch 7 58 3 3 4 Boolean Instructions 59 3 3 5 Subroutine Call 60 3 3 6 Conditional Branch Instructions 61 3 3 7 Logical qa 63 3 4 Instruction Set Summary sess essere ense 65 4 System GCORIFOIlGF cete ux ERE Ka EN UMEN EK EA EMEN EE 69 dl pe
20. aqa qaqa 127 8 4 Register EE 132 SP e 140 E 140 SENIUM 140 pod agree 140 4 Block DIagram uuu E eim i 141 Operall l es 142 s OPegstaerDesqiiplien u u uuu uuu uuu u uy u 147 SS E S A sa sassa 151 1 Em 151 10 AIuee 151 JO Pim u EE 151 10 4 Block a u 152 10 5 u uD E kas 153 10 6 Register 158 jj 164 11 1 164 11 2 FEIOS 2 2 neste 164 11 3 Pin DOSCrIPTHON s 164 114 Block Diagrama u io lee 165 11 5 ss ch seb vende 166 11 6 Register Description eee ae eee em 169 SAMSUNG ELECTRONICS qo 12 13 14 15 16 17 18
21. sg L Hos cup SAMSUNG ELECTRONICS 146 S3Fl1BG_USER S MANUAL_REV1 00 9 SPI 9 6 REGISTER DESCRIPTION SUMMARY Name a w Den SPICK SPI Baud Rate counter clock select Register SPIDATAO SPI Transmit and Receive Data SPIDATA1 SPI Transmit and Receive Data SAMSUNG ELECTRONICS 147 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI SPIMOD Name SPI Interrupt Pending If the IESPI in the IEO register is enabled and GIE is enabled an interrupt is requested when this bit is set to 1 User can clear this bit by writing 1 to this bit SPI Slave Select Enable 0 SCSN signal is not routed to a port pin 1 SCSN signal is mapped as an output input SPI Clock Phase 0 Data centered on first edge of SCK period 1 Data centered on second edge of SCK period SPI_INTPEND SPI_SSMD SPI Clock 0 SCK line low in idle state 1 SCK line high in idle state SPI Master Slave Mode 0 Master Mode 1 Slave Mode SPI Data Direction 0 MSB first 1 LSB first SPI Operation Mode PI MODE gt 0 Receive only mode 1 Receive Transmit mode SPI 0 Disable SPI operation 1 Enable SPI operation 000 SPICK SPI SCKPOL SPI SLVEN SPI DIR SPI Baud rate counter clock select register BaudRate Fsys CntValue This bit is set to logic
22. v Tranmit Shifter Transmit Holding Register Control Baud rate Unit Generator Receiver Clock Source Fsys EXTUCLK 2 Fsys 4 Fsys 8 16 v Receive Shifter Receive Buffer Register URXBUF k Receive Holding Register Figure 10 1 UART Block Diagram SAMSUNG ELECTRONICS 152 S3Fl1BG_USER S MANUAL_REV1 00 10 UART 10 5 OPERATION The following sections describe the UART operations that include data transmission data reception interrupt generation baud rate generation Loopback mode and infrared mode Transmission The data frame for transmission is programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits which can be specified by the control register UCON The transmitter can also produce the break condition which forces the serial output to logic 0 for one frame transmission time This block transmits break signals after the present transmission word is transmitted completely After transmission of the break signal it continuously transmits data into the UTXBUF Tx holding register Reception Like the transmission the data frame for reception is also programmable It consists of a start bit 5 to 8 data bits an optional parity bit and 1 to 2 stop bits in the control register UCON The receiver can detect overrun erro
23. AN AN Description E B TnDATA1 7 Timer 0 1 2 reference data register 1 OxFF TnCNTO TOCNTO T1CNTO OxFEOB T2CNTO OxFE13 Timer 0 1 2 counter TnCNT1 7 0 TRCNTO 7 0 m Timer 0 1 2 Count register 0 OxFF TnCNT1 TOCNT1 OxFE04 T1CNT1 OxFEOC T2CNT1 OxFE14 TnCNT1 Timer 0 1 2 Count register 1 OxFF gt SAMSUNG ELECTRONICS 170 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS TnPDRO TOPDRO 5 T1PDRO OxFEOD T2PDRO OxFE15 Timer 0 1 2 PWM value TnPDR1 7 0 TnPDRO 7 0 Br Timer 0 1 2 PWM Data register 0 TnPDRO 70 RW This register must not have zero value and will be written any value in PWM mode TnPDR1 TOPDR1 0xFE06 T1PDR1 T2PDR1 OxFE16 mw Timer 0 1 2 PWM Data register 1 0 00 This register will written value PWM mode Programming TIP An example setup procedure with a description of each step is shown below Setup Procedure Description void TIMERO setup rCLK ENO 0x10 1 Enable TIMER 0 operation clock rP1MODO 0x30 2 Set P1MODO register for TIMER 0 operation Using rPOMOD1 rlEO 0x40 3 Enable TIMER 0 interrupt rGIE 0x80 4 Enable Global interrupt rTODATAO 0x03 rTODATA1 OxE8 rTOCON 0x90 5 7 4 select counting clock source
24. esses 59 Mnemonic and Operand of Instructions related to the Subroutine Call 60 Mnemonic and Operand of Conditional Branch Instructions 61 Mnemonic and Operand of Logical Instructions U eee 64 IP status on Normal and STOP 80 PLL value 89 Interrupt Default 92 Serial Flash Interface PIN 120 SPI PIN isana 140 UART PIN RI Te gero m 151 Baud Rate Example ot UAR T 155 Timers gregi 164 ADG PIN ERE 179 Summary of EndpoiBnt erat awak aaa alo e Mesa Lor 189 USB PIN Description E 190 180 LCD Interface PIN 226 LCD PIN Desoripti6em 241 4COM x 32SEG Display Memory 243 Frame EE 244 LCD Drive voltage
25. 0 disable prediction 1 enable DC prediction AN Block size for VLD IQ IDCT BLOCK TYPE R W 0 4x4 1 8x8 BRJPEG_BUFSEL 0xFF57 BRJPEG_BUFSEL defines which buffers are used by VLD or IDCT IDCT_OUT 3 2 IDCT output buffer selection for 3x64x1bytes 00 BUFO 01 BUF2 02 BUF4 03 BUF5 R W IDCT input buffer selection for 3x64x2bytes VLD output buffer or IQ input output buffer selection for 3x64x2 bytes VEBEDUT 0 BUFO1 1 BUF23 BRJPEG CMD 0xFF58 mem IDCT enable command When set it is not cleared until the IDCT IDCT EN 1 RW operation is done IDCT operation is defined by BRJPEG_IDCT_MODE register 0 idle 1 enable W busy R VLD enable command When set it is not cleared until the VLD VLD_EN RAN operation is done VLD operation is defined by BRJPEG VLD MODE register SAMSUNG ELECTRONICS 137 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER idle 1 enable W busy R BRJPEG_IE 0 59 Name ee RW ___ eee DONE IE 1 RW per done interrupt enable 0 disable 1 enable VLD done interrupt enable Sa 0 disable 1 enable n BRJPEG 5 s mw mw fef ea w done nteruptcearbywitnat o vio pone eir o w vi cone ierruprctear by wiin Jo
26. SAMSUNG ELECTRONICS 60 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 6 CONDITIONAL BRANCH INSTRUCTIONS All of these Jumps specify the destination address by the relative offset method and so are limited to a jump distance of 128 to 127 bytes from the following the conditional jump instruction Since no ZERO bit is in the PSW the JZ and JNZ instructions test the Accumulator data instead of PSW The DJNZ Decrement and Jump If Not Zero instruction is for loop control To execute a loop N times load a counter byte with N and terminate the loop with a DJNZ to the beginning of the loop The CJNE Compare and Jump if Not Equal instruction can also be used for loop control Two bytes are specified in the operand field of the instruction The jump is executed only if the two bytes are not equal Another application of this instruction is in greater than less than comparisons The two bytes in the operand field are taken as unsigned integers If the first is less than the second then the CY is set If the first is greater than the second the CY is cleared Table 3 7 is Mnemonic and operand description of each conditional branch instruction Each function and effects PSW are also described The symbol means no effect to PSW the symbol gt means can effect to PSW Table 3 7 Mnemonic and Operand of Conditional Branch Instructions Opcode PSW Mnemonic amp Operand
27. 32 Kbytes Embedded Flash Memory BANK 11 2 MEMORY ORGANIZATION 4 Kbytes On Chip XRAM 32 Kbytes Embedded Flash Memory BANK 0 32 Kbytes Embedded Flash Memory BANK 0 Figure 2 2 28 Code Space Memory Structure S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION 2 2 DATA MEMORY Table 2 2 Data Memory Logical Address XROMB Description Range Value BANKO 11 0x0000 7 0 11 FLASH 32KB Depending on the XRAMB any of e FLASH can accessed through this area Default XRAMB is zero X RAM osoo OxBFEF X BAM 4KB X RAM is always assigned to this area regardless of XRAMB Even when the value of ROMB is 31 this X RAM can be accessed through this address range 4 Kbytes On Chip XRAM Access through 0x8000 4 Kbytes On Chip XRAM Access through MOVX 4 Kbytes On Chip XRAM Access through Ox8FFF 4 Kbytes On Chip XRAM Access through 0x7FFF 0x0000 32 Kbytes Embedded Flash Memory BANK 0 Access through 32 Kbytes Embedded Flash Memory BANK 1 Access through MOVX 32 Kbytes Embedded Flash Memory BANK 2 Access through Setup example void DATA setup rXRAMB 2 A 32 Kbytes Embedded Flash Memory BANK 11 Access through MOVX Figure 2 3 Data Space Memory Structure Accesses to da
28. SAMSUNG ELECTRONICS 186 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER ADREFCMP 0xE6 Normal Mode me Den ADREFCMP This register is used to compare to certain conversion bit ADREFCMP 0xE6 Recording Mode ee Desn Doro ___ n pe BUSY 4 R 0 Encoding is done 1 Under BRAC Encoding ENC_RESULT 306 R Encoding Result SAMSUNG ELECTRONICS 187 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER USB CONTROLLER 14 1 OVERVIEW USB products are easy to use for end users Electrical details such as bus termination are isolated from end users and plug and play is supported There are other merits for users Self identifying peripherals automatic mapping function to driver auto configuration dynamically attach and detach and reconfiguration and so on SAMSUNG ELECTRONICS 188 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER 14 2 FEATURES e Fully Compliant to USB 2 0 full speed specification maximum 12Mbps e Complete Device Configuration e Compatible with both OpenHCl and Intel UHCI Standards e Support 5 Endpoints 1 Control Endpoint 4 Data Endpoints with logical endpoint numbering e 16 Bytes Control Status Endpoint e 1 2 64 Bytes Data Endpoint IN OUT supporting automatic double buffering e EP3 4 16 Bytes Data Endpoint IN OUT supporting automatic double buffering Supports Bulk D
29. Block Diagram ener tenent ne E idee e ets 173 Timing Diagram with 174 WDT Timing Diagram with interrupt and unane 174 WDT Timing diagram with WAKEEN on STOP mode a 175 ADG Block 1 mm 180 Operation of A D aaa enne entente sintesi tete entes 181 USB Device Block Diagram sssssssesessseeese esee nnne nitent enne sn nnns snnt enne 190 USB Transceiver Block Diagram U U entere nnns nnne neni 191 RTC SIBI rant MEE 208 Basic operation c 210 VDMA Block tans 217 VDMA 2 Frame EU 218 I80LCD single write timing 227 I80LCD single read timing parameters asa 228 I80LCD 8 bit interface for Index Command transfer a 229 I80LCD 8 bit interface for Parameter transfer a 230 I80LCD 8 bit interface for RGB332 transfer aaa 231 I80LCD 8 bit interface for RGB565 transfer 232 I80LCD 8 bit interface for RGB666 transfer 233 I80LCD 8 bit inte
30. Figure 10 5 UART Frame Structure SAMSUNG ELECTRONICS 156 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART lt IR Transmit Frame Start Bit Data Bit gt Stop Bit Bit time 3 16 T Figure 10 6 Infrared Tx Timing Diagram IR Receive Frame Start Bit Data Bit 3 16T gt Stop Bit Figure 10 7 Infrared Rx Timing Diagram SAMSUNG ELECTRONICS 157 S3Fl1BG_USER S MANUAL_REV1 00 10 UART 10 6 REGISTER DESCRIPTION SUMMARY me Add RW R R W User can t access these registers if access it might cause unexpected operation SAMSUNG ELECTRONICS 158 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART UCONO 0xF1 row essen 7 5 100 ODD parity 101 EVEN parity 110 Parity is forced checked as a 1 111 Parity is forced checked as a 0 Setting this bit to 1 causes the UART to enter Loop back mode In this mode the transmit data output UTXD keeps 1 and UTXBUF is LOOPB 4 internally connected to the receive data register URXBUF This mode is provided for test purposes only For normal operation this bit should always be 0 Echo mode enable ECHO 3 0 Disable echo test 1 Enable test R
31. PGP1 PGP3 PGPe 3 0 PGP8 Input high ViN Vpp leakage current All input pins except PTEST jy Vin Vpp PXI PXTI Input low Vin leakage current All input pins except PnRESET 2 Vin OV PXI PXTI Output high leakage current Vout All output pins lo Vour OV All output pins LCD voltage Ta 25 LCNST 2 0 dividing resistor Riess LCNST2 Oscillator Rosci Vpp 3 3V Ta 25 1700 a PXO 0 V resistor Rosc2 Vpp TA 25 2200 4500 9000 PXTI 0 V Vin 3 3 TA 25 PnRESET 8 3 25 ME Output low leakage current PGPO PGP1 PGP3 PGP8 Pull down resistor Pull up resistor OV 25 PGP1 PGP3 PGP8 Vpp 2 4V 10 3 3V 1 3 Bias 0 67Vpp LCD clock 2 0 2 0 2 0 2 0 2 Middle output voltage Vicpo COMi Voltage drop i 0 3 Voltage drop i 0 31 Supply current 1 15 per common pin Normal Operating mode Vpp 3 3V EMCLK 12MHz ESCLK 32 768KHz IMCLK 16MHz ISCLK 32 768KHz 15 per segment pin Bl SAMSUNG ELECTRONICS 283 S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA Crystal oscillator C1 C2 22pF IDLE mode 3 3V EMCLK 12MHz ESCLK 32 768KHz
32. 2005 conversion time 50K SPS 3MHz ADC conversion clock Programmable input clock frequency e 1channel 10 bit D A Converter Serial Flash Controller Master only interface with dual DMA functions BSPI clock is divided by 2 from Fsys system clock BSPlis mainly used for external serial flash BSPlon the fly function by a dedicated DMA high speed data read even during voice Playback UART Supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive TX RX Supports external clocks for the UART operation Programmable baud rate Supports IrDA 1 0 Loopback mode for testing Insertion of one or two Stop bits per frame Parity checking LSB first RTC Time information seconds minutes hours directly in BCD code Calendar information date month year day of the week directly in BCD code up to year 9999 Leap year generator Wake up signal generation support on the STOP mode Alarm interrupt Cyclic interrupt the interrupt cycle may be 1 512 1 256 1 64 1 16 1 4 1 2 and 1 second SAMSUNG ELECTRONICS 13 en S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION e USB Device Fully Compliant to USB 2 0 full speed specification maximum 12Mbps Complete Device Configuration Compatible with both and Intel UHCI Standards Support 5 Endpoints 1 Control Endpoint 4 Data Endpoints with logical endpoint numbering 1
33. 32 Kbytes 128 Bytes BANK 2 0x1_0000 Lower 0x0_FFFF 128 Bytes 32 Kbytes BANK 1 0x0_8000 0x0_7FFF 32 Kbytes BANK 0 0x0_0000 384 Kbytes eFLASH Figure 2 1 Memory Organization of the S3FI1BG SAMSUNG ELECTRONICS 26 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION 2 1 CODE MEMORY After reset CPU begins execution from location 0 0000 CPU can access using MOVC instruction in code memory Table 2 1 Code Memory Logical Address ROMB Description Range Value Bank 0 82 KB 0x00000 0x07FFF This range includes the default boot code area in e FLASH memory and all the contents are downloaded and burned normally by JTAG ICE 0 08000 OxOFFFF Bank 32 KB 0x08000 Bank 2 32 KB 0x08000 Bank 3 Bank 11 32 KB each per Bank X RAM 4 KB This area is mapped to 4 KB X RAM and program can be copied to this 0x8000 Ox8FFF i area to be executed For example the e FLASH burning program executed in this area X means don t care SAMSUNG ELECTRONICS 27 er S3Fl1BG_USER S MANUAL_REV1 00 ROMB VALUE OxFFFF 0x8000 Ox7FFF 0x0000 32 Kbytes Embedded Flash Memory BANK 1 32 Kbytes Embedded Flash Memory BANK 2 32 Kbytes Embedded Flash Memory BANK 0 32 Kbytes Embedded Flash Memory BANK 0 Setup example void CODE_setup rROMB 10 SAMSUNG ELECTRONICS
34. B5 Registers 1 1 RGB565 read in 8 bit interface max 2 pixels min 1pixel Figure 17 6 I80LCD 8 bit interface for RGB565 transfer SAMSUNG ELECTRONICS 232 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE LCD_RS LCD_CSN LCD_WRN Internal_ LCD_DO 7 0 LCD D 7 0 R6X2 G6X2 B6X2 R6X2 G6X2 B6X2 I I I I I I RGB666 write in 8 bit interface max 2 pixels min 1 pixel LCD_RS LCD_CSN LCD_RDN LCD D 7 0 Internal __ Data Capture Registers Figure 17 7 80LCD 8 bit interface for RGB666 transfer SAMSUNG ELECTRONICS 233 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE LCD_RS LCD_CSN LCD_WRN Internal_ LCD_DO 7 0 LCD 07 01 LCD RS LCD CSN LCD RDN LCD D 7 0 Internal __ Data Capture Registers Figure 17 8 I80LCD 8 bit interface for RGB8868 transfer SAMSUNG ELECTRONICS 234 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE 17 4 REGISTER DESCRIPTION SUMMARY au I80LCD_TP_W4 OxFFC4 I80LCD_TP_W5 i i Number of HCLK cycles from LCD_RS LCD_D high Undef impedance in LCD write operation becomes I80LCD_TP_W4 1 i Number of HCLK cycles from LCD_RS to LCD_RDN high in Undef EOL RLF ss LCD read operation becomes I80LCD_TP_R2 1 Number of HCLK cycles from LCD_RS to LCD_CSN high Undef LCD write operation becomes I80LCD_TP_
35. Besrpim ACC 0 Bits 7 0 of the accumulator in IDCT engine et aw espn ACC 1 Bits 15 8 of the accumulator in IDCT engine enj RW Description IDCT_ACC_2 Bits 23 16 of the accumulator in IDCT engine Name __ BDesrpim fa IDCT_ACC 3 Bits 31 24 of the accumulator in IDCT engine SAMSUNG ELECTRONICS 139 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI SPI 9 1 OVERVIEW Serial Peripheral Interface SPI of the S3FI1BG can interface the serial data transfer During SPI transfer data is simultaneously transmitted shifted out serially and received shifted in serially It can operate as master or slave device in 3 wire or 4 wire modes All SPI input output pins are multiplexed with GPIOs 9 2 FEATURES e Full duplex 3 wire or 4 wire Synchronous Data Transfer e Support Master and Slave operation e Serial clock with programmable polarity and phase e Baud rate clock selectable in Master mode e MSB First or LSB First Data Transfer e Support 1 Byte 2 Byte operation 9 3 PIN DESCRIPTION Table 9 1 SPI PIN Description GP84 GP54 SCLK SPI Clock When configured as master this pin is an output When configured as slave this pin is an input GP85 GP55 SMISO SPI master in slave out When configured as master this pin is an input When configured as slave this pin is an output GP86 GP56 SMOSI SPI master out slave in When configured as ma
36. Destination Frame VDMA FG H WIDTH Background Frame VDMA_DST_H_WIDTH VDMA BG H WIDTH Figure 16 2 VDMA 2 D Frame Structure SAMSUNG ELECTRONICS 218 er S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA 16 4 REGISTER DESCRIPTION SUMMARY Name Ae ww ree VDMA 0 OxFFEO Configuration byte 0 VDMA CFG 1 OxFFE1 Configuration byte 1 VDMA H LEN OxFFE2 Horizontal length 1 for the background and destination moving area VDMA V LEN OxFFE3 Vertical length 1 for the background and destination moving area VDMA BG H WIDTH L OxFFE8 Low byte of the horizontal width of the background source frame VDMA BG H WIDTH H OxFFE9 High byte of the horizontal width of the background source frame VDMA BG ADDR L OxFFEA R W Low byte of the background source area starting Undef address VDMA BG ADDR M OxFFEB R W Middle byte of the background source area starting Undef address VDMA BG ADDR OxFFEC of the background source area starting RESERVED aseve To Reserveo oerer aseve Jo VDMA FG H WIDTH L OxFFF4 of the horizontal width of the foreground source VDMA FG H WIDTH H OxFFF5 High byte of the horizontal width of the foreground source frame VDMA_FG_ADDR_L OxFFF6 Low byte of the foreground source area starting address VDMA FG ADDR M OxFFF7 4 7 of the foreground source area starting VDMA_FG_ADDR_H OxFFF8 High byte of the foreground source area starting add
37. Immediately after the changing of ROMB the fetch of next instruction loads ROMB 4 0 R W code from the new BANKn selected by ROMB 0x0000 0x07FFF 32KB Bank this value 1 0x08000 0x0FFFF 32KB per Bank 0xA2 et aw 75 n 2 e FLASH 32KBytes Bank Selector If this value 0 Select Bank 0 0 0000 Ox7FFF e FLASH area 0 8000 0x8FFF area CLKCON 0xA3 This register will be only reset by or LVDRST This register configures the source clock and the division ratio of clock The operation speed of clock can be slower to reduce the overall power consumption if application does not require full performance Name ew Bewnpim Select source clock with CLKOUT pad GP14 111 CLK12M PLL from USB 110 CLK12M SIE from USB 101 ESCLK CLKO 7 5 R W 100 EMCLK 011 RTC output clock 010 ISCLK 001 IMCLK 000 System source Fsgyrce_ clock select CLKSRC 2 0 R W 000 IMCLK Internal Main Clock Typ 16MHz 001 EMCLK External Main Clock 4 12MHz Using PXI and PXO SAMSUNG ELECTRONICS 83 System clock divisor select 00 Fsys 8 CLKDIV 4 3 01 Fsys Fsouncz 4 10 10 Fsys Fgource 2 11 Fsys Fgource 1 S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER 010 ISCLK Internal Sub Clock Typ 32 768KHz
38. Pu stase 7 R ofuweme Pus 9 ss Rem PLL EN 0 disable 1 PLL enable P value These bits can t be set 0 SAMSUNG ELECTRONICS 88 S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER PLLCON1 0xAF This register will be only reset by PRRESET or LVDRST en Rw Deo PLL M value 2 inii These bits can t be set 0 sov w mw mLswme s NOTE Although there is the equation for choosing PLL value we strongly recommended only the values in the PLL value recommendation Table 4 2 below If you have to use other value please contact to us Table 4 2 PLL value Recommendation Hz Target PLLCLK MHz k SAMSUNG ELECTRONICS 89 S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE 5 1 OVERVIEW interrupt controller has a total of 30 interrupt sources Each Interrupt request can be generated by internal function blocks or external interrupt pins Figure 5 1 shows how the IEx IPx registers and the polling sequence work together to determine which interrupt will be served After reset the CPU begins execution from location 0x0000 Each interrupt causes the CPU to jump to that location where it commences execution of the service routine If any interrupt is assigned to location 0 0003 and it is going to be used its service routine must begin at locatio
39. S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION CPU Control Registers Name Aaa RW PSW s oro Interrupt Control Registers amp w nw Ponty ones Je System Control Registers 87 SYSCFG System Configuration Register SAMSUNG ELECTRONICS 37 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION IVCON0 PLLCONO PLL control Register 0 PLLCON1 PLL control Register 1 USB Device Control Registers UJ 5 6 UJ USBEP1CSR1 USBEP1CSR2 USBEP2CSR1 USBEP2CSR2 USBEP2CSR3 USBEP3CSRO USBEP3CSR1 USBEPSCSR2 0xC5 USBEP3CSR3 USBEP4CSRO USBEP4CSRI1 USBEP4CSR2 USBEP4CSR3 USBEPOWC USBEP1WC1 USBEP1WC2 HN MN NW EN 200 00 EW 202 USB EP2 Common Status 200 USB EP2 Common Status Register2 200 USBEP2CommonStatusRegister3 202 USB EP3 Common Status Registro USB EP3 Common Status Register 200 USBEPSCommonStatusRegister2 200 USB EP3 Common Status Register3 202 200 00 202 203 s 03 EN 04 sr 03 NN 04 199 2 3 4 0 0 xBB xBC USBEP1CSR3 xBD xBE xB 2 xC xC2 2 xC3 xC4 2 2 2 USBEP2CSR0 0xG 7 F 1 7 2 2 2 USB EP1 Write Count Register 2
40. Select DPTR 0 1 register PSW 0xD0 rw 7 mw ove ___________ 00 available to the user for general purpose 00 Register Bank 0 0 00 0x07 01 Register Bank 1 0 08 0x0F 10 Register Bank 2 0x10 0x17 11 Register Bank 3 0x18 0x1F ACC 0xE0 Name Dei B 0xF0 z m Rw 0 AN B Register 0x00 SAMSUNG ELECTRONICS 51 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 2 PSW The PSW Program Status Word contains several status bits that reflect the current state of the CPU The PSW resides in SFR space at OxDO It contains the CY Carry bit the AC Auxiliary Carry for BCD operations the two registers bank select bits RS the OV Overflow the P Parity and a F0 F1 user defined status flag The serves the functions of a carry bit in arithmetic operations also serves as the accumulator A for a number of Boolean operations Auxiliary carry flag AC is set when the last arithmetic operation resulted in a carry into during addition or borrows from during subtraction the high order nibble The bits of RS are used to select one of the four register banks A number of instructions refer to these I RAM locations as RO through R7 Overflow flag OV is set when the last arithmetic operation resulted in a carry addition borrow subtraction or
41. to changed to other number from 5 to 15 USBNAKCON1 0xDC Name sr cru uss 74 mw end Address ransmi Donotsero Joo so mw 1st EPx wansmit NAK Do notseto NOTE 1 You set each USBNAKCON1 USBNAKCON registers separately NOTE 2 Do not set NAKEP1 and to 0 Setting with 0 will lead to error on will send NAK packet if the EP number matched with the one in NAKEP1 and NAKEP2 even though EP is already configured in USBEPxCSRx and USBEPLOGNUMXx USBNAKCON 0xDD en ceu uss Takers Rw at EPx Address to NAK Do notseto Makers Rw ara Address to wansmi Donoso NOTE 1 You set each USBNAKCON1 and USBNAKCON registers separately NOTE 2 Do not set NAKEP3 and NAKEPA to 0 Setting with 0 will lead to error on will send NAK packet if the EP number matched with the one in and NAKEPA even though 15 already configured in USBEPxCSRx and USBEPLOGNUMx SAMSUNG ELECTRONICS 205 er S3FH BG USER S MANUAL_REV1 00 14 USB CONTROLLER USBNAKEN 0xDE svo re reserves If you set this bit H W will send NAK packet as a response from IN NAKEN2 1 R W packet to all endpoints involved in USBEPNAKCONe register 0 NAK disable 1 NAK enable If you s
42. 0 No power Down 1 Power Down NS PD EN 2 Rw Sub IVC Power Down Enable when normal operation mode 0 No power Down 1 Power Down 1 RW Main IVC Power Down Enable when normal operation mode 0 No power Down 1 Power Down TRIMEN SBZ Should Be Zero WKUPSTAT 0xAD The field 7 4 of this register indicates which source is used for changing system state into normal mode from STOP mode The field 7 4 of this register can be cleared by writing 1 per bit or by entering into STOP mode __ Deseo USB 7 nw waewtyUsemomSTORmoe f s w 5 mcwu 5 w fp 1 wor 4 w Wake up by wacnaogimer STOP mode 0 mv PLLCONO 0xAE PLL control PLLCLK EMCLK MDIV 5 0 8 PDIV 3 0 2 2SDIVI1 0 The output frequency of the PLL is determined by the value MDIV and SDIV fields The reset value of MDIV and SDIV generates 48MHz output frequency when input is 12 2 When PLL_EN bit is set PLL clock will be generated after 300us lockup time when is 12MHz Especially you want to use over 24MHz PLL clock for FSOURCE the fields CLKDIV in CLKCON register should be set over FSOURCE 2 This register will be only reset by PnRESET or LVDRST si mw
43. 011 ESCLK External Sub Clock 32 768KHz Using PXTI and PXTO 101 PLLCLK 2 Output from PLL SMCLKCON 0xA4 This register will be only reset by or LVDRST The smart clock control register which controls input clock of VDMA 180 LCD BRJPEG and BRAC and also controls a number of wait clocks is used for low power and performance enhancement Ress 5 EN 6 smart Clock Enae toreo LoD eo Flash Read Wait Count register When EF_WAIT_MODE of PCON is 0 All Flash Area gt 0 0 wait 1 1 wait 2 2 wait 3 Reserved When EF_WAIT_MODE of PCON is 1 FLASH_WAIT_CNT 3 2 R W 0x00000 0x0FFFF gt 0 0 wait 1 0 wait 2 1 wait 3 Reserved 0x10000 0x5FFFF gt 0 0 wait 1 1 wait 2 2 wait 3 Reserved This bit should be set to 2 when Fsyg is greater than 20MHz and set to 1 when is greater than 10MHz If user want to use PLLCLK or IMCLK as clock source should think these bit value ONE CACHE EN One Cache Enable for performance enhancement and low power flash access Reserved Don t make this bit set to 1 to avoid anything unexpected CLK_EN0 0xA5 to supply each peripheral is frozen when bit of this register is set to 0 Nam Control into UART 0 block 00 7 RW 0 disable 1 enable Control into Timer 2 bloc
44. 12 1 H 172 12 2 FOAtUICS een 172 12 3 Block Danii u uw 173 Ne ub 174 12 5 Register m 176 ADC Controller 179 EE 179 13 2 Foa 179 13 3 PUM EP 179 13 4 Block donation wean 180 SEEMS 181 13 6 Register iene ene 183 USB Controller s s 188 e E 188 14 2 E 6alill68 u Etenim Wm kuku 189 143 Phi oi S E 190 14 4 Block eee 190 14 5 OperatiOM uuu EET 192 14 6 Register DescrptioOh tont REIR soe 193 uuu 207 1541 CILE 207 15 2 Features uuu 207 15 3 Block MDC TEL 208 4 ee 209 155 Register Desermplie Em 211 216 161 ean en neces ene fin hein 2
45. Internal OSC Typ 16MHz Peripheral Internal OSC CLKCONI4 3 Peripheral z Typ 32KHz PXTI 32 768KHz gt WDT gt USB gt RTCCLK CLK12M_PLL from USB CLK12M_SIE from USB ESCLK EMCLK CLKOUT RTC output clock ISCLK IMCLK Fsys CLKCON 7 5 Figure 4 6 Clock generator Block Diagram SAMSUNG ELECTRONICS 73 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER IMCLK INTERNAL MAIN CLOCK 16MHz IMCLK means an internal main clock 16MHz The internal 16MHz oscillator supplies the clock to the Fsource when CLKSRC field in register is 000b Enabling and disabling the internal 16MHz oscillator is possible by controlling Int16MOSCdis bit in SYSCFG register User should check Int16MOSCstable bit in SYSCFG register when IMCLK is used for the Fsource can t be used for PLL input After reset IMCLK is enabled by default and can be used for by default EMCLK EXTERNAL MAIN CLOCK 4 12MHz EMCLK means an external main clock The frequency range of external clock oscillator is allowed from 4MHz to 12MHz When the resonators from 4MHz to 8MHz and load capacitors are used as the external oscillator not recommended they have to be placed as close to the processor as possible in order to have the stable clock and minimize the stabilization time The value of load ca
46. No frame error during receive 1 Frame error Interrupt is requested Break Signal This bit is set to 1 automatically to indicate that a break signal has Detected BKD been received 0 No break receive 1 Break receive Interrupt is requested UINTCON 0xF5 These bits in conjunction with the IEURX IEURXERR and IEUTX in the IE1 register enables UART interrupts Name __ Deep URXERRINTPEND 7 R W RX ERROR Interrupt Pending Register This bit is cleared by setting 1 0 Non pending 1 Pending URXINTPEND R W RX Interrupt Pending Register This bit is cleared by setting 1 0 Non pending 1 Pending UTXINTPEND 5 R W TX Interrupt Pending Register This bit is cleared by setting 1 0 Non pending 1 Pending THE 4 R W Transmit empty Interrupt Enable 0 Disable 1 Enable THEIE 3 R W Transmit Buffer empty Interrupt Enable 0 Disable 1 Enable RXERRIE 2 R W Enable the UART to generate an interrupt upon an exception such as a break frame error parity error or overrun error during a Rx operation 0 Do not generate receive error status interrupt 1 Generates receive error status interrupt RSVD Reserved Don t make this bit set to 1 to avoid anything unexpected RDVIE R W Receive Data Valid Interrupt Enable 0 Disable 1 Enable UBAUD 0xF6 Baud Rate Select CNT0 1 x 16 CNTO Time constant value CNTO 7 0 0x20
47. PUSH Dir SP Dir Dir SP POP Dir SP 1 D0 If destination address Accumulator it is set or cleared Table 3 2 is Mnemonic and Operand description of each data transfer instruction Each function and effects on PSW are also described The symbol means no effect to PSW and the symbol gt means can effect to PSW SAMSUNG ELECTRONICS 55 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 2 ARITHMETIC INSTRUCTIONS These instructions are addition subtraction decimal adjustment increment decrement multiplication and division between two operands The accesses of addition and subtraction are by all addressing mode except indexed addressing The space can be incremented or decremented without going through the accumulator The MUL AB instruction multiplies the Accumulator by the B register and puts the product into the concatenated B and Accumulator registers The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8 bit quotient in the Accumulator and the remainder in the B register The DA A instruction is for BCD Binary Coded Decimal arithmetic operations In BCD arithmetic ADD and ADDC instruction should always be followed by a DA A operation to ensure that the result is also in BCD DAA will not convert a binary number to BCD The DA A operation produces a
48. RW 10 SEG24 O 11 EINTO 1 P7MOD 1 5 ame Pr RW Description 00 Input 01 Output GP77MOD 76 RW 10 52831 11 Reserved 00 Input 01 Output GP76MOD 5 4 RW 10 52030 11 Reserved 00 Input 01 Output GP75MOD 3 2 RW 10 SEG29 O 11 UTXD O 00 Input 01 Output GP74MOD 1 0 R W 10 SEG28 O 11 URXD 1 P7PUR 0 Pull up Disable 1 Pull up Enable 76 6 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable o GP73PU 0 Pull up Disable 1 Pul up Enable GP72PU 0 Pull up Disable 1 Pull up Enable GP71PU 0 Pull up Disable 1 Pull up Enable GP70PU 0 RW 0 Pull up Disable 1 Enable SAMSUNG ELECTRONICS 274 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO P8MODO 0xFE60 Name ek Rw Den 00 Input 01 Output GP83MOD 76 RW 10 I 11 EINT4 1 00 Input 01 Output GP82MOD 5 4 RW 10 I 11 EINTS 1 P8MOD1 0xFE61 Name aw Besrpion 00 Input 01 Output GP87MOD 7 6 R W 10 Reserved 11 SCSN B 00 Input 01 Output GP86MOD 5 4 R W 10 Reserved 11 SMOSI B 00 Input 01 Output GP85MOD 3 2 RW 10 Reserved 11 SMISO B 00 Input 01 Output GP84MOD 1 0 R W 10 Reserv
49. T2OUT O GPos TICAP TIOUT O TOOUT 0 ET GP00 SEG12 O I80D14 B Table 19 2 GPIO 1 Configuration PORT1 Selectable Functions Shared Function Gema creou GPs woo EINTS Gi ari 077000710 EI TION HOUT GP10 AIN3 1 T2CAP T2OUT O SAMSUNG ELECTRONICS 257 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO Table 19 3 GPIO 3 Configuration PORT 3 Selectable Functions Shared Function iu s BSOSN 0 Vos 0 BVISO aSCLK 0 ams crasu ame craou Gm Gema Grows Table 19 4 GPIO 4 Configuration PORT 4 Selectable Functions Shared Function FEE eu ee m GP42 Input GP42 Output SEG2 O 18004 B GP41 Input GP41 Output SEG1 O I80D3 B GP40 Input GP40 Output SEGO 0 8002 B Table 19 5 GPIO 5 Configuration PORT 5 Selectable Functions Shared Function 00 Default GP57 Input GP57 Output SCSN B GP56 GP56 Input GP56 Output SEG22 O SMOSI GP55 GP55 Input GP55 Output 5 21 SMISO 53 GP53 Input GP53 Output SEG11 O 180013 GP52 Input GP52 Output SEG10 O I80D12 B GP51 Input GP51 Output SEG9 O I80D11 B 5 GP54 Input GP54 Output SEG20 O SCLK B B
50. The analog input level must lie between the AVREF and AVSS values 13 2 FEATURES e Max 50K sampling per second with 3MHz e Programmable input clock frequency e 6 channel 10bit ADC e If Key scan or other ADC functions need to be used while ADC is in recording mode firstly the wanted function must be placed in ADC interrupt service routine and secondly after the wanted function finishes ADC operation should be returned to the previous recording mode 13 3 PIN DESCRIPTION Table 13 1 ADC PIN Description GPO PinNam GP8 2 ADIN 5 0 Analog Input pins for 6 channel Range 0 0V AVREF value GP8 3 GP1 0 GP1 1 GP1 2 GP1 3 AVREF ADC Reference Top Voltage Normally the max value of AVREF VDD SAMSUNG ELECTRONICS 179 er S3FI1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER 13 4 BLOCK DIAGRAM ADCON1 ADINSEL ADCON1 ADCKSEL I Fsys gt Clock Selector AIN1 GP12 AINO GP13 ADCONO ADCON 1 AIN2 GP1 1 Analog Comparator AIN3 GP10 gt ADATO 0 AIN4 GP83 AINS GP82 gt lt Y Conversion Result ADAT1 10 bit D A ADATO Converter P1MODO P8MODO Assign Pins to ADC input Figure 13 1 ADC Block Diagram SAMSUNG ELECTRONICS 180 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER 13 5 OPERATION A D Conversion Time The
51. ew Den ____ _ VDMA DONE IE RW done interrupt enable 0 disable 1 enable VDMA_ICLR 0xFFFB sr Rw eee o a o w done ST ee RW mee 000200000 done status This bit can set by writing 1 VDMA DONE ST R faw 0 idle 1 done R set W VDMA RGB 0xFFFD VDMA RGB 0xFFFE RGB B 0xFFFF VDMA RGB register is RGB color register for background image et SB VDMA RGB G VDMA RGB Green value Name s RW Besrpin SAMSUNG ELECTRONICS 225 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE 180 LCD INTERFACE The S3FI1BG has an 8080 series interface for LCD 17 1 FEATURES e Support parallel serial external LCD interfaces 8 bit 9 bit 16 bit 18 bit parallel 180 interface 3 4 wire serial interface e Support VDMA local bus interface 17 2 PIN DESCRIPTION Table 17 1 180 LCD Interface PIN Description Fm Geg sons Regiserselectonout GP6 2 I80RDN Read strobe output GPO 3 0 180D 17 0 Data Input Output GP5 3 0 GP4 7 0 GP6 7 6 SAMSUNG ELECTRONICS 226 er S3Fl1BG_USER S MANUAL_REV1 0
52. 0 P7PUR P8PUD1 OxFE63 R W PORT Pull Up Down Control Register 1 2 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 5 6 6 7 7 7 8 8 8 9 9 9 70 70 71 71 71 72 72 72 73 73 73 74 74 74 75 75 75 75 SAMSUNG ELECTRONICS 42 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION BRAC Control Registers BRAC_INT_PEND BRAC Interrupt pending Register 115 AN AN AN BRAC_START_ADRL oxFFo4 W Low Byte of BRAC Start Address for decoding compressed data BRAC START ADRM W Middle Byte of BRAC Start Address for decoding compressed data BRAC START ADRH W High Byte of Start Address for decoding compressed data W W W W W W BRAC SIZEM The data amount to be read from internal e FLASH or external serial FLASH BRAC SIZEH 09 The data amount to be read from internal e FLASH or 1 external serial FLASH 115 115 116 116 16 SIZEL OxFF07 The data amount to be read from internal e FLASH or external serial FLASH BRAC CTRL3 OxFFOE Control Register3 for BRAC 117 BRAC ENC CTRL oxFF10 R BRAC Encoder Status Register 117 BRAC SAMPLE L 0xFF11 W BRAC Encoder Sample Low Register 147 BRAC SAMPLE 12 W BRAC Encoder Sample High Register 117 BRAC RESULT Ox
53. 0 P7MODO GP70 GP73 Mode Control Register 0 P7MOD1 GP74 GP77 Mode Control Register 1 P7PUR PORT 7 Pull Up Control Register 0 P8MODO GP82 GP83 Mode Control Register 0 P8MOD 1 GP84 GP87 Mode Control Register 1 P8PUDO PORT Pull Up Down Control Register 0 P8PUD1 PORT Pull Up Down Control Register 1 NOTE These registers except P8 registers have to be accessed using instruction In the S3FI1BG most of the pins are multiplexed pins So it is determined by PnMODn register which function is selected for each pin If ports are configured as output ports data can be written to the corresponding bit of Pn Or if configured as input ports the data can be read from the corresponding bit of Pn When PnPUDn are configured as pull up or pull down it will be enabled 1us later SAMSUNG ELECTRONICS 261 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO PO 0x80 mw General Purpose I O 0 7 0 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user P1 0x90 Name pt nw Deseo General Purpose I O 1 P1 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user P3 0xB0 Name w Bespion General Purpose I O 3 P3 7 0 R W Each of these pins can be used as either any data transfer purpose
54. 10 Reserved 11 UTXD O 00 Input 01 Output GP15MOD 3 2 RW 10 Reserved 11 URXD 1 00 Input 01 Output GP14MOD 1 0 R W 10 CLKOUT O 11 EINT5 P1PUDO OxFEAE espion 00 Pull Up Down disabled 01 Pull down enabled GP13PUD 7 6 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP12PUD 5 4 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP11PUD 3 2 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP10PUD 1 0 R W 10 Pull up enabled 11 Don t use Never set SAMSUNG ELECTRONICS 268 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO P1PUD1 Name en Rw Reset sw 75 00 Pull Up Down disabled 01 Pull down enabled GP16PUD 5 4 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP15PUD 3 2 R W 10 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP14PUD 1 0 R W 10 Pull up enabled 11 Don t use Never set 50 Name aw 00 Input 01 GP33MOD 7 6 R W 10 Reserved 11 Reserved 00 Input 01 Output GP32MOD 54 R W 10 Reserved 11 Reserved 00 Input 01 Output
55. 107 The Playing Time of the 109 eren 110 BRAC Decoder Decoding Scheme Normal Play 2 111 BRAC Decoder Decoding Scheme Play 112 Serial Flash Controller Block Diagram l L nnne 120 Timing Diagram of read operation from external serial Flash 121 Application of voice E 122 BRJPEG Decoder Decoding Scheme sss enne nennen nennen 128 IDCT engine operation for MAC16 and MUL16 instructions 129 IDCT engine operation for ADD16H ADD16W and ADD32 insturctions 130 IDCT engine operation for SUM16W SUM32 instructions 2 131 SPI Block Diagralffi u ev dedu atl Debe daa 141 3 Wire Master Slave 143 4 Wire Master Slave Interconnection aaa 143 u L te cete Ente aie er LUE ER I BEC 144 4 Wire SPI Master Timing SCKPHA 0 144 4 Wire SPI Master Timing 1 145 4 Wire SPI Slave Timing SCKPHA 0 2 2 44 04 8
56. 1111 1111 XXXX XXXX Reserved Reserved Reserved SPIMOD 0100 0000 SAMSUNG ELECTRONICS 32 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Table 2 4 Extended Special Function Register Map 1 Upper Address Hex gt FE FE m MEMO P3MOD0 P8MOD0 0000 0000 0000 0000 0000 1100 XXXX XXXX 0000 0000 0000 0000 0000 0000 TODATAO T2DATAO DISP_MEM1 EINTMOD0 P3MOD1 P8MOD1 1111 1111 1111 1111 0000 0000 XXXX XXXX 0000 0000 0000 0000 0000 0000 TODATA1 T2DATA1 LCKSEL DISP MEM EINTMOD1 P8PUDO 11111111 11111111 0000 1111 XXXX XXXX 0000 0000 0000 1010 1010 0000 TOCNTO T2CNTO DISP_MEMS3 EINTMOD2 P3PUD1 P8PUD1 1111 1111 1111 1111 XXXX XXXX 0000 0000 0000 0010 1010 1010 TOCNT1 T2CNT1 DISP_MEM4 EINTMOD3 P4MOD0 1111 1111 1111 1111 XXXX XXXX 0000 0000 0000 0000 TOPDRO T2PDRO DISP MEM5 EINTENO PAMOD 1 0000 0001 0000 0001 XXXX XXXX 0000 0000 0000 0000 TOPDR1 T2PDR1 DISP_MEM6 EINTEN1 P4PUR 0000 0000 0000 0000 XXXX XXXX 0000 0000 0000 0000 7 DISP_MEM7 EINTPNDO P5MODO XXXX XXXX 0000 0000 0000 0000 T1CON DISP 8 EINTPND1 P5MOD 1 0000 0000 XXXX XXXX 0000 00000 0000 0000 T1DATAO DISP MEM9 POMODO P5PUR 1111 1111 XXXX XXXX 0000 0000 0000 0000 T1DATA1 DISP MEM10 POMOD1 P6MODO 11111111 XXXX XXXX 0000 0000 0000 0000 T1CNTO DISP_MEM11 POPUR P6MOD1 11111111 XXXX XXXX 0000 0000 0000 00
57. 16 2 ISCLK 32 768KHz Crystal oscillator C1 C2 22pF Sub IDLE mode Vpp 3 3V Disable ESCLK 32 768 2 IMCLK Disable ISCLK 32 768KHz Crystal oscillator C1 C2 22pF STOP mode 3 3V EMCLK Disable ESCLK Disable IMCLK Disable ISCLK Disable Sub STOP mode 3 3V Disable ESCLK 32 768 2 Disable ISCLK Disable Sub STOP mode Vpp 3 3V EMCLK Disable ESCLK Disable IMCLK Disable ISCLK 32 768KHz NOTE 1 Supply current does not include current drawn through internal pull up down resistors LCD voltage dividing resistors and external output current loads NOTE 2 Ippi and Ipp include a power consumption of external sub clock oscillation internal main clock oscillation and internal sub clock oscillation NOTE 3 is the current when the external main external sub internal main and internal sub clock oscillation stops SAMSUNG ELECTRONICS 284 er S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA Table 21 3 Electrical Characteristics TA 40 to 85 2 2 V to 4 2 V Se NN RES ee ee External interrupt input All external interrupt pins high low width PGP7 2 0 3 3V PGP8 3 2 PGP14 PGP3 7 PoRESET ss External Interrupt Figure 21 1 Input Timing for External Interr
58. 5 4 R W 10 VLC2 O 00 Input GP61MOD 3 2 R W 10 VLC1 00 Input GP60MOD 1 0 R W 10 VLCO P6MOD1 5 19 GENERAL PURPOSE I O GPIO 01 Output 11 180 01 Output 11 01 Output 11 Reserved 01 Output 11 nRSTOUT O Name Den 00 Input GP67MOD 7 6 R W 10 00 Input GP66MOD 5 4 R W 10 COM2 00 Input GP65MOD 3 2 R W 10 COM1 O 00 Input GP64MOD 1 0 R W 10 P6PUR 5 Name RW 0 Pull up Disable 66 6 0 Pull up Disable 0 Pull up Disable 0 Pull up Disable 0 Pull up Disable 0 Pull up Disable 0 Pull up Disable GPeOPU RW 0 Pull up Disable SAMSUNG ELECTRONICS Description 1 Pull up Enable 1 Pull up Enable 1 Pull up Enable 1 Pull up Enable 1 Pull up Enable 1 Pull up Enable 1 Pull up Enable 1 Pull up Enable 273 01 Output 11 180D1 B 01 Output 11 18000 B 01 Output 11 I80RS 01 Output 11 180CSN O S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 7 0xFE5D aw 00 Input 01 Output GP73MOD 7 6 RW 10 SEG27 O 11 UCLK I 00 Input 01 Output GP72MOD 5 4 RW 10 SEG26 O 11 EINT2 1 00 Input 01 Output GP71MOD 32 RW 10 SEG25 O 11 EINT1 I 00 Input 01 Output GP70MOD 1 0
59. A 1 12 2 ADDC A Rn 1 12 1 ADDC A Dir 2 12 2 SUBB A imm 2 12 2 SUBB A 1 12 2 SUBB A Rn 1 12 1 SUBB A Dir 2 12 2 INC A 1 12 1 INC Ri 1 12 3 ING Rn 1 12 2 ING Dir 2 12 3 ING DPTR 1 24 1 DEC A 1 12 1 DEC Ri 1 12 3 DEC Rn 1 12 2 DEC Dir 2 12 3 DA A 1 12 1 MUL AB 1 48 1 DIV AB 1 48 11 Detailed Unconditional Branch Instruction Summary Maximum Clock Cycles Unconditional Branch Instruction Bytes Standard 8051 S3FI1BG AJMP add1 1 2 24 3 JMP A DPTR 1 24 3 SJMP rel 2 24 3 LJMP add16 3 24 3 NOP 1 12 1 SAMSUNG ELECTRONICS 66 Um S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET Detailed Boolean Instruction Summary Maximum Clock Cycles Boolean Instruction Bytes Standard 8051 S3FI1BG ANL C bit 2 24 2 ANL C bit 2 24 2 ORL C bit 2 24 2 ORL C bit 2 24 2 CLR 1 12 1 CLR bit 2 12 3 CPL 1 12 1 CPL bit 2 12 3 SETB C 1 12 1 SETB bit 2 12 3 MOV C bit 2 12 2 MOV bit C 2 24 3 Detailed Subroutine Call Instruction Summary Maximum Clock Cycles Subroutine Call Instruction Bytes Standard 8051 S3FI1BG ACALL 11 2 24 3 LCALL add16 3 24 3 RET 1 24 4 RETI 1 24 4 Detailed Conditional Branch Instruction Summary In this case jump is not taken Maximum Clock Cycles Conditional Branch Instructi
60. BRAC ADDR VOLUME BRJPEG BITS LEFT XXXX XXXX 1111 1111 XXXX XXXX C DATA DCOL BRJPEG GET PEEK L XXXX XXXX 0000 0000 XXXX XXXX BRAC BUFF DCOH BRJPEG GET PEEK H XXXX XXXX 0000 0000 XXXX XXXX BRAC CTRL3 BRJPEG QP Y 0000 0000 XXXX XXXX BRJPEG QP C XXXX XXXX SAMSUNG ELECTRONICS 34 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Table 2 6 Extended Special Function Register Map 3 Upper Address gt FF7 69 mam XXXX XXXX XXXX XXXX 0000 0000 0000 0000 UE CC mmm XXXX XXXX XXXX 0000 0000 0000 0000 XXXX XXXX XXXX XXXX npa h CAM a XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX mu XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 0000 0000 O 0000 0000 XXXX XXXX 11111111 O 0000 0000 XXXX XXXX 0000 1111 07 0000 0000 0000 0000 NEN 0000 0000 0000 0000 e XXXX XXXX 0000 0000 XXXX XXXX 0000 0000 0000 0000 o ___ SAMSUNG ELECTRONICS 35 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Table 2 7 Extended Special Function Re
61. BRJPEG_ST 0xFF5B Mame __ aw Reset IDCT done status This bit can be set by writing 1 IDCT_DONE_ST 1 R 1 aw 0 idle 1 done R set W VLD done status This bit can be set by writing 1 VLD_DONE_ST R jwo cove st aw 0 idle 1 done R set W BRJPEG_VLD_MODE 0xFF5C BRJPEG_VLD_MODE register defines which operation will be done by VLD engine Name ek mw VLD operation selection 000 VLD_IQ 001 VLD 010 IQ VLD OP 7 5 RW 011 RESERVED 100 BITS 101 PEEK_BITS 110 DROP_BITS 111 FILL BUFFER Number of bits for GET_BITS PEEK_BITS DROP_BITS and rud FILL_BUFFER operations SAMSUNG ELECTRONICS 138 IEP S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER BRJPEG_IDCT_MODE 0xFF5D BRJPEG_IDCT_MODE register defines which operation will be done by IDCT engine Name operation selection 000 2D IDCT and Clipping 001 MAC16 010 MUL16 IDCT_OP 7 5 RW 011 ADD16H 100 ADD16W 101 ADD32 110 SUM16W 111 SUM32 SAT DIS 4 RW IDCT saturation i Undef 0 saturation enable 1 saturation disable Number of operations for MAC16 MUL16 ADD16H ADD16W BRJPEG IDCT ACC 0 0xFF60 BRJPEG IDCT 1 OxFF61 BRJPEG ACC 2 0xFF62 BRJPEG IDCT ACC 3 0xFF63 BRJPEG IDCT ACC 31 0 register is the accumulator for the IDCT operations en
62. DI 55 lt gt ANL Dir imm Dir lt Dir amp imm 53 ANL Dir A Dir Di 52 ORL A imm A A imm 44 e ORL A A Ri 46 47 oe ORL A Rn A A Rn 48 oe ORL A Dir A A Dir 45 o ORL Dir imm Dir lt Dir imm 43 ORL Dir Dir lt Dir A 42 XRL A imm A lt A imm 64 e XRL A Ri A A Ri 66 67 e XRL A Rn A A Hn 68 6F lt XRL A Dir A A Dir 65 Dir imm Dir lt Dir imm 63 XRL Dir A Dir lt Dir A 62 CLR A A lt 0 E4 lt CPL A A lt F4 SWAP A 7_4 lt 0 4 An 1 lt lt 0 6 RL A A0 _ 7 23 1 lt lt 0 6 RLC A CY A7 33 lt gt lt gt 1 gt gt 0 6 RR A A0 _ 7 03 1 gt gt 0 6 RRC A A7 CY 13 e lt If destination address are Accumulator it is set or cleared SAMSUNG ELECTRONICS 64 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 4 INSTRUCTION SET SUMMARY The S3FI1BG is fully binary compati
63. Erase PROG_MODE 1 R W When sector erase mode FCON_ADDR_H and FCON_ADDR_M pair is sector number This controller does not support Chip Erase 5 1 FCON BUSY This register indicates the status of FCON 1 Flash write is in progress 0 Flash write is done ADDR 1 0xFFA2 FCON ADDR M 0xFFA3 FCON ADDR 0xFFA4 Description Flash Program Address Half Word Address Internal flash is composed of 16 bit data Then this register can address 512 bytes 1 sector data When sector erase this register has no effect This register is auto incremented during Flash Programming mw Desn R W R W Flash Program Erase High Address Half Word Address AN R W WDATA 0xFFA5 7 0 RAW Flash Program Lower Write Data SAMSUNG ELECTRONICS 280 er S3Fl1BG_USER S MANUAL_REV1 00 20 EMBEDDED FLASH CONTROLLER FCON WDATA H EN 0xFFA6 Deep Reset Flash Program Upper Write Data and Write Enable Register When this register is written Flash Write Operation starts Flash Erase Program does NOT proceed when corresponding protection bit is set FCON WP 8 Description Flash Program Erase Protection Low Register Each bit protect 32KB blocks of internal flash 1 Protected 0 Not Protected Bit 0 0x00000 0x07FFF Bit 1 0x08000 0x0FFFF Bit 2 0x10000 0x17FFF Bit 3 0
64. GP31MOD 3 2 R W 10 Reserved 11 Reserved 00 Input 01 Output GP30MOD 1 0 R W 10 Reserved 11 Reserved NOTE When reset PGP3 0 TCK PGP3 1 TMS PGP3 2 TDI is used as JTAG input pins and PGP3 3 is used as JTAG output pin PSMODO register is effective only when JTAGOFF register is 1 P3MOD1 0xFE51 Name 00 Input 01 Output GP37MOD 7 6 RW 10 BSCSN O 11 EINTO 00 Input 01 Output GP36MOD 5 4 R W 10 BMOSI B 11 EINTS 00 Input 01 Output GP35MOD 3 2 RW 10 BMISO B 11 EINT7 1 00 Input 01 Output GP34MOD 1 0 RW 10 BSCLK O 11 EINT6 I SAMSUNG ELECTRONICS 269 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 52 aw 00 Pull Up Down disabled 01 Pull down enabled GP33PUD 7 6 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP32PUD 5 4 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP31PUD 3 2 R W 10 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP30PUD 1 0 R W 10 10 Pull up enabled 11 Don t use Never set P3PUD1 OxFE53 Name aw Desripion 00 Pull Up Down disabled 01 Pull down enabled GP37PUD 7 6 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down d
65. Handling Different Level Interrupts Lower Level is first issued Normal Program Processing Single Interrupt 2 Level Interrupt 3 Level INT Disable gt Interrupt Setting Level Service Routine SPI Interrupt IPWDT 0 IPSPI 1 gt IPT2 1 IPEXT1 1 SENICE Routing 2 Interrupt Service Routine Y INT Enable p EXINT1 WDT Interrupt i Interrupt Generated Service SPI Interrupt Routine Generated T2 Interrupt EXEAT RE Generated Interrupt Generated Figure 5 5 Handling Multiple Level Interrupts SAMSUNG ELECTRONICS 94 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE 5 4 REGISTER DESCRIPTION SUMMARY Name Aa Rw Desn aw interrupt foo SAMSUNG ELECTRONICS 95 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE GIE 0x91 R W Global Interrupt Enable 0 Disable All interrupt 1 Enable All interrupt saen seam ____________ Reserved 0 00 IE0 0 92 Br mw IET1 0 Disable Timer 1 interrupt 1 Enable Timer 1 interrupt IETO 6 RW 0 Disable Timer 0 interrupt 1 Enable Timer 0 interrupt IESPI 0 Disable SPI interrupt 1 Enable SPI interrupt IEEXT 1 0 Disable External interrupt 1 1 Enable External interrupt 1 IEEXTO 0 Disable External interrupt 0 1 Enable Exte
66. In the above case the voice data _chord_16K_mono is compressed into 4 Bit So the 4 Bit compression is selected like Sentence Index E SAMSUNG ELECTRONICS 104 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 4 USING INTERRUPT SERVICE ROUTINE FOR BRAC DECODING BRAC decoding starts immediately after the setting of BRAC_CTRL as 0x81 or 0x89 And the end of BRAC decoding can be detected by polling or interrupt method The polling means S3FI1BG should check the BRAC SIZEx register whether it s value becomes zero or not Zero value means all the BRAC data is decoded and no more data is remained to be played But this operation requires the operational load of the S3FI1BG and spends more power Instead of this the interrupt method is simple and easy to check the end of BRAC decoding Sentence C Programmin Index g g pem a E B rBRAC_INT_PEND BRAC_PEND PlayNext void BracDmatTest 1 rGIE 0x80 PlayNext BRAC interrupt is assigned to Interrupt 1 as like Sentence Index A The syntax interrupt 1 gives the interrupt information to the C compiler and the interrupt vector table is generated automatically at address OxOB by C compiler And the interrupt should be enabled like Sentence Index C in the initialization routine And in the interrupt service routine the interrupt pending vector should be clea
67. Operation amp Functions HEX cy RS P 74 e MOV A Ri A lt E6 E7 Rn E8 EF lt gt MOV _ A Dir A lt Dir E5 lt gt MOV Ri A Ri F6 F7 MOV imm Ri 76 77 MOV Dir Ri lt Dir A6 A7 MOV Rn A Rn F8 FF MOV Rn Dir Rn Dir 8 MOV Rn imm Rn 78 MOV Dir Dir F5 MOV Dir imm Dir 75 MOV Dir Dir Ri 86 87 Dir Rn Dir Rn 88 8F MOV Dirt Dir2 Dirt lt 85 MOV DPTR imm16 lt 90 MOVC A A DPTR lt A DPTR 93 lt gt lt 1 A PC 83 o MOVX DPTR DPTR EO lt gt A Ri E2 E3 lt gt MOVX DPTR A DPTR lt FO MOVX Ri A Ri A F2 F3 XCH A Ri A o C6 C7 XCH A Rn A o9 Hn C8 CF o XCH A Dir A lt Dir C5 o XCHD A Ri A3 0 lt Ri 3 0 D6 D7 o SP lt 5 1
68. Operation amp Functions HEX HEX cy FO RS OV If bit 1 bit 20 lt If bit 1 bit rel 10 lt bit 0 If CY 1 JC rel 40 lt If bit 0 JNB bit rel 30 PG lt PC rel If CY 0 JNG rel 50 PG lt PC rel If A 0 JZ rel 60 PG lt PC rel 0 JNZ rel 70 e lt If Ri imm CJNE Ri imm rel PC lt PC rel Beez j me x w CY lt Ri imm CY lt gt imm z imm CJNE A immrel PC lt ala ee 1 A lt imm CY lt gt imm Dir If A Dir B5 e SAMSUNG ELECTRONICS 61 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET PC lt 1 A Dir lt gt Dir If Rn imm CINE Rn imm re PC rel Bie BE 5 lt imm 0 Rn gt Dir Dir 1 DJNZ rel If Dir 0 D5 lt lt 1 If Rn 0 DJNZ Rn rel D8 DF If destination addresse
69. Ox1c Oxad 2 0x01 Ox3f 0x1a 0x2a 0 5 3 0x01 0x69 0x77 0 0 0x2c 4 0x01 0x77 4 0x07 0x56 5 0x01 0x7e Oxfb 0x3c 0xb9 6 0x01 0xbb 0xb5 0x13 5 74 0x01 Oxcf 0x7b 0x96 8 0x02 Oxba 0x12 Oxea 0x96 9 0x03 0xa4 0xa9 0x0f 107 0x03 0xb4 0x4d OxOc Oxef 11 0 03 Oxc1 Ox3d 12 0 03 Oxcd 0x0d 0x75 13 0x03 Oxda 0 0 14 0x03 0 9 0 0 15 0 03 Oxf8 0x48 7 167 0 04 0 05 7 0x0b 0xcb 17 0x04 0x11 0x93 Oxf7 18 0x04 Ox1c Ox8b 0x10 0x10 19 0x04 0x2c 9 0x08 Ox2f The voice compressed data can be stored into any address of flash memory User can define the address in the Power Development Studio tool For this example it is assumed that the address starts from Ox7FFF The Filelnfo information includes the string data of waveform file name sampling frequency and compression format The FilePos information includes the start address and the size of each voice compressed data These data are required to play the voice for the S3Fl1BG The address is consisted of three byte and the size is two bytes select the range of waveform by mouse drag gt Wave create new waveform with select If the 3 bit compression is selected then higher compression algorithm is sele
70. RESET SWRST Software can initialize the internal state by writing the RSTCON register Watchdog RESET WDTRST The watchdog timer monitors the devices state and generates the watchdog reset when the state is abnormal Low Voltage Detect RESET LVDRST When VDD is changed in condition for LVD operation in the normal operation mode reset occurs PnRESET SWRST WDTRST LVDRST Figure 4 1 RESET source of the S3FI1BG When LVD circuit detects VDD below VLVD reset is generated When Watch dog timer overflow is occurred reset is generated PnRESET pin is issued to low reset is generated Chip reset occurs when it writes OxB into RSTCON register SAMSUNG ELECTRONICS 70 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER Pin RESET PnRESET Pin reset is invoked when the PnRESET pin is asserted and all units in the system except RTC block are initialized to known states When the unmaskable PnRESET pin is asserted as low the internal hardware reset signal is generated Upon assertion of PRRESET the SSFI1BG enters into reset sate regardless of the previous state The internal oscillator stabilization time is 6 1ms Over 2us PnRESET Internal Oscillator Stabilization time about 6 1 ms 16MHz IMCLK Internal Reset Figure 4 2 Pin RESET Sequence LVD RESET LVDRST The Low Voltage Detect Circuit is built on the S3FI1BG to generate a system reset When LVD circ
71. SAMSUNG ELECTRONICS 161 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART URXBUF 0xF7 UTXBUF 0xF8 TXBUF Transmit Data Undef SAMSUNG ELECTRONICS 162 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART Programming TIP An example setup procedure with a description of each step is shown below Setup Procedure Description void UART NONFIFO setup rCLK_EN0 0 80 1 Enable UART operation clock rP7MOD1 0x0F 2 Set P7MOD1 register for UART operation Using GP1 rP1PUDO 0x00 pullup disable rP1MOD1 0x3C rlE1 0x04 3 Enable UART TX interrupt rGIE 0x80 4 Enable Global interrupt rUBAUD 12 5 Baud Rate 57600 12MHz rUINTCON 0x18 6 TXIDLE THE interrupt enable rUCON1 0x06 7 Clock source 8 bit word length 1 stop bit per frame rUCONO 0x01 8 No parity Transmit enable At this time interrupt will be generated because Transmit holding buffer is empty Some data should write to UTXBUF in UART TX interrupt service routine SAMSUNG ELECTRONICS 163 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS TIMERS 11 1 OVERVIEW S3FI1BG have three 16 bit timers Timer 0 1 and 2 Timers have Pulse Width Modulation PWM function capture function and timer output pins All timers have a clock divider independently All timers input output pins are multiplexed with GPIO pins The timer down count register will be decreased whe
72. SEG Controller Driver Registers LCD Control Register LCD Contrast Control Register Add LCON RW LCNST OxFE21 LCKSEL OxFE22 R W LCD Clock Select Register DISP MEMO OxFE30 RA Display Memory 0 AN RAN RAN DISP MEM2 OxFE32 R W Display Memory 2 DISP OxFE33 Display Memory DISP 4 OxFE34 RW Display Memory 4 DISP MEMS5 OxFE35 RW Display Memory 5 DISP 6 OxFE36 Display Memory 6 AN AN AN AN RW RW RW RW DISP MEM OxFES1 RW DispayMemoy RW RAW RAW RW RW DISP 7 Display Memory 7 DISP 8 OxFE38 RW Display Memory 8 DISP 15 0xFE3F Display Memory 15 2 GPIOs Control Registers 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 54 54 54 43 43 43 43 43 43 43 43 43 43 43 43 43 43 43 43 Reserved for standard 8051 262 RW 262 262 R W R W R W General Purpose I O 6 262 General Purpose I O 7 263 OxE8 General Purpose 8 263 rw 05 SAMSUNG ELECTRONICS 41 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION POMOD1 OxFE4A R GP02 GP03 Mode Control Register 1 PAPUR P6MOD0 OxFE5A RW P6MOD1 OxFE5B R W GP64 GP67 Mode Control Register 1 AN PePUR 5 RAW PORT 6 Pull Up Control Register 0 P7MODO OxFE5D R GP70 GP73 Mode Control Register
73. Space Memory 28 Data Space Memory Structure 222 renis 29 RAM Memory sje 30 RESET so rce of the SSF BG iiu iit enint te d dre td mega dl Lid 70 RESET Sequence nec e bie e 71 LVD RESET Seque6nce eibi ide Ite dades dag a det edes 71 Software RESET Timing u a A eee oa EO Ee dec E LEO dep 72 Watchdog RESET Timing iioi casted e 72 Clock generator Block 73 Main Oscillator eU E 74 PLL Block Diagram c 75 The case that changes clock souroe U U U U 76 Power down mode State Diagram 78 Entering STOP mode and Exiting STOP mode 81 Interrupt Control Systems Rr 91 Handling Same Level of Interrupts l n n 93 Handling Different Level of Interrupt Higher Level is first issued 93 Handling Different Level Interrupts Lower Level is first issued 94 Handling Multiple Level 94 DG level shifting
74. USBEP2WC1 USB EP2 Write Count Register 1 2 USBEP2WC2 USB EP2 Write Count Register 2 2 SAMSUNG ELECTRONICS 38 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION oe sero or utero oe lt a EJ EN Ee Ex HEN E Cw USBEPOFIFO IN ADC Control Registers R Aaa RW Page ADREFCMP RW ADC Reference Compare Register 187 WDT Control Registers Add RW Description WDTCON WDT Control Register WCNTCLK WDT Counter Pre Scale value register WDTCNT R Counter WDTREF WDT Reference Value UART Control Registers UCONO UART Control Register 0 159 SAMSUNG ELECTRONICS 39 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION UCON1 UART Control Register 1 159 UTRSTAT UART TX RX Status Register 160 UERSTAT UART RX Error Status Register 160 SPI Conirol Registers Timer Control Registers T1DATA1 OxFEOA Timer 1 Reference Data Register 1 170 T2DATA1 OxFE12 Timer 2 Reference Data Register 1 170 T2CNTO OxFE13 Timer 2 Lower Down Counter 170 T2CNT1 OxFE14 R W Timer 2 Upper Down Counter 170 SAMSUNG ELECTRONICS 40 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION T2PDRO OxFE15 Timer 2 PWM Data Register 0 171 OxFE16 Timer 2 PWM Data Register 1 171 LCD COM
75. VSSUSB USBPHY Ground AVSS Analog Ground for ADC and DAC SAMSUNG ELECTRONICS 24 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION MEMORY ORGANIZATION There are three kinds of memory areas 384KBytes e FLASH 4KBytes X RAM and 256Bytes I RAM Figure 2 1 shows the memory organization of the S3FI1BG I RAM includes 4 banks of 8 working registers and can be available as stack area X RAM is 4KBytes and can be used for the data memory and code memory also The total size of e FLASH for the SSFI1BG is 384KBytes and can be used for the data memory and code memory X RAM and e FLASH are separated physically but are mapped into the same memory space together logically depending on the register values of XRAMB and ROMB in terms of code memory space and data memory space The register XRAMB and ROMB choose the BANK depending on it s value The BANK 0 of e FLASH is the basic BANK for code memory space and is mapped to the address 0x0000 Ox7FFF regardless of the XRAMB and And X RAM is also the basic data memory and is mapped to the address 0x8000 Ox8FFF also The detail conceptual block diagram and its explanation are described in Chapter 2 1 and Chapter 2 2 SAMSUNG ELECTRONICS 25 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION 0x5 FFFF 32 Kbytes BANK 11 0 5 8000 eXtended SFR 4 Kbytes XRAM 0x8000 0x1_FFFF 32 Kbytes BANK 3 0x1_8000 0x1_7FFF Upper
76. ae eee cma s Pop 7 Fe Fes Gas ms Pwe crear SAMSUNG ELECTRONICS 18 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION mew o Tem ems RESET RESET Pes Po mo mo o Pereo o Por Ge oes Fu a ee Pup Poma ares 3 cescowmes ome Gee J Tas La Pop J arearsecaneoos J Tas papas apaaisecareoos Gea J 5 oma s ems emssecmo os 3 s ome 7 ww wo w ws vs s eer ermseameo cz s omo Go 1 Ls er J 5 roms 7 5 roms
77. byte of intermediate bit stream buffer 135 BRJPEG GET BUFFER M 0xFF49 Middle byte of intermediate bit stream buffer 135 BRJPEG GET BUFFER H OxFF4A High byte of intermediate bit stream buffer 135 BRJPEG IBB PTR M OxFF45 R W Middle byte of video input bit stream buffer address 134 BRJPEG BITS LEFT OxFF4B R W Number of valid bits in GET BUFFER 135 9 SAMSUNG ELECTRONICS 44 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Accumulator byte 3 MSB in IDCT engine 139 RTC Control Registers RTCCONO OxFF80 RTC Control Register 0 212 RTCCON1 OxFF81 RTC Control Register 1 212 AN raw raw SAMSUNG ELECTRONICS 45 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Embedded Flash Control Registers FCON_CTRL OxFFAO FCON_STAT OxFFA1 FCON ADDR L OxFFA2 FCON WDATA L 5 WDATA OxFFA6 R FCON_ADDR_H OxFFA4 Address High and Write Start Register 280 Write Data Low 280 Write Data High and Write Enable Register 281 FCON_WP_L OxFFA8 Program Sector_Erase Protect Low Register 281 FCON_WP_H 9 Program Sector_Erase Protect High Register 281 I80 Interface Registers I80LCD_TP_W0 I80LCD_TP_W1 I80LCD_TP_W2 I80LCD_TP_W3 I80LCD_TP_W4 I80LCD_TP_W5 I80LCD_TP_W6 I80LCD_TP_RO I80LCD_TP_R1 I80LCD_TP_R2 I80LCD_TP_R3 I80LCD_TP_R4 I80LCD_CFG_0 SAMSUNG ELECTRONICS 46 Number of H
78. done interrupt enable a 0 disable 1 enable E ISOLCD OxFFDA Name aw Besrpon np mesa pone e done b 1801 _ 0xFFDB Name Rw Deep vo BUSY_ST 1 2 status 0 idle 1 busy DONE_ST RW I80LCD done status This bit can be set by writing 1 0 idle 1 done R set W SAMSUNG ELECTRONICS 240 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER LCD DRIVER CONTROLLER 18 1 OVERVIEW The LCD driver controller has 4 com x 32 segment drivers so that a maximum of 128 segments panel are controllable Each segment is controlled by a corresponding bit in the LCD Display Memory Register 18 2 FEATURES e LCD controller driver Display Memory 0 0 0 Registers contain the data to be displayed the LCD 32 segment output pins SEGO SEGS1 e 4common output pins COMO COM3 4 LCD operating power supply pins VLCDO LCD bias by internal or external voltage dividing resistors e Programmable bias voltage level selector e Supports bias and duty mode for each corresponding operation e Programmable frame clock generator 18 3 PIN DESCRIPTION Table 18 1 LCD PIN Description GP6 7 4 CON 3 0 Appropriate voltage level for COM driver signal GP7 7 0 SEG 31 0 Appropriate voltage level for SEG driver signal GP5 7 4 GPO 7 0 GP
79. each index parameter of external LCD device 0 1 byte 1 2 bytes SAMSUNG ELECTRONICS 238 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE I80LCD_DATA_0 OxFFD2 Description 2 2 DATA 0 W Data buffer byte 0 I80LCD_DATA_1 0xFFD3 Data buffer byte 1 DATA_1 7 0 RW I80LCD_DATA_2 4 W Data buffer byte 2 I80LCD_DATA_3 0xFFD5 R W Data buffer byte 3 I80LCD_DATA_4 0xFFD6 Data buffer byte 4 I80LCD_DATA 5 0xFFD7 DATA_2 DATA_3 7 B 2 2 DATA_4 7 R DATA_5 7 0 Data buffer byte 5 Description Undef Undef Undef Undef Undef Undef SAMSUNG ELECTRONICS 239 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE I80LCD_CMD 0xFFD8 Name RW Deep Number of I80LCD transactions It is different depending on the data type METRAN Index Parameter transfer bytes gt gt I80LCD_ _P_BIT_LEN 1 RGB data transfer bytes gt gt I80LCD_RGB_N_PIXEL 3 1 KEEP_CSN_LOW te CSN is kept low after the transaction is done when this bit is CMD_WR 3 RW 0 read transaction 1 write transaction I80LCD transaction type MD_TYPE 00 Index 01 Parameter 10 RGB data 11 180 enable command When set it is not cleared until the I80LCD_ EN I80LCD operation is done 0 idle 1 enable W busy R I80LCD_IE OxFFD9 I80LCD
80. has frequency multiplication capabilities for the output clock frequency PLLCLK based on the input clock frequency EMCLK by the following equation PLLCLK EMCLK MDIV 5 0 8 PDIV 3 0 2 2SDIVI1 0 Where MDIV the value for Main Divider PDIV the value for Pre Divider SDIV the value for Post Scaler Pre Divider Post Scaler PLLCLK 1 Main Divider Figure 4 8 PLL Block Diagram MDIV PDIV and SDIV are the values for programmable dividers see the register description The PLL consists of a Phase Frequency Detector PFD a Charge Pump a Voltage Controlled Oscillator VCO a pre divider a main divider and post scaler as depicted in Figure 4 8 above PLL generates clock sources for USB and FsouRncE Changing PLL Settings in Normal Operation During the operation of the S3FI1BG in NORMAL mode if the operation frequency wants to be changed by writing the PMS value the sequences are as follows Enable an external main oscillator EMCLK by controlling MAIN OSC DIS bit in CLKCON register Checking an external main oscillator stable by monitoring MAIN OSC STABLE bit in SYSCFG register Changes PMS value in PLLCONO and register Enable PLL by controlling PLL EN bit in PLLCONO register SAMSUNG ELECTRONICS 75 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER Check
81. high SAMSUNG ELECTRONICS 206 S3Fl1BG_USER S MANUAL_REV1 00 15 RTC RTC 15 1 OVERVIEW The data of RTC includes second minute hour date day of the week month and year The RTC units works with an external 32 768KHz crystal ESCLK from PXTI and also can perform the alarm function Please refer to Figure 15 2 using s w code 15 2 FEATURES e Time information seconds minutes hours directly in BCD code e Calendar information date month year day of the week directly in BCD code up to year 9999 e Leap year generator e Alarm interrupt Wake up signal generation to exit from STOP mode This interrupt can be set by sec unit is the shortest time to be set e Cyclic interrupt the interrupt cycle may be 1 512 1 256 1 64 1 16 1 4 1 2 and 1 second SAMSUNG ELECTRONICS 207 er S3Fl1BG_USER S MANUAL_REV1 00 15 RTC 15 3 BLOCK DIAGRAM RTCOSC Oscillator and Leap Year Generator RTCCLK Clock Divider 32 768 2 PRIINT lt Control Register ALARM Generator m gt ALMINT Figure 15 1 RTC Block Diagram SAMSUNG ELECTRONICS 208 er S3Fl1BG_USER S MANUAL_REV1 00 15 RTC 15 4 OPERATION RTC RST bit of RSTCON register System Controller goes HIGH to LOW for resetting RTC block After that RTC block should be activated LEAP YEAR GENE
82. input channel select ADINSEL R W 000 ADINO 001 ADIN1 010 ADIN2 011 ADIN3 100 ADIN4 101 ADIN5 SAMSUNG ELECTRONICS 185 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER ADATO 0xE3 AD Conversion Ready indication 0 ADC preparing 1 ADC Ready When ADCEN is set to 1 ADC source clock selected by ADCKSEL is supplied to ADC ADC operation will be ready after 3 clocks are supplied ADRDY is a flag bit of this readiness Once the ADC gets into ready state while the ADCK is supplying the ADC is always in ready status so that it is not necessary to check ADRDY bit again When ADCEN bit in ADCON0 is cleared to 0 ADRDY is cleared to 0 as well AD Conversion Completion Indication 0 ADC on going 1 ADC complete The bit indicates the end of conversion process that is started by STC 1 or recording request End of conversion can be notified by either setting EOC bit or the ADC interrupt EOC bit is automatically cleared as below In ADMOD 0 Normal mode or ADMOD 3 Recording mode is cleared by reading ADATA0 ADMOD 1 Infinite mode or ADMOD 2 Compare mode is automatically cleared by hardware ADAT1 0xE4 Pen ADATA1 AD conversion result 9 2 ADREF 0 5 When ADC Compare mode if ADREF ADREFCMP Interrupt is occurred When ADC Recording mode recorded data is stored in this register Upper Recorded Data AD result 9 AD result 8 2
83. is applied 110 1 bit plane 111 VDMA_RGB register VDMA foreground source memory 00 XRAM 01 I80LCD 10 Internal eFlash 11 External serial flash 221 S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA Set this field to XRAM if this field is not required for the operation VDMA blending enable 0 disable Only background image is moved to the destination VDMA BLEND EN RW memory 1 enable Foreground and background images are blended and moved to the destination memory VDMA H LEN 0xFFE2 Mam Bt aw Pesrpi VDMA H LEN Horizontal length 1 for the background and destination moving area VDMA V LEN 0xFFE3 Mam s jaw VDMA V LEN Vertical length 1 for the background and destination moving area DST WIDTH L 0xFFE4 VDMA DST WIDTH H 5 DST WIDTH 8 0 register keeps the horizontal image frame width of the destination a Bees VDMA DST H WIDTH L Bits 7 0 of the horizontal width of the destination frame Bee Pisi VDMA DST WIDTH 0 RW of the horizontal width of the destination frame VDMA DST ADDR L 0xFFE6 VDMA_DST_ADDR_H 0xFFE7 VDMA DST ADDR 11 0 register is the destination memory address if it is XRAM Name Bit Rw Besrpin VDMA DST ADDR L Bits 7 0 of the destination area starting address
84. read in 8 bit ienaa max 6 bytes min tbyte Figure 17 3 I80LCD 8 bit interface for Index Command transfer 229 S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE LCD_RS LCD_CSN LCD_WRN Internal_ LCD_DO 7 0 LCD 07 0 LCD RS LCD CSN LCD RDN LCD 07 0 Internal Data Capture Registers Parameter read in 8 bit interface max 6 bytes min 1 byte Figure 17 4 I80LCD 8 bit interface for Parameter transfer SAMSUNG ELECTRONICS 230 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE LCD_CSN LCD_WRN 83 DATA of7 5 LS 1 7 5 G3 DATA 4 7 5 Internal_ LCD DO T7 0 LCD D 7 0 R3G3B2 R3G3B2 1 RGB332 write 8 bit interface max 2 pixels min 1pixel LCD_RS LCD_CSN LCD_RDN LCD D 7 0 R3G3B2 R3G3B2 Internal DATA _017 51 83 Data Capture DATA_1 7 5 G3 4 Registers BAFA FEB DAFA RGB332 read 8 bit interface max 2 pixels min 1pixel Figure 17 5 IB0LCD 8 bit interface for RGB332 transfer SAMSUNG ELECTRONICS 231 er S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE LCD_CSN LCD_WRN Internal_ LCD_DO 7 0 LCD D 7 0 R5G3 G3B5 R5G3 G3B5 I 1 1 RGB565 write 8 bit interface max 2 pixels min 1pixel LCD_CSN LCD_RDN LCD 07 01 Internal _ DATA 0 3 5 1 42 G3 DATA 442 G3 Data Capture DATA 17 51 G3 DATA 27 3 B5 DATA 5 7 3
85. to internal RAM spaces SFR locations Remember the Upper 128 bytes of internal l RAM can be accessed only by indirect addressing and SFR space only by direct addressing The stack pointer resides in internal IRAM The PUSH instruction increment the SP then copies the byte into the stack The POP instruction fetches the byte from the stack and then decrement the SP PUSH and POP use only direct addressing to identify the byte being saved or restored but the stack itself is accessed by indirect addressing using the SP register This means the stack can go into the upper 128 but not SFR space The Data Transfer instructions include a 16 bit MOV that can be used to initialize the Data Pointer DPTRx x 0 1 for look up tables in e FLASH or for X RAM accesses The XCH XCHD can be used to facilitate data manipulations MOVX instruction is used to access the internal X RAM and e FLASH area Only indirect addressing can be used The choice whether to use a one byte address QRi where Ri can be either RO or R1 of the selected register bank or a two byte address 9 DPTR MOVC instructions are available for reading lookup tables in internal X RAM or e FLASH memory SAMSUNG ELECTRONICS 54 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET Table 3 2 Mnemonic and Operand of Data Transfer Instructions PSW Mnemonic amp Operand
86. user program user should prepare the compressed voice data and store it into flash memory as follows For more details please refer to Power Studio User s Manual This example is the default samples included in Power Studio Open the project Project gt Open project gt SimpleVoice Simple Voice prj If the default project SimpleVoice is opened then step 1 to 3 in the following procedure can be skipped 1 Prepare the waveform wav file to be encoded 2 Include the waveform into Wav File Folder in the project through Add files to project in Project Menu 3 Edit the waveform Cut Paste Delete Copy and test it with Play Stop and re sampling command in tool bar 4 Build gt Build Brac in Menu A Choose the order of waveform and Compression ratio 3bit 4bit B All the information for this compression is stored into 2 files with the name of project name brc and project name h which are located in the chosen directory C Fill the blank in Memory start address of BRAC Data D Press Build button If any error check the size of compressed voice data 5 Download the compressed data project name brc into e FLASH A Tools gt Brac Data Writing in Menu B Choose type of flash memory internal e FLASH or external Serial Flash C Type the same address as the start address written in 4 C step in the range of the chosen flash memory for this example Ox7FFF 1 of End address mea
87. write operation 4 becomes I80LCD_TP_W4 1 I80LCD_TP_W5 0xFFC5 RW Deep mw z mesa Number of ending cycle of LCD_CSN low in LCD write operation becomes _ 5 IBOLCD W5 1 SAMSUNG ELECTRONICS 236 eq S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE I80LCD_TP_W6 OxFFC6 _ RW mw z TP_W6 Number of cycles for one LCD write operation becomes I80LCD_TP_W6 1 I80LCD_TP_RO OxFFC7 RW mw z Number of starting cycle of LCD_CSN low in LCD read operation becomes TP_R0 I80LCD_TP_R0 1801 _ _ 1 0xFFC8 _ RW mw z Number of starting cycle of LCD_RDN low in LCD read operation becomes IBOLCD TP Het IS0LCD TP R2 0xFFC9 _ RW mw mesa Number of ending cycle of LCD RDN low in LCD read operation becomes TP_R2 I80LCD_TP_R2 1 undek I80LCD_TP_R3 OxFFCA _ RW Deep mw z mesa Number of ending cycle of LCD_CSN low in LCD read operation becomes TP_R3 IBOLCD R3 1 eager I80LCD_TP_R4 OxFFCB ew mw z mesa TP_R4 Number of cycles for one LCD read operation becomes I80LCD_TP_R4 1 SAMSUNG ELECTRON
88. 0 17 180 LCD INTERFACE 17 3 OPERATION TP_W6 LCD_RS Register Select LCD_CSN LCD_WRN Internal_ LCD DO OEN Internal LCD DO 17 0 LCD D 17 0 I from LCD RS to LCD low 1 TP_W1 from LCD_RS to LCD_WRN low 2 TP_W2 from LCD_RS to LCD_DO start 3 TP_W3 from LCD RS to LCD_WRN high 1 5 TP_W4 from LCD_RS to end 1 6 TP_W5 from LCD RS to LCD CSN high 1 7 Single Write Operation Cycles 1 8 Figure 17 1 I80LCD single write timing parameters SAMSUNG ELECTRONICS 227 Lu S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE TP_R4 LCD_RS Register Select LCD_CSN LCD_RDN LCD D 17 0 Internal Data Capture Registers TP from LCD RS to LCD CSN low 1 TP R1 LCD RS to LCD RDN low 2 TP_R2 from LCD RS to LCD high 1 5 TP R3 LCD RS to LCD CSN high 1 7 TP_R4 Single Read Operation Cycles 1 8 Figure 17 2 I80LCD single read timing parameters SAMSUNG ELECTRONICS 228 Lu S3Fl1BG_USER S MANUAL_REV1 00 LCD_CSN LCD_WRN Internal_ LCD DO 7 0 LCD D 7 0 LCD CSN LCD RDN LCD D 7 0 Internal _ Data Capture Registers SAMSUNG ELECTRONICS DATA 0 1 DATA 2 DATA 3 DATA 4 DATA 5 17 180 LCD Index Command write in 8 bit interface 6 bytes min 1 byte
89. 00 DISP_MEM12 P1MODO P6PUR 11111111 XXXX XXXX 0000 0000 0000 0000 T1PDRO DISP_MEM13 P1MOD1 P7MODO 0000 0001 XXXX XXXX 0000 0000 0000 0000 T1PDR1 DISP MEM14 P1PUDO P7MOD1 0000 0001 XXXX XXXX 0000 0000 0000 0000 DISP_MEM15 P1PUD1 P7PUR XXXX XXXX 0010 1000 1100 0000 SAMSUNG ELECTRONICS 33 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Table 2 5 Extended Special Function Register Map 2 Upper Address Hex gt BRAC_CTRL ENC_CTRL SFCTRL BRJPEG_BUF_PTR_L 0000 0000 0000 0000 0000 0010 XXXX XXXX BRAC_CTRL2 ENC_SAMPLE_L SFPORT BRJPEG_BUF_PTR_H 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX BRAC_INT_EN ENC SAMPLE H SFDMA CTRL BRJPEG TABLE 0000 0000 XXXX XXXX 0000 0000 XXXX XXXX BRAC INT PEND ENC RESULT SFDMA START ADRL BRJPEG TABLE PTR H 0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX BRAC START ADRL SFDMA START ADRM BRJPEG IBB PTR L XXXX XXXX XXXX XXXX XXXX XXXX BRAC START ADRM SFDMA START ADRH BRJPEG IBB PTR M XXXX XXXX XXXX XXXX XXXX XXXX BRAC START ADRH SFDMA RXBUF BRJPEG XXXX XXXX XXXX XXXX XXXX XXXX 7 BRAC SIZEL SFDMA TSIZE BRJPEG IBB XRAM PTR 0000 0000 0000 0000 XXXX XXXX BRAC SIZEM DAC CTL SFDMA X BASE L BRJPEG GET 0000 0000 0000 1100 XXXX XXXX XXXX XXXX BRAC_SIZEH DACOUT_L SFDMA_X_BASE_H BRJPEG GET BUFFER M 0000 0000 0000 0000 XXXX XXXX XXXX XXXX IBB READ PTR DACOUT H SFCTRL2 BRJPEG GET BUFFER H 0000 0000 0000 0000 0000 0000 XXXX XXXX
90. 00 _number_2 16000Hz 4Bit _number_3 16000Hz 4Bit _number_4 16000Hz 4Bit _number_5 16000Hz 481 _ number 6 16000 2 481 number 7 16000Hz 481 _ number 8 16000Hz 481 number 9 16000Hz 481 number 10 16000Hz 481 endif Const struct _Filelnfo char FileName unsigned int Fs unsigned char FileInfo O ra Psy rary 5 9 10 Pt 1127 1 14 15 16 FT 4187 19 16K 16000 4 ding_16K_mono wav 16000 4 notify 16K mono wav 16000 4 Cringin mono wav 8000 4 Cringout 8000 4 16K 16000 4 CChimes 16K mono wav 16000 4 part 16 16000 4 Chinese part 16 monoO 3 wav 16000 4 number 0 wav 16000 4 Cnumber 1 16000 4 2 wav 16000 4 Cnumber 16000 4 number 4 16000 4 number_5 wav 16000 4 number_6 wav 16000 4 number_7 wav 16000 4 number_8 wav 16000 4 number_9 wav 16000 4 number_10 wav 16000 4 const unsigned char FilePos SAMSUNG ELECTRONICS 102 6 BRAC CODEC S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC addrh addrm sizeh sizel 04 0x01 0x00 0x00 0x22 Ox6b Ir 0x01 0x22 0x6c
91. 000 00000000 0000 0000 0111 0000 0000 0000 0000 0000 0000 0000 0001 0000 00000000 00000001 00000000 0000 0001 1001 0000 0000 0000 0000 0111 1000 10011111 00000100 00000000 xxxx xxxx 0000 0000 0000 0000 0000 0001 00000000 00000000 xxxx 0000 0000 DPSEL IE2 USBFN_H ADREFCMP 0000 0000 0000 0000 0000 0000 00000000 00000000 xxxx 11111111 P2 E3 P3 UERSTAT 0000 0000 UINTCON 0000 0000 UBAUD 0010 0000 URXBUF XXXX XXXX UTXBUF XXXX XXXX USBEP0CSR0 USBEP4CSRO USBEP2FIFO 0000 0000 0010 0000 0000 0001 0000 0001 XXXX XXXX P5 P6 RSTCON P7 USBEP4CSR1 USBEP3FIFO P8 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 XXXX xxxx 0000 0000 RSTSTAT USBPE0CSR1 USBEP4CSR2 USBEP4FIFO 0000 0000 0000 0001 0000 0000 0000 0000 XXXX XXXX SYSCFG USBEP1CSR0 USBEP4CSR3 USBEPLNUM1 0000 0000 0000 0000 0000 0001 0000 0000 0010 0001 IVCON0 USBEP1CSR1 USBEPOWC USBEPLNUM2 0001 0011 0000 0100 0000 0000 0100 0011 IVCON1 USBEP1CSR2 USBEP1WC1 UusBNAKCON1 WDTCON 0000 0000 0000 0000 0000 0000 0000 0000 0000 0011 WKUPSTAT USBEP1CSR3 USBEP1WC2 USBNAKCON2 WONTCLK SPICK 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 0000 0000 PLLCONO USBEP2CSRO USBEP2WC1 USBNAKEN WDTONT SPIDATAO 0000 1010 0000 0001 0000 0000 0000 0000 XXXX XXXX XXXX XXXX PLLCON 1 USBEP2CSR1 USBEP2WC2 USBCONF WDTREF SPIDATA1 1010 0000 0000 0100 0000 0000 0000 0000
92. 0000 Sector 256 512B 0x1_FE00 Sector 255 512B 0x1_0000 Sector 128 512B 0x0_FE00 Sector 127 512B 0x0_FC00 Sector 126 512B 0x0_0200 Sector 001 512B 0x0_0000 Sector 000 512B Figure 20 1 Sector Mapping within the 5 embedded flash SAMSUNG ELECTRONICS 277 er S3Fl1BG_USER S MANUAL_REV1 00 20 EMBEDDED FLASH CONTROLLER 20 2 FEATURES S3FI1BG consists of one 3072Kbits 384Kbytes e FLASH embedded NOR Flash Main feature is as follows e Auto Timing Generation for internal flash programming erase e Small Sector Erase Capability Uniform 512 Byte sectors Total 768 sectors e Fast Chip Sector Erase Sector Erase Time 8 0ms typ Chip Erase Time 50 01 typ Not supported CPU Word Program Time 2515 typ 20 3 OPERATION Embedded Flash Controller is simple to use Here is sector erase program example C code sector function erases one sector and sector program function write 512bytes to a sector The argument sec num is sector number from 0 to 767 And buf is 512 bytes array pointer Corresponding FCON WP register bit should be set before sector erase program define F PROGRAM 2 define F SECTOR ERASE 0 void sector erase int sec num FCON CTRL F SECTOR ERASE FCON ADDR H unsigned char sec gt gt 8 amp Oxff FCON ADDR M unsigned char sec num amp Oxff FCON ADDR L 0x00 Any v
93. 1 when a SPI transfer is in progress Master or SPI BUSY 7 Slave mode 0 SPI idle 1 SPI Busy 1 Byte or 2 Byte selection SPI 2BYTE LEIDEN 0 1 Byte 8 bit operation mode 1 2 Byte operation mode SPI CKSEL RAN SAMSUNG ELECTRONICS 148 S3Fl1BG_USER S MANUAL_REV1 00 9 SPI 0111 CntValue 50 BaudRate 240 Kbps 1000 CntValue 25 BaudRate 480 Kbps 1001 CntValue 12 BaudRate 1 Mbps 1010 CntValue 10 BaudRate 1 2 Mbps 1011 CntValue 5 BaudRate 2 4 Mbps 1100 CntValue 4 BaudRate 3 Mbps SPIDATAO SPI Transmit and Receive Data 0 This register is used transmit and receive SPI data Writing data to SPIDATAO places the data into transmit buffer and shift register and SPIDATAO 70 RW initiates starts a transfer when in Master Mode A read of SPIDATA0 returns the contents of the receive buffer When in Master mode Receive operation can only be possible to write any data i e any dummy data into this register even if Receive operation is only required SPIDATA1 0xFF s SPI Transmit and Receive Data 1 This register is used transmit and receive SPI data in Double Byte Mode SPIDATA1 70 RW which Two Byte bit of SPICK register is set In Double Byte Mode this register should be set before the SPIDATAO is transmitted A read of SPIDATAt returns the contents of the receive buffer SAMSUNG ELECTRONICS
94. 149 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI Programming Tip Transmit and receive setup example procedure with a description of each step is shown below Setup Procedure Description void SPI setup rCLK ENO 0x08 1 Enable SPI operation clock rP5MOD1 OxFF 2 Set P5MOD1 register for operation Using GP8 rP8MOD1 0xFF rlEO 0x20 3 Enable SPI interrupt rGIE 0x80 4 Enable Global interrupt rSPICK 0x4C 5 Set SPICK register to select the baud rate 3Mbps Set 2 Byte operation mode rSPIMOD 0x42 6 SPIMOD 6 1 Enable SCSN signal SPI SCKPHA 0 SPI SCKPOL 0 SPIMOD 3 0 Master Mode In this case SCLK pin is operation as output SPIMOD 2 0 MSB first SPIMOD 1 1 Receive Transmit mode THHHHHE Atthis time slave device should be enabled before master device is enabled rSPIMOD 0x1 SPIMOD 0 1 Enable SPI operation rSPIDATA1 7 Write the second transmit data to rSPIDATA1 rSPIDATAO 0x75 8 Write the transmit data to rSPIDATAO Then an internal baud rate clock is generated to start transmit receive After transmit receive have been finished SPI interrupt INTSPI is generated in 1 byte operation mode SAMSUNG ELECTRONICS 150 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART UART 10 1 OVERVIEW Universal Asynchronous Receiver and Transmitter UART of the S3FI1BG provide one asynchronous serial I O ports The UART can support bit rates up to 115K
95. 16 16 2 Sau 217 16 3 ee Ae 218 16 4 Register Descriptio eite rent evene edd de 219 LCD 226 dE ealill68 ionem o SA asss 226 17 2 226 17 8 227 12 4 DESPIOI ER 235 LCD Driver Controller 241 uu 241 18 2 emi 241 18 3 Pin EE 241 18 4 Block Diagram uuu Ems 242 SAMSUNG ELECTRONICS qo 18 6 Register Descriptio sicions 253 19 General Purpose I O GPIO 255 TO AC QVGIVIOW ayka 255 T9 2 Features asa ans eared 255 19 3 Block Diagram Der ce eats 256 19 4 PORT GOntiguratio i a n aaa ead 257 19 5 Register BI Re 260 20 Embedded Flash Controller
96. 1b Otherwise In case there is one packet in FIFO USBEPnCSR2 1 0 is 01b it means the byte count number of data in FIFO due to be unloaded by the CPU SAMSUNG ELECTRONICS 203 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER USBEP1WC2 0xCD USBEP2WC2 0xCF When OORDY USBEPnCSR2 register is set for OUT endpoints this register maintains the byte count number of data in FIFO due to be unloaded by the CPU Name sr cru uss 7 ea The byte count number of data second saved in FIFO due to be secondly unloaded by the CPU when there are two packets of MAXP WRTONTE lt 1 2 FIFO size USBEPnCSR2 1 0 is 11b In case USBEPnCSR2 1 0 is 00b or 01b 0x00 is displayed on this fields USBEP3WC1 0xD1 USBEP4WC1 0xD3 When OORDY in USBEPnCSR2 register is set for OUT endpoints this register maintains the byte count number of data in FIFO due to be unloaded by the CPU Name en oru fuss no zs new The byte count number of data first saved in FIFO due to be firstly unloaded by the CPU when there are two packets of MAXP lt 1 2 WRTCNT1 4 0 W FIFO size USBEPnCSR2 1 0 is 11b Otherwise In case there is one packet in FIFO USBEPnCSR2 1 0 is 01b it means the byte count number of data in FIFO due to be unloaded by the CPU USBEP3WC2 0xD2 USBEP4WC2 0xD4 When OORDY USBEPnCSR2 register is set for OUT endpoints this register
97. 30 31 decimal 01 ALMDATE 5 0 RW 31 5 4 bit is from 0 to 3 3 0 bit is from 0 to 9 SAMSUNG ELECTRONICS 215 er S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA VDMA The S3FI1BG has VDMA for 2 dimensional data movement 16 1 FEATURES e Two dimensional DMA engine with on the fly additional functions Color space conversion from YCbCr to RGB Mixing foreground and background images Alpha blending supporting 4444 and 5551 formats Local I80LCD channel to read write RGB data to from external frame memory SAMSUNG ELECTRONICS 216 er S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA 16 2 BLOCK DIAGRAM Foreground Frame uS YCbCr to XRAM RGB888 IB0OLCD 3 RGB888 2 level overwrite or transparent Serial cC Flash P RGB332 2 level overwrite with VDMA RGB or transparent RGBA5551 RGBA4444 1 eFlash RGB565 i 16 level alpha blending VDMA RGB Destination Frame m XRAM Background Frame YCbCr to RGB888 or xRam gt 888 RGB565or RGB332 IB0LCD RGB888 RGBA5551 eFlash RGB565 Serial Flash RGB332 RGBA5551 VDMA Control RGBA4444 Status RGBO black Regist 99893 VDMA RGB Figure 16 1 VDMA Block Diagram SAMSUNG ELECTRONICS 217 er S3FI1BG_USER S MANUAL_REV1 00 16 VDMA 16 3 OPERATION Foreground Frame FG V
98. 5 3 0 4 7 0 GP6 3 0 VLCDI 3 0 LCD bias circuit pin NOTE If any PINs of COM 3 0 SEG 31 0 VLCD 3 0 are not used Not Used PINs must be set as GPIO ports using GPnn Mode Control Registers PRMODn SAMSUNG ELECTRONICS 241 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 18 4 BLOCK DIAGRAM 4 mo Vicp0 Vicp3 4 LCD Controller Driver o 32 7 o SEQ0 SEG31 5 S 8 5 E Figure 18 1 LCD Controller Top Block Diagram LCD Display Memory Registers Segment Driver DATA BUS NU WCNTCLK Timing Controller Control Logic Contrast Controller COM Driver Generator SAMSUNG ELECTRONICS _1 from WDT block 242 LCD Voltage Figure 18 2 LCD Controller Block Diagram S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 18 5 OPERATION Bit settings in the LCD control register LCKSEL determine the LCD frame frequency source clock from WDT block duty and bias and the segment pins used for display output When a external sub oscillator ESCLK WDTCON S 1 is selected the LCD display will be enabled even during stop and idle mode The LCD control register LCON turns the LCD display on and off LCD data stored in the display RAM locations are transferred
99. 6 Bytes Control Status Endpoint EP1 2 64 Bytes Data Endpoint IN OUT supporting automatic double buffering 4 16 Bytes Data Endpoint IN OUT supporting automatic double buffering Supports Bulk Data Transfer CRC16 Generation and CRC5 CRC16 Checking Suspend Resume Control On Chip USB Transceiver e Timers with Pulse Width Modulation PWM 3 channels 16 bit Programmable Timers Interval Mode Toggle Mode Capture Mode PWM Mode PWM output Timer output and Capture Input Supports external clock sources SPI Full duplex 3 wire or 4 wire Synchronous Data Transfer Support Master and Slave operation Serial clock with programmable polarity and phase Baud rate clock selectable in Master mode MSB First or LSB First Data Transfer Support 1 Byte 2 Byte operation e Watchdog Timer 8 bit Timer with pre scaler f an overflow of watchdog timer is generated a reset is issued e B0LCD Interface Support parallel serial external LCD interfaces o 8 bit 9 bit 16 bit 18 bit parallel 180 interface o 3 wire 4 wire serial interface Support VDMA local bus interface LCD Controller Driver 32 segments and 4 common terminals 1 2 1 3 and 1 4 duty selectable 16level LCD contrast control by software LCD display data memory registers e Other Features 30 programmable interrupt sources 10 external interrupt sources Low power consumption e Low Voltag
100. 7 0x95 0x9c 0x78 0x82 0x00 0x78 0x82 0 9 0x98 0x95 0x57 Oxea Oxb8 OxOc Oxe7 0x00 0x18 OxOf 0x13 0x47 Oxa8 0x65 0x64 0x87 Ox7d Oxff 0x87 Ox7d 0x64 0x67 0xa8 0x15 0x47 OxOf Oxf3 0x18 0x00 0x00 0xe7 0xf0 Oxec Oxb8 0x57 0x95 Ox9c 0x78 0x82 0x00 0x78 0x82 0 9 0x98 0x95 0x57 Oxea 0xb8 Oxf0 OxOc Oxe7 0x00 0xf0 0x18 OxOf 0x13 0x47 Oxa8 0x65 0x6a 0x64 0x87 Ox7d Oxff 0x87 Ox7d 0x64 0x67 Oxa8 0x15 0x47 OxOf Oxf3 0x18 0x00 0x00 Oxe7 0xf0 Oxec Oxb8 0x57 0x95 0x9c 0x78 0x82 0x00 0x78 0x82 0 9 0x98 0x95 0x57 0xb8 0xf0 OxOc 7 rBRAC_SIZEM 0 rBRAC_SIZEL 0 2 should be size 1 START ADRH 0 rBRAC START ADRM UCHAR UINT BracDirectPcm_Sine amp Oxff00 gt gt 8 START ADRL UCHAR UINT BracDirectPcm_Sine amp Oxff rBRAC CTRL z 0x87 The PCM output is very simple The size and the address of PCM sample is set first and BRAC_CTRL is set as 0x87 The PCM data can be stored in any position of memory This means the data can be located in the area of program memory or data memory Above example shows the data is stored in program memory as the variable type of const char SAMSUNG ELECTRONICS 108 em S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC The format of PCM sample is 12 bit and all the da
101. A D conversion process requires 4 steps 4 clock edges to convert each bit and 10 clocks to set up A D conversion Therefore total of 50 clocks are required to complete a 10 bit conversion When the frequency is 24MHz and the pre scale value 1 total 10 bit conversion time is given A D Conversion frequency 24MHz 8 3MHz 4 clocks bit 10bits setup time 50 clocks 50 clocks 333ns 20 us Normal Mode Performing AD Conversion according to STC bit enable of ADCONO register When ADRDY bit is 1 and STC bit set to 1 the AD Conversion will be started And then the AD Conversion is completed STC is automatically cleared If users want to AD Conversion again user should set STC bit to 1 If ADINTEN bit in ADCONO register is 1 the interrupt will be generated whenever the AD Conversion is completed About 20us 333ns ADCKSEL 001 FSYS 24MHz ADCK 2 49 50 ADCEN STC in ADCONO _ STC to ADC EOC from ADC EOC in ADATO ADC interrupt Figure 13 2 Operation of A D Conversion SAMSUNG ELECTRONICS 181 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER Infinite Mode When ADRDY bit is 1 and STC bit set to 1 the AD Conversion will be started And then the AD Conversion operation is executed continuously until clearing STC bit to 0 by software To finish the A
102. ADC is performed constantly in the same cycle of ADIN and ADCK and Interrupt can be occurred on every ADC cycle when ADINTEN was set to 1 Compare mode While ADCEN 1 by STC enable ADC is performed constantly in same cycle of ADIN and ADCK and then interrupt can be occurred if ADAT 9 2 ADREF 7 0 Recording mode During ADCEN 1 Performing AD conversion only once according to each recording request In this time STC bit should be zero because it will be automatically enabled and then disabled ADMOD 0 Disable ADC interrupt 1 Enable ADC interrupt ADINTEN 1 R W This bit in conjunction with IEADC in the register enables ADC interrupts 0 Disable ADC operation 1 Enable ADC operation w This bit should not written during AD conversion SAMSUNG ELECTRONICS 184 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER ADCON1 0xE2 a tan ADC source clock selector ADCK Internal ADC supports maximum 50 KSPS at 3 MHz 111 Fsys 29 24MHz 512 46 875 KHz Fsys 24MHz 110 ADCK 28 24MHz 256 93 75 KHz 101 ADCK Fsys 27 24MHz 128 187 5 KHz ADCKSEL R W 111 100 26 24 2 64 375 KHz Fsvs 25 24MHz 32 750 KHz Feyg 24 24MHz 16 1 5 MHz 001 ADCK 23 24MHz 8 MHz 000 Reserved should not to this value RSVD 3 R Reevd esses Reserved ADC
103. CLK cycles from LCD_RS to LCD_CSN low in LCD write operation becomes 801 TP WO OxFFC1 Number of HCLK cycles from LCD RS to LCD low in LCD write operation becomes IBOLCD W1 Number of HCLK cycles from LCD RS to LCD D valid output in LCD write operation becomes IBOLCD TP W2 OxFFC3 RW Number of HCLK cycles from LCD RS to LCD CSN high in LCD write operation becomes 180 TP 5 1 Number of HCLK cycles for single LCD write operation becomes 2 ides IBOLCD W6 1 236 236 236 36 Number of HCLK cycles from LCD RS to LCD high 1 in 2 LCD write operation becomes IBOLCD TP 1 Number of HCLK cycles from LCD RS to LCD D high 236 impedance 1 in LCD write operation becomes IBOLCD W4 1 wor masis r sl Emas UG Em OxFFDO Configuration byte 0 2 2 2 2 236 37 237 237 37 37 37 38 N S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION osro Rw Gwmwawntge 1 238 239 239 239 239 239 239 240 240 240 40 R W i i W W I80LCD_CMD OxFFD8 R W Command I80LCD_IE OxFFD9 Interrupt enable B AN Interrupt clear R W IBOLCD ICLR OxFFDA R VDMA Control Registers VDMA CFG 0 OxFFEO R Configuration byte 0 221 VDMA 1 OxFFE1 R Configuration byte 1 221 VDMA H LEN OxFFE2 Horizontal length 1 for the background and dest
104. D Conversion is completed ADCEN bit or STC bit clear to 0 If ADINTEN bit in ADCONO register is 1 the interrupt will be generated whenever the AD Conversion is completed Compare Mode When ADRDY bit is 1 and STC bit set to 1 the AD Conversion will be started And then the AD Conversion operation is executed continuously until clearing STC bit to 0 To finish the AD Conversion is completed ADCEN bit or STC bit clear to 0 If ADINTEN bit in ADCONO register is 1 the interrupt will be generated whenever conversion result value in ADAT1 is the same as ADREF value according to ADREFCMP register Using this mode can check AD input voltage range Voice Recording by BRAC encoding Both ADC controller and BRAC encoder periodically generates encoded sample from PCM data which is capture from internal 10 bit ADC CPU task is only transferring encoded voice data ADREFCMPT 3 0 to internal or external storage device ADC recording mode setting and ISR flowchart is as follows ISR entrance 1 ADC Setting for recording ADC interrupt enable ADCONO 6 0 Auto Recording Mode if ADREFCMPH 0 2 BRAC encoding mode setting BRAC_CTRL2 0x02 BRAC encoding mode VOLUME ADC gain value DAC_CTRL 2 0x0 Volume Gain Writing ADREFCMPT 3 0 to eFlash or external serial Falsh 3 Setting DCO value 8KHz 16KHz etc V ADC interrupt is periodically g
105. EL 2 b01 IVCONO BLD SEL 2610 z201 257 277 257 poU 5 poe BJ ET voltage rising time 1 5 5 BN Figure 21 3 LVR Low Voltage Reset Timing SAMSUNG ELECTRONICS 288 er S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA Table 21 9 LCD Contrast Controller Electrical Characteristics TA 40 to 85 2 4 V to 4 2 V Parameter Conaitions mim Uni x ie Max Output Voltage V pp Ywa Vpp 3 3V LCNST 0 8 Table 21 10 Internal Flash ROM Electrical Characteristics TA 40 to 85 2 2 V to 4 2 V md wn m wx a Read frequency m eta Remeron Tue Los ne 1 The Programming time is the time during which 2 byte 16 bit is programmed Not allowed one byte program 2 The Chip erasing time is the time during which entire program memory is erased 3 The Sector erasing time is the time during which all 512 byte block is erased 4 The Chip erasing is available in Tool Program Mode only SAMSUNG ELECTRONICS 289 er S3Fl1BG_USER S MANUAL_REV1 00 22 MECHANICAL DATA MECHANICAL DATA 14 00 0 20 0 7 12 00 0 073 0 127 0 037
106. Enable GP40PU 0 RW 0 Pull up Disable 1 Pull up Enable SAMSUNG ELECTRONICS 271 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO P5MODO 0xFE57 Name aw 00 Input 01 Output GP53MOD 7 6 R W 10 SEG11 O 11 180D13 B 00 Input 01 Output GP52MOD 5 4 RW 10 SEG10 O 11 180D12 B 00 Input 01 Output GP51MOD 32 RW 10 SEG9 11 180D11 B 00 Input 01 Output GP50MOD 1 0 R W 10 SEG8 11 180D10 B P5MOD1 0xFE58 Rese 00 Input 01 Output GP57MOD 76 10 SEG23 O 11 SCSN B 00 Input 01 Output GP56MOD 5 4 R W 10 SEG22 O 11 SMOSI B 00 Input 01 Output GP55MOD 3 2 RW 10 SEG21 11 SMISO B 00 Input 01 Output GP54MOD 1 0 RW 10 SEG20 O 11 SCLK B P5PUR 0xFE59 0 Pull up Disable 1 Pull up Enable 56 6 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable o GP53PU 0 Pull up Disable 1 Pull up Enable GP52PU 0 Pull up Disable 1 Pull up Enable GP51PU 0 Pull up Disable 1 Pul up Enable GP50PU 0 RW 0 Pull up Disable 1 Pull up Enable SAMSUNG ELECTRONICS 272 er S3Fl1BG_USER S MANUAL_REV1 00 P6MODO Name 00 Input GP63MOD 7 6 R W 10 VLC3 O 00 Input GP62MOD
107. FF13 R BRAC Encoder Result Register DAC CTL OxFF18 AW DAC Control Register 118 R DACOUT 1 OxFF19 DAC Low Output Register 118 DACOUT_H OxFF1A DAC High Output Register 118 Volume Control Register in Decoding Mode 118 VOLUME OxFF1B W Auto Gain Control Register Encoding Mode DCO L OxFF1C DCO Low Register 119 DCO H OxFF1D DCO High Register 119 SAMSUNG ELECTRONICS 43 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Serial Flash Control Registers Name SF Control register For CPU mode only 124 SF Receive Transmit Buffer For CPU mode only 124 SFDMA Control Register 124 SFDMA Start Address Low 124 BRJPEG Decoder Control Registers EA mm w BRJPEG BUF L OxFF40 Low byte of XRAM buffer base address BRJPEG_BUF_PTR_H OxFF41 High byte of XRAM buffer base address 134 AN BRJPEG TABLE OxFF42 ELT of constant table base address in internal e 134 R W R W R 134 BRJPEG TABLE PTR H OxFF43 AN of constant table base address internal 134 134 BRJPEG_IBB_PTR_L OxFF44 R W Low byte of video input bit stream buffer address BRJPEG_IBB_PTR_H OxFF46 R W High byte of video input bit stream buffer address 134 BRJPEG IBB XRAM PTR 0xFF47 bit stream buffer offset address in 135 W Low byte of the get_bits peek_bits result 135 High byte of previous DC value for Y component 136 BRJPEG GET BUFFER L 0xFF48 R W Low
108. FFH The instructions that access these bits are conditional branches move set clear complement OR and AND instructions All bit accesses are by direct addressing Table 3 5 is Mnemonic and operand description of each Boolean instruction Each function and effects on PSW are also described The symbol means no effect to PSW and the symbol lt gt means can effect to PSW and the symbol 0 means force to 0 Table 3 5 Mnemonic and Operand of Boolean Instructions Mnemonit x Operation amp Functions HEX cy FO RS P ANL C bit CY CY amp bit 82 gt ANL C bit CY lt CY amp bit e CLR C CY 0 m CLR bit bit 0 2 lt CPL C CY lt ICY B3 o CPL bit bit bit B2 lt MOV C bit CY bit A2 MOV bit C bit CY 92 ORL C bit CY CY bit 72 o ORL C bit CY CY Ibit o SETB CY T D3 gt SETB bit bit lt T D2 If destination address Accumulator it is set or cleared SAMSUNG ELECTRONICS 59 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 5 SUBROUTINE CALL INSTRUCTIONS The LCALL inst
109. FSYS 211 Interval mode Start timer SAMSUNG ELECTRONICS 171 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT WDT 12 1 OVERVIEW The watchdog timer is used to prevent the system from locking up for example in infinite software loops If the software does not write to the watchdog during the programmed time then it can generate an internal reset 12 2 FEATURES e 8 bit Timer with pre scaler e f an overflow of watchdog timer is generated a reset is issued when WAKEEN is disabled or WAKE UP is issued when enabled SAMSUNG ELECTRONICS 172 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT 12 3 BLOCK DIAGRAM WCNTCLK To LCD Driver Controller Fsvs 0 WDTCON 4 Pre Scaler RESET ESCLK 1 2 WDTCON 3 WDTCLK overflow ey 65536 WDTCNT ISCLK WAKEUP WDTCONI4 WDTCON 4 compare C9 STOP mode WDT_INT WDTCON 4 WDTREF Figure 12 1 WDT Block Diagram SAMSUNG ELECTRONICS 173 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT 12 4 OPERATION Fsys WCNTCLK 0 means using Fsvs WDTREF WDT Int flag Interupt is issued WDTCON 5h Figure 12 2 WDT Timing Diagram with interrupt WCNTCLK 0 means using Fsvs 3h reset value WDTREF 80h FFh reset value wor Ces s WDT Int flag Interupt is issued WDT RESET WDTCON 7h Fi
110. G ELECTRONICS 30 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION 2 4 SFR SPECIAL FUNCTION REGISTER MAP The S3FI1BG employs dual data pointers to accelerate data program memory block moves It maintains the data pointers as DPTRO at SFR location 0x82 and 0x83 It is not necessary to modify code to use DPTRO The SSFI1BG adds a second data pointer DPTR1 at SFR location 0x84 and 0x85 The DPTR select bit in the bit 0 of DPSEL selects the active pointers When DPSEL O instruction data that use the DPTR will use DPOL and DPOH When DPSEL 1 instruction data that use the will use and DP1H DPTR related instruction data use the currently selected data pointer To switch the active pointer toggle the DPSEL bit Using dual data pointers provides significantly increased efficiency when moving large blocks of data The special function registers SFRs control several of the features of the S3FI1BG SAMSUNG ELECTRONICS 31 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION Table 2 3 Special Function Register Map Higher Nibble Hex gt P3 P4 PSW ACC B 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SP GIE ROMB USBFA USBEP2CSR2 USBEP3WC1 ADCONO UCONO 0000 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00000
111. ICS 237 eq S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE IS0LCD CFG 0 0xFFD0 ek Rw eron Reset This bit defines two pixel packing method when I8B0LCD RGB PIXEL is high for two pixel mode 0 no packing 2 pixels in 8 bytes RO GO BO X R1 G1 B1 X 1 packing 2 pixels in 6 bytes R0 GO BO R1 G1 B1 Number of RGB pixels to read or write for each IBOLCD enable RGB N PIXEL 0 1 pixel 1 2 pixel External LCD RGB type 00 RGB332 RGB TYPE 5 4 01 RGB565 10 RGB666 11 RGB888 Internal byte mapping for external LCD interface data pins 00 use 15 0 for 16 bit interface Use 7 0 for 8 bit interface 01 use 17 2 for 16 bit interface Use 17 10 for 8 bit interface 10 use 16 9 7 0 for 16 bit interface Use 16 9 for 8 bit interface 11 use 17 10 8 1 for 16 bit interface Use 8 1 for 8 bit interface Number of external LCD parallel data pins 00 8 bits 01 9 bits 10 16 bits 11 18 bits RGB 2PIXEL PACK I80LCD_RS output is inverted if this bit is set CPU wait enable not to use the interrupt or polling scheme CPU WAIT EN 3 RW 0 Tenable If this bit is disabled SW should check guarantee the completion of the current command before issuing the next command LINE 2 R Number of SPI lings for serial SPI type interface 0 lines 1 4 lines SPI_EN 1 External LCD interface 0 parallel 180 type 1 serial SPI type P Number of bytes
112. Input 01 Output GPOOMOD 1 0 R W 10 SEG12 11 180014 B POMOD 1 0xFE4A Besrp m Rese 00 Input 01 Output GPO7MOD 7 6 RW 10 SEG19 O 11 2 I T2OUT 00 Input 01 Output GPO6MOD 5 4 RW 10 SEG18 O 11 I TTOUT 00 Input 01 Output GPO5MOD 3 2 RW 10 SEG17 O 11 TOCAP I TOOUT O 00 Input 01 Output GPO4MOD 1 0 RW 10 SEG16 O 11 TCLK I POPUR 0xFE4B 0 Pull up Disable 1 Pull up Enable 6 0 Pull up Disable 1 Pull up Enable 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable o o GP03PU 0 Pull up Disable 1 Pull up Enable GP02PU 0 Pull up Disable 1 Pull up Enable GP01PU 0 Pull up Disable 1 Pul up Enable GPooPU 0 RW 0 Pull up Disable 1 Pull up Enable SAMSUNG ELECTRONICS 267 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO P1MODO 0xFE4C Name 00 Input 01 Output GP13MOD 76 RW 10 AINO I 11 TCLK 1 00 01 Output GP12MOD 5 4 RW 10 AIN1 11 TOCAP I TOOUT 00 ME 01 Output GP11MOD 32 R W 10 AIN2 11 I TTOUT 00 Input 01 Output GP10MOD 1 0 RW 10 AINS I 11 T2CAP I T2OUT P1MOD1 4 Name ek o 00 Input 01 Output GP16MOD 5 4 R W
113. LUSH EP_ODERR EP_OOVER EP_OFFULL EP_OORDY SAMSUNG ELECTRONICS HEH 14 USB CONTROLLER This bit is valid only when endpoint N is set to OUT The USB sets this bit when an OUT token is ended with a STALL handshake The USB issues a stall handshake to the host if it sends more than MAXP data for the OUT token 0 No operation 1 Stall handshake transmitted Out mode SenD STALL This bit is valid only when endpoint N is set to OUT The CPU writes a 1 to issue a STALL handshake to the USB The CPU clears this bit to end the STALL condition 0 No operation 1 Stall handshake transmit state Out mode Fifo FLUSH This bit is valid only when endpoint N is set to OUT The CPU writes a 1 to flush the FIFO This bit can be set only when OORDY is set The packet due to be unloaded by the CPU will be flushed 0 No operation 1 FIFO flush Out mode Data ERRor This bit is valid only when endpoint N is set to OUT ISO This bit should be sampled with OORDY When set it indicates the data packet due to be unloaded by the CPU has an error either bit stuffing or CRC If two packets are loaded into the FIFO and the second packet has an error then this bit gets set only after the first packet is unloaded This is automatically cleared when OORDY gets cleared 0 Normal operation 1 Data error ISO Out mode fifo OVER run This bit is valid only when endpoint N is set to OUT ISO This bit is set
114. N Enable external Interrupt 8 rw 0 Disable 1 Enable NOTE Must clear each pending bit before setting this register SAMSUNG ELECTRONICS 265 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO EINTPNDO 47 This bit is cleared by writing 1 to each bit Name ei w Deep Penr7eno _7 Enable extemal nterupt7 Fed oo PENTePNO e RW Enable mierrupte Peran PENTSPND 5 RW Enable nterupts Pending PENT PND _4 Rw Enable nterupt 4 Pending s RW Enable external nterupta Penang 2 Rw Enable interupt Pending PENT PND RW Enable nterupt ewmewo o Rw Enable external interuptoPendng EINTPND1 0 48 This bit is cleared by writing 1 to each bit sr mw Den no z new _ EINT9PND Enable external Interrupt 9 Pending EINT8PND RW Enable external Interrupt 8 Pending SAMSUNG ELECTRONICS 266 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 0xFE49 aw 00 Input 01 Output GP03MOD 76 RW 10 52015 11 180017 00 Input 01 Output GPO2MOD 5 4 RW 10 SEG14 O 11 180016 B 00 Input 01 Output GPO1MOD 3 2 R W 10 SEG13 O 11 180015 B 00
115. NT7 BMISO GP35 FSDAT EINT8 BMOSI GP36 FSCLK EINT9 BSCSN GP37 PnRESET PV330UT Assignment 80TQFP P 17 2 1 igure F S3Fl1BG_USER S MANUAL_REV1 00 1 3 PIN ASSIGNMENT SAMSUNG ELECTRONICS S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION 1 4 PIN DESCRIPTIONS e RESET RESET 9 Pops Gsswso Ges pump s pares Gee Pu 4 e erson oeer Puu s Few oma s Pop cea pum ems ams Pops ame s e GewescwEws ww wo we ws vs sem m e x Jo m X 1 xw mr mr Fem r m m Pro w x o vw pum 1 Tie 9 w em w m m me 06 m a vsus a Ass AS mns Gruo m Poco o La AAC woen ADC we Le Pan Ame Amr a pares pur a pares GresawsENra Pulp Gee GPioianarecarmacur Geo Pop
116. OF INC Dir Dir Dir 1 05 lt INC DPTR DPTR 1 A3 DEC A A A 1 14 o DEC Ri Ri Ri 1 16 17 DEC Rn Rn Rn 1 18 DEC Dir Dir lt Dir 1 15 DA A A Da A D4 o MUL AB AB AxB 4 0 e o DIV AB AB A B 84 0 e o 7 If destination address are Accumulator it is set or cleared SAMSUNG ELECTRONICS 57 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 3 UNCONDITIONAL BRANCH INSTRUCTIONS The Unconditional Branch instructions are three format SUMP LUMP The SJMP instruction encodes the destination address as a relative offset The instruction is 2 bytes long consisting of the opcode and the relative offset byte The jump distance is limited to a range of 128 to 127 bytes relative to the instruction following the SJMP The LJMP instruction encodes the destination address as a 16 bit constant The instruction is 3 bytes long consisting of the opcode and two address bytes The destination address can be anywhere in the 64KB code memory space The AJMP instruction encodes the destination address as an 11 bit constant The instruction is 2 bytes long consisting of the opcode which itself contains 3 of 11 address bits followed by another type containing the low 8 bits of the destin
117. ON 0x19 rSMCLKCON OxF6 rCLKCON 0x18 Using PLLCLK rSYSCFG 0 While rSYSCFG amp 0x40 rPLLCON1 0 28 lt lt 2 0x0 rPLLCONO PLL_EN While rPLLCONO amp 0x80 rPCON rPCON 4 OxBF rSMCLKCON OxFA rCLKCON 0x1D SAMSUNG ELECTRONICS 4 SYSTEM CONTROLLER enable external Sub Oscillator Fgource Fsys FsouncE enable internal Sub Oscillator 1 Fgource Fgys Fgource enable internal Main Oscillator wait internal Main Oscillator stable 1 Fgource IMCLK Fsys Fgource 2 enable external Main Oscillator wait external Main Oscillator stable Fsys Fgource or Flash Access 1 wait ONE_CACHE_EN 1 Fsys Fgource 2 enable external Main Oscillator wait external Main Oscillator stable PLL output frequency 48MHz MDIV 0x28 SDIV 0 0 PLL enable wait PLL stable EF_WAIT_MODE 0 Flash Access 2 wait ONE CACHE EN 1 FsoURCE PLLCLK 2 FsoURCE 24MHz S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER 4 3 3 POWER MANAGEMENT The power management block controls system clocks by software for the reduction of power consumption of the S3Fl1BG The S3FH BG has three power down modes Power Saving Mode State Diagram Figure 4 10 shows Power saving mode state with either Entering or Exiting condi
118. ONICS 248 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 1 2 Duty 1 2 Bias Mode The AC timing diagram of COM SEG signals under 1 2 duty 1 2 bias mode is described as below Vicp0 Vicp1 2 3 Vss Vicp0 Vicp1 2 3 Vss Vicp0 Vicp1 2 3 Vss Vicpl 2 3 Vicp0 Figure 18 6 COM SEG Signal in 1 2 Duty and 1 2 Bias Mode SAMSUNG ELECTRONICS 249 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 1 3 Duty 1 2 Bias Mode The AC timing diagram of COM SEG signals under 1 3 duty 1 2 bias mode is described as below Vicp0 Vicp1 2 3 Vss Vicp0 Vicp1 2 3 Vss Vicp1 2 3 VicpO Figure 18 7 COM SEG Signal in 1 3 Duty and 1 2 Bias Mode SAMSUNG ELECTRONICS 250 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 1 3 Duty 1 3 Bias Mode The AC timing diagram of COM SEG signals under 1 3 duty 1 3 bias mode is described as below Figure 18 8 COM SEG Signal in 1 3 Duty and 1 3 Bias Mode SAMSUNG ELECTRONICS 251 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER 1 4 Duty 1 3 Bias Mode The AC timing diagram of COM SEG signals under 1 4 duty 1 3 bias mode is described as below
119. OxFF10 R BRAC Encoder Status Regier ori BRAC Encoder Register Unde Volume Control Register in Decoding Mode OxFF SAMSUNG ELECTRONICS 113 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC BRAC_CTRL 1 Enable DMA operation This bit must set to 1 for audio playing 1 Silence Start size with BRAC_SIZEx This bit generates interrupt when operation is completed 1 Bring the Output DAC level to VOmax 2 from zero This bit generates interrupt when operation is completed 1 Bring the Output DAC level to zero from VOmax 2 This bit generates interrupt when operation is completed 0 Enable 4bit BRAC Decoding 1 Enable 3bit BRAC Decoding DIR_PCM EN R W 1 Enable Direct PCM output 1 Start the BRAC Decoding This bit generates interrupt when operation is completed BRAC_EN R W SIL_EN GO_MID GO_BOT and BRAC_EN bits should be asserted exclusively Only one bit should be asserted at one time BRAC CTRL2 0xFF01 Name RW O XRAM IBB Enable bit XRAM IBB EN 7 1 raw data is from XRAM pointed by START ADR 0 BRAC raw data is from internal Flash or serial Flash R W R RW BRAC Encoding Mode Enable 0 BRAC decoding 1 BRAC encoding ENC_MODE 1 R W BRAC encoding is initialized when 1 is written to this bit This bit should be set whenever BRAC encoding starts This bit dete
120. PEG PREV DC Y L 0xFF50 BRJPEG_PREV_DC_Y_H 0xFF51 BRJPEG PREV DOC Y 12 0 register keeps the previous DC value for Y component neme __ Besrpion PREV DC Y L Bits 7 0 of previous DC value for Y component Name Deseo Reset RSVD 8 Rewd PREV DC Y H Bits 12 8 of previous DC value for Y component BRJPEG PREV DC 0xFF52 PREV DC 0xFF53 BRJPEG PREV DC CB 12 0 register keeps the previous DC value for Cb component Name Bespion PREV DC L Bits 7 0 of previous DC value for Cb component Name __ RW Besplon PREV DC CB H Bits 12 8 of previous DC value for Cb component BRJPEG PREV DC 0xFF54 PREV DC CR 0xFF55 BRJPEG PREV DC CR 12 0 register keeps the previous DC value for Cr component Nm Deep PREV_DC_CR_L Bits 7 0 of previous DC value for Cr component Bmw SAMSUNG ELECTRONICS 136 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER mw ew PREV_DC_CR_H Bits 12 8 of previous DC value for Cr component BRJPEG_CFG 0xFF56 Wane en Rw spt sv ____ 6 SOS Memory type of IBB 00 Internal eFlash IBB_TYPE 4 3 R W 01 External serial flash 10 XRAM 11 Reserved z RW DC prediction mode in quantized DC coefficients 1 R
121. RATOR The leap year generator can determine the last date of each month out of 28 29 30 or 31 based on data from BCDDATE BCDMON BCDYEARL and BCDYEARH This block considers leap year in deciding the last date A 16 bit counter can just represent four BCD digits so it can decide whether any year is a leap year or not READ WRITE BCD REGISTERS Bit 0 BCDMOD of the register must be set high in order to write the BCD register in RTC block When BCDMOD 0 or START 1 the CPU can t write a data into BCD registers The CPU must be clear BCDMOD bit after writing data into BCD registers If not BCD registers do not run even though START bit is set to 1 An one second error when the CPU reads data from BCD counters and this cause the change of the higher time units When the CPU reads data from the BCD counters another time unit may be changed if BCDSEC register is overflowed The reading sequence of the BCD counters is BCDYEARH L BCDMON BCDDATE BCDHOUR BCDMIN and BCDSEC is required to read it again from BCDYEARH to BCDSEC if BCDSEC is zero ALARM function The RTC generation alarm signal at specified time in the STOP mode or normal mode In normal mode the alarm interrupt is activated and in the STOP mode wake up signal is activated The RTC alarm register RTCALM determines the alarm enable and the condition of the alarm time setting SAMSUNG ELECTRONICS 209 er S3Fl1BG_USER S MANUAL_REV1 00 15 RTC RTCALM ALARM Inter
122. S3FI1BG 8 bit CMOS Microcontroller Revision 1 00 Aug 2010 User s Manual SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All informa tion discussed herein is provided on an AS IS basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics No license of any patent copyright mask work trademark or any other intellectual property right is granted by one party to the other party under this document by implication estoppel or otherwise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates or additional information about Samsung products contact your nearest Samsung office All brand names trademarks and registered trademarks belong to their respective owners 2010 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS Um Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no resp
123. SAMSUNG ELECTRONICS 115 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC BRAC_SIZEL 7 BRAC_SIZEM 0xFF08 BRAC SIZEH 9 BRAC_SIZE 23 0 registers is automatically decreasing by 1 after starting BRAC decoding Name eu Rnw Besrpio size to read from e FLASH external Serial FLASH This is SEL concatenated with SIZEH and SIZEM Bespio size to read from e FLASH external Serial FLASH This is concatenated with SIZEH and 5261 Name Bi Rw Data size to be read from e FLASH or external Serial FLASH This is concatenated with SIZEM and SIZEL IBB_READ_PTR 0xFF0A mam ew aw Beso BRAC DMA read pointer CPU should observe this register before CPU writes BRAC data to IBB area not to overwrite BRAC data RD PTR 7 0 If the half of IBB is consumed interrupt is generated BRAC CMD ADDR Command address for BRAC Decoding Encoding Nome Den BRAC DATA Command value for BRAC9 Decoding Encoding SAMSUNG ELECTRONICS 116 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC BRAC BUFF 0xFFOD Name ee Rw Deep Reset Buffer for BRAC Decoding BRAC BUFF 7 0 W Voice data is stored to this buffer by CPU This buffer is used only when CPU mo
124. SBPHYPUPEN 7 NSP PHY Pull UP enable 0 disable 1 enable Controls internal flash wait mode Flash read wait count is determined by SMCLKCON FLASH_WAIT_CNT But when this bit is set the wait count of 0x0000 OxFFFF flash area is decremented by 1 Refer to SMCLKCON FLASH WAIT ONT bits Full System Stop with Oscillator Stop mode can be released by PIN Reset LVD Reset Power on Reset External pin wake up signal USB wake up or RTC wake up 0 Disable 1 Enable 0 Disable 1 Enable 7 5 Reserved RTCRST 4 reset by software Set this bit to 1 before starting RTC This bit is automatically cleared SWRST 3 0 W If this field has B then the system will restart RSTSTAT 0xA9 Reset DN CNN WOTRST Reset oy Watchoogtmer SWRST Reset by Software PINRST EN Reset by SAMSUNG ELECTRONICS 86 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER SYSCFG 0xAA Name ____ sese Internal 16MHz Oscillator stable flag INT_MOSC_STABLE 7 0 Internal 16MHz Oscillator is unstable 1 Internal 16MHz Oscillator is stable Main Oscillator stable flag STABLE 0 Main Oscillator is unstable 1 Main Oscillator is stable Internal 16MHz Main Oscillator enable bit in STOP mode INCUMOSGEN STOP 0 disable in STOP mode 1 Enable in STOP mode External Main Oscillator enable bit i
125. SR3 1 0 is 10 1 packet in FIFO 11 2 packets of lt 1 2 FIFO or 1 packet of gt FIFO size 0 No data packet in FIFO 1 there is at least one packet of data in FIFO In mode IN packet ReaDY This bit is valid only when endpoint N is set to IN The CPU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so 5 the CPU load the next packet While this bit is set CPU will not be able to write to the FIFO If the SEND STALL bit is set by the CPU this bit cannot be set 0 Not ready for IN operation 1 Ready for IN operation USBEP0WC 0xCB When ORDY in USBEP0CSR1 register is set for OUT endpoints this register maintains the byte count number of data in FIFO due to be unloaded by the CPU Name et oru juss no z new WRTCNT4 ae fon w number of data due to be unloaded by USBEP1WC1 0xCC USBEP2WC1 0xCE When OORDY in USBEPnCSR2 register is set for OUT endpoints this register maintains the byte count number of data in FIFO due to be unloaded by the CPU _ et oru Juss no 7 ew The byte count number of data first saved in FIFO due to be firstly unloaded by the CPU when there are two packets of MAXP lt 1 2 WRTONT 1 W FIFO size USBEPnCSR2 1 0 is 1
126. STATIC Figure 18 3 Voltage Dividing Internal Resistor Circuit Diagram SAMSUNG ELECTRONICS 246 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER VDD LCON 0 Contrast VDD LCON 0 Controller LONST 3 o lt 1 3 BIAS VDD LCON O Contrast Contrast lt Controller Controller 6 LCNST 3 LONST 3 gt A lt VLCD1 VLCD3 m 1 2 BIAS STATIC Figure 18 4 Voltage Dividing External Resistor Circuit Diagram SAMSUNG ELECTRONICS 247 eq S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER LCD OUTPUT SIGNAL WAVEFORM If the LCD is supplied with DC power the LCD element undergoes a chemical change causing a deterioration of the element Therefore the LCD controller has a built in AC circuit to drive the LCD with a two frame AC waveform The LCD controller supports several operation modes with different numbers of COM and different biasing levels 1 1 Duty 1 COM 1 1 Bias 1 2 Duty 2 COM 1 2 Bias 1 3 Duty 3 COM 1 2 Bias 1 3 Duty 3 COM 1 3 Bias 1 4 Duty 4 COM 1 3 Bias Static Mode The AC timing diagram of COM SEG signals under static mode is described as below COMO COMO COMO lt abis Figure 18 5 COM SEG Signal in Static Mode SAMSUNG ELECTR
127. Stall handshake transmitted In mode SenD STALL This bit is valid only when endpoint N is set to IN The CPU writes EP_ISDSTALL 1 to this bit to issue a STALL handshake to the USB The CPU clears this bit to end the STALL condition 0 No operation 1 Stall handshake transmit state In mode UNDER run This bit is valid only when endpoint N is set to IN ISO The USB sets this bit when in ISO mode an IN token is received and the IINRDY bit is not set The USB sends a zero length data packet for such conditions and the next packet that is loaded into the FIFO is flushed EP_IUNDER 0 No operation 1 Received IN token but not ready ISO In mode fifo Not EMPty EP_INEMP This bit is valid only when endpoint N is set to IN Indicate there is at least one packet of data in FIFO SAMSUNG ELECTRONICS 202 In mode Fifo FLUSH This bit is valid only when endpoint N is set to IN The CPU sets this bit if it intends to flush the IN FIFO This bit is cleared by the USB when the FIFO is flushed The CPU is interrupted when this happens If a token is in progress the USB waits until the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 0 No operation 1 FIFO flush S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER If USBEPnC
128. TAG TMS pin and user program can change this pin as normal GPIO when ICE is not connected SAMSUNG ELECTRONICS 21 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION SPI Interface 4 pins Nm SCLK SPI Clock When configured as master this pin is an output When configured as slave this pin is an input SPI master in slave out When configured as master this pin is an input When SMISO configured as slave this pin is output SPI master out slave in When configured as master this pin is an output When SMOSI configured as slave this pin is input SCSN SPI slave select When configured as master this pin is an output When configured as slave this pin is an input UART Interface 3 pins Nm io uak extemal umo 1 receve Daa moru ooo umo Transmit Serial Flash Interface 4 pins wm o oo eson ms sranane O Timer Interface 4 pins Nam TCLK External Clock Source for Timer 0 Timer 1 and Timer 2 TOCAP TOOUT 10 Timer 0 Capture input Timer 0 16 bit PWM mode output or counter match toggle output T1CAP T1OUT Timer 1 Capture input Timer 1 16 bit PWM mode output counter match toggle output T2CAP T2OUT lO Timer 2 Capture input Timer 2 16 bit PWM mode output or counter match toggle output DAC Interface 1 pins Name Pen O DACO Analog out
129. TC_CLKRST 0 No Reset 1 Reserved Reset BCD counter MODify The CPU can write a value into the BCDxxx counters when this bit ANG ROEM is set to 1 This bit should be cleared after setting any value by the CPU RTC start bit This bit controls to run the BCD counters The CPU can t modify the BCDxxx counters during running RTC STARTB RTC_STARTB 0 0 RTC running 1 RTC no running RTCCON 1 0xFF81 EET Interrupt Pending PEINTPEND If the IERTCPRI in the IE2 and PEINTEN in this register is enabled and GIE is enabled an interrupt is requested when this bit is set to 1 User can clear this bit by writing 1 to this bit Periodic interrupt select 000 No Periodic interrupt generated 001 Periodic interrupt generated every 1 512 second 010 Periodic interrupt generated every 1 256 second PEINTS 011 Periodic interrupt generated every 1 64 second 100 Periodic interrupt generated every 1 16 second 101 Periodic interrupt generated every 1 4 second 110 Periodic interrupt generated every 1 2 second 111 Periodic interrupt generated every 1 second o SAMSUNG ELECTRONICS 212 ums S3Fl1BG_USER S MANUAL_REV1 00 15 RTC 0 Not generate interrupt with the period designated by the PEINTS 1 Generate interrupt with the period designated by the PEINTS BCDSEC 0xFF82 Name Bt Description 777 RTC RST Rsvo 7 R Reseed BCD v
130. TION Endpoint Architecture USB core has totally 5 endpoints one is endpoint 0 EPO and the others are endpoint 1 6 All endpoints except endpoint 0 can be double buffered in order to support best transfer speed In case of USB core without double buffering functionality if it has not finished loading data into the endpoint buffer when the next IN token arrives the CPU it sends a NAK handshake in response to the IN token This means that the host should send an IN token at a later time to receive valid data from the USB device However USB core of the S3FI1BG can load the next packet of bulk data while the previous packet is being transferred over USB This is accomplished by double buffering This function is always enabled and does not support triple or quadruple buffering Therefore in the case Endpoint 1 for maximum transfer speed you need to define 32 bytes of endpoint size in your descriptor information and configure 32 bytes of physical size by setting in USBEP1CSRO register as 0100b USBEPnCSR2 1 0 bits indicates the status of double buffering in OUT endpoint 00b means that there is no packets in double buffer 01b means that 1 packet is existed in buffers and 11b means that buffer is full USBEPnCSR3 1 0 bits indicates the status of double buffering in IN endpoint 00b means that there is no packets in buffers 10b means that 1 packet is existed in buffers and 11b means that buffers is full Logical Endpoint Fea
131. Timing Diagram CYCLE SPI CLK CPHA 0 CPOL 0 SPI CLK CPHA 0 CPOL 1 SPI CLK CPHA 1 CPOL 0 SPI CLK CPHA 1 CPOL 1 SPI MOSI SPI MISO Sampled Receive Data Master Mode Sampled Receive Data Slave Mode Figure 9 4 SPI Transfer Format SPInCS SCK SCKPOL 1 SCK SCKPOL 0 Figure 9 5 4 Wire SPI Master Timing SCKPHA 0 SAMSUNG ELECTRONICS 144 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI SPInCS SCK SCKPOL 1 SCK SCKPOL 0 Figure 9 6 4 Wire SPI Master Timing SCKPHA 1 SPInCS SCK SCKPOL 1 SCK SCKPOL 0 Figure9 7 4 Wire SPI Slave Timing SCKPHA 0 SAMSUNG ELECTRONICS 145 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI SPInCS SCK SCKPOL 1 SCK SCKPOL 0 TsckH Tso Figure 9 8 4 Wire SPI Slave Timing 1 SPI Timing Parameters Parameter ________ _________ Master Mode Timing Figure 9 5 and Figure 9 6 SCSNfalingiofrstSOKede L mae 1 27853 Jom Lg 18 Slave Mode Timing See Figure 9 7 and Figure 9 8 ms snn n ______ nos Bog SOKtowTme 7
132. V1 00 5 INTERRUPT STRUCTURE 5 3 INTERRUPT HANDLING The interrupt flags are sampled at the end of instruction cycle When an interrupt occurs only the Program Counter is automatically pushed on to the stack area not the PSW or any other registers Normal Lower Higher Level Processing Interrupt Processing by the default priority WDT Interrupt Service papas Setting Level IPWDT 0 IPSPI 0 IPWDT 1 IPSPI 1 INT Enable 5 WDT SPI Interrupt Generated simultaneoulsy SPI Interrupt Service Routine Figure 5 2 Handling Same Level of Interrupts Normal Program Higher Level Interrupt Processing Processing by the interrupt priority register SPI Interrupt INT Disable Service Routine Setting Level gt IPWDT 0 IPSPI 1 Enable WDT SPI Interrupt Generated simultaneoulsy WDT Interrupt Service Routine Figure 5 3 Handling Different Level of Interrupt Higher Level is first issued SAMSUNG ELECTRONICS 93 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE Normal Program Lower Level Interrupt Processing Processing by the default priority WDT Interrupt INT Disable gt Service Routine Setting Level y SPI Interrupt Service Routine IPWDT 0 IPSPI 1 Enable Lower priority WDT SPI Interrupt Interrupt Generated Generated Figure 5 4
133. W5 1 Number of HCLK cycles from LCD_RS to LCD_CSN high in Undef LCD read operation becomes I80LCD_TP_R3 1 Number of cycles single LCD read operation becomes Undef I80LCD_TP_R4 R4 1 NOTE These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 235 er IBOLCD CFG 1 IBOLCD DATA 0 IBOLCD DATA 1 IBOLCD DATA 2 IBOLCD DATA 3 IBOLCD DATA 4 IBOLCD DATA 5 IBOLCD S3Fl1BG_USER S MANUAL_REV1 00 17 180 LCD INTERFACE 180 0 Name RW mw z mesa Number of starting cycle of CSN low in LCD write operation becomes TP_W0 IBOLCD TP WO I80LCD_TP_W1 OxFFC1 _ mw z mesa Number of starting cycle of LCD low in LCD write operation becomes IBOLCD TP W1 wnaei I80LCD_TP_W2 0xFFC2 RW mw z fesa Number of starting cycle of D output active in LCD write operation 2 becomes 1801 W2 180 TP W3 _ RW Deep mw mesa Number of ending cycle of LCD WRN low in LCD write operation becomes IBOLCD W3 1 det I80LCD_TP_W4 0xFFC4 Name RW Deep mw z me Number of ending cycle of LCD_D output active in LCD
134. X data is sent not only RXBUF but also TX port directly so TXBUF data will not be transmitted Setting this bit causes the UART to send a break A break is defined as a SBR 2 continuous Low level signal on the transmit data output with the duration of more than one frame transmission time RMODE 0 Disable Receive mode 1 Enable Receive mode TMODE RW 0 Disable Transmit mode 1 Enable Transmit mode 0xF2 Name ee mw Deep Clock Source Selection 000 Fsys 001 EXTUCLK 010 Fsys 2 UBAUDCLK 6 4 R W 011 Foys 4 100 8 101 16 Other value Reserved Word Length 00 5bits 01 6bits 10 7bits 11 8bits RW Number of stop bits 0 One stop bit per frame 1 Two stop bit per frame 0 Normal operation mode AMEE B 1 Infrared TX RX mode n SAMSUNG ELECTRONICS 159 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART UTRSTAT 0xF3 Transmit Buffer This bit is set to 1 automatically when transmit buffer register is Empty empty regardless of shift register If THEIE bit in UINTCON THE register is 1 and this bit is 1 TX interrupt Request will be generated 0 The buffer register is not empty 1 Empty This bit is cleared automatically by writing transmit data into transmit buffer register UTXBUF Transmitter This bit is set to 1 automatically when the transmit buffer register Empty TXIDLE has no valid data to transmit a
135. alue for second bits Undef rw 6 4 bit is 0 to 5 3 0 bit is from 0 to 9 BCDMIN 0xFF83 Name Bt Fw Description RTC_RST Rsvo 7 R Reserved x BCD value for minute bits R Undef rw 6 4 bit is from 0 to 5 3 0 bit is from 0 to 9 ue BCDHOUR 0xFF84 me Rw Deseo re n rsm BCD value hour bits i Undef 5 4 bit is from 0 to 2 3 0 bit is from 0 to 9 BCDDATE 0xFF85 BCD value for bits From 0 to 28 29 30 31 decimal 01 31 BCDDATE m u 5 4 bit is from 0 to 3 3 0 bit is from 0 to 9 BCDDAY 0xFF86 Rw BCD value for day of a week bits 2 0 bit is from 0 10 6 BGDDAY oe 000 Sunday 001 Monday 010 Tuesday 011 Wednesday 100 Thursday 101 Friday 110 Saturday SAMSUNG ELECTRONICS 213 LN S3Fl1BG_USER S MANUAL_REV1 00 15 RTC BCDMON 0xFF87 BCD value for month bits 4 bit is from 0 to 1 3 0 bit is from 0 to 9 Undef Description RTC_RST BCDYEARL 7 0 BCD value for lower of year bits From 0 to 99 BCDYEARH 0xFF89 Description RTC_RST BCDYEARH 7 0 BCD value for upper of year bits From 0 to 99 RTCALM 0xFF8A Alarm Wake up Pending from STOP mode If the IERTCALM in the IE2 is enabled and GIE is enabled a WKUP_PEND R W wakeu
136. alue is O K This can be skipped FCON WDATA H EN 0x1 Any value is Start to erase while FCON STAT Wait until sector erase is done void sector_program int sec_num unsigned char buf int addr FCON_CTRL F_PROGRAM FCON_ADDR_H unsigned char sec_num gt gt 8 amp Oxff FCON ADDR M unsigned char sec num amp Oxff FCON ADDR L 0x00 Program from 0x00 Other value except 0 can be used for addr 0 addr lt 51 2 addr 2 FCON_WDATA_L buf addr FCON_WDATA_H_EN buf addr 1 Start to program Flash Address is automatically incremented after programming while FCON_STAT Wait until sector erase is done SAMSUNG ELECTRONICS 278 er S3Fl1BG_USER S MANUAL_REV1 00 20 EMBEDDED FLASH CONTROLLER 20 4 REGISTER DESCRIPTION SUMMARY w Reset Foon srar m sausros foo FCON WDATA L 5 Write Data Low FCON WDATA 0xFFA6 Write Data High and Write Enable Register RSvD 7 R Reserved 0x00 FCON_WP_L OxFFA8 Program Sector_Erase Protect Low Register OxFF FCON WP H 9 Program Sector_Erase Protect High Register OxOF These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 279 er S3Fl1BG_USER S MANUAL_REV1 00 20 EMBEDDED FLASH CONTROLLER FCON CTRL Wane ee RW sw ra Red nm a reset AW o 1 Program 0 Sector
137. ash from this base address pointer This address pointer should be assigned less than OxFA60 to access 1440 byte constant tables within 16 bit address domain B Besmpion TABLE PTR L Bits 7 0 of constant table base address in internal eFlash __ TABLE PTR H Bits 15 8 of constant table base address in internal eFlash BRJPEG IBB 1 0xFF44 BRJPEG IBB M 45 BRJPEG IBB 0xFF46 BRJPEG IBB PTR 23 0 register is the video input bit stream buffer IBB pointer For the internal eFlash IBB and serial flash IBB this register is incremented according to the bit stream parsing by VLD engine But for the XRAM IBB this register is the base address register and the BRJPEG IBB XRAM PTR 6 0 is the offset register and incremented mi IBB PTR L Bits 7 0 of video input bit stream buffer Nm s ew IBB PTR M Bits 15 8 of video input bit stream buffer IBB_PTR_H Bits 23 16 of video input bit stream buffer SAMSUNG ELECTRONICS 134 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER BRJPEG_IBB_XRAM_PTR 0xFF47 BRJPEG IBB XRAM PTR 6 0 register is the video input bit stream buffer offset address pointer in XRAM IBB mode BRJPEG IBB PTR 11 0 BRJPEG IBB XRAM PTR 6 0 is the XRAM IBB address Only BRJPEG IBB XRAM PTR is incremented and wrappe
138. ata Transfer e CRC16 Generation and CRC5 CRC16 Checking e Suspend Resume Control e On Chip USB Transceiver Table 14 1 Summary of Endpoint scription 16 Bytes FIFO Endpoint 0 Does not support double buffering Bidirectional endpoint for control transfer 64 Bytes FIFO Configurable FIFO size Supports double buffering E 1 2 IN OUT configurable Bulk Interrupt Isochronous Support logical endpoint feature 16 Bytes FIFO Configurable FIFO size Supports double buffering E 4 IN OUT configurable Bulk Interrupt Isochronous Support logical endpoint feature SAMSUNG ELECTRONICS 189 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER 14 3 PIN DESCRIPTION Table 14 2 USB PIN Description ___ __ for USB device 14 4 BLOCK DIAGRAM Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO 4 Internal BUS Endpoint 3 FIFO 4 0 TRANSCEIVER Endpoint 4 FIFO SUSPEND OENB General Function Interface Register Figure 14 1 USB Device Block Diagram SAMSUNG ELECTRONICS 190 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER PULLUP_EN 3 RXDP Figure 14 2 USB Transceiver Block Diagram PULLUP EN USBPHYUPEN bit of PCON register in System Controller SAMSUNG ELECTRONICS 191 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER 14 5 OPERA
139. ation address Hence the destination has to be within the same 2KB block as the instruction following the AJMP The JMP A DPTR instruction supports case jumps The destination address is computed at execution time as the sum of the 16 bit DPTR register and the Accumulator Typically DPTR is set up with address of a jump table and the Accumulator is given an index to the table Table 3 4 is Mnemonic and operand description of unconditional branch instruction Each function and effects on PSW are also described As shown in the table any instruction related subroutine call can not effects on PSW Table 3 4 Mnemonic and Operand of Unconditional Branch Instructions Opcode PSW Mnemonic amp Operand Operation amp Functions HEX FO RS OV AJMP 11 PC100 lt addrll 01 21 41 61 81 A1 C1 E1 JMP DPTR 73 SJMP lt 80 LJMP addr16 PG lt addrl16 02 NOP No operation 00 SAMSUNG ELECTRONICS 58 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 4 BOOLEAN INSTRUCTIONS The Boolean Instructions are single bit processing functions The I RAM 20H contains 128 addressable bits OOH 7FH and the SFR space address ends in 000b that OH or 8H can support up to 128 other addressable bits 80H
140. ble with the standard 8051 instruction set The difference between the SSFI1BG and the standard 8051 is the number of cycles required to execute an instruction 10MHz The execution time of NOP is 50ns Detailed Data Transfer Instruction Summary this case destination is internal flash area Maximum Clock Cycles Data Transfer Instruction Bytes Standard 8051 S3FI1BG MOV A imm 2 12 2 MOV A Ri 1 12 2 MOV A Rn 1 12 1 MOV A Dir 2 12 2 MOV Ri A 1 12 2 MOV Ri imm 2 12 2 MOV Chi Dir 2 24 3 MOV Rn A 1 12 1 MOV Rn Dir 2 24 3 MOV Rn imm 2 12 2 MOV Dir A 2 12 2 MOV Dir imm 3 24 3 MOV Dir Ri 2 24 3 MOV Dir Rn 2 24 2 MOV Dirt Dir2 3 24 3 MOV DPTR imm16 3 24 3 A DPTR 1 24 4 1 24 4 DPTR 1 24 3 MOVX Ri 1 24 3 MOVX DPTR 1 24 3 4 MOVX Ri A 1 24 3 4 XCH A Ri 1 12 3 XCH A Rn 1 12 2 XCH A Dir 2 12 3 XCHD A Ri 1 12 3 PUSH Dir 2 24 3 POP Dir 2 24 2 SAMSUNG ELECTRONICS 65 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET Detailed Arithmetic Instruction Summary Maximum Clock Cycles Arithmetic Instruction Bytes Standard 8051 S3FH BG ADD A imm 2 12 2 ADD A ORi 1 12 2 ADD A Rn 1 12 1 ADD A Dir 2 12 2 ADDC A imm 2 12 2 ADDC
141. bps using system clock UART input and output pins are multiplexed with GPIOs The UART includes programmable baud rates infrared IR transmit receive or two stop bit insertion 5 bit 6 bit 7 bit or 8 bit data width and parity checking UART contains a baud rate generator transmitter receiver and a control unit as show in Figure 10 1 The baud rate generator can be clocked by EXTUCLK Feys 2 Fsys 4 Fsys 8 or 16 clock Transmit data is written first to transmit buffer register Holding register From there it is copied to the transmit shifter and then shifted out by the transmit data pin UTXD Received data is shifted in by the receive data pin URXD It is then copied from the shifter to the receive buffer register when one data byte has been received 10 2 FEATURES e Supports 5 bit 6 bit 7 bit or 8 bit serial data transmit receive TX RX e Supports external clocks for the UART operation e Programmable baud rate e Supports IrDA 1 0 e Loopback mode for testing e Insertion of one or two Stop bits per frame e Parity checking 10 3 PIN DESCRIPTION Table 10 1 UART PIN Description GP73 UCLK External Clock Source for UART GP15 GP74 URXD Receive Data Input for UART GP16 GP75 UTXD Transmit Data Output for UART SAMSUNG ELECTRONICS 151 er S3Fl1BG_USER S MANUAL_REV1 00 10 4 BLOCK DIAGRAM Peripheral BUS Transmitter 10 UART 4 Transmit Buffer Register UTXBUF
142. ce routine for BRAC COCOdING EE 105 6 25 Playing UT 106 6 2 6 DCO Selecting the sampling frequency for playing a 106 6 2 7 DC level shifting and Pause 107 6 2 8 Playing data u u 108 6 2 9 Reducing the total size of compressed 109 6 2 10 Volume n a 110 6 2 11 Digital Low pass filtering and 110 6 2 12 IBB Input Bit stream Buffer 111 6 3 Register 113 Serial Flash e 120 MIT 120 7 2 5 ceded 120 7 9 BlOCK Dia Gram EE 120 Z E 121 7 5 Register Description uu dett 123 BRJPEG Decoder eM 126 8 1 A E 126 8 2 M HQ 126 SEES
143. create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 446 711 Contact Us misko samsung com TEL 82 31 209 3107 FAX 82 31 209 3262 Home Page http www samsungsemi com Printed in the Republic of Korea SAMSUNG ELECTRONICS Revision History Revision No Date Description Author s 1 00 Aug 4 2010 Initial draft SAMSUNG ELECTRONICS Um Table of Contents 1 Introducll oiuu III 12 AD ah
144. cted and the file size of compression data becomes smaller than 4 bit compression And to provide the compression type the selected compression algorithm is listed in Filelnfo variables The lower sampling frequency causes the smaller compressed data But in this case the quality of voice sound can be degraded so that careful editing the wave file is required SAMSUNG ELECTRONICS 103 Lu S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 3 DECODING THE COMPRESSED VOICE DATA penienee C Programmin Index 9 9 void PlayNext int PlayAddr const Pointer variable of FilePos PlayAddr chord 16k mono 5 Let s Play chord 16K mono A Setting BRAC_CTRL2 00 fPos FilePos PlayAddr EU rBRAC_START_ADRM of BRAC Compressed Data B rBRAC_START_ADRL fPos rBRAC_SIZEM fPos Set Size of BRAC Compressed Data rBRAC SIZEL fPos dSeDCOVae rDCOL Fs 16KHz FSOURCE 12Mhz Upsampling FileInfo chord 16k mono 4 B rBRAC_CTRL 0x81 4 Bit BRAC Starts Else rBRAC_CTRL 0x89 3 Bit This sample code describes how to play a voice _chord_16K_mono To play the voice BRAC initialization is done like Sentence Index BRAC Start Address and the size like Sentence Index B DCO_VAL like Sentence Index C Depending on the compressed data BRAC Starting Command is set
145. d around 128 bytes Name s mw Ben mw o Rem Ll IBB XRAM PTR 6 0 R W Video input bit stream buffer offset address in XRAM IBB mode BRJPEG GET BUFFER 0xFF48 GET BUFFER M 0xFF49 BRJPEG GET BUFFER BRJPEG IBB PTR 23 0 register is the intermediate bit stream buffer to access more than 8bits from IBB GET BUFFER L Bits 7 0 of intermediate bit stream buffer GET BUFFER M Bits 15 8 of intermediate bit stream buffer BUFFER H Bits 23 16 of intermediate bit stream buffer BRJPEG_BITS_LEFT OxFF4B Name en Rew rs resen O y yO BRJPEG_GET_PEEK_L 0xFF4C BRJPEG_GET_PEEK_H 0xFF4D BRJPEG_GET_PEEK 15 0 register is the result of get_bits or peek_bits command in BRUPEG_VLD_MODE register Name L R Bits 7 0 of the get_bits peek_bits result Name en aw Besrpion Reset GET PEEK H R Bits 15 8 of the get bits peek bits result SAMSUNG ELECTRONICS 135 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER BRJPEG QP Y 0xFF4E Name __ Bewpim Quantization scale for luminance component BRJPEG C 0xFF4F eit Rw Quantization scale for chrominance component BRJ
146. de CPU mode is NOT recommended BRAC CTRL3 sr mw ENC CTRL 10 m n cc BRAC BUSY 0 1 BRAC Encoder is under running 0 BRAC is idle SAMPLE L 0xFF11 Name s aw Encoding PCM Sample Lower Bits SAMPLE L 7 4 RW BRAC Encoding starts when this bit is written Then this register should be written after SAMPLE H is written mw so ee ENC_SAMPLE_H 0xFF12 Name aw SAMPLE H 7 0 R Encoding PCM Sample Upper Bits This should signed number ENC_RESULT 0xFF13 Name sr mw 1 RESULT R Encoding Result SAMSUNG ELECTRONICS 117 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC DAC 18 DAC Control Register fei jaw Internal DAC goes to power down when this bit is set to 1 0 DAC is operating 1 DAC power down VOL_DIS Volume value has maximum this bit is set to 1 i 0 Enable volume control 1 Disable volume control DAC_PDN D3_UP_DIS 0 Enable 3x up sampling 1 Disable 3x up sampling 0 Disable DAC 1 Enable DAC DAGEN When this bit is set to 1 the data outputs to DACO DACOUT_L 0xFF19 72 new Output Data for DAC 1 0 This is concatenat
147. duce current before entering STOP mode Optional There are several ways to release STOP mode Execute a reset All system and peripheral control register except RTC block are reset to their default values WDT Wakeup counting overflow by when WAKEEN bit WDTCON register is set to 1 in STOP mode causes STOP mode to be released RTC wakeup In STOP mode the RTC ALARM feature causes STOP mode to be released If any of RTC related Interrupts are enabled after the release RTC ALARM interrupt takes External Interrupt USB Wakeup MainOSCEN STOP 0 STOP mode is initiated OSC settle time If Voo gt STOP is released automaticall If Voo lt reset is issued Wake up excepl reset MainOSCEN_STOP 1 STOP mode is initiated Fsvs About 2ms If Voo gt STOP is released automaticall If Voo lt reset is issued Wake up excepl reset Figure 4 11 Entering STOP mode and Exiting STOP mode Wake up SAMSUNG ELECTRONICS 81 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER 4 4 REGISTER DESCRIPTION SUMMARY TRSTSTAT R Reset Source Status Register oo SAMSUNG ELECTRONICS 82 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER ROMB 0xA1 ee RW Dee 75 n 2 ROM Bank Selection
148. e Addr Offset signed adder ADD16W Y XRAM Byte Addr Offset 3210 signed adder ADD32 XRAM Byte Addr Offset 2 1 0 7 6 514 lt Ed 62 61 60 Figure 8 3 engine operation for ADD16H ADD16W ADD32 insturctions SAMSUNG ELECTRONICS 130 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER SUM16W XRAM Byte Offset orator ponpon pone esr 16 bit input data Up to 16 iteration signed adder XRAM Byte Addr Offset cere 8 2111917161514 er camer era 32 bit input data Up to 16 iteration signed adder Figure 8 4 engine operation for SUM16W and 2 instructions SAMSUNG ELECTRONICS 131 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER 8 4 REGISTER DESCRIPTION SUMMARY Name Add RW Description Reset BRJPEG_BUF_PTR_L OxFF40 Low byte of XRAM buffer base address BRJPEG BUF PTR H OxFF41 High byte of XRAM buffer base address BRJPEG TABLE PTR L OxFF42 E of constant table base address in internal e BRJPEG TABLE PTR H OxFF43 Re of constant table base address in internal BRJPEG IBB PTR L OxFF44 Low byte of video input bit stream buffer address BRJPEG IBB PTR M OxFF45 Middle byte of video i
149. e DAC output signal has zero Voltage But the DAC output pin should have VOmax 2 offset before playing a waveform For this operation the SSFI1BG supports the DC level shifting by hardware The basic concept of DC level shifting is as Figure 6 1 Duration Time z 1024 Fs Sampling Frequency Interrupt Interrupt Interrupt Duration Time DAC_OFF GOTO_MIDDLE Waveform GOTO_BOTTOM Figure 6 1 DC level shifting Before playing a waveform GOTO MIDDLE should be issued like sentence index A in the following table Sentence C Programmin Index 9 9 rDCOH 0 0 rDCOL 0 80 rBRAC_CTRL 0x20 GOTO_MIDDLE After the end of playing waveforms if the S3FI1BG don t need to play any more waveform then the voltage of DAC is better go to bottom Zero Volt with command with GOTO_BOTTOM The speed of increment and decrement depends on the value of DCOL DCOH The calculation of this value is same as normal waveform SAMSUNG ELECTRONICS 107 er S3Fl1BG_USER S MANUAL_REV1 00 6 2 8 PLAYING NORMAL PCM DATA 6 BRAC CODEC The supports the direct output of PCM data to DAC The control sequence of sine wave is as follows Sentence Index C Programming const char BracDirectPcm Sine 0x00 0 10 0x18 OxOf 0x13 0x47 0x65 0x64 0x87 Ox7d Oxff 0x87 Ox7d 0x64 0x67 0xa8 0x15 0x47 OxOf Oxf3 0x18 0x00 0x00 Oxe7 0xf0 Oxec Oxb8 0x5
150. e Reset LVR SAMSUNG ELECTRONICS 14 er S3Fl1BG_USER S MANUAL_REV1 00 Criteria voltage 2 0V e On Chip Regulator VDD to 1 8V conversion VDD to 3 3V conversion Clock Circuit External crystal 4MHz 12MHz External resonator 4MHz 8MHz Internal typ 16MHz oscillator External crystal 32 768KHz Internal typ 32 768KHz oscillator Onchip PLL Max 48MHz e Power Down Mode IDLE only CPU clock stops STOP selected system clock and CPU clock stop e Operating Frequency Max 24 2 e Operating Voltages 2 2V to 4 2V at 4 12MHz e Operating Temperature Range 40 85C e I O and Package type 61 GPIOs 80 pin 12x12 mm TQFP SMART option RDP Flash Read Protection Flash Program Protection SAMSUNG ELECTRONICS 15 1 INTRODUCTION S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION 1 2 BLOCK DIAGRAM Memory Controller 6 ch 10 bit ADC 4KBytes X RAM RISC 8051 Core 384KBytes Code Data Flash Watch dog Timer Interrupt 256Byte Controller TF BRJPEG Controller BRAC 10 bit DAC Advanced ADPCM LCD Controller 325 x 4com USB2 0 Device FS LCD I80 interface BSPI Master SPI
151. ed 11 SCLK B P8PUDO OxFE62 en aw Bewpon 00 Pull Up Down disabled 01 Pull down enabled GP83PUD 7 6 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP82PUD 54 RW 10 10 Pull up enabled 11 Don t use Never set mw s SAMSUNG ELECTRONICS 275 er S3Fl1BG_USER S MANUAL_REV1 00 P8PUD1 OxFE63 Name ek Den SAMSUNG ELECTRONICS 00 Pull Up Down disabled 10 Pull up enabled 00 Pull Up Down disabled 10 Pull up enabled 00 Pull Up Down disabled 10 Pull up enabled 00 Pull Up Down disabled 10 Pull up enabled 276 19 GENERAL PURPOSE I O GPIO 01 Pull down enabled 11 Don t use Never set 01 Pull down enabled 11 Don t use Never set 01 Pull down enabled 11 Don t use Never set 01 Pull down enabled 11 Don t use Never set S3Fl1BG_USER S MANUAL_REV1 00 20 EMBEDDED FLASH CONTROLLER EMBEDDED FLASH CONTROLLER 20 1 OVERVIEW This block is used for programming erase of internal flash Figure 20 1 shows sector mapping within the 384KB embedded flash Physical Start Address Sector Number 0x5 00 Sector 767 5128 0 5 0000 Sector 640 512B 0 4 00 Sector 639 512 0 4 0000 Sector 512 5128 Ox3 00 Sector 511 5128 0x3 0000 Sector 384 512B 0x2_FE00 Sector 383 512B 0x2_
152. ed with DACOUT_H DACOUT_L 1 0 RA This Register should be written before DACOUT_H and should not be written during decoding because this value affects Vout of DAC DACOUT_H 0xFF1A ea RW Output Data for DAC 9 2 This is concatenated with DACOUT L DACOUT_H 7 0 RW This register should not be written during decoding because this value affects Vout of DAC VOLUME 0xFF1B Name ek Rw Decoding Mode Volume 0x00 Mute 0xFF Max Volume Volume 70 W Encoding Mode AGC_ GAIN Value upper 4 bit lower 4 bit 16 NOTE VOmax Maximum Output Voltage of DAC SAMSUNG ELECTRONICS 118 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC DCOL 0xFF1C 0xFF1D This register selects BRAC Sampling rates at decoding and ADC auto sample rate at encoding Encoding Decoding is paused by writing 0 to this register Fs sampling Frequency when 3 up sampling mode Fsource DCO_VAL 217 5 Example Fs 10 2 Fsource 4MHz gt VAL 0x3d7 and up sampling DCO lower value 0x00 DCO higher value 0x00 SAMSUNG ELECTRONICS 119 er S3Fl1BG_USER S MANUAL_REV1 00 7 SERIAL FLASH CONTROLLER SERIAL FLASH CONTROLLER 7 1 FEATURES e External Serial Flash controller with BSPI signals e Dedicated Read DMA SFDMA for transferring from serial flash to XRAM e Dedicated SPI signals BSPI for the access of ext
153. ending Y TIMER 1 pending TIMER 2 pending BRJPEG pending BRJPEG_IE UTX pending THEIE THE URX pending RDVIE URXERR pending RxERRIE RxTOIE VDMA pending VDMA_IE IBOLCD pending IBOLCD IE EINT2 3 pending EINT2 3bEN EINT4 5 pending EINT4 5EN EINT6 pending EINT6EN EINT7 pending EINT7EN EINT8 pending EINT8EN EINT9 pending EINT9EN RTC Periodic pending PEINTEN RTC Alarm pending ALMEN USB reset suspend resume pending RSTINTEN SUSPINTEN USB SOF interrupt SUSE USB EPO interrupt EPOINTEN USB interrupt EP1INTEN USB EP2 interrupt EP2INTEN USB interrupt EP3INTEN USB EP4 interrupt EP4INTEN Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y YV OO O O 075040520 Figure 5 1 Interrupt Control System SAMSUNG ELECTRONICS 91 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE Table 5 1 Interrupt Default Priority Default Priorit Px 0 or Px 1 Oon O e O wae GENE Pp 0083H USB Device Endpoint 2 interrupt 00DBH USB Device Endpoint 3 interrupt 00 USB Device Endpoint 4 interrupt SAMSUNG ELECTRONICS 92 S3Fl1BG_USER S MANUAL_RE
154. enerated by this rate Return from ISR Auto Recording Mode Setting gt ADC ISR Interrupt Service Routine gt SAMSUNG ELECTRONICS 182 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER 13 6 REGISTER DESCRIPTION SUMMARY Wane a Rw Deep AD Conversion Lower Resut Register Une ADAT1 4 R AD Conversion Higher Result Register ADREF ADC Reference Register ADREFCMP ADC Reference Compare Register SAMSUNG ELECTRONICS 183 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER ADCONO 0xE1 Name Deep AD conversion start bit 0 Not affect 1 ADC start STC 7 RW Only in Normal mode ADMOD 00 this bit is automatically cleared by hardware when AD conversion has completed The actual AD conversion can be delayed to synchronize with the selected ADC clock period ADCKSEL This bit is effective when Recording mode RECORD 0 Auto Recording Mode ADC Data is automatically transferred to BRAC R W CON encoder and start encoding 1 Manual Recording Mode ADC Data should be transferred by CPU ADC interrupt pending register INT_PEND 5 RW ADC interrupt set this bit When this bit is set by CPU pending bit is cleared 0 Using Internal AVREF s 1 Using External AVREF Normal mode Performing AD conversion once according STC enable 3 2 Infinite mode While ADCEN 1 with STC enable
155. ernal serial flash 7 2 PIN DESCRIPTION Table 7 1 Serial Flash Interface PIN Description Gmo pinnam Gra esok searen ares r GP36 BMOSI Serial Data Output GP37 BSCSN Serial Flash Chip Select 7 3 BLOCK DIAGRAM SF DMA Figure 71 Serial Flash Controller Block Diagram SAMSUNG ELECTRONICS 120 S3Fl1BG_USER S MANUAL_REV1 00 7 SERIAL FLASH CONTROLLER 7 4 OPERATION CPU access by SFCTRL and SFPORT BSPI CSN BSCSN signal is controlled by CPU in software GPIO control When BSPI CSN bit of SFCTRL register is written 0 and there s no master which is using BSPI CPU come to have the right to use BSPI port After CPU finishes the use of BSPI BSPI_CSN bit of SFCTRL register should be written to 1 If not other masters which want to use BSPI cannot access BSPI permanently SFDMA is strongly recommended except SPI Erase Programming by CPU when high speed serial read operation is required BSPI BUSY zl 1 2 3 4 5 67 8 BSCLK Fsys 2 Fsys
156. eset Disable In this case it is used as timer counter That is interrupt occurs when WDTONT value get equals to WDTREF value and then WDTONT value is cleared to re start same operation of counting No reset occurs Interrupt Reset all Enable Reset WDTCNT overflow Interrupt is equal to WDTREF Watch dog timer interrupt occurs when WDTONT is equal to WDT SEL WDTREF and future more WDTCNT continuously counts to reach overflow that goes to reset operation WDTEN RW 0 Disable Watch dog Timer 1 Enable Watch dog Timer WCNTCLK 0xED mee ENL WDT counter source clock WCNTCLK 3 0 WCNTCK Select Clock 2 1 n 0 15 This value 15 Foyg 12MHz WCNTCK 12 MHz 216 183 Hz SAMSUNG ELECTRONICS 177 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT WDTCNT Jaw WDTCNT Watch dog Counter WDTREF 0xEF Name w Bespio Watch dog timer reference value OxFF Watch dog timer interrupt condition is WOTCNT WDTREF at WDTEN Watchdog timer counter clock Frequency NOTE WDTREF OxFF SAMSUNG ELECTRONICS 178 er S3Fl1BG_USER S MANUAL_REV1 00 13 ADC CONTROLLER ADC CONTROLLER 13 1 OVERVIEW The 10 bit A D Converter ADC module uses successive approximation logic to convert analog levels entering at one of the eight input channels to equivalent 10 bit digital values
157. et this bit H W will send NAK packet as a response from IN NAKEN1 R W packet to all endpoints involved in USBEPNAKCON1 register 0 NAK disable 1 NAK enable USBCONF 0xDF User can select SOF interrupt or CRC error interrupt for USB INTSOF SEL 7 RAN SOF interrupt source 0 SOF interrupt 1 CRC error interrupt Sending NAK operation SEND NAK RW This bit will be reset whenever SOF packet is received 0 Normal operation 1 NAK response to USB host s IN OUT SETUP packet USB Wakeup disable S3FI1BG enters to USB suspend mode whenever STOP WAKE_EN 5 R W is enabled In this time the can release from USB suspend mode when D level is low 0 Wakeup function disable 1 Wakeup function enable For power down mode in another mode except USB mode this bit is used SET SUSP 4 R W 0 No operation 1 Suspend will be issued to USB host en s aw User can select to drive D and D line by software or USB hardware DPM DI 5 RU 0 D D are set to bi direction driven by USB 1 D D are set to output only driven by Software This bit is used when user only want to drive D line by software in force 0 if DP DM DIR 1 D drives low 1 If DP DM DIR 1 D drives high This bit is used when user only want to drive D line by software in force EVE 0 if DP_DM_DIR 1 D drives low 1 If DP DM DIR 1 D drives
158. gister Map 4 Upper Address gt FB FE __ FF WO I80LCD 0 VDMA CFG 0 VDMA_FG_H_OFFSET XXXX XXXX 0000 0000 0000 0000 XXXX XXXX I80LCD_TP_W1 I80LCD_CFG_1 VDMA_CFG_1 VDMA_FG_V_OFFSET XXXX XXXX 0000 0000 0000 0000 XXXX XXXX I80LCD_TP_W2 180 DATA 0 VDMA H LEN VDMA FG H LEN XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 80 DATA 1 VDMA V LEN VDMA FG V LEN XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX IBOLCD W4 I80LCD DATA 2 VDMA DST H WIDTH L VDMA FG H WIDTH L XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX TP W5 180 DATA 3 VDMA DST H WIDTH H VDMA FG H WIDTH H XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX IBOLCD TP W6 180 DATA 4 VDMA DST ADDR L VDMA FG ADDR L XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX IBOLCD TP RO 180 DATA 5 VDMA_DST_ADDR_H VDMA_FG_ADDR_M XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX IBOLCD TP I80LCD_CMD VDMA_BG_H_WIDTH_L VDMA_FG_ADDR_H XXXX XXXX 0000 0000 XXXX XXXX XXXX XXXX I80LCD_TP_R2 I80LCD_IE VDMA_BG_H_WIDTH_H VDMA_CMD XXXX XXXX 0000 0000 XXXX XXXX 0000 0000 I80LCD_TP_R3 I80LCD_ICLR VDMA_BG_ADDR_L VDMA_IE XXXX XXXX 0000 0000 XXXX XXXX 0000 0000 7 VDMA_BG_ADDR_H VDMA_ST XXXX XXXX 0000 0000 VDMA_RGB_R XXXX XXXX VDMA_RGB_G XXXX XXXX VDMA_RGB_B XXXX XXXX I80LCD_TP_R4 IBOLCD ST VDMA BG ADDR M VDMA ICLR XXXX XXXX 0000 0000 XXXX XXXX 0000 0000 SAMSUNG ELECTRONICS 36 er
159. gnal or they can be assigned a signal function dedicated to an integrated peripheral device Each GPIO can be configured as either an input or an output The GPIO ports also can be connected to the internal interrupt controller to generate an interrupt from input signals 19 2 FEATURES e PORT 0 GPO e PORT 1 GP1 e PORT 3 GP3 e PORT 4 GP4 8 bit Input Output Port e PORT 5 GP5 7 bit Input Output Port 8 bit Input Output Port 8 bit Input Output Port 8 bit Input Output Port 8 bit Input Output Port 8 bit Input Output Port 6 bit Input Output Port PORT 6 GP6 e PORT 7 GP7 e PORT 8 GP8 gt 4 lt gt o SAMSUNG ELECTRONICS 255 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 19 3 BLOCK DIAGRAM Input Output Cotrol PnMODn Register Shared Function Output gt PORT Register Shared Function Input Shared input enable puen_b PnPUn Register pden Analog Input Figure 19 1 GPIO Block Diagram SAMSUNG ELECTRONICS 256 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 19 4 PORT CONFIGURATION B Bidirectional Input Output Table 19 1 GPIO 0 Configuration PORT 0 Selectable Functions Shared Function m RUN m cm T2CAP
160. gure 12 3 WDT Timing Diagram with interrupt and reset SAMSUNG ELECTRONICS 174 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT Fsys ISCLK WAKEEN wow Y e Wakeup Figure 12 4 WDT Timing diagram with WAKEEN on STOP mode SAMSUNG ELECTRONICS 175 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT 12 5 REGISTER DESCRIPTION SUMMARY Name Aa RW WCNTCLK WDT Counter Pre scale value register WDTREF WDT Reference Value SAMSUNG ELECTRONICS 176 er S3Fl1BG_USER S MANUAL_REV1 00 12 WDT WDTCON 0xEC Name s Bespim mw 7 WDT Interrupt Pending WINTPEND R W If the IEWDT in the IEO register is enabled and GIE is enabled a interrupt is requested when this bit is set to 1 User can clear this bit by writing 1 to this bit 0 Not effect 1 Clear Watch dog Counter WCNTCLR This bit is automatically cleared by hardware on Enable Wake up function When this bit is set to 1 other WDT function is ignored This function is only available on STOP mode WDT is operating by using internal RC R W oscillator clock WDTCNT reach overflow that goes to wake up operation WDTWAKEEN 0 Disable 1 Enable Pre Scale input source clock 0 5 1 ESCLK 32 768KHz sub oscillator clock T Interrupt Reset all disable Interrupt Disable and Reset Enable WDTONT is only used as overflow reset 01 Interrupt Enable and R
161. ically be set without any intervention from CPU If the CPU EP_IATCLR writes less than MAXP data then IINRDY bit has to be set by the CPU automatically 0 No operation 1 Auto clearing when MAXP sized packet loaded ERN In mode ISO mode EP 160 This bit is valid only when endpoint N is set to IN 0 Endpoint N will be Bulk mode 1 Endpoint N will be ISO mode In out MODE selection _ 0 Transfer direction will be OUT 1 1 Transfer direction will be IN Out mode AuTo CLeaR This bit is valid only when endpoint N is to OUT If set EP OATCLR 1 whenever the CPU unloads last data in endpoint N FIFO OORDY will automatically be cleared without any intervention from CPU 0 No operation 1 Auto clearing ORDY when FIFO data unloaded Out mode ISO mode This bit is valid only when endpoint N is set to OUT EP_OISO 0 Endpoint N will be Bulk mode 1 Endpoint N will be ISO mode USBEP1CSR2 0xBC USBEP2CSR2 0xC1 USBEP3CSR2 0xC5 USBEP4CSR2 0xC9 This register is available on OUT endpoint Name sr ceu uss mode Clear data TOGgle This bit is valid only when endpoint N is set to OUT When the EP_OCLTOG 7 W CPU writes a 1 to this bit the data toggle sequence bit is reset to DATAO 0 No operation 1 Data toggle flag set to 0 ossa 6 s owmos sersa T SAMSUNG ELECTRONICS 200 ex S3Fl1BG_USER S MANUAL_REV1 00 EP_OSDSTALL EP_OFF
162. if the CPU is not able to load an OUT ISO packet into the FIFO 0 Normal operation 1 Data received at FIFO full state ISO Out mode fifo FULL This bit is valid only when endpoint N is set to OUT Indicate no more packets can be accepted Ift USBEPnCSR2 1 0 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packets of lt 1 2 FIFO or 1 packet of gt FIFO size 0 Normal operation 1 FIFO full state Out mode Out packet ReaDY This bit is valid only when endpoint N is set to OUT The USB sets this bit once it has loaded a packet of data into the FIFO Once the CPU reads the FIFO for the entire packet this bit should be cleared by the CPU II S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER 0 Not received data packet 1 Received data packet from USBEP1CSR3 0xBD USBEP2CSR3 0xC2 USBEP3CSR3 0xC6 USBEP4CSR3 0xCA This register is available on IN endpoint In mode Clear data TOGgle This bit is valid only when endpoint N is set to IN When the CPU EP_ICLTOG writes a 1 to this bit the data toggle bit is cleared This is a write only register 0 No operation 1 Data toggle flag set to 0 In mode SenT STALL This bit is valid only when endpoint N is set to IN The USB sets EP ISTSTALL this bit when a STALL handshake is issued to an IN token due to the CPU setting SEND STALL bit When the USB issues a STALL handshake IINRDY is cleared 0 No operation 1
163. imal n o x s o wu s gt o ww s o wem wmm 9 ws 7 1 1 5 2 emu SAMSUNG ELECTRONICS 155 S3Fl1BG_USER S MANUAL_REV1 00 10 UART Loopback Mode The UART provides a test mode referred to as the Loopback mode to aid in isolating faults in the communication link This mode structurally enables the connection of URXD and UTXD in the UART In this mode therefore transmitted data is received to the receiver via URXD This feature allows the processor to verify the internal transmit and to receive the data path This mode can be selected by setting the loopback bit in the UART control register UCONO Infrared IR Mode The UART supports infrared IR transmission and reception which can be selected by setting the Infrared mode bit in the UART control register In IR mode the transmit period is pulsed at a rate of 3 16 that of the normal serial transmit rate when the transmit data value in the UTXBUF register is 0 In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a 0 value in the receiver buffer register URXBUF as the IR receive data IrDA Tx Encoder UART IRMODE Block IrDA Rx Decoder Figure 10 4 IrDA Function Block Diagram 4 UART Frame gt Start Bit Data Bit Stop Bit
164. ination 222 moving area w W W Vertical length 1 for the background and destination 222 VDMA_V_LEN RW moving area V RW 222 VDMA BG H WIDTH L OxFFE8 Low byte of the horizontal width of the background source frame VDMA BG H WIDTH H OxFFE9 High byte of the horizontal width of the background source frame VDMA BG ADDR L OxFFEA Low byte of the background source area starting address VDMA BG ADDR M OxFFEB R W Middle byte of the background source area starting 223 address VDMA BG ADDR H OxFFEC of the background source area starting SAMSUNG ELECTRONICS 47 er S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION VDMA FG H WIDTH H 0xFFF5 High byte of the horizontal width of the foreground 224 source frame VDMA_FG_ADDR_L OxFFF6 Low byte of the foreground source area starting address 224 VDMA FG ADDR M OxFFF7 Middle byte of the foreground source area starting 224 address VDMA FG ADDR 2 of the source area starting 224 VDMA IE OxFFFA Interrupt enable 225 VDMA RGB B VDMA_RGB Blue value 225 SAMSUNG ELECTRONICS 48 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET INSTRUCTION SET All S3FI1BG instructions are binary code compatible and perform the same functions as they do with the standard 8051 The effects of these instructions on bits flags and other status functions are identical to the standard 8051 However
165. ing Run ength decoding Inverse quantization IQ e Inverse DCT engine 16 bit multiplier and 32 bit accumulator supporting 4 point and 8 point DCT Clipping circuit Support additional MAC MUL ADD SUM instructions with up to 16 data input SAMSUNG ELECTRONICS 126 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER 8 3 OPERATION Figure 8 1 on the next page shows BRJPEG Decoder decoding scheme BRJPEG Decoder has two hardwired engines VLD and IDCT VLD engine consists of bit processor BP variable length decoder VLD and inverse quantizer IQ Bit processor reads the bit stream data from input bit stream buffer in internal e FLASH external serial flash or XRAM The Huffman codes extracted from BP are decoded by VLD and IQ with the table information in e FLASH And the output is sent to the one of BUFO1 and BUF23 XRAM IDCT engine reads the VLD engine output from BUF01 or BUF23 performs 2 D IDCT and clipping and saves the result to the one of BUFO BUF2 BUF4 and BUF5 Then VDMA takes the decoded YCbCr data does the color space conversion from YCbCr to RGB on the fly and sends RGB data to the I80LCD controller for display For the maximum performance BRJPEG decoder provides ping pong buffers for both VLD engine and IDCT engine VLD engine can select one of BUFO1 and BUF23 for its output IDCT engine can select the input data from one of BUF01 and BUF23 and the output data from one of BUF4 and BUF5 6 buffer
166. ing PLL stable by monitoring PLL STABLE bit in PLLCONO register 300 Lock up time If PLLis stable set CLKSRC fields CLKCON register to 1010 and then Fsource is fed from PLLCLK 2 Clock Source Selection Clock input source Fggyrce can use EMCLK PXI ESCLK PXTI PLLCLK IMCLK internal 16MHz OSC default or ISCLK internal 32K OSC as its clock source by setting CLKCON 2 0 only after stabilization Otherwise it might bring the chip into unexpected status of operations Especially when using PLLCLK as clock source must use EMCLK as PLL clock input Figure 4 9 shows system clock source change timing diagram Other case is same operation EMCLK SUUUUUU External Oscillator Stabilization time 05 MainOSCdis Main OSC enable MainOSCstable IntMOSCdis nt MOSC disable Int MOSC enable IntMOSCstable FsouncE Freezed 16 During 3 times EMCLK es IMCLK Check MainOSCstable Check IntMOSCstable Internal Oscillator Stabilization time 2ms It changes to EMCLK It changes to IMCLK Figure 4 9 The case that changes clock source SAMSUNG ELECTRONICS 76 er S3Fl1BG_USER S MANUAL_REV1 00 How to control clock source After Reset system is running by IMCLK Using ESCLK rSYSCFG 0 rCLKCON 0x1B Using ISCLK rSYSCFG 0 rCLKCON Ox1A Using IMCLK rSYSCFG 0 While rSYSCFG amp 0x80 rCLKCON 0x10 Using EMCLK rSYSCFG 0 While rSYSCFG amp 0x40 rCLKC
167. isabled 01 Pull down enabled GP36PUD 5 4 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP35PUD 3 2 R W 10 Pull up enabled 11 Don t use Never set 00 Pull Up Down disabled 01 Pull down enabled GP34PUD 1 0 R W 10 10 Pull up enabled 11 Don t use Never set SAMSUNG ELECTRONICS 270 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO 0xFE54 00 Input 01 Output GP43MOD 7 6 RW 10 SEG3 11 18005 B 00 Input 01 Output GP42MOD 5 4 R W 10 SEG2 11 18004 B 00 Input 01 Output GP41MOD 3 2 R W 10 SEG1 11 18002 B 00 Input 01 Output GP40MOD 1 0 R W 10 SEGO 11 18002 B P4MOD1 0xFE55 00 Input 01 Output GP47MOD 76 RW 10 SEG7 11 18009 B 00 Input 01 Output GP46MOD 5 4 R W 10 SEG6 O 11 18008 B 00 Input 01 Output GP45MOD 3 2 R W 10 SEG5 11 180D7 B 00 Input 01 Output GP44MOD 1 0 RW 10 SEG4 11 180D6 B P4PUR 0xFE56 0 Pull up Disable 1 Pull up Enable GP46PU 6 RW 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable lo 0 Pull up Disable 1 Pull up Enable o GP43PU 0 Pull up Disable 1 Enable GP42PU 0 Pull up Disable 1 Pull up Enable GP41PU 0 Pull up Disable 1 Pull up
168. ister to end USBSUSM 1 R C RW resume signaling The CPU reads USB interrupt Pending register for the USB resume interrupt 0 Normal operation 1 Suspend state SUSpend Enable USBSUSE 0 Disable Suspend mode 1 Enable Suspend mode SAMSUNG ELECTRONICS 195 er RESUme Mode The CPU sets this bit for a duration of 10ms maximum of 15ms to initiate a resume signaling The CPU generates resume signaling USBRESUM 2 RW while this bit is set in suspend mode 0 Normal or suspend state 1 Resume signal generation in suspend state S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER USBIPEND 0xB3 The CPU will be written a 1 to clear each pending bit Mame ReSeT interrupt PENDing USBRSTPEND The USB sets this bit when it receives reset signaling USBRESPEND USBSUSPEND 0 No reset interrupt 1 Reset interrupt generated RESume interrupt PENDing The USB sets this bit when it receive resume signaling while in suspend mode If the resume is due to a USB reset then the CPU is first interrupted with a Resume Interrupt Once the clocks resume and the SEO condition persists for 3ms USB RESET interrupt will be asserted 0 No resume interrupt 1 Resume interrupt generated SUSpend interrupt PENDing The USB sets this bit when it receives suspend signaling This bit is set whenever there is no activity for 3ms on the bus Thus if the CPU does not stop the clock after the first suspend inter
169. k 2_ R W 0 disable 1 enable 6 SAMSUNG ELECTRONICS 84 uU S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER x irenabie Control into Timer 0 block 0 4 0 disable 1 enable Control into SPI block SPI CKEN 3 RW 0 disable 1 enable Control into ADC block ADC CKEN 2 RW 0 disable 1 enable Control into RTC block Even if this bit is set to 0 RTC counter is RTC_CKEN R W alive if RTCCLK is running 0 disable 1 enable Control into WDT block WDT CKEN R W 1 0 disable 1 enable CLK_EN1 0xA6 to supply each peripheral is frozen when bit of this register is set to 0 Control into LCD block LCD_CKEN 7 RW 0 disable 1 enable Control Fsys into block VDMA_CKEN R W 0 disable 1 enable Control Fsys into IBOLCD block I80LCD_CKEN 5 RW 0 disable 1 enable Control into BRJPEG block JPEG CKEN 4 RW 0 disable 1 enable FLASH CKEN R W Flash control block s clock enable bit 0 disable 1 enable _ Control Fsys Fsys 2 into block 0 disable 1 enable Control Fsys into USB Device block U11_CKEN R W 0 disable 1 enable SAMSUNG ELECTRONICS 85 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER PCON 0xA7 U
170. le 2 6 Table 2 7 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 3 5 Table 3 6 Table 3 7 Table 3 8 Table 4 1 Table 4 2 Table 5 1 Table 7 1 Table 9 1 Table 10 1 Table 10 2 Table 11 1 Table 13 1 Table 14 1 Table 14 2 Table 17 1 Table 18 1 Table 18 2 Table 18 3 Table 18 4 Table 19 1 Table 19 2 Table 19 3 Table 19 4 Table 19 5 Table 19 6 Table 19 7 Table 19 8 Table 21 1 Table 21 2 Table 21 3 Table 21 4 Table 21 5 Table 21 6 Table 21 7 List of Tables Title Page Number Gode Memory MAP u u u L ua a asqa awakusqa de Ru Qa d 27 Data Memory u D oh acted 29 Special Function Register 32 Extended Special Function Register 1 33 Extended Special Function Register 2 ener ener nre 34 Extended Special Function Register 3 35 Extended Special Function Register 4 36 Notalions decir eis lies 5 Mnemonic and of Data Transfer Instructions 55 Mnemonic and Operand of Arithmetic Instructions nennen 57 Mnemonic and Operand of Unconditional Branch Instructions 58 Mnemonic and Operand of Boolean Instructions
171. ler Electrical Characteristics Table 21 10 Internal Flash ROM Electrical Characteristics SAMSUNG ELECTRONICS eq S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION INTRODUCTION S3FI1BG combines a powerful RISC 8051 based micro controller with a hardwired high quality ADPCM voice codec called BRAC to simply play voice or sound at the sampling frequency of up to 48KHz and with hardwired JPEG like graphic image decoder called BRJPEG And its 384Kbytes embedded e FLASH memory and richer peripherals will reduce the chip count on your system resulting in manufacturing cost down and early time to market In addition In house software development tool kit Power Studio Debugger and hardware In circuit emulator called PowerlCE will make your development much faster and easier 1 1 FEATURES 8 bit RISC 8051 core MCU Advanced RISC B51 core using 1 clocks per instruction Dual DPTRs Data Pointer Registers for fast block move e Hardwired ADPCM Voice Codec e Har Embedded own ADPCM Codec BRAC with a dedicated DMA Selectable sampling frequency from 4KHz to 48KHz o Built In Low Pass Filter times up sampling o 33 bit 4 bit data compression Volume control with mute feature Automatic DMA access to external Serial Flash up to 1Gbit IBB Input Bit stream Buffer mode for direct playback
172. maintains the byte count number of data in FIFO due to be unloaded by the CPU Name Bn CPU The byte count number of data second saved in FIFO due to be secondly unloaded by the CPU when there are two packets of MAXP lt 1 2 FIFO size USBEPnCSR2 1 0 is 11b In case USBEPnCSR2 1 0 is 00b or 01b 0x00 is displayed on this fields USBEPOFIFO 0xD5 USBEP1FIFO 0xD6 USBEP2FIFO 0xD7 USBEP3FIFO 0xD8 USBEP4FIFO 0xD9 CPU Description Name CPU USB Descripion Reset Fuss SAMSUNG ELECTRONICS 204 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER USBEPLNUM1 0xDA This register holds the endpoint numbers to indicate each physical endpoint and the default number is the same as physical one You can change endpoint number from 5 to 15 by setting this register ee C These bits express logical number So Endpoint 2 default is able to be changed to other EP number from 5 to 15 These bits express logical number So Endpoint 1 default is able LNUMEP to changed to other number from 5 to 15 USBEPLNUM 0xDB ater emer 2 These bits express logical EP number So Endpoint 4 default is able EISSIMIEPA to changed to other number from 5 to 15 These bits express logical number So Endpoint 3 default is able
173. mber within SOF packet Frame Number within SOF packet is 11 bits Frame Number 7 0 from SOF packet 0x00 et cu uss Desn ra Rem w Frame numerosi rom soF pare i 79 BE L SAMSUNG ELECTRONICS 197 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER USBEPOCSRO 0xB7 Name sr ceu uss Deep 0 MAXP isn t overwritten when CPU writes any value to MAXPSET 7 W USBEPnCSRO register 1 MAXP is overwritten fea Rem MAXP size value If MAXP is 00 then MAXP is 8 bytes If MAXP is 01 then MAXP is 8 bytes If MAXP is 10 then MAXP is 16 bytes USBEPOCSR 1 0xB9 Name espio SerViced SETup end The CPU writes a 1 to this bit to clear SETEND 0 No operation 1 SETEND bit clear SerViced Out ReaDY The CPU writes a 1 to this bit to clear ORDY 0 No operation 1 ORDY bit clear SenD STALL The CPU writes a 1 to this bit at the same time it clears ORD Y if it decodes an invalid token The USB issues a STALL handshake to the current control transfer The CPU writes a 0 to end the STALL condition 0 Normal operation state 1 Go to stall token transmit state SETup END This bit is read only bit The USB sets this bit when a control transfer ends before DEND is set The CPU clears this bit by writing a 1 to the SVSET bit When the USB sets this bit an interrupt i
174. meaningful result only as the second step in the addition of two BCD bytes Table 3 3 is Mnemonic and operand description of each arithmetic instruction Each function and effects on PSW are also described The symbol means no effect t PSW the symbol lt gt means can effect to PSW and 0 means always force to 0 SAMSUNG ELECTRONICS 56 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET Table 3 3 Mnemonic and Operand of Arithmetic Instructions Mnemonit amp Operation amp Functions cy Fo RS ADD A mm A lt 24 e gt e e ADD A Ri A lt 26 27 gt e ADD A Rn A lt A Rn 28 2F m gt e ADD A Dir A A Dir 25 lt gt o o ADDC A imm A lt A imm CY 34 o lt gt PEN ADDC A QhRi A lt 36 37 e o o ADDC A Rn A lt A Rn CY 38 e o e o ADDC A Dir A Ar bDi CY 35 o o SUBB imm A lt A imm 94 e o oe e SUBB A Ri A _ 96 97 o o o SUBB 98 OF o o SUBB Dir A lt A Dir CY 95 e o INC A A 1 04 o INC Ri Ri lt 1 06 07 INC Rn Rn lt Rn 1 08
175. mon Status Registers CH Tuseeracsro oxca EPs Common Regstero Tuseeracsrt USB EP Common Status Regitert Tusaeracsra ncs USB Common Status Register Puseeracsra os EPs Common Tuseeracsro oxc7 USB EP4 Common Regstero oo ussmcsm os USB EPs Common Status Register Tuseeracsre wo 98 EPs Common Status Register 0x00 Tuseeracsra usBEPACommonstusRegsrs oo voce Ero wrie Coun oo usseemwci occ USB EPt wrie Coun Register 00 EPt wrie Count oxce usstReWieCourFegser 00 05 Coun Registera ussERsWHeCourFegser oo oe USBEFSWHeCoutFegsters xs EPa wrie Count Reistert 00 usseawce Use Count Regstera SAMSUNG ELECTRONICS 193 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER ows _ 006 ustermo O or O USBNAKCON2 USB Control Register 2 0x00 USBNAKEN
176. n 0x0003 If the interrupt is not going to be used its service location is available as general purpose program memory The interrupt service locations are spaced at 8 byte intervals If an interrupt service routine is short enough it can reside entirely within that 8 byte interval Longer service routines can use a jump instruction to skip over subsequent interrupt location if other interrupt are in use 5 2 INTERRUPT PRIORITY Each interrupt source can also be individually programmed to one of two priority levels by setting or clearing a bit in Special Function Register IPx A low priority interrupt can itself be interrupted by a high priority interrupt but not by another low priority interrupt A high priority interrupt can t be interrupted by any other interrupt source If two requests of different priority levels are received simultaneously the request of higher priority level is serviced requests of the same priority level are received simultaneously smaller number of default priority value is serviced Table 5 1 describes Interrupt Default Priority just after reset SAMSUNG ELECTRONICS 90 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE IEx Higher Individual enables Lower WDT pendin 9 Priority BRAC pending BRAC_INT_EN ADC pending ADINTEN EINTO pending EINTOEN EINT1 pending EINT1EN Y SPI pending Y TIMER 0 p
177. n STOP mode MAIN OSCGEN STOP 0 disable in STOP mode 1 Enable in STOP mode I 32KH ill trol INT 32K OSC DIS 3 RW nternal 3 2 oe ator enable contro 1 0 1 disable INT MOSC DIS 2 RW Internal 16MHz Oscillator enable contro 0 enable 1 disable ill PXTI SUB OSC DIS 1 Rw Sub Oscillator enable contro 0 enable 1 disable MAIN OSC DIS RW Main Oscillator enable control 0 enable 1 disable IVCON0 0xAB Nome Rw Den BLD Level selection bits Each value 0 2 tolerance BLD_SEL 7 6 Be careful with the order of bit values 00 3 08V 11 2 77V 10 2 43V 01 2 23V BLD EN 5 RW Battery Level Detector BLD Enable 0 disable 1 enable Control IVC driving capability in STOP mode 3 ISTOP 43 RW i strongest largest 11 weakest smallest Low Voltage Reset LVR Level selection bits LVR SEL 2 1 Be careful with the order of bit values 00 2 051V 11 2 000V 10 1 951V 01 1 905V LVR Enable 0 disable 1 enable SAMSUNG ELECTRONICS 87 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER 1 Name o 7e Red BLDOUT 5 BLD Battery Level Detector output signal IS PD EN 4 RN Sub IVC Power Down Enable when idle operation mode 0 No power Down 1 Power Down IM PD RW Main IVC Power Down Enable when idle operation mode
178. n the timer is enabled The timer time out value register is to be loaded into the TCNTn register 11 2 FEATURES e 3 Programmable Timers e Interval Mode Toggle Mode PWM Mode and Capture Mode 3 Programmable duty control of output wave form PWM and Timer output 11 3 PIN DESCRIPTION Table 11 1 Timers PIN Description ee GP13 GP04 TCLK External Clock Source for Timer 0 Timer 1 and Timer 2 GP12 GP05 TOCAP TOOUT Timer 0 Capture Input Timer 0 16 bit PWM mode output or counter match toggle output GP11 GPO6 T1CAP T1OUT Timer 1 Capture Input Timer 1 16 bit PWM mode output or counter match toggle output GP10 GP07 T2CAP T2OUT Timer 2 Capture Input Timer 2 16 bit PWM mode output or counter match toggle output SAMSUNG ELECTRONICS 164 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS 11 4 BLOCK DIAGRAM 14 16 bit time out value Register 18 TnDATA1 INT 1 4096 16 bit Down Counter gt EXT EXTTCLK TnCNT1 TnCNTOJ Figure 11 1 Timers Block Diagram SAMSUNG ELECTRONICS 165 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS 11 5 OPERATION When TnDATA is set it loads a data value into count register When timer is enabled it begins decrement of the count register value TNCNT When the TnCNT reaches 0 the associated interrupt is generated The base val
179. nRESET level initialize the internal state of the device Thereafter setting the input to high release the reset status The SSFI1BG waits for the system clock to be stable and then set PC to the reset interrupt vector Internal Reset is generated after clock stabilization nRSTOUT External Device reset control nRSTOUT Pin RESET LVD Reset SW Reset WDT Reset Clock Output signal The CLKOSEL bits in CLKCON register configure the clock output CLKOUT mode among Main OSC clock Sub OSC clock Internal 16MHz main OSC clock Internal 32KHz sub OSC clock RTC clock output PLL output clock and etc Factory test input pin TEST NOTE This pin should be connected to Ground External Interrupt 10 pins Nm External Interrupt input pins EINT0 EINT9 The valid edge for EINT0 to EINT9 can be selected through the EINTMODx register When these are not used for interrupts these can be used as normal pins JTAG System Interface 4 pins ICE The default function of this is JTAG pin and user program can change this pin as normal GPIO when ICE is not connected ICE TDI TDI The default function of this pin is JTAG TDI pin and user program can change this pin as normal GPIO when ICE is not connected ICE TCK TCK The default function of this pin is JTAG TCK pin and user program can change this pin as normal GPIO when ICE is not connected ICE TMS TMS The default function of this pin is J
180. nd it can be controlled through register VOLUME It effects immediately after setting Therefore during the sound output from the S3FI1BG changing the level of volume with the big difference value compared to the previous one may cause noise 6 2 11 DIGITAL LOW PASS FILTERING AND UPSAMPLING has digital low pass filter inside of the chip called upsampling function This low pass filter up samples three times from original waveform which means the sound quality is improved a lot without the implementation of analog filter outside of the chip Even though programmer selects the upsampling function the voice data don t need to be changed But if up sampling function is selected then the BRAC_DCO_VALx should be set with 3 times larger value than the original value Sentence Index C Programming define UPSAMPLING ifdef UPSAMPLING rDAC_CTL 1 3x up sampling On else rDAC_CTL 3 3x up sampling Off endif Original Sine Wave Upsampled Sine Wave Figure 6 3 3x Up sampling SAMSUNG ELECTRONICS 110 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 12 IBB INPUT BIT STREAM BUFFER MODE S3FI1BG supports BRAC data read from X RAM instead of voice data memories This is very useful for NAND flash devices because of direct playback in X RAM In other words BRAC DMA reads BRAC data from X RAM instead of e FLASH or external serial flash The size of IBB fo
181. nd the transmit shift register is empty If TIIE in UINTCON register is 1 and this bit is 1 TX interrupt Request will be generated 0 Not ies Receive This bit is set to 1 automatically whenever receive buffer register Data Valid contains valid data received over the URXD port RDV 0 Empty 1 The buffer register has a received data This bit is cleared automatically by reading URXBUF Receive This bit is only for CPU to monitor the receive state of UART This IDLE RXIDLE bit indicates that RX operation is in active UERSTAT 0xF4 All bits of UERSTAT register are automatically cleared to 0 when this register is read Waman 72500 mw _ Error This bit is to 1 automatically whenever a overrun error occurs OER during receive operation When URXBUF has a previous valid data but a new received data is going to be written into URXBUF 0 No overrun error during receive 1 Overrun error Interrupt is requested Parity Error This bit is to 1 automatically whenever a parity error occurs during PER receive operation 0 No parity error during receive 1 Parity error Interrupt is requested SAMSUNG ELECTRONICS 160 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART Frame Error This bit is set to 1 automatically whenever a frame error occurs during FER receive operation A frame error occurs when a 0 is detected instead of the stop bit s 0
182. nput bit stream buffer address BRJPEG IBB PTR H OxFF46 High byte of video input bit stream buffer address BRJPEG IBB XRAM PTR OxFF47 bit stream buffer offset address XRAM Reem SAMSUNG ELECTRONICS 132 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER BRJPEG 0 OxFF60 Accumulator byte 0 LSB in IDCT engine BRJPEG_IDCT_ACC_1 OxFF61 Accumulator byte 1 in IDCT engine BRJPEG IDCT ACC 2 OxFF62 Accumulator byte 2 in IDCT engine BRJPEG IDCT ACC 3 OxFF63 Accumulator byte 3 MSB in IDCT engine NOTE These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 133 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER BRJPEG_BUF_PTR_L 0xFF40 BRJPEG_BUF_PTR_H 0xFF41 BRJPEG BUF PTR 11 0 register is the base address pointer for the XRAM buffers which are used by the processing engines to save the intermediate data and pass the input and output data For the minimum performance two 192 byte buffers BUFO BUF1 are needed For the maximum performance six 192 byte buffers BUFO to BUF5 are needed Wee ei RW sasa BUF PTR L Bits 7 0 of XRAM buffer base address Nm ee Rw Den vw ra new E BRJPEG TABLE 0xFF42 BRJPEG TABLE H 0xFF43 BRJPEG TABLE PTR 15 0 register is the base address pointer for the constant tables in internal Flash Seven constant tables should be located in predefined order in internal fl
183. ns Download all the data to the end of file D Download and verify SAMSUNG ELECTRONICS 100 er S3Fl1BG_USER S MANUAL_REV1 00 6 2 2 FILE FORMAT OF PROJECT_NAME H Let s assume the name of waveform files are as follows 0 1 2 37 4 6 71 9 107 117 12 14 15 16 17 187 197 chord_16K_mono wav ding_16K_mono wav notify 16K mono wav ringin 8K mono wav ringout 8 mono wav tada 16K mono wav Chimes 16K mono wav chinese part 16 monoO0 wav chinese part 16 3 wav number 0 wav number 1 wav number 2 wav number 3 wav number 4 wav number 5 wav number 6 wav number 7 wav number 8 wav number 9 wav number 10 wav 6 BRAC CODEC The generated header file for BRAC includes the enumeration of file name the start address and the size of each compressed voice data if 1 enum only English file name cane be enumerated chord 16K mono ding 16K mono notify 16K mono ringin ringout mono tata 16K mono Chimes 16K mono chinese part 16 0 chinese part 16 0 3 number 0 number 1 SAMSUNG ELECTRONICS 101 16000Hz 4Bit 16000Hz 4Bit 8000Hz 4Bit 8000Hz 4Bit 8000Hz 4Bit 16000Hz 4Bit 16000Hz 4Bit 16000Hz 4Bit 16000Hz 4Bit 16000Hz 4Bit 16000Hz 4Bit S3Fl1BG_USER S MANUAL_REV1
184. ntenupt8 1 Enable o Disable Enable o Hexe w O Disable Enable o Eexta 5 o Rw o Disable extemal interrupt 46 1 Enabie External nterupt a o SAMSUNG ELECTRONICS 97 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE IP2 0x97 wane er Rw Den Heusensr 7 0 Lower priory evel 1 tioner priory 6 Raw 0 Lower priory tevel 1 Higher pronty evel 5 Raw 0 Lower priory tevel 1 4 Raw 0 Lower priory tevel 1 Higher prty evel Raw 0 Lower priory tevel 1 Higher pry evel 72 raw 0 Lower priory tevel 1 Higher pry Raw 0 Lower priory evel 1 Higher priory ev 0 5 o Rw 0 Lower priory evel 1 Higherprionyievel 0 IE3 0x99 Nm Rw esr s Parodio _ Enabie ATO Prodo memu o Rw 0 Disabie Exteralintenupt7 Enable Exeral o s 0 Disabie Enabe o 2 0 Disable Extemalintenupts Enable
185. ocks for USB Software program can control the operation frequency of the PLLs internal clock sources and either enable or disable the clock to reduce the power consumption The S3FI1BG has various power down modes to keep optimal power consumption for a given task The power down modes consists of three modes General Clock Gating mode IDLE mode and STOP mode General Clock Gating mode is used to control the ON OFF of clocks for internal peripherals in the S3FI1BG User can optimize the power consumption of the SSFI1BG using this General Clock Gating mode by supplying clocks for peripherals that are necessary for a certain application 4 2 FEATURES e Include on chip PLL e Include on chip 16MHz Main oscillator e Include on chip 32 768KHz Sub oscillator e Independent clock ON and OFF control to reduce power consumption e Supports power down mode Power clock gating IDLE and STOP mode to optimize the power consumption e Wake up by one of external interrupt WDT wake up USB wake up and RTC alarm wake up STOP mode Only SAMSUNG ELECTRONICS 69 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER 4 3 OPERATION 4 3 1 RESET MANAGEMENT RESRT Types processor has four types of resets and reset controller can place the system into the predefined states with one of the following resets Pin RESET PnRESET Uncompromised unmask able and complete reset it is generated when PnRESET pin is asserted Software
186. of voice data in X RAM Voice Recording dwired BRJPEG Decoder Embedded own DCT based Image decoder o 128x128 10 frame decoding 12MHz o 192x192 10 frame decoding 24MHz Built in processing engines for image decoding o Variable length decoding engine o Inverse DCT engine Support additional MAC MUL ADD SUM instructions with up to 16 data input e VDMA Two dimensional DMA engine with on the fly additional functions o Color space conversion from YCbCr to RGB o MMixing foreground and background images o Alpha blending with 4444 and 5551 formats Local IBOLCD channel to read write RGB data to from external frame memory SAMSUNG ELECTRONICS 12 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION e Memories 384 embedded NOR Flash Memory e FLASH for program and data o Sector Endurance 10 000 Cycles o Greater than 10 years Data Retention o This memory is protected from writing after reset 256Bytes On chip data SRAM I RAM 4KBytes On chip Extended data SRAM X RAM Upto 1Gbits Serial NOR Flash externally expandable JTAG Interface Debug and In System Programming through JTAG In house Development Tools Power Studio v1 2 SDK Software Development Kit and In Circuit Emulator PowerlCE Support IAR Compiler n house Mass Production Tools Gang Writer PowerWriter Gang writer with 8 Sockets 80TQFP plus JTAG and USB interface to Host PC ADC 6 channels 10 bit
187. oggle Mode In toggle mode the timer pulse continues to toggle whenever a time out occurs An interrupt request is generated whenever the level of the timer output signal is inverted that is when the level toggles The toggle pulse is output directly at the configured output pin Using toggle mode you can achieve a flexible timer clock range which 50 duty In case Interval Mode TnOUT Interupt 15 Interupt is x Interupt is issued issued issued In case Toggle Mode TnOUT Interupt 15 t Interupt is 4 Interupt 15 issued issued issued Figure 11 3 Example of Timer Operation in Interval and Toggle Mode SAMSUNG ELECTRONICS 167 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS Capture Mode In Capture Mode the interrupt is generated whenever TnCAP pin is issued Capture interrupt enable bit isn t existence and TnOUT is not coming out In capture mode the interrupt is generated whenever rising edge of TnCAP pin is detected An interrupt request a capture trigger are generated at switching the active rising edge of a TnCAP pin At the same time the value of a counter is stored to the temporary register And reading TnCNT by CPU the temporary register value will be read out to the CPU If a new capture trigger is generated before the value of TnCNT is read the value of temporary can be rewritten So new value will be read out when CPU read TnCNT register is shared with TnOUT pin T T
188. on Bytes Standard 8051 S3FI1BG JB bit rel 3 24 4 3 JNB bit rel 3 24 4 3 JBC bit rel 3 24 4 3 JC rel 2 24 3 2 JNC rel 2 24 3 2 JZ rel 2 24 3 2 JNZ rel 2 24 3 2 CJNE Ri imm rel 3 24 4 3 imm 3 24 4 3 SAMSUNG ELECTRONICS 67 en S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET CJNE A Dir rel 3 24 4 3 Rn imm 3 24 4 3 DJNZ Dir rel 3 24 4 3 DJNZ Rn rel 2 24 3 2 Detailed Logical Instruction Summary 7 Maximum Clock Cycles Logical Instruction Bytes Standard 8051 S3FI1BG ANL A imm 2 12 ANL A Ri 1 12 2 ANL A Rn 1 12 1 ANL A Dir 2 12 2 ANL Dir imm 3 24 3 ANL Dir A 2 12 3 ORL A imm 2 12 2 ORL A Ri 1 12 2 ORL A Rn 1 12 1 ORL A Dir 2 12 2 ORL Dir imm 3 24 3 ORL Dir A 2 12 3 XRL A imm 2 12 2 XRL A Ri 1 12 2 XRL A Rn 1 12 1 XRL A Dir 2 12 2 XRL Dir imm 3 24 3 XRL Dir A 2 12 3 CLR A 1 12 1 CPL A 1 12 1 SWAP A 1 12 1 RL A 1 12 1 RLC A 1 12 1 RR A 1 12 1 RRC A 1 12 1 SAMSUNG ELECTRONICS 68 mm S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER SYSTEM CONTROLLER 4 1 OVERVIEW The system controller consists of three parts reset management system clock management and system power management control The system clock management logic can generate the required system clock signals There is a PLL to generate internal cl
189. onsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages SS3FI1BG 8 bit CMOS Microcontroller User s Manual Revision 1 00 Copyright 2010 Samsung Electronics Co Ltd Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could
190. ound moving area SAMSUNG ELECTRONICS 223 er S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA VDMA_FG_V_LEN 0xFFF3 Name VDMA_FG_V_LEN Vertical length 1 for the foreground moving area FG WIDTH 0xFFF4 VDMA FG WIDTH 0xFFF5 VDMA FG H WIDTH 8 0 register keeps the horizontal image frame width of the foreground source nw Bei VDMA FG H WIDTH L Bits 7 0 of the horizontal width of the foreground source frame m mm nmmn me VDMA FG H WIDTH H EH Bit 8 of the horizontal width of the foreground source frame FG ADDR VDMA FG ADDR M 0xFFF7 ADDR 8 VDMA FG ADDR 23 0 register is the foreground source image address Name B Rw Deseo VDMA_FG_ADDR L Bits 7 0 of the foreground source area starting address Nm Besrpion FG ADDR M Bits 15 8 of the foreground source area starting address Mame s RW Besp o VDMA FG ADDR H Bits 23 16 of the foreground source area starting address 0xFFF9 sv Reseed SS VDMA enable command When set it is not cleared until the VDMA VDMA_ EN R W operation is done 0 idle 1 enable W busy R SAMSUNG ELECTRONICS 224 er S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA VDMA_IE Name __
191. overflow multiply or divide The Parity bit reflects the number of 1s in the Accumulator P 1 if Accumulator contains an odd number of 1s Odd Parity Check Thus the number of 1s in the Accumulator plus P is always even SAMSUNG ELECTRONICS 52 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 INSTRUCTION TYPE The register and operand notations for instructions are follows Table 3 1 Operand Notations Ri 8 bit internal I RAM location OOH addressed indirectly through RO or R1 bit direct addressed bit in I RAM 20H or SFR 80H Signed two s complement 8 bit offset byte used by SUMP and all conditional umps Range 128 to 127 bytes relative to first byte of the following instruction 16 bit destination address used by LCALL and LUMP a branch can be anywhere within the 64KB code memory address space 11 bit destination address used and a branch be within the same 2KB of code memory as the first byte of the following instruction 8 bit constant included in instruction 16 bit constant included in instruction SAMSUNG ELECTRONICS 53 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 1 DATA TRANSFER INSTRUCTIONS Data transfer instructions are available for moving data around SFR internal I RAM X RAM and e FLASH area The MOV instruction allows data to be transferred between any internal I RAM spaces or SFR locations and between accumulator
192. p signal and interrupt will be requested when this bit is set to 1 User can clear this bit by writing 1 to this bit In the STOP mode this bit is available Alarm Interrupt Pending If the IERTCALM in the IE2 is enabled and GIE is enabled an ALM_PEND 5 interrupt is requested when this bit is set to 1 User can clear this bit by writing 1 to this bit In the STOP mode this bit is not available ALARM global enable bit 0 Disable 1 Enable Date ALARM enable bit EN 0 Disable 1 Enable Hour ALARM enable bit HOURS 0 Disable 1 Enable Minute ALARM enable bit 0 Disable 1 Enable Second ALARM enable bit 0 Disable 1 Enable SAMSUNG ELECTRONICS 214 S3Fl1BG_USER S MANUAL_REV1 00 15 RTC ALMSEC 0xFF8B 7 R Rend SOS BCD value for ALARM second bits R 0 00 MEC m n 6 4 bit is from 0 to 5 3 0 bit is from 0 to 9 ALMMIN 8 Name Bt Fw Description 7777 RTC RST 7 R Reseed S e BCD value for ALARM minute bits R 0x00 MERI 6 4 bit is from 0 to 5 3 0 bit is from 0 to 9 ALMHOUR 0xFF8D Name Bit RTC RSVD 76 n Reewed ___ BCD value for ALARM hour bits 0 00 RAN 5 4 bit is from 0 to 2 3 0 bit is from 0 to 9 2 ALMDATE 0xFF8E Rw re n BCD value for ALARM date bits From 0 to 28 29
193. pacitor should be chosen according to the external oscillator EMCLK can be used for the Fsource or PLL input source It can be disabled or enabled by controlling DIS bit in SYSCFG register User should check MAIN OSC STABLE bit in SYSCFG register when EMCLK is used for the After reset EMCLK is enabled External 70 C Y j p Main Oscillator Circuit External Crystal or Ceramic Resonator External Clock Circuit Figure 4 7 Main Oscillator Circuit ISCLK INTERNAL SUB CLOCK 32 768KHz ISCLK means an internal sub clock 32 768KHz ISCLK can be used for the It is not impossible to use as PLL input source The internal 32 768KHz oscillator is used for wakeup of watch dog timer as a clock source in STOP mode It can be optionally enabled or not ISCLK cannot be used for the RTC working clock After reset ISCLK is enabled SAMSUNG ELECTRONICS 74 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER ESCLK EXTERNAL SUB CLOCK 32 768KHz ESCLK means an external sub clock 32 768KHz ESCLK can be used for the It is not impossible to use as PLL input source It can be disabled by S W ESCLK can be used for the RTC working clock and watch dog timer clock source PLL The PLL Phase Locked Loop frequency synthesizer is constructed in CMOS in single monolithic structure The PLL
194. put of DAC SAMSUNG ELECTRONICS 22 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION ADC Interface 7 pins Nm AINO AIN5 Analog Input pins for 6 Range 0 0V AVREF value 10 bit A D converter AVREF ADC Reference Top Voltage Normally the max value of AVREF VDD 180 LCD Interface 22 pins wm ons sowan O wie stobe output C 180017 LCD Controller Driver 40 pins Nm o SEG 31 0 E LCD segment signal outputs CON 3 0 E LCD common signal outputs VLCD0 VLCD3 m LCD Bias pins USB Interface 2 pins o DATA for USB device DATA for USB device SAMSUNG ELECTRONICS 23 er S3Fl1BG_USER S MANUAL_REV1 00 1 INTRODUCTION GPIOs 61 pins GP00 GP07 GP10 GP16 GP30 GP37 GP40 GP47 8 Bit CMOS tri state I O port 2mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the POMODO and POMOD registers 7 Bit CMOS tri state I O port 4mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the P1 MODO and P1MOD 1 registers 8 Bit CMOS tri state I O port 4mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alterna
195. r parity error frame error and break condition each of which can set an error flag The overrun error indicates that new data has overwritten the old data before the old data has been read The parity error indicates that the receiver has detected an unexpected parity condition The frame error indicates that the received data does not have a valid stop bit break condition indicates that the URXD input is held in the logic 0 for duration of longer than one frame transmission time SAMSUNG ELECTRONICS 153 Lu S3Fl1BG_USER S MANUAL_REV1 00 10 UART Interrupt Request Generation UART of the S3FI1BG has eight status Tx Rx Error signals Overrun error Parity error Frame error Break Receive buffer data valid Transmit buffer empty and Transmit shifter empty all of which are specified by the corresponding UART status register UTRSTAT and UERSTAT The overrun error parity error frame error and break condition are referred to as the receive error status Each of which can cause the receive error status interrupt request if the receive error status interrupt enable bit is set to in the interrupt register UINTCON When a receive error status interrupt request is detected the signal causing the request can be identified by reading the value of UERSTAT When the receiver transfers the data in the receive shifter to the receive buffer register Rx interrupt is generated if the receive mode in control
196. r each channel is 256 Bytes For this mode some of X RAM area should be reserved for IBB mode And the start address of IBB can be set by lower 13 bit of BRAC_START_ADR at each channel BRAC 3 up 2 Decoder sampling Control BRAC DMA SEL_DATA_SRC Figure 6 4 BRAC Decoder Decoding Scheme Normal Play Mode SAMSUNG ELECTRONICS 111 S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC BRAC 3 up earns Decoder sampling Control Figure 6 5 BRAC Decoder Decoding Scheme IBB Play Mode SAMSUNG ELECTRONICS 112 qn S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 3 REGISTER DESCRIPTION SUMMARY Name BRAC START ADRL OxFF04 Low Byte of BRAC Start Address for decoding Undef compressed data W Middle Byte of BRAC Start Address for decoding Undef compressed data 06 High Byte of Start Address for decoding Winder compressed data BRAC SIZEL OxFFO7 W The data amount to be read from internal e FLASH or 0x00 external serial FLASH SIZEM W The data amount to be read from internal e FLASH or 0x00 external serial FLASH BRAC SIZEH OxFFO9 The data amount to be read from internal e FLASH or 0 00 external serial FLASH ER READ PTR orfon Read Pointer tor Charne crn
197. red like Index B SAMSUNG ELECTRONICS 105 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 5 PLAYING MUTE If there needs mute period between two waveforms then MUTE command can be used for it The mute period can be calculated with BRAC_SIZEx and DCOL DCOH Ex For 1 seconds muting Assumption Fsource 12MHz and upsampling DCO_VAL 0x20C 16KHz BRAC_SIZE 1 Sampling Time 1 1 16000 16000 0x3e80 penne C Programmin Index 9 9 rBRAC_SIZEM 0 3 Set Size of MUTE period rBRAC_SIZEL 0x80 rDCOH 0x2 A rDCOL 0x0C rBRAC_CTRL 0x40 MUTE Command 6 2 6 DCO SELECTING THE SAMPLING FREQUENCY FOR PLAYING S3FI1BG can generate all kinds of sampling frequency depending the value of DCOL DCOH register So the proper DCOL DCOH is selected depending on the waveform sampling frequency The value of DCOL DCOH can be calculated as follows rDCOL 217 3 for upsampling output Given Fs 16KHz and Fggyrce 12MHz then rDCOH rDCOL 0x20C rDCOL rDCOH Fs 217 Fin for non upsampling output Given Fs 16KHz and Fsource 12MHz then rDCOH rDCOL OxAE Fs is the desired output sampling frequency And is the operating frequency described in chapter 4 SAMSUNG ELECTRONICS 106 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 7 DC LEVEL SHIFTING AND PAUSE OPERATION When the S3FI1BG is reset or power on th
198. register UCON is selected Transferring data from the transmit holding register to the transmit will cause Tx interrupt Parity signal don t come out at no parity UTXD Start Data Bits 5 8 X Parity Stop 1 2 Start THE N Transmit data into load UTXBUF INT TXD N Data Bits 5 8 INT_RXD URXBUF Receive Data Receive Data Figure 10 2 UART Interrupt Timing Diagram SAMSUNG ELECTRONICS 154 er S3Fl1BG_USER S MANUAL_REV1 00 10 UART Baud rate Generation Baud rate generator of UART provides the serial clock for the transmitter and the receiver The source clock for the baud rate generator can be selected with one of internal system clock EXTUCLK Fsyg 2 Fsys 4 8 or 16 In other words dividend is selectable by setting Clock Selection of UCON1 Baud Rate CLK Source CLK CNT0 1 x 16 Source CLK EXTUCLK 2 Foys 4 8 or Fsys 1 6 EXTUCLK are sampled by But their clock and is asynchronous clock So they may not be sampled at exact time So it is recommended to use EXTUCLK under Fsyg 2 Fsys EXTUCLK Fsys 2 Fsys 4 I 8 bit Counter Divide by 16 Baud Rate CLK __Feys 8__ gt Sample CLK 16 CLK_SEL Figure 10 3 Baud Rate Generator Table 10 2 Baud Rate Example of UART Frequenc BAUD val Wanted Baud Rate Real Baud Rate eae Error Ratio Fsys Dec
199. reson secircows sesircoue secivcon sea cous secrecout seciecovo seciscons scorscouz secrocon seciecont secon Feann seceicows seceicon secercow sesencous sesencowe seczocovo seczscows seseacoue sesescon seaescoun seseacous secezcovo secercows sesercoue secercon secescovo co2sconz secescon sescacous seescowa secsicows seasicon sessocous sesencowe SAMSUNG ELECTRONICS 243 er S3Fl1BG_USER S MANUAL_REV1 00 18 LCD DRIVER CONTROLLER FRAME FREQUENCY The LCD clock signal LCDCK determines the frequency of COM signal scanning of each segment output This is also referred to as the frequency And LCDCK is generated by the watchdog timer block and its frequency is selected with values of LCKSEL register as described in Table 18 3 The LCD display can continue to operate during idle and stop modes if an external sub oscillator is used as the watch timer source when it is enabled Table 18 3 Frame Frequency Wren Fo e Tare
200. ress SAMSUNG ELECTRONICS 219 er S3Fl1BG_USER S MANUAL_REV1 00 VDMA_IE OxFFFA VDMA_ICLR OxFFFB Interrupt clear VDMA ST Status Interrupt enable VDMA RGB HR OxFFFD VDMA RGB Red value VDMA RGB G OxFFFE VDMA RGB Green value VDMA RGB B OxFFFF VDMA RGB Blue value NOTE These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 220 16 VDMA Undef Funes S3Fl1BG_USER S MANUAL_REV1 00 16 VDMA VDMA_CFG_0 Name Ress VDMA_BG_RGB VDMA_BG_SRC VDMA_DST_RGB R W VDMA background color components 000 YCbCr 001 RGB888 010 RGB565 RGB332 100 RGBA5551 1 bit alpha is ignored 101 RGBA4444 4 bit alpha is ignored 110 RGBO 0 0 0 Black background color VDMA RGB register VDMA background source memory 00 XRAM 01 801 10 Internal eFlash 11 External serial flash Set this field to XRAM if this field is not required for the operation VDMA background color components 00 RGB888 01 RGB565 10 RGB332 11 RGBA5551 VDMA destination memory 0 XRAM 1 1801 VDMA_CFG_1 1 Mam mw ____ VDMA_FG_RGB VDMA FG SRC SAMSUNG ELECTRONICS x Description Reset foreground color components 000 YCbCr 001 RGB888 010 RGB565 011 RGB332 100 RGBA5551 1 bit alpha blending is applied 101 RGBA4444 4 bit alpha blending
201. rface for RGB888 234 LCD Controller Top Block Diagram 242 LCD Controller Block 242 Voltage Dividing Internal Resistor Circuit 246 Voltage Dividing External Resistor Circuit Diagram 247 5 Signal in Static Mode n nnn enne 248 COM SEG Signal in 1 2 Duty and 1 2 Bias Mode 249 5 Signal in 1 3 Duty and 1 2 Bias 250 COM SEG Signal in 1 3 Duty and 1 3 Bias 251 COM SEG Signal in 1 4 Duty and 1 3 Bias Mode U 252 GPIO s l l li ee ee ee 256 Sector Mapping within the S3FI1BG embedded 277 Input Timing for External 285 Input Timing for PRRESET 2 2 Descente ped aoa iaa e E een ede pude added rana 285 LVR Low Voltage Reset Timing 288 80TQFP Package 290 SAMSUNG ELECTRONICS Um Table Number Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Tab
202. rmines where the BRAC raw data resides DATA_SRC R W 1 External serial FLASH data used for BRAC decoding 0 Internal embedded FLASH used for BRAC decoding SAMSUNG ELECTRONICS 114 er S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC BRAC_INT_EN 2 BRAC Interrupt Mask register __ Deer no 7 Rem IBB half empty interrupt enable register IBB_MASK 1 1 aw 1 Enable 0 Disable BRAC interrupt enable register BRAC MASK R W mask nw 1 Enable 0 Disable BRAC INT PEND 0xFF03 BRAC Interrupt Pending register en aw Den half empty interrupt pending register IBB_PEND 1 R W IBB half empty interrupt makes this bit 1 When this bit is set pending bit is cleared interrupt pending register BRAC_PEND R W BRAC interrupt makes this bit 1 When this bit is set pending bit is cleared BRAC START ADRL 0xFF04 BRAC START ADRM 0xFF05 BRAC START 0xFF06 BRAC START ADR 23 0 registers is increasing by 1 after starting BRAC decoding automatically Name sr mw _ STARTADRL The start address bit 7 0 for BRAC decoding Nm s ew Den STARTADRM The start address bit 15 8 for BRAC decoding s Been STARTADRH The start address bit 23 16 for BRAC decoding
203. rnal interrupt 0 5 IEADG 0 Disable ADC interrupt 1 Enable ADC interrupt IEBRAC 0 Disable BRAC interrupt 1 Enable interrupt 000 IEWDT RW 0 Disable Watch dog timer interrupt 1 Enable Watch dog timer interrupt IPO 0x93 Interrupt Priority 0 register IPO IP1 IP2 and IP3 contain information for interrupt priority Each IPx register value determines the priority of the corresponding interrupt source Default Priority IPWDT gt IPBRAC IPU1TX gt IPUSBEP4 ew 7 Rw o Lower pron level o 0 Lower priority eve 1 Higherprontylevel PSP AW o Lower priority level 1 Higherprontylevel 4 O Lower priority tever 1 Higher priory 3 AW o Lower riot level t Higherprontylevel 2 AW 0 Lower pnt evel 1 Higher rintylevel 1 O Lower priority tever 1 Higherprontylevel 0 Lower proriy tever 1 Higher prontylevel SAMSUNG ELECTRONICS 96 er S3Fl1BG_USER S MANUAL_REV1 00 5 INTERRUPT STRUCTURE IE1 0x94 Name et RW Deep Hexe s 7 Rw o DsableExemalntemmp2e Enable Aw Disable 1OLCD iterupt ____ 1 Enable 1010D 5 o Disable T Enable VOMAnterupt
204. ruction uses the 16 bit address format and the subroutine can be anywhere in the 64KB code memory space The ACALL instruction uses the 11 bit address format and the subroutine must be in the same 2KByte clock as the instruction following the ACALL Subroutines should end with a RET instruction which returns execution to the instruction following the CALL RETI is used to return from interrupt service routine The only difference between RET and RETI is that RETI tells the interrupt control system that the interrupt in progress is done Table 3 6 is Mnemonic and operand description of instructions related to the subroutine call Each function and effects on PSW are also described As shown in the table any instruction related subroutine call can not effects on PSW Table 3 6 Mnemonic and Operand of Instructions related to the Subroutine Call lt PSW Mnemonic amp Operand Operation amp Functions HEX AC FO RS OV PC PC 2 SP lt SP 1 11 31 SP PClow 51 71 ACALL add11 SP SP4 91 B1 SP PChigh D1 F1 PC100 lt addrll PC PC 3 SP lt SP 1 SP lt LCALL addr16 SP spt 12 SP PChigh PC100 lt 16 PChigh lt SP SP SP 1 RET PClow SP 22 SP SP 1 PChigh lt SP SP SP 1 RETI PClow _ SP 32 SP lt SP 1
205. rupt it will be continue to be interrupted every 3ms as long as there is no activity on the USB bus CPU USB R C 5 0 suspend interrupt 1 Suspend interrupt generated EndPoint N interrupt PENDing R G S For Bulk Endpoints The USB sets this bit under the following conditions IINRDY bit is cleared FIFO is flushed R C S OSTSTALL ISTSTALL is set ORDY bit is set USBEP3PEND USBEP2PEND USBEP1PEND SAMSUNG ELECTRONICS 196 For ISO Endpoints The USB sets this bit under the following conditions IUNDER bit is set IINRDY bit is cleared FIFO is flushed OSTSTALL ISTSTALL is set This conditions are mutually exclusive 0 No EP N Interrupt 1 EP N interrupt generated N 1 2 3 4 USBEP4PEND S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER EndPoint 0 interrupt PENDing This bit corresponds to endpoint 0 interrupt The USB sets this bit under the following conditions ORDY bit is set INRDY bit is cleared VSBEFOREND ads E STSTALL bit is set SETEND bit is set DEND bit is cleared Indicates End of control transfer 0 No EPO Interrupt 1 EPO interrupt generated USBINTEN 0xB4 mann 7 pepe p Revd a ERBEN ER a sceronren mw a rte usseranren 2 aw a rte CEREREM i Enabl USBEPOINTEN ndpoint 0 Interrupt Enable 0 Disable 1 Enable USBFN_L 0xB5 USBFN_H 0xB6 These registers maintain the Frame Nu
206. rupt Condition Not generate Interrupt Not generate Interrupt 1 1 1 ALMHOUR BCDHOUR ALMMIN BCDMIN ALMSEC BCDSEC 1 o ALMDATE BCDDATE BCDHOUR 0 BCDMIN 0 BCDSEC 0 o 1 ALMDATE BCDDATE ALMSEC BCDSEC ALMDATE BCDDATE ALMMIN BCDMIN BCDSEC 0 ALMDATE BCDDATE ALMMIN BCDMIN ALMSEC BCDSEC ALMDATE BCDDATE ALMHOUR BCDHOUR BCDMIN 0 BCDSEC 0 1 ALMDATE BCDDATE ALMHOUR BCDHOUR ALMSEC BCDSEC 0 ALMDATE BCDDATE ALMHOUR BCDHOUR ALMMIN BCDMIN BCDSEC 0 ALMDATE BCDDATE ALMHOUR BCDHOUR ALMMIN BCDMIN ALMSEC Ty 1 17 17 1 Alarm Interrupt Normal Operation STOP OSC Stabilization Time Update Time STOP Display Figure 15 2 Basic RTC operation SAMSUNG ELECTRONICS 210 er S3Fl1BG_USER S MANUAL_REV1 00 15 RTC 15 5 REGISTER DESCRIPTION SUMMARY Wane o w Dee NOTE These registers have to be accessed using MOVX instruction SAMSUNG ELECTRONICS 211 er S3Fl1BG_USER S MANUAL_REV1 00 15 RTC RTCCONO 0 80 RTC_CNTSEL RTC_CLKSEL and RTC_CLKRST bits are used for testing In normal operation these bits have to be cleared to 0 a Pw it no ___ n ee BCD count select RTC_CNTSEL 0 Merge BCD counters 1 Reserved Separate BCD counters BCD clock select RTC_CLKSEL 0 PXTI RTCCLK 1 215 divided clock 1Hz 1 RTC clock divider reset R
207. s Accumulator it is set or cleared SAMSUNG ELECTRONICS 62 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 3 7 LOGICAL INSTRUCTIONS The instructions that perform Boolean operations AND OR XOR NOT on bytes perform the operation on a bit by bit basis CLR clear CPL complement SWAP Rotate RL RLC RR RRC instructions manipulate the Accumulator The Rotate instructions shift the Accumulator 1 bit to the left or right For a left rotation the MSB rolls into the LSB position For a right rotation the LSB rolls into the MSB position The SWAP instruction interchanges the high and low nibbles within the Accumulator This is a useful operation in BCD manipulations Table 3 8 is Mnemonic and operand description of each logical instruction Each function and effects on PSW are also described The symbol means no effect to PSW the symbol lt gt means can effect to PSW SAMSUNG ELECTRONICS 63 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET Table 3 8 Mnemonic and Operand of Logical Instructions amp Operation amp Functions cy RS P ANL A imm A lt A amp imm 54 e ANL A lt A amp Ri 56 57 ANL A Rn A lt A amp Hn 58 lt gt ANL A Dir A A amp
208. s generated to the CPU When such a condition occurs the USB flushes the FIFO and invalidates CPU access to the FIFO When CPU access to the FIFO is invalidated this bit is cleared 0 Normal operation state 1 Setup end stage Data END The CPU sets this bit EPO DEND After loading the last packet of data into the FIFO at the same time INRDY is set While it clears ORDY after unloading the last packet of data SAMSUNG ELECTRONICS 198 er EPO_SVSET EPO_SVORDY EPO_SETEND S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER EPO_STSTALL For a zero length data phase when it clears ORDY and sets INRDY 0 Not dataend state 1 Dataend stage SenT STALL The USB sets this bit if a control transaction is ended due to a protocol violation An interrupt is generated when this bit is set 0 No stall token is transmitted 1 Control transaction is ended due to a protocol violation IN packet ReaDY The CPU sets this bit after writing a packet of data into endpoint 0 FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the 1 R S USB clears this bit so the CPU can load the next packet For a zero length data phase the CPU sets INRDY and DEND at the same time 0 Not yet loaded FIFO or in OUT mode 1 Loading packet to EP0 FIFO completed Out packet ReaD Y This bit a read only bit The USB sets this bit once a valid token is writ
209. s may need for the maximum throughput For the minimum memory usage only BUF01 BUFO and BUF1 is needed VLD engine sends the output to the BUF01 and then IDCT engine read the input from BUFO1 and send its output to BUFO SAMSUNG ELECTRONICS 127 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER Tables 1440 bytes LOOK_NBITS_DC 256 bytes LOOK_SYM_DC 256 bytes LOOK_NBITS_AC 256 bytes LOOK_SYM_AC 256 bytes HUFFVAL_AC 256 bytes BRJPEG Control Status QTABLE4x4 2 x 16 bytes Registers QTABLE8x8 2 x 64 bytes BUF01 or BUF23 8x64 x2 384 bytes 64 bytes Cr Y 64 bytes 64 bytes BUF2 BUF4 or BUF5 ms 3 x 64 x 1 192 bytes ytes Cr 128 bytes Figure 81 BRJPEG Decoder Decoding Scheme SAMSUNG ELECTRONICS 128 S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER XRAM Byte Addr Offset 3 2 116 1 0 312 5 417 6 IDCT Accumulator AOL BOL signed Up to 16 iteration 16x16 signed multiplier MUL16 XRAM Byte Addr Offset 3 16x16 signed multiplier Figure 8 2 IDCT engine operation for 16 MUL16 instructions SAMSUNG ELECTRONICS 129 er S3Fl1BG_USER S MANUAL_REV1 00 8 BRJPEG DECODER ADD16H XRAM Byt
210. sable LVD circuit orl PCON 02H nop nop nop Because the next instruction just after STOP mode entrance will also be executed the next instruction of STOP MUST be instruction Following operation will be executed before entering STOP mode LVD circuit should be disabled Mandatory LVD circuit will be automatically enabled when wakeup is generated except reset source and then LVD circuit checks the voltage level If voltage level is over VLVD STOP mode will be released If not LVD reset is generated If system is using the PLLCK for Fsource should change it to IMCLK or EMCLK before entering STOP mode Because PLLCLK will be stopped in STOP mode When any of external interrupts are used as Wakeup sources bits of registers EINTENO and EINTEN1 related to the external interrupts should be only enabled Otherwise it might cause unexpected system malfunction Disable JTAG function Optional Internal 3 3V LDO Power down Optional SAMSUNG ELECTRONICS 80 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER Disable USB PHY pull up Optional Disable Internal 32K sub oscillator Optional Disable External 32K sub oscillator Optional If system is using the EMCLK for make internal 16M main oscillator IMCLK disable to reduce current before entering STOP mode Optional If system is using the IMCLK for Fsource make external main oscillator EMCLK disable to re
211. specific alternative function defined by user P4 0xC0 Name et nw Deseo General Purpose I O 4 P4 7 0 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user P5 0x88 Name w espion General Purpose I O 5 P5 7 0 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user P6 0x98 mw General Purpose I O 6 7 0 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user SAMSUNG ELECTRONICS 262 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO P7 0xB8 R W Description Name Bit RW Descipion Reset General Purpose 7 P7 7 0 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user P8 0xE8 General Purpose I O 8 7 2 R W Each of these pins can be used as either any data transfer purpose or specific alternative function defined by user JTAGOFF 0xFE40 If this bit is 0 GP30 GP31 GP32 and GP33 are activated as JTAG PORT JTAGOFF R W independent of PSMODO Value 0 Enable JTAG Port 1 Disable JTAG Port EINTMODO 0xFE41 External interrupt mode register 0 When is set as interrupt pin its input go through noise filter by
212. ster this pin is an output When configured as slave this pin is an input GP87 GP57 SCSN SPI slave select When configured as master this pin is an output When configured as slave this pin is an input SAMSUNG ELECTRONICS 140 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI 9 4 BLOCK DIAGRAM Receive Buffer1 Receive Buffer Shift Register Port Control Logic CROSSBAR Transmit Buffer Transmit Buffer1 Fsvs Clock Control Generator Logic SPI Mode Register Figure 9 1 SPI Block Diagram SAMSUNG ELECTRONICS 141 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI 9 5 OPERATION The four signals used by SPI MOSI MISO SCK SCSN are described below Master Out Slave In MOSI The master out slave in MOSI signal is an output from a master device and an input to a slave device It is used to serially transfer data from the master to the slave This signal is an output when SPI is operating as a master and an input when SPI is operating as a slave Master in Slave Out MISO The master in slave out MISO signal is an output from a slave device and an input to the master device It is used to serially transfer data from the slave to the master This signal is an input when SPI is operating as a master and an outp
213. ta memory can use either MOVX DPTR or MOVX Ri SAMSUNG ELECTRONICS 29 S3Fl1BG_USER S MANUAL_REV1 00 2 MEMORY ORGANIZATION 2 3 Figure 2 4 consists of e 128 Bytes of I RAM accessible through direct or indirect addressing mode 0x00 Ox7F e Upper 128 Bytes of I RAM accessible through indirect addressing mode 0x80 OxFF and this area can be available as stack area e 128 Bytes of special function registers SFRs accessible through direct addressing mode 0x80 OxFF Although the SFRs and the upper 128 Bytes of I RAM share the same address range the actual address space is separate and is differentiated by the type of addressing Direct addressing accesses the SFHs indirect addressing accesses the upper 128 Bytes of I RAM The lowest 32 Bytes of the lower 128 Bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as RO through R7 Two bits in the PSW select which register bank are in use Accessible by indirect addressing only lt Available as stack space Accessible by direct addressing Only Upper 128 Bytes Accessible by direct and indirect addressing lt Available as stack space Lower 128 Bytes Bit Address HEX 70 7C 78 79 msi Register Bank Select PSW 4 3 Bit addressable 11 10 01 00 Figure 2 4 I RAM Memory Structure SAMSUN
214. ta should be concatenated The following program shows how to generate the PCM samples of sine table The byte order can be easily understood Sentence Index C Programming For i 0 i lt 0x2000 i 2 ddd unsigned short sin i 1 0 PI 16 0 0x7fff fprintf fp Yc ddd amp Oxff0 gt gt 4 ddd1 unsigned short sin i 1 1 0 PI 16 0 Ox7fff fprintf fp c ddd amp 0xf000 12 ddd180xf0 fprintf fp ddd1 amp 0xff00 gt gt 8 6 2 9 REDUCING THE TOTAL SIZE OF COMPRESSED DATA If the total size of compress data is larger than the allowed memory space then programmer should decrease its size Power Studio provides two kinds of scheme for this Resample the voice data into lower sampling frequency o Open Waveform gt Wave Re sampling gt Select Sampling Frequency Split the wave into several waves and remove the mute period between the waves Amplitude gt 24 Time sec Figure 6 2 The Playing Time of the Waveform As Figure 6 2 the playing time of the waveform is about 24 seconds and the total sum of mute period is over 8 7 seconds If the waveform is split into 6 waveforms A B C D E and F which are compressed separately and mute period is replaced with MUTE command then about 3696 of voice data can be reduced SAMSUNG ELECTRONICS 109 S3Fl1BG_USER S MANUAL_REV1 00 6 BRAC CODEC 6 2 10 VOLUME CONTROL The S3FI1BG has digital volume a
215. ten to the FIFO An interrupt is generated when the USB sets this bit The CPU clears this bit by writing a 1 to the SVORDY 0 Not received packet or in IN mode 1 Received packet from host EPO INRDY EPO ORDY USBEP1CSRO0 0xBA USBEP2CSRO 0xBE USBEP3CSRO 0xC3 USBEPACSRO 0xC7 cu uss 0 MAXP isn t overwritten when CPU writes any value to MAXPSET USBEPnCSRO register 1 MAXP is overwritten s4 Rem SOS MAXP size value If MAXP is 0000 then MAXP is 8 bytes If MAXP is 0001 then MAXP is 8 bytes If MAXP is 0010 then MAXP is 16 bytes If MAXP is 0011 then MAXP is 24 bytes If MAXP is 0100 then MAXP is 32 bytes MAXP R W If is 0101 then is 40 bytes If MAXP is 0110 then MAXP is 48 bytes If MAXP is 0111 then MAXP is 56 bytes If MAXP is 1000 then MAXP is 64 bytes NOTE 1 EPSCSRO and EPACSRO have up to 16 bytes NOTE 2 If a_i PSS SDD ot Eells ss D ooo want to use double buffering of EP1 you should set 0100b SAMSUNG ELECTRONICS 199 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER wd in this field You set 1000b in this field cannot use double buffering USBEP1CSR1 0xBB USBEP2CSR1 0xBF USBEP3CSR1 0 4 USBEP4CSR1 0xC8 Name sr cu uss no s Rem SSS In mode AuTo CLeaR This bit is valid only when endpoint N is set to IN If set whenever the CPU writes MAXP data in endpoint N FIFO IINRDY will automat
216. ter and a data transfer begins The SPI master immediately shifts out the data serially on the MOSI line while providing the serial clock on SCK During operating a next data don t have to be written into the SPIDATA If interrupts are enabled an interrupt request is generated at the end of transfer While the SPI master transfers data to a slave on the MOSI line the SPI slave device simultaneously transfers the contents of its shift register to the SPI master on the MISO line in a full duplex operation Therefore the interrupt serves as both a transmit complete and receive data ready Slave Mode Operation When SPI is enabled and not configured as a master it will operate as a SPI salve As a slave byte are shifted in through the MOSI pin and out through the MISO pin by a master device controlling the SCK signal A bit counter in the SPI logic counts SCK edges When 8 bits have been shifted through the shift register operation is finished A slave device cannot initiate transfers Data to be transferred to the master device should be pre loaded into shift register by writing a data to SPIDATA SAMSUNG ELECTRONICS 142 er S3Fl1BG_USER S MANUAL_REV1 00 9 SPI Master Device Figure 9 2 3 Wire Master Slave Interconnection Master Slave Device Device Figure 9 3 4 Wire Master Slave Interconnection SAMSUNG ELECTRONICS 143 er S3FI1BG_USER S MANUAL REV1 00 9 SPI
217. the timing of the instructions is different in terms of the number of clocks per instruction cycles and timing within the instruction cycle SAMSUNG ELECTRONICS 49 er S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET 3 1 REGISTER DESCRIPTION FOR CPU Summary add w Desn s or nmw smgse SP 0x81 R W Description Name RW Description Reset SP 7 0 R W Stack Pointer On PUSH CALL before Increment on POP RET after Decrement Available only by internal 256 bytes SRAM I RAM The SP is initialized to 07H after a reset This means the internal data addressed after 08H is used as stack DPOL 0x82 Besrpion Lower of Data Pointer 0 Brae If DPSEL 0 this register is available DPOH 0x83 Name Higher of Data Pointer 0 If DPSEL 0 this register is available DP1L 0x84 R W Description Name RW Description Lower Byte of Data Pointer 1 uias If DPSEL 1 this register is available SAMSUNG ELECTRONICS 50 Um S3Fl1BG_USER S MANUAL_REV1 00 3 INSTRUCTION SET DP1H 0x85 R W Description Name RW Description Higher Byte of Data Pointer 1 If DPSEL 1 this register is available DPSEL 0x86 et z mesa
218. tion In general the entering conditions CMD are set to PCON register by CPU Normal General Clock Gating Mode Reset Reset External Int Internal External Int RTC Wakeup WDT Wakeup USB Wakeup IDLE STOP Figure 4 10 Power down mode State Diagram General Clock Gating Mode Normal Mode In General Clock Gating mode both On and OFF of clock gating of the individual clock source of each block are performed by controlling each corresponding clock source enable bit of CLK_ENO and CLK_EN1 registers The Clock Gating is applied instantly whenever the corresponding bit or bits is changed SAMSUNG ELECTRONICS 78 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER IDLE Mode In IDLE mode clock to CPU is in stop Idle mode is invoked when the IDLE Mode bit of PCON is set to 1 In IDLE mode CPU operations are halted while some peripherals remain active During IDLE mode the internal clock is gated away from the CPU but all peripherals remain active There are two ways to release IDLE mode Execute a reset All system and peripheral control registers except RTC block are reset to their default values If interrupts are masked a reset is the only way to release IDLE mode Activate any enabled interrupt causing IDLE mode to be released How to Enter IDLE mode orl PCON 01H nop nop nop Because the next instruction just after IDLE mode entrance will also be executed the next ins
219. tive function defined by the PSMODO and PSMOD 1 registers 8 Bit CMOS tri state I O port 2mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the PAMODO and PAMOD 1 registers 8 Bit CMOS tri state I O port 2mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the and P5MOD1 registers 8 Bit CMOS tri state I O port 2 4mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the PEMODO and PeMOD registers 8 Bit CMOS tri state I O port 2mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the P7MODO and P7MOD1 registers 6 Bit CMOS tri state I O port 4mA output driving current capability Each bit can be set individually as either any data transfer purpose or specific alternative function defined by the and P8MOD1 registers GP50 GP57 GP60 GP66 GP70 GP77 GP82 GP87 POWER Digital Power 2 2 V 5 5V VDDi VDD2 P sia Connected to GND through 1uF capacitor u gt rn P PowerforUSBPHY AVDAG P Analog Power Supply For DAG Connected to PVSGOUT CS VSS1 VSS2 Digital Ground
220. to the segment signal pins automatically without program control LCD RAM ADDRESS AREA RAM addresses FF3FH are used as LCD data memory When the bit value of a display segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG31 using direct memory access DMA method that is synchronized with the signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use Table 18 2 4COM x 32SEG Display Memory Organization etuer eene cows como cows cow como secicone secrcone see1com secicow sesocows secocow sesocowo scoscov seascowa sececow sececow sesacowo stcrcous secrcow sesecowo stcacous sesecowe secocom stcacou sececow sesecowo secricows sesmicoue secricomt sercowo secrecont sesracon sec1ecovo
221. truction SAMSUNG ELECTRONICS 123 er S3Fl1BG_USER S MANUAL_REV1 00 7 SERIAL FLASH CONTROLLER SFCTRL 20 This register is only for CPU mode en aw Deep When it is set to 1 BSPI read operation starts This bit is cleared automatically just after writing W SPI chip select signal When both this bit and SF_BUSY bit are 0 DESEE external CSN pin goes to 0 l SF BUSY It 5 flag that BSPI operation is running 0 idle 1 busy SFPORT 21 This register is only for CPU mode Name Besrpio Write MSB in this register goes out through BSPI MOSI port firstly SF PORT 7 0 RW Read The value is inputted through BSPI MISO MSB firstly SFDMA CTRL 22 np 0 BRDMA automatically stores serial flash data to 1 XRAM is NOT written by BRDMA SFDMA_AUTO_INC 1 BRDMA_START_ADR is automatically incremented SFDMA_EN W BRDMA starts when this bit is set And this bit is cleared when DMA transfer operation is done SFDMA_START_ADRL 0xFF23 SFDMA_START_ADRM 0xFF24 SFDMA_START_ADRH 0xFF25 Name T ADDR_L BRDMA Start Address Undef Wane an aw O ADDR_M BRDMA Start Address Undef SAMSUNG ELECTRONICS 124 er S3Fl1BG_USER S MANUAL_REV1 00 7 SERIAL FLASH CONTROLLER
222. truction of IDLE MUST be instruction SAMSUNG ELECTRONICS 79 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER STOP Mode STOP mode is invoked when the STOP Mode bit of PCON is set to 1 In STOP mode the operation of the CPU and all peripherals except RTC and WDT If WAKEEN bit is set to 1 for using wakeup feature are halted That is the external main oscillator and internal 16MHz main oscillator are stopped Stopping oscillator circuit is optional for the necessary of faster oscillation stabilization time See MAIN OSCEN STOP and INT MOSCEN STOP bits in SYSCFG register The supply current is reduced External sub oscillator and internal 32KHz sub oscillator are configurable The clock supply to Fsource is disconnected in entry of STOP mode and connected in exit of STOP mode All system functions stop when the clock freezes but data stored in the internal register file is retained Table 4 1 status on Normal and STOP mode External Main Oscillator Configurable MAIN OSC DIS bit Configurable MAIN OSCEN STOP EMCLK of SYSCFG register bit of SYSCFG register Internal 16MHz Main Oscillator Configurable INT 5 DIS bit of Configurable INT MOSCEN STOP IMCLK SYSCFG register bit of SYSCFG register PLL Configurable PLL EN bit of STOP PLLCLK PLLCONO register ADC Configurable STOP DAC Configurable STOP USB Configurable Enter SUSPEND mode How to Enter STOP mode ani IVCONO 0FEH di
223. ture In USB core of the S3FI1BG logical endpoint capability allows a number of physical endpoints in the device to support a larger number of data pipes at logical endpoints requested by a host This is done by re assigning physical endpoints to support the logical endpoint requested by the host SAMSUNG ELECTRONICS 192 er S3Fl1BG_USER S MANUAL_REV1 00 14 USB CONTROLLER 14 6 REGISTER DESCRIPTION SUMMARY me u Rw Been Resa user oer US amp fumtonAddessRedsee foo 082 USBPowerManagemenregse oo USBPEND oes oo 0 Enable Register ussen i ussHamemmbermegsert oo user a USB Fame Number Register oo 0x87 Common Saus Regsero ussPoosm 0289 USB EPO Common Status Register oo UsBEFTCommonsmusRegsro ussEPrCommonsmusRegsr usseosma USB EPt Common Status Register 0x00 web USB Common Regsters 0x00 ussEPecsmo wee USB 2 Common ussEPzosm ner EP2 Common USB EP2 Common Status Register cz USB EP2 Com
224. ue TnDATA is then reloaded to the TnCNT and the timer continues decrement of its TnCNT unless each timer disable If timer is disabled you can write a new base value into its register during decrement of its PWM Mode The interrupt is generated by MATEN and OVFEN TnOUT goes to high at starting of counter and then TnOUT goes to low when is equal to In PWM mode the timer pulse continues to toggle whenever timer count value is same as the PWM data register and the timer pulse return to initial value whenever a time out occurs The PWM pulse is output directly at the TnOUT Using PWM mode you can achieve a flexible timer clock range which flexible duty TnDATA PDRn 33 REBEL Memes TnOUT i Interupt is Interupt is T issued issued Figure 11 2 Example of Timer Operation in PWM Mode SAMSUNG ELECTRONICS 166 er S3Fl1BG_USER S MANUAL_REV1 00 11 TIMERS Interval Mode In Interval Mode timer continues to toggle whenever a timer reference register TnDAT value is same as a timer count register TnCNT An interrupt request is generated whenever the level of the timer output signal is inverted that is when the level toggles In Interval Mode a timer generates one shot pulse of timer clock duration whenever a time out occurs This pulse generates a time out interrupt that directly output at the timer s configured output T
225. uit detects VDD below VLVD reset is generated The internal oscillator stabilization time is 2ms LVDRST Internal Oscillator Stabilization time about 2 ms 16MHz lt IMCLK Internal Reset Fsvs _ JL JL JU Figure 4 3 LVD RESET Sequence SAMSUNG ELECTRONICS 71 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER Software RESET Software can initialize the device state itself when it writes OxB to RSTCON register SW Reset Write OxB Internal Reset 6 5 times Fsys Figure 4 4 Software RESET Timing Watchdog RESET Watchdog reset is invoked timer overflows under the condition that both watchdog timer and reset are enabled Fsys Watch dog Reset Internal Reset 6 5 times Fsvs Figure 4 5 Watchdog RESET Timing SAMSUNG ELECTRONICS 72 er S3Fl1BG_USER S MANUAL_REV1 00 4 SYSTEM CONTROLLER 4 3 2 CLOCK MANAGEMENT Figure 4 6 show a block diagram of the clock architecture The main clock source comes from an external oscillator an internal 16M main oscillator clock IMCLK PLL output clock PLLCLK an external sub oscillator ESCLK or an internal 32K sub oscillator clock ISCLK The RTC working clock is generated by PXTI RTCCLK The frequency is 32 768KHz CLKCON 2 0 CPU RAM Interrupt PXI 12MHz EMCLK DIVIDER a n GPIO PLL PLLCLK FsouncE 2 gt e Max 48MHz 4 8 Peripheral x Software
226. upts PnRESET Figure 21 2 Input Timing for PRRESET SAMSUNG ELECTRONICS 285 er S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA Table 21 4 Input Output Capacitance TA 40 to 85 C 0 V Parameter Symbol Gonaitions min Input capacitance 1 MHz unmeasured pins are 10 pF Output capacitance COUT returned to Vas capacitance Table 21 5 A D Converter Electrical Characteristics TA 40 C to 85 C Vpp 2 7 V to 4 2V Offset error of bottom Conversion time 1 Analog block current 2 Vpp 3 3V 05 15 mA When power down mode NOTE 1 Conversion time is the time required from the moment a conversion operation starts until it ends NOTE 2 is an operation current during A D converter SAMSUNG ELECTRONICS 286 er S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA Table 21 6 D A Converter Electrical Characteristics TA 40 to 85 3 0 V to 3 6 V SAMSUNG ELECTRONICS 287 er S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA Table 21 7 Internal Oscillator Characteristics TA 40 to 85 Vpp 2 2 V to 4 2 V Oscillator IMCLK Frequency Internal Sub ISEREQ Vpp 25 C Oscillator ISCLK Frequency Table 21 8 Low Voltage Reset Electrical Characteristics TA 40 to 85 2 Typ Max usi s 5 0 0 Voltage of BLD Veo IVCONO BLD SEL 2000 IVCONO BLD S
227. using EINTxCON bit and generates interrupt If it is set as normal general I O port noise filter does not affect data flow ek aw mw 7 aw External interrupt request input for GP71 6 0 filtering off 1 filtering on EINT1CON 4 R 59 M 5 4 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection mw External interrupt request 70 2 0 filtering off 1 filtering on EINT N R 226 P gt 1 0 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection SAMSUNG ELECTRONICS 263 er S3Fl1BG_USER S MANUAL_REV1 00 19 GENERAL PURPOSE I O GPIO EINTMOD1 0xFE42 eR Deep mw __ 7 nw Rmewd External interrupt request input for GP83 and GP14 6 0 filtering off 1 filtering on R EINTA 64 my 5 4 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection mw o awase 2 27 External interrupt request input for GP72 and GP82 2 0 filtering off 1 filtering on R Elle 1 0 00 Reserved never used 01 rising edge detection 10 falling edge detection 11 both edge detection EINTMOD2 0xFE43 External interrupt request input for GP35 6 0 filtering off 1 filtering on R
228. ut when SPI is operation as a slave Serial Clock SCK The serial clock 5 signal is an output from a master device and an input to a slave device It is used to synchronize the transfer of data between the master and the slave on the MOSI and MISO lines SPI generates this signal when operating as a master In slave mode SPI receive this signal from a master The SCKPHA and SCKPOL in SPIMOD register and the CKSEL in SPICK control the shape and rate of SCK The CKSEL provide several possible clock rates when the SPI is in master mode In slave mode the SPI will operate at the rate of the incoming SCK as long as it does not exceed the maximum bit rate There are also four possible combinations of SCK phase and polarity with respect to the serial data The SPI data transfer formats are shown in Figure 9 4 To prevent glitches on SCK from disrupting the interface SCKPHA SCKPOL and CKSEL should be set up before the interface is enabled Slave Select SCSN The slave select SCSN signal is an output from a master device and an input to a slave device It is used when the SSMD bit in SPIMOD is set to logic 1 Master Mode Operation A SPI master device initiates all data transfers on a SPI bus SPI is placed in master mode by clearing the SLVEN bit in SPIMOD register Writing a byte of data to the SPI data register SPIDATA when in master mode writes to the transmit buffer The byte in the transmit buffer is immediately moved to the shift regis
229. x18000 Ox1FFFF Bit 4 0x20000 0x27FFF Bit 5 0x28000 Ox2FFFF Bit 6 0x30000 0x37FFF Bit 7 0x38000 Ox3FFFF FCON WP H 9 mw Besrpio svo ra Flash Program Erase Protection Low Register Each bit protect 32KB blocks of internal flash WP H 3 0 R W Bit 0 0x40000 Ox47FFF Bit 1 0x48000 Ox4FFFF Bit 2 0x50000 0x57FFF Bit 0 58000 OxSFFFF SAMSUNG ELECTRONICS 281 er S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA 2 1 ELECTRICAL DATA Table 21 1 Absolute Maximum Ratings TA 25 C Input voltage Ports 0 8 0 3 to VDD 0 3 Output current high ALL pins active 6 One pin active 30 Peak Value Output current low w wass pin current for ports 100 Peak Value Table 21 2 Electrical Characteristics TA 40 to 85 Vpp 2 2 V to 4 2 V Operating Vpp PXI 4 12MHz PXTI 32 768KHz 2 2 4 2 V Voltage 24MHz Using PLL Input high input pins except for V 0 8Vpp 8Vpp voltage Vio PXTI Input low Vict All input pins except for Vj 2 K voltage Output high Vout Vpp 3 3V lou 2 mA 1 0 voltage PGP0 PGP4 PGP5 PGP6 6 4 PGP7 PGP1 PGP3 PGP6 3 0 PGP8 Output low Vori Vpp 3 3V lo 2 2 mA voltage PGP4 PGP5 PGP6 6 4 PGP7 SAMSUNG ELECTRONICS 282 S3Fl1BG_USER S MANUAL_REV1 00 21 ELECTRICAL DATA c c

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