EE/CS 52 Digital Oscilloscope Documentation
Contents
1. Project oscilloscope requesting that the FIFO latch in data from the SAMPIE DATA output using its SAMPLE REO line lock divider og dk in aka ouput SAMPLE GLK System clock 20MH2 Ipm Ipm constant scale factor 31 0 k odun pm dio ip combine 16 18 le facto 31 0 SETTING Dette m detal15 0 Ipm constant3 Jon wise ug D n Value to be used for the selected setting 1 he as ol DH LOGICAL M shi shine Create a sample clock based on the selected SETTING SELECTORQ 0 eur sampling rate Sample rate input ltplier of a 100 Index of the setting to be altered Latch in sample rate Put the sample rate clock divider value period not the S ns period of our 20MHz in the low 18 bits of the clock divider input system clock It must therefore be multiplied by 2 Ipm om L Ipm decodet men eat clock as ol eq2 enable data 2 0 203 inst eqaj Delay unii the specified number of Jon cishifti Latch in trigger delay sample clocks have passed gal dafal7 0 resul 7 0 pa 1 Set sample rate i m distance Ipm dri2 RE u ter 2 Set trigger delay em constan p e pm counter 3 Set trigger level om ins gja PR a sor id 4 Set trigger slo S 7 0 clock d2. 2 3 4 5 6 VEE 12V VDD 56V TT TT Display Connectoy AS Ej Header 102A DN 3 alalal YSCL LP S 7 5 N 2 Top Right of the Adapter Board ECL AEG E 2 GND s VCC5 o 1034 2 DS 5 5 a DS E 8 1037 Start Frame DI LCD Sense 3 RIO 10113 E A 1038 10115 E OR Display Enable x 43 Ohm Ven amp 8 1041 Drive Signal FR 10117 2 Garage lt KE LAT Y Shift Clock n n z E NCS Row 1012 9 e NC6 Gi 10123 d GND 10134 a 1044 ul0162 5 1045 10135 5 E 1046 10139 a 1049 toa Dm 10140 a 8 1050 x ae 2 1014 8 8 Keypad Conn I zna Column 2 Data amp 1051 1 Header 10X2A SRS Cdum3baa 3 10151 5 E NC7 5 10152 NC8 10155 E GND 10159 2 E Ap 4 50 APERJS gt PE E mons 4 GND 3 7 de T 512k 8 Bit ROM E E Zen i gt 1058 AT i A0 S name USDIRI E S 1059 4 Al DATA7 B ea AZ RF Keypad Conn2 E sal 2 2 A3 9 Header 10X2A 5 1061 Dp Row 0 DATAO m a 1062 at Sl A4 SENESE en DATAS E 6 1063 2 AS PB m DATA4 5 E 6 13 DO y a B 8 1065 AT Zei DQl EE DATA3 A 1066 Ax Xu 2 Y J 10164 GND A8 DQ3 10165 A9 26 d Row 3 5 a 1067 si ATO 53 A9 DO4 P DB GND s 1068 Hi aS 3 AIO DQS KEYPAD4X4 10166 1069 ker ATO q 11 DQ6 10167 8 1070 L P ayar s i A2 007 DATA2 8 1071 1315 AAA Si Al3 DOS Keypad debouncing is done in the FPGA 10170 s 7 55 A V A15 ER R6
3. NIOS e ER Il se OY 01 4 NB HS Se an Ne gt co So se O v v x ER DECH OY OT B 0 So ve Se Ne 18 DER 20 als 22 25 2 nWBWE architecture Moore machine of vram controller lut is constant IDLE integer range 0 to 23 VRAM Read Cycle States constant READ ONE integer range 0 to 23 constant READ TWO integer range 0 to 23 constant READ THREE integer range 0 to 23 constant READ FOUR integer range 0 to 23 constant READ FIVE integer range 0 to 23 constant READ SIX integer range 0 to 23 VRAM Write Cycle States constant WRITE ONE integer range 0 to 23 constant WRITE TWO integer range 0 to 23 constant WRITE THREE integer range 0 to 23 constant WRITE FOUR integer range 0 to 23 constant WRITE FIVE integer range 0 to 23 constant WRITE SIX integer range 0 to 23 VRAM Refresh Cycle States constant REFRESH ONE integer range to 23 constant REFRESH TWO integer range 0 to 23 constant REFRESH THREE integer range 0 to 23 constant REFRESH FOUR integer range 0 to 23 constant REFRESH FIVE integer range 0 to 23 VRAM Data Transfer Cycle States constant DTRAN ONE integer range 0 to 23 constant DTRAN TWO integer range 0 to 23 constant DTRAN THREE integer range 0 to 23 constant DTRAN FOUR integer range 0 to 23 constant DTRAN FIVE integer range 0 to 23 constant DTRAN SIX integer range 0 to 23 L T for control line ouputs
4. TTT WedP s H DS V 98 O ZHINEEEEEE E gt 1 ne a m 1 3oua Huaj le 4 H a 4 9 4 o IWM LL ELT o7z sseuppy EFT pe 1 LLL lento 008 d q svo 44 Noch 4 ven EI KE o E a a e PEA a SEE GE PORGE II L T ES RER D e E UE I p E E E PEE a e suoos 5405 suoov SUOSE SUQOE suose SUQOZ suos SUOOL 5405 suo O ZHINOZ 419 obra ejeg NYNA SALON 00S 009 0S 071 001 022 OLL 02 OL 0c 0S 001 001 0 0S 9 69 991 XVIN NIIN jeubis wey e qissruueg aun ploy ejep asjnd yoje7 sun dm s ejep asind ug aun ploy YET bulu YET UPIM 1 esind YET UPIM Hu esind UNE aun dm s y90 9 lqeuz euin Y90 9 ajqeua euin ploy aun dm s gep lqeuq UIPIM Tu 49019 ejqeu3 UIPIM H 19019 ejqeu3 euin ploy geq aun dm s UIPIM Tu 49019 HUS UPIM Hu 9019 HUS e oKo 420 IUS NOILdI49S3d NOILINI43d TIM HIM 219 TOSINAS 40811 2 obed OSL 0z indino ajqeua dd SALON XVIN NIN NOlLdiHOS343 NOILINIJ3Q 108NAS penunuoo 40811 oDeg SALON 011 06 00S 009 gel 0 02 Ove OLL 007 081 081 007 XVIN NIIN p ull p eq o peuyep eq o p ull p eq p ull p q o p ull p eq o p ull p eq o
5. Eer valid keys L ERA E E E A A E ESE A A R ERARIALI PE Description i Constant table of valid keypress values terminated by KEY_ILLEGAL TFEPEPTEBEERERFERBERE REPELER TETRE ro oo y r o o oo yo o o o ro r o ESE o o To PRE PEPPE valid keys word KEY UP word KEY DOWN word KEY LEFT word KEY RIGHT word KEY MENU word KEY ILLEGAL F K EY ILLEGAL Terminates the list of valid keys Page 4 display s Pb P EL EE ARE EE RH O A A E R ES ES SET ESET E rr K E A A ET ESET Pg rry ET O A r KSC OA CET A ror EE Z File display s Description r Routines to set individual pixels on the LCD and clear th ntire LCD i input None Output Pixels displayed on LCD Known Bugs None Revision History 11 04 08 Julian Panetta Initial Revision LEER ETR L RAI ET ITA TIA K TRIA TA TIT RTTA A ET III T TAG TIA TA PET TIE TOT RT FI RA PIII TT ER EE EE include excalibur s include constants s text global plot pixel global clear display ARRA AA AGA ARRA TT TT T TT T TIT TT T TT T TT TT TT T TT TT TT TT TT TT T TT TT void plot pixel unsigned int x unsigned int y int p PTTTTTTTTTT TT TT ETT TIT TT T TT TT TT EE TIT TIT Description Sets the pixel at the passed x y to the value p H The origin of the screen coordinate system is the upper left corner Operation Computes the VRAM address of t
6. UcoEj femea olumio spike NS koumo UIDRI NS JGetumnvo UTR feno BOO uoe N olumio 07082 Ni mi URL mio S Umi N31 mo UP Ns Rowo 08082 PN30 m USDRI N32 P UR PNS colui USO PN33 0 Raro 0 09082 fensa colui 0 Ult Nia Rovito mee Nis colui 1 dil N71 olumio edu iN ur 0 bd N73 bd PN umo daria NS olmio aars ua column 1 adar 6 NS ea PN columniito 0 daria fenos olmio ed PN TC adar 20 PNG bd NS column 0 adar 22 N38 JCetumnvvo adar 23 NS umo 0 adria N10 JGetumnvo bd iN 10 column 1 adaro N10 JGetumnvo aaan NN 1 Colum 1 adare Pino JCetumnvo datato fen se umo 0 Hat N59 JGetumn vo Haa ua omno Hate ener Columio Haa N62 omno 0 datats N63 datato PINS5 colui 1 Digital Oscilloscope APEX20K Pin Assignments Has us TI
7. enable qn VM 15 0 datab 15 0 KS xi 15 0 Trigger level is 7 bit while the ADC output is 8 bit Multiply B kai hb 45 0 lowf7 0 level by 2 to distribute levels 2 PE qm ve H highf7 01 evenly throughout 8 bit domain Ipm compare Latch in trigger level insti onen El compara ins 8 Ipm dif4 5 18 w dataa 7 0 s DFF pm lt Only reset trigger delay counter on g Stop sampling after 640 samples are taken sid x unsigned compare E mmm databil 0 first trigger event since reset S until reset occurs regardless of new trigger events q dataal7 0 aeb ipm compare10 wian Zero lt gt Slope datab 7 0 Glen George s trigger compare pm T pm invo Ser ED a triggerlevel Lap state machine Triggers L data ADC DATAJT 0 pu xu ES b signal level 0 signal lt trigger on a specified slope event TL lom constante dataalt8 0 oy clock 2 Incoming data from the ADC Latch in trigger slope bn le s scoptig explicit s ge datab 15 0 Texas Instruments TLC5510 ADC SE m Ll ne H returns 255 for the lowest voltage and ish pl 3 KS O for the highest so input must be inverted Ipm dits nr Ipm constant3 L S Pen cureur SAMPLE REO ANALOG RESET INEUT b Ve al I L Rest clock mee m Signal to reset the triggering mechanism inst enable 5 and all the counters use for delay sampling P In Reset 07 Don t Reset Trigger sets has trigger until it is cleared by ANALOG RESET Must be on the kame
8. p ull p q o p ull p eq o pauyap eq o p ull p eq o eq o p ull p eq NOILdI49S3d euin ejep ndino geq jeubis a WEI ejqissiuueg euin ploy US 8320 Guru us ejeq euin ploy ejeg aun dm s geq OWA Ta 49019 HUS Sun H 19019 PUS euin 91149 yoop PUS UPIM 1 esind YET UPIM H esind yaje7 eun e oKo sind yojej NOILINI43d l n HOM 349 TIM HLM TAQ TOSINAS 0611 9Bed upy Buo7 q21don sequomasiuupyysBuies pue sjueunoo 2 L UI l m dilli eser BRE TTT oc led m r 1 O ZHINE 129 d O 103 HH Wl il 1VYl10SAd1 P s rb b i O H4 NANA g O ZHINOZ vo M ie 5400 EI suo 427 lupy pesi Wvys suelberg Buu smopuim uio4idopisequoesiuuupysBuies pue sjueuinoo 2 yua wanba ejep O osi eieq HO Wy o au o so 0 SS pe y e1eq ZA ZN ZX ZX Z AE ZA Zo ZHINOZ 119 O JEI EE JJ II SUOOE SUOGC 54002 SUOST SUOOT SUQG sdo SUQG T 3624 NVUS upr aum NVHS SUBIBBIG Buiu ysmopuim woy doy saguoensiuupy sbunas pue sjueuin2o q 2 M N h 9 0o o trs wea 3M NF o 30 SFX so H oo K A SY NJ Oo ME MP A SUOZI SUOOT su08 5409 SUOY 5402 suo 5402 T 96ed SHIM INVHS up peay WOY swebeig Buiu smopuim woudopsagvojensruupysBunss pue sjueunoo q 2 NX aa
9. ADD 10 5411 Add in the column portion of the nibble offset MOVI 12 3 AND 10 12 get the x offset within that nibble BGEN 511 7 set the leftmost pixel enable bit LSR 11 i0 Shift the pixel enable bit into the x location within the write mask If the color p is PIXEL WHITE set all the bits in the graphics nibble to 0 to clear the pixel Otherwise set all the bits in the graphics nibble to 1 blacken the pixel Assuming the PIXEL WHITE value is 0 and the PIXEL BLACK value is 0x0F p can simbly be ORed into the data byte OR 11 532 FILL8 rO 11 Fill all bytes of this word with the computed graphics byte so ST8D will read it in all cases ST8D 10 r0 RESTRET PROP RET TR A EME A R gg OA A A A A 7777577277 7 RP PE K A L OA K A P OA A A K O A A o K P 0 PE void clear display void FER D Operation ZPA T R RO 77 R RI RE 7 T ELS PI SLL RE PIAF 7 AR LS KEL ELE SSL R AO P A R A P A R A O A FA K A R AO OP A RA K A R EF sscription Sets all the LCD pixels to white Iterates over the portions of VRAM mapped to pixels on the LCD and paints them all white 16 pixels 4 nibbles at a time Arguments None Return Values None Fo utputs All pixels on the LCD are painted white All bits in VRAM that are displayed on the LCD are set to Registers Destroyed None d 2 4 e
10. R7 RS R S 1073 f A15 DATAI s 1074 Lil S 2 1 16 10174 a 3 SD Ar 5 RE 4 6K 4 6K 4 6K 4 6K F a 3 IN77 4 AI8 lo USDIR2 P 2 GND Pull columns low when no key is pressed USOE2 5 INSI FO CE CLKUSR GND J OE RDYnBSY 8 nSTATUS Se INITDONE GND gt WE INISI ENDE Am29F040 120 2 GND RON IN184 1089 2 nCEO 1090 A TRST 3 1091 AT 10188 1092 3 10190 E 1093 E 5 A0 10191 E 1094 Al SC WB WE 10192 E 2 5 S ione ALD A z do Only one VRAM chip is used so SOE is lw a S 8 El 1097 A Zi AN SOE 10194 i amp GND e AS Zei A4 CAS 10195 E E 1098 A Am 7 AS RAS 10196 2 3 1099 AM AT Ze A6 GND E 10100 215 AS A AT 10197 a p 10101 Als AS A A8 A6 10198 3 8 10102 AU A Ste A9 AS 10200 3 10103 Ais AT 37 AIO A4 10201 s 10104 A TA A3 10202 a 10106 di z AR A2 10203 R 5 ATI T AB Al 10204 5 1 2 Al4 10205 se GND es2 Res2 VCC33 z CLKI 10K 10K QE VCC33 E oe Di 5 20 DEET gt Bo cs SD GND xos LOOK 15 conma 2 043 W2457A SRAM zr S 3 xrpo HA NC3 5 TMS L 1022 a TCK 1021 5 4 UB TDI TA M 142406 1020 x xTDI 5 3 1019 dyp 9 psam Dy 1017 2 E DI 4 TX1 UIA TIIN WS rop of A GND 4 nRS L o 3 145406 4 NC2 s ncs lat Reset Circuitry vec OF RY Rx Ex NCI EM Drm 77 44 wn vec 2 2 DA RX2 7 a DEVCLRn fiji Kam 1014 E 5 406 2 L MR Woo 1 U2A Io S CLK Log 4 RST T ot 109 x 5 TRI IS PFI RST o ioc ES
11. demonstration trace Page 3 Julian Panetta EE CS 52 Page 1 TA Gabe Cohn Digital Oscilloscope Functional Specification Description The system is an interactive digital oscilloscope displaying on a 640 x 200 LCD panel The signal is input via an analog line in which runs through an analog to digital converter There is a keypad to change the operation parameters The system must be connected to a computer to program the FPGA but can be disconnected once booted Inputs Input is received through a keypad a serial connection and an analog input signal Input Name Input Type Description Keypad 4 4 Array of 16 Of the 16 keys only 5 are used by the OS keys 0000 62 bat 08900 OOOO Serial RS 232 Port Allows communication with the NIOS using GERMS Downloading of sample data to the oscilloscope from the computer is not yet implemented Analog Analog Line In Analog signal line whose voltage variation with time the scope measures This portion of the oscilloscope is not yet implemented Outputs Output is implemented with a display a serial connection and a LED Output Name Output Type Description Display LCD Panel A 640 x 200 graphics panel used to display the analog input and to present an operation and configuration menu to the user Serial RS 232 Port Allows sampled data to be uploaded to a Julian Panetta TA Gabe Cohn EE CS 52 Page 2 computer v
12. gt nRAS 1 gt AGAS type TABLE is array 0 to 23 of std logic vector 4 downto 0 constant OUTPUT BITS TABLE IDLE control 1317131 READ control IITIDT 0124 line values line values 11110 10100 ODIQQOW 11111 Page 2 3 gt nbTOE 4 gt vram controller lut vhd WRITE control line values s11011 11010 110107 11000 321000 III REFRESH control line values VALI MPT 131009 111007 11111 DTRAN control line values MD PDM 10100 11100 LLUMIN signal CurrentState integer range 0 to 23 current state signal NextState integer range 0 to 23 next state begin Compute the next state function of current state and inputs using concurrent statements NextState Transitions to TDLE IDLE when nRS 0 else IDLE when CurrentState READ SIX or CurrentState WRITE SIX or CurrentState REFRESH FIVE or CurrentState DTRAN SIX Idle State transitions else READ ONE when CurrentState IDLE and nRD 0 and DT SOON 0 and nCS 0 else WRITE ONE when CurrentState IDLE and nWR 0 and DT SOON 0 and nCS else REFRESH ONE when CurrentState IDLE and nCS 1 and DT
13. Framing Error Parity Error Break Error and Serial Error are displayed respectively A FFT may be implemented in the future for data analysis purposes Currently no FFT is used A look up table is used to validate the user s keypresses A circular queue will be used to buffer serial input in case bytes are received faster than the NIOS can respond A FIFO will also be used to buffer the signal input from the analog to digital converter analog control block There is currently no analog or serial input Clock Logic Reset Logic EE CS 52 Digital Oscilloscope Block Diagram FPGA eee Address Data oo y NIOS CPU E 1 Data mu 610 D Chip Select Logic 2 E T m SRAM ROM Interrupt Controller VRAM LCD H T Bl Debouncer Controller U VRAM LCD o FIFO Buffers HN
14. DIOU uognoe es HQ GUM euin dm s puew wo JUM MOJ SVU 194e lin pjou SJM euin DIOU puew wo IUM euin dhjes 1iq Jed S uM Sun poy HQ 19d SHJM euin uonisue UEL pue esi ublu JOS oy eui lqesip indino eves aun 9Bueuoaid FOS Ael p dnjes jndino jenas oj Moj 30S ublu OS Joye euin pjou indino jenas NOILdI49S3d penunuoo suomneoinioeds BUIWIL INVHA G sbed jupr peer ue dopjsaqotensiuupyshunmas pue sjueunooq 2 O OU AM o 30 10 o ANVEM O 0791 SSe xpv n o O ZHINOZ vo su005 SUOSY SUOOY SUOGE 54002 54062 54002 SUOST SUOOT 5405 540 T peal wel UPY opum uiejA dopisequojesiunupysBurjes pue sjuaunoo 2 fijen ered indui DIEN ASEN SIM o OM gt D o 30 10 o EM S M MOH o orsi SSeJ ppv ugy o 972 E 7 0 lt r o 2 ZHINOZ yo CREO GGI LILLO LE e Ae suosr 54007 5406 5400 SUOSZ SUQOZ SUOST SUOOT 5406 540 5406 T OHIM WRIA jupi usejjer Wen dojprsegwojejsiuiupy sBuieg pue siueunooqy 2 SUOSY LULI SUOOY o O M O ZHINOZ vo SUOGE 54002 54062 54002 SUOST SUOOT 5405 540 uysalja1 WIA Jupy p ue donjsaqyojensiuupyishunjas pue sjuaeunooq 2 CL HDS yos 021 Aq ul payne e1ep
15. OUTPUT gt FR RADDR 7 0 teri Avalon Bus Ctl Line Wait Request OUTPUT gt WaitReq Collection of counters that implement pulses to be sent to the LCD and computes the address of the row the VRAM needs to transfer into its serial shift register Page 1 of 1 Revision Date November 2008 lcd signal generator bdf Project oscilloscope LCD Signal Generator Generates the timing signals to be sent to the LCD and the row address used during a VRAM Data Transfer See the LCD timing diagram for the timings that this design implements Inputs nRS Active low reset signal XSCL has a period of 6 clocks XSCL is high for 3 clocks and clk System clock assumed to be 20MHz XSCLCounter low for 3 clocks Make sure all signals change on system clock edges NOT counter and prevent glitching with flip flops as I BE Do solr modulus 6 XSCLCompare 4 ei POR Signal to clear reset components in Kasel i i 7 Must be made active high LCDSignalFlipFlop ok L e clock qi2 0 dataa 2 0 ab data DFF System c
16. SOON 0 else DTRAN ONE when CurrentState IDLE and DT NOW 1 else IDLE when CurrentState IDLE Movement Within Cycles else CurrentState 1 Upon transition into the new state update the contol line values using the output lookup table output computation process CurrentState begin Look up and set control line values for the current state nRAS lt OUTPUT BITS CurrentState 0 nCAS lt OUTPUT BITS CurrentState 1 nWBWE lt OUTPUT BITS CurrentState 2 nDTOE lt OUTPUT BITS CurrentState 3 WR lt OUTPUT BITS CurrentState 4 VRAM address line access Assert rov address for the first and second read and write states if CurrentState READ ONE or CurrentState WRITE ONE or CurrentState READ TWO or CurrentState WRITE TWO then vaddr lt addr 15 downto 8 else Assert col address for the third fourth read and write states if CurrentState READ THREE or CurrentState READ FOUR or CurrentState WRITE THREE or CurrentState WRITE FOUR then vaddr lt addr 7 downto 0 else Assert DT row address for the first and second DT states if CurrentState DTRAN ONE or CurrentState DTRAN TWO then vaddr DT ROW else Output zero addess in all other states vaddr lt 00000000 end if end if end if Page 3 vram controller lut vhd VRAM data bus access Transfer VRAM data to Avalon Bus for th
17. built in simulated signal Even better there is no need to try to figure out how switch to another input signal because this oscilloscope has been specialized to display only this signal Hardware The hardware devices you use to interact with and monitor the oscilloscope are described on the next page Julian Panetta EE CS 52 Page 2 TA Gabe Cohn Device Name Device Type Description Keypad 4 4 Array of 16 Of the 16 keys only 5 are used keys Display LCD Panel A high quality LCD to display the oscilloscope s output Status LED LED A shiny red LED that lights when system has booted to let you know that initialization has completed successfully and the scope interface should be running User Interface 000 X EE52 Digital Oscilloscope Simulator cale Axes SweeP 100 ns Tri99er caval t 4804 Once programmed the system boots into Normal mode with a 100ns sampling rate and a positive slope mid level 2 480V trigger with no delay x and y axes are displayed behind the trace and a menu in the upper right hand corner demonstrated in the screenshot above lets you change all of the scope s settings and enter different sampling modes To hide and show the menu press the lt Menu gt key Julian Panetta TA Gabe Cohn EE CS 52 You can change from one highlighted menu item to the next using the lt Up gt and lt Down gt keys To alter the highlighted configuration setting the user pr
18. clock as the trigger not the sample clock instar clock 47 0 SAMPLE DATAT 0 data 7 0 en prr pm dme Page 1 of 1 Revision Date November 2008 LCD VRAM Block Implements reads writes data transfers and refreshes LCD VRAM Block bdf for the VRAM using a finite state machine implemented in VHDL Generates the signals needed to drive the LCD using a block design file with counters and comparators vram controller lut ADDR 18 0 gp aadr 18 0 nWR coh nWR nRD em nRD cik nes Oe Itt FSA nes VRAM Chip Select nRS VRAM LCD Rest DT SOON DT NOW nRS DT ROW 7 0 data 7 0 vdata 3 0 vaddr 7 0 nCAS nRAS nWBWE nDTOE WR Project oscilloscope State machine implementing VRAM cycles VRAM Control Lines BIDIR DATA PUT gt vdata 3 0 OUTPUT vaddr 7 0 OUTPUT gt nCAS H EE 3 nRAS OUTPUT nWBWE OUTPUT nDTOE inst LCD Control Lines OUTPUT gt DisplayEnable i Display enabled when no reset is occurini led signal generator Display 9 OUTPUT E XSCL ECL nRS XSCL e lt dk ECL System Clock 20 MHz DT SOON DT NOW OUTPUT YSCL 7 LP DI OUTPUT gt DI FR
19. in VRAM per LCD row equ VRAM WIDTH 256 Number of nibbles in VRAM per VRAM row Constants used for clearing the LCD efficiently equ NIBBLES PER WRITE 4 Number of nibbles cleared per write equ COLUMN ADVANCE NIBBLES PER WRITE Number of nibbles to skip over to advance to the next column equ ROWS PER LOOP 1 Number of rows cleared per iteration equ ROW ADVANCE VRAM WIDTH LCD NIBBLES WIDE Number of nibbles to skip LA to advance to the next row AES PALE PATE SECS SATE PS Ee TET SSS SS LETS SPSS FEDS LE SI LEP PERSP S PRI SS SS ETE RI PRI Keypad Constants Oe CST eS SKC SPCC ST R EES E A A 7 SCS A O A A A PIERA ES CSS A A R E PA FS R A E OA P ELSES PEC 7 ELECT ECS 7 equ KEY UP equ KEY DOWN equ KEY LEFT equ KEY RIGHT equ KEY MENU equ KEY ILLEGAL 0x02 0x22 0x11 0x14 0x12 S 0x00 i Up lt Down gt Left Right Menu Illegal Key stubfnc s c O xx x k k x x k kok k kok x x x k kok k kok k K kk K kk kok x ok x x k kk kk KKAKKAKKAKKAKKKKKKKKKKKKAKJ Xy STUBFNCS E Oscilloscope Stub Functions ny Digital Oscilloscope Project EE CS 52 7 x This file contains stub functions for the har
20. lom cishifto data 31 0 result 31 0 Ipm constanto distance i LOGICAL right shift inst3 inst2 many counts it should be low Divide scale factor by two to determine the number of counts the divided clock should be high and how Make counter reduce mod scale factor 2 1 Ipm compare5 unsigned compare Ipm add subo dataa 31 0 datab 31 0 98 7149 data Toggle clock output every scale factor 2 counts so that an entire output clock cycle occurs in scale factor counts Ipm tifo TFF inst4 inst6 We want scale factor 2 distinct counter values so we count up to scale factor 2 1 Page 1 of 1 inst5 Project oscilloscope b clock q I Q9UTPUT r cik out Revision VHDL e VRAM Controller State Machine o State machine diagram o vram controller lut vhd Miscellaneous Helper Blocks o split vhd o combine vhd o combine 16 16 vhd Actions executed upon state entry READ TWO P M WRITE THREE nRAS low VIBITE TWO Assert Input Data n OW A t IA READ THRE ssert Col Addr Assert Col Addr READ ONE Assert Row Addr WRITE ONE nDT High Assert Row Addr WRITE FOUR READ FOUR nCAS high Assert Write Mask nCAS low nCAS low nWE High nCAS high WRITE FIVE WAIT nWB low i nOE low VRAM Read Cycle VRAM Write Cycle READ FIVE Transfer Data WR low WRITE SIX READ SIX nRAS hi
21. ooooooooooooooooooooooonoooooooooo oooooooooooooooooooooooonooooooooo Timing Diagrams o VRAM Timing Specifications Read Write Refresh Data Transfer o LCD Timing Specifications 1180F 1190 LCD Signals o SRAM Read Write o Rom Read 0 SHQ SUSE aHa SUOZ HHG sugg Ho suop Wo sugor IN suo aso 5402 ko suol duo sugz Ndo 5409 sugz WHO suoy Hao sug9 svo suoz HVO su09 ovo Su asv W osv 5408 xv NIN 108WNAS euin dmes uBiu 10 MOI SVA Jaye euin plou Ul e eq aun plou ubiy La euin DIOU ur ejeq euin Peal SVO 0 pueululoo SM Kejep 3M 01 SVO euin dmos ysejal SVY 21994 SVO aun DIOU sva aun moj 97 o uBiy Svo ejoKo eBeduou euin aBreyosld Svo uo eBed euin sGieuoaid Svo euin plov yseya SYY 21094 SVO MOI SVY leje euin nol LG Upim sind SVO aun DIOU sseJppe uuinjo2 SVO Woy euin sseooy euin dnjes ssalppe moy euin dnjas sseJppe uwnjo3 mol SYH Jeye aun pou ssaippe uwnjog NOILdiHOSIA suonjeorjioeds Bulwil WVHA 2 obed 0 HOY SVO Jeye euin plou pue woo Be 5409 sugg E ou el p SVO o Sv SUOZZ ou aun ejofo JO peas ulopues SUQOOOL 54021 57 Upim sind SVA sug euin pjoy sseippe moy SUOZI Suh sva UJOJJ WI SSe29y SUOZI ad aun e oKo sbed suog 0 yBly SVO Woy aun ejgesip jndino suog 0 z UBIU 30 Woy tin lqesipindino 5001 S30 aun dm s angoeui SYY 0 JO 3006 H30 MO A
22. 7 777777 K TPE OA 7727 77777 772 O O R OA A R O P R F OA K A RK OA P A R FK RETA Description Installs and initializes the isr that is run when a key is debounced Operation Intalls ISR i Clears key ready and key data variables i Clears edge capture register so previous keypresses aren t detected Arguments None Return Values None Outputs None Registers Destroyed None Registers SAVED RESTORED Shared Variables E key ready Cleared Boolean value recording the occurance of a keypress i key_data Cleared Byte recording the value of the keypress Data Structures Algorithms None E E E R E TESST SEER E K A O OA T A T OA A E P OE K TPC K A T ee Te O K TC EES EZE A O OE AK TP O R E R O SC K OA A O F O RE EF install key handler SAVE sp 0 no stack space is needed MOVIA 00 na key ready pio irq Select key ready interrupt MOVIA Sol key handler h load ISR address MOVIA 502 0 context ignored BSR nr installuserisr install our keypad isr NOP Initialize key ready and key data words to zero MOVIA 12 false MOVIA 11 key ready ST 11 12 No key is ready initially keypad s MOVIA 12 KEY ILLEGAL Not needed as false KEY ILLEGAL MOVIA 11 key data No valid key is encoded initially ST Es 512 Clear the edge capture register to ensure a keypress made before loadin
23. B PET cle row col tack depth 0 hared Variables None ata Structures Algorithms None A S SS CESSES ZE Eege d edd Eege deed Eege PLAS SSES EA CPE 400420 ar display SAVE ssp 0 no stack space is required Load VRAM base address MOVIA 10 na vram 0 MOVIA 13 CLEAR PATTERN Load pattern to clear 4 graphics nibbles MOVIA 11 SIZE Y loop over all LCD rows MOVIA 14 ROW ADVANCE Ammount added to address to advance row loop MOVIA 12 LCD NIBBLES WIDE loop over all the nibbles in the row loop ST 10 13 Clear 4 nibbles 16 pixels of the LCD SUBI 12 NIBBLES PER WRITE Subtract nibbles cleared from remaining IFS mz BR col loop Continue until there are none remaining Page 2 display s ADDI SUBI DES BR ADD RESTRET de oe 10 11 C In OW 10 COLUMN ADVANC CJ ROWS_PER_LOOP 2 loop 514 Move to the next set of 4 nibbles Subtract rows cleared from rows remaining Continue until there are no rows remaining Advance to the start of the next row Page 3 interrupts s E EE E E RSC SS ES ES PES eS ER TSE ST ESET 7077777 77777 77 777 7 E AER A K TP T TF Z r include File interrupts s Description Routine to enable interrupts for the NIOS CPU The only interrupts acknowledged are from the keypad so only the na key ready pio s interrup
24. CS NOS RAM N37 mi CS ROM N34 m hb CU 01 HR PNG olmio USDRI N56 umo Td Ni mi o Ro pny m keypad roden 120 Rowo keypad roden 12 Rowo keypad ropN 1233 Rowo o STEIN TIO keypad co N 140 m keypad col PIN i4 Fait keypad colm 151 bai P keypad col PIN 152 Rowto Uli piii Rowo Ula PR 1 STATUS LEJPIN i Row UIDRI NIS omaro 0 uar N20 JGetumnvo vadarlor PNA Rowto vadra N24 olumio Mad en 203 Column Madd 3 N02 JGotumnvvo vadarlal N20 columniito O vadarl51 NN 200 olumio vadare uge mi 1 vadarl7 N19 olumio vdatafol NN 195 Bim 1 dsl On JCotumnvo vdataf2l en 195 Bim 1 vdataf3l N19 mit mas PNA m cas pnas Rowo O o hDTOE fema Rowo mwewe enso mio vaan se fens ROO D N35 DisplaytnalPIN 40 Row FR pna m Y p Nm m ea pi Rowo wl pna m 7 Quartus Design Top Level Desig
25. D Conector 9 2 R 15 RIOUT Los 5 varon Ee GND PFO RY x RA RIOUT RXI APEX J4 APEX 710 NAAR eU 145406 Top Left of the Adapter Board WDI WDO and PFO are left floating as allowed by datasheet am EE52 Digital Oscilloscope Protoboard Size Numba Revision B 1 0 Date 11 19 2008 Sheet of File C Documents and Settings protoboard s hawn By Julian Panetta 2 3 4 5 6 5800mil KR NA D 00000000100 PHS TAR ECA OL v6 4 oo no oono o 99 o KEYBOARD MOUSE UGA o c 2 r o o Ww a Board ETHERNET ETHERNET oo cados dodo p00 0 OR A 00000000 o 0000000000 0000000000 00000000 000000090 000000000 000000000 o Sco o 000000000 o ol lo ooooooooo o 9 o o oo oo o o o o o oo oo 0000 0 o o o 000000000000 o o o 000000000000 o o o 000000000000 o o o 000000000000 o o o o oooooolo0 o o o ooooooooloo o o o 090000000000 o lo o 000000000000 o o o o 0 00 0 0000000 o lo lolo 000000000000 Clo ool o 000000000000 olo ujel o OLOJO OLOJO 010 00 00 0 0 e ilo 000000000000 le o o 0 00 00000000 o o o 000000000000 o o o oooo m 0000 oooooooooooooooooooooooooooooooooonooooooooon o oooo 13 moooooooooooooooooooooooooooooooooooooooooooo ooooooooo 000000000 000000000 010 000 ooo o o m O o o o o O o ooooooooo 14 Li al B 5 Neen a I Co 19 22 oon o Na o s 5
26. EE CS 52 Digital Oscilloscope Documentation Julian Panetta TA Gabe Cohn Table of Contents User s manual Functional Specification Block Diagram Protoboard Schematic Board Layout Timing Diagrams o VRAM Timing Specifications Read Write Refresh Data Transfer o LCD Timing Specifications LCD Signals o SRAM Read Write o Rom Read Memory Map Pin Assignment Quartus Design o Top Level Design Analog Control Block LCD VRAM Control Block LCD Signal Generator Keypad Debouncer o Clock Divider VHDL o VRAM Controller State Machine State machine diagram vram controller lut vhd o split vhd combine vhd combine 16 16 vhd Software o Drivers Initialization starts keypad s display s interrupts s constants s o OS stubfuncs c interfac h Julian Panetta EE CS 52 Page 1 TA Gabe Cohn Digital Oscilloscope User s Manual AAA X EE52 Digital Oscilloscope Simulator Normal cale Axes SweeP 2 Hs TridYer 7 Level t 4804 Z SloPe Delay t 5000ms Introduction This digital oscilloscope is an easy to use instrument for visualizing analog input signals In fact such great care has been taken to ensure ease of use that the user s task of finding and attaching an analog voltage signal source has been removed entirely Simply attach the oscilloscope to a computer open up your 2500 copy of Quartus program the FPGA design into it and you re ready to view the beautiful noise free
27. M eye aun pjou 20 sugg aso ejep dnjas ul ejep o 20 supe va0 30 Woy su sseooy sugg 29 Upim sind 30 suo aig kejep uBiu sva o udiu La 5402 Hin UBIU svy Joye own ploy ubiu LA SUOL da Kejep uBiu svo o UBIU La 0 sq euin das ur ejeq 0 sla au dm s Moj 10 XVIN NIN 109INAS NOILdlH2S3d penunuoo suomeaiioedgs GUIWIL INVHA abed sug 308 sugg vos suol Has sup 009 5401 TS su00005 sup 2999 suop ZE sup O sup 1 sugg sugog 6409 HSM suoz HMM 0 Oda 5406 em SUOOL Eh 0 sou XV NIN 108WAS Upim sind 308 BOS woy sun ss ooe jndjno elas uBiu 10 eye stu DIOU Mol OS u lu La o UBIU OS aun 9Bueuoaid OS au aj9 9 19019 elas OS Woy aun sseooe ndino elas Upim asind OS SW pee SVY O PUELU woo JUM peuyep eq o fejep 3M o sva euin ejo o aun ploy sva uBiu SVU Jepe ploy pueululoo peas aun ebieyooid MOI SYO 0 ublu sva aun eB1ueuoeJd sva jemejul e noe pod jenas Moj Sv Jaye eun plou mo LG euin dm s peas NOILdI49S3d penunuoo suoneoro ds BUIWIL INVHA sbed jen joy qod 001 001 0 SUSE aM 5402 RR 0 SOM sugg SM suce HOM o suoz HEM 5409 sug 5 suog 0 20 sug dos ES oos suo HOS ven NIN 108WAS SVO o sva enjoy aun dnjes uonoejes 114 AUM UJPIM sind puewwo SIM euin
28. REEFREE EA NV PLAT TESTS OL EFE PETER I Pr include excalibur s include constants s text global start CVA PEA R A A O A PST R A NS OA A O EE A SS A A ST SS PRI PARE PEER rr EEE IT OA o O NR ETETETT ESE Void start void ZZ ff BEZE Z 7 7 7 o7 777 PASTE 7 0 FEAR ESPE 77 to EE FREE FF EFI ZE Description Code located at the NIOS reset location Initializes hardware and then runs the oscilloscope OS Operation i Installs the keypad handler initialize interrupts and forces interrupts to be enabled gt Turns on the status LED Branches to the oscilloscope s main loop from which the NIOs should never i EMI Arguments None Return Values None Lnpute Keypresses read from keypad Outputs User interface displayed on LCD Registers Destroyed None Registers SAVED no supervisor caller anyway Shared Variables None YT 7 77 7777 77 7 777 70 7 7777 ff 7 7 7777 7 777 9 7 7 70977 7 7 79 EZE Start SAVE ssp 0 No stack space is needed _BSR install_key_handler NOP _BSR init_interrupts NOP Turn on interrupts According to the NIOS Programmer s Manual interrupts should be enabled by default and need only b nabled if explicitly disabled previously However I have found the interrupts don t function if they aren t enabled as done by the following two lines These lines were copied v
29. Z File constants s Description Defines constants used by the keypad and display hardware drivers E Also defines global software constants and constants related to the status LED i Revision History 11 17 08 Julian Panetta Initial Revision E E E EN R A O EE E A O O AO E AO A A E A EEE EE E EE Boolean true value Global Constants PLE D T equ true 1 egu false 0 Boo lean false value CN EP EL EEE E A E E ES E A ET E NA A gt status L 0 0 7 57 equ LED ON equ LED OFF ED Constants 4 0 Va Value to write to L lue to write to TI 7 7 77 77 7 7 7 7777777 7777777777 77 ED PLO to turn on Status LE LED PIO to turn oft Status 1 PIERRE RR PETER RP BEI a a a ee E E s Display Constants TU rr r r PE TF FE SPE EF FS PT AEP FEE ST A r EZ ES ro r r REST PETS STP ESSE SPP ES ECCS See Se EZE or o equ PIXEL BLACK OXOF Pixel color passed to draw black pixels equ PIXEL WHITE 0x00 Pixel color passed to draw white pixels equ CLEAR PATTERN OxFOFOFOFO Word value that will clear 16 bits of VRAM VRAM LCD Properties equ SIZE X 640 X resolution of the LCD equ SIZE Y 200 Y resolution of the LCD equ LCD NIBBLES WIDE SIZE X 4 Number of nibbles
30. datab 0 Key is debounced after 20ms have passed without inst counter3 the row nibble changing Key will repeat after being Ipm dffo pm compare Are any keys being held up counter held for 300ms since the counter reduces mod 300 DFF compare sclr modulus 300 col 3 0 Ipm compare3 compare e aneb b clock insito k a 8 0 dataa 8 0 ai dak Poll the current keypad rovv insti ent en datab 20 indefi clock once each millisecond Detect changes in the row nibble inst inst12 which will reset the debouncing counter Ipm d DFF q HUEL 1 key ready inst debounce counter only counts when we are debouncing a key when the row data read is not zero The counter resets every time a value is read that differs from the last read Prevent key ready from glitching when it changes due to combinational logic since it needs to be used as an interrupt line Page 1 of 1 Revision Date November 2008 Clock Divider Divides clk in by scale factor generating a new clock on clk out clock divider bdf Known issues if scale factor is odd the divided clock cycle will occur in scale factor 1 ticks rounds down to nearest even Ipm counters a integer A scale_factor of 1 is not allowed as it will cause an sclr overflow in the computation of scale_factor 2 1 clk_in INPUT dind q 31 0 inst
31. downto 0 high lt a 15 downto 8 end dataflow Page 1 of 1 Revision Date November 2008 combine vhd Project oscilloscope Combine For use with computing debounced keypress output Concatenates 2 bit row address read from port a with 4 bit column data read from port b into a 6 bit output placed on port c The row address is placed in the MSBs of the output and the column address is placed in the LSBs Library ieee use ieee std logic 1164 all entity combine is port a in std logic vector 1 downto 0 b in std logic vector 3 downto 0 G out std logic vector 5 downto 0 end combine architecture dataflow of combine is begin c lt a 6 b end dataflow Page 1 of 1 Revision Date November 2008 combine 16 16 vhd Project oscilloscope Combine 16 16 Concatenates two 16 bit inputs read from ports a and b into a 32 bit output value placed on port c the value of port a is placed in the most significant bits of c and b s value is placed in the least significant buts Revision History 09 05 08 Julian Panetta Initial Revision Library ieee use ieee std logic 1164 a11 entity combine 16 16 is port a in std logic vector 15 downto 0 b in std logic vector 15 downto 0 G out std logic vector 31 downto 0 end combine 16 16 architecture dataflow of combine 16 16 is begin c lt a 6 b end dataflow Pag
32. dware interfacing code for the Digi tal Oscilloscope project The file is meant to allow linking of the main code without necessarily having all of the low level functions or hardware working The functions included are key available check if a key is available getkey get a key clear display clear the display plot pixel plot a pixel set sample rat set the sample rate set trigger set the trigger level and slope set delay set the trigger delay start sample Start sampling sample done sampling status The local functions included are none The locally global variable definitions included are none Revision History 3 8 94 Glen George Initial revision 3 13 94 Glen George Updated comments 3 13 94 Glen George Changed set sample rate to return SIZE X 5 9709 Glen George Updated start sample stub to match the new Specification 11 4 08 Julian Panetta Altered stub functions to implement test 7 analog sample Also removed stub functions for keypad display which have real implmeentations library include files none f loca 1 include files include include Anberfac h scopedef h Variables used to store state of analog hardware simulator static static static static long int sampl int sample level long int sample de int is sampling le rate sample slope lay Buffer to store simulated analog inp
33. e 1 of 1 Revision Software Drivers Initialization NIOS Assembly o start s Initializes hardware and calls oscilloscope operating system main loop Global symbols start o keypad s Interrupt driven driver for the keypad Global symbols install key handler getkey key available o display s Code for drawing on and clearing the LCD Global symbols plot pixel clear display o interrupts s Code for initializing interrupts Global symbols init interrupts o constants s Include file holding constants used throughout the NIOS assembly files listed above e OS C o stubfuncs c Functions emulating hardware not yet implemented Global symbols set sample rate set trigger set delay start sample sample done o interfac h Include file holding constants used throughout the oscilloscope operating system start s yo rr r E SF ES ET SPS fy o TS ET ESET TSC rg K E TPE A E O rg K A 777 FE ro E O O A K A PS ee SSA File start s Description Code run when the NIOS resets Performs hardware initialization and then branches to Glen George s oscilloscope code DH input Keypresses from the user analog signal input not implemented Output Output displayed DH Known Bugs None Revision History gt 11 04 08 Julian Panetta Initial Revision 5 11 17 08 Julian Panetta Added more extensive documentation Foy A T RET L T PEST FLEES T OA O O A A A R O A A SCE PST OA O AR A R OR TO TEET
34. e fifth read state if CurrentState READ FIVE then data lt 0000 amp vdata else Assert write mask for the first and second write state if CurrentState WRITE ONE or CurrentState WRITE TWO then vdata lt data 7 downto 4 else Assert graphics nibble for the third and fourth write state if CurrentState WRITE THREE or CurrentState WRITE FOUR then vdata lt data 3 downto 0 else In all other states the Avalon data bus and the VRAM data bus should be high impedance vdata lt ZZZZ data lt 22222222 end if end if end if end process output computation Make actual transition to the new state on rising clock edge make transition process clk begin if clk 1 then Only change on the rising clock edge CurrentState NextState Transition to the new state end if end process end Moore machine Page 4 Date November 2008 split vhd Project oscilloscope Splat Splits the 16 bit input bits read from port a evenly into the 8 LSBs place d on low ouptut line and the 8 MSBs placed on high output line Revision History 09 05 08 Julian Panetta Initial Revision Library ieee use ieee std logic 1164 a11 entity split is port a in std logic vector 15 downto 0 low E out std logic vector 7 downto 0 high 5 out std_logic_vector 7 downto 0 i end split architecture dataflow of split ig begin low lt a 7
35. erbatim from the Programmer s Manual PFX WRCTL g0 Turn on the LED to indicate the system has booted MOVI 11 LED ON ES start s MOVIA PEX ST BSR NOP y R This line should never be reached ESTR ET 610 na LED pio np piodata 10 main 11 Run Glen s oscilloscope code Page 2 E EE E r r E T E ESE KCL KA ES EPS ET AE K A A E K E EES A OA A O T O rrr A A O A r r v OA DR E O A REP O OD eee O SS Z File keypad s n Description Routines to allow Glen George s oscilloscope software interface with S the debounced keypad Inputs Debounced keypresses from the user ISR run when keypress made QUEDOLI None Known Bugs None Revision History i 09 06 08 Julian Panetta Initial Revision gt 11 17 08 Julian Panetta Added documentation and replaced magic numbers with constants P ED ER RL A R E T OA IN AR O O NO O P R OA R K A Te Pr TET A r OP PEE Se CSIP TST Se CSP PLAT EE EZE PETITE PRPPII PI include excalibur s include constants s data key ready 4byte false key data 4byte KEY ILLEGAL text global install key handler global getkey global key available PO P AT A T A O T K 7 O K A ee Sy O O AAA O K 7 O P FE RAEE EA Z T A OA 7 777772777 r7 7 E O A O ee OA K 0 67 ro void install key handler void You 7 77 777777 77777 77
36. esses the lt Left gt and Right keys to select a value The configurable settings and their values are as follows Menu Title Options and Description Mode Normal Scope waits for a trigger after completing each retrace Automatic Scope waits for a trigger after each retrace but retriggers automatically without a trigger event after a delay One Shot Scope triggers only once continuing to display the last trace captured Scale Scale Axes Display x and y axes along with trace Scale Grid Display x y grid along with the trace Scale Off Display the trace only Sweep Items are time quantities that specify the sweep rate or the time between successive samples options 100ns 200ns 500ns lus 2us Sus 10us 20us 50us 100us 200us 500us 1ms 2ms 5ms 10ms 20ms Level 128 voltage quantities are given as choices for the trigger voltage level The levels are equally spaced from 0V to 5V Slope Slope Scope is triggered on a positive slope rising edge Slope Scope is triggered on a negative slope falling edge Delay Time quantities ranging between Oms and 1ms specify the time between the trigger and the start of the trace Limitations If for some reason you have decided to go through the effort of finding a voltage source you want to measure you will find that the oscilloscope has no connector to which you can attach the signal The oscilloscope is compatible only with the built in
37. g the code doesn t result in an interrupt MOVIA 511 na key ready pio MOVI 510 false PFX np pioedgecapture ST 11 10 RESTRET G Ee rr LS TP r o To E ETA LETS SEPP CESSES SP RATA LE PP LFEPA EPSP ES PE PES E PRI LT ET ELE SS ET ES void key handler void U PAT TR ETE EE E ISI A R A A A O A A A SE EE A DO R P gc A A O A A A R A A A O ES FEX A A A O PIPE E O O R O O EEES ES Description ISR that is run when a key is pressed Simply records the presence of a key and resets the interrupt event Operation Clears the edge capture register so the event doesn t fire until a new keypress is made Sets key ready and stores debounced key data in key data Arquments None Return Values None gt Inputs Keys pressed by the user trigger this handler Qutpute None Registers Destroyed None Registers SAVED RESTORED Shared Variables key ready Set Boolean value recording the occurance of a keypress i key_data Stored Byte recording the value of the keypress Data Structures Algorithms None FELL SL SS KEL SEES SES SS SLE ESS SES KS ES ES STS EES SSeS SE SES ES ESE EE EE EEE KEE PES EET REEF key_handler SAVE Ssp 0 no stack space is needed clear the edge capture register MOVIA 11 na_key_ready_pio MOVI 10 0 PFX np pioedgecapture ST 11 10 MOVIA 10 key ready MOVI r0 true ST8S 10 r0 Indicate a debounced
38. gh nRAS high nCAS high nCAS high nWB high nOE high i WR low WR high REFRESH ONE Assert Row Addr nCAS low DT TWO nDT Low ARAS low _ nCAS high DT THREE REFRESH FIVE Asser Col Addr VRAM Data Transfer Cycle nRAS high DT FIVE REFRESH FOUR DT FOUR nDT high WAIT nCAS low REFRESH TWO nRAS low VRAM Refresh Cycle REFRESH THREE nCAS high vram controller lut vhd Page 1 Oscilloscope VRAM Controller This VHDL file implements a controller for the NEC uPD41264 12 VRAM chip The controller is implemeted using a state machine whose transitions are a function of the input lines Output signals change upon transition to a new state and their values are looked up in a table indexed by current state number The controller uses a wait request line to halt the NIOS cpu until it is able to complete a read or write since a refresh cycle or data transfer cycle could delay read write cycles an amount unpredictable to the Avalon Tristate Bus See the state diagram for a visual overview of the state machine Inputs and outputs are enumerated and described in the port section below Revision History 10 23 08 Julian Panetta Initial Revision 11 16 08 Julian Panetta Reformatted to fit within 80 chracters wide Library ieee use ieee std logic 1164 all use ieee std logic unsigned all use ieee numeric std all entity vram controller lut is port 16 b
39. he nibble holding the desired pixel R Adds this offset to the VRAM base address to compute the absolute address Creates a bit mask for the VRAM write so that only the desired pixel of R the nibble is modified H Sets the write data to all 1 s for p PIXEL BLACK and all 0 s for p PIXEL WHITE This ensures the selected pixel is set to the correct i value regardless of which of the four pixels it is Sends these computed write mask and data nibbles to the VRAM Arguments After execution of SAVE i0 x coordinate of desired pixel 311 y coordinate of desired pixel 12 p color to paint specified pixel i Return Values None i r Outputs Pixel at x y painted with color p Corresponding bit in VRAM is set i Registers Destroyed None Registers SAVED RESTORED Stack depth O0 Shared Variables None CREDERE RE E EE EE POPS PIPPE DAR RESPETE E ER PET SS ERE SEP EE PPP PCS PI Pe OT eS Pe ADN plot_pixel SAVE ssp 0 Load VRAM base address MOVIA 10 na vram 0 Compute offset from VRAM base address Offset VRAM row 8 i y lt lt B LSLI 211 8 ADD 10 Sil VRAM column x gt gt 2 no stack space is reguired move y coordinate into the row portion of offset display s ZZ MOV 11 10 Get a copy of the x coordinate LSRI 511 2 get the nibble in which the pixel appears
40. ia a serial connection This feature is not yet implemented Status LED LED LED lights when system has booted to inform user that the software initialization has completed successfully and the OS should be running User Interface By default the system boots into Normal mode with a 100ns sampling rate and a positive slope mid level 2 480V trigger with no delay x and y axes are displayed behind the trace and a menu in the upper right hand corner lets the user change all of the scope s settings and enter different sampling modes The user can press the menu key to toggle the menu s visibility The user changes from one highlighted menu item to the next using the up and down keys To alter the highlighted configuration setting the user presses the left and right keys to select a value Serial transfers will be implemented with silent linking The computer will send a request to transmit data or a request to receive data and the oscilloscope will comply without asking the user to confirm A status message for the transfer will be displayed in the lower left hand corner The menu options are as follows Menu Title Options and Description Mode Normal Scope waits for a trigger after completing each retrace Automatic Scope waits for a trigger after each retrace but retriggers automatically without a trigger event after a delay One Shot Scope triggers only once continuing to display the last trace capt
41. it address input row amp column addresses with 3 disregarded most significant bits so it interfaces with 19 bit shared Avalon bus addr in std logic vector 18 downto 0 8 bit data bus data writemask nibbles data inout std logic vector downto Write enable nWR in std logic Output enable nRD in std logic System clock Assumed to be 20MHz clk in std_logic Chip select ncs in std logic Data transfer needs to occur before a new cycle can be completed 1 true false DT SOON in std logic Data transfer needs to occur NOW 1 true 0 false DT NOW in std logic reset state machine to known IDLE state nRS in std_logic Row address to be used for the data transfer cycle The data transfer column is always 0 DT ROW in std logic vector 7 downto 0 vram controller lut vhd 4 bit data bus to VRAM vdata inout std logic vector 3 downto 0 8 bit address bus out to VRAM out std logic vector 7 downto 0 vaddr ee RE B nCAS RAS 8 nRAS nWB n nWBWE nDT n nDTOE ignal to VRAM ignal to VRAM out std logic out std logic WE signal to VRAM out std_logic OE signal to VRAM out std_logic Wait request signal for WR out std logic end vram controller lut WR
42. key was received MOVIA 10 na keydata pio PFX np piodata LD 11 10 MOVIA 10 key data 10 511 ST RESTORE TRET 307 EELS EELS AR OA T A KEL OA AR O ESE SL ELE LEK ELSE ETRE PI OA AR PIPE T OA AR O TO OA AR RI RE O AR OR A TE R A R A R A SET RET EES unsigned char key available void Fo dE Eet Ee Ee E 2 SEPA SSS SLES SESS 2 SSSA SESS SS PSE SSS SESS TSS SLES SP ES SPSS DIES SOT ET oro Description Returns 0x01 if a key press is ready for reading and 0x00 if not Page 2 keypad s Page 3 Operation i Reads key ready and extracts bit 1 as the return value Arguments None Return Values None i inputs None Outputs None Registers Destroyed None Registers SAVED RESTORED Shared Variables i key_ready Read Boolean value recording the occurance of a keypress PZ Z ZZZ OPEL ES ES PT EL EST ES EP TT ET TT TT TT PTP TT EE EP CSET EP eT PPP CPSP EE EP 7 7 key_available SAVE ssp 0 No stack space is needed MOVIA sol key ready LD 500 01 MOVI 01 true AND 00 Sol Check if a keypress is ready RESTRET L t X Eet PPS EZE SE Ee WE SSF SLES SSS Ee EEL SS EES AE GA SS ZE E E E AE E RITA int getkey void L E EK E AR AR R RR A EE 2 A PERI PRAIA PE PPP PE Description Waits until a valid keypress is made if one hasn t been already and then returns that keypress code Operation Waits until a a ke
43. lock 20MHz ECL is high for clocks 2 to datab 3 Dap e mr su 9 at the start of its period e clock q ECL has a period of 96 clocks ECLCompareLow insta7 Occurs once every 16 XSCLs unsigned compare ECLCounter dataa 6 0 up counter ageb est modulus 96 datab 2 instar AND2 LCDSignalFlipFlop e clock Sa T N id Z ECLCompareHigh data inst unsigned compare m 5 dock a our ecc dataal6 0 ve ataa 6 0 y datab DT SOON is high from clock 950 in ohe inst SOONCompareLow Period to clogk 8 in the next unsigned compare this is a very conservative interval dataal9 0 i i 7 gt ageb ore LeDSignalFlipFlop DT has a period of 960 clocks t bir data Occurs once every 10 ECLs DT NOW is high for clocks insi33 ups ec DT SOON DTCounter 3 to7 at its period beginning SOONCompareHigh up counter unsigned compare e uy modulus 960 NOWCompareLow unsigned compare dataal9 01 A e clock qi9 0 dateal9 0 et databll 8 ins databfl inse 3 inst AND LCDSignalFlipFlop 5 NOWCompareHigh dala DEF 5 unsigned compare D inst22 clock q OUTPUT gt DT NOW dataal9 0 A um databll 8 V LP has a period of 1920 clocks LPCompareLow LP is high from clocks 6 to 13 Occurs once every 20 ECLs unsigned compare at the start of its period LP Counter dataa 10 0 Up counter eb sol modulus 1920 datab 6 wi AND2 LCDSignalFlipFlop clock 10 0 DS DFF Kee LPCompareHigh data inst Unsigned compare
44. n Analog Control Block LCD VRAM Control Block LCD Signal Generator Keypad Debouncer Clock Divider Date November 2008 oscilloscope bdf NIOS ck RESET o CH System Reset out port from the LED pio out port from the analog control reset pio out port from the analog control settings data pio 15 0 Cic DONE System Clock 20MHz in port to the analog filo data in pio 7 0 in port to the analog filo empty pio in port to the analog fifo full pio Debounce keypresses with key repeat and interrupt the NIOS when one is debounced key debouncer in port to the key ready pio Keypad row enable lines cik rowo ALBU keypad et row S keypad rowir in port to the keydata piojs 0 Input lines for reading undebounced row row2 ABT keypad route WaitRequest from the vram 0 of keypress data from the keypad rowa ATD keypad el key data 5 0 my key ready linterrupt line for keypad input RX2 Jpg Serial input data line for NIOS terminal rd to the uar 0 out port from the analog control settings selector pio 2 0 out port from the analog filo read req pio nCS to the ram 0 nCS to the rom 0 NCS to the vram 0 nRS to the vram 0 rom 0 ROMAm29FO40B wait counter eq 1 tri state bridge address 18 0 tri state bridge O data 7 0 tri state bridge O readn tri state bridge O writen txd from the uar 0 Project oscilloscope Contr
45. ol line for the status LED Bringing this line high turns on the LED OUTPUT STATUS LED Buffer Enables Enabled Buffers 4 6 7 8 9 10 ayo umur U40E1 U4OE2 cumur Venez U70E1 U70E2 cumur goes 8062 veer umur 80 2 U100E1 U100E2 Buffer Directions GND input VCC output Input Buffers 8 1 Serial in 10 2 Keypad column DJ Ram q usi am 53 Vum Output Buffers 6 2 Address CS lines 7 Address 8 2 Serial out 9 1 OE WE LCD Control lines 9 2 VRAM control 10 LED Keypad row 4 2 VRAM address VapiR2 Uess Urbini Uess USDIRI Uess UtODIRI Variable Bufler 6 1 Data bus 4 1 VRAM data bus an ncs RAM outeur ncs ROM RAM and ROM Chip Select Lines DE DE OUTPUT ep LTELT vm gt n insti ANALOG RESET B bit Input from the ADC Ipm constant Store ADC samples until software can read and process them pm Hat ADC DATA 7 0 g LA a L SETTING SELECTORI2 0 SAMPLE DATA 7 0 The analog input hardware is not constructed SETTING DATA 15 0 SAMPLE REQ wired so take the input to be a constant zero SAMPLE CLK neq analog clock ai7 01 full empty When requested sample data from the ADC at a specified sample rate seir 8 bits x 16 wo
46. rds E stem Clock 20MHz the Avalon bus and the VRAM s bus LCD VRAM Block Generate signals to control the VRAM and the LCD and provide an interface between ADDR 18 0 DATA WA vdata 3 0 nRD vaddrl7 0 ncs nCAS nRS nRAS dk nWBWE nDTOE DisplayEnable XSCL EOL YSCL LP DI FR WaitReq VRAM Ctl Bus LCD Signal Lines s Lamar gt wes I ee amu p soe omur o gt CA TD 3 VRAM SC OUTPUT EcL OUTPUT gt ven pu gt QUUD DI FR insir Page 1 of 1 Revision Date November 2008 Analog Control Block Samples data from the ADC at a specified rate after a set delay following a trigger event defined by a configurable level and slope The settings are altered by first selecting the desired setting by placing a 3 bit identifier on the selector line 1 Sample rate 2 Trigger delay 3 Trigger level 4 Trigger slope Then the value for that setting is placed on the SETTING DATA line Once the setting is made the setting can be deselected by writing the identifier 0 or by selecting another setting to change This control block interacts with the FIFO storing sample data on SAMPLE CLK s rising edge by analog bdf
47. suozi Y O 3o O 3M O 39 I os ssenv peay ereq o E E E 4 O su00s suQor su00 54002 SUOOT suo SUOOT T 3624 pe INOH Memory Map rom 0 ram 0 E onchip memory uart 0 keydata pio key ready pio E analog control settings data pio analog control settings selector E analog control reset pio analog fifo read req pio El analog To data in pio analog fifo full pio E analog fifo empty pio vram 0 tri state bridge 0 E nios 0 ROM RAM Legacy On Chip Memory RAM or R UART RS 232 serial port PIO Parallel VO PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 1 0 PIO Parallel 110 VRAM Avalon Tri State Bridge Nios Processor Altera Corporation cik cik cik cik cik cik cik cik cik cik cik cik cik 0x00000000 0x00080000 0x00088000 0x00088800 0x00088820 0x00088830 0x00088840 0x00088850 0x00088860 0x00088870 0x00088880 0x00088890 0x000888A0 0x000888B0 0x00090000 Ox0007FFFF Ox00087FFF 0 000887 0x0008881F 0x0008882F 0x0008883F 0x0008884F 0x0008885F Ox0008886F 0 0008887 0x0008888F 0 0008889 0x000888AF 0x000888BF Ox0009FFFF 3 Digital Oscilloscope APEX20K Pin Assignments ep Function T Function RESET PN fio ON UE Ni colui 101 U40 2 piN206 olm io column
48. t need b nabled Input Output Known Bugs None None None Revision History 09 06 08 Julian Panetta Initial Revision FU da A S A SRS PRE PEPE POPE EE REPS SES SCOTS E eS SP Ee SP eS E text global init interrupts excalibur s P ZZ EZ ZZ E ZZ EL ET EL EP ESET ES SE SSE ES EE ES ES EL eT ESET 7777777 77 77 7777777777 Pe void init interruots void E SE ETE R AE AR A EE A 7 A A A A a R A A 0 A A EE A A R A A A A A SES Se ZE ES A A K A PER PAPPE PRA PE Description Enables al 1 the interrupts to be acknowledged by the NIOS This shoul already been installed Operation Sets the key ready pio s interrupt mask bit to 1 so that the debounced Arguments key bit ld only be called AFTER the ISRs to handle these interrupts have line can interrupt the NIOS operation None Return Values None Outputs None Registers Destroyed None Registers SAVED RESTORED Stack depth 0 Shared Variables None Data Structures Algorithms None P ER EE E ES K A A E ER P O r r A A K r ri A A O A A P eS T A OA K A Tee E TT O P A O O E AK A O E A K AR OA CSC O A K PSEC ETE inzt Interrupts SAVE sp 0 No stack space is needed MOVIA 10 na key ready pio MOVI STB 1510 R ESTRET i 3 np piointerruptmask 11 constants s EEE E A E K E ET eS EP ES o PERE PERE E TS ET a A E T A A r A OA A E TC STS SC ST TPT o Ko A OR eC O ETE OA OD o EE
49. taneous kepresses occuring on different rows In this case the first row with a keypress encountered during row multiplexing is the only one from which keypresses are debounced When a key is debounced key ready will pulse cnt en inst key debouncer bdf ipm decode0 Row select lines ego OUTPUT rowO OUTPUT row1 egt gt data 1 0 OUTPUT gt row2 eq3 OUTPUT gt row3 inst Select keypad row corresponding to given 2 bit address notDebouncing row multiplexing counter increments only when we are not debouncing high for 1ms and the encoded presses can be read from key data 6 0 when there is no kepress read from the current row This debouncer assumes that the clock runs at 20MHz If it doesn t the debounce and key repeat times will differ from the stated values The the 6 bit key output key data 5 0 is encoded as follows Project oscilloscope a 1 0 b 3 0 0 5 0 je QUIPUT key data 5 0 clk INPUT clock divider Bits 5 4 the index of the row from which the presses were read Ipm constanti clk in clk out e Bits 0 3 nibble representing the pressed keys in the row 1 pressed combine 200009 scale factor 31 0 inst4 inst2 Divide clock by 20000 so that Ipm compare2 it eycles every 1 ms comparel 0 5 T
50. ts of my hardware drivers y ifndef INTERFAC H define INTERFAC H library include files none local include files none constants keypad constants define KEY MENU 0x12 Menu define KEY UP 0x02 Up define KEY DOWN 0x22 Down Z fdefine KEY LEFT 0x11 lt Left gt ES define KEY RIGHT 0x14 Right define KEY ILLEGAL 0 illegal key display constants define SIZE X 640 size in the x dimension define SIZE Y 200 size in the y dimension define PIXEL WHITE 0 pixel off define PIXEL BLACK OxF pixel on scope parameters 1 1 define MIN DELAY 0 minimum trigger delay define MAX DELAY 50000 maximum trigger delay define MIN LEVEL 0 minimum trigger level in mV define MAX LEVEL 5000 maximum trigger level in mV sampling parameters define MAX SAMPLE SIZE 2400 maximum size of a sample in samples endif Page 1
51. ured Scale Scale Axes Display x and y axes along with trace Scale Grid Display x y grid along with the trace Scale Off Display the trace only Sweep Items are time quantities that specify the sweep rate or the time between successive samples options 100ns 200ns 500ns lus 245 Sus 10us 20us 50us 100us 200us 500us 1 ms 2ms 5ms 10ms 20ms Level 128 voltage quantities are given as choices for the trigger voltage level The levels are equally spaced from 0V to 5V Slope Slope Scope is triggered on a positive slope rising edge Slope Scope is triggered on a negative slope falling edge Delay Time quantities ranging between Oms and 1ms specify the time between the trigger and the start of the trace Julian Panetta TA Gabe Cohn Error Handling Algorithms Data Structures Limitations EE CS 52 Page 3 If a key not mapped to an interface action in the current mode of operation is pressed then no operation occurs No other errors are anticipated for the current implementation Once analog and serial input is implemented the following error handling will apply If a buffer overflow occurs on the signal input queue Signal Buffer Overflow is displayed in the lower left hand corner and no further input is accepted If a serial overflow occurs Serial Buffer Overflow is displayed If an error with framing parity a break or some other serial error occurs the messages
52. ut data static char sample_data SIZE_X sampling parameter functions int set_sample_rate long int rate Page 1 stubfncs c sample rate rate return SIZE X void set trigger int level int slope sample level level sample slope slope return void set delay long int delay sample delay delay return sampling functions void start sample int auto trigger get test sample sample rate SIZE X is sampling 1 unsigned char far sample done sample data Only return NULL once per sample if is sampling return NULL else is_sampling 0 return sample_data Page 2 interfac h KKK xx x k x x k kok k kok kok k kok k kok k Kk k K kok kok k kok k x k kk kok kok X kk kk kk kok k kk X ke X ke e x si x INTERFAC H s Interface Definitions Include File ur Digital Oscilloscope Project wi EE CS 52 ge mr JSKKKKKKKKKKKKAKKAKKKKKKAKKAK kk K kk AA This file contains the constants for interfacing between the C code and the assembly code hardware for the Digital Oscilloscope project This is a sample interface file to allow compilation of the c files Revision History 3 8 94 Glen George Initial revision 3 13 94 Glen George Updated comments 3 17 97 Glen George Added constant MAX SAMPLE SIZE and removed KEY UNUSED 11 04 08 Julian Panetta Updated to match constan
53. wg gt dock q OUTPUT LP d T ins ataa 10 0 A datab 14 V DI is high for clocks 12 to 17 anma nn tt prod Occurs once very 100 LPs si 9 pi DiCounter dataa 17 0 eeh Up counter databll 12 29 Jsclr modulus 192000 insiq5 AND2 LCDSignalFlipFlop DFF e clock q 17 0 DiCompareHigh data ue unsigned compare T ok a QUTPUT DI di T 552 Seel A A datab 18 d s FRToggle S R T LCDSignalFlipFlop clock OFF q data Toggle FR on fallinc clock q OUTPUT FR edge of DI Fi inst e There are 200 rows to transfer to the LCD in total Move to the next row each LP so the inverted LP signal is used as a clock RowCounter up counter clock modulus 200 Row Decoder RowAddressFlipFlo DFF q 7 0 RowCounter 7 0 ROW ADDR 7 0 data 7 0 clock 47 0 RADDRI7 0 Fi insf55 insi insiT Asynchronous clear is used because the clock To make rows of VRAM correspond to physical rows on the LCD Event will never occur upon reset Transfer rows in the order 0 100 1 101 etc Row increment clock Page 1 of 1 Revision Date November 2008 This design file implements a keypad debouncer The implementation debounces a keypress for 20ms Ipm counter1 and repeats a key every subseguent 300ms if the MOL user continues to hold it up counter b clock q 1 0 The debouncer supports multiple keypresses on a single row but does not respond to Simul
54. ypress has been made Performs a lookup to see if that key is valid E Returns the key if it is valid otherwise waits for another keypress Arguments None Return Values None Inputs Valid keys pressed by the user are returned by this routine Outputs None Registers Destroyed None Registers SAVED RESTORED Shared Variables None 7 key ready Read Boolean value recording the occurance of a keypress key data Read Byte recording the value of the keypress Data Structures Algorithms Look up table is used to validate keypresses CPPS KEP AR TA 7777577 7777 A R O A A O A A A R OA P A O A A A O eS A O OA A A O OA P A O OA A HS SFE R 7 PEPE PE PE getkey SAVE ssp no stack space is needed MOVIA 10 key ready MOVIA 13 key data MOVI 12 true wait LD 11 10 AND 11 12 Check key is ready IFS ce z BR wait wait until a key is ready NOP MOVI 11 false ST 10 11 Clear key ready keypad s LD 10 13 EXT8D 10 1 validate loop MOVIA 14 valid keys get key data put key data in low byte of return value valid key return it invalid key wait for a valid one not sure yet move to the next key entry LD 15 14 CMP 10 15 TES ce eq BR valid NOP CMPI 15 KEY ILLEGAL TES eq BR wait NOP BR validate loop ADDI 14 1 valid RESTRET t Za Ee EZE Za Ee Es
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