Z80185/195 USER`S MANUAL
Contents
1. dac aa at i EE EE lia sai Chapter 10 Parallel Ports TOM ANtroducti n mite tace a ai caute caca E au e ataca aa tutti i 10 2 Port A A et ace aaa a e eege Chapter 11 Z80185 Bidirectional Centronics P1284 Controller I Tea lee Introductionis Io 11 2 Bidirectional Centronics Registers 2000 iasa ata iia elada aa ana at na dal ee t122 Operating Modesa a id aaa ala Daia pia eat al c t leidos 11 23 Non 21284 Modest ora 11 24 Peripheral Inactive Mode Sadismo 1152 5 Host Compatible Mode 2 caseta oana ata uta t ad ani s calda d aa 11246 Host Nepouauon Model pala ia el aie aa ua aa 1127 Host Reserved Mode ii aa ta ad reda aa a eee Roe aaa dai ta 11 2 8 Peripheral Compatible Negotiation Mode AAA 11 29 Host Nibble Mode a he dt nara ee aa gate 11 2 10 Peripheral Nibble Mode xccrociiioriiici eee a e a i d 11 2 TL Ost Byte Mod EE RN E Peripheral Byte Mode sates cae e iata a ea aaa 11 213 Host RCP Forward Mode tii 11 2 14 Peripheral ECP Forward Modest caca aaa a alde 11213 Host ECP Reverse Mod s n pata nai n ada ia Ga ad alcatel ida 11 2 16 Peripheral BCP Reverse Mode cunda ii eds UM971800200 Z80185 195 USER S GUIDE PAGE Z80185 195 Zilog USER S GUIDE CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 12 ESCC 120 Introductions ns late 12 1 12 2 Elements of the ESCC Channel nai cau de lili li 12 1 122 le Baud Rate Generator A ri 12 3 12 2 2 Data Encodine Decoding A A AS 12 4 12 23 Digital Phase Locke2. 2 N S PA Z80185 195 USER S MANUAL TABLE OF CONTENTS CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 1 Z80185 Z80195 Overview A e dl e aia do at 1 1 E ENEE 1 1 1 3 General DESCLIPUO Ms tidad 1 1 1 4 Pin Descriptions sia iii asa au d d ua aaa dap aa cul pad 1 4 Ils RE 1 4 142 WAR T and ESTO Siena Si acc eee aa cata aaa a ee ASE te ad it data 1 5 VAL Multipleze d Siena ici ata ide Se z i d cess ce et d adu ed BA a ae 1 5 E EE EE o aaa a 1 5 1 4 5 Z80185 Parallel Ports E 1 5 146 Bidirectional Centronics PANS dias 1 6 1 47 System Control Signals siana cca a ia da dc i a iad pala ata ai os dala dan ada aio 1 6 125 480185 MPU Funcional D s ript n nde 1 7 kaft PRTC GG CONS ee EE 1 7 Chapter 2 Memory and Input Output Cycle Timing DA Are E EE 2 1 22 Basle A A 303 loa Sua AR te Cal at cl a a 2 1 2 3 A O plc el n aa duct net ie ate la na ea nee ae ele 2 8 23 1 Internal VO Registers cui da ege oase dl la ata ada dada ba a elada 2 8 E AIC REAGIW Tite VAM dt re a 2 8 Chapter 3 The Processor SrA Introduction asc cel ta Ge at Pau ed St lat an nal ata o aa Da ne i Date Da 3 1 3 2 CPU EE 3 1 3 2 T Z800 yersus 64 80 Compatibility A a a a al a apa 3 1 5 2 2 0 Control Register IGR ze oie ec ca da Ree Seed a er Be c 3 4 3 2 5 CPU Control Register CCR n a edatecaesdcatasesiaa ac odata a oa i ta ad da din ca sia a odata 3 5 3 2 4 System Configuration Register A al i aud a 3 7 3 3 On Chip ROM sii arie aia A i i al aaa pia at
3. 7 6 Read Register 5 12 7 7 Read Register 6 12 7 8 Read Register 7 12 7 9 Read Register 8 12 7 10 Read Register 9 12 7 11 Read Register 10 12 7 12 Read Register 11 12 7 13 Read Register 12 12 7 14 Read Register 13 12 7 15 Read Register 14 ESCC and 85C30 Only 12 7 16 Read Register 15 Chapter 13 Z80185 195 Instruction Set 13 1 Introduction 13 2 Operand Codes 13 3 Z80 Status Indicators Flags 13 3 1 Carry Flag C 13 3 2 Add Subtract Flag N 13 3 3 Parity Overflow Flag P V 13 3 4 Half Carry Flag H 13 3 5 Zero Flag Z 13 3 6 Sign Flag S 13 4 The Instruction Set Appendix A Opcode Maps A 1 Introduction Appendix B Z8018X Instruction Execution B 1 Bus and Control Signal Condition in each Z8018X Machine Cycle UM971800200 Z80185 195 USER S GUIDE PAGE vi Zilog 1998 by Zilog Inc All rights reserved No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog Inc The information in this document is subject to change without notice Devices sold by Zilog Inc are covered by warranty and patent indemnification provisions appearing in Zilog Inc Terms and Conditions of Sale only ZILOG INC MAKES NO WARRANTY EXPRESS STATUTORY IMPLIED OR BY DESCRIPTION REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT ZILOG INC MAKES NO WARRANTY
4. OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE UM971800200 Z80185 195 User s Manual Zilog Inc shall not be responsible for any errors that may appear in this document Zilog Inc makes no commitment to update or keep current the information contained in this document Zilog s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use Life support devices or systems are those which are intended for surgical implantation into the body or which sustains life whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user Zilog Inc 210 East Hacienda Ave Campbell CA 95008 6600 Telephone 408 370 8000 FAX 408 370 8056 Internet http www zilog com vii Z80185 195 User s Manual Zilog viii UM971800200
5. Write Register 5 Transmit Parameters and Controls manea eee e 12 49 12 6 7 Write Register 6 Sync Characters or SDLC Address Field oooonnccnnccinnninocononccannnnnncnnnonns 12 51 12 6 8 Write Register 7 Sync Character or SDLC Flag cnc cic dota ad aaa aa aaa da 12 52 12069 Write Resister 7 PEG sd ea 0 nad de aa la e aa a ale aa 12 52 12 6 10 Write Register 8 Transmit Buffer id 12 53 12 6 11 Write Register 9 Master Interrupt Control ssssesesessesseseseseseeeseesseserssresseseresressessresressesee 12 53 12 6 12 Write Register 10 Miscellaneous Tx Rx Control Bits manea eee en nana 12 54 12 6 13 Write Register 11 Clock Mode Control AA 12 56 12 6 14 Write Register 12 Lower Byte of Baud Rate Generator Time DOIR I EEE A da ta aia 12 57 12 6 15 Write Register 13 Upper Byte of Baud Rate Generator Time CORSO tt AA tat aa dl 12 58 12 6 16 Write Register 14 Miscellaneous Control Bits oonocnnnnccinncnnonononoconnnonnnononcnoncnnnn ea 12 58 12 6 17 Write Register 15 External Status Interrupt Control A 12 59 127 Read REZISTE ES A 12 60 12 7 1 Read Register 0 Transmit Receive Buffer Status atid External Status nai ea ee else Gade eects pi ata taia tates d aat 12 60 12 2 Read R sister nai st a papa aa ca da t d cad a ai ta at da uni tatea aa dada a ataca a da aib aa 12 61 ES Read RESIS AAA A a 12 62 UM971800200 v Zilog CHAPTER TITLE AND SUBSECTIONS 12 7 4 Read Register 3 12 7 5 Read Register 4 12
6. a 3 8 3 4 Chip Select Outputs iis Siva ds Na ew hie Se eect SRG EE E 3 9 3 3 EE 3 10 3 5 1 Wait States in VO Cycles siana na toata 0 na aaa a d a i dada bn a 3 10 3 5 2 Wait States in Interrupt Acknowledge Cycles ceccceessceeseceesceceeneeceseeeceenceceeeeecseeeeceeeeeenaeees 3 10 UM971800200 i Z80185 195 USER S MANUAL Zilog CHAPTER TITLE AND SUBSECTIONS PAGE 3 5 3 Wait States in Memory Space Cycles ceia otto a a Rl ta aaa ia a ee 3 11 3 6 HALT and Low Power Operating Modes ccceesscsesssecesseceseeceeseeceeaeeceeneeceeeeecseceeceeeeecsueeecseeeesaes 3 11 36 1 Normal Operation escala ul a a ti a lac et oil ti at 3 11 3 0 2 EEN WEE 3 11 30 39 LEER MOJE i ou e d E pe 3 12 36A AO EOP EE ee Ee Ee 3 13 3 09 SYSTEM STOP Mode cias 3 13 3 00 IDEE Mode p i o sa anca e ut a a int geen ta a a e 3 13 3 6 7 STANDBY Mode With or without Quick Recovery mean eee 3 15 Sef Fraps ANCE CS cc c Soe te datate a da aa ute se 3 17 3 7 1 INT TRAP Control Register ITC VO Address 34H men nenea eee 3 18 3 7 2 Interrupt Enabling and Disabling seceta ia dea a aaa Baia aa A A da a a 3 20 3 7 3 NMI Non Maskable Een 3 21 3 7 4 Maskable Int rrupt Level Q ni ia 3 22 3 19 Anterrupt Vector Low UL RES tS Geis iii a asa 3 26 3 1 0 Interrupt Edge Register mesi aaa stiati a a d dada catea a aa acd a aaa d da da ia anal 3 27 Def ah UN Ian INTZ Interrupts AA 3 27 3 7 8 DMA ASCI PRT and ESO Interrupts ne ea aa ea
7. a aia ada d da cada pda ada da d 3 30 Se Th REL DATS BUN WE 3 31 3 8 Memory Management Unit MMU none aia md t il dl da sica 3 31 3 8 1 MMU Register Description sense neta nisa ata a a d a adn ada aia ana 3 35 3 9 Dynamo RAM Refresh Control TE AA ac dau d 3 38 Chapter 4 Direct Memory Access E Eet He A mea Oar aa Da a ut ada 4 4 2 DMA VEL VILE ees 4 1 4 3 DMAC Block Diagta ado 4 2 4 4 IMAG Register eege Ee 4 3 4 4 1 DMA Source Address Register Channel O oooococnococnnocccooncccnononononanononcnononanononononnnoncnnncnconncnnnnnos 4 3 4 4 2 DMA Destination Address Register Channel O mean nea nne ee nnaee 4 3 4 4 3 DMA Byte Count Register Channel Q suicida 4 3 4 4 4 DMA Memory Address Register Channel 1 4 3 4 4 5 DMA IO Address Register Channel 1 ipsos d da aaa ga d a aaa ide ia plai 4 3 434 05 DMA Status Register DS TAT a A a ta a 4 4 447 DMA Mode Register DMODE urna iii arab dea ias 4 4 4 4 8 DMA WAIT Control Register DCNTL AA 4 6 ANIMACION 4 7 ASA Memory t Memory Channel EE 4 7 4 5 2 Memory TO Memory Mapped I O Channel Q nne ea 4 8 45 3 Channel TOMA EE 4 9 4 54 DMA Bus TIOS ii a et ad ac as anala lia ana adn aa 4 10 45 5 DMAC Channel Priority iio 4 10 45 6 DMAC and BUSREO BUSACK sica 4 10 4 5 7 DMAC Internal Interrupts A An 4 10 E a seen de head ate case a ial ada fag 4 1 4 5 9 DMAC and RESET iii sa daia a bad a iata aa a 4 11 i UM971800200 Z80185 195 USER S MANUAL Zi
8. d Loop cai cassantsdassdcvasaseananadssanas a di da da aaa dea dd ea aaa 12 6 12 24 Cl k Selection os e dad aa de dada bal oda St z iama des alia 12 11 12 23 Transmit Data Path inci iia 12 13 12 20 Receive Data EE 12 13 12 3 Serial Modes and EE 12 15 12 3 1 Asynchronous Mode id taia ce E aia d adina n a a ata 12 15 12 3 2 Character Oriented Synchronous Modes icsiscsssseccesscsvetestvassvccdassctesacavavecaeea uhessdaatcenseadebes aeons 12 19 12 3 3 Bit Oriented Synchronous SDLC HDLC Mode ceea enma enma aaa ea 12 19 12 4 Register Addressing ee Eege ie Ida at anl ala on a 12 31 123 A aaa aa ana e bata al a ca lata a a aaa da da 12 32 12 5 1 Interrupt Control cca s po aia A A dada a de dt a ua ia d le a 12 33 12 3 2 Daisy Chato Resolution EE 12 34 12 3 3 Interrupt Acknowledge ss coana acea ceat ina 12 37 12 54 The Receiver Interrupt ET 12 37 12 5 5 Transmit Interrupts and Transmit Buffer Empty Bit nenea eee en 12 40 12 20 NEEN ee e EE 12 42 12 6 eh 12 44 12 6 1 Write Register 0 Command Register isis al ze a dada aia aa ed ala i aa 12 44 12 6 2 Write Register 1 Transmit Receive Interrupt and Data Transfer Mode Definition mea eee eee eee eee eee aaa aaa anna 12 46 12 6 3 Write Register Cotten A teas A 12 47 12 6 4 Write Register 3 Receive Parameters and Control isis decta oaia ia dai ed aaa dead 12 47 12 6 5 Write Register 4 Transmit Receive Miscellaneous Pa rameters and Mode scie anca ata a ap tt 12 48 12 6 6
9. io aa a aaa aan data ac aa eer eases 6 2 G32 ESO COMO SAS Re Osetia hry data o ellos 6 2 04 CSO A A 6 3 6 3 CSI O Operation Timing Notes scania oa aa da nins aa i e d a iai as ia a e da anna 6 4 6 6 ESTO Operation INGLES see ase da ace ali ot ole Da ges aan as rel as 6 6 Gt ESO and RESET ii ee 6 6 Chapter 7 Programmable Reload Timers PRTs Teele MINER E O 7 1 TPRI A A n deca con tied anda ala eure aa totaal aed att aa al ae 7 1 TA ERE REGISTER DG SCION EEE aaa aaa ala e dace oe sua yet alia at E E E ET 7 2 7 341 Timer Data Register nia d d ti atu dia d at dE 7 2 13 2 FUMED Reload EE 7 2 7 3 3 Timer Control Register TER assets a dat Ne ca a diana ata n a aia a a aa 7 2 TA sal TIMIN A A aca 7 3 A RO 7 4 TOPR Tand RESET reene Ech 7 4 A PRL Operation Notes ss aula a cana e la a a ba ma st 7 4 ii UM971800200 Zilog CHAPTER TITLE AND SUBSECTIONS Chapter 8 Counter Timer Channels CTCS Biz MRO GUCUION esec aaa a i rusa lo 8 2 O AQOresses asia ia ada da d i d d at a ca da d d dd a a A Ai pai aaa c a aa ga ab aliat OGRE PISTOLS A A a a li ala aati A 8 4 1 Control Register cun aci add ceea d da i ea e di at d i d lu a ia 9 4 2 Time Constant REDISUEIE iO at at a ca ria c 8 4 3 Interrupt Vector Register cenusa ioana iata cane fat n i ai 0 alui Zeen E IS A A rai 8 3 CTE O ad atar lio i d SE EEC Interrupts di Chapter 9 Watch Dog Timer 91 Karger Te EE ke MEA 9 2 1 WDT Master Register e pat et pna a
10. log CHAPTER TITLE AND SUBSECTIONS PAGE Chapter 5 Asynchronous Serial Communication Interface ASCIs ES base LETSATSI DEE 5 1 LOVE VIEW iasi ca faces o aaa vines os e gues A AS i a be lease ideas as 5 1 Dio ASCL Block Dia Or anti ace ca petala cc aaa ced ice di tl ua aa 5 1 SA ASCL Register Descrip n i ceteris oc aa dea a al aaa i tied de ai e pna 5 3 5 4 1 ASCI Transmit Shift Register 0 1 TSR Di ae ela aa ad daia dana a aa a ac dada 5 3 5 42 ASCI Transmit Data Register 0 ninia add a e 5 3 5 4 3 ASCI Receive Shift Register 0 1 RSR 1 EE 5 3 344 ASCI Recerve Data ELFO O lovin 5 3 DA Ee attert e el eae A A ni al ss 5 3 5 4 6 ASCI Status Register 0 1 STATO 1 Ra 5 3 5 4 7 ASCI Control Register A0 LCN TAD iii 5 4 5 4 8 ASCI Control Register BO 1 CNIIBO 1 vistosidad a hav ao alea ia 5 6 5 4 9 ASCI Extension Control Register ASEXTO 1 oooonncccnnncccnoncccconcncnoncnonnnononnnononnnnnononcnnnnnccnnnnnnos 5 7 5410 ASCI Time EE 5 8 5 5 Clocking Summary reia e A 5 8 MORE Control o O ia ara 5 9 3l Ss Pel TILER URES eats tee Sec cette nt ro tei ae ata iulia A ate le ole e A Or aia sagt ete Saua 5 10 5 8 ASCI DMAC Operation ses seaca an ct ada aa 5 11 9 9 ASC lands EEN RE 5 11 Chapter 6 Clocked Serial I O Port CSIO 6 1 Introduction sola Ba i au Dal a zau al 6 1 6 2 CSI O Block Diagram ss cucoana caca dai ua a a io do aa e ed d 6 1 IAP EE EE 6 2 6 3 1 510 Transmit Receive Data Register pc acas
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