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Value line, 24 MHz STM8S 8-bit MCU, 64 Kbytes Flash

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1. Table 8 General hardware register map continued Address Block Register label Register name di 0x00 5300 TIM2 CR1 TIM2 control register 1 0x00 0x00 5301 TIM2 IER TIM2 interrupt enable register 0x00 0x00 5302 TIM2_SR1 TIM2 status register 1 0x00 0x00 5303 TIM2_SR2 TIM2 status register 2 0x00 0x00 5304 TIM2_EGR TIM2 event generation register 0x00 0x00 5305 TIM2 CCMR1 TIM2 capture compare mode register 1 0x00 0x00 5306 TIM2 CCMR2 TIM2 capture compare mode register 2 0x00 0x00 5307 TIM2 CCMR3 TIM2 capture compare mode register 3 0x00 0x00 5308 TIM2 CCER1 TIM2 capture compare enable register 1 0x00 0x00 5309 TIM2 CCER2 TIM2 capture compare enable register 2 0x00 0x00 530A TIM2 TIM2 CNTRH TIM2 counter high 0x00 0x00 530B TIM2 CNTRL TIM2 counter low 0x00 00 530COx TIM2 PSCR TIM2 prescaler register 0x00 0x00 530D TIM2 ARRH TIM2 auto reload register high OxFF 0x00 530E TIM2 ARRL TIM2 auto reload register low OxFF 0x00 530F TIM2 CCR1H TIM2 capture compare register 1 high 0x00 0x00 5310 TIM2 CCR1L TIM2 capture compare register 1 low 0x00 0x00 5311 TIM2 CCR2H TIM2 capture compare reg 2 high 0x00 0x00 5312 TIM2 CCR2L TIM2 capture compare register 2 low 0x00 0x00 5313 TIM2 CCR3H TIM2 capture compare register 3 high 0x00 0x00 5314 TIM2 CCR3L TIM2 capture compare register 3 low 0x00 UE Reserved area 11 bytes 0x00 5320 TIM3 CR1 TIM3 control register 1 0x00 0x00 5321 TIM3 IER TIMS interr
2. 5 E 3 un alternate sla 22 sjaje z9 function after remap 5 F 5A O o a5 option bit LI SPI master 33 PC6 SPL MOSI l O X X X Hs O3 X X Port C6 out slave in SPI master in 34 PC7 SPI MISO O X X X HS O3 X X Port C7 slave out 35 PGO o X x O1 X Port GO 36 PG1 olx X O1 X Port G1 37 PE3 TIM1 BKIN vo x x x 01 X X Port e3 ine 1 break input 38 PE2 I2C SDA O X X 01 T2 Port E2 I2C data 39 PE1 2C SCL O X X O1 T2 Port E1 I2C clock 40 PEUCLK CCO vo x X x Hslos X X Port Eo Configurable clock output TIM1 BKIN Timer 3 AFR3 41 PDO TIM3_CH2 VO X X X HS 03 X X Port DO CLK CCO AFR2 42 PDijSWIM vol x x X Hsloa x X Port p1 SWIM data interface 43 PD2 TIMa CH1 vo x X X HS O3 X X Port p2 8r 3 TMA CHS channel 1 AFR1 Timer 2 ADC ETR 44 PD3 TIM2_CH2 O X X X HS O3 X X Port D3 1 AFRO PD4 TIM2_CH1 B Timer 2 BEEP output 45 rp VO X X X HS 03 X X Port D4 AFR7 46 PD5 UART3 TX O x x X 01 X X Port D5 VARTS data transmit PD6 UART3 data 47 UART3 AXI vo x x xX O1 X X Port D6 48 PD7 TLI vo x x x O1 X X Port pz 0P level interrupt 1 The default state of UART1 RX and UARTS RX pins is controlled by the ROM bootloader These pins are pulled up as part of the bootloader activation process and returned to the floating stat
3. liliis nn 84 Table 51 Document revision history e n 89 6 90 Doc ID 022171 Rev 3 ky STM8S007C8 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 STM8S007xx value line block diagram sss 10 Flash memory organisation ce rn 13 LQFP 48 pin pinout ie maa a e a aia E O E E E E a i 21 Memory map m 26 Supply current measurement conditions e seua 42 Pin loading conditions s eR I n 43 Pin input voltage sse sees ta pasko eek RR cR ORE ee e kvine E ERR Pad kor n 43 fcPUmax VETSUS VDD occ beeen ebb eee ee eee ee eese nis 47 External capacitoICpgxr s ssssssssssesesessesesesesessesisoso 47 Typ IDD RUN VS Vpp HSI RC OSC fcpu 1T6MHZ 54 Typ IDD WFN VS Vpp HSI RC OSC fcpu zonae TITT TETTE EI 54 HSE external clock source ssssesssssesassessassvo 55 HSE oscillatorcircuitdiagram s ssssssssssssussso 56 Typical HSI frequen
4. 48 90 Doc ID 022171 Rev 3 STM8S007C8 Electrical characteristics Table 19 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit i i T HSE crystal osc 24 MHz 4 0 24 z i ui HSE user ext clock 24 MHz 3 7 7 3 HSE crystal osc 16 MHz 2 9 Supply sumentia fcpu fMASTER 16 MHz HSE user ext clock 16 MHz 2 7 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 cede ted HSE user ext clock 16 MHz 1 2 4 1 execute fcpu fuAsTER 28 125 kHz from RAM HSI RC osc 16 MHz 1 0 1 3 fcpu fuasTER 128 15 625 kHz HSI RC osc 16MHz 8 0 55 fcpu TMASTER 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN mA R TT HSE crystal osc 24 MHz 11 0 f 24 z LM HSE user ext clock 24 MHz 10 8 18 0 HSE crystal osc 16 MHz 8 4 Supply 15 2 SUNENKIS fcpu fMASTER 16 MHz HSE user ext clock 16 MHz 8 2 5 run mode HSI RC osc 16 MHz 8 1 13 2 code 2 executed CPU fMAsTER 2 MHz HSI RC osc 16 MHz 8 1 5 from Flash fopu fMAsSTER 1 28 125 kHz HSI RC osc 16 MHz 1 1 fcpu fuasTER 128 15 625 kHz HSI RC osc 16 MHz 8 0 6 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration ky Doc ID 022171 Rev 3 49 90 Electrical characteristics STM8S00
5. 9 1 6 Loading capacitor ss ere 43 9 1 7 Pin input voltage irrs iis srnre ri KARE Er EER ner EREEREER 43 9 2 Absolute maximum ratings 44 9 3 Operating conditions sessassitautri RE ERE RETRRESE ERES Ere 46 9 3 1 VCAP external capacitor s eee 47 9 3 2 Supply current characteristics 0 0 0 cece eee 48 9 3 3 External clock sources and timing characteristics 55 9 3 4 Internal clock sources and timing characteristics 57 9 3 5 Memory characteristics lile 59 9 3 6 I O port pin characteristios s ssssssso 60 9 3 7 Reset pin characteristics s eee 68 9 3 8 SPI serial peripheral interface les eee 71 9 3 9 IC interface characteristics sss segas ISIS ununun dre ges 74 9 3 10 10 bit ADC characteristics llle 76 9 311 EMCcharacteristios i s s s ren 79 Package characteristics ss 82 10 1 Package mechanical data eaea 83 10 2 Thermal characteristics clle 84 10 2 1 Reference document sssssss s 84 10 2 2 Selecting the producttemperaturerange 85 STM8 development tools sssssssss 86 11 1 Emulation and in circuit debugging tools 86 MGA BOMMWATETODIS 2 35285
6. KY STM8S007C8 Value line 24 MHz STM8S 8 bit MCU 64 Kbytes Flash true data EEPROM 10 bit ADC timers 2 UARTs SPI I2C Features m Core Max fcpu up to 24 MHz O wait states fcpu lt 16 MHz Advanced STMS core with Harvard Datasheet production data LQFP48 7x7 architecture and 3 stage pipeline a Extended instruction set Max 20 MIPS 24 MHz m Memories Program 64 Kbytes Flash data retention 20 years at 55 C after 100 cycles Data 128 bytes true data EEPROM endurance 100 kcycles E RAM 6 Kbytes m Clock reset and supply management 2 95 to 5 5 V operating voltage Low power crystal resonator oscillator External clock input Internal user trimmable 16 MHz RC Internal low power 128 kHz RC Clock security system with clock monitor Wait active halt amp halt low power modes Peripheral clocks switched off individually Permanently active low consumption power on and power down reset m interrupt management Nested interrupt controller with 32 interrupts Up to 37 external interrupts on 6 vectors m Timers May 2012 2x 16 bit general purpose timers with 2 3 CAPCOM channels IC OC or PWM Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 8 bit basic timer with 8 bit prescaler Auto wakeup timer Window watchdog independent watchdog Doc ID 022171 Rev 3 Communications interfaces
7. MS19405V1 MS19406V1 Doc ID 022171 Rev 3 STM8S007C8 Electrical characteristics Figure 26 Typ Vpp Von Vpp 3 3 V standard ports 3 4 lon mA MS19407V1 Figure 27 Typ Vpp Vou 9 Vpp 5 V high sink ports 0 5 10 15 20 25 lon mA MS19408V1 ky Doc ID 022171 Rev 3 67 90 Electrical characteristics STM8S007C8 Figure 28 Typ Vpp Von Vpp 3 3 V high sink ports 0 2 4 6 8 10 12 14 lon mA MS19409V1 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 39 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit ViLNAST NRST Input low level voltage u 0 3 V 0 3 x Vpp Vinwrst NRST Input high level voltage 0 7 x Vpp Vpp 0 3 V VoL NAsT NRST Output low level voltage 1 loL 2 mA 0 5 Reuwrst NRST Pull up resistor 2 30 55 80 kQ rp unsr NRST Input filtered pulse 9 75 ns tINFP NAST NRST Input not filtered pulse 9 500 ns top vrst NRST output pulse l 15 us 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production a 68 90 Doc ID 022171 Rev 3 STM8S007C8 Electrical characteristics Figure 29 Typical NRST Vj and Vj
8. Timer size Prescaler F Ants z mode channels outputs trigger onization bits m chaining TIM1 16 Any integer from 1 to 65536 Up down 4 3 Yes TIM2 16 Any power of 2 from 1 to 32768 Up 3 0 No o TIM3 16 Any power of 2 from 1 to 32768 Up 2 0 No TIM4 8 Any power of 2 from 1 to 128 Up 0 0 No 4 13 Analog to digital converter ADC2 STM8S007xx value line products contain a 10 bit successive approximation A D converter ADC2 with up to 10 multiplexed input channels and the following main features e Input voltage range O to Vppa e Conversion time 14 clock cycles e Single and continuous modes e External trigger input e Trigger from TIM1 TRGO e Endofconversion EOC interrupt 4 14 Communication interfaces The following communication interfaces are implemented UARTT1 Full feature UART SPI emulation LIN2 1 master capability Smartcard mode IrDA mode single wire mode UARTS Full feature UART LIN2 1 master slave capability SPI Full and half duplex 10 Mbit s I2C Up to 400 Kbit s Doc ID 022171 Rev 3 17 90 Product overview STM8S007C8 4 14 1 UART1 Main features One Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN master mode Single wire half duplex mode Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fcp 16 an
9. UART with clock output for synchronous operation LIN master mode UART with LIN 2 1 compliant master slave modes and automatic resynchronization SPI interface up to 10 Mbit s I2C interface up to 400 Kbit s 10 bit ADC with up to 16 channels m I Os 38 I Os including 16 high sink outputs Highly robust I O design immune against current injection Development support Single wire interface module SWIM and debug module DM 1 90 This is information on a product in full production www st com Contents STM8S007C8 Contents 1 Introductio asa ska omen Kak ARA Da c De a a D D melan 8 2 DeserpHOH 22229 xxm etu TRACER RCRCR KAPAL Ron qo l koka ISR eens 9 3 Block diagram suu sea ka 616 us ENNA RR rao oa 6 WG ee bebe ara dad 10 4 Product overview iss mia aaa am ce ee ee m e m eel 11 4 1 Central processing unit STM8 00 cee else 11 4 2 Single wire interface module SWIM and debug module DM 12 4 3 Interrupt controller aus iio cy nde Er bI AA Re deba 12 4 4 Flash program and data EEPROM memory 12 45 CIDOEKGONIONDI sss ou savas PRI ree eR Sensei Rad Eg rika saoo 14 4 6 Power management s sssssssssso 15 4 7 Watchdog timers essem RR RRRREXQUERE REGI ERR XA EREXA AX Rd 15 4 8 Auto wakeup counter sssssssssvo 16 4 9 Beeper D Oe 16 4 10 TIM1 16 bit advanced control timer 16 4
10. Electrostatic discharge voltage TA 25 C conforming to VESD CDM Charge device model JESD22 C101 y 1000 M 1 Data based on characterization results not tested in production Doc ID 022171 Rev 3 ky STM8S007C8 Electrical characteristics Static latch up Two complementary static tests are required on 10 parts to assess the latch up performance e A supply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable I O pin is performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table48 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C A LU Static latch up class Ta 85 C A 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international standard Doc ID 022171 Rev3 81 90 Package characteristics STM8S007C8 10 82 90 Package characteristics To meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST t
11. Reset state Bold X pin state after internal reset release Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release Table 5 LQFP48 pin description Input Output E 5 2 v Alternate Ke E So 5 29 parauli function 3 Pin name E Eg 3 3r alternate E riza 2 2 Solo t function after remap S 5a ojaj 5 option bit ui 1 NRST O X Reset 2 PA1 OSCIN vo x x O1 X X Port a1 Resonator crystal in 3 PAZ OSCOUT o X X X O1 x x Port az Resonator crystal out 4 Vasto 1 S I O ground 5 Vas S Digital ground 6 VCAP S 1 8 V regulator capacitor 7 Vpp S Digital power supply 8 Vppio 1 S I O power supply Timer 2 TIM3 CH1 9 PA3 TIM2 CH3 O X X X O1 X X Port A3 E AFR1 10 PA4 UART1 RX VO X X X HS O8 X X Port A4 UART1 receive 11 PAS UART4 TX lo x X X HS O3 X X Port As VARTI transmit UART1 12 PAG UART1 CK O X X X HS O3 X X Port A6 synchronous clock 13 VppA S Analog power supply 22 90 Doc ID 022171 Rev 3 a STM8S007C8 Pinouts and pin description Table 5 LQFP48 pin description continued Input Output o oF 2 amp o Default Anernate E So Ss c9 function 3 Pin name S g E E 3 3r alternate Fflz a 3 2 8 9 g os function fter remap 5 F 5A O
12. code UBC NOPT1 NUBC 7 0 FFh 4803h Alternate OPT2 AFR7 AFR6 AFR5 Reserved AFR3 AFR2 AFR1 AFRO 00h function 4804n remapping NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO FFh AFR LSI IWDG WWDG WWDG 4805h OPT3 Reserved 00h Watchdog _EN _HW _HW HALT option NLSI NIWDG NWWDG NWWDG 4806h NOPT3 Reserved EN HW LW HALT FFh EXT CKAWU PRS PRS 4807h OPT4 Reserved 00h CLK SEL C1 CO Clock option NEXT NCKAWUS NPR NPR 4808h NOPT4 Reserved FFh CLK EL SC1 SCO 4809h HSE clock OPT5 HSECNT 7 0 00h 480Ah Startup NOPT5 NHSECNT 7 0 FFh 480Bh OPT6 Reserved 00h Reserved 480Ch NOPT6 Reserved FFh 480Dh Flash wait OPT7 Reserved Wait state 00h 480Eh States NOPT7 Reserved Nwait state FFh 487Eh OPTBL BL 7 0 00h Bootloader 487Fh NOPTBL NBL 7 0 FFh 38 90 Doc ID 022171 Rev 3 ky STM8S007C8 Option bytes Table 12 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to the family reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 UBC 7 0 User boot code area 0x00 no UBC no write protection 0x01 Pages 0 to 1 defined as UBC memory write protected 0x02 Pages 0 to 3 defined as UBC memory write protected 0x03 Pages 0 to 4 defined as UBC memory write protected OxFE Pages O0 to 255 defined as UBC memory write protected OxFF Reserved
13. o a5 option bit Lu 14 Vasa S Analog ground 15 PB7 AIN7 Vx x x O1 x X Port B7 8log input 7 16 PB6 AING vol x x x O1 X X Port Be 8log input 6 Analog IC SDA 17 PB5 AIN5 JO X X X O1 X X Port B5 input 5 AFR6 Analog IC SCL 18 PB4 AIN4 VO X X X O1 X X Port BA input 4 AFR6 Analog TIM1 ETR 19 PB3 AIN3 JO X X X O1 X X Port B3 input 3 AFR5 Analo 20 PB2 AIN2 V OXX x O1 X X Port B2 NAY CH3N input 2 AFR5 Analo TIMI 21 PB1 AIN1 vo x x x O1 X X Port B1 MA CH2N input 1 AFR5 Analo HM 22 PBO AINO JO X X X O1 X X Port BO 9 CHIN input O AFR5 23 PE7 AIN8 O X O1 Port E7 Analog input 8 24 PEG AIN9 O X X X O1 X Port E6 Analog input 9 SPI 25 PE5 SPI NSS O X X X O1 X X Port E5 master slave select 26 PCi TIM cH1 vol X X X Hslos x X Port ci er 1 channel 1 27 pceartim1_cH2 lio x X X HS O8 X X Port ca er 1 channel 2 28 PC3 TIMi cH3 O X X X HS O3 X X Port ca mer channel 3 29 PC4 TIMM cHa O x X X Hslos X X Port ca Timer channel 4 30 PC5 SPI SCK O X X X HS O3 X X Port C5 SPI clock 31 Vssio 2 S O ground 32 Vppio 2 S I O power supply ky Doc ID 022171 Rev 3 23 90 Pinouts and pin description STM8S007C8 Table 5 LQFP48 pin description continued Input Output a 5 oF 2 Bl 50 Default AREIS Slo 3 co function 3 Pin name gt
14. vs Vpp E 3 temperatures MS19410V1 Figure 30 Typical NRST pull up resistance vs Vpp 3 temperatures BR AB a Qi Q o a o a eo NRESET Pull Up resistance k11 wo a MS19411V1 Doc ID 022171 Rev 3 69 90 Electrical characteristics STM8S007C8 70 90 Figure 31 Typical NRST pull up current vs Vpp E 3 temperatures NRESET Pull Up current uA ai15069b The reset network shown in Figure 32 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below the Vj max level specified in Table 35 Otherwise the reset is not taken into account internally For power consumption sensitive applications the capacity of the external reset capacitor can be reduced to limit charge discharge current If the NRST signal is used to reset the external circuitry care must be taken of the charge discharge time of the external capacitor to fulfill the external device s reset timing conditions The minimum recommended capacity is 10 nF Figure 32 Recommended reset pin protection Vpp STM8 External NRST Internal reset reset o Filter circuit 0 1luF optional Doc ID 022171 Rev 3 ky STM8S007C8 Electrical characteristics 9 3 8 SPI serial peripheral interface Unless otherwise specified the parameters given i
15. 27 General hardware register map aana 29 CPU SWIM debug module interrupt controller registers 35 Interrupt mapping 66 RR RR IRR HR III 3 t n 37 Option Dyt s ccs oe ed anka Ku ae de APO RUE et er an CR PESE RU d 38 Option byte desocription ss rr 39 Voltage characteristiois ss tkir nn 44 Currentcharacteristios s tetas 45 Thermal characteristics ss sssssssssssesssesssseso 45 General operating conditions sssssssssssssssesso 46 Operating conditions at power up power down ssssssssis e 47 Total current consumption with code execution in run mode at Vpp 2 5 V 48 Total current consumption with code execution in run mode at Vpp 3 3 V 49 Total current consumption in wait mode at Vpp25V eee 50 Total current consumption in wait mode at Vpp 3 3V 0 eee eee 50 Total current consumption in active halt mode at Vpp 5 V Ta 40t085 C 51 Total current consumption in active halt mode at Vpp 3 3V a 51 Total current consumption in halt mode at Vpp 5 V Ta 40 to 85 C 52 Total current consumption in halt mode at Vpp 3 3V 0 0 000 52 Wakeuptimes sssssssssssssessssessssesrcosoo 52 Total current consumption and timing in forced reset state 53 Peripheral curr
16. 501E PG_ODR Port G data output latch register 0x00 0x00 501F PG_IDR Port G input pin value register 0x00 0x00 5020 Port G PG DDR Port G data direction register 0x00 0x00 5021 PG CR1 Port G control register 1 0x00 0x00 5022 PG CR2 Port G control register 2 0x00 0x00 5023 PH ODR Port H data output latch register 0x00 0x00 5024 PH IDR Port H input pin value register 0x00 0x00 5025 Port H PH DDR Port H data direction register 0x00 0x00 5026 PH CR1 Port H control register 1 0x00 0x00 5027 PH CR2 Port H control register 2 0x00 0x00 5028 PI ODR Port data output latch register 0x00 0x00 5029 PI IDR Port input pin value register 0x00 0x00 502A Port PI DDR Port data direction register 0x00 0x00 502B PI CRI Port control register 1 0x00 0x00 502C PI CR2 Port control register 2 0x00 28 90 Doc ID 022171 Rev 3 I STM8S007C8 Memory and register map Table 8 General hardware register map Address Block Register label Register name heset status 0x00 5050 to 0x00 5059 Reserved area 10 bytes 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash complementary control register 2 OxFF 0x00 505D Flash FLASH FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary
17. 8054 20 UART3 Tx complete 0x00 8058 21 UART3 Receive register DATA FULL 0x00 805C 22 ADC2 ADC2 end of conversion 0x00 8060 23 TIM4 TIM4 update overflow 0x00 8064 24 Flash EOP WR PG DIS 0x00 8068 Reserved 0x00 806C to 0x00 807C 1 Except PA1 ky Doc ID 022171 Rev 3 37 90 Option bytes STM8S007C8 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device They are stored in a dedicated block of the memory Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 11 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP option that can only be modified in ICP mode via SWIM Refer to the STM8S Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 11 Option bytes Option bits Factory Option Option Addr s b HG default 6 5 4 3 2 1 0 setting Read out 4800h protection OPTO ROP 7 0 00h ROP 4801h User boot OPT1 UBC 7 0 00h 4802h
18. Min Unit VRM Data retention mode Halt mode or reset Vir max V 1 Minimum supply voltage without losing data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to Table 17 on page 47 for the value of Vir may Flash program memory data EEPROM memory General conditions Ta 40 to 85 C Table34 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage all modes execution write erase fopu lt TEMPE 2 95 pig id Vpp Standard programming time including erase for byte word block 6 0 6 6 ms hong 1 byte 4 bytes 128 bytes Fast programming time for 1 block 128 bytes lerase Erase time for 1 block 128 bytes 3 0 3 3 ms 3 0 3 3 ms Erase write cycles 100 program memory Ty 85 C cycles 100 k Erase write cycles data memory Data retention program memory after 100 erase write cycles at 20 Ta 85 C TRET 55 C trer Data retention data memory after 10 k erase write cycles at Ta 85 C 20 years Data retention data memory after 100 k erase write cycles at Ta 85 C TRer 89 Supply current Flash programming or erasing for 1 to 128 bytes 2 0 mA Ipp Data based on characterization results not tested in production 2 The physical gr
19. Note Refer to the family reference manual RM0016 section on Flash EEPROM write protection for more details OPT2 AFR7Alternate function remapping option 7 0 Port D4 alternate function TIM2_CH1 1 Port D4 alternate function BEEP AFR6 Alternate function remapping option 6 0 Port B5 alternate function AIN5 port B4 alternate function AIN4 1 Port B5 alternate function I2C SDA port B4 alternate function FG SCL AFR5 Alternate function remapping option 5 0 Port B3 alternate function AIN3 port B2 alternate function AIN2 port B1 alternate function AIN1 port BO alternate function AINO 1 Port B3 alternate function TIM1 ETR port B2 alternate function TIM1 CHSN port B1 alternate function TIM1 CHAN port BO alternate function TIMI CH1N AFR4 Alternate function remapping option 4 Reserved AFR3 Alternate function remapping option 3 0 Port DO alternate function TIM3 CH2 1 Port DO alternate function TIM1 BKIN AFR2 Alternate function remapping option 2 O Port DO alternate function TIM3 CH2 1 Port DO alternate function CLK CCO Note AFR2 option has priority over AFR3 if both are activated AFR1 Alternate function remapping option 1 0 Port A3 alternate function TIM2 CH3 port D2 alternate function TIM3 CH1 1 Port A3 alternate function TIM3 CH1 port D2 alternate function TIM2 CH3 AFRO Alternate function remapping option O 0 Port D3 alternate function TIM2_CH2 1 Port D3 alternat
20. analog input voltage have no effect on the conversion result Values for the sample clock tg depend on programming Doc ID 022171 Rev 3 I STM8S007C8 Electrical characteristics Table 43 ADC accuracy with Ran lt 10 KO Vppa 5 V Symbol Parameter Conditions Typ Max fapc 2 MHz 1 2 5 IE Total unadjusted error fApc 4 MHz 14 3 fapo 6 MHz 1 6 3 5 fapo 2 MHz 0 6 2 IEg Offset error fApc 4 MHz 1 1 2 5 fapc 6 MHz 1 2 2 5 fapc 2 MHz 0 2 2 IEgl Gain error fapo 4 MHz 0 6 2 5 fApc 6 MHz 0 8 2 5 fApc 2 MHz 0 7 1 5 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fApc 6 MHz 0 8 1 5 fapo 2 MHz 0 6 1 5 IE I Integral linearity error fapc 4 MHz 0 6 1 5 fApc 6 MHz 0 6 1 5 Unit LSB ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for liny pin and XliNj piN in Section 9 3 6 does not affect the ADC accuracy Table 44 ADC accuracy with Rain lt 10 kQ RAIN VppA 3 3 V Symbol Parameter Conditions Ty
21. compare mode register 3 0x00 0x00 525B TIMI CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1 CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1 CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIMI CNTRH TIM1 counter high 0x00 0x00 525F TIMI CNTRL TIM1 counter low 0x00 0x00 5260 i TIM1 PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1 PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1 ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1 ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1 RCR TIM1 repetition counter register 0x00 0x00 5265 TIMI CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIMI CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIMI CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1 CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIMI CCRAH TIM1 capture compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1 OISR TIM1 output idle state register 0x00 o ee Reserved area 147 bytes 32 90 Doc ID 022171 Rev 3 KYT STM8S007C8 Memory and register map
22. line provide the following benefits reduced system cost performance robustness short development cycles and product longevity The system cost is reduced thanks to a true data EEPROM for up to 100 k write erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Device performance is ensured by 20 MIPS at 24 MHz CPU clock frequency and enhanced characteristics which include robust I O independent watchdogs with a separate clock source and a clock security system Short development cycles are guaranteed due to application scalability across a common family product architecture with compatible pinout memory map and modular peripherals Full documentation is offered with a wide choice of development tools Product longevity is ensured in the STM8S family thanks to their advanced core which is made in a state of the art technology for applications with 2 95 V to 5 5 V operating supply Table 1 STM8S007xx value line features Features STM8S007C8 Pin count 48 Max number of GPIOs I O 38 External interrupt pins 35 Timer CAPCOM channels 9 Timer complementary outputs 3 A D converter channels 10 High sink I Os 16 High density Flash program memory 64 Kbytes Data EEPROM 128 bytes RAM 6 Kbytes Doc ID 022171 Rev 3 9 90 Block diagram STM8S007C8 3 10 90 Block diagram Figure 1 STM8S007xx value line block diagram Single wir
23. protected during IAP 1 page steps 64 Kbytes Flash program memory Program memory area Write access possible for AP Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller SI Doc ID 022171 Rev 3 13 90 Product overview STM8S007C8 4 5 14 90 Clock controller The clock controller distributes the system clock fmaster coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features Clock prescaler To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safeclock switching Clock sources can be changed safely on the fly in run mode through a configuration register The clock signal is not switched until the new clock Source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core individual peripherals or memory
24. protection register OxFF 0x00 505F FLASH IAPSR Flash in application programming status Ox00 register 0x00 5060 to 0x00 5061 Reserved area 2 bytes 0x00 5062 Flash FLASH PUKR Flash Program memory Unprotection 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area 59 bytes 0x00 50A0 me EXTI CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area 17 bytes 0x00 50B3 RST RST_SR Reset status register oxxx 0x00 50B4 to 0x00 50BF Reserved area 12 bytes 0x00 50CO rfe CLK ICKR Internal clock control register 0x01 0x00 50C1 CLK_ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 0x00 50C3 CLK_CMSR Clock master status register OxE1 0x00 5004 CLK_SWR Clock master switch register OxE1 0x00 50C5 CLK_SWCR Clock switch control register OxXX 0x00 50C6 T CLK CKDIVR Clock divider register 0x18 0x00 50C7 CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte ky Doc ID 022171 Rev 3 29 90 Memory and register
25. to ambient thermal resistance in C W Ppmax is the sum of Pintmax and Pyomax PDmax PINTmax Piomax e Pintmax is the product of Ipp and Vpp expressed in Watts This is the maximum chip internal power Pyomax represents the maximum power dissipation on output pins where Pyomax Vor lon Z Vpp VoH loH and taking account of the actual Vo lo and Volon of the I Os at low and high level in the application Table 50 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Doc ID 022171 Rev 3 ky STM8S007C8 Package characteristics 10 2 2 Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Figure 40 STM8S007xx value line ordering information scheme 1 The following example shows how to calculate the temperature range needed for a given application Assuming the following application conditions Maximum ambient temperature Tam x 82 C measured according to JESD51 2 IDDmax 15 mA Vpp 5 5V Maximum eight standard I Os used at the same time in output at low level with Io 10 mA Vg 22V Maximum fo
26. with 8 pins sunk lio 10 MA Vpp 5 V 0 8 VoL Output low level with 4 pins sunk lo 10 MA Vpp 3 3 V 100 Output low level with 4 pins sunk lo 20 MA Vpp 5 V 150 T Output high level with 8 pins sourced lo 10 mA Vpp 5V 4 0 Vou Output high level with 4 pins sourced llo 10 MA Vpp 3 3 V 2 10 Output high level with 4 pins sourced lo 20 mA Vpp 5 V 3 3 1 Data based on characterization results not tested in production q Typical output level curves pin Figure 19 Typ Vo 8 Vpp 5 V standard ports Figure 20to Figure 27 show typical output level curves measured with output on a single MS19400V1 Doc ID 022171 Rev 3 63 90 Electrical characteristics STM8S007C8 Figure 20 Typ Vo Vpp 3 3 V standard ports 0 75 Vor V 0 5 0 25 0 1 2 3 4 lo mA Figure 21 Typ Vo Vpp 5 V true open drain ports MS19401V1 Va V 25 MS19402V1 64 90 Doc ID 022171 Rev 3 STM8S007C8 Electrical characteristics Figure 22 Typ Vor Vpp 3 3 V true open drain ports Vo V 2 1 5 1 25 0 75 0 5 0 25 6 8 lo mA MS19403V1 Figure 23 Typ Vor Vpp 5 V high sink ports Va V MS19404V1 Doc ID 022171 Rev 3 65 90 Electrical characteristics STM8S007C8 66 90 Figure 24 Typ Vo Vpp 3 3 V high sink ports Vor V
27. 0w OUT OUTPUT l ai14136V2 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp 4 Doc ID 022171 Rev 3 73 90 Electrical characteristics STM8S007C8 9 3 9 74 90 I2C interface characteristics Table 41 1 C characteristics Standard mode I2C Fast mode 12C Symbol Parameter Unit Min Max Min Max twscLL SCL clock low time 4 7 1 3 us tw SCLH SCL clock high time 4 0 0 6 tsu spA SDA setup time 250 100 trspay SDA data hold time o 9 o9 9009 SDA SDA and SCL rise time 1000 300 ns tr scL MWSDA SDA and SCL fall time 300 300 lkscr thistay START condition hold time 4 0 0 6 us lsusra Repeated START condition setup time 4 7 0 6 tsuisto STOP condition setup time 4 0 0 6 us STOP to START condition time Iw STO STA bus free 4 7 13 us Cp Capacitive load for each bus line 400 400 pF 1 faster must be at least 8 MHz to achieve max fast PC speed 400kHz Data based on standard 1 C protocol requirement not tested in production The maximum hold time of the start condition has only to be met if the interface does not stretch the low time 4 The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL Doc ID 022171 Rev 3 I STM8S007C8 Electrical characteristics 4 Figure 36 Typical applicati
28. 1 OSCIN PA1 2 350 PGO OSCOUT PA2 03 340 PC7 HS SPI_MISO Vssio 1 4 33 1PC6 HS SPI_MOSI Vss O5 320 Vppio 2 VCAP g6 311 Vaso 2 Vpp 07 301 PC5 HS SPI SCK Vppio 1 08 290 PC4 HS TIM1 CH4 TIM3 CH1 TIM2_CH3 PA3 Hg 28H PC3 HS TIM1_CH3 UARTI RX HS PA4 C10 274 PC2 HS TIM1 CH2 UART1_TX HS PAS 011 26H PC1 HS TIM1 CH1 UARTI CK HS PA6 C12 25 PES SPI_NSS 1314151617 18192021 222324 LI LI LT LI LT ET ET LT LT ELT ET TANOD t C QN TONO vm c m m ta cc ww LIAO OO OD PF Q 10 SF OO QN O dao 2222222222 LLLI lt x xxx F onga o OU TITT o o kani 9 9 o NN reer E EEE 1 HS high sink capability T True open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option If the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Doc ID 022171 Rev3 21 90 Ji Pinouts and pin description STM8S007C8 Table 4 Legend abbreviations for LOFP48 pin description table Type input O output S power supply floating Input wpu weak pull up Ext interrupt external interrupt HS high sink O1 Slow up to 2 MHz a Speed OS Fast slow programmability with slow as default state after reset utput OA Fast slow programmability with fast as default state after reset OD open drain PP push pull
29. 11 TIM2 TIMG 16 bit general purpose timers 16 4 12 TIM4 B bitbasictimer sssssss e 17 4 13 Analog to digital converter ADC2 0 0 eee eee 17 4 14 Communication interfaces asane 17 4141 UARTI Scc Mek wd a on KA KANE NA ee EG PALANG lb kat paro 18 444 2 UART cicero de RR d ta dem heed Bi MEA pa C 18 4143 SPl RE eR EE koka RG e x ara E x REC AR 19 qid AAA A TT7 20 5 Pinouts and pin description ssss ss 21 5 1 Alternate function remapping s s 25 6 Memory and register map s ssssssssss 26 6 1 Memory map suene ecce kasu Sueza bated PLA RERO REG LIKES 26 6 2 Register Map sauia CT Eon Pup a eb En oa po Ep Poesia a prd ija NG 27 2 90 Doc ID 022171 Rev 3 ky STM8S007C8 Contents 10 11 Interrupt vector mapping ssssssresssee 37 Opllon DVIGS sz sg os es no lee taeda e a d acie de a e Re RR lu 38 Electrical characteristics 42 9 1 Parameter conditions s ssssssssss 42 9 1 1 Minimum and maximum values ssssc 42 9 1 2 Typical values unaua rea kaa pi Eka ira a 42 9 1 3 Typical CUNVOS sus salva pave kape eE EEEREN ANRE 42 9 1 4 Typical current consumption 42 9 1 5 Pin loading conditions sssssssisisss 43
30. 7C8 Total current consumption in wait mode Table 20 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 24 MHz 2 4 fopu luasren 24 MHz HSE user ext clock 24 MHz 1 8 AT HSE crystal osc 16 MHz 2 0 Supply fcpu MASTER 16 MHz HSE user ext clock 16 MHz 1 4 4 4 Ippwri current in HSI RC osc 16 MHz 12 16 mA wait mode fcpu fuasrER 128 125 kHz HSI RC osc 16 MHz 1 0 ur ieee lom HSI RC osc 16 MHz 8 2 0 55 fcpu fuasTER 128 kHz LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off Table 21 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 24 MHz 2 0 cpu fmasten 24 MHz HSE user ext clock 24 MHz 1 8 4 7 HSE crystal osc 16 MHz 1 6 dias fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 1 4 4 4 IDD WFI PER in HSI RC osc 16 MHz 1 2 1 6 mA wait mode 4 5 funsTER 128 125 kHz HSI RC osc 16 MHz 1 0 Kajo MASTER HSI RC osc 16 MHz 8 2 0 55 a MASTER LSI RC osc 128 kHz 0 5 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off 50 90 Doc ID 022171 Rev 3 KY
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32. CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC SPR2 Interrupt software priority register 2 OxFF 0x00 7F72 ITC SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 i ITC SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC SPR8 Interrupt software priority register 8 OxFF posue Reserved area 2 bytes 0x00 7F80 SWIM SWIM CSR SWIM control status register 0x00 papala Reserved area 15 bytes Sr Doc ID 022171 Rev 3 35 90 Memory and register map STM8S007C8 Table 9 CPU SWIM debug module interrupt controller registers continued Address Block Register Label Register Name rieaj 0x00 7F90 DM BK1RE DM breakpoint 1 register extended byte OxFF 0x00 7F91 DM BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status
33. CR1 register ky Doc ID 022171 Rev 3 51 90 Electrical characteristics STM8S007C8 Total current consumption in halt mode Table 24 Total current consumption in halt mode at Vpp 5 V T4 40 to 85 C Symbol Parameter Conditions Typ Max Unit Flash in operating mode HSI 63 5 kal P clock after wakeup x upply current in halt mode u sao Flash in powerdown mode HSI clock after wakeup 6 3 s Table 25 Total current consumption in halt mode at Vpp 3 3 V Symbol Parameter Conditions Typ Unit Flash in operating mode HSI clock after 61 5 l Suppl in hal d A DD H upply current in halt mode H g Flash in powerdown mode HSI clock after 45 wakeup Low power mode wakeup times Table 26 Wakeup times Symbol Parameter Conditions Typ Max Unit See t Wakeup time from wait note WU WFI mode to run mode fopu fmasTER 16 MHz 0 56 p operating 4 6 7 6 MVR voltage mode 4 regulator on Flash in powerdown 30 i Wakeup time active halt mode HSI after US WU AH mode to run mode 9 Flash in operating Wakeup 180 5 MVR voltage mode 4 regulator off Flash in powerdown 6 mode 9 Wakeup time from halt Flash in operating mode 52 twu H 3 g mode to run mode Flash in powerdown mode 54 1 Data guaranteed by design not tested in production 2 twuwel 2 X 1 fmaster 7 X 1 fcpu 3 Measured from
34. CU is clocked at 24 MHz Ta x 85 C and the WAITSTATE option bit is set Subject to general operating conditions for Vpp and Ta Table 18 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit i R mo HSE crystal osc 24 MHz 4 4 24 z I HSE user ext clock 24 MHz 3 7 7 3 HSE crystal osc 16 MHz 3 3 Supply 16 MH HSE t clock 16 MH 2 7 curenti fcpu fmaster 16 MHz SE user ext clock 16 MHz 5 8 run mode HSI RC osc 16 MHz 2 5 3 4 a HSE user ext clock 16 MHz 1 2 4 1 128 125 kHz from RAM CPU MASTER HSI RC osc 16 MHz 10 1 30 fcpu fuasTER 128 16 SE kle HSI RC osc 16 MHz 8 0 55 fcpu TMASTER 128 kHz LSI RC osc 128 kHz 0 45 IDD RUN mA HSE crystal osc 24 MHz 11 4 f f 24 MHz HSE user ext clock 24 MHz 10 8 18 HSE crystal osc 16 MHz 9 0 Supply m E 1 current in fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 82 152 run mode HSI RC osc 16 MHz 8 1 13 2 0 code executed CPU fMAsTER 2 MHz HSI RC osc 16 MHz 8 1 5 from Flash fopy fmastep 128 125 kHz HSI RC osc 16 MHz 1 1 fcpu fuasTER 128 e HSI RC osc 16 MHz 8 0 6 fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 55 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off
35. EE Vpp Vpp io Standard operating voltage 2 95 5 5 V Cext capacitance of 470 3300 nF external capacitor 1 Vcap ESR of external capacitor 03 Ohm At 1 MHz ESL of external capacitor 15 nH 48 pin devices with output 3 Power dissipation at on 8 standard ports 2 high Pp Ta 85 C for suffix 6 sink ports and 2 open drain mW ports simultaneously TA ir ila udi Maximum power dissipation 40 85 pra Tj Junction temperature range 40 105 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter specifications must be respected for the full application range This frequency of 1 MHz as a condition for VcAp parameters is given by the design of the internal regulator 3 To calculate Pprax T a use the formula Ppmax Tymax Ta Oya see Section 10 2 Thermal characteristics on page 84 with the value for Tymax given in Table 16 above and the value for O j4 given in Table 50 Thermal characteristics 4 Referto Section 10 2 Thermal characteristics on page 84 for the calculation method I 46 90 Doc ID 022171 Rev3 STM8S007C8 Electrical characteristics Figure 8 fCpymax Versus Vpp fce u MHz 24 Functionality guaranteed Functionality not with 1 wait state guaranteed in 16 this area 1 2 Li l Functionality guaranteed w
36. EH 4 VHsEL d Cl OSCIN JUUL Do gt fuse STM8 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 24 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start up stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Doc ID 022171 Rev 3 55 90 Electrical characteristics STM8S007C8 Table 30 HSE oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fuse External high speed oscillator 1 24 MHz frequency Rr Feedback resistor 220 kQ Cc Recommended load capacitance 20 pF C 20 pF 6 startup fosc 24 MHz 2 stabilized 9 IppD HSE HSE oscillator power consumption mA C 10 pF 6 startup fosc 24 MHz 1 5 stabilized 9 9m Oscillator transconductance 5 mA V tsutuse Startup time Vpp is stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cload 2 The oscillator selection can be optimized in terms of supply current using a high quality resonator with small R value Refer to crystal manufacturer fo
37. FF 0x00 5000 GPIO and peripheral registers 0x00 57 FF see Table 8 and Table 9 0x00 5800 Reserved 0x00 5FFF 0x00 6000 2 Kbytes boot ROM 0x00 67 FF 0x00 6800 Reserved 0x00 7E FF 0x00 7F00 CPU SWIM debug ITC 0x00 7FFF register see Table 10 0x00 8000 32 interrupt vectors 0x00 807F 0x00 8080 Flash program memory 64 Kbytes 0x01 7FFF MS19412V1 Doc ID 022171 Rev 3 a STM8S007C8 Memory and register map 6 2 Ji Table 6 lists the boundary addresses for each memory size The top of the stack is at the RAM end address in each case Table 6 Flash Data EEPROM and RAM boundary addresses Memory area Size bytes Start address End address Flash program memory 64 K 0x00 8000 0x01 7FFF RAM 6K 0x00 0000 0x00 17FF Data EEPROM 128 0x00 4000 0x00 407F Register map Table 7 I O port hardware register map Address Block Register label Register name Ha 0x00 5000 PA ODR Port A data output latch register 0x00 0x00 5001 PA IDR Port A input pin value register 0x00 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB IDR Port B input pin value register 0x00 0x00 5007 Port B PB DDR Port B data d
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39. PSCR TIM4 prescaler register 0x00 0x00 5346 TIM4_ARR TIM4 auto reload register OxFF e Reserved area 185 bytes 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADR ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register low 0x00 puse Reserved area 1016 bytes 1 Depends on the previous reset source 2 Write only register 34 90 Doc ID 022171 Rev 3 I STM8S007C8 Memory and register map Table 9 CPU SWIM debug module interrupt controller registers Address Block Register Label Register Name sv 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x17 0x00 7F09 SPL Stack pointer low OxFF 0x00 7FOA CCR Condition code register 0x28 o Bins Reserved area 85 bytes 0x00 7F60
40. SIN ES SG ed eS eee eh ogee ME S Nba 87 11 2 1 STM8toolset s l sss ee 87 Doc ID 022171 Rev 3 3 90 Contents STM8S007C8 11 2 2 C and assembly toolchains s ss ss ss sss 87 11 3 Programming Tools usce REX KRA ER EKRA ae SAK KA DRA eens 87 12 Ordering information css ehh eee eee ee 88 13 Revision history ss kasata kak NASKAR ewes esas cec 89 4 90 Doc ID 022171 Rev 3 ky STM8S007C8 List of tables List of tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Table 25 Table 26 Table 27 Table 28 Table 29 Table 30 Table 31 Table 32 Table 33 Table 34 Table 35 Table 36 Table 37 Table 38 Table 39 Table 40 Table 41 Table 42 Table 43 Table 44 Table 45 Table 46 Table 47 Table 48 br STM8S007xx value line features s sessesssssesessoo 9 Peripheral clock gating bit assignments in CLK PCKENR 1 2 registers 14 TIM timer features 2 0 llle mun 17 Legend abbreviations for LQFP48 pin description table 2 202000 22 LQFP48 pin description 0 0000 cette 22 Flash Data EEPROM and RAM boundary addresses sssssol 27 I O port hardware register map 0 0 ce rh
41. T STM8S007C8 Electrical characteristics Total current consumption in active halt mode Table 22 Total current consumption in active halt mode at Vpp 5 V Ta 40 to 85 C Conditions Symbol Parameter Mainvoltage Typ Max Unit regulator Flash mode Clock source MVR 2 HSE crystal oscillator 16 MHz 1000 Operating mode LIRC i oscillator 128 kHz on 260 2 S ill Supply current in HSE crystal oscillator 940 IDD H active halt mode 16 MHz HA Powerdown mode LSI RC oscillator 140 128 kHz Off Operating mode S RC oscillator 68 Powerdown mode 128 kHz 11 45 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH CR1 register Table 23 Total current consumption in active halt mode at Vpp 3 3 V Conditions Symbol Parameter Main voltage Typ Unit regulator Flash mode Clock source MVR HSE crystal osc 16 MHz 600 Operating mode 6 LSI RC osc 128 kHz 200 n HSE crystal osc 16 MHz 540 IDD AH piya NG Powerdown mode HA active halt mode LSI RC osc 128 kHz 140 Operating mode 66 Off LSI RC osc 128 kHz Powerdown mode 9 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in the CLK ICKR register 3 Configured by the AHALT bit in the FLASH
42. anularity of the memory is 4 bytes so cycling is performed on 4 bytes even when a write erase operation addresses a single byte Doc ID 022171 Rev 3 59 90 Electrical characteristics STM8S007C8 9 3 6 O port pin characteristics General characteristics Subject to general operating conditions for Vpp and T4 unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 35 IO static characteristics Symbol Parameter Conditions Min Typ Max Unit Input low level ViL voltage 0 3 0 3 x Vpp V Input high level Vpo 5V ViH voltage 0 7x Vpp Vpp 0 3 V V Vhys Hysteresis 700 mV Rou Pull up resistor Vpp 5 V Vin Vas 30 55 80 kQ Fast I Os 202 ns iuj Rise and fall time Load 50 pF R E 10 90 Standard and high sink I Os 425 2 ns Load 50 pF Input leakage lkg current VssS VinS Vpp 1 UA analog and digital Analog input 3 likg ana leakage current Vss Vin Vpop 250 nA likg ini Bre Injection current x4 mA x19 HA 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Guaranteed by design 3 Data based on characterization results not tested in production 60 90 Doc ID 022171 Rev 3 I STM8S007C8 Electrical characteristics Figure 16 Typical Vj and Vj
43. ation between any actual transition and the end point correlation line Figure 38 Typical applic ation with ADC Rain an 000 AINx STM8 10 bit A D conversion TI Capo Doc ID 022171 Rev 3 I STM8S007C8 Electrical characteristics 9 3 11 EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e ESD Electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vgs through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software It should be noted that good EMC performance is highl
44. cy variation vs Vpp atB3temperatures 57 Typical LSI frequency variation vs Vpp 25 C 22 58 Typical Vj and Vip vs Vpp Btemperatures sssssssssssss 61 Typical pull up resistance vs Vpp 3temperatures s ss sese 61 Typical pull up current vs Vpp E 3 temperatures sss 62 Typ Vol 9 Vpp 5V standardports ssessesesese esos 63 Typ Vol 9 Vpp 3 3 V Standard ports eee 64 Typ Voi 9 Vpp 5 V true open drain ports 0 0 0 0 eee 64 Typ Vol 9 Vpp 3 3 V true open drain ports eee 65 Typ VoL Vpp 5 V high sink ports BIS 65 Typ Vol 9 Vpp 8 3 V high sink ports aaaea 66 Typ Vpp Vou 9 Vpp 5 V standard ports nanana 66 Typ Vpp Vou 9 Vpp 3 3 V standard ports 67 Typ Vpp Vou Vpp 5 V high sink ports naaa 67 Typ Vpp Vou 9 Vpp 3 3 V high sink ports sense 68 Typical NRST Vj and Vip vs Vpp E 3 temperatures 0 0 00 cee ee 69 Typical NRST pull up resistance vs Vpp 3temperatures 69 Typical NRST pull up current vs Vpp E 3temperatures ss 70 Recommended reset pin protection eren 70 SPI timing diagram slave mode and CPHA 20 ssssssssse 72 SPI timing diagram slave mode and CPHA 100 l a 72 SPI timing diagram master mode we 73 Typical application wit
45. d Kingdom United States of America www st com 90 90 Doc ID 022171 Rev 3 ky
46. d capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control Synchronous communication Full duplex synchronous transfers SPI master operation 8 bit data communication Maximum speed 1 Mbit s at 16 MHz fcpy 16 LIN master mode Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame 4 14 2 UART3 Main features 18 90 1 Mbit s full duplex SCI LIN master capable High precision baud rate generator Doc ID 022171 Rev 3 ky STM8S007C8 Product overview 4 14 3 Asynchronous communication UART mode Full duplex communication NRZ standard format mark space Programmable transmit and receive baud rates up to 1 Mbit s fcp 16 and capable of following any standard baud rate regardless of the input frequency Separate enable bits for transmitter and receiver Two receiver wakeup modes Address bit MSB Idle line interrupt Transmission error detection with interrupt generation Parity control LIN master capability Emission Generates 13 bit synch break frame Reception Detects 11 bit break frame LIN slave mode SPI Autonomous header handling one single interrupt per valid message header Automatic baud rate synchronization maximum tolerated i
47. e debug interf 400 Kbit s 10 Mbit s LIN master SPI emul Master slave autosynchro 16 channels beep Reset dimus 1 2 4 c e re ng BAN NE a Reset block pa XTAL 1 24 MHz Clock controller Reset 4 RC int 16 MHz Detector FOR BOR 44 RCint 128 kHz Clock to peripherals and core Window WDG STM8 core Independent WDG Debug SWIM 64 Kbytes high density program Flash 2 KO o KO 128 bytes data EEPROM 3 i SPI S lt gt 6 Kbytes RAM 3 o o F lt gt Boot ROM UART1 is vo lt L gt 16 bit advanced control UART3 timer TIM1 ADC2 o 16 bit general purpose timers TIM2 TIM3 Beeper lt gt 8 bit basic timer TIM4 AWU timer Up to 4 CAPCOM channels 3 complementary outputs Up to 5 CAPCOM channels Doc ID 022171 Rev 3 a STM8S007C8 Product overview 4 4 1 Product overview The following section intends to give an overview of the basic features of the STM8S007xx value line functional modules and peripherals For more detailed information please refer to the corresponding family reference manual RM0016 Central processing unit STM8 The 8 bit STM8 core is designed for code efficiency and performance I
48. e Master clock sources Four different clock sources can be used to drive the master clock 1 24 MHz high speed external crystal HSE Up to 24 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock After reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS This feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHzZ 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK PCKENR1 2 registers Bit Peripheral Bit Peripheral Bit Peripheral Bit Peripheral clock clock clock clock PCKEN17 TIM1 PCKEN13 UART3 PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM3 PCKEN12 UART1 PCKEN26 Reserved PCKEN22 AWU PCKEN15 TIM2 PCKEN 11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM4 PCKEN10 ec PCKEN24 Reserved PCKEN20 Reserved Doc ID 022171 Rev 3 STM8S007C8 Product overview 4 6 4 7 Power management For efficent power management the application can be put in one of four different low power mode
49. e Vppio Vssio pins 4 liNu PIN must never be exceeded This is implicitly insured if Vjy maximum is respected If Vjy maximum cannot be respected the injection current must be limited externally to the liy jp value A positive injection is induced by Viy Vpp while a negative injection is induced by Viy lt Vgs Por true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected 5 Negative injection disturbs the analog performance of the device See note in Section 9 3 10 10 bit ADC characteristics on page 76 6 When several inputs are submitted to a current injection the maximum 2Iiy pi is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with Zlj py maximum current injection on four I O port pins of the device Table 15 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 de Ty Maximum junction temperature 150 ky Doc ID 022171 Rev 3 45 90 Electrical characteristics STM8S007C8 9 3 Operating conditions The device must be used in operating conditions that respect the parameters in Table 16 In addition full account must be taken of all physical capacitor characteristics and tolerances Table 16 General operating conditions Symbol Parameter Conditions Min Max Unit 0 24 MHz fopu Internal CPU clock frequency 7
50. e before a return from the bootloader 2 In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to Vpp are not implemented 3 The PD1 pin is in input pull up during the reset phase and after the internal reset release Note 2 MHz 24 90 Doc ID 022171 Rev 3 The slope control of true open drain pins cannot be programmed and by default is limited to ky STM8S007C8 Pinouts and pin description 5 1 Alternate function remapping As shown in the rightmost column of the pin description table some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the I O ports see the GPIO section of the family reference manual RM0016 Doc ID 022171 Rev 3 25 90 Memory and register map STM8S007C8 6 6 1 26 90 Memory and register map Memory map Figure 4 Memory map 0x00 0000 0x00 17 FF 1024 bytes stack 0x00 1800 Reserved 0x00 3FFF 0x00 4000 128 bytes data EEPROM 0x00 407F 0x00 4080 0x00 47FF RESER 0x00 4800 Option bytes 0x00 487F 0x00 4900 Reserved 0x00 4F
51. e function ADC ETR Ji Doc ID 022171 Rev3 39 90 Option bytes STM8S007C8 40 90 Table 12 Option byte description continued Option byte no OPT3 Description LSI_EN Low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG HW Independent watchdog 0 IWDG Independent watchdog activated by software 1 IWDG Independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on halt 0 No reset generated on halt if WWDG active 1 Reset generated on halt if WWDG active OPT4 EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for for AWU PRSC 1 0 AWU clock prescaler 00 24 MHz to 128 kHz prescaler 01 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time This configures the stabilisation time 0x00 2048 HSE cycles OxB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles OPT6 Reserved OPT7 WAITSTATE Wait state configuration This option configures the
52. e injection is induced by VjysVss For true open drain pads there is no positive injection current and the corresponding Viy maximum must always be respected I Doc ID 022171 Rev 3 STM8S007C8 Electrical characteristics Table 14 Current characteristics Symbol Ratings Max Unit lypp Total current into Vpp power lines source 60 lyss Total current out of Vgs ground lines sink 60 Output current sunk by any I O and control pin 20 lo Output current source by any I Os and control pin 20 Total output current sourced sum of all I O and control pins for devices with two Vppjo pins 200 Total output current sourced sum of all I O and control pins for devices with one Vppjo pin 100 Xl 5 Total output current sunk sum of all I O and control pins for devices with two Vggio pins 190 Total output current sunk sum of all I O and control pins for i 3 80 devices with one Vssio pin Injected current on NRST pin 14 Ingen 99 Injected current on OSCIN pin 4 Injected current on any other pin 4 lue Total injected current sum of all I O and control pins 20 1 Data based on characterization results not tested in production 2 All power Vpp Vppio Vppa and ground Vss Vassio Vssa pins must always be connected to the external supply 3 I O pins used simultaneously for high current source sink must be uniformly spaced around the package between th
53. e occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout At 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window The downcounter is refreshed before its value is lower than the one stored in the window register Doc ID 022171 Rev 3 15 90 Product overview STM8S007C8 4 8 4 9 4 10 4 11 16 90 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHZ LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM3 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin for sound generation The signal is in the range of 1 2 or 4 kHz TIM1 16 bit advanced cont
54. ection The first level is known as MASS memory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option bytes To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option bytes A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to Figure 2 Doc ID 022171 Rev 3 ky STM8S007C8 Product overview The size of the UBC is programmable through the UBC option byte Table 12 in increments of 1 page 512 bytes by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory 64 Kbytes minus UBC e User specific boot code UBC Configurable up to 64 Kbytes The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organisation Data Data memory area up to 2 Kbytes EEPROM memory Option bytes Programmable area from 1 Kbyte UBC area 2 first pages up to 64 Kbytes Remains write
55. ed for versatility and cost effectiveness In addition STMS application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8 microcontrollers via the STMS single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers STice key features Occurrence and time profiling and code coverage new features Advanced breakpoints with up to 4 levels of conditions Data breakpoints Program and data trace recording up to 128 KB records Read write on the fly of memory during emulation In circuit debugging programming via SWIM protocol 8 bit probe analyzer 1 input and 2 output triggers Power supply follower managing application voltages between 1 62 to 5 5 V Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requi
56. ent consumption aaaea 53 HSE user external clock characteristics llle 55 HSE oscillatorcharacteristios Les ene 56 HSI oscillator characteristics lille ren 57 LSI oscillator characteristics 0 0 0 0 cc ren 58 RAM and hardware registers eee 59 Flash program memory data EEPROM memory 0c cece eee 59 I O static characteristics 0 0 0 0 eee 60 Output driving current standard ports 000 00 eects 62 Output driving current true open drain ports 0 0 eee eee 62 Output driving current high sink ports llli 63 NRST pin characteristics rn 68 SPI characteristics sssssessssseessassessasso 71 KE phiaraeletislos sx aaa Ala GA ride Pis ei ede dad De mek DAGTA d ELSE 74 ADC characteristics anana 76 ADC accuracy with RAIN lt 10kQ VppA oO MI EB ae teta petia eiu t e dk 77 ADC accuracy with Rain lt 10 kQ RAIN VDDA Mi a jj Sa nee ro a cate Ro de kajo 77 EMS dala s cios mada pan les nah sheba dd d veko de Vd oe nekla oeheas 79 E Nm 80 ESD absolute maximum ratings s s ssssssssssssessoo 80 Electrical sensitivities s l ss sl sss III 81 Doc ID 022171 Rev 3 5 90 List of tables STM8S007C8 Table 49 48 pin low profile quad flat package mechanical data 83 Table 50 Thermal characteristics
57. h I2C bus and timing diagram 75 ADC accuracy characteristics 78 Typical application with ADC RI n 78 48 pin low profile quad flat package 7X7 ss ssssssss4 83 STM8S007xx value line ordering information Si hemo MENGE 88 Doc ID 022171 Rev 3 7 90 Introduction STM8S007C8 8 90 Introduction This datasheet contains the description of the STM8S007xx value line features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8S microcontroller memory registers and peripherals please refer to the STM8S and STM8A microcontroller families reference manual RM0016 e Forinformation on programming erasing and protection of the internal Flash memory please refer to the PM0051 How to program STM8S and STM8A Flash program memory and data EEPROM e Forinformation on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STMS core please refer to the STM8 CPU programming manual PM0044 Doc ID 022171 Rev 3 ky STM8S007C8 Description 2 Description The STM8S007xx value line 8 bit microcontrollers offer 64 Kbytes Flash program memory They are referred to as high density devices in the STM8S microcontroller family reference manual All devices of the STM8S007xx value
58. he input voltage measurement on a pin of the device is described in Figure 7 Figure 7 Pin input voltage KK STMS pin Doc ID 022171 Rev3 43 90 Electrical characteristics STM8S007C8 9 2 44 90 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 13 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including Vppa ang Vppio 0 3 6 5 Input voltage on true open drain pins PE1 PE2 Vas 0 3 6 5 V VN Input voltage on any other pin Vas 0 3 Vpp 0 3 IVppx Vppl Variations between different power pins 50 IVssx Vggl Variations between all the different ground pins 50 see Absolute maximum Vesp Electrostatic discharge voltage ratings electrical sensitivity on page 80 1 All power Vpp Vppio Vppa and ground Vss Vssio Vssa pins must always be connected to the external power supply 2 liNu PIN must never be exceeded This is implicitly insured if Vjy maximum is respected If Vjy maximum cannot be respected the injection current must be limited externally to the liy pi value A positive injection is induced by Viy Vpp while a negativ
59. icrocontroller Family type S standard Sub family type 007 C 007 peripheral set Pin count C 48 pins Program memory size 8 8 64 Kbyte Package type 1 T LOFP Temperature range 6 6 40 C to 85 C Package pitch TR No character 0 5 mm Packing No character Tray or tube TR Tape and reel For a list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the ST Sales Office nearest to you Refer to Table 1 STM8S007xx value line features for detailed description Doc ID 022171 Rev 3 a STM8S007C8 Revision history 13 Revision history Table 51 Document revision history Date Revision Changes 31 Oct 2011 1 Initial release Table 34 Flash program memory data EEPROM memory updated 06 Jan 2012 2 Vpp condition updated tRET parameters Table 39 NRST pin characteristics updated typ and max values of the NRST Pull up resistor Added document status on page 7 datasheet production data Modified temperature range and ACCyg values in Table 31 HSI 26 Apr 2012 3 oscillator characteristics on page 57 ACCyg parameter Modified Figure 35 SPI timing diagram master mode 1 on page 73 SCK output instead of SCK input Doc ID 022171 Rev 3 89 90 STM8S007C
60. interrupt event to interrupt vector fetch 4 Configured by the REGAH bit in the CLK ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization I 52 90 Doc ID 022171 Rev3 STM8S007C8 Electrical characteristics Total current consumption and timing in forced reset state Table 27 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Ipp R Supply current in reset state E 2 mA Vpp 3 3 V 0 8 estat e release to bootloader vector 150 Hus 1 Data guaranteed by design not tested in production Current consumption of on chip peripherals Subject to general operating conditions for Vpp and T HSI internal RC fcpy fMASTER 16 MHz Table 28 Peripheral current consumption Symbol Parameter Typ Unit Ibom TIMI supply current 220 lpp rivo TIM2 supply current 120 Ipp TIM3 TIM3 timer supply current 1 100 IDD TIM4 TIM4 timer supply current 1 25 Ipp uanri UARTI supply current 2 90 UA Ipp uanra UARTS supply current 2 110 Ipp sPi SPI supply current 40 lpp c IC supply current 2 50 IDD ADC2 ADC2 supply current when converting 3 1000 Ji 1 Data based on a differential Ipp measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in prod
61. irection register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register 0x00 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Port D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register 0x00 0x00 5011 Port D PD_DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 Doc ID 022171 Rev 3 27 90 Memory and register map STM8S007C8 Table 7 O port hardware register map continued Address Block Register label Register name Vieh 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE IDR Port E input pin value register 0x00 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE_CR2 Port E control register 2 0x00 0x00 5019 PF_ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register 0x00 0x00 501B Port F PF_DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF_CR2 Port F control register 2 0x00 0x00
62. ith O wait state 8 l l 4 0 2 95 4 0 5 0 5 5 Supply voltage V MS19413V1 Table 17 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 20 co tvDD us V Vpp fall time rate 2l co Reset release iai 1 tremp delay Vpp rising 1 7 ms Power on reset Vim threshold 2 65 2 8 2 95 V Brown out reset Vit threshold 2 58 2 73 2 88 V Brown out reset VHYS BOR hysteresis mu 1 Guaranteed by design not tested in production 9 3 1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor Cex7 to the Vcap pin C xr is specified in Table 16 Care should be taken to limit the series inductance to less than 15 nH Figure 9 External capacitor Cex7 ESR C ESL L Lan Bot Rleak 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance 4 Doc ID 022171 Rev 3 47 90 Electrical characteristics STM8S007C8 9 3 2 Supply current characteristics The current consumption is measured as described in Figure 5 on page 42 Total current consumption in run mode The MCU is placed under the following conditions e All I O pins in input mode with a static value at Vpp or Vas no load e Allperipherals are disabled clock stopped by Peripheral Clock Gating registers except if explicitly mentioned e When the M
63. le and debug module permits non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug module and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 bytes ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Beside memory and peripherals also CPU operation can be monitored in real time by means of shadow registers e R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined configurations Interrupt controller Nested interrupts with three software priority levels 32 interrupt vectors with hardware priority Up to 33 external interrupts on six vectors including TLI Trap and reset interrupts Flash program and data EEPROM memory e 64 Kbytes of high density Flash program single voltage Flash memory e 128 bytes true data EEPROM e Read while write Writing in data memory possible while executing code in program memory e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write prot
64. map STM8S007C8 Table 8 General hardware register map continued Address Block Register label Register name nese status 0x00 50CC CLK_HSITRIMR HSI clock calibration trimming register 0x00 CLK 0x00 50CD CLK_SWIMCCR SWIM clock control register a 0x00 50CE to 0x00 50D0 Reserved area 3 bytes 0x00 50D1 ue WWDG CR WWDG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F 0x00 50D3 to 0x00 50DF Reserved area 13 bytes 0x00 50EO IWDG KR IWDG key register OxXX 2 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF 0x00 50E3 to 0x00 50EF Reserved area 13 bytes 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU asynchronous prescaler buffer register Ox3F 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F 0x00 50F4 to 0x00 50FF Reserved area 12 bytes 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI interrupt control register 0x00 0x00 5203 Bei SPI SR SPI status register 0x02 0x00 5204 SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF 0x00 5208 to 0x00 520F Reserved area 8 bytes 0x00 5210 I2C CR1 I2C control register 1 0x00 0x00 5211 I2C CR2 I2C control register 2 0x00 0x00 5212 pa l2C FREQR I2C frequency regi
65. n Table 40 are derived from tests performed under ambient temperature fMAsTER frequency and Vpp supply voltage conditions tMASTER 1 MASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 40 SPI characteristics Symbol Parameter Conditions Min Max Unit f Master mode 0 10 SCK SPI clock frequency MHz 1 te sck Slave mode 0 6 Ce SPI clock rise and fall time Capacitive load C 30 pF 25 f SCK tsuNss NSS setup time Slave mode 4 X MASTER tss NSS hold time Slave mode 70 1 W SCKH SCK high and low time Master mode tsck 2 15 tecx 2 15 tw SCKL t 1 Master mode 5 su MI Data input setup time tsu sl Slave mode 5 1 Master mode 7 ns tivo Data input hold time thsi Slave mode 10 teo Data output access time Slave mode 3 X MASTER taiso 9 Data output disable time Slave mode 25 tuso Data output valid time Slave mode after enable edge 75 two Data output valid time Master mode after enable edge 30 kien Slave mode after enable edge 31 naa Data output hold time tr mo Master mode after enable edge 12 Values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data Min time is for the minimum time to invalidate the output and the max time is for the ma
66. nitial clock deviation 15 96 Synch delimiter checking 11 bit LIN synch break detection break detection always active Parity check on the LIN identifier field LIN error management Hot plugging support Maximum speed 10 Mbit s fyasteR 2 both for master and slave Full duplex synchronous transfers Simplex synchronous transfers on two lines with a possible bidirectional data line Master or slave operation selectable by hardware or software CRC calculation 1 byte Tx and Rx buffer Slave master selection input pin Doc ID 022171 Rev 3 19 90 Product overview STM8S007C8 4 14 4 20 90 IC I2C master features Clock generation Start and stop generation IC slave features Programmable I2C address detection Stop bit detection Generation and detection of 7 bit 10 bit addressing and general call Supports different communication speeds Standard speed up to 100 kHz Fast speed up to 400 kHz Doc ID 022171 Rev 3 ky STM8S007C8 Pinouts and pin description 5 Pinouts and pin description Figure 3 LQFP 48 pin pinout o o 9 x O To z I 05 di n Hs mazr E rrr TD xx 999 9024 ffuNuoZo 2398 e Wz222232311015 EEEEEDEORS GECHHDDODD HESS ES SLLLILIEEE So soNuro Orang 2Aa2000 000 uuww Qaaaaaaaadaad D1OIOODOOODDOODLDJ 4847 4645 4443424140393837 NRST Clie 36rPG
67. number of wait states inserted when reading from the Flash data EEPROM memory 1 wait state is required if fopy gt 16 MHz 0 No wait state 1 1 wait state I Doc ID 022171 Rev 3 STM8S007C8 Option bytes Table 12 Option byte description continued Option byte no Description BL 7 0 Bootloader option byte For STM8S products this option is checked by the boot ROM code after reset Depending on the content of addresses 0x487E 0x487F and 0x8000 reset vector the CPU jumps to the bootloader or to the reset vector Refer to the UMO560 STM8L S bootloader manual for more details For STMBL products the bootloader option bytes are on addresses OxXXXX and OxXXXX 1 2 bytes These option bytes control whether the bootloader is active or not For more details refer to the UM0560 STM8L S bootloader manual for more details OPTBL 4 Doc ID 022171 Rev 3 41 90 Electrical characteristics STM8S007C8 9 9 1 42 90 Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vgs Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at Ta 25 C and Ta Tamax given by the selected temperature range Data based on characterization re
68. on with IZC bus and timing diagram VDD 47kQ STM8S20xxx t SDA gt re SDA isu SDA tw SCLH i tr sCL gt e Le scc ai17490 1 Measurement points are made at CMOS levels 0 3 x Vpp and 0 7 x Vpp Doc ID 022171 Rev 3 75 90 Electrical characteristics STM8S007C8 9 3 10 76 90 10 bit ADC characteristics Subject to general operating conditions for VppA MASTER and Ta unless otherwise specified Table 42 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vppa 3 to 5 5 V 1 4 fanc ADC clock frequency MHz VDDA 4 5to5 5V 1 6 VppA Analog supply 3 5 5 V Vngr Positive reference voltage 2 750 VDDA V Vrer Negative reference voltage Vssa os v Vain X Conversion voltage range Vssa VppA V Internal sample and hold Canc capacitor 3 pF f 4 MHz 0 75 tg Sampling time one us fADC 6MHz 0 5 tsrap Wakeup time from standby 7 us fADC 4 MHz 3 5 US Total conversion time including conv sampling time 10 bit resolution fanc 6 MHz aii us 14 l fApc 1 Data guaranteed by design not tested in production 2 During the sample time the input capacitance Cy 3 pF max can be charged discharged by the external Source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the
69. p Max Unit fapc 2 MHz 1 1 2 IErl Total unadjusted error fapc 4 MHz 1 6 2 5 fap 2 MHz 0 7 1 5 IEg Offset error E fapc 4 MHz 1 3 2 fap 2 MHz 0 2 1 5 IEg Gain error E LSB fapc 4 MHz 0 5 2 fap 2 MHz 0 7 1 IEpl Differential linearity error z fADC 4 MHz 0 7 1 fap 2 MHz 0 6 1 5 IE Integral linearity error E fapc 4 MHz 0 6 1 5 ky Doc ID 022171 Rev 3 77 90 Electrical characteristics STM8S007C8 78 90 Figure 37 ADC accuracy characteristics A g 10235 ecu us a NE aene E 1092 fre VDDA VSSA le IDEAL 7 1024 A 1021 4 qe I 7 BI oe i MI E d p 14 3 i 7 1 6 F Pa i l M l 5 1 4 a i 4 4 Eo p 2 7 EL 1 1 i 3 4 f Z f i i 7 b F Ep i 2 1 LA Li dp 1 1d AH 1 LSBipEAL i l l l l LJ Il J I l 0 1 2 3 4 5 6 T 1021102210231024 Vssa VDDA 1 Example of an actual transfer curve 2 The ideal transfer curve 3 End point correlation line Ey Total unadjusted error maximum deviation between the actual and the ideal transfer curves Eo Offset error deviation between the first actual transition and the first ideal one Eg Gain error deviation between the last ideal transition and the last actual one Ep Differential linearity error maximum deviation between actual steps and the ideal one E Integral linearity error maximum devi
70. r more details Data based on characterization results not tested in production tsu HsE is the start up time measured from the moment it is enabled by software to a stabilized 24 MHz oscillation is reached This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 13 HSE oscillator circuit diagram gt STM8 pezas ms duas 3 f to core HSE R pom l R l Co l j l Lm l m i Cu T i OSCIN Cm shod e 9m Resonator Consumption a e control Resonator OSCOUT Ci HSE oscillator critical gm formula merit 2X TI x fyse x Rm 2C0 C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification C Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 42C C Grounded external capacitance Om gt gt Omcrit 56 90 Doc ID 022171 Rev 3 I STM8S007C8 Electrical characteristics 9 3 4 Subject to general operating conditions for Vpp and Ta fuse High speed internal RC oscillator HSI Internal clock sources and timing characteristics Table 31 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fug Frequency 16 MHz Trimmed by the Accu
71. racy of HSI oscillator CLK_HSITRIMR register 4 96 1 0 for given Vpp and TA ACCus conditions o Vpp 5 V Ta 25 C 5 Accuracy of HSI oscillator factory calibrated Vpp 5 V 5 5 40 C lt Tas 85 C HSI oscillator wakeup 1 suHS time including calibration Lat HSI oscillator power 2 IDD HSI consumption Era HA 1 Guaranteeed by design not tested in production 2 Data based on characterization results not tested in production Figure 14 Typical HSI frequency variation vs Vpp at 3 temperatures 3 2 1 gt 8 8 0 E 1 2 3 ai15067b ky Doc ID 022171 Rev 3 57 90 Electrical characteristics STM8S007C8 Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ty Table 32 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit figi Frequency 128 kHz tsu Ls1 LSI oscillator wakeup time 70 us Ipp Lsi LSI oscillator power consumption 5 HA 1 Guaranteeed by design not tested in production Figure 15 Typical LSI frequency variation vs Vpp 25 C 3 4 2 accuracy 0 PP 2 3 2 5 3 3 5 45 Voo V 5 5 6 ai15070 58 90 Doc ID 022171 Rev 3 a STM8S007C8 Electrical characteristics 9 3 5 Memory characteristics RAM and hardware registers Table 33 RAM and hardware registers Symbol Parameter Conditions
72. rademark Doc ID 022171 Rev 3 ky STM8S007C8 Package characteristics 10 1 Package mechanical data Figure 39 48 pin low profile quad flat package 7 x 7 m 5B ME Ji Table 49 48 pin low profile quad flat package mechanical data mm inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 170 0 220 0 270 0 0067 0 0087 0 0106 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 500 0 2165 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 500 0 2165 e 0 500 0 0197 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 0 3 5 7 0 0 0 3 5 7 0 ccc 0 080 0 0031 1 Values in inches are converted from mm and rounded to four decimal places Doc ID 022171 Rev 3 83 90 Package characteristics STM8S007C8 10 2 10 2 1 84 90 Thermal characteristics The maximum chip junction temperature T Jmax must never exceed the values given in Table 16 General operating conditions The maximum chip junction temperature T Jmax in degrees Celsius may be calculated using the following equation TJmax Tamax Ppmax X ja Where Tamax is the maximum ambient temperature in C e Oy is the package junction
73. register 1 0x10 0x00 7F99 DM_CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM_ENFCTR DM enable function register OxFF us e Reserved area 5 bytes 1 Accessible by debug module only 2 Product dependent value see Figure 4 Memory map 36 90 Doc ID 022171 Rev 3 I STM8S007C8 Interrupt vector mapping 7 Interrupt vector mapping Table 10 Interrupt mapping Eo Description akaun rom Makeup omg Vector adres RESET Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wake up from halt Yes 0x00 800C 2 CLK Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTI4 Port E external interrupts Yes Yes 0x00 8024 8 Reserved 0x00 8028 9 Reserved 0x00 802C 10 SPI End of transfer Yes Yes 0x00 8030 11 TIMI uM 0x00 8034 12 TIM1 TIM1 capture compare 0x00 8038 13 TIM2 TIM2 update overflow 0x00 803C 14 TIM2 TIM2 capture compare 0x00 8040 15 TIM3 Update overflow 0x00 8044 16 TIM3 Capture compare 0x00 8048 17 UART1 Tx complete 0x00 804C 18 UART1 Receive register DATA FULL 0x00 8050 19 FE eC interrupt Yes Yes 0x00
74. rements Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 Doc ID 022171 Rev 3 ky STM8S007C8 STM8 development tools 11 2 11 2 1 11 2 2 11 3 Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST Visual Develop STVD IDE and the ST Visual Programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 A free version that outputs up to 32 Kbytes of code is available STMS toolset STMB8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com mcu This package includes ST Visual Develop Full featured integrated development environment from ST featuring Seamless integration of C and ASM toolsets Full featured debugger Project management Syntax highlighting editor Integrated programming interface Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller s Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and a
75. rm to the SAE IEC 61967 2 standard for test software board layout and pin loading Table 46 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit General conditions frequency band 16 MHz 16 MHz 24 MHz 8MHz 16 MHz 24 MHz 0 1MHz to 30 MHz 14 13 24 Vpp 5 V Peak level TA 25 C 30 MHz to 130 MHz 19 23 17 dBuV EMI LQFP48 package 130 MHz to 1 GHz 4 4 7 conforming to SAE IEC mli 61967 2 SAE EMI level 1 5 2 2 5 1 Data based on characterization results not tested in production 80 90 Absolute maximum ratings electrical sensitivity Based on two different tests ESD and LU using specific measurement methods the product is stressed in order to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges 3 positive then 3 negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181 Table 47 ESD absolute maximum ratings Symbol Ratings Conditions Class AU Unit Electrostatic discharge voltage TA 25 C conforming to VESD HBM Human body model JESD22 A114 2909 M
76. rol timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down autoreload counter with 16 bit prescaler e Fourindependent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output Synchronization module to control the timer with external signals Break input to force the timer outputs into a defined state Three complementary outputs with adjustable dead time Encoder mode Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break TIM2 TIM3 16 bit general purpose timers 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 Timers with 3 or 2 individually configurable capture compare channels PWM mode Interrupt sources 2 or 3 x input capture output compare 1 x overflow update Doc ID 022171 Rev 3 ky STM8S007C8 Product overview 4 12 TIM4 8 bit basic timer e 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 e Clock source CPU clock e Interrupt source 1 x overflow update Table 3 TIM timer features Counter Timer nd Counting CAPCOM Complem Ext synchr
77. s You can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode In this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on In this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off This mode is the same as active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode In this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without performing a reset Window watchdog timer The window watchdog is used to detect th
78. ssembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of your application directly from an easy to use graphical interface Available toolchains include e Cosmic C compiler for STM8 One free version that outputs up to 32 Kbytes of code is available For more information see www cosmic software com e Haisonance C compiler for STM8 One free version that outputs up to 32 Kbytes of code For more information see www raisonance com e STM8 assembler linker Free assembly toolchain included in the STVD toolset which allows you to assemble and link your application source code Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol Additional tools are to include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming your STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family Doc ID 022171 Rev 3 87 90 Ordering information STM8S007C8 12 Ordering information 88 90 Figure 40 STM8S007xx value line ordering information scheme Example Product class STM8 S STM8 m
79. ster 0x00 0x00 5213 l2C OARL IC own address register low 0x00 0x00 5214 I2C OARH I2C own address register high 0x00 0x00 5215 Reserved 30 90 Doc ID 022171 Rev 3 ky STM8S007C8 Memory and register map Table 8 General hardware register map continued Address Block Register label Register name kargo 0Ox05216 cR fCdetaregser OXO 0x00 5217 I2C SRI I C status register 1 0x00 0x00 5218 l2C SR2 I2C status register 2 0x00 0x00 5219 fc I2C SR3 I2C status register 3 0x00 0x00 521A I2C ITR ec interrupt control register 0x00 0x00 521B I2C CCRL I2C clock control register low 0x00 0x00 521C I2C CCRH I2C clock control register high 0x00 0x00 521D I2C TRISER I2C TRISE register 0x02 se Reserved area 18 bytes 0x00 5230 UART1 SR UART status register OxCO 0x00 5231 UART1 DR UART1 data register OxXX 0x00 5232 UART1 BRR1 UART1 baud rate register 1 0x00 0x00 5233 UART1_BRR2 UART1 baud rate register 2 0x00 0x00 5234 UART1 CR1 UART1 control register 1 0x00 0x00 5235 UART1 UART1 CR2 UART1 control register 2 0x00 0x00 5236 UART1_CR3 UART1 control register 3 0x00 0x00 5237 UART1_CR4 UART1 control register 4 0x00 0x00 5238 UART1_CR5 UART1 control register 5 0x00 0x00 5239 UART1_GTR UART1 guard time register 0x00 0x00 523A UART1_PSCR UART1 prescaler regis
80. sults design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Based on characterization the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation mean 3 2 Typical values Unless otherwise specified typical data are based on Ta 25 C Vpp 5 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range where 95 of the devices have an error less than or equal to the value indicated mean 2 x Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Typical current consumption For typical current consumption measurements Vpp Vppio and Vppa are connected together in the configuration shown in Figure 5 Figure 5 Supply current measurement conditions 5Vor3 3V d Voo PHP Doc ID 022171 Rev 3 ky STM8S007C8 Electrical characteristics 9 1 5 9 1 6 Pin loading conditions Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6 Figure 6 Pin loading conditions STM8 pin 50PF MAN Pin input voltage T
81. t contains 6 internal registers which are directly addressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture 3 stage pipeline 32 bit wide program memory bus single cycle fetching for most instructions X and Y 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations 8 bit accumulator 24 bit program counter 16 Mbyte linear memory space 16 bit stack pointer access to a 64 K level stack 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set 80 instructions with 2 byte average instruction size Standard data movement and logic arithmetic functions 8 bit by 8 bit multiplication 16 bit by 8 bit and 16 bit by 16 bit division Bit manipulation Data transfer between stack and accumulator push pop with direct stack access Data transfer using the X and Y registers or direct memory to memory transfers Doc ID 022171 Rev 3 11 90 Product overview STM8S007C8 4 2 4 3 4 4 12 90 Single wire interface module SWIM and debug module DM The single wire interface modu
82. ter 0x00 Reserved area 5 bytes 0x00 5240 UART3 SR UARTS status register COh 0x00 5241 UART3 DR UARTS data register OxXX 0x00 5242 UART3 BRR1 UART3 baud rate register 1 0x00 0x00 5243 UARTS BRR2 UARTS baud rate register 2 0x00 0x00 5244 UART3 CR1 UARTS control register 1 0x00 0x00 5245 adi UART3_CR2 UARTS control register 2 0x00 0x00 5246 UART3_CR3 UARTS control register 3 0x00 0x00 5247 UART3_CR4 UARTS control register 4 0x00 0x00 5248 Reserved 0x00 5249 UART3_CR6 UARTS control register 6 0x00 Reserved area 6 bytes ky Doc ID 022171 Rev 3 31 90 Memory and register map STM8S007C8 Table 8 General hardware register map continued Address Block Register label Register name kargo 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1_ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1_SR1 TIM1 status register 1 0x00 0x00 5256 TIM1_SR2 TIM1 status register 2 0x00 0x00 5257 TIM1_EGR TIM1 event generation register 0x00 0x00 5258 TIM1_CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture
83. uction 2 Data based on a differential Ipp measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential lh measurement between reset configuration and continuous A D conversions Not tested in production Doc ID 022171 Rev 3 53 90 Electrical characteristics STM8S007C8 Current consumption curves Figure 10 and Figure 11 show typical current consumption measured with code executing in RAM Figure 10 Typ Ipp RUN vs Vpp HSI RC OSC fcru 16 MHz lbpeunyasi MA ai18796 Figure 11 Typ Ipp wFi vs Vpp HSI RC OSC fepy 16 MHz lppwenxsi MA ai18797 54 90 Doc ID 022171 Rev 3 ky STM8S007C8 Electrical characteristics 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and Ty Table 29 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit lan an e clock source 0 24 MHz Vasen input pin high level 0 7 x Vpp Vpp 0 3 V Vie input pin low level Va 0 3 x Vpp ILEAK HSE PRERA Vss lt Vin lt Vpp 1 1 HA 1 Data based on characterization results not tested in production Figure 12 HSE external clock source External clock source Vus
84. upt enable register 0x00 0x00 5322 TIM3_SR1 TIM3 status register 1 0x00 0x00 5323 TIM3_SR2 TIM3 status register 2 0x00 0x00 5324 TIM3_EGR TIM3 event generation register 0x00 0x00 5325 TIM3 TIM3 CCMR1 TIM3 capture compare mode register 1 0x00 0x00 5326 TIM3 CCMR2 TIM3 capture compare mode register 2 0x00 0x00 5327 TIM3 CCER1 TIM3 capture compare enable register 1 0x00 0x00 5328 TIM3 CNTRH TIM3 counter high 0x00 0x00 5329 TIM3_CNTRL TIM3 counter low 0x00 0x00 532A TIM3_PSCR TIM3 prescaler register 0x00 Dr Doc ID 022171 Rev 3 33 90 Memory and register map STM8S007C8 Table 8 General hardware register map continued Address Block Register label Register name keno 0x00 532B TIM3 ARRH TIMS auto reload register high OxFF 0x00 532C TIM3 ARRL TIM3 auto reload register low OxFF 0x00 532D TIM3 CCR1H TIM3 capture compare register 1 high 0x00 0x00 532bE mm TIM3 CCR1L TIM3 capture compare register 1 low 0x00 0x00 532F TIM3 CCR2H TIM3 capture compare register 2 high 0x00 0x00 5330 TIM3 CCR2L TIM3 capture compare register 2 low 0x00 Reserved area 15 bytes 0x00 5340 TIM4 CR1 TIM4 control register 1 0x00 0x00 5341 TIM4 IER TIM4 interrupt enable register 0x00 0x00 5342 TIM4 SR TIM4 status register 0x00 0x00 5343 TIM4 TIM4 EGR TIM4 event generation register 0x00 0x00 5344 TIM4 CNTR TIM4 counter 0x00 0x00 5345 TIM4
85. ur high sink I Os used at the same time in output at low level with Io 20 mA Vo 1 5 V Maximum two true open drain I Os used at the same time in output at low level with lo 20 mA Vg 22V PINTmax 215 mA x 5 5 V 82 5 mW Piomax 10 MA x 2 V x 8 20 mA x 2 V x 2 20 MA x 1 5 V x 4 360 mW This gives PiNTmax 82 5 mW and Piomax 360 mW Ppmax 82 5 mW 360 mW Thus Ppmax 443 mW Using the values obtained in Table 50 Thermal characteristics on page 84 T Jmax is calculated as follows for LOFP64 10 x 10 mm 46 C W TJmax 82 C 46 C W x 443 mW 82 C 20 C 102 C This is within the range of the suffix 6 version parts 40 lt Tj lt 105 C In this case parts must be ordered at least with the temperature range suffix 6 Doc ID 022171 Rev 3 85 90 STMS development tools STM8S007C8 11 86 90 STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation system supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STM8 is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is design
86. vs Vpp E 3 temperatures ai18798 Figure 17 Typical pull up resistance vs Vpp E 3 temperatures a a o o a o Pull Up resistance kO A Cc wo a ai18799 Doc ID 022171 Rev3 61 90 Electrical characteristics STM8S007C8 Figure 18 Typical pull up current vs Vpp E 3 temperatures 140 o eo Pull Up current HA 40 0 2 3 4 5 6 Voo V ai15068b 1 The pull up is a pure resistor slope goes through 0 Table 36 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 8 pins sunk lo z 10 mA Vpp 25V 2 You Output low level with 4 pins sunk lio 4 mA Vpp 3 3 V 100 l Von Output high level with 8 pins sourced lig 10 mA Vpp 5 V 2 8 V Output high level with 4 pins sourced lig 4 MA Vpp 3 3 V 2 10 1 Data based on characterization results not tested in production Table 37 Output driving current true open drain ports Symbol Parameter Conditions Max Unit lo 10 mA Vpp2 5 V 1 VoL Output low level with 2 pins sunk lio 10 mA Vpp 3 3 V 150 V lio 20 mA Vpp 2 5 V 20 1 Data based on characterization results not tested in production 62 90 Doc ID 022171 Rev 3 a STM8S007C8 Electrical characteristics Table 38 Output driving current high sink ports Symbol Parameter Conditions Min Max Unit Output low level
87. ximum time to put the data in Hi Z Ji Doc ID 022171 Rev 3 71 90 Electrical characteristics STM8S007C8 Figure 33 SPI timing diagram slave mode and CPHA 0 SU NSS p a te SCK gt h NSS 7 CPHA 0 if po CPOL 0 SCK Input OO 3i iT o o A r h SO lla tr SCK tdis SO re Tej mi ti E MISO C OUTPUT MSBOUT MSBOUT X BITO OUT Bom o o OUT tsu SI 9 4c m ain Xun X TT INPUT Ll su this gt ai14134 Figure 34 SPI timing diagram slave mode and CPHA 1 NSS input CPHA 1 df X f NX CPOL 0 TN CPHA 1 t E CPOL 1 mm ai o or 7 Jai SCKy at di th SO lt gt is SO e MISO AM OUTPUT wow BIT6 OUT BOT OUT me Sl ia SI INPUT man I I AN issn IN ai14135 SCK Input 1 Measurement points are done at CMOS levels 0 3 Vpp and 0 7 Vpp a 72 90 Doc ID 022171 Rev 3 STM8S007C8 Electrical characteristics Figure 35 SPI timing diagram master mode High NSS input SCK Output I I CPHA 0 r 1 1 I CPHA 1 N CPOL 0 IR l I I I CPHA 1 N I i i E CPOL 1 l lim 1 i t 1 I i tw SCKH i A EE tsu MI anal ug RM r SCK SCK Output tw SCKL PIE MISO Eur um INPUT MsBING BITO IN LBN O IN I th klan MSBOUT OUT MSBOUT BIT1 OUT 8
88. y dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Software recommendations The software flowchart must include the management of runaway conditions such as e Corrupted program counter e Unexpected reset e Critical data corruption control registers Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see application note AN1015 Table 45 EMS data Symbol Parameter Conditions Level class V Voltage limits to be applied on any I O pin to un aa e C 2B FESD i f MASTER 7 induce a functional disturbance conforming to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 5 V Ta 25 C Verte applied through 100pF on Vpp and Vas pins fyasterR 16 MHz 4A to induce a functional disturbance conforming to IEC 61000 4 4 Doc ID 022171 Rev 3 79 90 Electrical characteristics STM8S007C8 Electromagnetic interference EMI Emission tests confo

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