TIP-VBY1HS Receiver Core User Manual
Contents
1. 27 Table 8 5 Spartan 6 GTP Transceiver Performance 27 Table 8 6 Video data format VS 29 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 5 inreviun 1 Introduction This chapter introduces the Tokyo Electron Device Ltd TED s Receiver Core that makes up V by One HS standard IP Core TIP VBY1HS designed for Xilinx FPGAs It also describes design environment for development and provides other related information V by One HS standard has been developed by THine Electronics Inc to offer capabilities for Flat Panel Display FPD markets that are requiring ever higher frame rates and higher resolutions This manual provides information about how to edit the TIP VBY1HS Receiver Core s wrapper files and constraint files and so on 1 1 About the Core TIP VBY1HS Receiver Core is a Soft IP designed for Verilog HDL design environment It can be implemented in any suitable arrangement with User Logic for the following FPGA family Hardware Validation The TIP VBY1HS Core has acquired a connectivity certification from THine electronics Inc by successfully completing a connectivity test between an FPGA board with the Core and a V by One HS evaluation board Target Device Target devices of the TIP VBY1HS Core include the Virtex 6 family with GTX Transceiver and the Spartan 6 family with GTP Transceive2. Gets 514 Blank lt d ine bod oU Lo s _ _ EE NN _ i Figure 7 1 Allocation of pixel to Data Lane Rev1 00 TOKYO ELECTRON DEVICE LIMITED 25 inreviun 8 Appendix 2 8 1 Reference clock When GTX GTP Transceiver requires the different frequency reference clock to the pixel clock transmitter side requires the external PLL to generate the REFCLK In addition REFCLK is recommended to be supplied by the exclusive differential port and to be satisfied the specification shown in Table 8 1 and Table 8 2 Table 8 1 Virtex 6 GTX REFCLK Characteristics Symbol Description Max Units Reference clock frequency ange 625 650 MHz TDCREF Reference clock duty cycle Rxppmtol Data REFCLK PPM offset tolerance Table 8 2 Spartan 6 GTP REFCLK Characteristics Symbo Description min Tp Mex Unis Reference dock Jitter toleranca 80 160 ps TDCREF Reference clock duty cycle 45 5 5 Rxppmtol Data REFCLK PPM offset tolerance 200 200 ppm Figure 8 1 shows the construction of the Receiver FPGA board In addition to the same purpose as the Transmitter side the Receiver side has the external VCXO PLL IC to generate the initial REFCLK of the frequency that is required for the Clock Data Recovery CDR of the GTP GTX
3. Figure 2 2 User Data Interface Timing Chart As shown in Figure 2 3 as the number of data lanes increases the effective period for Control data is shortened since the ineffective period at both ends increases This should be considered when using Control data DE Minimum DE low cycle without CTL lane Active lt 2 2lanes icycle 4 Active gt icycle 4 SINE 4lanes lt 3 Active lt 3cycle gt g lanes P gt Active lt x lt 16 Figure 2 3 Control Data Active Term Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun N Transceiver Interface Table 2 4 describes the Transceiver Interface signals Table 2 4 Transceiver Interface Signal Descriptions Signal ame REFCLK of GTX GTP Transceiver Positive optional me High speed serial Data Lanes negative Recovery clock output to External PLL optional Equalizer Setas 0 5 impt Highspeed serial Data Lanes postive RXO P N n 0 0 1 3 7 These are external pins of the FPGA for receiving the serial video data reception Input pins of Virtex 6 GTX Transceivers or Spartan 6 GTP Transceivers are used In the case of using the input pins of Spartan 6 GTP Transceiver the RX MAIN LINK module shown in Figure 2 1 Block Diagram section 2 1 Block Diagram is definitely mapped to a
4. Schedule of Tables Table 2 1 General Use Signal Descriptions 9 Table 2 2 Mode Setting Signal 9 Table 2 3 User Data Interface Signal 10 Table 2 4 Transceiver Interface Signal Descriptions 11 Table 2 5 Link Status Signal Descriptions 12 Table 3 1 RX Signal 13 Table 3 2 RX GEN Signal 14 Table 5 1 Parameterization Table of Wrapper file 16 Tapes ByE Mode Daa 16 Table 5 3 Parameterization Table 0 00000 20 Table 7 1 RGB YCbCr444 RGBW RGBY color data mapping 23 Table 7 2 YCbCr422 color data mapping 8 eee ea 24 Table 8 1 Virtex 6 GTX REFCLK Characteristics 26 Table 8 2 Spartan 6 GTP REFCLK 26 Table 8 3 PLL Divider Attribute and Common Values 27 Table 8 4 Virtex 6 GTX Transceiver
5. 5 000ns TIMESPEC TS 2 PXCLK FROM TNLCLK TO TN PXCLK 5 000ns HH Timing Ignore INST TN HTPDN INST rLOCKN TNLOOCKN INST FIELD BET ERR TN FIELDBET TIMESPEC TS HTPDN TIG FROM TN HTPDN TO TN HTPDN TIMESPEC TS LOCKN TIG FROM TNLOCKN TNLOCKN TIG TIMESPEC TS FIELDBET FROM FFs TO TN FIELDBET TIG Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun 6 2 Placement The following is a placement constraint for Virtex 6 GTX Transceiver These positions are only an example so it should be changed according with the GTX port to use Placement for GTX of Data Lane 0 INST MAIN LINKO1 U GTX WRAPO gtxO rx gtx wrap i gtxel i LOC GTXE1_X0Y0 Placement for GTX of Data Lane 1 INST U_RX_MAIN_LINK0O1 U_RX_GTX_WRAP1 gtx0_rx_gtx_wrap_i gtxel_i LOC GTXE1_X0Y1 Placement for GTX of Data Lane 2 INST U_RX_MAIN_LINK32 U_RX_GTX_WRAPO gtx0_rx_gtx_wrap_i gtxel_i LOC GTXE1_X0Y2 Placement for GTX of Data Lane 3 INST MAIN LINK32 U GTX WRAPT1 gtxO rx gtx wrap i gtxel i LOC GTXE1_X0Y3 Placement for GTX of Data Lane 4 INST U_RX_MAIN_LINK54 U_RX_GTX_WRAPO gtx0_rx_gtx_wrap_i gtxel_i LOC GTXE1_X0Y4 Placement for GTX of Data Lane 5 INST U_RX_MAIN_LINK54 U_RX_GTX_WRAP1 gtx0_rx_gtx_wrap_i g
6. Limited Inrevium Division Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa 221 0056 Japan TEL 81 45 443 4031 81 45 448 4059 URL http www inrevium jp eng Email inrevium contact teldevice co jp Your Local Contact The Information described in this document will be changed from time to time without prior notice If you plan to buy and use this device product described herein please contact the sales person or address specified herein Tokyo Electron Device Limited shall not be liable for any claim by third party alleging an infringement of patent right or any other intellectual property right where alleged liability of Users arises by reason of using the information and drawing described in this document Tokyo Electron Device Limited shall not be liable for any claim by third party alleging an infringement of the patent right utility model right circuit layout use right copyright or any other intellectual property right where alleged liability of Users arises by reason of using this device product in combination with other products or of any derivative products integrating this device product This device product is not designed manufactured or intended for use 1 in hazardous environment requiring extremely high safety including without limitation in operation of nuclear reaction control in nuclear facility aircraft flight control air traffic control mass transport control medic
7. Transceivers After CDR is locked this VCXO PLL should be phase locked to the recovery clock and generate the REFCLK of frequency that is completely the same as the Transmitter side Receiver FPGA Receiver Main Links VCXO PLL pss Clock Synthesizer amp Jitter Cleaner MGTREFCLK pin Open drain output Lcucocss s v Figure 8 1 Receiver FPGA Recommended Board Design Rev1 00 TOKYO ELECTRON DEVICE LIMITED 26 inreviun 8 2 PLL configuration of Transceiver To make the Reference Clock MGTREFCLK of the GTX GTP transceiver equal to the Pixel clock of the V by One HS standard this core requires the tuning of transceivers PLL settings in the relation to the Byte mode and should have the limitation of clock rate according to the transceiver s specification Equation 8 1 shows how to determine the PLL output frequency GHz means the frequency of the Reference Clock FPLLOkout NI N2 M Equation 8 1 Equation 8 2 shows how to determine the line rate Gbps FLineRate 2 D Equation 8 2 Table 8 3 shows the actual attribute and commonly used divider values Table 8 3 PLL Divider Attribute and Common Values Valid Settings TXPLL_DIVSEL_REF RXPLL_ DIVSEL_REF N1 TXPLL_DIVSEL45_FB 4 5 1 RXPLL DIVSEL45 FB TXPLL DIVSEL FB RXPLL DIVSEL FB 1 2 4 9 TXPLL DIVSEL OUT
8. Use Signal Descriptions This signal clears all functional blocks Mode Setting Signals Table 2 2 describes the Mode Setting signals Table 2 2 Mode Setting Signal Descriptions FIELD BET Field BET Mode Enable In the mode to check the quality of high speed serial data lines Field BET Mode enables FIELD BET input to receive a data pattern like BET Bit Error Tester from a transmitting device in Field BET mode and validate it Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun N User Data Interface Table 2 3 describes the User Data Interface signals Table 2 3 User Data Interface Signal Descriptions PXCLK Output Pixel Clock VSYNC Output Vertical sync pulse L HSYNC Horizontal sync pulse Ou cowania Figure 2 2 shows the timing chart of the User data interface Video data is output as effective pixel region when DE is High active On the other hand Control data is output as effective data region when DE is Low inactive excluding a period of 1cycle before and after that period Note that there are constraints on this effective period dependent on number of lanes used For more information refer to the subsequent description TUUR UUU UUR UU REU LII LI UIT U UR UT ec d E E swo Q L LA TE QTE amp d DO Active Active Active CTL Active Active Active
9. data in packer and un packer mapping The color data mapping should refer to Table 7 1 and Table 7 2 Table 7 1 RGB YCbCr444 RGBW RGBY color data mapping ete une ud Unpacker output YCbCr444 YCbCr444 YCbCr444 YCbCr444 RGBY RGBY D mot mot m2 RJ DJ RBI RU sd 018 cvv cvo ci Goo _ 019 G v Byte 016 2 B ceio BI _pi7 5 1 BB od _ j j RH 20261 2 cO Byteg D27 B OM3 Boot pps cv qvo pps qv j B piso mot mot w Di mot pag wv wy png ww Disa Bc wy Bytes DISS Boot ww 00361 evo wve pag cv j ww piss mot j Www we Di9 WT 4byte mode 3byte mode 5byte mode Rev1 00 TOKYO ELECTRON DEVICE LIMITED 23 inrevium Table 7 2 YCbCr422 color data mapping Packer input amp 32bpp 24bpp 20bpp 16bpp Unpacker output YCbCr422 YCbCr422 YCbCr422 YCbCr422 ByteO Byte _ s B
10. 120Hz 36 bit II 18 24bt QG 240Hz AX s Dom v v ve w __ 18 24 bit _ Um m 60Hz 36 bit 18 24 bit 49 L8 9 _ 120Hz 36 bit EZB RD ERN 18 24 QG 240Hz 594MHz vw wv vwa w oo iB 2Abt wa G 60Hz 594MHz v v va 36 bit 2 AKx2K 1188MHz 16 30 bit 36bit 18 24 bit Z 2376MHz 30bt 2 36bit 2 1 Frequency of the GTX s REFCLK should not be integer dividing ratio to the pixel clock ones 2 Requires the double number of Data lanes 1lane gt 2lanes 2lanes gt 4lanes 4lanes gt 8lanes 3 Although Data rate of the lane will be higher than it needs the 30bit color depth mode is able to cover the 18 24bit color depth Rev1 00 TOKYO ELECTRON DEVICE LIMITED 29 INIEVIUTI m m gt lt O a H Q m LLI O gt x O 5 x VBY1HS 3 3 E o 3 S i 3 2 3 E 3 L 3 o L L o L o 3 L L o 3 L o L o 3 E E E E 3 L _ L L o 3 3 2 L s o L o L L L 3 L 2 3 L r o j 3 S 3 3 Sz c M E 3 S 4 r o 3 o 3 S E o Ei TIP Rev1 00 inrevium W TOKYO ELECTRON DEVICE LIMITED Tokyo Electron Device
11. CLK frequency 297MHz for Virtex 6 PLL DIVSEL REF 1 DIVSEL FB 2 DIVSEL OUT 1 600MHz lt 297MHz P RXRECCLK MULT P RXRECCLK DIVIDE lt 1200MHz 1 1 P RXRECCLK MULT 2 P RXRECCLK DIVIDE must be integer 1 128 P RXRECCLK MULT 4 P RXRECCLK DIVIDE 1 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 17 inreviun N parameter P_PCLK PERIOD real II PCLK Period This parameter is used to set frequency period of PCLK input of Figure 3 2 RXUSRCLK from RX_PLL of Figure 3 1 This value can be calculated the following equation Pixel clock Period Number of Data Lanes Byte mode Example Pixel Clock period 6 734ns 148 5MHz Number of data lanes 2 Byte mode 4byte 6 734 2 4 3 367 ns parameter P PCLK MULT integer PCLK MULT parameter P PCLK DIVIDE integer PCLK DIVIDE This parameter is used to set frequency multiplication and dividing ratio of the PLL Figure 3 2 that generates an internal clock from the PCLK RXUSRCLK from RX PLL input These values should be observed the following rule Depending on the VCO specification In the case of Spartan 6 the value in is corresponded 600 400MHz lt P PCLK MULT P PCLK DIVIDE lt 1200 1000 MHz Example PCLK frequency 297MHz for Spartan 6 400 2 lt 297MHz P PCLK MULT P PCLK DIVIDE lt 1000MHz P PCLK MULT 2 or 3 P PCLK DIVIDE 1 X Parameter of RX GEN module Although the RX CLK RST GEN in
12. Constraint File A constraint file RX_VX1HS_TOP ucf also contains some important parameters Table 5 3 shows the parameterization that can be defined within the User Constraint File RX VX1HS TOP ucf Table 5 3 Parameterization Table of UCF P PLL DIVSEL REF PLL Reference clock input Divider of GTX GTP Transceiver P PLL DIVSEL FB 1 2 4 5 PLL Feedback Dividers of PLL Feedback Dividers of GTXIGTP Transceiver 00 Transceiver P PLL DIVSEL OUT PLL Output Divider of GTX GTP Transceiver These parameter settings have a close relation with device specifications and characteristics of Virtex 6 GTX and Spartan 6 GTP For more information about the meaning and the effectiveness of these setting values refer to Chapter 8 2 of this document The attached TIP VBY1HS Transceiver PLL Settings Estimate Sheet Exel Sheet is helpful for calculating a setting value It is important to understand the basic idea of these parameters before calculating a setting value Rev1 00 TOKYO ELECTRON DEVICE LIMITED 20 inreviun N 6 Constraint the Core A constraint file RX_VX1HS_TOP ucf contains placement and timing constraints of major dedicated blocks It is needed to enter RX VX1HS TOP ucf directly as a constraint file with the same hierarchy with RX_VX1HS_TOP v or load it into a constraint file for the top hierarchy of User Logic on ISE 6 1 Timing The following are the timing constraints on clocks associated with the TIP VBY1HS Rece
13. RXPLL DIVSEL OUT 1 DIVSELA5 FB 5 when INTDATAWIDTH is High 10bit mode for 8B 10B encoding Table 8 4 and Table 8 5 show the GTX GTP Transceiver Performance Table 8 4 Virtex 6 GTX Transceiver Performance sme M E FGTPMAX Maximum GTP Transceiver data rate Am PLL frequency range 1 23 3 1272 7 FGCLK Reference clock frequency range 62 5 650 Table 8 5 Spartan 6 GTP Transceiver Performance T Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium Example Byte mode 4byte Pixel Clock frequency 148 5MHz No of Data Lanes 2 Data rate 32bit 148 5MHz 1 25 2 2 97bps Virtex 6 GTX peed grade 2 M 1 N1 5 must be this value N2 4 Fpliclkout 148 5MHz 5 x 4 2 97GHz 1 2 3 3GHz D 2 Flinerate 2 97GHz x 2 2 2 97Gbps 3 75Gbps Spartan 6 GIP speed grade 3 M 1 N1 5 must be this value N2 2 Fpliclkout 148 5MHz 5 x 2 1 485 2 1 2 1 62GHz D 1 Flinerate 1 485GHz x 2 1 2 97Gbps 614Mbps 810Mbps 1 2288Gbps 1 62Gbps 2 457 Gbps 3 125Gbps Rev1 00 TOKYO ELECTRON DEVICE LIMITED 28 TIP VBY1HS RX_UM inreviun Table 8 6 shows the correspondence list for the video data formats Table 8 6 Video data format vs FPGA GTP GTP Resolution Serres die POI Color depth Spartan 6 Spartan 6 Pixel Clock Lane Virtex 6 sp 3 sp 2 18 24 bit 60Hz 74 25MHz 1 30 bit 36 bit w o ooo 18 24 bit
14. Signal Descriptions Direction Polarity Dee _ Parallel clock RKUSRCLK from RX PLL module H PLL locked signal from RX_PLL module owu tl ma l RX_PLL_ RX_PLL_LOCKED Output Locked signal of all PLLs emmser peer Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium 4 File Hierarchy Construction 4 1 Folders Figure 4 1 shows the design folder hierarchy in Transmitter Core folder contains the all wrapper sources and ISE folder contains the all NGC Netlists constraint files and ISE project of sample design DOC Documentations RTL RTL designs Wrapper files of the Macros ISE MACRO Macros NGC Netlists UCF Constraint files Z cna SIM RTL Simulation Figure 4 1 TIP VBY1HS Folder Hierarchy Construction 4 2 Source Files Figure 4 2 shows the RTL source and NGC Netlist hierarchy in Receiver Core Receiver Core can be customized by editing RTL source RX VX1HS TOP v and User Constraint File UCF RX FPGA TOP ucf and merging and implementing them RX FPGA TOP v RX_VX1HS_TOP v RX_CLK_RST_GEN v Sample Design RX_FPGA_TOP ucf RX PLL v RX DEFORMATTER v FIELD BET v FIELD BET ngc FORMAT BUF v S6 AFIFO F v S6 AFIFO F ngc V6 AFIFO F v V6 AFIFO F ngc S6 RX MAIN LINK ngc RX LANE X v S6 RX LINK v NGG Netlist V6_RX_MAIN_LINK v V6_RX_MAIN_LINK nge Fi
15. al life support system missile launch control in weapon system in which the failure of this device product could have a serious effect to the public and lead directly to death personal injury severe physical damage or other loss or 2 in any other environment requiring extremely high reliability including without limitation in operation of submarine transmissions or space satellite 2010 Tokyo Electron Device Limited printed in Japan Apr 2010 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 31 p inreviun W Rev1 00 TOKYO ELECTRON DEVICE LIMITED 32
16. cludes the following parameters to set the dividing values of PLL outputs for all combinations of the byte mode and number of Data Lanes more simple constitution that makes an appropriate frequency for PXCLK and LCLK would be acceptable These dividing values should be observed the following rules P nBYTE PXCLK DIVIDE P PCLK MULT P PCLK DIVIDE P BYTE MD PLANE NUM P nBYTE LCLK DIVIDE P PCLK MULT P PCLK DIVIDE P BYTE MD Example II P PCLK MULT 4 8 in the case of P NUM LANE 8 PCLK DIVIDE 1 parameter P 3BYTE PXCLK DIVIDE LANE NUM z21 12 P LANE NUM 2 76 LANE NUM 4 3 3 parameter P 4BYTE PXCLK DIVIDE P LANE NUM 1 16 P LANE NUM 2 78 P LANE NUM 4 4 4 parameter P 5BYTE PXCLK DIVIDE LANE NUM 1 20 P LANE NUM 2 10 P LANE NUM 224 25 5 MULT 4 8 in the case of P NUM LANE 8 P PCLK DIVIDE 1 parameter P 3BYTE DIVIDE LANE NUM 8 24 12 parameter P 4BYTE DIVIDE P LANE NUM 8 32 16 parameter P 5BYTE DIVIDE LANE NUM 8 40 20 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inrevium Simulation attributes parameter P SIMSPEEDUP 0 II Set to 1 for speed sim reset parameter P SIMULATION 0 II Set to 1 for simulation These parameters are set to 1 for RTL Simulation Set 0 for Normal Merging Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun N 5 2
17. d soft IP core that is provided in the form of a NGC Netlist for V by One HS compliant components and a Verilog RTL for other components 2 1 Block Diagram The Receiver Core is partitioned into three major blocks as shown in Figure 2 1 RX LANE X Provides for the delivery of the video stream This block contains major functional blocks called RX MAIN LINKs based on the number of Data Lanes Each RX MAIN LINK has two Data Lanes one Data Lane is valid in single Data Lane setting DEFORMATTER This block restores formatted data from the RX LANE X block and outputs to User Logic RX RST GEN This block generates all clocks needed for the above blocks FPGA RX VX1HS TOP RX DEFORMATTER MGTREFCLK P N AFIFO_F PME T NGC Netlist RXO P N RX LINK 0 1 NGC Netlist dia ial AFIFO_F NGC Netlist s LN VSYNC N 1 0 s LNO HSYNC N 1 0 s DE N 1 0 s LNO DI N 40 1 0 s LNO CTL N 24 1 0 VSYNC HSYNC DE DI 39 0 CTL 23 0 XN Number of Data Lanes RXn 1 P N gt RX MAIN LINK n 1 n RXn P N NGC Netlist FIELD BET FIELD BET NGC Netlist FIELD BET CHK PXCLK RXRECCLK RXUSRCLK2 RXUSRCLK RX CLK RST GEN PDN Figure 2 1 Receiver Core Top Level Block Diagram Rev1 00 TOKYO ELECTRON DEVICE LIMITED 8 inreviun 2 2 Receiver Core Interfaces General Signals Table 2 1 describes the General Use signals Table 2 1 General
18. eiver parameter P RXRECCLK PERIOD real RXRECCLK Period This parameter is used to set frequency period of the recovery clock that is output from the GTP GTX Transceiver This value can be calculated by following equation Refer to chapter 5 2 Constraint File about PLL DIVSEL parameter for Virtex 6 RXRECCLK PERIOD Pixel clock Period P BYTE MD 8 1 25 PLANE NUM Z PLL DIVSEL OUT 2 PLL DIVSEL REF PLL DIVSEL FB 5 for Spartan 6 RXRECCLK PERIOD Pixel clock Period P BYTE MD 8 1 25 P LANE NUM Z PLL OUT DIVSEL REF PLL DIVSEL FB 5 Example Pixel clock Period 6 734ns 148 5MHz 4 byte mode 2 data lanes for Spartan 6 PLL DIVSEL REF 1 DIVSEL FB 2 DIVSEL OUT 1 RXRECCLK PERIOD 6 734 4 8 1 25 2 1 1 2 5 3 367 parameter P_RXRECCLK_MULT integer RXRECCLK PLL MULT parameter P_RXRECCLK_DIVIDE integer RXRECCLK PLL DIVCLK_DIVIDE This parameter is used to set frequency multiplication and dividing ratio of PLL Figure 3 1 that generates an internal clock from the recovery clock RXRECCLK output of the GTP GTX Transceiver in the MAIN_LINK block These values should be observed the following rules 600 400 lt P RXRECCLK MULT P RXRECCLK DIVIDE lt 1200 1000 MHz PLL_DIVSEL_REF PI L DIVSEL OUT P RXRECCLK MULT PLL DIVSEL FB P RXRECCLK DIVIDE must be integer 128 Example RXREC
19. gure 4 2 TIP VBY1HS RX Source Hierarchy Construction Rev1 00 TOKYO ELECTRON DEVICE LIMITED TIP VBY1HS RX_UM inreviun 5 Parameterization 5 1 Wrapper File RX VX1HS TOP v is a wrapper file that can be regarded as a single hierarchy or used by merging it into the top hierarchy of user logic Table 5 1 shows the parameters that are defined in the wrapper file VX1HS TOP v Table 5 1 Parameterization Table of Wrapper file Select the target FPGA P FPGA TYPE 0 1 0 Virtex 6 1 Spartan 6 Division rate of the PCLK reference PLL output parameter P FPGA TYPE integer I 1 Spartan6 0 Virtex6 This parameter is used to select a target FPGA type Based on this parameter a dedicated module for Virtex 6 or Spartan 6 is called in the merge routine parameter P LANE NUM integer II TX Lane Number 1 2 4 8 This parameter is used to set the number of Data Lanes parameter BYTE MD integer II Byte mode 3 4 5 This parameter is used to set Byte Mode for user data interface Table 5 2 provides a mapping table between Byte Mode setting and DO CTL output effective bit width Table 5 2 Byte mode Data Mapping P BYTE MD DO 39 0 CTL 23 0 o8 30 70 39 0 23 0 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun parameter P REFCLK PERIOD real Reference clock Period This parameter is used to set frequency period of a REFCLK that is input as a reference clock for the GTP GTX Transc
20. inreviun Preliminary TIP VBY1HS Receiver Core User Manual V by One9 HS Standard for Xilinx FPGA Rev 1 00 High speed and Reduced digital connection concept Tokyo Electron Device Ltd Rev1 00 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History The following table shows the revision history for this document Revision Dae 02 0 Rev 1 0 0E 2010 04 12 First Release Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun Table of Contents L WME TOON VIOI u UU tan a cuc aloce 6 1 1 About ca ia ta a a ta 6 1 2 Recommended Design Experience 7 1 3 Additional Core Resources insista poet a a Da nes 2 a a a tt e 7 SIDO 7 ES 7 2 Core 8 2 1 BIOCK DIA GFA PNE ta di tat taiat i altei 8 2 2 Receiver Core Interfaces 9 Clock Construction eee eee eee eee eee eee 13 A File uuu un mi ari anl i al UT 15 IP G OP U U u E 15 4 2 Source Files aaa aaa aaa aaa aaa ae 15 5 6 ae e aa aaa aaa ae aaa aaa rare 16 VID CL il ERIT IRR 16 5 2 Constraint File eee eee eee eee 20 O CONS ral p x x oa
21. is available TIP VBY1HS Data Sheet TIP VBY1HS Transmitter Core User Manual TIP VBY1HS Transceiver PLL Setting Estimate Sheet Excel TIP VBY1HS CVK Reference Design User Manual 1 4 Technical Support For technical support go to ipg support teldevice co jp Tokyo Electron Device Ltd TED provides technical support for this IP Core when used as described in the product documentation TED cannot guarantee timing functionality or support of product if implemented in devices that are not defined in the documentation if customized beyond that allowed in the product documentation TED also offers a contract based development service for customized design or additional function design ex more than 16 data lanes for Virtex 6 1 5 References The following V by One amp HS Standard and FPGA documentations were referenced when developing the TIP VBY1HS V by One HS Standard Version 1 2 Jan 15 2009 by THine Electronics Inc Virtex 6 FPGA GTX Transceivers User Guide UG366 v2 2 Feb 23 2010 Virtex 6 FPGA Data Sheet DC and Switching Characteristics 05152 v2 2 Feb 9 2010 Spartan 6 FPGA GTP Transceivers User Guide UG386 v2 1 Mar 30 2010 Spartan 6 FPGA Data Sheet DC and Switching Characteristics 05162 v1 4 Mar 10 2010 Rev1 00 TOKYO ELECTRON DEVICE LIMITED 7 inreviun 2 Core Architecture This chapter provides and overview of the TIP VBY1HS Receiver Core architecture The TIP VBY1HS is a full feature
22. iver Core in the case of 4 byte mode 148 5MHz pixel clock frequency 2 Data Lanes To make explanation plain the constraint values are matched with real movement speed So the value with the margin is recommended in the development Generating the clock groups and period constraints for each clock domain Recovery clock RXRECCLK TNM NET TN RXRECCLK TIMESPEC TS_RXRECCLK PERIOD TN RXRECCLK 3 367ns HIGH 50 RXUSRCLK for GTP GTX RXRECCLK period RXUSRCLK TNM NET TN RXUSRCLK TIMESPEC TS RXUSRCLK PERIOD TN RXUSRCLK 3 367ns HIGH 50 RXUSRCLK2 for GTP GTX RXRECCLK period 2 RXUSRCLK2 TNM NET TN_RXUSRCLK2 TIMESPEC TS RXUSRCLK2 PERIOD TN RXUSRCLK2 6 734ns HIGH 50 Pixel clock NET PXCLK NET TN PXCLK TIMESPEC TS PXCLK PERIOD TN PXCLK 6 734 HIGH 50 Lane clock LCLK TNM NET TIMESPEC TS PERIOD TNLCLK 13 468ns HIGH 50 Data Path Constraints between the other clock domains TIMESPEC TS RXUSRCLK 2 RXUSRCLK2 FROM TN RXUSRCLK TO TN RXUSRCLK2 5 000ns TIMESPEC TS RXUSRCLK2 2 RXUSRCLK FROM TN RXUSRCLK2 TO TN RXUSRCLK 5 000ns TIMESPEC TS RXUSRCLK 2 LCLK FROM TN RXUSRCLK TNLCLK 5 000ns TIMESPEC TS LCLK 2 RXUSRCLK FROM TN_LCLK TO TN RXUSRCLK 5 000ns TIMESPEC TS PXCLK 2 FROM TNPXCLK TO TNLCLK
23. le ll sii lie 21 O T TIMING so 21 0 2 ad S161 IQ er ASA a ae di ss 22 r eei ii a ata ee ta ee 23 7 1 Byte length and Color 23 7 2 Allocation of pixel to Data Lane 25 WMluo pebcQOT 26 8 1 Reference eee eee 26 8 2 PLL configuration Of Transceiver 2 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun Schedule of Figures Figure 2 1 Receiver Core Top Level Block 8 Figure 2 2 User Data Interface Timing 10 Figure 2 3 Control Data Active 10 Figure 1 RA PEL CONSILIERI uuu uu 13 Figure 3 2 RX RST GEN Construction 14 Figure 4 1 TIP VBY1HS Folder Hierarchy Construction 15 Figure 4 2 TD BX1HSip RX Source Hierarchy Construction 15 Figure 7 1 Allocation of pixel to Data 25 Figure 8 1 Receiver FPGA Recommended Board Design 26 Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun
24. ocked FIELD This notifies the result of checking the Field BET mode H Error Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun 3 Clock Construction Figure 3 1 shows the construction of the clock module RX PLL RX PLL_ADV MMCM_ADV RXRECCLK CLKIN CLKOUTO RXUSRCLK CLKINSTOPPED CLKOUT RXUSRCLK2 GTPPLLLKDET LOCKED RX PLL LOCKED Figure 3 1 RX PLL Construction Table 3 1 describes the RX PLL signals About the connection of each clock refer to the Figure 2 1 Top Level Block Diagram Table 3 1 RX PLL Signal Descriptions RXRECCLK Recovery clock from GTP G TX GTPPLLLKDET Locked signal from PLLLKDET port of GTP GTX Clock to RXUSRCLK port of GTP GTX and parallel k ES clock for RX MAIN LINK internal logic RXUSRELO Output Clock to RXUSRCLK2 port of GTP GTX K Output PLL locked signal Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun Figure 3 2 shows the construction of the clock module GEN RX_CLK_RST_GEN PLL ADV MMCM ADV PCLK CLKOUTO gt PXCLK CLKOUTI1 CLKOUT2 CLKOUT3 gt CLKOUT4 CLKOUT5 CLKINSTOPPED RX PLL LOCKED RX_PLL LOCKED HTPDNIn 1 0 GTPRESET PDN Figure 3 2 RX CLK RST GEN Construction Table 3 2 describes the RX CLK RST GEN signals About the connection of each clock refer to the Figure 2 1 Top Level Block Diagram Table 3 2 RX CLK RST GEN
25. r Note that dependent on FPGA transceiver specifications the following constraints are imposed on high speed data 5 transmission bandwidth that is provided by the transceiver 600Mbps 3 75Gbps per data lane same as the standard e Virtex 6 LXT XC6VxxxLXT all speed grade e Virtex 6 SXT XC6VxxxSXT all speed grade 614Mbps 810Mbps 1 2288Gbps 1 62Gbps 2 457Gbps 3 125Gbps per data lane e Spartan 6 LXT XC6SxxxLXT speed grade 3 4 speed grade 2 Maximum rate is less than 2 7Gbps Following equation shows how to determine the data rate of the lane Gbps FDataRata BI ByteMode FPixelCik 1 25 8B 10B Nane Example Byte mode 4byte Pixel Clock frequency 148 5MHz Number of data lanes 2 Data rate per lane 32bits x 148 5MHz x 1 25 2 2 97Gbps Besides the above there are other constraints and cautions that are attributed to FPGA specifications and characteristics For more information refer to the relevant chapters of this document and the FPGA data sheets Rev1 00 TOKYO ELECTRON DEVICE LIMITED 6 inrevium 1 2 Recommended Design Experience The following development environments are required to develop TIP VBY1HS Core Implement ISE 11 4 Logic Edition and above Synthesis Xilinx XST 11 4 and above Simulation Mentor Graphics ModelSim 6 5a and above for Verilog HDL 1 3 Additional Core Resources Besides this document the following support documentation
26. single GTP DUAL Tile Two GTPs exist in GTP DUAL Tile So in the case of 1 Data Lane and 2 Data Lanes one GTP DUAL Tile should be used in the case of 4 Data Lanes two GTP DUAL Tiles should be used and in the case of 8 Data Lanes four GTP DUAL Tiles should be used As for Virtex 6 there are no above constraints REFCLK 0 REFCLK P N1 Two external reference clock input pins are provided for Spartan 6 GTP Transceiver They are used to provide a clock to each GTP DUAL Tile on the top and bottom sides of FPGA If only either side of GTP DUAL Tile is used it is not needed to have two clock pins For more information about GTP DUAL Tile refer to the Spartan 6 FPGA GTP Transceivers User Guide As for Virtex 6 there are no above constraints Rev1 00 TOKYO ELECTRON DEVICE LIMITED 11 inreviun Link Status Signals Table 2 5 describes the Link Status signals Table 2 5 Link Status Signal Descriptions HTPDN Output Hot plug detect LOCKN Output Lock detect FIELD BET CHK Output Filed BET mode Check Error Status This is an external pin connecting to the equivalent output pin of a transmitting end device It notifies the transmitter side of that the receiving end device has been connected This is an external connecting to the equivalent output pin of a transmitting end device It notifies the transmitter side of that the clock data recovery CDR of the receiving end device has been l
27. txe1_i LOC GTXE1_X0Y5 Placement for GTX of Data Lane 6 INST MAIN LINK76 U GTX WRAPO gtxO rx gtx wrap i gtxel i LOC GTXE1_XOY6 Placement for GTX of Data Lane 7 INST MAIN LINK76 U GTX 1 2 0 rx gtx wrap i gtxel i LOC GTXE1 X0Y7 The following is a placement constraint for Spartan 6 GTP Transceiver These positions are only an example so it should be changed according with the GTP port to use Placement for GTP of Data Lanes 0 1 INST RX MAIN LINKO1 tileO rx gtp wrap i gtpal duali LOC GTPA1 DUAL XOYO Placement for GTP of Data Lanes 2 3 INST MAIN LINK32 tileO rx gtp wrap i gtpal LOC GTPA1 DUAL X1YO Placement for GTP of Data Lanes 4 5 INST MAIN LINK54 tileO rx gtp wrap i gtpal LOC GTPA1 DUAL XOYI1 Placement for GTP of Data Lanes 6 7 INST RX MAIN LINK76 tileO rx gtp wrap 1 LOC GTPA1 DUAL X1Y1 The contents mentioned above are the constraints necessary to a minimum So it is also recommended to add appropriate placement constraints to clock sources such as PLL BUFG and BUFIO2 at a good balance with the user logic Rev1 00 TOKYO ELECTRON DEVICE LIMITED 22 inreviun N 7 Appendix 1 7 1 Byte length and Color mapping The V by One HS can be used to various types of color video format allocating D 39 0 to pixel
28. yte2 3byte mode 4byte mode pel j j J opo Jj 221 op 0011 opg va Does avo Lob evotn vi Popa 1 1 Lope ovo wd w4 ws x4 Lope ovot Lope 5byte mode Rev1 00 TOKYO ELECTRON DEVICE LIMITED inreviun 7 2 Allocation of pixel to Data Lane Depend on the data rate and pixel color depth it is permitted to increase the Data Lanes About the multiple Data Lanes combination Refers to Figure 7 1 The V by One HS compliant components must be implemented with at least one Data Lane If the data rate of the required color depth and timing is higher than the components maximum supported data rate additional Data Lane can be used The maximum data rate of V by One HS Data Lane is 3 5Gbps per lane In this case total lane count should be even number under the condition of the fewer lane number The pixel number for the horizontal active and blanking term H active H blank should be adjusted to become the multiple number of the lane count Lane 1 Lane 2 Lane 3 Lane N L C NEN s Blanking End amp System Reset
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