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User`s Manual

1. App 3 S TECHNICA Co LTD MKY40 User s Manual Appendix 2 Internal Equivalent Block Diagram in IO Mode Data expanded onto owned area D 1028 to 1031 tee a 4 CT gt 1 M p De 1024 4 INV3 B DS to 1027 BS Dosas 4 gt 400844 5 Ll q gt 4 Bove BD MDOSAD ad 1020 ES Bop pus soswap D D5 88 22 P L 1016 are eee i j P 1012 L 1 to 1015 Received data from CUnet station specified with DOSA CLR it t D 1 108 i 2 to 1011 CL i CIR B 0015 D 104 to 7 21 89 Lf D 100 to 103 a CE OSTB1 n STB2 App 4 S TECHNICA Co LTD Appendix Appendix 3 Register List in Address Order Starting Section Register name addisss Width Target function Primary Window Read Control Register Primary Window Write Control Register Access control Secondary Window
2. 4 15 Fig 4 9 Data Hazards during 4 16 Fig 4 10 Secondary ee es 4 17 Fig 4 11 Appropriate Use of GMPW and GMSW eene 4 18 Fig 4 12 64 01 LFB aine nte note Rampe nbn taba eu IE Ua annuus 4 20 40 User s Manual STE Fig 4 13 Starting Point of Status Management eee 4 21 Fig 4 14 LFR Monitoring Dy LGH nire eaaet o no sn 4 22 Fig 4 15 64 bit MFR and ohne 4 23 Fig 4 16 MFR Monitoring by MGR and Bit Status of SSR 4 25 Fig 4 17 64 bit DRGR arid DRFR venice tee tee tex reed 4 28 Fig 4 18 Outline of Data Renewal Detection for Time Passage 4 30 Fig 4 19 Mail Hecelve BUITers 4 33 Fig 4 20 Permission for Mail Reception cessent 4 33 Fig 4 21 MROCR with Dataset Stored in eee 4 34 Fig 4 22 MR1CR with Dataset Stored in MRB1 eee 4 34 Fig 4 23 Mail Send eine ees ete eee 4 36 Fig 4 24 Operation of MSLR and MSCR eese nnns 4 36
3. 5 30 5 26 INTerrupt 2 Control Register INT2CR eere 5 31 5 27 INTerrupt 0 Status Register INTOSR eere 5 32 5 28 INTerrupt 1 Status Register 1 5 34 5 29 INTerrupt 2 Status Register INT2SR eere 5 34 5 30 Interrupt Timing 0 Control Register ITOCR eee 5 35 5 31 Interrupt Timing 1 Control Register IT1CR esee 5 36 5 32 Care CounTer Register 5 37 5 33 Query Control Register QCR 5 38 Chapter 6 Hardware in 6 3 Chapter 7 Operation and Connection in IO Mode 7 1 Internal Configuration of MKY40 in IO Mode eere 7 4 7 2 Operation In IO neret detras at aso ed abate 7 5 7 2 4 Sending of Internal Input Pin 7 5 7 2 2 Data Updating of Internal Output Pins esee ennt 7 5 7 2 3 Operation of General purpose External I O Pins lo0 to lo31 and Multi selector 7 6 7 2 4 Selection of Data Output to Inter
4. Ida cuv ade 3 9 Fig 3 8 Example of Station Address Setting 3 11 Fig 3 9 Example of Owned Area Setting eese 3 12 Fig 3 10 Example of LED Display Pin Connection eere 3 13 Fig 3 11 Connection to 32 bit Wide User CPU eene 3 17 Fig 3 12 Connection to 16 bit Wide User CPU eene 3 19 Fig 3 13 Connection to 8 bit Wide User CPU eene 3 21 Fig 3 14 Precautions for User Bus Connection cere 3 22 Fig 3 15 Data Storage Method nette trucem orta 3 23 Start 5 45 iiia rose ihv in rata eris ena aea 4 5 Fig 4 2 Phase Transition of MKY40 and Corresponding Bits of SCR 4 6 Fig 4 3 Write POTS CUI paca tu IDE COD XE 4 7 Fig 4 4 Station Times Indicated by Bits 0 to 6 of SCR 4 8 Fig 4 5 Global Memory GM iie iuc ceti cones pde cet cue Ec aci OPUS en eo ee 4 12 Fig 4 6 Expansion of Owned enne nnn 4 13 Fig 4 7 Mechanism of Data Hazard 4 14 Fig 4 8 64 bit Data Read via 8 bit
5. seen 3 24 S TECHNICA Co LTD MKY40 User s Manual Chapter 4 Software in MEM Mode 4 1 Start and Stop of Communication eese 4 3 4 1 1 Memory Map Lerner eI erret eren 4 4 4 1 2 Checking Connection of 4 4 4 1 3 Initialization and Start up of 4 5 4 1 4 Responses to Each Phase esses eene nennen ennt n innen nannten 4 6 4 1 5 Protection against 4 7 4 1 6 Cycle Time of nente enema annt nnns daek aaan samak uhisani 4 8 4 1 7 Detailed Timing during 4 8 4 1 8 ME DOSE 4 9 4 1 8 1 Details of SNF Station 0 4 10 4 1 8 2 Details of OC Out of Cycle 4 10 4 1 8 3 Stop ueniens 4 10 4 1 8 4 Stop Exception 2 inrer tette ett Peer reete eiie Dente ei 4 11 4 2 gt MSS ode Tw 4 12 4 2 1 4 12 4 2 2 Data Hazards and Protection Against Data
6. gt 0 111 ET BIS LI LI L EL EHE 111 111 11111111 10 t O O O O x QN 10 6 D 10 10 VDD VDD RXD I 1015 1014 TXD I 1013 SAO I 1012 SA1 I 1011 SA2 1 1010 SA3 TT 109 SA4 11 7 108 SA5 C 11 7 STB2 DOSAO 113 GND DOSA1 TT GND DOSA2 GND DOSA3 CO VDD DOSA4 I lo7 DOSA5 11 7 106 TTT 105 DONA I lo4 como 11 7 103 EXC TTT 102 50 T1 01 BPS1 1 lo0 Xo Crm 113 STB1 Xi CoO IOSWAP VDD T1 VDD CO lt 1 cer CN CN CN CON CN LI LI LI LI Li LI ETE OUL LI LI LI LI E 111 E ET 1 1 88000026 555528555500069 2222 02 6 04222222200060 c oO Lu OF gt connect Note Pins prefixed with are negative logic active Low Fig 6 1 Pin Assignment in Mode STECHNICA CO LTD 40 User s Manual Table 6 1 lists the pin functions in IO mode of the MK Y40 Table 6 1 Pin Functions in IO Mode Input pin that sets 40 mode Positive In IO mode always fix this pin at High Output pin with PING function that goes High when PING instruction r
7. 4 14 4 2 2 1 Window LOCk ceci ciun de 4 15 4 2 2 2 GMPW Read Window Lock eese eeeeeeeeen nennen nsn nnn nnn 4 15 4 2 2 3 GMPW Write Window LoCkK neuen sienne nnne nnne nnn nnnm 4 16 4 2 2 4 Relation between Window Lock Functions eene 4 17 4 2 2 5 Global Memory Secondary Window GMSW 4 17 4 2 2 6 Appropriate Use of GMPW GMSW esee 4 18 4 2 2 7 Protection Against Data Hazard Without Window Lock 4 19 4 2 3 Quality Assurance of GM 4 20 4 2 3 1 Status Indication by Registers sese 4 20 4 2 3 2 Starting Point of Status Management and Exception 4 21 4 2 3 3 Link Group Register 4 22 4 2 3 4 MEMBO Item eret REI 4 23 4 2 3 5 Member Flag Register MFR eene nnn 4 24 4 2 3 6 Member Group Register 4 24 4 2 3 7 Detection of Member Increase and 4 26 4 24 Detection of Global Memory Data Transition eere 4 27 4 2
8. S TECHNICA CO LTD 7 SIE 4 CUnet CUnet IC MK Y40 User s Manual Note 1 The information in this document is subject to change without prior notice Before using this product please confirm that this is the latest version of this document 2 Technical information in this document such as explanations and circuit examples are refer ences for this product When actually using this product always fully evaluate the entire sys tem according to the design purpose based on considerations of peripheral circuits and the PC board environment We assume no responsibility for any incompatibility between this product and your system 3 We assume no responsibility whatsoever for any losses or damages arising from the use of the information products and circuits in this document or for infringement of patents and any other rights of a third party 4 When using this product and the information and circuits in this document we do not guaran tee the right to use any property rights intellectual property rights and any other rights of a third party 5 This product is not designed for use in critical applications such as life support systems Con tact us when considering such applications 6 No part of this document may be copied or reproduced in any form or by any means without prior written permission from StepTechnica Co Ltd S TECHNICA Co LTD MKY40 User
9. oni eite esiste ined ead uetus 3 9 3 5 Network Cable Length eere 3 10 3 6 Setting Station 3 11 3 7 Expansion Setting for Owned Area eese 3 12 3 8 Connecting LED Indication 3 13 3 9 Connection of Timing Notification Signal HSTB Pin 3 14 3 10 Connecting PING Signal archi itae noeh aec usata e unen un eben 3 14 3 11 Connecting General purpose Output Ports eee 3 15 3 12 Connecting User CPU Mines e tad patur eno ete 3 15 3 12 1 Connection of 32 bit Wide User 3 16 3 12 2 Connection of 16 bit Wide User CPU esses nennen 3 18 3 12 3 Connection of 8 bit Wide User 3 20 3 12 4 Recognition of 3 21 3 12 5 Designing Access 3 22 3 12 6 Access Test after Embedding MKYAO eee 3 23 3 12 7 Data Storage Method 5 neuen 3 23 3 12 8 Connection of Interrupt Trigger Signals
10. Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 2 2 7 Protection Against Data Hazard Without Window Lock Data hazards are caused by data changes due to data copying based on the sharing of memory data during several accesses from the user CPU Data hazards can be avoided without using the window lock if the user CPU can make several accesses at the timing when data copying based on the sharing of memory data does not occur In the CUnet the timing when data copying based on the sharing of memory data occurs can be recognized by Station Time ST The user system program can recognize ST by reading bits 0 to 6 STO to ST6 of the System Control Register SCR of the 40 refer to 4 1 7 Detailed Timing during Cycle Specific examples are shown below 1 When making several read accesses to the memory block corresponding to SA 03H addresses 018 to of the GMPW the user system program continues to read the SCR until the ST goes to other something than 03H and waits for read access to memory 2 If ST is not 03H after reading the SCR data hazards may not occur the user system program immediately makes several read accesses The above methods are applicable only when the user CPU is fast enough for the CUnet cycle and access after recognizing timing by the ST is terminated by the arrival of the timing of waiting until the next data hazard may occur For example the program pro
11. DRFR DRFR DRFR DRFR DRFR DRFR DRFR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Address 32 bit address 420H big amp little 16 bit address 420H big 422H little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial valie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Address 32 bit address 424H big amp little 16 bit address 426H big 424d little 15 47 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Address 32 bit address 424H big amp little 16 bit address 424 big 426d little 15 63 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR DRFR 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Functional description This register indicates the result of detection of data transition for a Memory Block M
12. gt OWNO UJ OWN1 OWN2 OWN3 OWN4 ZOWN5 MON LCARE MCARE EXC BPSO BPS1 X 1111 1 1 0 olv vvo wvv ololololololo olm 01 1 1 10 0 01 S TECHNICA Co LTD MKY40 User s Manual Figure 2 2 shows the electrical characteristics of pins in the MKY40 MEM mode Type B TTL Level input Type A CMOS Level input 35 v ViL max V lid max 1 5 10 A liL max TTL Level input 30 KQ pull up ViH min 10 A ViL max max Rpu typ 30 liL max min 12 max 75 min VoL max max loL max 12 max ViH min max max liL max VoH min VoL max loH max lo max 12 max Fig 2 2 Pin Electrical Characteristics in Circuit Types in MEM Mode V V ViL max 0 6 max 10 liL max TTL Level input Type D Schmitt trigger typ 10 A Vt typ min AVt min max liL max min VoL max loH max lol max 12 max Chapter 3 Connections in MEM Mode This chapter describes the pin functions and connections required for the MKY40 in MEM mode to func
13. 5 18 5 13 Data Renewal Flag Register 5 19 5 14 Primary Window Read Control Register 5 20 5 15 Primary Window Write Control Register PWWCR 5 20 5 16 Secondary Window Read Control Register SWRCR 5 21 5 17 Secondary Window Write Control Register SWWCR 5 21 5 18 Mail Receive 0 Control Register 5 22 5 19 Mail Receive 1 Control Register MR1CR 5 23 5 20 Mail Send Control Register 5 5 24 5 21 Mail Send Limit time Register 518 5 25 5 22 Mail Error Status Register 5 5 26 5 23 Mail Send Result Register MSRR 5 27 5 24 INTerrupt 0 Control Register INTOCR eene 5 28 5 25 INTerrupt 1 Control Register 1 1
14. Bit 10 9 8 B SSR 40 Ro 5 RW RW RW This goes to 1 when CUnet station in the BREAK phase is detected The BD goes to 0 when 1 is written to it Fig 4 30 BD Bit of SSR When bit 10 BD of the SSR changes to 1 the MK Y40 can output an interrupt trigger For details refer to 4 5 Interrupt Trigger Generation Function Bit 10 BD can be cleared by writing 1 It changes to 1 again when a break packet is received subse quently Perform expanded resizing to change FS values through operation in 4 4 2 Resizing of Cycle Time when the user system program that recognized the presence of a CUnet station in the BREAK phase by receiving interrupt triggers or by reading the SSR to check that the BD bit is 1 adds the CUnet station in the BREAK phase to a cycle resizing to the maximum FS value 63 Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 4 4 Detection and Handling of Jammer When a jammer CUnet station that can only send a packet due to hardware trouble or failure is detected the CUnet protocol defines that the MKY40 warns the user system about the jammer When a jammer is detected the MKY40 sets bit 9 JD Jammer Detect of the SSR to 1 and warns the user system program about it Fig 4 31 RW RW RW N This bit goes to 1 when a jammer is detected The
15. pin while the MKY40 transmits packets However the MKY40 is designed not to receive any packet transmitted by itself while the TXE pin is High so there is no problem Background information to help build a network are described in CUnet Technical Guide For more information about how to select components or to get recommended components visit our Web site at www steptechnica com STECHNICA CO LTD 40 User s Manual 3 3 2 Details of RXD TXE and TXD Pins The MKYAO receives packets transmitted from another CUnet station at pin and outputs packets transmitted to another CUnet station from the TXD pin During sending a packet a High level is output from the TXE pin When the TXE pin goes High design the TRX so that the enable pin of the TRX driver is activated thereby enabling the serial pattern for a packet output from the TXD pin to be transmitted to the network Fig 3 4 The 40 outputs input signals from the RXD pin to the TXD pin except while packets are being trans mitted while the TXE pin is Low This permits addition of a dedicated cable for connecting a GMM sta tion operated by the GMM function Fig 3 5 For details of the GMM station refer to 4 4 9 Global Memory Monitor GMM Function C SN Fig 3 5 Example of Adding Cable for GMM Station 3 3 3 Cautions for Directly Connecting to HUB IC When connecting the MK Y40 directly to a HUB IC such as
16. 2 inside the user equipment without the TRX components in order to allow for cables wired in a star topology take care not to input signals output from the TXD pin to the HUB IC while the TXE pin is Low only input packets to be transmitted from the 40 to the HUB IC Fig 3 6 C E MKY40 HCOB etc HUB IC 2 Fig 3 6 Example of Direct Connection to HUB IC Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD 3 4 Setting Baud Rate To set the baud rate of the MKY40 combine High and Low levels to be input to the BPSO pin pin 96 and BPS 1 pin pin 97 Figure 3 7 shows the levels of the BPSO and BPS 1 pins corresponding to the baud rates When a hardware reset is activated the MKY40 writes these pin settings to the BCR Basic Control Regis ter The baud rate can be reset by rewriting data of the BCR by the user system program For details refer to 4 1 3 Initialization and Start up of Communication When the external baud rate is set its value is 1 4 of the clock frequency supplied to the EXC pin pin 95 For example if the clock frequency supplied to the EXC pin is 5 MHz the baud rate is 1 25 Mbps The maximum clock frequency to the EXC pin is 12 5 MHz when Xi 50 MHz with a duty ratio of 40 to 60 Always fix the EXC pin at High or Low when not inputting any external clock to the EXC pin MKY40 7 Inthis setting the baud rate is 6 Mbps a
17. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R The number of cycles time required from when mail sending is started until it is completed is stored when mail sending is completed Fig 4 25 MSRR STECHNICA CO LTD 40 User s Manual 43 4 Operation against Mail Sending Errors The procedure and quality for mail sending reception are strictly managed by the CUnet protocol of the MKY40 Therefore a mail sending error exists only on the sending not on the receiving There are several types of mail sending errors as follows 1 NORDY destination NOt ReaDY Mail sending failed because mail receive buffer at a destina tion CUnet station is not in the RDY state 2 NOEX destination NOt EXist Mail sending failed because a destination CUnet station is not con nected to a network or is in a phase other than RUN 3 TOUT limit Time OUT Mail sending could not be completed within the cycle time set in the MSLR Mail Send Limit time Register 4 SZFLT SiZe FauLT Mail sending failed because the sizes hexadecimal of datasets set in bits O to 5 SiZe 570 to SZ5 of the MSCR Mail Send Control Register are invalid 5 LMFLT LiMit time FauLT Mail sending failed because the values hexadecimal set in bits O to 12 Limit Time LTO to LT12 of the MSLR Mail Send Limit time Register 6 STOP communication STOPped A self station changed to a phase other than RUN during ma
18. The BREAK phase is continued until access to a cycle is allowed by resizing other CUnet stations When access to a cycle is allowed the MK Y40 changes to the RUN phase S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode 7 4 4 Support for Resizing The MKYAO in IO mode cannot perform resizing Resizing can be performed from only the CUnet station other than the I O station MKY40 in MEM mode However when resizing is performed by the CUnet sta tion other than the I O station the internal Final Station FS values are updated and the MKY40 in IO mode 15 resized 7 4 5 Network Stop and Restart As mentioned before the MKY40 in MEM mode is stopped by the following three cases described in 4 1 8 Network Stop 1 0 is intentionally written to the START bit of the SCR System Control Register 2 SNF Station Not Found No link with CUnet stations other than the self station could be estab lished 32 cycle times consecutively 3 OC Out of Cycle Resizing by other CUnet stations caused timing loss to send self station packets at cyclic time sharing In the MKY40 in IO mode although a network will not stop intentionally the network may be stopped by 2 or 3 For details of network stop refer to 4 1 8 Network Stop If a network is stopped by the above 2 or 3 the MK Y40 in IO mode is restarted within 8 x TBPS time After a network is stopped by 2 SNF Station Not Found the 40
19. When using the frame option described in 4 4 10 Frame Option for HUB the LOF is fixed at 256 Final station FS values are stored in the FSR Final Station Register in registers of the 40 The ini tial FS value in a CUnet is 63 3FH If resizing described in 4 4 2 Resizing of Cycle Time is not per formed the value stored in the FSR is 63 3FH 4 1 7 Detailed Timing during Cycle The user system can recognize the detailed tim 2 5k ing during the cycle proceeding with frame tran sT 0 SCR fee ST6 ST5 ST4 ST3 ST2 ST1 STO sition in the MKY40 5 Llololololololo To recognize the detailed timing during a cycle 5 4 3 2 1 0 ST 1 the user system program needs to read the SCR ST6 ST5 ST4 ST3 ST2 ST1 STO Each value of bits 0 to 6 STO to ST6 of the Cn 0 0 0 0 0 0 1 SCR indicates Station Time ST Fig 4 4 5 2 When each value of bits 0 to 6 STO to ST6 of 2 ST6 515 514 513 512 811 0 01 0101011 0 the SCR corresponds to the setting values preset pi 5 in a given register the MK Y40 can output inter A ST 3 ST6 515 ST4 ST3 ST2 514 STO rupt triggers called alarm For details refer to 2 0 0 0 0 0 1 1 4 5 Interrupt Trigger Generation Func tion ST 65 41H ST6 ST5 ST4 ST3 ST2 ST1 STO MM k 5 Fig 4 4 Station Times Indicated
20. is set to this bit otherwise STECHNICA CO LTD 40 User s Manual 5 5 Final Station Register FSR Address 32 bit address 494H big amp little 16 bit address 496H big 494H little Initial value 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 R W R R R R R R R R R R R R R R R R Functional description This 15 a read only register where hexadecimal FS Final Station values are stored in its FSO to 55 Final Station bits 5 6 New Final Station Register NFSR Address 32 bit address 470H big amp little 16 bit address 472H big 470H little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial valie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R RW RW RW Functional description This is a register where a new FS Final Station value is written when performing resizing Resizing is performed when a hexadecimal NFS value is written to the NFSO to NFS5 New Final Station bits of this register When this device MK Y40 is not in the RUN phase writing to this register is ignored When the value written to this register is a value to exclude the self station owned area writing to the register is ignored refer to 4 4 2 2 Rejection of Resizing At completion of resizing always write 00H to this register never leave the register with any numerical value other than 00 For details of resizing refer to 4 4 2 Resizing of Cycle Time 5 E
21. is written when data in the INTOSR is 1004p 2 A new enabled interrupt factor occurs concurrently with a write operation to clear the statuses held in the INTOSR For example a new enabled interrupt factors 0004H occurs at the same time writing of 1000H when data in the INTOSR is 1000p 7 Example of occurrence of interrupt factor for bit 3 after occurrence of interrupt factor for bit 12 INTOSR Bit 12 INTOSR Bit 3 INTO pin 5 x Txi time User CPU interrupt detection 104 ns 48 MHz User CPU interrupt handling Outp gobs Low agaih due to interrupt factor for bit 3 of INTOSR Passage of time Write 1 to bit 12 of INTOSR Ss Fig 4 43 Operation Example of Retrigger Function Even if the interrupt controller of a user CPU is edge detection type the retrigger function of the MKY40 prevents interrupts from being lost unexpectedly If the interrupt controller is a type that enables the next interrupt occurrence when the End Of Interrupt EOI code is issued from the CPU it may be necessary to consider the order of issuing the EOI code and clearing the status of the INTOSR described in item 4 of 4 5 1 Operation of ZINTO Pin depending on whether the interrupt controller is edge detection type or level detection type Edge detection type The status of the INTOSR is cleared after the EOI code is issued If the INTOSR sta tus is cleared before issuing EOI the retrigg
22. BPS1 lt BPS Hi Hi Lo 96 Hi Lo Hi BPSO B aud rate 12 Mbps 6 Mbps 3 Mbps 777 95 A clock frequency of four times um 5 EXC the external baud rate is input tisseuimng Kept High or Low when not used Duty ratio 40 to 60 Frequency 12 5 MHz Xi 50 MHz Fig 3 7 Setting of Baud Rate when the user system program writes the baud rate to the BCR before starting the MK Y40 network This helps reduce component such DIP Switch In this case leave the BPSO and BPS1 pins open or keep High or Low The BPSO and 51 pins are connected pull up resistor in the 40 Leaving these pins open is comparable to keeping them High Caution 1 Set the same baud rates to all CUnet devices connected to the network 2 The EXC pin pin 95 is an input pin When not inputting external clocks fix the EXC pin High or Low and NEVER leave it open 3 Our recommended pulse transformers may not support baud rates other than 12 Mbps to 3 Mbps In this case use a pulse transformer matching the baud rate CO LTD 40 User s Manual 3 5 Network Cable Length In this manual each connection point of a multi drop network cable is called a branch Table 3 1 indicates the network cable length for the CUnet when using the network described in 3 3 Con necting Network Interface with 32 or less branche
23. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RAW RW Address 32 bit address 434H big amp little 16 bit address 434H big 436H little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RAW RW RW R W RW RW RW RW Functional description This register presets the bit corresponding to a Memory Block MB where data transition is detected when using the function to detect data transition of Global Memory GM The bit where 1 is writ ten is to be detected Bit 0 of the DRCR corresponds to MBO bit 7 to MB7 and bit 63 to MB63 The function of this register is also enabled when the MKY40 operates as a GMM Global Memory Monitor station Chapter 5 Register Reference in MEM Mode ST CO LTD 5 13 Data Renewal Flag Register DRFR Address 32 bit address 420H big amp little 16 bit address 422H big 420 little 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRFR DRFR DRFR DRFR DRFR DRFR DRFR
24. Fix the BWO pin pin 9 of the MK Y40 High and the BW1 pin pin 10 Low The WRHH ESEL pin pin 11 functions as the ESEL pin Fix the WRHH ESEL pin High when the user CPU is big endian and Low when the user CPU is little endian The WRHL AI pin pin 12 functions as the A1 pin Connect the address bus pin A1 output from the user CPU to the WRHL A1 pin Connect the address bus pins A2 to A10 output from the user CPU to the A2 to A10 pins pins 13 to 21 of the MKY40 Connect the data bus signal pins DO to D15 output from the user CPU to the DO to D15 pins pins 29 to 32 pins 42 to 49 Connect the RD signal output from the user CPU to the RD pin pin 23 The WRLH AO pin pin 40 functions as the WRLH pin Connect the write strobe signals D8 to D15 output from the user CPU to the WRLH AO pin pin 40 Connect the write strobe signals DO to D7 output from the user CPU to the WRLL pin pin 27 Connect the signal to arrange the MKY40 in memory to the CS pin pin 22 If the data bus signal pins DO to D15 of the user CPU enter the open floating state when all periph eral devices including the MK Y40 do not drive the data bus connect a pull up or pull down resistor The hardware designer should select an appropriate resistance value The D16 to D31 pins pins 53 to 60 pins 64 to 71 of the 40 are unused They should be pre vented from entering the open floating state Usually connect them to GND The precautions for connection
25. IOSWAP HIOSWAP Lo Fig 7 14 Concept of Use of IOSWAP Pin Input pin of A e g Io0 pin 29 is output pin of B Therefore a user circuit connected to A and B must be different User circuit for A only cannot be used for B Caution STECHNICA Co LTD MKY40 User s Manual 7 5 3 Use of LFS Long Frame Select Pin for HUB When inserting a HUB network cable branching unit into the networks shown in Figure 7 12 and Figure 7 13 fix the LFS pin of one or more MKY40 at Low If the LFS pin of one or more I O stations connected to a network is set Low all CUnet ICs connected to a network is set to a frame option state by the CUnet protocol The frame option is also set for the I O station which is later connected or powered to the frame option set network in operation The frame option enables the insertion of up to two HUBs network cable branching units into a CUnet network The CUnet with HUBs inserted into a network provides high degree of flexibility in connecting network and longer network cables for many applicable applications refer to User s Manual for HUB IC MKY02 The cycle time with a length of frame LOF of 256 is a cycle time calculated from Equations 4 1 and 4 2 described in 4 1 6 Cycle Time of CUnet Table 7 6 Frame option set Cycle Time with FS 63 Baud rate Cycle time 12 Mbps 3 520 ms 6 Mbps 7 040 ms 3 Mbps 14 080 ms Cautio
26. SA 0 OWN 2 Owned area at SA 2 ee SA 2 OWN 4 i p cai wned area a 2 030H 8 OWN 3 Owned at SA 8 T PECES SA 11 OWN 0 Owned area at SA 11 SA 12 OWN 1 040H 050H Owned area at SA 12 Fig 4 6 Expansion of Owned Area An owned area must not be duplicated in any CUnet stations constituting a CUnet For example if SA is set to 3 and OWN to 2 for one 40 SA must not be set to 4 for another MKY40 An owned area must not be duplicated when performing the setting described in sections 3 6 Setting Station Addresses 3 7 Expansion Setting for Owned Area and item 2 of section 4 1 3 Initialization and Start up of Communication Unless duplicated an owned area can be set widely For example in a CUnet consisting of two MEM sta tions each MEM station can have 256 byte owned area When the OWN width value of the BCR is the OWN width is treated as 1 If the value to which the SA value and OWN value stored in BCR are added exceeds 64 40H the value exceeding 64 is ignored For example if the SA value is 62 3EH and the OWN value is the OWN width is 2 If the SA value is 32 20H and the OWN value is 63 3FH the OWN width is 32 STECHNICA CO LTD 40 User s Manual 4 2 2 Data Hazards and Protection Against Data Hazards When another CUnet
27. This register controls mail transmission for data sets written to the MSB Mail Send Buffer Bit description send SiZe 520 to 525 bit bits O to 5 Function These are bits where the size of datasets for mail sending is set Write the size hexadecimal of datasets for mail sending before or at the same time 1 is written to the SEND bit bit 14 The dataset size uses 8 bytes as one unit For example if a dataset is 34 bytes its size is 05H If a dataset is a maximum of 256 bytes its size is 20H DeSTination station address DSTO to DST5 bit bits 8 to 13 Function These are bits where destination station addresses to which mail is sent are set Write the destination station address hexadecimal before or at the same time 1 is written to the SEND bit bit 14 mail SEND SEND bit bit 14 Function This bit starts mail transmission Write 1 to this bit when starting mail sending When the ERR bit bit 15 is 1 this bit is write protected When mail sending is terminated correctly or stopped by an error this bit is cleared to 0 When this bit is 1 mail sending is on writing to the MSB Mail Send Buffer is protected If the MSB is read when this bit is 1 the read data is set forcibly to OOH mail send ERRor ERR bit bit 15 Function This bit indicates that mail sending is terminated with an error When an error occurs during mail sending this bit transits t
28. d by owned expansion 05H to 1FH Reserved by manufacturer Caution For Frame option in Table 4 2 refer to 4 4 10 Frame Option for For Owned expansion refer to 3 7 Expansion Setting for Owned Area and 4 2 1 Details of Owned Area STECHNICA Co LTD MKY40 User s Manual 4 4 8 Operation of General purpose Output Ports To operate the output levels of four general purpose output port pins PoO to Po3 pins 3 to 6 of the MK Y40 write data to bits 0 to 3 of the SSR Bit 0 of the SSR corresponds to the pin and its bit 3 to the Po3 pin Write 1 to any of bits 0 to 3 to which a High level is output Fig 4 38 When the bus width connecting the user CPU and 40 is 16 or 32 bits and any of bits 8 9 and 10 of the write data to the SSR is 1 at 16 bit write access and 32 bit write access the lower 4 bits PoO to Po3 of data are not written to the SSR to prevent operational errors When a hardware reset is activated bits 0 to 3 are all set to 0 and the outputs of the PoO to Po3 pins are all Low Po2 Po1 Pin6 Pin5 Pin4 Pin 3 Pin MEI Bit 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Lok 5 MR MGNC MGNE 2 Poo R R R R R RW RW RW R R R R RW RW RW RW After hardware reset 0 o o o pz x o Write data to
29. written to an address out of scope the data is held in the PWWT corresponding to the lower address 4 2 2 5 Global Memory Secondary Window GMSW Addresses 200H to 3FFH shown in the memory map of the MKY40 2 the Global Memory Secondary Window GMSW to access Global Memory from the user CPU Fig 4 10 000H Primary Window GMPW 40 has independent functions for the GMSW equivalent to 1FFH those in 4 2 2 2 GMPW Read Window Lock and 4 2 2 3 GMPW 200H Sencondary Window Write Window Lock GMSW The GMSW read window lock can be used by writing a read count to lock the GMSW to the Secondary Window Read Control Register SWRCR Fig 4 10 Secondary Window The GMSW write window lock can be used by writing a write count to lock the GMSW to the Secondary Window Write Control Register SWWCR How to use these functions and the behavior and scope of the GMSW are the same as those for the GMPW S TECHNICA CO LTD MKY40 User s Manual 4 2 2 6 Appropriate Use of GMPW and GMSW If the GMPW is read for special processing ANE such as interrupt handling while the user sys Reading 64 bit data using 16 bit data bus tem program is using the PWRCR to read from the GMPW in several batches the data Read 64 bit data read from the GMPW in special processing Write 4 to PWRCR is output from
30. 0 1 1 Owned area of self station Low when any bit other than owned area of self station is 1 MON pin output Fig 4 35 Example of Output to MON Pin STECHNICA CO LTD 40 User s Manual 4 4 6 PING Instruction The 40 in RUN phase can issue the PING instruction to operate the PING pin output of other CUnet station connected to a network to the network The PING pin of the 40 is kept Low after hardware reset The 40 that received the PING instruc tion from the network produces a High level output at the PING pin The MKY40 where the PING instruction is received and the PING pin keeps High output outputs Low level signal of the PING pin and keeps Low until it receives next PING instruction When an interrupt trigger is enabled by receiving the PING instruction the interrupt trigger can also be out put from the MKY40 to a user CPU when the MKY40 receives the PING instruction For details refer to 4 5 Interrupt Trigger Generation Function What to use the PING pin output is not specified in the CUnet protocol and can be defined freely by the user system For example the PING pin output can be used to reset a user CPU when it runs away In the 40 to issue the PING instruction to operate the PING pin output of other CUnet station con nected to a network proceed as follows Fig 4 36 1 Write the destination S
31. 10 12 max ViH min ViL max lin max liL max VoH min VoL max loH max lo max 12 max Fig 6 2 Pin Electrical Characteristics in I O Circuit Types in IO Mode Chapter 7 Operation and Connection in Mode This chapter describes the operation and connection of the 40 in IO mode For a better understanding of this chapter read CUnet Introduction Guide and Chapter 1 MKY40 Role and Features 7 1 Internal Configuration of MKY40 in IO Mode 7 4 7 2 Operation in IO Mode eee 7 5 7 3 Connection in IO 7 10 7 4 Support for Phase Transition 7 21 7 5 Configuration Using Only I O Stations 7 24 S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode Chapter 7 Operation and Connection in IO Mode This chapter describes the operation and connection of the MKY40 in IO mode For a better understanding of this chapter read CUnet Introduction Guide and Chapter 1 MKY40 Role and Features In IO mode connect the MODE pin pin 2 of the MK Y40 to VDD High level of the power supply Con nect the VDD pins pins 26 37 50 61 76 100 to a 5 0 V pow
32. 466H big 464H little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Ca T To ine re Terre ve Tenere wer T T T Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R W RW RAW RW RW RW RAW RW RW RW RW RW RW R R Functional description This register indicates the interrupt factor generated by the interrupt trigger generation function of the INT2 pin The bit corresponding to the generated interrupt factor changes to 1 The user system program can determine which interrupt factor triggered an interrupt by reading this register When all the bits of this register go to 0 the INT2 pin returns to keep its High level output To clear a bit indicating 1 of this register to 0 write 1 to the bit writing 0 is ignored Bit description Mail Receive MR bit to Jammer Detect JD bit bit 2 to 15 Function For these bits refer to the explanation of the same bit in 5 27 INTerrupt 0 Status Register INTOSR Chapter 5 Register Reference in MEM Mode ST ECHNICA CO LTD 5 30 Interrupt Timing 0 Control Register ITOCR Address 32 bit address 468H big amp little 16 bit address 46AH big 468 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 one ons one ons one Tune ve n Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R RW RW RW RW RW R RAW RW RW RW RW
33. 4A2H big 4 0 little Bit 15 8 7 0 4BH K 4DH M R W R R Address 32 bit address 4A0H big amp little 16 bit address 4A0H big 4 2 little Bit 15 8 7 0 34H 4 59H Y R W R R Address 32 bit address 4A4H big amp little 16 bit address 4A6H big 4 4 little Bit 15 8 7 0 30H 0 R W R R Address 32 bit address 4 4 big amp little 16 bit address 4A4H big 4 6 little Bit 15 8 7 0 81H 1 76H v R W R R Functional description This register can read a byte type ASCII code 40 v1 from a little endian CPU It is a read only register to check whether the MKY40 is embedded 4YKM1v_0 is read from a big endian CPU 5 5 STECHNICA Co LTD MKY40 User s Manual 5 2 Basic Control Register BCR Address 32 bit address 498H big amp little 16 bit address 49AH big 498 little Initial value 0 0 R W R W R W R W R W R W R W R W R W R W Functional description This register stores the basic settings for the MK Y40 used to build a CUnet When a hardware reset 15 activated the setting state of each input pin is set as an initial value for part R W of this register This register can be written only when the GMM bit bit 15 of the SCR System Control Register is SI Bit description Station Addre
34. 826 00 1 652 00 3 304 00 860 33 1 720 67 3 441 33 895 00 1 790 00 3 580 00 930 00 1 860 00 3 720 00 965 33 1 930 67 3 861 33 1 001 00 2 002 00 4 004 00 1 037 00 2 074 00 4 148 00 1 073 33 2 146 67 4 293 33 1 110 00 2 220 00 4 440 00 1 147 00 2 294 00 4 588 00 1 184 33 2 368 67 4 737 33 1 222 00 2 444 00 4 888 00 1 260 00 2 520 00 5 040 00 1 298 33 2 596 67 5 193 33 1 337 00 2 674 00 5 348 00 1 376 00 2 752 00 5 504 00 1 415 33 2 830 67 5 661 33 1 455 00 2 910 00 5 820 00 1 495 00 2 990 00 5 980 00 1 535 33 3 070 67 6 141 33 1 576 00 3 152 00 6 304 00 1 617 00 3 234 00 6 468 00 1 658 33 3 316 67 6 633 33 1 700 00 3 400 00 6 800 00 1 742 00 3 484 00 6 968 00 1 784 33 3 568 67 7 137 33 1 827 00 3 654 00 7 308 00 1 870 00 3 740 00 7 480 00 1 913 33 3 826 67 7 653 33 1 957 00 3 914 00 7 828 00 2 001 00 4 002 00 8 004 00 2 045 33 4 090 67 8 181 33 2 090 00 4 180 00 8 360 00 2 135 00 4 270 00 8 540 00 2 180 33 4 360 67 8 721 33 2 226 00 4 452 00 8 904 00 2 272 00 4 544 00 9 088 00 2 318 33 4 636 67 9 273 33 2 365 00 4 730 00 9 460 00 unit us 12 Mbps 6 Mbps 3 Mbps 172 00 344 00 688 00 215 83 431 67 863 33 260 00 520 00 1 040 00 304 50 609 00 1 218 00 349 33 698 67 1 397 33 394 50 789 00 1 578 00 440 00 880 00 1 760 00 485 83 971 67 1 943 33 532 00 1 064 00 2 128 00 578 50 1 157 00 2 314 00 625 33 1 250 67 2 501 33 672 50 1 345 00 2 690 00 720 00 1 440 00 2 880 00 767 83 1 535 67 3 071 33 816 00 1 632 00 3 264 00 864 50
35. Chip Code Register Basic Control Register System Control Register System Status Register Final Station Register New Final Station Register Receive Flag Register Link Flag Register Link Group Register Member Flag Register Member detection Data transi tion detection Member Group Register 64 64 Data Renewal Check Register 64 64 Data Renewal Flag Register Primary Window Read Control Register 220 Primary Window Write Control Register Secondary Window Read Control control Register 5 20 Secondary Window Write Control Register Mail Receive 0 Control Register Mail Receive 1 Control Register Mail Send Control Register Mail sending Mail Send Limit time Register reception Mail Error Status Register Mail Send Result Register INTOCR INTO Control Register INT1CR INT1 Control Register INT2CR INT2 Control Register INTOSR INTO Status Register Interrupt INT1SR INT1 Status Register control INT2SR INT2 Status Register ITOCR Interrupt Timing O Control Register IT1CR Interrupt Timing 1 Control Register Care CounTer Register 16 System Query Control Register 16 support For a register list in the address order refer to Appendix 3 S TECHNICA Co LTD Chapter 5 Register Reference in MEM Mode 5 1 Chip Code Register CCR Address 32 bit address 4A0H big amp little 16 bit address
36. NM New Member and bit 15 MC Member Care of the SSR Sys tem Status Register to detect the bit transition of the MFR Member Flag Register regardless of the bit status of the MGR Member Group Register When the MFR bits change from 0 to 1 member increase and from 1 to 0 member decrease NM and MC indicate the result where 1 is true with a flag bit respectively The NM and MC bits of the SSR are updated at the starting point of status management This result enables the output of interrupt triggers For details refer to 4 5 Interrupt Trigger Generation Function Managing the NM and MC bits enables the user system program to manage the member without using the MGR as described in 4 2 3 6 Member Group Register MGR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 2 4 Detection of Global Memory Data Transition The MKY40 has a function to detect the data transition of global memory occurring when data in other CUnet stations are updated This function enables construction of a user system algorithm so that global memory is read only when data transition is detected This section describes the function to detect the data transition of global memory and its use STECHNICA CO LTD 40 User s Manual 4 2 4 4 Data Renewal Check Register for Setting Detection of Data Transition The Data Renewal Check Register DRCR is used to detect data transition
37. Setting of DOSAO to DOSAS pins 8 Bit 47 Always 0 9 Bits 48 to 55 Setting of INVO to INV7 pins 10 Bits 56 to 63 Always 0 Bits 0 to 31 where data in internal input pins in 1 above is stored go to 0 if corresponding general pur pose external I O pins 100 to 1031 are not set to input bits set to output Fig 7 2 Items 3 5 6 and 7 above are negative logic input pins Reversed positive logic setting states are embedded in the bits of the MB For example bit 35 goes to 1 when the pin is Low and 0 when the pin is High for this rea son no symbol is shown in Table 7 3 Data in an MB that is owned by the 40 in IO mode is sent to all other CUnet stations connected to a network This enables all other CUnet stations connected to a network to recognize the pin setting states as well as data in internal input pins DiO to Di31 Table 7 3 Data Structure of Owned Memory Block MB Bit15 Bit14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0 Di15 Di14 Di13 Di12 Di11 Di10 Di9 Di8 Di7 Di6 Di5 Di4 Di3 Di2 Di1 Di31 Di30 Di29 Di28 Di27 Di26 Di25 Di24 Di23 Di22 Di21 Di20 Di19 Di18 Di17 Di16 Bit47 Bit46 Bit45 Bit44 Bit43 Bit42 Bit41 Bit40 Bit 39 7 Bit36 Bit35 Bit34 Bit33 Bit32 O0 DOSAS DOSA4 DOSA3 DOSA2 DOSA1 DOSAO 0 0 Bit60 Bit59 Bit56 Bit 55 Bi
38. Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Functional description This register stores the time required for mail sending At completion of mail sending the cycle count hexadecimal that is the time required from when mail sending starts until it ends is set to the RLTO to RLT12 ResuLt Time bits The register values are kept until the next mail sending is completed STECHNICA Co LTD MKY40 User s Manual 5 24 INTerrupt 0 Control Register INTOCR Address 32 bit address 450H big amp little 16 bit address 452H big 450 little Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 0 2 4 504 ER E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RAW RW RW RW RW RW RW RW RW RAW RW RW Functional description This register enables the interrupt trigger generating function of the INTO pin When 1 is written to the bit corresponding to the interrupt source required by the user system of the interrupt sources defined in the bits of the INTOCR the function of the INTO pin is enabled Bit description ALarM ALM bit bit 0 Function This bit enables interrupt trigger occurrence when the station time during cycles reaches the time prespecified to the ITOCR Interrupt Timing 0 Control Register Data Renewal DR bit bit 1 Function This bit enables interrupt trigger occurrence when the data transition of the Memory Block MB cor
39. and type codes shown in Table 4 2 are stored in bits 8 to 12 Station Type STO to 514 3 Use the user system program to read the QCR and check that bit 6 TQ is 0 and obtain the type codes from bits 8 to 12 STO to ST4 Bit 12 1 249 9 6 5 4 3 2 4 0 sts st1 sto Pie 155 154 153 52 151 Tso R R R R R RW RW RW RW RW RW RW RW Se Type codes are stored when Write target SAs bit checking is terminated Write 1 when checking When 1 is written to both bits 7 and 6 writing is disabled When checking is terminated bit 6 returns to 0 a when checking cannot be terminated bit 6 remains 1 2 Fig 4 37 Mode Checking for Each MEM Station If the target CUnet station is not on the network bit 6 TQ does not change from 1 to 0 If the TQ bit does not return to 0 even after the elapse of several cycle times the target CUnet station is either not con nected to the network or is not in operation In this case write 0 to the TQ bit and terminate mode check ing Even if the TQ bit remains 1 continuously although the PING instruction cannot be issued it does not affect any other functions of the MK Y40 Table 4 2 Type Codes Type code set at bits 8 to 12 of QCR CUnet IC Mode Status of frame option 00H MEM Mode 01H MEM Mode 02H IO Mode 03H IO Mode MEM mode not based on current status
40. bit returns to 0 5 When all bits of the INTOSR go to 0 the INTO pin returns to hold its High level output di N O Write 1 to the bit to enable the interrupt trigger generation function Bit 15 14 13 12 11 10 9 8 INTOCR 40 PR LNG RSTR RW RW RW RW RW RW RW RW 7 6 5 4 3 2 4 0 RSTP MGNC MGNE MsF MR DR ALM RW RW RW RW RW RW RW RW When the trigger factor with the enabled status at 1 occurs the bit of the INTOSR corresponding to it changes to 1 The user system program can recognize which source caused the interrupt trigger by reading the INTOSR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTOSR JD PR RO BD LNG LOK MC MGNC MGNE MSF MR DR ALM R W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW INTO pin output When 1 is written to the bit at 1 the corresponding bit changes to 0 When any of bits 0 to 15 is 1 the INTO pin output goes Low J Fig 4 41 Interrupt Trigger Generating Function The user system program needs to specify beforehand the interrupt generation time for the interrupt factors ALM ALarM and DR Data Renewal The Interrupt Timing 0 Control Register ITOCR is used to spec ify the timing for the INTO pin Fig 4 42 Write the station time to generate the interrupt factor ALM to bits 0 to 6 ALMO to ALM6 of the ITOCR Write the
41. in the MFR Member Flag Register increases or decreases During interrupt trigger occurrence by this factor all bits of the RFR Receive Flag Register all bits of the LFR Link Flag Register and bit 12 LOK Link group OK of the SSR Sys tem Status Register freeze Link group OK LOK bit bit 10 Function This bit enables interrupt trigger occurrence by the result of Link OK During interrupt trigger occurrence by this factor all bits of the RFR all bits of the LFR and bit 12 LOK of the SSR freeze Link group No Good LNG bit bit 11 Function This bit enables interrupt trigger occurrence by the result of Link NG No Good During interrupt trigger occurrence by this factor all bits of the RFR all bits of the LFR and bit 12 LOK of the SSR freeze Break Detect BD bit bit 12 Function This bit enables interrupt trigger occurrence when break packets sent from other CUnet sta tions are received Resize Overlap RO bit bit 13 Function This bit enables interrupt trigger occurrence when a resize overlap occurs Ping Receive PR bit bit 14 Function This bit enables interrupt trigger occurrence when the PING instruction is received from other CUnet stations Jammer Detect JD bit bit 15 Function This bit enables interrupt trigger occurrence when a jammer is detected STECHNICA CO LTD 40 User s Manual 5 25 INTerrupt 1 Control Register INT1CR Address 32
42. read the SCR to check that bit 14 LF is 1 di N When setting a frame option write 1 at initialization Only 1 can be written to this bit and 0 cannot be set except when a hardware reset occurs Bit 15 14 13 BCR LFS CP OWNsy Applies to where another MEM station connected to network writes 1 to LFS bit Applies to when LFS pin of another I O station connected to network set Low Initial value O 0 Network recognizes frame option The LF bit in all CUnet stations connected to a network goes to 1 GMM LF SNF BOR TERES SCR Fig 4 40 Setting of Frame Option The CUnet that operates with the LF bit at 1 has LOF of 256 and provides longer cycle time as com pared with the case where a frame option is not used refer to 4 1 6 Cycle Time of CUnet Caution The LF bit of the SCR can be cleared only by an MK Y40 hardware reset In all CUnet sta tions to link with the MEM stations where the LF bit is 1 1 is set to the LF bit There fore when canceling the frame option for the system perform an operation to activate a hardware reset for all CUnet ICs in the system Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 5 Interrupt Trigger Generation Function The MKY40 has three output pins INTO to INT2 pin that can supply signals to the interrupt trigger pins of a user CPU The three interrupt trigger output p
43. s Manual Preface This manual describes the 40 or a kind of CUnet IC Be sure to read CUnet Introduction Guide before understanding this manual and the MKY40 Target Readers This manual is for Those who first build a CUnet Those who first use StepTechnica s various ICs to build a CUnet Prerequisites This manual assumes that you are familiar with Network technology e Semiconductor products especially microcontrollers and memory Related Manuals e CUnet Introduction Guide CUnet Technical Guide Caution To users with CUnet User s Manual released before March 2001 Some terms in this manual have been changed to conform to International Standards Some terms in this manual are different from those used on our website and in our product bro chures The brochure uses ordinary terms to help many people in various industries understand our products Please understand technical information on HLS Family and CUnet Family based on technical documents manuals E This manual has been prepared based on Standard English meeting the requirements of the International Organization for Standardization ISO and the American National Standards Institute ANSI This English manual is consistent with the Japanese document STD CU40 V2 4J Standard English is a trademark of Win Corporation ii STECHNICA CO LTD MKY40 User s Manual 40 User s M
44. the user system in this example operates at 12 Mbps the time required for the above sequences 1 to 6 to proceed is about 80 ms Such cases occur in a system with a continuously unstable power supply after power on If the user system program waits just until it enters the RUN phase it cannot get to the next step The CUnet station with the 40 should be configured to cancel a hardware reset after the power supply stabilizes immediately after power on START bit to restart the network STECHNICA CO LTD 40 User s Manual 4 2 Use of GM This section describes the use of Global Memory GM where data is shared in the CUnet The MKY40 has two memory address area for read write access to GM Global Memory Primary Window GMPW and Global Memory Secondary Window GMSW 4 2 1 Details of Owned Area GM in the MKY40 is 512 byte memory where sixty four 8 byte memory blocks MBs defined in the CUnet protocol are arranged consecutively Each MB is an area at each corresponding SA that is owned by the CUnet station Fig 4 5 y Global Memory EMO a 000H Primary Window 000H Owned area at SA 0 Owned area at SA 1 GMPW 010H Owned area at SA 2 Owned area at SA 3 020H Owned area at SA 4 Owned area at SA 5 030H Owned area at SA 6 Owned area at SA 7 200H Secondary Window 040H Owned area at SA 8 Owned area at SA 9 GMSW 050H
45. 04H DOSA 04H DOSA Don t Care Fig 7 13 Concept of System Where Multiple I O Signals Be Connected with One Network Cable S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode 7 5 1 Cycle Time Only for I O Station Final station FS values are involved in the cycle time of a CUent The initial FS value of the MK Y40 by hardware reset is 63 3FH A CUnet cannot be performed resizing by the MKY40 in IO mode The cycle time of a CUnet configured only by I O stations is a cycle time with FS 63 3FH calculated from Equations 4 1 and 4 2 described in 4 1 6 Cycle Time of CUnet Table 7 5 Table 7 5 Cycle Time with FS 63 Baud rate Cycle time 12 Mbps 2 365 ms 6 Mbps 4 730 ms 3 Mbps 9 460 ms 7 5 2 Use of IOSWAP Pin The setting of IOSO to IOS2 pins should be the same between A and B By setting the IOSWAP pin of A High and the IOSWAP pin of B Low the pins of B corresponding to input of A can be set to output and the pins of A corresponding to input of B can be set to output Fig 7 14 Va station 3 E 16 bit output 5 lt 16 bit input H Network 16 bit input p gt 16 bit output IOS 4H i IOS 4H IOSWAP Hi i IOSWAP Lo station station i Network 28 bit input p gt 4 bit output lt IOS 1H lOS 1H P 28 bit output lt 4 0 input
46. 1 to the START bit of the SCR or when a hardware reset is acti vated the SNF bit and OC bit of the SCR are cleared to 0 STECHNICA CO LTD MKY40 User s Manual 4 1 8 1 Details of SNF Station Not Found Network stop by SNF occurs when the following events in the RUN phase cause the self station to be iso lated 1 Disconnection from network network cable breaking and damage to receiver parts 2 Intentional stop of all CUnet stations other than the self station In these cases all links with other CUnet stations are unestablished The MKY40 regards the self station as being isolated if a cycle in which no link with any CUnet station is established continues for 32 times This causes network stop by SNF 4 1 8 2 Details of OC Out of Cycle Network stop by OC occurs when resizing by another CUnet station in the RUN phase prevents packet transmission of data in the owned area of the self station For example if another CUnet station is resized to when the SA of the self station is 20H the cycle is reduced and the self station follows the FS causing timing loss to send packet If another CUnet station is resized to 20H when the SA of the self sta tion is 20H and OWN is 02H the timing at packet sending of a part 21H of the owned area of the self station is also lost This causes network stop by OC Network stop by OC occurs when the MKY40 detects resizing preventing pack
47. 2 1 0 1 Public frame 210 o 1 1 0 0 bits of RFR and LFR corresponding to the owned areas of the self station are always Bt 5 4 3 2 1 0 51225 0 0 L L o o Packet with FUN Bt 5 43 2 10 The MKY40 has a monitoring function 2 8 81 described in section 4 4 9 Global Memory Packet with TR Bt 5 432 1 0 Monitor GMM Function in addition to 2 1 1 1 1 T it packet functions defined in the CUnet protocol ojojoj1jojo The SA of the self station is undefined in the Base point of status management MKY40 that operates as a GMM station by Passage of time this function This means that there is no SSS starting point of status management in the Fig 4 13 Starting Point of Status Management station Therefore in the GMM sta tion the starting point of status management is used as the lead point Station Time 0 of a cycle At the lead point of a cycle all bits of the RFR are cleared to 0 and the bits for which receiving is established change to 1 sequentially Since the GMM station is not linked with another CUnet station the status of the LFR bits has no meaning resulting in invalid data Caution When except as described in section 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation the RFR and LFR are read immediately after the starting point of status management 0 is read from
48. 3 Setting initialization before communication start to initialization 4 Responses to each phase 5 Protection against misoperation 6 Cycle time of CUnet 7 Detailed timing during cycle 8 Network stop STECHNICA Co LTD MKY40 User s Manual 4 1 1 Memory The MKY40 in MEM mode connected to the user CPU occupies 2 KB 2048 bytes OOOH 7FFH of memory area Table 4 1 shows the memory map Table 4 1 Memory Map a OOOH to 1FFH Global Memory Primary Window GMPW 200H to 3FFH Global Memory Secondary Window GMSW 400H to 4FFH Register 500H to 5FFH Mail Send Buffer MSB 600H to 6FFH Mail Receive Buffer 0 MRBO 700H to 7FFH Mail Receive Buffer 1 MRB1 The Global Memory GM of the MK Y40 is 512 bytes The GM Primary Window GMPW and GM Sec ondary Window GMSW are provided for access to GM from the user CPU GM can be accessed from either the GMPW or the GMSW Only the GMPW is usually used for access to GM The GMSW is used for access to GM when exceptions such as interrupt handling occur ards and Protection Against Data Hazards Caution Memory and register addresses indicated in the MKY40 memory map are on the 4 byte boundary If the user CPU performs byte access and word access to the MK Y40 from the 32 bit wide data bus and access from the 8 bit and 16 bit wide data bus the lower addresses may differ depending on the endian type For details ref
49. 3 Connections in MEM Mode SF ECHNICA CO LTD 22 MKY40 40 12 13 14 15 16 E CU i AO to A10 ERU DUE ST 332 17 18 19 20 21 AOO ATO 78 Network I F circuit 77 c 95 Clock input pin used as the baud 42 to 49 rate depends the external clock e 53 to 60 D8 to D31 Should be fixed Hi or Lo level 2 64 to 71 when external clock not used Connection of LED 00 to D7 510 Q approx 8 mA 5 0 V mex 92 o LCARE Paci Orange WRLL b 9 Red ZINTO 99 Interrupt input INT1 Xi Driving clock 48 MHz of MKY40 ZINT2 24 O Hardware reset of MKY40 Requiring Xi of 10 or more clocks when Low WBO WB1 ZSAO to SA5 Setting of station addresses Big endian selected High ESEL Little endian selected Low OWNO 86 to 91 Setting of OWN widths MODE to ZOWN5 uw Fig 3 13 Connection to 8 bit Wide User CPU 3 12 4 Recognition of Access The conditions when the MKY40 recognizes access from the user CPU are as follows 1 Read When both CS pin and RD pin Low For example when only the RD pin is Low read access is not started and data is not output to the data bus When the 40 recognizes read access it outputs data to the data bus with the bit width set by the level of the BWO pin and BW1 pin 2 Write When the CS pin WRHH pin WRHL pin WRLH pin and WRLL pin Low For exam ple when both CS pin and WRLL pin go Low and only the CS pin goes H
50. 59 58 57 56 55 54 53 52 51 50 49 48 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RAW RW RW Bit Functional description This register sets the bit for monitoring the MFR Member Flag Register status The bits of this reg ister correspond to the bits of the MFR When the bits of this register are set to 1 to set a member group the member status of any CUnet station can be monitored collectively STECHNICA CO LTD 40 User s Manual 5 12 Data Renewal Check Register DRCR Address 32 bit address 430H big amp little 16 bit address 432H big 4304 little 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR 14 13 12 11 10 9 8 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RAW RW RW Bit Address 32 bit address 430H big amp little 16 bit address 430H big 432H little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR DRCR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial vahie 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RAW RW RW RW RW RW RW RW RAW RW Address 32 bit address 434H big amp little 16 bit address 436H big 434H little
51. 6 Connect a clock with a frequency accuracy of 500 ppm or better 3 1 3 Checking Driving Clock When a hardware reset becomes activated the MK Y40 outputs a clock at a frequency of 1 32 of the driving clock from the TXD pin pin 79 Fig 3 1 This clock and its frequency can be used to check that whether the driving clock supplied to the MK Y40 or the external clock generated by the oscillator is correct considering aging over time temperature changes and voltage fluctuations StepTechnica recommends the oscillating frequency accuracy be within 200 ppm with a power supply of 5 0 V at room temperature PPM means parts million 1 ppm 1 1 000 000 or 0 000001 or 0 0001 A frequency of 1 32 of 48 MHz is 1 5 MHz A frequency of 1 5 MHz 200 ppm ranges from 1 49970 to 1 50030 MHz A frequency of 1 5 MHz 500 ppm ranges from 1 49925 to 1 50075 MHz A frequency of 48 MHz 200 ppm ranges from 47 9904 to 48 0096 MHz A frequency of 48 MHz 500 ppm ranges from 47 9760 to 48 0240 MHz S TECHNICA CO LTD 40 User s Manual 3 2 Hardware Reset When Low level is input to the RST ReSeT pin pin 24 the 40 is hardware reset If a period in which the Low level signal has been input is less than clock the signal is ignored to prevent malfunc tion To reset the MKY40 completely the RST pin must be kept Low for 10 or more clock while supply ing a driving clock Fig 3 3 This manual refers to
52. DR interrupt triggers by user DRFR and DR return to their original state ng y q DR ey Fig 4 18 Outline of Data Renewal Detection for Time Passage Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 2 4 4 Precautions for Use of Detection of Data Transition One cycle time in CUnet is very short Perform user processing immediately after data renewal is detected If user processing is not performed before the target memory block receives packets in the next cycle the next data transition may not be detected or the user system may not respond even if the data transition is detected When using the data renewal DR interrupt trigger generating function perform user system processing to avoid the above problem Also set the generation timing of DR interrupt trigger values set to bits 8 to 14 of the ITICR for example the lead point of a public frame or self station to avoid the above problem STECHNICA CO LTD 40 User s Manual 4 3 Use of Mail Sending Reception Function This section describes the use of the 40 mail sending reception function The CUnet protocol defines that a CUnet IC has all the mail sending reception protocols Mail sending reception based on the CUnet protocol functions between CUnet ICs in the MEM mode in the RUN phase At mail sending reception by the MKYAO errors occur only on the sending not on the receiving Accord ingly the user system program can
53. Functional description This register sets the occurrence timing of DR Data Renewal and ALM ALarM interrupt triggers in the interrupt trigger generation function of the INTO pin These interrupt triggers occur when the setting value matches the station time Bit description ALarM ALMO to ALM6 bit bits 0 to 6 Function These bits set the occurrence timing of an ALM interrupt trigger Values of 0 to 127 00H to 7FH can be written to these bits However the station time value in a CUnet must be a value stored in the FSR Final Station Register with up to 2 added When numerical values exceeding these values are written an interrupt trigger does not occur Do not write an incorrect value Data Renewal DRO to DR6 bit bits 8 to 14 Function These bits set the occurrence timing of a DR interrupt trigger Values of 0 to 127 OOH to 7FH can be written to them However the station time value in a CUnet must be a value stored in the FSR with up to 2 added When numerical values exceeding these values are written an interrupt trigger does not occur Do not write an incor rect value STECHNICA Co LTD MKY40 User s Manual 5 31 Interrupt Timing 1 Control Register IT1CR Address 32 bit address 46CH big amp little 16 bit address 46EH big 46 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 value R W R R W RW R W RW RW R
54. Global Memory Primary Window GMPW The MKY40 has a Primary Window Write Control Register PWWCR to set a write count to lock the GMPW An example of locking the GMPW primarily for write access locking during two write accesses is shown below 1 Write the write count 02H to lock the GMPW to bits 0 to 3 ACO to AC3 of the PWWCR 2 Perform the first write accress to the GMPW The PWWCR count is decremented by 1 to OIR When the PWWCR is any value other than OOH the data written by the user CPU is held in the Pri mary Window Write Temporarily PWWT in the 40 without being written to GM 3 Perform the second write access to the GMPW The count of the PWWCR is decremented to OOH and the data held in the PWWT is written collectively to GM This unlocks the GMPW The GMPW can be locked primarily during the write count set in the PWWCR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 2 2 4 Relation between Window Lock Functions Read window lock by the PWRCR and write window lock by the PWWCR are completely independent functions that do not interfere with each other The scope target address range for use of the PWRCR is one memory block on an 8 byte boundary If data is accidentally read from an address out of scope the data is output from the PWRT corresponding to the lower address The scope for use of the PWWCR is also one memory block on an 8 byte boundary If data is accidentally
55. RDY writing to this bit However writ MR1CR 5 R W ing 0 to this bit during mail recep tion is ignored and mail reception Bit where 1 is written when giving permission for mail reception When 1 is written to the RDY bit the RCV goes to 0 cannot be inhibited The RDY bit goes to 0 at completion of mail reception When the RDY bit is 1 permission for mail reception can be When the START bit of the SCR Sys cancelled by writing to this bit tem Control Register is 1 the MRBO is write protected If the Bit that changes to 1 when mail received When the RCV bit goes to 1 the RDY bit goes to 0 MRBO is read when the RDY bit of When the RCV bit is 1 can be written to the RCV bit the MROCR is 1 data is always _ OOH Fig 4 20 Permission for Mail Reception When the user system program writes 1 to bit 6 RDY of the MRICR the is permitted to receive mail The RDY bit returns to 0 upon mail reception When the RDY bit of the MRICR is 1 mail reception can be inhibited by writing 0 to this bit How ever writing 0 to this bit during mail reception is ignored and mail reception cannot be inhibited When the START bit of the SCR is 1 the MRB1 is write protected If the MRB1 is read when the RDY bit of the MRICR is 1 data is always OOH Dataset received by mail is stored in the buffer with the RDY
56. RXD TRNW TRNW TRWW TRWW Passage of time Baud rate Short pulse width of sending signal 83 33 5 166 67 5 Short pulse width of input signal 0 51 x TBPS 333 33 5 Allowable pulse 19061839 width as RZ signal 1 0 x TBPS Long pulse width of input signal 1 51 x TBPS Allowable pulse 2 0 x TBPS width as RZ signal 2 49 x TBPS 8 2 1 3 Transfer Timing when External Clock EXC Used External baud rate clock period width 4 TXI External baud rate clock High level width 1 5 x TXI External baud rate clock Low level width 1 5 x TXI EXC TEXCL STECHNICA CO LTD 40 User s Manual 8 2 2 Signal Timing Specific to MEM Mode This section shows specifications for signal timing specific to MEM mode of MKY 40 8 2 2 1 Read Write Timing TBCS TBCH ESEL TADS TADH Tcss TCSH gt CS e M RD TRD TBR lg TRO TRH gt 0 031 Read Tww TAA P4 gt WRHH WRHL WRLH WRLL gt gt Twes TwPs Tws Twy Passage of time gt Xi 48 MHz Bus change setup Bus change hold Address setup Address hold CS setup CS hold Access to access Read to out bus drive Read to data valid data output Read data hold Bus release Write signal widt
57. Read Control Register Secondary Window Write Control Register Receive Flag Register Link detection Link Flag Register Data transition Data Renewal Flag Register detection Member Member Flag Register detection Data transition detection Link Group Register Link detection Data Renewal Check Register Member Member Group Register detection System Status Register System Control Register INTOCR INTO Control Register INT1CR INT1 Control Register INT2CR INT2 Control Register INTOSR INTO Status Register INT1SR INT1 Status Register INT2SR INT2 Status Register ITOCR Interrupt Timing 0 Control Register Interrupt control IT1CR Interrupt Timing 1 Control Register New Final Station Register Query Control Register System support Care Counter Register Mail Send Control Register Mail Send Limit time Register Mail Error Status Register Mail sending Mail Send Result Register reception Mail Receive 0 Control Register Mail Receive 1 Control Register Final Station Register Basic Control Register System Chip Code Register App 5 STECHNICA CO LTD MKY40 User s Manual App 6 Revision History e 2 4 2009 Modified description of 2 in 4 2 3 6 Member Group Register MGR Changed the cacography bit 0 of DRCR in the l
58. SCR is 0 the cycle status immediately before that time is collectively updated Therefore the following can be recognized by reading the RFR 1 If there is a bit at 1 the CUnet station with the SA corresponding to that bit is operating on a net work 2 The data in the memory block of GM corresponding to the bit at 1 is updated upon receiving pack ets from target CUnet station It is possible to recognize that a resized cycle is operating when the values stored in bits 0 to 5 FSO to FS5 of the FSR are not the initial value of 63 3FH network electrical performance allows Co LTD MKY40 User s Manual 4 4 10 Frame Option for HUB The MKY40 conforms to the frame option defined in the CUnet protocol The frame option causes the Length Of Frame LOF to be 256 This option enables insertion of a HUB communications cable branching unit into the CUnet network The CUnet where a HUB communications cable branching unit is inserted into a network provides high degree of flexibility in connecting network cable resulting in expanded user systems for details refer to HUB IC User s Manual as shown below 1 Cables in network can be extended 2 Cables in network can be branched 3 Termination resistors at each CUnet station device can be reduced 4 Star topology possible 5 Easy support for optical fibers Chapter 4 Software in MEM Mode SF ECHNICA CO L
59. Signal for Notifying Output Availability of General purpose External I O Pins DOA The MKY40 in IO mode has the DOA Data Out Available pin pin 8 as a pin to output a signal for notify ing the output availability of general purpose external I O pins The DOA pin changes to a High level when STBI output update strobe and then to a Low level if STB1 does not generate within 16 cycle times Using the DOA pin enables the user system to recognize that data in pins set to output of the general pur pose external I O pins is updated within 16 cycle times when the output of the DOA pin is High Leave this pin open when not used S TECHNICA Co LTD Chapter 7 Operation and Connection in IO Mode 7 3 9 Indicating Output Availability of General purpose External I O Pins DONA The MK Y40 in IO mode has the DONA Data Out Not Available pin pin 93 available to indicate the out put availability of general purpose external I O pins The DONA pin outputs the inversion level of the DOA pin described in 7 3 8 Use of Signal for Notifying Output Availability of General purpose External Pins DOA Using the DONA pin enables the user system to indicate that data in pins set to output of the general pur pose external I O pins is updated within 16 cycle times when the output of the DONA pin is Low The DONA pin can be connected to the LED cathode pin _ to light an LED This pin is capable of driving a current
60. bit address 454H big amp little 16 bit address 456H big 454H little Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 0 2 50 2221 E Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RAW RW RW RW RW RW RW RW RW RAW RW RW Functional description This register enables the interrupt trigger generating function of the INT1 pin When 1 is written to the bit corresponding to the interrupt source required by the user system of the interrupt sources defined in the bits of the INT1CR the function of the INT1 pin is enabled Bit description ALarM ALM bit bit 0 Function This bit enables interrupt trigger occurrence when the station time during cycles reaches the time prespecified to the ITICR Interrupt Timing 1 Control Register Data Renewal DR bit bit 1 Function This bit enables interrupt trigger occurrence when the data transition of the Memory Block MB corresponding to the detection bit preset to the DRCR Data Renewal Check Register is detected at the time prespecified to the ITICR Interrupt Timing 1 Control Register When the same bit value of the INTOCR INTerrupt 0 Control Register is 1 writing 1 to this bit is protected Mail Receive MR bit to Jammer Detect JD bit bits 2 to 15 Function For these bits refer to the explanation of the same bit in 5 24 INTerrupt 0 Control Regis ter INTOCR Chapter 5 Register Reference in MEM M
61. by Bits 0 to 6 of SCR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 1 8 Network Stop The MKY40 mounted MEM station stops its network when 1 0 is intentionally written to the START bit of the SCR System Control Register 2 SNF Station Not Found No link with CUnet stations other than the self station could be estab lished 32 cycle times consecutively 3 OC Out of Cycle Resizing by other CUnet stations caused timing loss to send self station packets at cyclic time sharing By writing 0 to the START bit of the SCR even if the MKY40 is in the START CALL RUN or BREAK phase the user system program running on the user CPU connected to the MKY40 can stop the network intentionally At this network stop the RUN CALL and BRK bits of the SCR also change to 0 Network stop by in 2 and SNF in 3 occurs only when the MKY40 is in the RUN phase even while the user system program running on the user CPU connected with the MKY40 is proceeding according to any algorithm At network stop by SNF the RUN bit and START bit of the SCR change to 0 and SNF bit 13 changes to 1 At network stop by OC RUN bit and the START bit of the SCR change to 0 and OC 12 changes to When the network is stopped by SNF and OC the 40 can output interrupt triggers For details refer to 4 5 Interrupt Trigger Generation Function When the user system program writes
62. hardware reset is activated and does not need to be set every mail sending 4 Write the dataset sizes hexadecimal to bits 0 to 5 SiZe 570 to SZ5 of the MSCR the destination SAs hexadecimal to bits 8 to 13 DeSTination DSTO to DST5 and 1 to the SEND bit bit 14 The dataset sizes are given in 8 bytes as one unit For example if a dataset is 34 bytes its size is 05H If a dataset is a maximum of 256 bytes its size is 20H g Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 LMT9 LMT7 5 LMT2 LMTO R R R RW RW RW RW RW RW RW RW RW RW RW RW RW pU Write the cycle count for the time out time of mail sending The initial value is 1FFFH Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 MSCR SEND 0875 DST4 DST3 DST2 DST1 DSTO 0 o 825 524 823 522 521 szo R RW RW RW RW RW RW RW R R RW RW RW RW RW RW Write the destination SAs Write the dataset sizes given in 8 bytes as one unit Write 1 when starting mail sending This bit goes to 0 when mail sending is terminated Check that this bit is 0 before starting mail sending This bit goes to 1 if an error occurs when mail sending is terminated Fig 4 24 Operation of MSLR and MSCR Chapter 4 Software in MEM Mode TEP S TECHNICA CO LTD 5 The 40 starts mail sending immediately after 1 is written t
63. in IO mode enters the START phase and then the CALL phase After a network is stopped by 3 OC Out of Cycle the MKY40 in IO mode enters the START phase and then the BREAK phase As mentioned above in the MK Y40 in IO mode the user system needs not start or stop a network An I O station consisting of the MKY40 in IO mode is available just by being connected to a network and capable of hot swapping STECHNICA CO LTD 40 User s Manual 7 5 Configuration Using Only I O Stations A CUnet system can be configured only by I O stations without CUnet stations other than the I O station e g an MEM mode MKY40 mounted station Figs 7 12 and 7 13 In this case set the 1DOHL pin of the MKYA0 mounted on the I O station High 7 Network Network cable Network I F Network I F Network I F Network I F General purpose General purpose General purpose General purpose external I O pins external I O pins external I O pins external I O pins I O station I O station I O station I O station V Fig 7 12 CUnet Configured Only by I O Stations C 32 bit input IOS 0H SA 07H DOSA 00H IO mode IOS 0H SA 06H DOSA Don t Care IO mode 32 bit output SA 05H IOS 7H A 02H DOSA 04H DOSA 00H IO mode One network cable 32 bit output IOS 7H 0 SA
64. internal logic 0 is the pin Low level When the INVO pin is High internal logic 1 corresponding to the Io0 to Io3 pins is the pin Low level and internal logic 0 is the pin High level Table 7 1 lists the general purpose external I O pins 100 to 1031 corresponding to INVO to INV7 Table 7 1 General purpose External I O Pins Corresponding to INVO to INV7 INV Pin Name Corresponding general purpose external I O pin 100 to 103 104 10 107 108 10 1011 1012 10 1015 1016 to 1019 1020 to 1023 1024 to 1027 1028 10 1031 S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode Table 7 2 Input Output and Connection of General purpose External I O Pins When IOSWAP pin is High When IOSWAP pin is Low dis 2 Setting level Lo Lo Lo Lo Hi Hi Hi Hi Lo Lo Hi Hi Lo Lo Hi Hi Lo Hi Lo Hi Lo Hi Lo Hi Input output Input output Dixx in the table indicates input and Doxx indicates output STECHNICA CO LTD MKY40 User s Manual 7 2 4 Selection of Data Output to Internal Output Pins Select data to be output to internal output pins by the DOSAO to DOSAS pins and DOHL pin Figure 7 3 shows the concept of data sele
65. of PING Instruction PING The 40 in IO mode has the PING pin pin 7 to notify the reception of the PING instruction from other CUnet stations A PING signal is operated by intervention from other CUnet stations regardless of the status of a self I O station Usually keep the PING pin Low The PING pin changes to a High level when the PING instruction is received from other CUnet stations and then to a Low level when packets in which the PING instruction for a self I O station is not embedded are received from other CUnet stations When a hardware reset is activated the PING pin changes to a Low level in preference to the above opera tion The CUnet protocol does not specify what to use and where to connect the PING signal The PING signal is an auxiliary expanded function that helps construct user system Leave the PING pin open when not used Caution A PING signal can be generated from only the CUnet station other than I O station refer to 4 4 6 PING Instruction It cannot be generated from the MKY40 in IO mode STECHNICA CO LTD 40 User s Manual 7 3 14 Schematic Connection Diagram Figure 7 11 shows the pin setting and connection concept of the 40 in IO mode MKYAO in IO mode Differential driver receiver Network cable Half duplex Set input output inversion of 27 general purpose external I O pin Set input output of general ps purpose external I O pins General purpose e
66. of global memory Each bit of the 64 bit DRCR corresponds to each memory block constituting global memory for example bit O of the DRCR corresponds to memory block 0 bit 7 to memory block 7 and bit 63 to memory block 63 3FH Writing 1 to the DRCR bits beforehand provides the following detection results when data transition occurs in the corresponding memory blocks 1 Bit 11 DR Data Renewal flag bit of the SSR changes to 1 The user system program can recog nize the data transition of global memory by monitoring the DR flag bit 2 Interrupt triggers can be output The user system program can recognize the data transition of global memory by accepting interrupt triggers For details refer to 4 5 Interrupt Trigger Generation Function DRCR Bit 62 16 15 141312 11 019817 6 5 413 21110 Each corresponds to the bit number of the same memory block The data transition of the memory block corresponding to the bit where 1 is written is detected This flag goes to 1 when data transition occurs in the memory blocks corresponding to the bit at 1 of those in the DRCR Fig 4 17 64 bit DRCR and DRFR Writing 1 to multiple bits of the DRCR beforehand also provides the detection results when data in one or more memory blocks change In this case the MK Y40 also has a flag bit the 64 bit DRFR Data
67. of the BW1 pin and BWO pin to the data bus Continue Chapter 2 Hardware in MEM Mode TEC HNICA CO LTD Table 2 1 Pin Functions in MEM Mode Continued Input pin for hardware reset of MK Y40 Immediately after the power is turned ON or when the user resets hardware intentionally keep this pin Low for 10 or more clocks of the frequency of the Xi pin Negative Connect a signal that controls writing to DO to D7 to this pin If Negative either this pin or the CS pin goes High when both pins are Low DO to D7 data in the bus is written into the MK Y40 Output pin with no function e pun Always leave this pin open DO 07 291036 Positive Bidirectional data bus pins DO to D7 connected to user CPU This pin functions as the WRLH input pin except when both the and BWO pins are Low Connect a signal that controls writ ing to D8 to D15 to the WRLH input pin If either this pin or the CS pin goes High when both pins are Low D8 to D15 data in the d bus are got into the MKY40 This pin functions as the AO input pin of the 11 bit address bus pins to A10 connected to the user CPU when both the BW land BWO pins are Low When using the AO input pin connect the AO signal output from the user CPU to the AO input pin Pin that outputs interrupt trigger signals to user CPU INTO 41 Negative This pin outputs a Low level when an interrupt trigger occurs It is controlled by the INOC
68. output B pins DoO to Do31 8 CLRH CLRL SA0 to SA5 DOHL 1080 01082 lIOSWAP to DOSAS STB4 RST Fig 7 1 Internal Configuration of MKY40 in IO Mode S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode 7 2 Operation in IO Mode This section describes the operation of the MK Y40 in IO mode The MKY40 in IO mode Station Addresses SAs must be set to the SA0 SA5 pins by combining High or Low levels that the user inputs and owns one Memory Block MB corresponding to the SA 7 2 1 Sending of Internal Input Pin Data The MKY40 in IO mode sends data of internal input pins DiO to Di31 to Global Memory GM in other CUnet stations as follows Fig 7 1 1 The MKY40 in IO mode generates an STB2 input update strobe signal at the lead point of sending packet determined by the station address SA 2 The 40 in IO mode samples data in internal input pins DiO to Di31 with the STB2 signal The sampled data is allocated in the lower 32 bits of an owned Memory Block MB 3 The status of each setting pin is embedded in the upper 32 bits of the owned MB 4 The latest data data in 2 and 3 above in the MB owned by MK Y40 in IO mode is sent to GM in all CUnet stations in accordance with the CUnet protocol Because the STB2 signal is output to external pins the user can recognize the input sampling time 7 2 2 Data Updating of Internal Output Pins The MKY40 in IO mode
69. output Low level while stable link Negati ente with other CUnet stations is established Output pin to notify that data in 100 to 1031 pins set to output by setting of IOSO to IOS2 pins not updated within a given time If data is not updated within a given time this pin keeps output Positive High This pin is the reverse output of the DOA pin It outputs a Low level when the DOA pin High and a High level when the DOA pin is Low When a hardware reset is activated this pin 15 kept High Clock input pin that is used as baud rate depends on external clock The baud rate is 1 4 of the supply frequency up to 12 5 MHz Fix this pin at High or Low when it is not used Positive Input pin to set baud rates Positive When a hardware reset is activated the MKY40 writes the status of this pin into the internal BCR Continue STECHNICA CO LTD 40 User s Manual Table 6 1 Pin Functions in IO Mode Continued Positive Pin for oscillator connection 99 Positive Pin for connection of oscillator or generated clock 26 37 50 61 Power pins for 5 0 V supply 76 100 1 25 38 40 51 62 7210 75 Power pins connected to 0 V 3 to 6 52 63 Non functional output pins 94 Leave these output pins open Note Pins prefixed with are negative logic active Low Chapter 6 Hardware in IO Mode TEC HNICA CO LTD Table 6 2 shows the electrical ratings in IO m
70. pin at High when not used Fix the CLRL pin at High when not used time is ignored to prevent malfunction due to noise When a hardware reset is activated the output level of general purpose external I O pins 100 to 1031 is cleared in preference to the above CLRH pin and CLRL pin Fig 7 1 STECHNICA CO LTD 40 User s Manual 7 3 11 Clearing Output by Watchdog Timer As shown in Figure 7 9 if output data in internal output pins Do0 to MKYAO in IO mode Do31 is not updated within 16 cycle times when the output of the DOA pin is connected to the CLRH pin or CLRL pin a watchdog timer which forcibly set the internal output pins DoO to Do31 Low can be constituted the output level of the general purpose external I O pins 100 to Io31 set to output is specified This connection is effective for an I O station when the output level of general purpose external I O pins 100 to 1031 set to output must be specified when a link is cut off in the user system Fig 7 9 Example of Clearing Output by Watchdog Caution Figure 7 9 is a reference diagram Determine whether 16 cycle times are suitable for an I O station as the time up time of a watchdog timer 7 3 12 Indicating Input Data Sending Status of General purpose External I O Pins ZMON The MKY40 in IO mode has the MON MONitor pin pin 92 as a pin that outputs a signal indicating the status of a link esta
71. pins is changed when the MKY40 in IO mode is operating the input and output of general purpose external I O pins 100 to Io31 changes In this case the input output transition time of the general purpose external I O pins 100 to Io31 during operation varies according to the connection environments such as load capacity The output level depends on the operating state Therefore StepTechnica recommends not changing the setting of the IOSWAP pin and IOSO to 1052 pins during operation When intentionally changing the setting of the IOSWAP pin and IOSO to IOS2 pins dur ing operation take care not to bring problems such as input output transition of general purpose external I O pins and electrical collision and interference between output pins S TECHNICA CO LTD 40 User s Manual 7 3 4 Logic Setting of General purpose External I O Pins INVO to INV7 Set the logic of the 32 general purpose external I O pins 100 to 1031 by a combination of High or Low lev els to be input to the INVO to INV7 pins pins 13 to 20 Figs 7 1 7 2 7 7 Tables 7 1 7 2 Setting by jumper pin etc MKY40 Short circuit status High Logic inversion active when set short 274 Operation follows setting changes even when MKY40 operating Fig 7 7 Example of Logic Setting of General purpose External I O Pins Caution If the setting of the INVO to INV7 pins is changed when the
72. ready to send and receive packets after a network is started the MKY40 changes to the RUN phase 7 4 3 Operation in BREAK Phase The BREAK phase is the state where no access to a cycle is allowed Because packets are not sent to other CUnet stations connected to a network the setting state of and data in internal input pins 1310 to Di31 are not sent to the network When CUnet stations at station addresses matching the setting of DOSAO to DOSAS pins operate on a network pulse are output from the STB1 pin and data in internal output pins DoO to Do31 is updated In this case as compared with the standard features of an I O station the I O station operates as follows 1 The MON pin remains High 2 The DOA pin changes to a High level and the DONA pin to a Low level 3 The STBI pin outputs periodically pulses synchronized with a cycle 4 The STB2 pin remains Low does not output pulses If CUnet stations at station addresses matching the setting of DOSAO to DOSAS pins do not operate on a network or are not connected to a network pulses are not output from the STB1 pin and data in internal out put pins DoO to Do31 is not updated In this case as compared with the standard features of an I O station the I O station operates as follows 1 The MON pin remains High 2 The DOA pin remains Low and the DONA pin High 3 The STBI pin remains Low does not output pulses 4 The STB1 pin remains Low does not output pulses
73. states of these pins into the BCR register in the MK Y40 OWNDO to OWNS Output pin that outputs Low level for lighting LED while stable MON link with another CUnet station is established Continue STECHNICA CO LTD 40 User s Manual Table 2 1 Pin Functions in MEM Mode Continued Output pin that outputs Low level for lighting LED for given time LCARE Negative at LCARE Output pin that outputs Low level for lighting LED for given time MCARE Negative at MCARE Clock input pin that is used as baud rate depends on external clock Positive The baud rate is 1 4 of the supply frequency which can be up to 12 5 MHz Set this pin to High or Low when it is not used Input pins that set baud rates Positive When a hardware reset becomes active these pins write the state of this pin into the BCR register in the MK Y40 Positive Pin for oscillator connection Positive Pin for connection of oscillator or generated clock Power pins for 5 0 V supply Power pins connected to 0 V 72 10 75 Note Pins prefixed with are negative logic active Low Chapter 2 Hardware in MEM Mode TEC HNICA CO LTD Table 2 2 shows the electrical ratings in MEM mode of the MKY40 Table 2 2 Electrical Ratings in MEM Mode we Negative VDD RXD TXE TXD SA0 SA1 SA2 SA3 SA4 SA5 ololNi oalalaAlol rm w
74. station time to generate the interrupt factor DR to bits 8 to 14 DRO to DR6 of the ITOCR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD Bit 4 0 INTOSR A DR interrupt trigger occurs when An ALM interrupt trigger occurs when the the ST matches the DRO to DR6 values ST matches the ALMO to ALM6 values 4 T 4 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DR5 DR3 DR2 DRO ALMe ALMS ALM3 ALV2 ALM1 ALMO ITOCR R RW RW RW RW RW RW RW R RW RW RW RW RW RW RW Fig 4 42 DR and ALM Interrupt Trigger Generation Timing Reference When status is held in the INTOSR it is not cleared even if the corresponding enable bit of the INTOCR is canceled After a hardware reset is activated all the enable bits of the interrupt factor are initialized to 0 disabled STECHNICA CO LTD 40 User s Manual 4 5 2 Retrigger Function Multiple interrupt factors can be set in the INTO pin outputting interrupt signals If the user system pro gram uses an interrupt that enabled two or more interrupt factors the pin output may change to Low again after five clocks right after the output returns to High This is called retrigger function Fig 4 43 The retrigger function is enabled when 1 Statuses are held in the INTOSR and some of them are cleared For example 10009
75. the BCR Fig 7 4 Setting Example of Station Addresses in Mode Caution In the MKY40 in IO mode an owned area is specified for The same SA values must not be set at all CUnet ICs connected to one network The owned area must not be duplicated by its expanded setting MEM mode S TECHNICA Co LTD MKY40 User s Manual 7 3 2 Selection of Data Output to Internal Output Pins ZDOSAO to DOSAS5 DOHL Select a Memory Block MB and the upper lower bits of data to be output to internal output pins DoO to Do31 by a combination of High levels or Low levels to be input to the DOSAO to DOSAS pins pins 86 to 91 and DOHL Data Out High or Low pin pin 12 The DOSAO to DOSAS pins are negative logic input pins that are pulled up internally Select an MB using hexadecimal numbers to 0 to 63 that use a High level to be input to the DOSAO to DOSAS pins as 0 and a Low level as 1 The most significant bit is DOSAS pin 91 The upper lower bits of the MB are selected by High or Low level input to the DOHL pin Figs 7 1 7 3 Caution and 7 5 C 40 5 9 DOSA4 Because the ZDOSAO0 to DOSAS5 pins and e DOSA3 DOHL pin are negative logic input pins ON bits are treated internally as 1 DOSA2 e DOSA1 DOSAO At OFF internally 0 bits 0 to 31 Ped of the target MB are set to output
76. the MK Y40 works as follows Fig 4 22 1 Causes bit 7 RCV ReCeiVed of MRICR to change to 1 2 Causes bit 6 RDY ReaDY of MRICR to change to 0 3 Stores dataset sizes hexadecimal received by mail in bits 0 to 5 SiZe 570 to SZ5 of MRICR The dataset sizes are given in 8 bytes as one unit 4 Stores source Station Addresses SAs hexadecimal in bits 8 to 13 SRC SouRCe0 to SouRCe5 of MRICR 5 Outputs interrupt triggers if mail reception interrupt triggers enabled The user system program must read datasets from the beginning of the MRBI referring to the source SAs and dataset sizes from the MRICR 0 can be written to bit 7 RCV of the MRICR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MR1CR 0 0 5 5 5 4 SRC3 5 2 5 1 5 RCV RDY 525 544 843 522 521 520 R R R R R R R RW RW R R R R Source SAs 7 a Dataset sizes received by email using 8 bytes as one unit i Ghanges Changes from 1 to Fig 4 22 MR1CR with Dataset Stored in MRB1 Chapter 4 Software in MEM Mode SF ECHNICA CO LTD Even if the user system executes processing for the MRBO after mail reception the MKY40 can store dataset in the MRB Similarly even if the user system executes processing for the MRB after mail recep tion the MKY40 can also store dataset in the MRBO When the RCV bit of the MROCR o
77. the PWRT The read count in Reading 64 bit data ist by interrupt handling special processing is subtracted from the PWRC 3 PWRCR Interrupt gt m Y This also applies to writing at special pro 1 cessing while the user system program is T SWRC 4 using the PWWCR to write to the GMPW in PWRC 2 Y Read GMSW 4st es sa severa atches PWRC 1 Y Read GMSW 2nd This requires exclusive management for spe 4th SWRC 2 Y Pe PWRC 0 1 Read GMSW 3rd cial processing in the user system program Exclusive management may become Read GMSW 4th extremely complex depending on the user SWRC system configuration C Fig 4 11 Appropriate Use of GMPW and GMSW The MKY40 has a Global Memory Secondary Window GMSW to solve this problem simply The GMSW window locking function and the GMPW window lock are completely independent and do not interfere with each other When the above special processing accesses GM accessing the GMSW eliminates the need for exclusive management for special processing Fig 4 11 Caution Once any value other than 0 is written the PWRCR PWWCR SWRCR and SWWCR where the access count is written are write protected until the window lock is terminated The maximum numeric value that can be written to these registers is 8 If numeric values bigger than 9 are written 8 is set
78. trigger For details on freeze refer to 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation Link group OK LOK bit bit 12 Function This bit indicates the Link OK 1 is set to this bit when all bits of the LFR Link Flag Register corresponding to the bit of the LGR Link Group Register are 1 This bit is cleared to 0 at the starting point of status management However this bit freezes during output of ALM ALarM MC Member Change LOK Link group OK and LNG Link group No Good interrupt triggers For details of freeze refer to 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation Link group No Good LNG bit bit 13 Function This bit indicates the Link NG No Good 1 is set to this bit when any of the bits of the LFR corresponding to the bit of the LGR at 1 is 0 at the starting point of status management 0 is set to this bit otherwise New Member NM bit bit 14 Function This bit indicates member increase 1 is set to this bit when any of the bits of the MFR changes from 0 to 1 at the starting point of status management It is set to 0 otherwise Member Care MC bit bit 15 Function This bit indicates member decrease 1 is set to this bit when any of the bits of the MFR changes from 1 to 0 at the starting point of status management 0
79. user CPU must be designed to accept the retrigger function Caution Before using these pins refert to 4 5 Interrupt Trigger Generation Function Chapter 4 Software in MEM Mode This chapter describes the software to use the MK Y40 It also assumes that the connection between the user CPU and the 40 based on the description in Chapter 3 Connec tion in MEM Mode allows the user system program to access 40 4 1 4 2 4 3 4 4 4 5 Start and Stop Of Communication 4 3 56 Of M 4 12 Use of Mail Sending Reception Function 4 32 Detailed Operation and Management of CUnet System 4 41 Interrupt Trigger Generation Function 4 61 Chapter 4 Software in MEM Mode SF ECHNICA CO LTD Chapter 4 Software in MEM Mode This chapter describes the software to use the MKY40 It also assumes that the connection between the user CPU and the MKY40 based on the description in Chapter 3 Connection in MEM Mode allows the user system program to access the MKY40 4 1 Start and Stop of Communication This section describes the operation of the MKY40 by the user CPU to use communication in the MEM mode The basic items to operate the MKY40 in MEM mode are described in the following order 1 Memory map 2 Checking for connection of MKY40
80. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RAW RW RW RW RW RW RW RW RW RAW RW RW Address 32 bit address 43CH big amp little 16 bit address 43CH big 43EH little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RAW RW RW RW RAW RW RW RW RAW RW RW Functional description This register sets the bit for monitoring the LFR Link Flag Register status The bits of this register correspond to the bits of the LFR When the bits of this register are set to 1 to set the CUnet station whose link status is monitored the link status of any CUnet station can be monitored collectively STECHNICA CO LTD 40 User s Manual 5 10 Member Flag Register MFR Address 32 bit address 428H big amp little 16 bit address 42AH big 428 little 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Address 32 bit address 428H big amp little 16 bit address 428H big 42Ad little 15 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial v
81. 1 729 00 3 458 00 913 33 1 826 67 3 653 33 962 50 1 925 00 3 850 00 1 012 00 2 024 00 4 048 00 1 061 83 2 123 67 4 247 33 1 112 00 2 224 00 4 448 00 1 162 50 2 325 00 4 650 00 1 213 33 2 426 67 4 853 33 1 264 50 2 529 00 5 058 00 1 316 00 2 632 00 5 264 00 1 367 83 2 735 67 5 471 33 1 420 00 2 840 00 5 680 00 1 472 50 2 945 00 5 890 00 1 525 33 3 050 67 6 101 33 1 578 50 3 157 00 6 314 00 1 632 00 3 264 00 6 528 00 1 685 83 3 371 67 6 743 33 1 740 00 3 480 00 6 960 00 1 794 50 3 589 00 7 178 00 1 849 33 3 698 67 7 397 33 1 904 50 3 809 00 7 618 00 1 960 00 3 920 00 7 840 00 2 015 83 4 031 67 8 063 33 2 072 00 4 144 00 8 288 00 2 128 50 4 257 00 8 514 00 2 185 33 4 370 67 8 741 33 2 242 50 4 485 00 8 970 00 2 300 00 4 600 00 9 200 00 2 357 83 4 715 67 9 431 33 2 416 00 4 832 00 9 664 00 2 474 50 4 949 00 9 898 00 2 533 33 5 066 67 10 133 33 2 592 50 5 185 00 10 370 00 2 652 00 5 304 00 10 608 00 2 711 83 5 423 67 10 847 33 2 772 00 5 544 00 11 088 00 2 832 50 5 665 00 11 330 00 2 893 33 5 786 67 11 573 33 2 954 50 5 909 00 11 818 00 3 016 00 6 032 00 12 064 00 3 077 83 6 155 67 12 311 33 3 140 00 6 280 00 12 560 00 3 202 50 6 405 00 12 810 00 3 265 33 6 530 67 13 061 33 3 328 50 6 657 00 13 314 00 3 392 00 6 784 00 13 568 00 3 455 83 6 911 67 13 823 33 3 520 00 7 040 00 14 080 00
82. 14 4 54 4 4 7 Function to Detect Mode of Each Station esee 4 55 4 4 8 Operation of General purpose Output Ports eese 4 56 4 4 9 Global Memory Monitor GMM 4 57 4 4 10 Frame Option for HUB eire cioe oc cac aoo nnmnnn nnmnnn nnmnnn 4 58 4 4 10 1 Number of Insertable HUBS censere nennen 4 59 4 4 10 2 Setting of Frame Option 4 60 4 5 Interrupt Trigger Generation Function ecce 4 61 4 5 1 Operatiori of INTO Pin reor recreo ccc oce et te xus corto scs 4 62 4 5 2 hetrigger Function 2er eher 4 64 4 5 3 Interrupt 5 rne Ie recie eicere Rire t abiens 4 65 4 5 4 Operation of ZINT1 Pin eeeeeeere eene eren nnne nnne 4 66 4 55 Operation of ZINT2 Pin treten teurer 4 66 4 5 6 Precautions for Specifying Timing of Interrupt Trigger Generation 4 66 4 5 7 Precautions for Use of Data Renewal DR Interrupt Trigger 4 67 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation 4 67 Chapte
83. 2 Values and Baud Rates for 48 MHz Clock 5 6 Table 5 3 Type Codes at Query Completion eene 5 38 Table 6 1 Pin Functions in IO 6 4 Table 6 2 Electrical Ratings in IO Mode eene 6 7 Table 7 1 General purpose External I O Pins Corresponding to INVO to INV7 7 6 Table 7 2 Input Output and Connection of General purpose External I O Pins 7 7 Table 7 3 Data Structure of Owned Memory Block 7 9 Table 7 4 Same Connections in MEM Mode eere 7 10 Table 7 5 Cycle Time with FS 63 7 25 Table 7 6 Frame option set Cycle Time with FS 63 7 26 Table 8 1 Absolute Maximum 5 8 3 Table 8 2 Electrical Ratings ieiunii su n USE CRANE A 8 3 Table 8 3 Characteristics Measurement 8 4 xiii STECHNICA CO LTD MKY40 User s Manual Chapter 1 MKY40 Role and Features This chapter describes the role and features of the MK Y40 in CUnet 1 1 1 2 1 3 1 4 1 5 CUnet Station in MEM Mode MEM Station 1 3
84. 3 74 75 to O V of the power supply and a capacitor of at least 10 V 0 1 104 between the adjacent VDD and GND pins Leave the NC No Connection pin pin 28 open S TECHNICA CO LTD 40 User s Manual 3 1 Driving Clock This section describes the MK Y40 driving clock 3 1 1 Self generation of Driving Clock The 40 can be connected to an oscillator to self generate a driving clock In this case connect the oscillator usually a 48 MHz crystal oscillator to the Xi pin pin 99 and Xo pin pin 98 Place the oscillator and auxiliary components to be connected to the Xi pin and Xo pin near the 40 Select an appropriate value for the additional capacitance depending on the oscillator types and manufactur ers Fig 3 1 a 48 MHz Crystal oscillator Oscillator and auxiliary component MKY40 Internal TXD signal When the RST pin is Low a driving clock frequency divided by 32 is output Driving clock Role of DR Damping resistor is used to prevent the abnormal oscillation which is caused by high frequency signal With DR Fig 3 1 Self generation of Driving Clock Caution 1 The 40 oscillation frequency ranges from 40 MHz to 50 MHz If the driving clock frequency outside this range is required use the generated clock described in 3 1 2 Supplying Generated Driving clock 2 Some oscillator types may need to be inserted a dump
85. 365 ms x 4 9 46 ms efer to procedure 4 Refer to procedure 5 Yes Write to NFSR Check for correct link with other CUnet stations Check LFR MFR Refer to procedure 7 p Fig 4 28 Resizing 6 Write OOH to the NFSR to terminate resizing 44 Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 7 If there is a CUnet station stopped by OC Out of Cycle after resizing on the network the bits of the Link Flag Register LFR and Member Flag Register MFR corresponding to the CUnet station change from their pre resizing status Use the LFR MFR and function to monitor them described in 4 2 3 Quality Assurance of GM Data to check that the link with other CUnet stations required by the user system is correct If the link is incorrect refer to 4 1 8 Network Stop particularly Stop by OC to perform expanded resizing and promote entry of a stopped CUnet station When any one of the CUnet stations performs resizing the Final Station FS values of all CUnet stations connected to the network are updated to resized values In this case MEM stations other than the station that performed resizing can output interrupt triggers when the FS values are updated For details refer to 4 5 Interrupt Trigger Generation Function Caution Always write 00H to the NFSR to terminate resizing as described in procedure 6 Leave the NFSR as is when
86. 4 1 Data Renewal Check Register DRCR for Setting Detection of Data Transition 4 28 4 2 4 2 Transition Timing of DR Flag Bit and DRFR Bits from 0 to 1 4 29 4 2 4 8 Transition Timing of DR Flag Bit and DRFR Bits from 1 to Q 4 29 4 2 4 4 Precautions for Use of Detection of Data Transition 4 31 4 3 Use of Mail Sending Reception 4 32 4 3 1 Permission for Mail Reception 4 33 4 3 2 Operation for Mail Reception 4 34 4 3 3 Operation for Mail Sending and after Completion of Sending 4 36 4 3 4 Operation against Mail Sending Errors cccsssccseeeeeeseeseseeeeeeseeseseeeeeseseeseneeneeeees 4 38 4 3 5 Quality Assurance for Mail Sending Reception essere 4 39 4 3 6 User support Functions in Mail Sending Reception 4 39 4 3 7 Estimation of Mail Sending Reception 4 40 4 3 8 Precautions for Mail Sending Reception eese 4 40 vi S TECHNICA Co LTD MKY40 User s Manual 44 Detailed Operation and Ma
87. 40 in IO mode of t8mA Any LED which can be lit at a current of 8 mA or less can be connected as shown in Figure 7 8 where the 510 Q approx 8 mA 5 0V LED lights at a Low level The user system s hardware designer needs to determine the value of a current limit ing resistor R in Figure 7 8 in accordance with the LED part ratings A green LED part indicating operational sta Fig 7 8 Example of LED Connection to DONA Pin bility should be connected to the DONA pin Leave this pin open when not used 7 3 10 Clearing Output Level of General purpose External I O Pins CLRH CLRL The 40 in IO mode has the CLRH CLeaR Hi pin pin 9 and CLRL CLeaR Lo pin pin 10 as the input pins to clear the output level of general purpose external I O pins The output level of pins set to output of the upper 16 bits 1016 to 1031 of general purpose external I O pins can be cleared by inputting Low level to the CLRH pin for a time longer than 2 x TXT time Fig 7 1 The output level of pins set to output of the lower 16 bits 100 to 1015 of general purpose external I O pins can be cleared by inputting a Low level to the CLRL pin for a time longer than 2 x TXT time Fig 7 1 The level at which pins set to output of the general purpose external I O pins 100 to 1031 are cleared depends on the setting state of a multi selector Figs 7 1 and 7 2 Tables 7 1 and 7 2 Fix the CLRH
88. 425 it Md tesis uu Ma ELLE 4 37 lg 4 26 MES Ro 555 4 38 aD vr In T E 4 43 Flg4 28 12 Dax 4 44 Fig 4 29 RO Bit Ol SSR uinea duo 4 46 Fig 4 30 BD Bit of SSR usen etie eee eee ade 4 48 E 4 31 JD BitOf SSR c 4 49 Fig 4 32 Number of LCARE Occurrences of CCR eene 4 50 Fig 4 33 CP Bit of BCR emet iiec sca EIE 4 51 Fig 4 34 Number of MCARE Occurrences of 4 52 Fig 4 35 Example of Output to 4 53 Fig 4 36 Issuing PING Instruction 4 54 Fig 4 37 Mode Checking for Each MEM Station eene 4 55 Fig 4 38 General purpose Output 4 56 Fig 4 39 Number of Inserted HUBS 4 59 Fig 4 40 Setting of Frame Option eese nennen nnns 4 60 Fig 4 41 Interrupt Trigger Generating Function eene 4 62 Fig 4 42 DR and ALM Interrupt T
89. 777 The 40 always follows changes in DIP SW settings LLLA Fig 7 5 Setting Example of ZDOSAO to DOSAS Pins and DOHL Pin in Mode The setting states of the DOSAO to DOSAS pins and DOHL pin can always be changed because there are no rules such as writing the setting states internally when a hardware reset is activated Therefore take care not to allow pin setting states to change except when intentionally changing them using the user system Chapter 7 Operation and Connection in IO Mode TEP S TECHNICA CO LTD 7 3 3 Input Output Setting of General purpose External I O Pins IOSO to IOS2 IOSWAP Set the input and output of 32 general purpose external I O pins 100 1031 pins 29 to 36 42 to 49 53 to 60 64 to 71 by a combination of High or Low levels to be input to the IOSWAP pin pin 27 and IOSO to IOS2 pin 21 to 23 Figs 7 1 7 2 7 6 and Table 7 2 Caution Setting by jumper pin etc Short circuit status Low High when set open 274 Input and output change as the setting is changed even when the MKY40 is operating Fig 7 6 Input Output Setting Example of General purpose External I O Pins Usually set the IOSWAP pin to High Set it Low only when configuring a specific I O station as described in 7 5 Configuration Using Only Stations If the setting of the IOSWAP pin and IOSO to IOS2
90. 8 7 3 13 Notifying Reception of PING Instruction PING eene 7 19 7 3 14 Schematic Connection Diagram 7 20 7 4 Support for Phase 7 21 7 4 1 Operation in 7 21 7 4 2 Operation in CALL 7 22 7 4 3 Operation in BREAK 7 22 7 4 4 Support for 2011 7 23 7 4 5 Network Stop and 7 23 7 5 Configuration Using Only Stations eee 7 24 7 5 1 Cycle Time Only for I O 5 7 25 7 5 2 Use cof HOSWAP Pin eere sesetvaeesdeicecsencenedenesdeteceeaseee 7 25 7 5 3 Use of ZLFS Long Frame Select Pin for 7 26 Chapter8 Ratings 8 1 cauce a
91. A 1 are kept waiting during mail sending from the MEM station with SA 2 to the MEM station with SA 1 The CUnet has a function to control priority assigned when multiple mail sendings are started simulta neously In the CUnet if three or more mail sendings are started simultaneously priority is given to a mail sending from a smaller value Station Address SA This priority is rotated Therefore even if the CUnet station with a small value SA performs mail sending continuously mail sending from the MK Y40 with a large value SA are not kept endlessly waiting STECHNICA CO LTD 40 User s Manual 4 3 7 Estimation of Mail Sending Reception Time The estimated time required for mail sending reception of the MKY40 can be calculated using Equation 4 3 It does not include the waiting time taken when two or more CUnet stations start mail sending reception simultaneously and the resending retry time when a delay occurs in packet transmission Therefore use the time calculated using Equation 4 3 as a guide when building up a user system Equation 4 3 Byte count of dataset 7 8 3 x cycle time s In a partial solution underlined part digits after the decimal point are dropped 12 Mbps the time required for sending receiving of 250 bytes of mail can be calculated as follows 250 7 8 3 x 109 us 35 x 109 us 3 82 ms 4 3 8 Precautions for Mail Sending Reception Note the following when t
92. B Bit 63 62 555995255 3 11 10 9 8 7 6 5 4 3 2 1 0 LFR gt ae o o o 1 1 0 LGR o o olololod b Link NG ii Bit 12 of SSR 0 When all bits corresponding to LGR bits where 1 is written go to 1 Link is considered OK Bit 63 62 annunuuana 11109 8 7 5 4 3 2 1 0 LFR DUERME uS 0 LGR 0 0 2 Bit 12 of SSR 1 LNG for 13 of SSR Passage of time Timing at base point of status management 2 Fig 4 14 LFR Monitoring by LGR This result is notified to the user system by the following two methods 1 The result is indicated by the flag bit where 1 is true in bit 13 LNG Link group No Good and bit 12 LOK Link group OK of the SSR Except for the special case described in 4 5 8 Register Freezing in Synchronization with Inter rupt Trigger Generation the LOK flag bit is cleared to 0 at the starting point of status manage ment The LNG flag bit samples the result in the immediately preceding cycle at the starting point of status management and holds the sampled result for the next one cycle Fig 4 14 Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 2 The 40 can output interrupt triggers The user system program
93. B set to the DRCR Data Renewal Check Register Bit 0 of the DRFR corresponds to MBO bit 1 to MB1 and bit 63 to MB63 The bit corresponding to the MB where data transition is detected keeps 1 For details of the timing of bit transition of this register refer to 4 2 4 Detection of Global Memory Data Transition The bit status of this register freezes during the output of the DR Data Renewal interrupt trigger For details of freezing refer to 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation The function of this register is also enabled when the MK Y40 operates as a GMM Global Memory Monitor station S TECHNICA CO LTD 40 User s Manual 5 14 Primary Window Read Control Register PWRCR Address 32 bit address 400H big amp little 16 bit address 402H big 400 little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R RW RW RW Functional description This register executes the read window lock function that freezes a GMPW Global Memory Primary Window primarily until a specified number of read accesses are completed when reading data from Global Memory GM via the GMPW A hexadecimal read access count of less than 08H can be written to the to ACO Access Count bits of this register When a value of more than 08H is written to this register 8 is forcibly set The values stored in this regis
94. CARE pin described in 4 4 5 1 LCARE Signal Output are also shortened Fig 4 33 In this case LED lighting cannot be seen but specifications to output Low pulses each time MCARE occurs are suitable for use in counting the number of MCARE occurrences with the user system s circuit Chapter 4 Software in MEM Mode Caution TEP S TECHNICA CO LTD MCARE occurs and Low pulses are output from the MCARE pin even when resizing described in 4 4 2 Resizing of Cycle Time disables a link with the CUnet station with which the link has been established 4 4 5 3 MON Signal Output If a link is established consecutively more than three times the MKY40 considers the link with other sta tions to be stable This status is controlled by the Member Flag Register MFR described in 4 2 3 5 Mem ber Flag Register MFR The MKY40 outputs a Low level to the MON pin when 1 is stored in any of the bits corresponding to CUnet stations other than the self station of the MFR and outputs a High level in any other status Fig 4 35 The stable status of a link with other CUnet stations can be checked visually by connecting LED indicator to the MON pin so that it can go ON when a Low level is output For details of connecting the LED indicator refer to 3 8 Connecting LED Indication Pins hui Q9 8 7 6 5 4 3 2 1 0 61 minii 1 0 1 1 1 1 1 0 1
95. CHNICA CO LTD Chapter 5 Register Reference in MEM Mode T 5 7 Receive Flag Register RFR Address 32 bit address 410H big amp little 16 bit address 412H big 410 little 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R Address 32 bit address 410H big amp little 16 bit address 410H big 412d little Bit R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W R R R R R R R R R R R R R R R R Address 32 bit address 414H big amp little 16 bit address 416H big 414d little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 RW R R R R R R R R R R R R R R R R Address 32 bit address 414H big amp little 16 bit address 414H big 416H little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR RFR 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R W R R R R R R R R R R R R R R R R Functional description This register stores the individual receiving status that guarantees data in individual memory blo
96. EXist The mail receive buffer at the destination MEM station is not in the RDY state NORDY distination NOt ReaDY Fig 4 26 MESR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 3 5 Quality Assurance for Mail Sending Reception If trouble with sending packet by mail occurs due to environmental problems including external noise the 40 with the CUnet protocol is recovered by resending retry Resending is executed three times If packets cannot be sent by mail even after resending is executed three times processing is terminated with an NOEX destination NOt EXist error This prevents the mail or the datasets becoming lost in transit Datasets sent received by mail are quality guaranteed as with packet that shares memory data This prevents data errors that are likely to occur 4 3 6 User support Functions in Mail Sending Reception In a CUnet two CUnet stations can send receive mail simultaneously For example mail from the MEM station with SA 1 to the MEM station with SA 2 and mail from the MEM station with SA 3 to the MEM station with SA 4 can be sent received simultaneously However if mail sending from the MEM station with SA 3 to the MEM station with SA 1 are started immediately after mail sending from the MEM station with SA 2 to the MEM station with SA 1 were started since the destination is same the mail sending from the MEM station with SA 3 to the MEM station with S
97. Features of MEM 1 4 Station in IO Mode I O Station 1 5 Features of IO 1 6 Mode Selection 1 6 Chapter 1 MKY40 Role and Features TEC HNICA CO LTD Chapter 1 MKY40 Role and Features This chapter describes the role and features of the MK Y40 in the CUnet The MKY40 is a CUnet dedicated IC with the CUnet protocol CUnet IC based on full hard wire logic packaged in a 100 pin TQFP using CMOS technology It has two modes MEM mode and IO mode A station in MEM mode is called a MEM station and a station in IO mode is called an T O station These two stations are collectively called a CUnet station In MEM mode the CUnet station can also be used as a station operated by a global memory data monitoring GMM function refer to 4 4 9 Global Memory Monitor GMM Function 1 1 CUnet Station in MEM Mode MEM Station CUnet consists of multiple user equipment with a CUnet IC and a network connecting these equipment The 40 a CUnet IC in MEM mode has a bus interface BUS I F and a network interface network I F C
98. Fig 3 10 Example of LED Display Pin Connection ing medium level warning should be connected to the LCARE pin The red LED indicating a clear warn ing should be connected to the MCARE pin For details when the MON LCARE MCARE pins go Low refer to 4 4 5 Controling and Monitoring Network Quality Leave the MON LCARE and MCARE pins open when they are not used Caution If bit 14 of the BCR Basic Control Register is set to 1 the width of Low levels output from the LCARE and MCARE pins is too short for the LED lighting to follow and the user cannot find the LED is lit For details of setting bit 14 of the BCR to 1 refer to 4 4 5 Controling and Monitoring Network Quality STECHNICA CO LTD MKY40 User s Manual 3 9 Connection of Timing Notification Signal STB Pin The MKY40 has output pin STB STroBe pin 8 to notify the start timing of a cycle The STB pin is usually kept High and outputs a pulse that goes Low for 2 x TBPS time at the start timing of a cycle Using the timing at which the output of this pin changes to Low allows the user to recognize the timing synchroni zation common to all CUnet stations connected to a network The synchronous performance of a CUnet can be calculated using equation 3 1 Leave this pin open when it is not used Equation 3 1 2 x TBPS cycle time x clock accuracy signal propagation delay or less For example the synchronous perf
99. Fig 7 10 Example of LED Connection to MON Pin eee 7 18 Fig 7 11 Pin Setting and Connection Concept of MKY40 in IO Mode 7 20 Fig 7 12 CUnet Configured Only by I O Stations eere 7 24 Fig 7 13 Concept of System Where Multiple I O Signals Can Be Connected with One Network 7 24 Fig 7 14 Concept of Use of Pin eene 7 25 xij 40 User s Manual STE ENE Tables Table 2 1 Pin Functions in MEM Mode 2 4 Table 2 2 Electrical Ratings in MEM Mode eere 2 7 Table 3 1 Network Cable 3 10 Table 4 1 Meniory 4 4 Table4 2 nee eno qe onte eere See resina 4 55 Table 4 3 Interrupt Factors eoi iere cla rosas suae eonun aid spe Cer raa Susa pu cia n nannan 4 65 Table 4 4 Frozen 4 67 Table 5 1 Register Dist uc cari narius d dt ec EE 5 4 Table 5
100. Flag Register RFR and Link Flag Register LFR The RFR and LFR are 64 bit registers Fig 4 12 Since a CUnet can be constructed using up to 64 CUnet stations bit 0 in each register corresponds to the Sta tion Address SA 0 and Memory Block MB 0 bit 1 to SA 1 and MB 1 and bit 63 to SA 63 and MB 63 The user system program reads the RFR and LFR to recognize bits set to 1 and thereby determining the assured status of shared memory data in GM 1 When recognizing whether data in MBs other than the owned area is the latest data copied from other CUnet stations read the RFR containing individual flag bit values guaranteeing that data in individ ual MBs is fetched by the latest cycle 2 When recognizing whether there is any CUnet station incapable of copying data in the owned areas read the LFR containing individual flag bit values guaranteeing that data in individual MBs is fetched by the latest cycle and that data in the MB of the self station is copied correctly to individual CUnet stations E RFR Bit 63 62 16115114113112111110 9 8 16 15 14 13 12 14 10 N 6 51413 21110 The bit beyond the owned area of self station is cleared to 0 at lead point of self ST start point of status management The bit of the target CUnet station receiving the packet goes to 1 sequentially up to the starting point of the next status mana
101. Good All bits of DRFR Bit 11 DR of SSR DR Data Renewal Caution Ifthe Member Change MC interrupt occurs the Member Flag Register MFR is not fro zen The MFR is updated at the starting point of status management so the processing started by the MC interrupt should be cared so as not to refer to the MFR going over the next starting point of status management STECHNICA CO LTD MKY40 User s Manual Chapter 5 Register Reference in MEM Mode This chapter provides functional references for registers of the MK Y40 in MEM mode Chapter 5 Register Reference in MEM Mode ST CO LTD Chapter 5 Register Reference in MEM Mode This chapter provides functional references for registers of the MKY40 in MEM mode Table 5 1 The description in this chapter conforms to the following format 1 Register addresses are represented by starting addresses common to big endian and little endian of 32 bit access and starting addresses given for big endian and little endian individually of 16 bit access 2 Data bits are represented by 16 bit access When referencing this chapter consider the following points 1 The MKY40 in MEM mode has a 16 bit wide register and a 64 bit wide register 2 At 32 bit read access to the 16 bit wide register 0 can be all read from upper 16 bits 3 At 32 bit write access to the 16 bit wide register writing to upper 16 bits is ign
102. Group Not Collect MGNC Ordered ee d 63 62 61 111098765432 10 5 MFR 0 0 0 011101111 11111111111111 MGR 0 0 0 Disordered x 63 62 61 1409 8 76 5 4 32 10 MFR 0 0 0 011 1011111111 011111111 1 MGR 0 010 101111 11111111111111 Fig 4 16 MFR Monitoring by MGR and Bit Status of SSR As described above when the user system program presets the MGR bits for monitoring the MFR status the user system can monitor the status collectively For example when monitoring the lack of a CUnet station periodically read the SSR System Status Sys tem at the appropriate time while the user system program is running If bit 4 Member Group Not Equal of the SSR is 0 the CUnet station corresponding to the bit where 1 was written beforehand to the MGR is not separated from the member Stations other than the CUnet station corresponding to the bit where 1 was written beforehand to the MGR do not exist as a mem ber When permitting their existence ensure that bit 5 MGNC Member Group Not Collect of the SSR is 0 When monitoring the above status by the accepting interrupt triggers method the user system program does not need to periodically read the SSR S TECHNICA CO LTD 40 User s Manual 4 2 3 7 Detection of Member Increase and Decrease The MKY40 has a function bit 14
103. JD bit goes to 0 when 1 is written to it Fig 4 31 Bit of SSR Bit 9 JD of the SSR can be cleared by writing 1 It changes to 1 again when a jammer is detected sub sequently When bit 9 JD of the SSR goes to 1 the MK Y40 can output interrupt triggers For details refert to 4 5 Interrupt Trigger Generation Function The user system program that recognized the jammer by reading the SSR to check that the JD bit is 1 warns the user system operator or manager to remove the jammer or perform failure recovery Even if no CUnet stations have a hardware failure a slight difference in the start timing may occasionally cause a jammer to be detected at network start Therefore if the JD bit is 1 clear the bit and check for a jammer at network start and then issue a warning to an operator or manager operator or manager or failure recovery must be performed S TECHNICA CO LTD 40 User s Manual 445 Controling and Monitoring Network Quality The MKY40 has two concepts LCARE Link CARE and MCARE Member CARE that can control net work quality It also has the MON MONitor pin that can monitor the state that a link with other CUnet stations is stable In understanding this section refer to 4 2 3 Quality Assurance of GM Data 4 4 5 1 LCARE Signal Output A dead link defined in the CUnet protocol does not occur in a stable CUnet operating enviro
104. LCCO to LCC7 of the CCR When clearing the number of LCARE occurrences by the user system program write 1 to bit O of the CCR Fig 4 32 Number of LCARE Occurrences of CCR A Low pulse output from the LCARE pin is generated by a retriggerable one shot multivibrator with a minimum time of 2096896 x TXT Therefore if a new dead link occurs within this time the Low pulse width gets longer If the driving clock of the MKY40 is 48 MHz the minimum time of the Low pulse is about 43 ms and the lit LED can be seen Chapter 4 Software in MEM Mode SF ECHNICA CO LTD Low pulses output from the LCARE pin can be changed to short pulses of 5 to 7 TBPS time When changing Low pulses to short in Step 2 3 described in 4 1 3 Initialization and Start up of Communi cation write 1 to bit 14 CP Care Pulse of the Basic Control Register BCR Low pulses output from the MCARE pin described in 4 4 5 2 MCARE Signal Output are also shortened Fig 4 33 In this case the lit LED cannot be seen but specifications to Bit 15 14 13 urs ce owns 5 RW RW RW tem circuit output Low pulses each time LCARE occurs are useful in counting the number of LCARE occurrences by the user sys BCR When 1 is written pulses from the LCARE and MCARE pins are shortened Fig 4 33 CP Bit of BCR Caution LCARE occurs and Low pulses are output from the LCARE pin even
105. LFR LFR LFR LFR LFR LFR LFR LFR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R W R R R R R R R R R R R R R R R R Address 32 bit address 41CH big amp little 16 bit address 41 big 41 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 R W R R R R R R R R R R R R R R R R Address 32 bit address 41CH big amp little 16 bit address 41CH big 41 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR LFR 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 R W R R R R R R R R R R R R R R R R Functional description This register stores the individual flags that guarantees data in individual memory blocks MBs con stituting Global Memory GM are written by the latest cycle and data in MBs of a self station is cop ied to each CUnet station Bit O corresponds to the station address SA 0 and MBO bit 1 to SA1 and MBI and bit 63 to SA63 and MB63 The register bit corresponding to the self station owned area is always 1 except when the GMM Global Memory Monitor bit bit 15 of the SCR System Control Register is 1 when this device operates as a GMM station So as an initial value of this register the register bit corresponding to the self station owned area is 1 and the bit other than that is 0 F
106. MEM station owns 32 memory blocks in the CUnet with two MEM stations GM can be used as dual port RAM owning 256 bytes 4 Standard baud rates of 12 6 and 3 Mbps 5 Can generate various interrupts including ones to detect data transition in GM 6 Can send a dataset of up to 256 bytes 7 Can be connected to 8 16 and 32 bit user bus 8 The CUnet protocol of the MKY40 guarantees that data can be transferred between CUnet stations without error or garbage Chapter 1 MKY40 Role and Features TEC HNICA CO LTD 1 3 Station in IO Mode I O Station The MKY40 can be used as a CUnet I O IC Fig 1 3 C N The MKY40 CUnet IC set to IO mode can connect its general purpose Network external I O pin signals I O signals directly to GM by connecting a net work I F to the network Network I F 10 mode The CUnet system shown in Figure 1 4 is a CUnet that connects two MEM General purpose t stations in ME mode with a user CPU and two T O stations in IO mode external I O pins signal circuit via a network In this setup all user CPUs can read the state of input ports used in I O station of the T O stations from GM User CPUs can also set the state of output ports of the I O stations Fig 1 3 I O Station Network cable Network Network I F Network I F Network I F Network I F MEM mode IO mode IO mode General purpose external I O p
107. MKY40 in IO mode is operat ing the logic of general purpose external I O pins 100 to 1031 changes In this case the logic transition time of the general purpose external I O pins 100 to 1031 during operation varies according to the connection environments such as load capacity The output level depends on the operating state Therefore StepTechnica recommends not changing the set ting of the INVO to INV7 pins during operation When intentionally changing the setting of the INVO to INV7 pins during operation take care not to bring problems S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode 7 3 5 Setting of Frame Option LFS The MKY40 in IO mode has the LFS Long Frame Select pin pin 11 that sets a frame option Usually fix the LFS pin at High Use the LFS pin in the user system constituting a CUnet only by I O stations described in 7 5 3 Use of LFS Long Frame Select Pin for HUB The MKY40 conforms to a frame option defined in the CUnet protocol The frame option is the option function with a length of frame LOF of 256 The frame option enables the insertion of up to two HUBs network cable branching units into a CUnet network A CUnet network into which HUBs are inserted pro vides high degree of flexibility in connecting network and longer network cables for many applicable appli cations refer to User s Manual for HUB IC MKY02 When setting the frame opt
108. N instruction is issued to CUnet stations at the station addresses set to the TSO to TS5 bits This bit is reset to 0 after completion of issuing Writing of data such that both this bit and TQ bit go to 1 is protected station TYPe TYPO to TYP4 bit bits 8 to 12 Function These bits set the type codes in Table 5 3 when the function query to detect other CUnet sta tion modes is completed Table 5 3 Type Codes at Query Completion Type codes set to bits 8 to 12 CUnet IC mode Status of frame option 00H MEM mode 01H MEM mode 02H IO mode 03H IO mode Unsubstantial MEM mode due 04H to owned expansion 05H to 1FH Reserved Chapter 6 Hardware in IO Mode This chapter describes the hardware such as pin assignment pin functions and input out put circuit types in the MK Y40 IO mode Chapter 6 Hardware in Mode TEP S TECHNICA CO LTD Chapter 6 Hardware in IO Mode This chapter describes the hardware such as pin assignment pin functions and input output circuit types in the MK Y40 IO mode Figure 6 1 shows the pin assignment in the MK Y40 IO mode 40 100 pins TQFP 2222
109. Owned area at SA 10 Owned area at SA 11 Owned area at SA 12 C Owned area at SA 47 180H Owned area at SA 48 Owned area at SA 49 190H Owned area at SA 50 Owned area at SA 51 1A0H Owned area at SA 52 Owned area at SA 53 1BOH Owned area at SA 54 Owned area at SA 55 1COH Owned area at SA 56 Owned area at SA 57 1D0H Owned area at SA 58 Owned area at SA 59 1E0H Owned area at SA 60 Owned area at SA 61 1 Owned area at SA 62 Owned area at SA 63 Fig 4 5 Global Memory GM The MKY40 can expand an owned area by the setting of OWN widths defined in Increased Practicality in the CUnet protocol The owned area depends on the SA and OWN width stored in the BCR Basic Control Register The MB with an OWN width corresponding to an SA is an owned area Fig 4 6 For example with SA 6 and OWN 2 the MK Y40 owns 16 byte area between MB 6 and 7 GMPW and 03 Chapter 4 Software in MEM Mode SF ECHNICA CO LTD The owned area in the CUnet is area to send copy data to other CUnet stations In the MKY40 the owned area can be always written but GM other than the owned area is write protected when the START bit of the SCR is 1 When using GM in a CUnet a write enable area and a read only area are definitely separated and simulta neous write and overwrite to the same address does not occur a Setting example 0H 7H 8H FH of each MEM station 000H
110. R and INTOSR registers in the MK Y40 D8 to D15 42 to 49 Positive Bidirectional data bus pins D8 to D15 connected to user CPU Pin that outputs interrupt trigger signals to user CPU INT1 52 Negative This pin outputs a Low level when an interrupt trigger occurs It is controlled by the INICR and INTISR registers in the MK Y40 D16 to D23 53 to 60 Positive Bidirectional data bus pins D16 to D23 connected to user CPU Pin that outputs interrupt trigger signals to user CPU INT2 Negative This pin outputs a Low level when an interrupt trigger occurs It is controlled by the IN2CR and INT2SR registers in the MK Y40 D24 to D31 64 to 71 Positive Bidirectional data bus pins D24 to D31 connected to user CPU Input pin that inputs packets RXD 77 Positi 2 US Connect this pin to the receiver output pin Output pin that goes High during packet output TXE 7 Positi is pi j j 8 Connect this pin to the enable input pin of the driver Output pin that outputs packets TXD 7 Positi is pi ive i i 9 Connect this pin to the drive input pin of the driver Input pins that set station addresses SAs 80 to 85 Negative When a hardware reset becomes active these pins write the inverted states of these pins into the BCR register in the MK Y40 SA0 to SA5 Input pins that set OWN width 86 to 91 Negative When a hardware reset becomes active these pins write the inverted
111. Renewal Flag Register indicating in which memory block the data transition occurred The bit arrangement of the DRFR corresponds to each memory block Fig 4 17 Of the DRFR bits the bit corresponding to the mem ory block where data changed is set to 1 The user system program can recognize the memory block where data changed by recognizing the DRFR flag bit Caution Bit 11 DR of the SSR and DRFR function only when 1 is set to the DRCR The func tion to detect data transition does not operate for the memory block owned by the self sta tion even if 1 is set to the target DRCR Chapter 4 Software in MEM Mode TEP S TECHNICA CO LTD 4 2 4 2 Transition Timing of DR Flag Bit and DRFR Bits from 0 to 1 Bit 11 DR Data Renewal of the SSR and each bit of the DRFR transits from 0 to 1 when packets are received from other CUnet stations and data in the global memory is updated for data copying based on sharing of received memory data Fig 4 18 4 2 4 3 Transition Timing of DR Flag Bit and DRFR Bits from 1 to 0 The timing of bit 11 DR of the SSR and each bit of the DRFR changing from 1 to 0 depends on the MKY40 usage environment as follows Fig 4 18 1 Bit 11 DR and DRER bits change from 1 to 0 at the lead point of the time for writing to bits 8 to 2 3 wm 14 of the ITOCR time for writing to bits 8 to 14 of the INTICR when
112. Resize Overlap of the SSR to 1 and warns the user system program about a resize overlap If a resize overlap occurs write OOH to the di NFSR and terminate resizing The occurrence SSR LUN 5 so 5 RW RW RW of the resize overlap reveals that the algorithm of the user system itself is contradictory Opti p mize the system algorithm The warning about This bit goes to 1 when a resize overlap occurs the resize overlap RO bit of the SSR is 1 can The RO bit goes to 0 when 1 is written to it be cleared to 0 when the user system program writes 1 to the same bit RO bit of SSR Fig Fig 4 29 RO Bit of SSR 4 29 When a resize overlap occurs the MKYA0O can output interrupt triggers For details refer to 4 5 Interrupt Trigger Generation Function Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 4 2 4 Caution when RO Occurs an MEM station with a smaller value Station Address SA than that of a self station terminates resizing OOH is written to the NFSR when a resize overlap occurs values other than OOH are stored in the NFSR of the self station the self station immediately performs resizing and the Final Station FS value is resized to the value that the self station wrote to the NFSR If OOH is written to the NFSR to stop resizing before the MEM station terminates resizing it is resized to the FS value by t
113. TD 4 4 10 1 Number of Insertable HUBs In a CUnet network to which the frame option is set up to two HUBs communications cable branching units can be inserted Fig 4 39 When two HUBs are inserted CUnet IC CUnet station CUnet station CUnet IC CUnet station CUnet station N 2 CUnet station CUnet station CUnet IC When three HUBs are inserted amp CUnet IC CUnet IC CUnet IC CUnet station CUnet station CUnet station CUnet station Fig 4 39 Number of Inserted HUBs S TECHNICA CO LTD 40 User s Manual 4 4 10 2 Setting of Frame Option To set the frame option write 1 to bit 15 LFS Long Frame Select of the Basic Control Register BCR in Step 2 3 of 4 1 3 Initialization and Start up of Communication Fig 4 40 The frame option is set to all CUnet stations in the mutual link process with other CUnet stations after net work start It is also set automatically in the CUnet station which is later connected turned on to the net work operating with the frame option set Therefore by writing 1 to the LFS bit of the BCR one or multiple CUnet station s connected to a network changes to a CUnet which operates in a cycle with a Length Of Frame LOF of 256 In the MK Y40 to which the frame option is completely set bit 14 LF Long Frame of the SCR is set to 1 To check the setting of the frame option by the user system program
114. W R R W RW RW RW RW RW Functional description This register sets the occurrence timing of DR and ALM interrupt triggers in the interrupt trigger gen eration function of the INT1 pin These interrupt triggers occur when the setting value matches the station time Bit description ALarM ALMO to ALM6 bit bits 0 to 6 and Data Renewal DRO to DR6 bit bits 8 to 14 Function For these bits refer to the explanation of the same bit in 5 30 Interrupt Timing 0 Control Register ITOCR Chapter 5 Register Reference in MEM Mode ST CO LTD 5 32 Care CounTer Register CCTR Address 32 bit address 478H big amp little 16 bit address 47AH big 478 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R W R R R R R R R R W Functional description This register stores the occurrence count of LCARE and MCARE signals Bit description Link Care Counter LCCO to LCC7 bit bits 0 to 7 Function The occurrence count of the LCARE signal is stored in these bits The occurrence count hexadecimal is counted by these bits When the occurrence count is counted up to FFR the value is kept The count values of these bits can be cleared to OOH by writing 1 to the LCCO bit bit 0 Member Care Counter MCCO to MCC7 bit bits 8 to15 Function The occurrence count of the MCARE signal is st
115. Y40 User s Manual 7 2 3 Operation of General purpose External I O Pins 100 to 1031 and Multi selector The general purpose external I O pins 100 to 1031 are connected to 32 bit internal input pins Di0 to Di31 or 32 bit internal output pin DoO to Do31 using a multi selector Fig 7 1 The multi selector functions by the combination of High or Low levels that the user inputs to the IOSO to IOS2 pins the IOSWAP pin and INVO to INV7 pins Figure 7 2 shows the internal configuration of a selector corresponding to one Io pin The multi selector has 32 selectors with the configuration shown in Figure 7 2 7 vst ng bytos0 te 1052 The lo pin is set to input at High lIOSWAP gt Internal output pins DoO to Do31 INVO to INV7 E 2 L 5 100 to 1031 pins Internal input pins DiO 0131 V Fig 7 2 Internal Configuration of Multi selector for One lo Pin IOSO to IOS2 are input pins that select general purpose external I O pins 100 to 1031 as input and out put IOSWAP is an input pin that reverses input and output determined by IOSO to IOS2 Table 7 2 indi cates the input and output selection by IOSO to IOS2 and IOS WAP INVO to INV7 are input pins that set the relationship between internal logic and the logic of general purpose external I O pin 100 to 1031 levels For example when the INVO pin is Low internal logic 1 correspond ing to the 100 to 103 pins is the pin High level and
116. al ratings of the MKY40 Table 8 2 Electrical Ratings Parameter Operating power supply voltage Conditions 25 C Vss 0 V Operating current Vi VDD or Vss Xi 50 MHz output open External input frequency Input to Xi pin Oscillation operating frequency Xi Xo oscillator connecting Input pin capacitance Output pin capacitance I O pin capacitance VDD Vi 0 V f21MHz TA 25 C Rise fall time of input signal Rise fall time of input signal Schmidt trigger input S TECHNICA Co LTD 8 2 AC Characteristics MKY40 User s Manual Table 8 3 lists the measurement conditions for AC characteristics of the MK Y40 Table 8 3 AC Characteristics Measurement Conditions Output load capacitance Power supply voltage Temperature 8 2 1 Signal Timing Common to Each Mode This section shows specifications for signal timing common to MEM mode and IO mode 8 2 1 1 Clock and Reset Timing RST Xi Passage of time gt TXI Xi 7 TXIL TRST Xi ZRST 45V VDD Clock period width Clock High level width Clock Low level width Reset enable Low level width 10 x TXI ECHNICA CO LTD Chapter 8 Ratings T 8 2 1 2 Baud Rate Timing TXD RXD TXE RZ 1 RZ RZ 0 RZ 0 RZ 1 TXD 5 5 RZ 1 RZ RZ 0 RZ 0 RZ 1
117. alue 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Address 32 bit address 42CH big amp little 16 bit address 42EH big 42 little 15 47 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Address 32 bit address 42CH big amp little 16 bit address 42CH big 42 little 15 63 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR MFR 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R R R R R Bit Functional description This register stores the individual member status in which 1 is set when Link Established is rec ognized consecutively three times and 0 is set when Link unestablished is recognized consecu tively three times Bit 0 corresponds to the station address SA 0 bit 1 to SAT and bit 63 to SA63 and MB63 The bit of this register is updated at the lead point of Station Time ST matching the SA of a self sta tion at the starting point of status management All the bits of this register keep 0 when the START bit of the SCR System Control Register is 0 and the GMM bit of the SCR is 1 5 ECHNICA CO LTD Chapter 5 Regis
118. ame option is set 24 7 Hardware reset RST OPEN J gt Leave unused output pins open 99 Crystal Oscillator VoD OUT 48 MHz standard 0 98 Insert capacitors multilayer ceramic max 50 MHz GND around 104 between power pins Precision 500 ppm less than 0 05 777 List of IO pin definitions IOSWAP Hi IOSWAP Lo Input and output pins Input and output pins Input pin Output pin Input Output pin lo 0 to 31 Unavailable 32 0 Unavailable lo 0 to 31 0 32 0 to 27 1028 to 31 28 4 i 1028 to 31 lo 0 to 27 4 28 0 to 23 1024 to 31 248 i 1024 to 31 lo 0 to 23 8 24 lo Oto 19 1020 to 31 i i 1020 to 31 loOto 19 lo 0 to 15 lo16 to 31 i lo16 to 31 lo 0 to 15 loOto 11 1012 to 31 i i 10121031 loOto 11 lo 0 to 7 lo 8 to 31 i i lo 8 to 31 lo 0 to 7 Unavailable lo 0 to 31 i i i lo 0 to 31 Unavailable The IOSWAP input output inversion setting pins are usually used at a High level in a system consisting of the MKY40 in IO mode alone the IOSWAP pins may be used at a Low level Fig 7 11 Pin Setting and Connection Concept of MKY40 in IO Mode S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode 7 4 Support for Phase Transition Like the MK Y40 in MEM mode the MK Y40 in IO mode has START CALL RUN and BREAK phases In the MKY40 in MEM mode a network must be started by the user system program However in
119. and MGNC flag bits are updated at the starting point of status management 2 The MK Y40 can output interrupt triggers The 40 if a given interrupt has been set for it outputs interrupt triggers when bit 4 MGNE or bit 5 MGNC of SSR mentioned in above 1 newly changes from 0 to 1 For this interrupt set ting refer to 4 5 Interrupt Trigger Generation Function Chapter 4 Software in MEM Mode SF ECHNICA CO LTD Flag representing mismatch X Matched Bit 4 of SSR 4 Member Group Not Equal 63 62 61 11109 876543210 MFR 0 010 0 10 10111111111111111111 0 63 62 61 11109 8 76 5 4 32 10 MGR 0 0 0 010 10111111111111111111 Mismatched J 63 62 61 1109876543210 i MFR 0 0 0 0 10 101111111111 0101111 1 H MGR 0 0 0 0 1010111111111111111111 Mismatched f 63 62 61 1109876543210 4 MFR 01010 01110111111 111 1111111 1 H MGR 0 0 0 0 1010111111111111111111 Flag representing disorder Bit 5 of SSR Member
120. ano yr vadur qa wa Cur n RR a dons c 8 3 8 2 AC Character Stes Mec 8 4 8 2 1 Signal Timing Common to Each Mode esee nnns 8 4 8 2 1 1 Clock and Reset Timing ZRST Xi 8 4 8 2 1 2 Baud Rate Timing TXD 8 5 8 2 1 3 Transfer Timing when External Clock EXC Used 8 5 8 2 2 Signal Timing Specific to MEM Mode esent 8 6 8 2 2 1 Read Write Timing 7 iet een cree teneri eerie 8 6 8 2 2 2 Output Timing of Interrupt 8 7 8 2 23 Output Timing of STB ZLCARE and 9 8 7 8 2 3 Signal Timing Specific to IO 8 8 8 2 3 1 STB1 STB2 and Data IO Pin eren 8 8 8 3 Package Dimensions Lepus tk ada SUR Sa 2144 XX RE ERE ERE RR dn 8 9 8 4 Recommended Soldering Conditions eese 8 10 8 5 Recommended Reflow 8 10 Appendix 1 Cycle Time Table iiie App 3 Appendi
121. anual STE COT CONTENTS Chapter 1 40 Role and Features 1 1 CUnet Station in MEM Mode MEM Station eere 1 3 1 2 Features of MEM Mode 5 enero ener 1 4 1 3 Station in IO Mode 1 5 1 4 Features of IO MOG ciiin rien ien Ie ete erra bier eren eet eet 1 6 1 5 Mode SGleCHlOM Pc Dc 1 6 Chapter 2 Hardware MEM Mode 2 3 Chapter 3 Connections in MEM Mode Sot Driving Glock edet iouis un rex ades 3 4 3 1 1 Self generation of Driving 3 4 3 1 2 Supplying Generated Driving 3 5 3 1 3 Checking Driving CIoCKk rine peso cere eee eee EC eee sce Una 3 5 3 2 Hardware Heset coe etre ne enr enti nere 3 6 3 3 Connecting Network Interface 3 7 3 31 Recommended Network 3 7 3 3 2 Details of RXD TXE and TXD 3 8 3 3 3 Cautions for Directly Connecting to HUB IC eese 3 8 3 4 Selling Baud
122. as pin assignment pin functions and input out put circuit types in the MKY40 MEM mode Chapter 2 Hardware in MEM Mode TEP S TECHNICA CO LTD Chapter 2 Hardware in MEM Mode This chapter describes the hardware such as pin assignment pin function the MK Y40 MEM mode Figure 2 1 shows the pin assignment in the MK Y40 MEM mode s and input output circuit types in 40 100 pins TQFP 75 Err3 GND 7TA Err3 GND 73 GND 12 GND 71 D31 54 D17 53 Erra3 D16 52 INT1 51 Err3 GND VDD I 17 VDD RXD L3 D15 TXE LT 11 7 014 TXD 113 013 SA0 I TEP D12 SA1 011 SA2 10 SA3 L1 113 09 SA4 I 11 3 D8 SA5 111 INTO OWNO WRLH AO OWN1 I 11 3 GND 2 I 11 3 GND OWN3 11 7 VDD OWN4 CLT I3 D7 OWN5 m 113 06 MON I 11 3 D5 LCARE 113 D4 MCARE 03 113 D2 BPSO mm 113 D1 BPS1 I DO Xo III N C Coo tt ZWRLL VDD rrj 11 3 VDD st LO 0 O ON st WO CN CN CN CN CN 1 1 1 1 1 01111 OQgGgsgagomorulr
123. at freezes a GMSW Global Memory Second ary Window primarily until a specified number of read accesses are completed when reading data from Global Memory GM via the GMSW A hexadecimal read access count of less than 08H can be written to the to ACO Access Count bits of this register When a value of more than 08H is written to this register 08H is forcibly set The values stored in this register are decremented at every read access to the GMSW after they are written If a value other than is stored this register is write protected 5 17 Secondary Window Write Control Register SWWCR Address 32 bit address 40CH big amp little 16 bit address 40EH big 40 little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R RW RW RW RW Functional description This register executes the write window lock function that freezes a GMSW Global Memory Sec ondary Window primarily until a specified number of write accesses are completed when writing data to Global Memory GM via the GMSW A hexadecimal write access count of less than 08H can be written to the to ACO Access Count bits of this register When a value of more than 8 is written to this register 8 is forcibly set The values stored in this register are decremented at every write access to the GMSW after they are written If a value other than OOH is stored this r
124. be output to pin When any of bits 8 9 and 10 of write data is 1 at 16 bit write access and 32 bit write access writing to PoO to Po3 is ignored to prevent operational errors Fig 4 38 General purpose Output Ports Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 4 9 Global Memory Monitor GMM Function The MKY40 has a global memory data monitoring function only for receiving packets from other CUnet stations based on cyclic time sharing without linking with other CUnet stations This function is called Global Memory Monitor GMM and CUnet station operated with this function is called a GMM sta tion When using the MKY40 as a GMM station operate as follows with the user system program 1 Check that the START bit of the SCR System Control Register is 0 2 Write 1 to the GMM bit of the SCR To cancel using as a GMM station write 0 to the GMM bit with the user system program In addition to monitoring described in 4 4 1 Monitoring before Network Start the MK Y40 used as a station can monitor data in Global Memory GM that executes memory data sharing in other CUnet stations The concept of owned area is not applied to the MK Y40 used as GMM station Therefore the setting of Station Addresses SAs and OWN widths is all ignored As for the Receive Flag Register RFR in the MK Y40 used as a GMM station when the Station Time ST indicated by bits to 6 of the
125. between the 40 and the 16 bit wide user CPU are as follows 1 2 3 4 For 16 bit wide user CPUs the byte write and word write CPUs have two write control lines write strobes DO to D7 write strobes D8 to D15 For user CPUs of this type connect the write strobes DO to D7 to the WRLL pin of MKY40 and the write strobes D8 to D15 to the WRLH pin Figure 3 12 shows this type of CPUs For 16 bit wide user CPUs the word write CPU has one write control line write strobes DO to D15 For user CPUs of this type connect the write strobes DO to D15 to the WRLL and WRLH pins of the 40 For sufficient access time between the user CPU and the 4 as described in 3 12 5 Designing Access Time adjust the operation timing of the user CPU if necessary by adding a WAIT gener ating circuit Check the level of signals connected to the user CPU by referring to the electrical characteristics of pins described in Chapter 2 Hardware in MEM Mode 5 When connecting interrupt trigger signals from the 40 to the user CPU refer to 3 12 8 Con nection of Interrupt Trigger Signals Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD 22 O im MKY40 merum E D E A1 to A10 ORB NE 17 18 19 20 21 A1 to A10 78 gt Network I F circuit 77 S 95 Clock input pin used as the baud c 53 to 60 rate depends on the external clock 9 64 to 71 D16 to D31 Should be fixed Hi or Lo le
126. bit at 1 When both the RDY bits of the MROCR and MRICR are 1 received dataset is stored in the MRBO S TECHNICA CO LTD 40 User s Manual 4 3 2 Operation for Mail Reception When the datasets received by mail from other CUnet stations are stored in the MRBO the MK Y40 works as follows Fig 4 21 1 Causes bit 7 RCV ReCeiVed of MROCR to change to 1 2 Causes bit 6 RDY ReaDY of MROCR to change to 0 3 Stores dataset sizes hexadecimal received by mail in bits 0 to 5 SiZe 570 to SZ5 of MROCR The dataset sizes are given in 8 bytes as one unit 4 Stores source Station Addresses SAs hexadecimal in bits 8 to 13 SRC SouRCe0 to SouRCe5 of MROCR 5 Outputs interrupt triggers when mail reception interrupt triggers enabled The user system program must read datasets from the beginning of the MRBO referring to the source SAs and dataset sizes from the MROCR 0 can be written to bit 7 RCV of the MROCR Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 9 9 sRcs sRc4 2 c1 525 524 823 522 521 szo R R R R R R R RW RW R R R R R Source SAs 22A m Dataset sizes received by email using 8 bytes as one unit Changes from to 1 Changes from 1 to 0 Fig 4 21 MROCR with Dataset Stored in MRBO When the datasets received by mail from other CUnet stations are stored in the MRB1
127. bits of the MESR Mail Error Status Register are cleared to 0 this bit is also cleared to 0 Chapter 5 Register Reference in MEM Mode ST CO LTD Resize Overlap RO bit bit 8 Function This bit indicates detection of a resize overlap 1 is set to this bit when resizing of a self station overlaps resizing of other CUnet stations and is disabled When 1 is written to this bit it is cleared to 0 Jammer Detect JD bit bit 9 Function This bit indicates the jammer detection 1 is set to this bit when a jammer is detected When 1 is written to this bit it is cleared to 0 Break Detect BD bit bit 10 Function This bit indicates detection of CUnet station in the BREAK phase When a break packet sent by other CUnet stations was received 1 is set to this bit When 1 is written to this bit it is cleared to 0 Data Renewal DR bit bit 11 Function This bit indicates detection of data transition in global memory 1 is set to this bit when data transition is detected in the memory block corresponding to the DRCR Data Renewal Check Register at 1 The transition timing of this bit from 1 to 0 depends on the MKY40 usage environment Refer to 4 2 4 3 Transition Timing of DR Flag Bit and DRFR Bits from 1 to 0 This flag freezes during the output of the DR Data Renewal interrupt
128. bits other than the owned areas of the self station After understanding the cyclic time sharing read the RFR and LFR at the appropriate time S TECHNICA CO LTD 40 User s Manual 4 2 8 8 Link Group Register LGR The status of the Link Flag Register LFR changes dynamically according to the constantly repeated cycles This change is very fast For example if the baud rate is 12 Mbps and the Final Station FS value is 01H the frame time is 25 5 us Thus the status changes every 25 5 us and is updated every 102 us of one cycle time If the user system manages the status of the LFR in detail the status changes so fast that the program cannot run sufficiently To solve this problem the MK Y40 has a group setting function that helps monitor the LFR status The MKY40 has the 64 bit Link Group Register LGR The LGR monitors the status of the LFR Each LGR bit corresponds to each bit The user system program can write 1 or 0 arbitrarily to the LGR bits The MKYAO clears the LFR to 0 at the starting point of status management and then sequentially detects the LFR bits corresponding to the LGR bits at 1 If all the bits to be detected go to 1 the MK Y40 con siders Link OK If any of the bits to be detected is 0 immediately before the starting point of the next status management after the cycle proceeded the MK Y40 considers Link NG No Good Fig 4 14 C
129. blished with other CUnet stations The MON pin changes to a Low level when one or more CUnet stations with which a link is consecutively established more than three times and then to a High level when a link is not consecutively established with any CUnet station more than three times If the MKYAO in IO mode established a link with other CUnet stations input data in general purpose external I O pins set to input is sent correctly to other CUnet stations The user system can use the MON pin to recognize that data in the pins set to input of the general pur pose external I O pins is sent to other CUnet stations when the output of MON pin is Low The MON pin can be connected to the LED cathode pin to light an LED This pin is capable of driving a current MKY40 in IO mode of 8 mA Any LED which can be lit at a current of 8 510 Q approx 8 mA mA or less can be connected as shown in Figure 7 10 where the LED lights at a Low level The user system s hardware designer needs to determine the value of a cur rent limiting resistor R in Figure 7 10 in accordance with the LED part ratings A green LED part indicating operational stability should be connected to the MON Fig 7 10 Example of LED Connection to MON Pin pin Leave this pin open when not used ter MFR and 4 4 5 3 MON Signal Output S TECHNICA Co LTD Chapter 7 Operation and Connection in IO Mode 7 3 13 Notifying Reception
130. can recognize Link OK or Link NG by receiving interrupt trigger For details refer to 4 5 Interrupt Trigger Generation Function As described above the user system program can monitor the LFR status collectively by pre setting the bits to the LGR bits for monitoring the LFR status Caution If the user system program monitors the link by method 1 above read the SSR at the appropriate time after understanding cyclic time sharing 4 2 3 4 Member The CUnet operation in a stable environment does not allow the occurrence of Dead Link defined in the CUnet protocol and LNG Link Group No Good during status management LGR bits at 17 described in 4 2 3 3 Link Group Register LGR Dead Link and LNG occur when the CUnet station disconnects or trouble with receiving or sending packet occurs due to environmental problems including external noise Instantaneous Dead Link is recovered by the next cycle based on cyclic time sharing that is a CUnet operating principle General communications conventionally use an error handling algorithm when recovery fails after three retries resending when trouble with receiving or sending packet occurs due to environmental problems including external noise The MKY40 has two registers to help manage accordingly 64 bit Member Flag Register MFR and Mem ber Group Register MGR In the 40 the concept of using this management form is called a mem be
131. ceeds to interrupt handling during above steps 1 and 2 making it unclear when read accesses are terminated Such user programs should be avoided Reference Timing sensitive user system programming generally tends to be more difficult Therefore the window lock should be used to avoid data hazards Reading the SCR to recognize the operation timing of the CUnet is also useful for purposes other than avoiding data hazards in the user system program Caution The scope target address range of avoidable data hazard by the window lock is one mem ory block 8 bytes When handling data exceeding this value such as 128 bit data or char acter strings of 9 or more bytes create the user system program based on the description in this section STECHNICA CO LTD 40 User s Manual 4 2 3 Quality Assurance of GM Data The MKY40 with CUnet protocol assures CUnet station to CUnet station N to N communications on a network As defined in the CUnet protocol this assured status is indicated in registers by the receiving status and link status The MKY40 has a function enabling the user system program to monitor each status easily This section describes registers and status monitoring functions related to data quality assurance of Global Memory GM data 4 2 3 1 Status Indication by Registers In the MKYA0O the receiving status and link status defined in the CUnet protocol are indicated by the Receive
132. cks MBs constituting Global Memory GM is written by the latest cycle when the START bit bit 8 of the SCR is set to 1 Bit 0 corresponds to MBO bit 1 to MB1 and bit 63 to MB63 The register bit corresponding to the self station owned area is always 1 except when the GMM Global Memory Monitor bit bit 15 of the SCR System Control Register is 1 when this device operates as a GMM station So as an initial value of this register the register bit corresponding to the self station owned area is 1 and the bit other than that is 0 For details of the bit transition timing of this register refer to 4 2 3 Quality Assurance of GM Data The bit status of this register freezes during the output of ALM ALarM MC Member Change LOK Link group OK and LNG Link group No Good interrupt triggers For details refer to 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation STECHNICA CO LTD 40 User s Manual 5 8 Link Flag Register LFR Address 32 bit address 418H big amp little 16 bit address 41AH big 418 little 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pepe pe pepe 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R Address 32 bit address 418H big amp little 16 bit address 418H big 41 little Bit R W Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LFR LFR LFR LFR LFR LFR LFR LFR
133. cted by pin setting When packets from the CUnet station matching the set ting of DOSAO to DOSAS pins are received data in internal output pins is updated refer to 7 2 2 Data Updating of Internal Output Pins Set by to DOSA5 Internal output pins Set by DOHL Bits 0 to 31 Bits 321063 9 4 When pins set High Bits 0 to 31 When DOSAO to DOSAS5 pins set to 04H 3BH pin Strobe received when packets received from CUnet station matching setting of ZDOSAO to DOSAS pins Fig 7 3 Selection of Data Output to Internal Output Pins Caution Internal output pins Do0 to Do31 are Low until packets are received from the CUnet sta tion matching the setting of the DOSAO to DOSAS pins after hardware reset If the CUnet station matching the setting of the DOSAO to DOSAS pins is not connected to a network the output is not updated S TECHNICA Co LTD Chapter 7 Operation and Connection in IO Mode 7 2 5 Data Structure of Owned Memory Block The following data is embedded in the Memory Block MB owned by the MK Y40 in IO mode set by the SA0 to SA5 pins Table 7 3 1 Bits 0 to 31 Data in internal input pins Di0 to Di31 2 Bits 32 to 34 Setting of IOSO to IOS2 pins 3 Bit35 Setting of 2IOSWAP pin 4 Bits 36 to 38 Always 0 5 Bit39 Setting of LFS pin 6 Bit40 Setting of DOHL pin 7 Bits 41 to 46
134. ction to the user CPU Caution The WRHH ESEL pin 11 WRHL A1 pin 12 and WRLH AO pin 40 pins are shared pins where input signals are selected according to the bus width selected by the set ting of BWO pin 9 and BW1 pin 10 pins S TECHNICA Co LTD MKY40 User s Manual 3 12 1 Connection of 32 bit Wide User CPU The co 1 2 3 4 5 6 7 8 9 10 nnection between the MK Y40 and the 32 bit wide user CPU is described below Fig 3 11 Fix the BW1 pin pin 10 of the MKY40 High and the BWO pin pin 9 High or Low Connect the address bus pins A2 to A10 output from the user CPU to the A2 to A10 pins pins 13 to 21 of the MKY40 Connect the data bus signal pins DO to D31 of the user CPU to the DO to D31 pins pins 29 to 36 42 to 49 53 to 60 64 to 71 Connect the RD signal output from the user CPU to the RD pin pin 23 The WRHH ESEL pin pin 11 functions as the WRHH pin Connect the write strobe signals D24 to D31 output from the user CPU to the WRHH ESEL pin The WRHL A1 pin pin 12 functions as the ZWRHL pin Connect the write strobe signals D16 to D23 output from the user CPU to the WRHL AI pin The WRLH AO pin pin 40 functions as the WRLH pin Connect the write strobe signals D8 to D15 output from the user CPU to the WRLH AO pin Connect the write strobe signals DO to D7 output from the user CPU to the WRLL pin pin 27 Connect a signal to arrange th
135. d with a cycle If CUnet stations at station addresses matching the setting of 4DOSAO to DOSAS pins are not started or not connected to a network pulses are not output from the STB1 pin and data in internal output pins Do0 to Do31 is not updated In this case as compared with the standard features of an I O station the I O station operates as follows 1 The MON pin changes to a Low level 2 The DOA pin remains Low and the DONA pin High 3 The STBI pin remains Low does not output pulses 4 The STB2 pin outputs periodically pulses synchronized with a cycle STECHNICA CO LTD MKY40 User s Manual 7 4 2 Operation in CALL Phase The CALL phase is a state in which CUnet is waiting to be connected Only one I O station connected to a network is started When the MKY40 in IO mode is in the CALL phase packets are sent to send the setting state of and data in internal input pins DiO to Di31 to a network No data in internal output pins DoO to Do31 is obtained from a network In this case as compared with the standard features of an I O station the I O station operates as follows 1 The MON pin remains High 2 The DOA pin remains Low and the DONA pin High 3 The STBI pin remains Low does not output pulses 4 The STB2 outputs periodically pulses synchronized with a cycle The CALL phase is continued until packets can be sent and received to and from other CUnet stations When other CUnet stations are
136. details about how to generate a PING signal refer to 4 4 6 PING Instruction Leave the PING pin open when not used Reference Forcibly resetting a user CPU from a network can be an example of using the PING sig nal For example if a program for a user CPU with one MEM station runs away it can be reset from another CUnet station if the output of the PING pin can perform a hardware reset Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD 3 11 Connecting General purpose Output Ports The MKY40 has four general purpose output ports PoO to Po3 pins 3 to 6 The output levels of these pins can be set by writing data to bits 0 to 3 of the SSR Bit 0 of the SSR corre sponds to the PoO pin and bit 3 corresponds to the Po3 pin The pin corresponding to any of bits 0 to 3 of the SSR where 1 is written is set High When a hardware reset is activated the output levels of these pins are all set Low in preference to writing data to bits 0 to 3 of the SSR Leave the pins open when not used 3 12 Connecting User CPU This section describes connection of a user CPU necessary for accessing the MK Y40 in MEM mode The MKY40 is connected to the user CPU using the CS pin 22 pin 23 WRHH ESEL pin 11 ZWRHL AI pin 12 WRLH AO pin 40 WRLL pin 27 pins address bus pins and data bus pins The signal levels of the BWO pin 9 and BW1 pin 10 pins are combined to set the bus width for conne
137. e MKY40 in memory to the CS pin pin 22 If the data bus signal pins DO to D31 of the user CPU enter the open floating state during the period when all peripheral devices including the MK Y40 do not drive the data bus connect a pull up or pull down resistor The hardware designer should select an appropriate resistance value The precautions for connection between the 40 and a 32 bit wide user CPU are as follows 1 2 3 4 5 6 For 32 bit wide user CPUs the byte write word write and doubleword write CPUs have four write control lines write strobes DO to D7 write strobes D8 to D15 write strobes D16 to D23 write strobes D24 to D31 These four write control lines can be connected to the MKY40 Figure 3 11 shows an example for this type of CPU For 32 bit data wide user CPUs the word write and doubleword write CPUs have two write control lines write strobes DO to D15 write strobes D16 to D31 For user CPUs of this type connect the write strobes DO to D15 to the WRLL and WRLH pins of the MK Y40 and the write strobes D16 to D31 to the WRHL and WRHH pins For 32 bit wide user CPUs the doubleword write CPU has one write control line write strobes DO to D31 For user CPUs of this type connect the write strobes DO to D31 to the WRLL WRLH WRHL and WRHH pins of the MK Y40 For sufficient access time between the user CPU and MKY40 as described in 3 12 5 Designing Access Time adjust
138. ead strength 8 5 Recommended Reflow Conditions gt Package surface temperature tw Time Parameter Pre heat time 60 to 120 s Pre heat temperature 150 to 180 C Temperature rise rate 2 to 5 C s Peak condition time 10 3 Peak condition temperature 255 5 C Cooling rate 2 to 5 C s High temperature area 220 C 60 5 max Removal temperature lt 100 C Caution The recommended conditions apply to hot air reflow or infrared reflow Temperature indi cates resin surface temperature of the package Appendix Appendix 1 Cycle Time Table Appendix2 Internal Equivalent Block Diagram IO Mode Appendix 3 Register List in Address Order S TECHNICA Co LTD Appendix Appendix 1 Cycle Time Table 12 Mbps 6 Mbps 3 Mbps 102 00 204 00 408 00 128 33 256 67 513 33 155 00 310 00 620 00 182 00 364 00 728 00 209 33 418 67 837 33 237 00 474 00 948 00 265 00 530 00 1 060 00 293 33 586 67 117338 322 00 644 00 1 288 00 351 00 702 00 1 404 00 380 33 760 67 1 521 33 410 00 820 00 1 640 00 440 00 880 00 1 760 00 470 33 940 67 1 881 33 501 00 1 002 00 2 004 00 532 00 1 064 00 2 128 00 563 33 1 126 67 2 253 33 595 00 1 190 00 2 380 00 627 00 1 254 00 2 508 00 659 33 1 318 67 2 637 33 692 00 1 384 00 2 768 00 725 00 1 450 00 2 900 00 758 33 1 516 67 3 033 33 792 00 1 584 00 3 168 00
139. eceived from other CUnet stations If a hardware reset is activated this pin is kept Low in preference to the PING instruction from other CUnet stations Positive Output pin to notify that data in 100 to 1031 pins set to output by setting of IOSO to IOS2 pins updated within a given time If data is updated within a given time this pin is kept High When a hardware reset is activated this pin is kept Low Positive Input pin to force 1016 to 1031 pins set to output by setting of IOSO to IOS2 pins to specific level When the input of this pin is Low the last stage latch of 1016 to 1031 pins set to output is cleared to 0 The 1016 to Io31 pins output High or Low according to the setting of the INV4 to INV7 pins Negative Input pin to force 100 to 1015 pins set to output by setting of IOSO to IOS2 pins to specific level When the input of this pin is Low the last stage latch of 100 to 1015 pins set to output is cleared to 0 The 100 to 1015 pins output High or Low according to the setting of INVO to INV3 pins Negative Input pin to set MK Y40 in IO mode to frame option Usually fix this pin at High Fix this pin at Low only when con structing a CUnet just using IO stations and setting the MK Y40 in IO mode to a long frame LF Negative Input pin to set whether to select upper bits bits 32 to 63 or lower bits bits 0 to 31 of memory blocks MBs selected by DOSAO to DOSAS pin
140. egister is write protected STECHNICA CO LTD 40 User s Manual 5 18 Mail Receive 0 Control Register MROCR Address 32 bit address 48CH big amp little 16 bit address 48EH big 48 little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R W R R R R R R Functional description This register controls the mail reception corresponding to the MRBO Mail Receive Buffer 0 Bit description receive SiZe 520 to SZ5 bit bits O to 5 Function These are bits where the dataset size hexadecimal of the received mail is set when the MRBO receives mail The dataset size uses 8 bytes as one unit receive ReaDY RDY bit bit 6 Function This bit sets permission for the MRBO Mail Receive Buffer 0 to receive mail This bit can be operated when the RUN bit of the SCR is 1 When 1 is written to this bit the MRBO is permitted to receive mail When this bit is 0 the MRBO is inhibited from receiving mail This bit value cannot be set from 1 to 0 during mail reception by the MRBO Therefore when 0 is written read this bit to check its status When 1 is written to this bit the RCV bit is forcibly set to 0 If the RUN bit of the SCR changes to 0 when this bit is 1 this bit also changes to 0 ReCeiVed RCV bit bit 7 Function This bit indicates the completion of mail reception This bit changes to 1 at comple
141. end Finish When mail sending to other CUnet stations termi nates correctly or incorrectly 4 3 3 Operation for Mail Sending and after Completion of Sending MGNE Member Group Not Equal When bit 4 MGNE of SSR changes from 0 to 1 4 2 3 6 Member Group Register MGR MGNC Member Group Not Collect When bit 5 MGNC of SSR changes from 0 to 1 4 2 3 6 Member Group Register MGR RC Resize Complete When resizing of self station completed in response to resize command from another CUnet station 4 4 2 1 Resizing RSTP Run SToP When network stops 4 1 8 Network Stop RSTR Run STaRt When MKY40 enters RUN phase 4 1 3 Initialization and Start up of Com munication MC Member Change When number of 1s of member flag bit increases or decreases 4 2 3 7 Detection of Member Increase and Decrease LOK Link group OK When Link OK judged by checking LFR bit corre sponding to LGR with bit 1 4 2 3 3 Link Group Register LGR LNG Link group No Good When Link No Good judged by checking LFR bit corresponding to LGR with bit 1 4 2 3 3 Link Group Register LGR BD Break Detect When CUnet station in BREAK phase detected 4 4 3 Detection and Handling of CUnet Station in BREAK Phase RO Resize Overlap When resize overlap occurs 4 4 2 3 Resize Overlap RO PR Ping Receive When PING i
142. er function causes the status to change from High to Low with acceptance of the next interrupt disabled This may prevent the user CPU from processing interrupts Level detection type The EOI code is issued after the status of the INTOSR is cleared If the INTOSR status is cleared after issuing EOI the Low level status may be detected again and interrupts may be accepted again Caution An algorithm of the interrupt handling and canceling procedure depend on the user system such as the type of the user CPU and peripheral hardware Use the 40 appropriately according to the user system Chapter 4 Software in MEM Mode TEP S TECHNICA CO LTD 4 5 3 Interrupt Factors The INTerrupt 0 Control Register INTOCR has the following 16 types of interrupt factors that can be enabled Table 4 3 Interrupt factor ALM ALarM Table 4 3 Interrupt Factors When trigger output occurs requirements When ST during cycle reaches time previously specified to ITOCR This interrupt trigger occurs every cycle Reference 4 1 7 Detailed Timing during Cycle DR Data Renewal Only when data transition of GM corresponding to detection bit previously set to DRCR detected and when ST during cycle reaches time previously spec ified to ITOCR 4 2 4 Detection of Global Memory Data Transition MR Mail Receive When mail received from other CUnet stations 4 3 2 Operation for Mail Reception MSF Mail S
143. er supply the GND pins pins 1 25 38 39 40 51 62 72 73 74 75 to 0 V power supply Connect a 10 V 0 1 104 or higher capacitor between the adjacent VDD and GND pins Leave the NC No Connect pins pins 3 to 6 52 63 94 open Caution Pin 40 of the MKY40 has a function in MEM mode but no function in IO mode It should be connected to GND STECHNICA CO LTD 40 User s Manual 7 1 Internal Configuration of MKY40 in IO Mode In IO mode the 40 has 32 bit internal input pins Di0 to Di31 and 32 bit internal output pins 000 to Do31 as well as a CUnet IC core The 32 bit internal input pins DiO to Di31 and 32 bit internal output pins DoO to Do31 are connected to general purpose external pins 100 to 1031 using a multi selector Fig 7 1 INVO to INV7 STB2 MKY40 IO mode CUnet IC core Input update strobe Signal at lead point of packet sending Packet sending data Bits 32 to 63 32 bit internal input Each setting pin status pins 010 to 0131 RXD uuum Se i Km TD Packet sending data Bits 0 to 31 Receive data 64 bits for memory block MB X 10010 lo31 Bit 16 bit latch Selection between upper and lower bits i selector mD Receive strobe MN CLK 3 CLR Receive data 6 bits D 16 bit latch for memory block MB 2 4 66 Matching 3 32 bit internal
144. er to 3 12 7 Data Storage Method 4 1 2 Checking Connection of MKY40 When theMKY40 is connected correctly to the user CPU the ASCII character string MKY40_v1 can be read when the Chip Code Register CCR is read If this character string can be read the user CPU can check that the MKY40 is connected The character string is MKY40_v1 when read from a little endian user CPU and 4YKM1v_0 when read from a big endian user CPU When the network is not started the START bit of the SCR System Control Register 15 50 any data can be written to all memory except registers 400H to 4FFH of the MK Y40 When any data is written to each memory for read verification the user CPU can check that the 40 is correctly connected to the user CPU Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 1 3 Initialization and Start up of Communication This section describes how to start communication Fig 4 1 1 Memory in the MKY40 after power on contains undefined values Write data at address 00H to a memory GM GMPW GMSW MSB MRBO except the register area at addresses 400H to 4FFH to clear the undefined values Table 4 1 Set SA OWN BPS 2 Set the Station Address SA OWN width OWN and baud rate BPS When a hardware Check that START of SCR is 0 reset is activated the MK Y40 writes combina nc Bk SH tion of High and Low le
145. et sending of data in the owned area of the self station 4 1 8 3 Stop Exception 1 If network stop by SNF or by OC occurs while the self station performs resizing when a value other than QOH is stored in the NFSR the network stops with the value stored in the NFSR The SNF bit and OC bit of the SCR and the NFSR are both cleared to 0 when the user system program writes 1 to the START bit of the SCR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 1 8 4 Stop Exception 2 If a CUnet station has a continuously unstable power supply immediately after power on network stop by SNF Station Not Found may occur immediately after a start is made by the following sequence The fol lowing is a stop sequence of a CUnet constructed by two MEM stations 1 The user CPU writes 1 to the START bit of an MEM station and this MEM station enters the CALL phase 2 1 is also written to the START bit of another MEM station and this MEM station and the above MEM station enter the RUN phase 3 If stability after power on of a MEM station is delayed and a hardware reset is activated again the START bit returns to 0 4 Another MEM station stops by SNF after 32 cycles 5 The program starts again from the beginning 1 is written to the START bit in a MEM station and the MEM station enters the CALL phase 6 Because the network is stopped by SNF another MEM station does not start again
146. etween little endian and big endian are represented as register addresses The addresses differ according to the endian type of the user CPU at byte and word access from the 32 16 and 8 bit wide buses Figure 3 15 b shows an example of reading the same address with big and little endian user CPUs a Internal configuration of address 000H in doubleword representation Big endian Little endian 000H 001H 002 003H Address 0034 002 001 H 8 31 24 23 16 15 8 7 0 31 24 23 16 15 8 7 0 Data bus Data bus bit b Cautions for access between CPUs with different endian types Big endian Little endian 000H 001H 002 003H 003H 002 001 OOOH 12 34 56 78 12 34 56 78 At doubleword 32 bit wide access from the 12345678 Doubleword read at 0001 12345678H So bitwide dab bue the aidrocnon do tex differ with endian type 1234H Word read at 000H 5678H 5678H Word read at 002H 1234H Even if data at the same address is accessed 12H Byte read at 000 78H data at a different location is read 34H Byte read at 001H 56H 56H Byte read at 002H 34H 78H Byte read at 003H 12H Fig 3 15 Data Storage Method 40 treats one occupied area 8 bytes in global memory as 32 bit wide data This does not cause a problem when building a s
147. f the MCARE Up to 255 MCARE occurrences are FK indicated at bits 8 to 15 MCCO to Bit 15 14 13 12 11 10 9 8 of the Care Counter Register 7 6 5 4 2 2 CCR Fig 4 34 MCC of the CCR is R R R R R R RW held at 255 FFH LCARE occur Number of MCARE occurrences rences without counting more than 256 times When 1 is written the number of MCARE occurrences is cleared to 00H When recognizing the number of _ MCARE occurrences with the user sys tem program read bits 8 to 15 MCCO to MCC7 of the CCR When clearing the number of MCARE occurrences by the user system program write 1 to bit 8 of the CCR A Low pulse output from the MCARE pin is generated by a retriggerable one shot multivibrator with a Fig 4 34 Number of MCARE Occurrences of CCR minimum time of 2096896 x TXT Therefore if a new MCARE occurs within this time the Low pulse width gets longer If the driving clock of MKY40 is 48 MHz the minimum time of the Low pulse is about 43 ms and lit LED can be seen Low pulses output from the MCARE pin can be changed to short pulses of 5 to 7 TBPS time When changing the Low pulses to short as described in Step 2 3 in 4 1 3 Initialization and Start up of Com munication write 1 to bit 14 CP Care Pulse of the Basic Control Register BCR Low pulses output from the L
148. g The 40 can mail the datasets written to the MSB Mail Send N Buffer to one specific Station Address SA The procedure is shown 000H Global Memory below Primary Window 1 When the bit 14 SEND of MSCR Mail Send Control Register GMPW is 0 write the datasets sequentially from the starting address of 200 Global Memory the MSB Fig 4 23 iie GMSW 2 Check that bit 15 ERR ERRor of the MSCR is 0 If the ERR 400H Registers reserved flag bit is not 0 the previous error remains Set the flag bit to by manufacturer 0 referring to 4 3 4 Operation against Mail Sending 500H Error If the ERR flag bit is 1 writing 1 to the SEND bit MSB described in 4 is ignored Fig 4 24 600H Receive Buffer 0 3 When setting the time out of mail sending write the time out val MRBO ues hexadecimals defined by the user system using a cycle time 700 Receive Buffer 1 MRB1 as one unit to bits to 12 LiMit Time LMTO to LMT12 of the 9 J MSLR Mail Send Limit time Register The initial value of the Fig 4 23 Mail Send Buffer MSLR is set to 1FFFH by hardware reset If the user system does not determine a time out value there is no need to write it The data written to the MSLR is held until a
149. g these pins open is comparable to keeping them High Caution The same SA values cannot be set to all CUnet ICs connected to one network Duplication of owned areas by expansion setting is prohibited STECHNICA CO LTD 40 User s Manual 3 7 Expansion Setting for Owned Area The MKY40 has six pins HOWNO to OWNS pins 86 to 91 to set OWN widths in order to increase prac ticality expand owned area defined by the CUnet protocol The to OWNS pins are negative logic input pins that are pulled up internally The OWN widths are given in hexadecimal as OOH 0 to 63 with a High level input to the OWNO to OWNS pins set to 0 and a Low level to 1 The most significant bit is HOWN pin 91 Fig 3 9 When a hardware reset is activated the MK Y40 writes the pin settings to the BCR OWN widths can be reset by rewriting data of the BCR by the user system For details refer to 4 1 3 Initialization and Start up of Communication When the setting value of the pin is OOH all High the OWN width is treated as 01 If the setting is added to the SA value and exceeds 64 40H the value exceeding 64 is ignored For example when SA 62 3EH the OWN width is 2 even if OWN is 03H When SA 32 0H the OWN width is 32 even if OWN is 63 3FH T UT MKY40 Due to the negative logic the ON bi
150. gement LFR Bit 63 62 16 15 14 13 12 11 10 9 8 7 e 8 4 8 2 1 o The bit beyond the owned area of self station is cleared to 0 at lead point of self ST start point of status management The bit of the target CUnet station where link established goes to 1 sequentially up to starting point of next status management 22 Fig 4 12 64 bit RFR and LFR Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 2 3 2 Starting Point of Status Management and Exception In the MKY40 the real time status based IE a E cycle transition at cyclic time sharing is Status flag in CUnet station with SA 2 when FS reflected in the status of RFR and LFR The one Example of RFR Packet with SA 0 Bit 543210 lead point of ST corresponding to the SA of gt 31310111 the self station is the starting point of status ae 4 Packet with SA 1 Bit 54 32 10 management Fig 4 13 2 o 1 1 The status of the RFR is managed Transmit oo gt Tolololalolo 7 with SA 2 every cycle Except for the case described in In CUnet station with SA 2 1 2 this timing is the base point of section 4 5 8 Register Freezing In Syn status management chronization with Interrupt Trigger Gen 43210 eration RFR and LFR are cleared to 0 at the starting point of status management The Bt 5 4 3
151. gnal that controls writing to D24 to D31 data to the WRHH input pin If either this pin the CS pin goes High when both pins are Low D24 to D31 data in the bus is written into the MKY40 This pin functions as the ESEL input pin selecting the user CPU endian type when the BW1 pin is Low Set the ESEL input pin to High when the user CPU is big endian and to Low when the user CPU is little endian Negative Positive This pin functions as the WRHL input pin when the BW1 pin is High Connect a signal that controls writing to D16 to D23 to the WRHL input pin If either this pin or the CS pin goes High when both pins are Low D16 to D23 data in the bus is written into the MKY40 This pin functions as the A1 input pin of the 10 bit address bus pins to A10 connected to the user CPU when the BW1 pin is Low When using the A1 input pin connect the A1 signal output from the user CPU to the A1 input pin A2 to A10 13to 21 Positive Parts of address bus pins connected to user CPU Connect A2 to A10 signals output from the user CPU to these pins Negative Access control pin connected to user CPU Set this pin Low at the right time when the user CPU performs read or write access to MKY40 Negative Read control pin connected to user CPU Set this pin Low at the right time when the user CPU reads the 40 When both this pin and the CS pin are Low the MKY40 outputs data with a bus width based on the setting
152. h Allowable difference between write signals Write data setup Write data hold Caution The above diagram shows the setting of all bus widths the functions of the pin signals of ESEL AO to A10 WRHH WRHL WRLH WRLL DO to D31 read DO to D31 write depend on the setting of bus widths ECHNICA CO LTD Chapter 8 Ratings T 8 2 2 2 Output Timing of Interrupt Trigger INT1 INT2 TINTLL Passage of time Symbol Name Unit TINTLL Pin Low level width Fioxt ns 8 2 2 3 Output Timing of STB ZLCARE and ZMCARE STB Tsw LCARE MCARE Passage of time STB pin output Low level width 1 8 x TBPS 2x 5 2 2 x TBPS CARE pulse Low level width CP flag bit in BCR 1 5 x TBPS 6 x TBPS 7 x TBPS CARE pulse Low level width CP flag bit in BCR 0 Retriggerable one shot multi vibrator output 221 256 x Txi STECHNICA CO LTD 40 User s Manual 8 2 3 Signal Timing Specific to IO Mode This section shows specifications for signal timing specific to IO mode of MKY 40 8 2 3 1 STB1 STB2 and Data IO Pin Timing Passage of time Ts1w STB1 Tso TDOT 100 1031 output Ts2w STB2 Tbis lo0 l031 input STB1 High level width 1 8 x TBPS TXI 2 x TBPS TXI 2 2 x TBPS TXI STB1 Data o
153. he MEM station with a smaller value SA than that of the self station As mentioned above if a resize overlap occurs it is hard to specify the FS value to be resized depending on the operation timing of an MEM station To prevent these problems use an algorithm to prevent the occurrence of resize overlaps as described in the following examples 1 Specify one MEM station to perform resizing 2 The user system where multiple MEM stations perform resizing should hold a superordinate concept program requiring acquisition of the right to perform resizing STECHNICA CO LTD 40 User s Manual 4 4 3 Detection and Handling of CUnet Station in BREAK Phase The MKY40 may enter the BREAK phase e When the CUnet station with an owned area larger than a Final Station FS value starts the network in the cycle that the FS value is resized as described in 4 4 2 Hesizing of Cycle Time e When the CUnet station stopped by OC Out of Cycle described in 4 1 8 2 Details of OC Out of Cycle starts the network again The CUnet station in the BREAK phase issues a break packet to another CUnet station in the RUN phase that is already active on a network in the stage of public frames constituting a cycle The MKYAO in the RUN phase receives this break packet and then set bit 10 BD Break Detect of the System Status Register SSR to 1 to warn the user system program about the presence of a CUnet station in the BREAK phase Fig 4 30
154. he user system uses the MK Y40 mail sending reception function 1 Mailing is limited to a station in the MEM mode The address of the IO station or the Station Address SA owned and expanded by OWN setting can not be specified as a mailing address If the address of the IO station is specified accidentally the mail to that address is terminated with an NORDY destination NOt ReaDY error If the SA owned and expanded by the OWN setting is specified accidentally the mail to that SA is terminated with an NOEX destination NOt EXist error 2 Broadcast mailing a method called discharge used for general RS 232C or broadcast in LAN communication cannot be performed 3 Mail sending and reception is performed in 8 bytes the CUnet protocol Therefore broadcast mailing that cannot be guaranteed by the 40 protocol cannot be used Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 4 Detailed Operation and Management of CUnet System The user system program can operate the MKY40 to operate and manage details of a CUnet system as shown below 1 Monitoring before network start 2 Resizing of cycle time 3 Detection and handling of CUnet station in BREAK phase 4 Detection and handling of jammer 5 Controling and monitoring network quality 6 PING instruction 7 Function to detect mode of each station 8 Operation of general purpose output ports 9 GMM Global Memory Monitor function 10 Frame opt
155. his bit indicates the status of a frame option This bit keeps 1 when a frame option is set For details on the frame option refer to 4 4 10 Frame Option for HUB Global Memory Monitor GMM bit bit 15 Function This bit operates the GMM function 1 can be written to this bit only when bit 8 START is 0 When 1 is written to this bit this device MK Y40 operates as GMM station This bit must be 1 when writing data to the BCR Basic Control Register For details of GMM refer to 4 4 9 Global Memory Monitor GMM Function S TECHNICA Co LTD MKY40 User s Manual 5 4 System Status Register SSR Address 32 bit address 448H big amp little 16 bit address 44AH big 4484d little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mc NM LOK BD JD MR MGNC MGNE mita o o 0o 1 1 o o 0 0 R W R R R R R R W RW R R R R RW RW RW RW Functional description This register stores various status in network operation for details of the starting point of status man agement or the time to update some bits of this register refer to 4 2 3 2 Starting Point of Status Management and Exception Bit description port Out PoO to Po3 bit bits O to 3 Function These bits set the output levels of general purpose output port pins to Po3 pins 3 to 6 Bit 0 corresponds to the PoO p
156. ifying Timing of Interrupt Trigger Generation The values to set timing to the ITOCR and ITICR are 0 to 127 OOH to 7FH but a CUnet cycle uses the values stored in the Final Station Register FSR with up to 2 added When numerical values exceeding these values are written to the ITOCR or ITICR corresponding interrupt triggers are not generated Do not write an incorrect value In particular the DR generation timing is the update timing of the DRFR described in 4 2 4 3 Transition Timing of DR Flag Bit and DRFR Bits from 1 to 0 Therefore if numerical values exceeding the values stored in the Final Station Register FSR with 2 added are written the DRFR is not updated Chapter 4 Software in MEM Mode SF ECHNICA 4 5 7 Precautions for Use of Data Renewal DR Interrupt Trigger The interrupt factor Data Renewal DR can use the INTO pin and INT1 pin at a time When the INTOCR is first enabled writing 1 to the enable bit of the INTICR is protected To the con trary when the INTICR is first enabled writing 1 to the enable bit of the INTOCR is protected Interrupt trigger generation timing of the DR is the time set at bits 8 to 14 of the ITOCR when the INTOCR is enabled and the time set at bits 8 to 14 of the ITICR when the INTICR is enabled The same is true for the timing of bit 11 DR Data Renewal of the System Status Register SSR and the Data Renewal Flag Registe
157. igh write access is assumed to have been terminated and data on the data bus pins DO to D7 is written S TECHNICA CO LTD 40 User s Manual 3 12 5 Designing Access Time Read access to MKY40 driven by a 48 MHz clock requires 130 ns more until condition 1 in 3 12 4 Recognition of Access is established Write access requires 90 ns or more by the time condition 2 in 3 12 4 Recognition of Access is established The MKY40 requires an access interval of at least 2 x TXT about 43 ns when driven by a 48 MHz clock This access time must be allowed for when designing the connection between the MKY40 and user CPU Fig 3 14 4 Address CS 2 3 RD WRHH WRHL WRLH WRLL Access condition established Access condition established Proper access interval E User CPU MKY40 Access Time required to establish condition Address Read 130 ns Fa Write 90 ns mo User circuit ecessary access interva WRHH WRHL 43 ns min WRLH WRLL WRLH WRLL DB MKY40 Pins Bus transceiver inserted a The address must not change while establishing the condition Direction controlled by control signal Address CS RD WRHH WRHL WRLH WRLL CPU bus MKY40 bus Skew is not allowed for control lines while establishing the condition An unexpected condition must not occur while ensuring the access inter
158. il sending and mail sending stopped If mail sending is unsuccessful the KY40 stores the status with error type 1 in the MESR Mail Error Sta tus Register Fig 4 26 When any of bits 0 to 5 of the MESR are 1 both bit 15 ERR ERRor of the MSCR and bit 7 MSE Mail Send Error of the SSR System Status Register are set to 1 If mail sending is unsuccessful the user system program needs to refer to the MESR and deal with in accordance with the error type Bits 0 to 5 of the MESR can all be cleared to 0 by writing some data to addresses where they exist This clearing causes both bit 15 ERR of the MSCR and bit 7 MSE of the SSR to return to 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MESR o o o o o o 0 0 o stop 1 1 827 11 Tout R R R R R R R R R R RW RW RW RW RW RW l When some data is written to these bytes ee the error status returns to 0 STOP communication STOPped Mail sending is stopped because the system enters a phase other than RUN during mail sending The setting value of MSLR is invalid LMFLT LiMit time FauLT The mail sending size setting value is invalid SZFLT SiZe FauLT The time required for mail sending exceeded the number of cycles set in the MSLR TOUT limit Time OUT The destination MEM station does not exist NOEX distination NOt
159. in and bit 3 to Po3 pin Write 1 for the High level output of a corresponding pin and 0 for the Low level output The bits are not written when any of the write data bits 8 9 and 10 is 1 in 16 bit write access and 32 bit write access Member Group Not Equal MGNE bit bit 4 Function This bit indicates MGR MFR 1 is set to this bit when the bit status of the MFR Member Flag Register does not match the bit status of the MGR Member Group Register at the starting point of status manage ment 0 is set to this bit otherwise Member Group Not Collect MGNC bit bit 5 Function This bit indicates MGR gt MFR 1 is set to this bit when any of the bits of the MFR corresponding to the MGR at 1 is 0 at the starting point of status management It is set to 0 otherwise Mail Received MR bit bit 6 Function This bit indicates completion of mail reception 1 is set to this bit when the MRBO Mail Receive Buffer 0 or MRB1 Mail Receive Buffer 1 completes the reception of dataset by mail When the RCV ReCeiVed bits of the MROCR Mail Receive 0 Control Register and MRICR Mail Receive 1 Control Register are cleared to 0 this bit is also cleared to 0 Mail Send Error MSE bit bit 7 Function This bit indicates that mail sending is terminated with an error 1 is set to this bit when an error occurs during mail sending When all
160. ine at the bottom of Fig 4 18 to bit 0 of DRFR Made addition and modification to description of 2 at the Caution part in 4 3 2 Operation for Mail Reception Changed the cacography GMM station in the second paragraph to CUnet station Improved the description of the third paragraph Made the sentences of items MGNE and MGNC in Table 4 3 appro priate Added a Caution part under Table 4 4 Added the following two sentences to Function part in receive ReaDY RDY bit bit 6 item This bit can be operated when the RUN bit of the SCR is 1 If the RUN bit of the SCR changes to 0 when this bit is 1 this bit also changes to 0 Added the following sentence to Function part in ReCeiVed RCV bit bit 7 item If the RUN bit of the SCR changes to 0 when this bit is 1 this bit also changes to 0 B North America Distributor Trans Data Technologies Inc 340 Arthur Ave Roselle IL 60172 Telephone 630 440 4075 Facsimile 630 539 4475 e mail info steptechnica us http www steptechnica us Developed and manufactured by Step Technica Co Ltd 757 3 Shimo fujisawa Iruma shi Saitama 358 0011 TEL 04 2964 8804 FAX 04 2964 7653 http www steptechnica com info steptechnica com CUnet CUnet IC MKY40 User s Manual Document No STD CU40 V2 4E Issued February 2009
161. ing resistor DR between the Xo pin and oscillator 3 The allowable oscillating frequency accuracy is within 500 ppm 4 To recognize the oscillating state and measure the oscillating frequencies use the TXD pin Reference StepTechnica provides some technical information such as an appropriate capacitance for the oscillator how to stabilize oscillation For more information visit our Web site at www steptechnica com Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD 3 1 2 Supplying Generated Driving Clock An external clock oscillator generated can be supplied directly to the MK Y40 and used as the driving clock In this case supply 40 the driving clock to the Xi pin pin 99 of the 40 and leave the Xo pin pin 98 open Crystal oscillator The specifications for direct supplying the driving clock exter nally are as follows 1 The upper frequency is 50 MHz and a lower frequency is not provided Usually supply a 48 MHz clock Fig Ge Supplying IVING 2 Electrical characteristics of the Xi pin VIH min 3 5 V VIL max 1 5 V 3 Connect a clock with a signal rise and fall time of 20 ns or less 4 Connect a clock with a minimum High level or Low level time of 5 ns or more 5 Connect a clock with jitter component of e 250 ps or less at input frequency of 25 MHz or more e 500 ps or less at input frequency of less than 25 MHz
162. ins I O station MEM station MEM station General purpose external I O pins I O station User CPU Fig 1 4 CUnet Connecting Two Modes STECHNICA CO LTD MKY40 User s Manual 1 4 Features of IO Mode The IO mode of the MKY40 has the following features 1 Can be connected to up to 64 CUnet stations 2 Occupies one memory block 8 bytes in GM 3 Standard baud rates of 12 6 and 3 Mbps 4 Has 32 general purpose external I O pins that can be selected between input and output every 4 bits and the logic between pin levels and data can be inverted 5 Has various pins for timing output and LED indication that can be easily expanded and applied by user application 6 Can configure CUnet system using only I O stations 7 The CUnet protocol of the 40 guarantees that data can be treated by general purpose exter nal I O pins without error or garbage 1 5 Mode Selection The MKY40 can use the MEM mode and IO mode in configuring a CUnet system The 40 functions in MEM mode by keeping the MODE pin pin 2 Low and in IO mode by keeping the MODE pin High This manual describes the MEM and IO modes separately Caution In the MKYAO the I O pin specifications are changed by changing the MODE pin setting Therefore do not change the MODE pin setting while power is applied Chapter 2 Hardware in MEM Mode This chapter describes the hardware such
163. ins can be used separately as follows 1 INTO pin to output frequently used interrupt trigger signals 2 INT1 pin to output interrupt trigger signals for processing error and failure that occur rarely This section describes the operation of the interrupt trigger generation function and the operation of the MKY40 associated with the interrupt trigger output S TECHNICA CO LTD 40 User s Manual 4 5 1 Operation of INTO Pin The interrupt trigger generation function of the INTO pin can be used through the following operation with the user system program Fig 4 41 1 The INTerrupt 0 Control Register INTOCR is a register that enables the function of the INTO pin Of the INTOCR interrupt factors write 1 to the bit corresponding to the interrupt factor that the user system requires and enable the function of the INTO pin When the enabled interrupt factor by the INTOCR occurs status 1 that occurred in the INTerrupt 0 Status Register INTOSR with the same bit assignment as that of the INTOCR is held and a Low level is output from the INTO pin 2 3 wm The user system program can recognize which interrupt factor generated an interrupt trigger by read ing the INTOSR 4 Write 1 to the corresponding interrupt factor bit of the INTOSR after completion of interrupt han dling by the user system program This clears the 1 held status of INTOSR and the corresponding
164. ion for HUB STECHNICA Co LTD MKY40 User s Manual 4 41 Monitoring before Network Start The MKYAO receives packets from other CUnet stations even before network start at START bit of SCR 0 Global memory updating and mail reception are not performed with the received packets but updating of the Receive Flag Register RFR and Final Station Register FSR and synchronization with and calibra tion of other CUnet stations in cyclic time sharing are performed This enables the user system program to perform monitoring before network start as shown below 1 The user system program can recognize that a resized cycle is operating on a network A resized cycle is operating if values stored in bits 0 to 5 FSO to FS5 of the FSR are anything other than the initial value 63 3FH If an FSR value is smaller than the owned area of a self station the user sys tem program can also estimate that the 40 enters the BREAK phase after having started the self station network 2 The user system program can recognize the Station Time ST that is the operation timing in cyclic time sharing by reading bits 0 to 6 STO to ST6 of the SCR System Control Register 3 At the timing that the Station Time ST exceeds the value stored in the FSR at the public frame period by reading the RFR the user system program can recognize that if there is a bit at 1 in any place other than the owned area of a self station
165. ion for a CUnet constituted only by I O stations fix the LFS pins of one or more I O station connected to a network at Low This places all CUnet stations connected to a network in a frame option state when the network operates The frame option is set for the CUnet station which is later con nected or powered to the operating network for which the frame option is set The cycle time with a length of frame LOF of 256 is the value in the frame option LF 1 column given in Appendix 1 Cycle Time Table based on Equations 4 1 and 4 2 described in 4 1 6 Cycle Time of CUnet Caution To cancel the frame option for the system the hardware reset needs to be activated for all CUnet ICs in the system In this case keep the LFS pin of an I O station High Reference In a system where or more MEM stations constituted by the 40 in MEM mode exist set the LFS pin of an I O station High and use the frame option according to the description of 4 4 10 Frame Option for HUB 7 3 6 Connection of General purpose External I O Pins Connect signals that a user circuit requires to general purpose external I O pins 100 to 1031 pins 29 to 36 42 to 49 53 to 60 64 to 71 When connecting signals to the user circuit appropriate levels must be kept refer to Chapter 6 Hardware IO Mode Set unused general purpose external I O pins to output for open or to input for connection to a pul
166. ion of values to be written to the NFSR or correlation with other CUnet stations To prevent this problem when resizing follow the procedures below Fig 4 28 1 Write a value to bits 0 to 5 NFSO to NFS5 of the NFSR Read the NFSR to check that the written value is stored in the register If the value is 2 not stored in the register the register is not ready or the value is rejected Refer to 4 4 2 2 Rejection of Resizing to stop resizing or perform resizing again with an appropriate value 3 Wait for four times the cycle time with FS max 63 3FH Read the System Status Register SSR to check that bit 8 RO Resize Overlap of the SSR is 0 If the RO bit is 1 refer to 4 4 2 3 Resize Overlap RO and 4 4 2 4 Caution when RO Occurs to deal with accordingly Read the Final Station Register FSR to check that its value is the same as the value written to the NFSR 4 5 If the value is different the waiting time in 3 may be insufficient RO in 4 may occur or the RUN phase may be terminated forcibly Read the System Control Register SCR to check that bit 9 RUN is 1 RUN phase and repeat steps 3 and 4 If the RUN bit of the QSCR is 0 refer to 4 1 8 Network Stop to deal with accord ingly an N Write value to NFSR Wait for four times the cycle time with FS For example when 12 Mbps 2
167. it controls the network start and stop When 1 is written to this bit the network starts This bit keeps 1 during network operation A network can be stopped intentionally by writing 0 when this bit is 1 RUN phase RUN bit bit 9 Function This bit indicates the phase of this device MKY40 This bit keeps 1 in the RUN phase CALL phase CALL bit bit 10 Function This bit indicates the phase of this device MKY40 This bit keeps 1 in the CALL phase BReaK phase BRK bit bit 11 Function This bit indicates the phase of this device MKY40 This bit keeps 1 in the BREAK phase Out of Cycle OC bit bit 12 Function This bit indicates that the network is stopped due to OC Out Of Cycle When the network is stopped due to OC 1 is set to this bit This bit is cleared to 0 when 1 is written to bit 8 START or when a hardware reset is activated For details on OC refer to 4 1 8 Network Stop Chapter 5 Register Reference in MEM Mode ST ECHNICA CO LTD Station Not Found SNF bit bit 13 Function This bit indicates that a network is stopped due to SNF Station Not Found When a network is stopped due to SNF 1 is set to this bit This bit is cleared to 0 when 1 is written to bit 8 START or when a hardware reset is activated For details on SNF refer to 4 1 8 Network Stop Long Frame LF bit bit 14 Function T
168. it is other than 00 If any value other than is written to NFSR the cycle time does not conform to Equa tion 4 2 refer to 4 1 6 Cycle Time of CUnet Reference Resizing can be performed from any MEM station but cannot be executed from the I O station STECHNICA CO LTD 40 User s Manual 4 4 2 2 Rejection of Resizing At resizing writing to the NFSR is rejected in the following cases 1 The is write protected when the MK Y40 is not in the RUN phase 2 The NFSR is write protected when a value excluding the owned area of a self station is written For example if a self station is set at SA 2 and OWN 5 its owned area range is from 02H to 06H and values more than 06H can be written However values less than 5 exclude the owned area and are rejected The MKY40 avoids contradictions in CUnet operation using these write protection method 4 4 2 3 Resize Overlap RO Any MEM station can perform resizing However when more than one MEM station performs resizing the following two points are prescribed 1 Priority is given to resizing performed first by the MEM station Resizing performed later by the MEM station is ignored 2 If resizing is performed simultaneously priority is given to resizing by the MEM station with the smaller station address Resizing by other MEM stations is ignored The MEM station with ignored resizing changes bit 8 RO
169. l up or pull down resistor and keep a High or Low level not to leave pins open STECHNICA Co LTD MKY40 User s Manual 7 3 7 Use of Timing Notification Signals STB1 STB2 The MKY40 in IO mode outputs an output update strobe signal from the STB1 STroBe 1 pin pin 28 when updating data in general purpose external I O pins 100 to 1031 set to output refer to Fig 7 1 and 7 2 2 Data Updating of Internal Output Pins The STBI pin is usually kept Low and outputs a High level for 2 x TBPS time at the time of output updating Data in general purpose external I O pin 100 Io31 set to output is updated during the output of High level pulses from the STB1 pin refer to 8 2 3 1 STB1 STB2 and Data IO Pin Timing The MKY40 in IO mode outputs an input update strobe signal from the STB2 STroBe 2 pin pin 41 when sampling data in general purpose external I O pins Io0 to Io31 set to input refer to Fig 7 1 and 7 2 1 Sending of Internal Input Pin Data The STB2 pin is usually kept Low and outputs a High level for 2 x TBPS time at the time of input updating Data in general purpose external I O pin 100 to 1031 set to input is sampled during the output of High level pulses from the STB2 pin refer to 8 2 3 1 STB1 STB2 and Data IO Pin Timing Use the STB1 and STB2 pins when the user system has more external additional circuits Leave these pins open when not used 7 3 8 Use of
170. mber Group Not Collect MGNC bit bit 5 Function This bit indicates that an interrupt trigger occurs by the result of MGR gt MFR Resize Complete RC bit bit 6 Function This bit indicates an interrupt trigger occurs when the resizing of a self station requested from other CUnet stations is completed Chapter 5 Register Reference in MEM Mode ST ECHNICA CO LTD Run SToP RSTP bit bit 7 Function This bit indicates that an interrupt trigger occurs when the network stops Run STaRt RSTR bit bit 8 Function This bit indicates that an interrupt trigger occurs when the phase changes to the RUN phase Member Change MC bit bit 9 Function This bit indicates that an interrupt trigger occurs when the number of bits at 1 in the MFR Member Flag Register increases or decreases Link group OK LOK bit bit 10 Function This bit indicates that an interrupt trigger occurs by the result of Link Link group No Good LNG bit bit 11 Function This bit enables an interrupt trigger that occurs by the result of Link NG No Good Break Detect BD bit bit 12 Function This bit indicates that an interrupt trigger occurs when break packets sent from other CUnet stations are received Resize Overlap RO bit bit 13 Function This bit indicates that an interrupt trigger occurs when a resize overlap occurs Ping Receive PR bit bit 14 Function This bit indicates that an i
171. n To cancel the frame option for the system the hardware reset needs to be activated for all CUnet ICs in the system In this case keep the LFS pin of an I O station High Chapter 8 Ratings This chapter describes the ratings of MKY40 8 1 Electrical 8 2 AG Characteristics se ire cti eia FI Den Cox Te Qu p SN V ROS Sad 8 3 Package Dimensions 8 4 Recommended Soldering Conditions 8 5 Recommended Reflow Conditions Chapter 8 Ratings TEP S TECHNICA Co LTD Chapter 8 Ratings This chapter describes the ratings of the MK Y40 8 1 Electrical Ratings Table 8 1 lists the absolute maximum ratings of the MK Y40 Table 8 1 Absolute Maximum Ratings Vss 0 V Parameter Power supply voltage VDD 0 3 to 7 0 V Input voltage Vi Vss 0 3 to VDD 0 3 V Output voltage Vo Vss 0 3 to VDD 0 3 V Peak output current Type E pin lop Peak 12 mA Peak output current Type F pin lop Peak 24 mA Peak output current Type G pin lop Peak 12 6 mA Allowable power dissipation PT 570 mW Operating temperature Topr 40 to 85 C Storage temperature Tstg 55 to 150 For Type E Type F and Type G pins see Figure 2 2 Pin Electri cal Characteristics in Circuit Types in MEM Mode and Fig ure 6 2 Pin Electrical Characteristics in I O Circuit Types in IO Mode Table 8 2 lists the electric
172. nagement of CUnet System 4 41 4 41 Monitoring before Network 51 4 42 4 4 2 Resizing of Cycle Time 4 43 4 4 21 Resizing oen hi 4 44 4 4 2 2 Rejection of 4 46 4 4 2 3 Resize Overlap 4 46 4 4 2 4 Caution when RO 4 47 4 4 3 Detection and Handling of CUnet Station BREAK 4 48 4 4 4 Detection and Handling Of 4 49 4 4 5 Controling and Monitoring Network 4 50 4 4 5 1 ECARE Signal Output 2 4 conc eceedserscurseeacetssveudestendetsuateenaeeeene 4 50 4 4 5 2 MCARE Signal 4 52 4 4 5 3 Signal Output eeeseeeesesseeeeeeeeeeee nennen nn nenne tnn n sina nnn nn nuin 4 53 4 4 6 PING 5 5 4 45425 2 4 22252422 424442 15 11144 444222 4 45641 42414411214404 41
173. nal Output Pins eese 7 8 7 2 5 Data Structure of Owned Memory Block esee 7 9 7 3 Connection lO Mode rrr irren euren os 7 10 7 3 1 Setting ZSA of Station 7 11 7 3 2 Selection of Data Output to Internal Output Pins ZDOSAO to DOSA5 7 12 7 3 3 Input Output Setting of General purpose External I O Pins IOSO to IOS2 HIOSWAP 7 13 7 3 4 Logic Setting of General purpose External I O Pins INVO to INV7 7 14 viii S TECHNICA Co LTD MKY40 User s Manual 7 3 5 Setting of Frame Option _ 5 7 15 7 3 6 Connection of General purpose External I O 7 15 7 3 7 Use of Timing Notification Signals STB1 2 7 16 7 3 8 Use of Signal for Notifying Output Availability of General purpose External I O Pins DOA 7 16 7 3 9 Indicating Output Availability of General purpose External I O Pins DONA 7 17 7 3 10 Clearing Output Level of General purpose External I O Pins CLRH CLRL 7 17 7 3 11 Clearing Output by Watchdog 7 18 7 3 12 Indicating Input Data Sending Status of General purpose External I O Pins MON 7 1
174. nected to the via the 8 bit width data Read GMPW Mors from GM to PWRT bus can use up to 8 bytes of data without PWRC 7 Y knowing that a data hazard has occurred Read 2nd PWRC 6 Y PWRC 5 Data during this Read GMPw 4th period is output from PWRT PWRC 4 Y Read GMPW 5th PWRC 3 Y Read GMPw 6th PWRC 2 Y PWRC 1 PWRC 0 Y Fig 4 8 64 bit Data Read via 8 bit Bus STECHNICA Co LTD MKY40 User s Manual 4 2 2 3 GMPW Write Window Lock Data hazards also occur during writing Fig 4 9 For example when the user CPU connected to the 40 via the 8 bit width data bus writes 1234H writing must be performed twice When the old data is copied to another CUnet station based on the sharing of memory data during the separate writing of 34H and 12H data another CUnet station that reads this data will recognize it as AB34H nonexistent data causing data hazards instead of 1234H or ABCDH Word write by 8 bit bus Word read by 16 bit bus Shared memory 1 2 3 4 11 11 Bit 15 14 13 12 1 10 e 8 v 6 8 4 3 2 1 ABCD ABCD gt Old correct data AB34 Data hazard 1234 1234 o New correct data Passage of time Fig 4 9 Data Hazards during Writing The MKY40 has a window lock to lock writing to the
175. nment It occurs when CUnet station disconnects when trouble with receiving or sending packet occurs due to environ mental problems including external noise or when network has marginal performance Therefore it is possible to identify what caused a dead link except when a CUnet station is disconnected intentionally by the user system Network hardware and environmental quality can be recognized by controlling the occur rence of this dead link the dead link is called When LCARE occurs the MK Y40 outputs pulse signals that go Low for a given time from the LCARE pin regardless of the bit status stored in the LGR described in 4 2 3 3 Link Group Register LGR The occurrence of LCARE can be checked visually by connecting an LED indicator to the pin For details of connecting the LED indicator refer to 3 8 Connecting LED Indication Pins Up to 255 LCARE occurrences are indi d cated by bits 0 to 7 LCCO to LCC7 of Bit 7 6 5 4 3 2 1 0 the Care Counter Register CCR Fig CCR lt recs ec4 teca cc 4 32 LCC of the CCR is held as 255 R R R R R R R RW FFH LCARE occurrences without 4 Number of LCARE occurrences counting more than 256 times When recognizing the number of When 1 is written the number of LCARE occurrences is cleared to 00H LCARE occurrences with the user sys _ tem program read bits 0 to 7
176. nstruction received from another CUnet station 4 4 6 PING Instruction JD Jammer Detect When jammer detected 4 4 4 Detection and Handling of Jammer S TECHNICA CO LTD 40 User s Manual 45 4 Operation of INT1 Pin The operation of the INT1 pin is the same as that of the INTO pin described in 4 5 1 Operation of ZINTO Pin to 4 5 3 Interrupt Factors The register to enable the function of the INT1 pin is INTerrupt 1 Control Register INTICR The register to hold the status of the INT1 pin is INTerrupt 1 Status Register INTISR The INTI pin also has retrigger function The register to specify the timing of the interrupt factors ALM and Data Renewal DR for the pin is Interrupt Timing 1 Control Register IT1CR 4 5 5 Operation of INT2 Pin The operation of the INT2 pin is the same as that of the INTO pin described in 4 5 1 Operation of INTO Pin to 4 5 3 Interrupt Factors However the interrupt factors ALM and DR cannot be used The register to enable the function of the INT2 pin is INTerrupt 2 Control Register INT2CR The register to hold the status of the INT2 pin is INTerrupt 2 Status Register INT2SR The INT2 pin also has a retrigger function The INT2 pin does not have the interrupt factors ALM and DR Therefore there is no register to spec ify their timing 4 5 6 Precautions for Spec
177. nterrupt trigger occurs when the PING instruction is received from other CUnet stations Jammer Detect JD bit bit 15 Function This bit indicates that an interrupt trigger occurs when a jammer is detected STECHNICA CO LTD 40 User s Manual 5 28 INTerrupt 1 Status Register INT1SR Address 32 bit address 460 big amp little 16 bit address 462H big 460 little Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 0 2 2 50 22221 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RAW RW RW RW RW RW RW RW RAW RW RW Functional description This register indicates the interrupt factor generated by the interrupt trigger generaton function of the INT1 pin The bit corresponding to the generated interrupt factor changes to 1 The user system program can determine which interrupt factor triggered an interrupt by reading this register When all the bits of this register go to 0 the INT1 pin returns to keep its High level output To clear a bit indicating 1 of this register to 0 write 1 to the bit writing 0 is ignored Bit description ALarM ALM bit to Jammer Detect JD bit bit O to 15 Function For these bits refer to the explanation of the same bit in 5 27 INTerrupt 0 Status Register INTOSR 5 29 INTerrupt 2 Status Register INT2SR Address 32 bit address 464H big amp little 16 bit address
178. o 1 When all bits of the MESR Mail Error Status Register are cleared to 0 this bit is also cleared to 0 Chapter 5 Register Reference in MEM Mode ST CO LTD 5 21 Mail Send Limit time Register MSLR Address 32 bit address 480H big amp little 16 bit address 482H big 4804 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 R W R R R RW RW RW RW RAW RW RW RW RW RW Functional description This register sets the time out value of mail sending Write the time out value hexadecimal using cycle time as one unit that is defined by the user system to the LMTO to LMT12 LiMit Time bits of this register When bit 14 SEND of MSCR Mail Send Control Register is 1 mail sending is on this register is write protected When a hardware reset is activated 1FFFH is set as the initial value in this register STECHNICA CO LTD 40 User s Manual 5 22 Mail Error Status Register MESR Address 32 bit address 484H big amp little 16 bit address 486H big 484H little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW R R R R R R R R R R R W R W R W R W R W R W Functional description This register indicates the status of a mail sending error that occurred after starting The bit corre sponding to the mail sending error type changes to 1 When any data is written to addresses with bi
179. o bit 14 SEND of the MSCR The 6 7 wm MSB is write protected during mail sending When the MSB is read during mail sending data is set forcibly to Upon completion of mail sending bit 14 SEND returns to 0 The completion of mail sending can be recognized by this bit transition The 40 can output interrupt triggers by the completion of mail sending For details refer to 4 5 Interrupt Trigger Generation Function Check bit 15 ERR of the MSCR after the completion of mail sending If the ERR flag bit is 0 mail sending is completed correctly This assures that the 40 was able to send datasets to the mail receive buffers at a destination station If the ERR flag bit is 1 the user system program needs to refer to 4 3 4 Operation against Mail Sending Error and deal with accordingly When referring to the time required for mail sending time taken from when sending is started until it is completed by the user system program read the Mail Send Result Register MSRR The 40 stores the number of cycles required from when mail sending is started until it is com pleted to the MSRR when mail sending is completed The MSRR holds this value until the next mail sending is completed or a hardware reset is activated Fig 4 25 MSRR RLT7
180. ode ST ECHNICA CO LTD 5 26 INTerrupt 2 Control Register INT2CR Address 32 bit address 458H big amp little 16 bit address 45AH big 458 little Bit 15 14 13 12 1 10 9 8 7 6 5 4 3 2 1 0 wo PR RO tna LOK MC Manc mene ef 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W RW RAW RW RW RW RAW RW RW RW RW RW R R Functional description This register enables the interrupt trigger generating function of the INT2 pin When 1 is written to the bit corresponding to the interrupt source required by the user system of the interrupt sources defined in the bits of the INT2CR the function of the INT2 pin is enabled This register does not have the DR Data Renewal bit and ALM ALarM bit Bit description Mail Receive MR bit to Jammer Detect JD bit bits 2 to 15 Function For these bits refer to the explanation of the same bit in 5 24 INTerrupt 0 Control Regis ter INTOCR STECHNICA CO LTD 40 User s Manual 5 27 INTerrupt 0 Status Register INTOSR Address 32 bit address 45 big amp little 16 bit address 45 big 45 little Bit 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 0 2 2 4 E s 22221 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RAW RW RW RW RW RW RW Functional description This register indicates the interru
181. ode of the MK Y40 Table 6 2 Electrical Ratings IO Mode 8 Negative logic VDD VDD lIOSWAP RXD STB1 TXE 100 TXD lo1 SA0 lo2 SA1 lo3 SA2 lo4 SA3 105 5 4 106 SA5 lo7 DOSAO VDD DOSA1 GND DOSA2 GND DOSA3 GND DOSA4 STB2 DOSA5 108 109 DONA 1010 N C lo11 EXC lo12 BPSO lo13 BPS1 lo14 Xo lo15 Xi VDD o oj jo 4 1 1 gt QO STECHNICA CO LTD 40 User s Manual Figure 6 2 shows the electrical characteristics of pins in the MK Y40 IO mode Type CMOS Level input Type B TTL Level input min 24 V 1 5 V ViL max 0 6 V max 10 pA max 10 liL max 10 A liL max 10 TTL Level input TTL Level input Type C pull up Type D schmitt trigger Vt max 2 4 min typ 1 6 V V max i Vt typ 1 2 V V V lid max min 0 6 Rpu typ 30 liL max AVt min 0 4 min 12 kQ max 75 kQ max 10 HA A liL max 10 Type E CMOS Level output Type F CMOS Level output VoH min 4 4 min VoL max 0 4 VoL max loH max 4 lOH max loL 4 loL max Iz max
182. onnecting the BUS I F to a user CPU and the network I F to a network offers the user equipment as one MEM station in the CUnet Fig 1 1 In this manual a user equipment with the MKY40 in MEM mode is described as a MEM station 7 One MEM station in CUnet User circuit User CPU MEM mode User equipment V Fig 1 1 CUnet Station with MKY40 in MEM Mode MEM Station The CUnet system shown in Figure 1 2 shares memory data between four MEM stations The user CPU in each MEM station communicates with the others simply and rapidly just by read and write access to a Glo bal Memory GM area in the MK Y40 The user CPUs in each MEM station can also use mail send buffer and a mail receive buffer of the MK Y40 to send up to 256 bytes of dataset to a specified MEM station 7 Network Network cable Network I F Network I F Network I F Network I F User CPU User CPU User CPU User CPU User circuit User circuit User circuit User circuit MEM station MEM station MEM station MEM station Fig 1 2 CUnet Connecting Four MEM Stations CO LTD 40 User s Manual 1 2 Features of MEM Mode The MKY40 MEM mode has the following features 1 Can be connected to up to 64 CUnet stations 2 512 bytes of Global Memory GM The memory block size in the CUnet is 8 bytes GM consists of 64 memory blocks 3 Can own multiple memory blocks For example if each
183. ontrol data in general purpose external I O pins 100 to 1031 in detail and display the operating state of the MKY40 in IO mode 1 STB1 STroBe 1 pin pin 28 2 STB2 STroBe 2 pin pin 41 3 DOA Data Out Available pin pin 8 4 DONA Data Out Not Available pin pin 93 5 CLRH pin pin 9 6 CLRL pin pin 10 7 MON pin pin 92 8 PING pin pin 7 Caution Always keep the CLRH pin and CLRL pin unused High fixed when not in use S TECHNICA CO LTD Chapter 7 Operation and Connection in IO Mode 7 3 4 Setting SA of Station Addresses Set the Station Addresses SAs using hexadecimal numbers OOH to 3FH 0 to 63 that use a High level to be input to 85 0 to SA5 pins pins 80 to 85 as 0 and a Low level as 1 The most significant bit is SAS5 pin 85 The 85 0 to SA5 pins are negative logic input pins that are pulled up internally Fig 7 4 When a hardware reset is activated the 40 writes these pin values to the internal Basic Control Regis ter BCR The Station Addresses SAs are not changed even if the setting of these pins is changed when a hardware reset is not activated The MKY40 in IO mode has no pin that sets OWN width If owns one Memory Block MB set by the SA0 to SAS pins Because the SA0 to SA5 pins are negative logic input pins ON bits are 1 When a hardware reset is activated the 5 0 to SA5 values are written to
184. opied to the same address in GM of other CUnet stations 2 The user system program can reference data copied from other CUnet stations by reading the owned area of other CUnet stations in GM 3 The user system program can mail the dataset to a specified CUnet station 4 The user system program can receive the dataset mailed to the self station The CALL phase means the stage in which the CUnet is waiting to be connected Bit 10 CALL of the SCR changes to 1 When all MKY40s except the self station connected to the network are not started they enter this phase The CALL phase is continued until packets can be transmitted and received to and from other CUnet stations The BREAK phase means the stage in which the self station cannot enter a cycle Bit 11 BRK of the SCR changes to 1 The BREAK phase is continued until other CUnet stations perform resizing to permit the self station to enter a cycle In this case refer to 4 1 8 4 Stop Exception 2 to remove the instability Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 1 5 Protection against Misoperation The MKY40 has the following protective functions to prevent misoperation by the user system program Fig 4 3 1 1 can be written to the GMM bit of the SCR only when the START bit of the SCR is 0 2 When the START bit of the SCR System Control Register is 1 any memory area other than the owned area in GM of the self station is
185. or details of the bit transition timing of this register refer to 4 2 3 Quality Assurance of GM Data The bit status of this register freezes during the output of ALM ALarM MC Member Change LOK Link group OK and LNG Link group No Good interrupt triggers For details refer to 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation 5 ECHNICA CO LTD Chapter 5 Register Reference in MEM Mode T 5 9 Link Group Register LGR Address 32 bit address 438H big amp little 16 bit address 43AH big 438 little 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RAW RW RW Bit Address 32 bit address 43AH big amp little 16 bit address 438H big 43AH little 15 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RW RW RW RW RW RW RAW RW RW Bit Address 32 bit address 43CH big amp little 16 bit address 43EH big 43 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR LGR 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Initial value 0
186. ored 4 Register addresses differ depending on the data bus width access width such as 8 bit access in 16 bit wide data bus and endian type of user CPU connected to the MKY40 in MEM mode Accesses not mentioned in this chapter such as 8 bit access require address conversion before use BCR 16 bit access Bt 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address 49AH big 498H little 8 bit access pit 7 6 5 4 3 2 1 017 6 5 4 3 2 4 o Address 49AH big 499H little 49BH big 498H little Fig 5 1 Addresses for 8 bit Access 16 bit Register DRCR LSB srToo zo s er s 26 22 2423 17 sese 4 a 12 T9 8 7 8T 4 3 2 5 8 bit access 430H big 433H little 431H big 432 little 432H big 431H little 433H big 430H little 16 bit access 430H big 432H little 432H big 430H little 32 bit access 430H big amp little DRCR LSB Bit 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 83 32 8 bit access 434H big 437H little 435H big 436H little 436H big 435H little 437H big 434H little 16 bit access 434H big 436H little 436H big 434H little 32 bit access 434H big amp little Fig 5 2 Addresses for Access 64 bit Register STECHNICA CO LTD 40 User s Manual Table 5 1 Register List Ao Starting Section Abbreviation Register name address
187. ored in these bits The occurrence count hexadecimal is counted by these bits When the occurrence count is counted up to FFR the value is kept The count values of these bits can be cleared to OOH by writing 1 to the MCCO bit bit 8 ST ECHNICA CO LTD 40 User s Manual 5 33 Query Control Register QCR Address 32 bit address 474H big amp little 16 bit address 476H big 474H little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R RW RW RW RW RW Functional description This register controls the PING function and the function query to detect other CUnet station modes Bit description Target Station TSO to TS5 bit bits O to 5 Function These bits set the station addresses of PING and query Try Query TQ bit bit 6 Function This bit performs querying When 1 is written to this bit queries are made for CUnet stations at the station addresses set to the TSO to TS5 bits This bit is reset to 0 after completion of querying If there is no tar get CUnet station this bit remains 1 If this bit is not reset to 0 even after the elapse of several time cycles write 0 to this bit to terminate querying Writing of such data that both this bit and PING bit go to 1 is protected PING PING bit bit 7 Function This bit issues the PING instruction When 1 is written to this bit the PI
188. ormance is calculated as follows at 12 Mbps TBPS 83 3 ns with 64 CUnet stations cycle time 2 365 ms at a driving clock accuracy of 200 ppm 0 02 and a total length of cable 7 ns m of 100 m 167 ns 473 ns 700 ns 1 34 us max Caution This equation cannot be used when a HUB is inserted into a network ning on a user CPU to recognize the cycle timing refer to 4 1 7 Detailed Timing during Cycle and 4 5 Interrupt Trigger Generation Function However in this case the timing accuracy depends on the program running status By comparison the output of the STB pin serves many uses mainly in supplying high accuracy synchronization signals to peripheral user circuits 3 10 Connecting PING Signal The MKY40 has a PING pin pin 7 to notify reception of the PING instruction from another CUnet station The PING signal is operated by another CUnet station regardless of the self station state The PING pin is usually kept Low The PING pin changes to High at receipt of the PING instruction from another CUnet station The pin then changes to Low at receipt of packets from another CUnet station that do not contain the PING instruction When a hardware reset is activated the PING pin changes to Low in preference to the above operation The CUnet protocol does not define why to use and where to connect the PING signal The PING signal is an auxiliary expanded function to support creation of a user application For
189. pt factor generated by the interrupt trigger generation function of the INTO pin A bit corresponding to the generated interrupt factor changes to 1 The user system program can determine which interrupt factor triggered an interrupt by reading this register When all the bits of this register go to 0 the INTO pin returns to keep its High level output To clear a bit indicating 1 of this register to 0 write 1 to the bit writing 0 is ignored Bit description ALarM ALM bit bit 0 Function This bit indicates that an interrupt trigger occurs when the station time during cycles reaches the time prespecified to the ITOCR Interrupt Timing 0 Control Register Data Renewal DR bit bit 1 Function This bit indicates that an interrupt trigger occurs when the data transition of the Memory Block MB corresponding to the detection bit preset to the DRCR Data Renewal Check Register is detected at the time prespecified to the ITOCR Interrupt Timing 0 Control Regis ter Mail Receive MR bit bit 2 Function This bit indicates that an interrupt trigger occurs when mail reception is completed Mail Send Finish MSF bit bit 3 Function This bit indicates that an interrupt trigger occurs when mail sending is terminated correctly or incorrectly Member Group Not Equal MGNE bit bit 4 Function This bit indicates that an interrupt trigger occurs by the result of MGR MFR Me
190. pt triggers are detected when MB data for bit at 1 of those in DRCR changes Bit DRFR Bit 3 0 gt 1 DRFR Bit 0 to 63 1 5 0 EEE GM yg DRCR Su AAAAH 0 T 0 1 011 CCCCH 2 12 5555H 3 1 3 Passage of time we Cleared at this point DRFR Bit 0 0 gt 1 1 DR q Ly o Qn 4 DR When DR interrupt triggers are detected user processing must be performed during this period DR A When Data renewal DR interrupt function used Write by packet reception Station time 40H 64 AAAAH GM DRCR BBBBH 110 N BBBBH 1 0 1 N CCCCH 2 112 My DDDDH 3 113 4 114 5 15 ITOCR or IT1CR 0040H Interrupt triggers occur at this point ABCDH OM PRES BBBBH N BBBBH 4 0 1 CCCCH 2 112 Write by packet reception 5555H 3 3 4 114 Passage of time The status detected during freezing is reflected For example when data transition in MB 0 is detected bit O of DRFR and DR returns to 1 Bit DR interrupt triggers are detected when MB data for bit at 1 of those in DRCR changes DRFR Bit 3 0 gt 1 DR and DRFR freeze during occurrence of DR interrupt triggers Note that GM data does not freeze Cancellation of
191. r Fig 4 15 a MFR Bit 63 62 16 15 14 113112111 1009 8 716 5 43121110 If the link flag is 1 for three consecutive cycles the bit of the target CUnet station goes to 1 If the link flag is for three consecutive cycles the bit of the target CUnet station goes to 0 MGR Bit 63 62 16 15 14 13 12 11 10 o 7 e 5 4 3 2 1 0 This register writes 1 to the target bit for monitoring the MFR Fig 4 15 64 bit MFR and MGR STECHNICA CO LTD 40 User s Manual 4 2 3 5 Member Flag Register MFR In the Member Flag Register MFR like the Link Flag Register LFR bit 0 corresponds to the CUnet sta tion with the Station Address SA 0 bit 1 to the CUnet station with SA 1 and bit 63 to the CUnet sta tion with SA 63 In the MFR flag bit like the LFR flag the lead point of the Station Time ST matching the Station Address SA is the starting point of status management When the MER flag bit recognizes Link established consecutively three times at the starting point of sta tus management it changes to 1 Conversely when the MFR flag bit recognizes Link unestablished con secutively three times at the starting point of status management in the CUnet station where the MFR is 1 it changes to 0 This method pro
192. r DRFR bits described in 4 2 4 3 Transition Timing of DR Flag Bit and DRFR Bits from 1 to 0 The time set at bits 8 to 14 of the when the INTOCR is enabled and the time set at bits 8 to 14 of the ITICR when the INTICR is enabled However when DRs of the INTOCR and INTICR are disabled the timing of bit 11 of the SSR and DRFR bits changing from 1 to 0 is the time set at bits 8 to 14 of the ITOCR 4 5 8 Register Freezing in Synchronization with Interrupt Trigger Generation The MKY40 freezes specific registers while outputting specific interrupt triggers Freezing registers prevents specific registers related to interrupt factors from being updated after interrupt triggers are output from the MK Y40 and before processing is referenced by the interrupt handling program of the user system Frozen registers are duplicated within the 40 and only the part that can be read from the user system is frozen Therefore when the status of specific interrupt triggers is cleared at comple tion of processing by the interrupt handling program of the user system the registers are immediately unfro zen and return their current status Table 4 4 lists the correspondence between frozen registers and interrupt factors Table 4 4 Frozen Registers Interrupt factor Frozen register and flag bit ALM ALarM 1 All bits of RFR MC Member Change All bits of LER LOK Link group Bit 12 LOK of SSR LNG Link group No
193. r 5 Register Reference in MEM Mode 5 1 Chip Code Register COH iei tereti eorr eter tacit eet 5 5 5 2 Basic Control Register BCR 11e ceres ee eee eee eee ne enne nnne nnn 5 6 5 3 System Control Register SCR 5 8 5 4 System Status Register SSR cccccessseeeeeeeeeeessseeeeeeeeeenseeeeeeeeeeeeseeeeeeseeneeees 5 10 5 5 Final Station Register 5 5 12 5 6 New Final Station Register enne 5 12 5 7 Receive Flag Register 5 13 5 8 Link Flag Redister EFH anta tk ru CE Ceca 5 14 59 Link Group Register amp trece rete rene Speer tende reete reno cues 5 15 5 10 Member Flag Register 5 16 5 11 Member Group Register 5 17 vii S TECHNICA 40 User s Manual 5 12 Data Renewal Check Register
194. r MRICR is 1 bit 6 MR Mail Received of the SSR System Status Register also goes to 1 The MR bit of the SSR is a flag bit where the Logical sum between the RCV bits of the MROCR and 1 is indicated The user system program can recognize mail reception by recognizing the MR bit of the SSR without recognizing the RCV bits of MROCR and MRICR individu ally For details of the function to output interrupt triggers when dataset is stored in the MRBO or MRB refer to 4 5 Interrupt Trigger Generation Function Caution 1 When the user system program reads the MROCR or MRICR that are the targets of the operations 1 to 4 in 4 3 2 while the MK Y40 internally receives mail the bit sta tus being transiting may be read When the user system program detects RCV flag of the MROCR or MRICR transits to 1 read the MROCR or MRICR again after 20 ns go by and use the got values When the user system program detects mail reception by bit 6 MR of the SSR or by interrupt trigger generation function which does not apply to 2 The RDY bit of the MROCR or MRICR in the MK Y40 can be operated when the RUN bit of the SCR is 1 The RCV flag and the RDY bit of the MROCR or MRICR tran sits to 0 automatically when the RUN bit of the SCR bit bit 9 transits to 0 S TECHNICA Co LTD MKY40 User s Manual 4 3 3 Operation for Mail Sending and after Completion of Sendin
195. responding to the detection bit preset to the DRCR Data Renewal Check Register is detected at the time prespecified to the ITOCR Interrupt Timing 0 Control Register When the same bit value of the INTICR INTerrrupt 1 Control Register is 1 writing 1 to this bit is protected Mail Receive MR bit bit 2 Function This bit enables interrupt trigger occurrence when mail reception is completed Mail Send Finish MSF bit bit 3 Function This bit enables interrupt trigger occurrence when mail sending is terminated correctly or incorrectly Member Group Not Equal MGNE bit bit 4 Function This bit enables interrupt trigger occurrence by the result of MGR MFR Member Group Not Collect MGNC bit bit 5 Function This bit enables interrupt trigger occurrence by the result of MGR gt MFR Resize Complete RC bit bit 6 Function This bit enables interrupt trigger occurrence when the resizing of a self station requested from other CUnet stations is completed Run SToP RSTP bit bit 7 Function This bit enables interrupt trigger occurrence when the network stops Chapter 5 Register Reference in MEM Mode ST CO LTD Run STaRt RSTR bit bit 8 Function This bit enables interrupt trigger occurrence when the phase changes to the RUN phase Member Change MC bit bit 9 Function This bit enables interrupt trigger occurrence when the number of bits at 1
196. rformance is not guaranteed Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD 3 6 Setting Station Addresses The MKY40 has six pins SA0 to SA5 pins 80 to 85 to set Station Addresses SA defined by the CUnet protocol The to 4SA5 pins negative logic input pins that are pulled up internally The SAs are given in hexadecimal as OOH to addresses 0 to 63 with a High level input to the 85 0 to SAS5 pins set to 0 and a Low level set to 1 The most significant bit is SA5 pin 85 Fig 3 8 When a hardware reset is activated the MK Y40 writes the pin settings to the BCR The SA can be reset by rewriting data of the BCR by the user system program For details refer to 4 1 3 Initialization and Start up of Communication 7 MM MU ME E MKY40 Due to the negative logic the ON bit is written as 1 to BCR If the user system program sets the BCR before starting the network the dashed part does not have to be implemented M Fig 3 8 Example of Station Address Setting Reference The SA0 to 55 5 pins can be fixed at any level regardless of the SA values only when the user system program writes the SA values to the BCR before starting the MK Y40 network This helps reduce component such DIP SW In this case leave the SAO to SA5 pins open or keep High or Low The SAO to SA5 pins are connected pull up resistor in the MKY40 Leavin
197. rigger Generation Timing 4 63 Fig 4 43 Operation Example of Retrigger 4 64 Fig 5 1 Addresses for 8 bit Access 16 bit Register 5 3 Fig 5 2 Addresses for Access 64 bit Register uusus 5 3 Fig 6 1 Pin Assignment in IO 6 3 Fig 6 2 Pin Electrical Characteristics Circuit Types in IO Mode 6 8 xi S TECHNICA CORD MKY40 User s Manual Fig 7 1 Internal Configuration of MKY40 in IO Mode 7 4 Fig 7 2 Internal Configuration of Multi selector for One lo Pin 7 6 Fig 7 3 Selection of Data Output to Internal Output Pins 7 8 Fig 7 4 Setting Example of Station Addresses Mode 7 11 Fig 7 5 Setting Example of ZDOSAO to DOSAS5 Pins and DOHL Pin in IO Mode irrito 7 12 Fig 7 6 Input Output Setting Example of General purpose External I O Pins 7 13 Fig 7 7 Example of Logic Setting of General purpose External I O Pins 7 14 Fig 7 8 Example of LED Connection to DONA Pin 7 17 Fig 7 9 Example of Clearing Output by Watchdog 7 18
198. s Table 3 1 Network Cable Length Network cable length The recommended differential driver receiver is an RS 485 based driver receiver Therefore the branch count 32 stipulated in the RS 485 specification is used as a guide in Table 3 1 Up to 64 CUnet stations can be connected to the CUnet enabling connection of 64 branches This recom mended network is isolated electrically by a pulse transformer and the format of signals propagated through the network is RZ Return to Zero Consequently 64 branches can be connected using a standard RS 485 based driver receiver without using DC component signals In this case the cable length is likely to be shorter than the value in Table 3 1 due to increase of dispersion of propagated signal energy Before using a CUnet perform function tests in the use environment and confirm that CUnet operation is stable without LCARE Link CARE and MCARE Member CARE described in 4 4 5 Controling and Monitoring Network Quality Reference Network cable length can be extended by setting the frame option or adding HUB s For I detail refer to 4 4 10 Frame Option for and User s Manual for HUB IC MKYO02 Caution The network cable length varies depending on the cable quality differential driver receiver components cable connection status and environment Therefore values in Table 3 1 Network Cable Length are only a guide and pe
199. s 5 to 7 TBPS time Long Frame Select LFS bit bit 15 Function The frame option of the MK Y40 is set to this bit When 1 is written to this bit the frame option is set Only 1 can be written to this bit To set this bit value to 0 activate a hardware reset For details on the frame option refer to 4 4 10 Frame Option for HUB Caution When pins of OWNO to OWNS are all Low and when a hardware reset is activated OWNO bit is set to 1 automatically When 0 is written to all bits of OWNO to OWN5 OWNO bit is set to 1 S TECHNICA Co LTD MKY40 User s Manual 5 3 System Control Register SCR Address 32 bit address 44CH big amp little 16 bit address 44EH big 44 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 uF snr CALL RUN START sts sta srs ste sti 80 o o 0o rip 0o 0 0 0 18 R W R W R R R R R R R W R R R R R R R R Functional description This register controls a CUnet network Bit description Station Time STO to ST6 bit bits O to 6 Function The station time is set to these bits The current station time hexadecimal is set The bit values change dynamically as a cycle passes through For details of the station time refer to 4 1 7 Detailed Timing during Cycle and CUnet Introduction Guide START START bit bit 8 Function This b
200. s for data to be output to 100 to 1031 pins set to output by setting of IOSO to IOS2 pins The lower bits are selected when this pin is High and the upper bits are selected when the pin is Low Negative Input pins to reverse internal logic and pin levels of IoO to Io31 pins 131020 Positive When these pins are Low the IoO to Io31 pins at internal logic 1 are High When these pins are High the Io0 to Io31 pins at internal logic 0 are High Input pins to set 100 to Io31 pins to input or output 21 to 23 Positive 100 to 1031 pins are set to input or output by combining High and Low level inputs to these pins IOSO to 1082 Input pin for 40 hardware reset Immediately after power on or when the user intentionally resets hardware keep this pin Low for 10 or more clocks of the fre quency of the Xi pin Usually keep this pin High Negative Continue Chapter 6 Hardware in IO Mode TEC HNICA CO LTD Table 6 1 Pin Functions in IO Mode Continued Input pin to reverse input or output status of 100 to 1031 pins determined by setting of IOSO to IOS2 pins The status is not reversed when this bit is High When this pin is Low the status of IoO to 1031 pins determined by the setting of IOSO to IOS2 pins is reversed from input to out put and from output to input IOSWAP Negative Output pin to notify when to update data in Io0 to Io31 pins
201. s permitted to receive mail When this bit is 0 the MRB1 is inhibited from receiving mail This bit value cannot be set from 1 to 0 during mail reception by the MRB1 Therefore when 0 is written read this bit to check its status When 1 is written to this bit the RCV bit is forcibly set to 0 If the RUN bit of the SCR changes to 0 when this bit is 1 this bit also changes to 0 ReCeiVed RCV bit bit 7 Function This bit indicates the completion of mail reception This bit changes to 1 at completion of mail reception The RDY bit bit 6 changes to 0 when this bit goes to 1 When 1 is written to the RDY bit this bit 15 set to 0 This bit can be forcibly set to 0 by writing 0 directly to it instead of writing 1 to the RDY bit If the RUN bit of the SCR changes to 0 when this bit is 1 this bit also changes to 0 SouRCe station address SRCO to SRC5 bit bits 8 to 13 Function The source station addresses hexadecimal are set to these bits when dataset is stored in the Mail Receive Buffer 1 STECHNICA CO LTD 40 User s Manual 5 20 Mail Send Control Register MSCR Address 32 bit address 47 big amp little 16 bit address 47EH big 47 little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R RW RW RW RW RW RW R R RW RW RW RW Functional description
202. ser CPU to the A2 to A10 pins pins 13 to 21 of the 40 Connect the data bus signal pins DO to D7 of the user CPU to the DO to D7 pins pins 29 to 36 Connect the RD signal output from the user CPU to the RD pin pin 23 Connect the write strobe output from the user CPU to the WRLL pin pin 27 Connect the signal to arrange the MKY40 in memory to the CS pin pin 22 If the data bus signal pins DO to D7 of the user CPU enter the open floating state when all periph eral devices including the MK Y40 do not drive the data bus connect a pull up or pull down resistor The hardware designer should select an appropriate resistance value The D8 to D31 pins pins 42 to 49 pins 53 to 60 pins 64 to 71 of the 40 are unused They should be prevented from entering the open floating state Usually connect them to GND The precautions for connection between the MKY40 and the 8 bit wide user CPU are as follows 1 For sufficient access time between the user CPU and the MKY40 described in 3 12 5 Designing Access Time adjust the operation timing of the user CPU if necessary by adding a WAIT gener ating circuit 2 Check the level of signals connected to the user CPU by referring to the electrical characteristics of pins described in Chapter 2 Hardware in MEM Mode 3 When connecting interrupt trigger signals from the 40 to the user CPU refer to 3 12 8 Con nection of Interrupt Trigger Signals Chapter
203. set to output by setting of IOSO to IOS2 pins This pin usually outputs a Low level and a High level for a given time at updating data Positive 100 0107 291036 M 32 bit general purpose external I O pins 108 to 1015 42 to 49 Positive 1016 to lo23 53 to 60 Negative 1024 1031 641071 INV7 pins Positive or negative logic depends on the setting of the INVO to Output pin to notify when to internally write data in 100 to Io31 pins set to input by setting of IOSO to IOS2 pins This pin usually outputs a Low level and a High level for a prede termined time when writing data internally Positive Input pin to input packets Positive 2 Connect this pin to the receiver output pin Output pin to output High level during outputting packets to be Positive sent Connect this pin to the enable input pin of a driver Output pin to output packets to be sent TXD Positi is pi ive i i i Connect this pin to the drive input pin of a river Input pin to set station addresses SAs 80 to 85 Negative When a hardware reset is activated the MKY40 writes the inverted state of this pin into the internal BCR SAO0 to SA5 Input pins to select Memory Block MB to output to Io0 to Io31 DOSA0 to EN Negative pins set to output by setting of IOSO to IOS2 pins DOSA5 Set the MB numbers to as 6 bit negative logic binary values 3FH to OOH Output pin for lighting LED to
204. ss SAO to 5 5 bit bits 0 to 5 Function The Station Addresses SAs are set to these bits When a hardware reset is activated the input values of SAO to SA5 pins pins 80 to 85 are set at these bits The bit values can be changed by writing BPS 50 1 bit bits 6 7 Function The baud rates are set to these bits When a hardware reset is activated the input values of BPSO and 51 pins pins 96 and 97 are set at these bits The bit values can be changed by writing Table 5 2 shows the relationship between bit values and baud rates Table 5 2 Bit Values and Baud Rates for 48 MHz Clock Bit 7 BPS1 Bit 6 BPSO 12 Mbps 6 Mbps 3 Mbps EXC input clock x 1 4 OWN width OWNO to OWNS bit bits 8 to 13 Function The block count of owned width OWN width are set to these bits When a hardware reset is activated the input values of OWNOto OWNS pins pins 86 to 91 are set at these bits The bit values can be changed by writing Chapter 5 Register Reference in MEM Mode ST CO LTD Care Pulse CP bit bit 14 Function A pulse width to be output to LCARE and MCARE pins pins 93 and 94 is set to this bit When 0 is written to this bit the pulse width is the time generated by a retriggerable one shot multivibrator with a minimum time of 2096896 x TXT This pulse signal can be seen by driving an LED When 1 is written to this bit the pulse width i
205. station reads datasets during the writing of the datasets such as character strings across addresses character strings with written data and old data mixed may be read This phenomenon is called data hazards Data hazards do not occur when handling data within the width of the bus connecting the user CPU and 40 When handling data that is wider than the width of the bus connecting the user CPU and MKYAO the fol lowing data hazards occur Fig 4 7 1 When the user CPU connected to the MK Y40 via the 8 bit width data bus reads 16 bit width data from the area in GM owned by the CUnet station access must be made twice 2 When data changes with data copying from another CUnet station based on the sharing of memory data between the user system program s first and second accesses to GM timing problems disable reading of correct data 5634H read in Fig 4 7 3 In this case the read data is erroneous data where data hazards occurred Word write by 16 bit bus Word read by 8 bit bus E Shared memory 15 14 1 3 12 11 10 9 7 6 5 4 2 1 CCPHINNS m write 1 2 3 4 Correct data 1 1 ee EUR 15 14 13 12 11 10 e 8 6 5 4 s 2 1 o 1234 es es 5678 Passage of time Ne 2 Fig 4 7 Mechanism of Data Hazard The MKY40 has a window lock to preven
206. t 54 Bit53 Bit 52 Bit 51 Bit50 Bit 49 Bit 48 INV4 INV3 S TECHNICA Co LTD MKY40 User s Manual 7 3 Connection in IO Mode This section describes the connection of the MK Y40 set in IO mode The items and pin connections in Table 7 4 are the same as those in MEM mode For the connections in Table 7 4 refer to the MEM mode description Table 7 4 Same Connections in MEM Mode Description in MEM mode Related pin Xi XO TXD RST Hardware reset 3 2 Hardware Reset Xi RST RXD TXE TXD BPS1 BPSO EXC Communication cable length 3 5 Network Cable Length Driving clock connection 3 1 Driving Clock Network interface connection 3 3 Connecting Network Interface Setting baud rate 3 4 Setting Baud Rate When using the MKY40 in IO mode connect the following pins in addition to the items in Table 7 4 1 5 to SA5 Station Address 0 to 5 pins pins 80 to 85 2 5 to DOSAS Data Out Station Address 0 to 5 pins pins 86 to 91 3 DOHL Data Out High or Low pin pin 12 4 IOSO to IOS2 IO Select 0 to 2 pins pins 21 to 23 5 SIOSWAP pin pin 27 6 INVO to INV7 INVert 0 to 7 pins pins 13 to 20 7 LFS Long Frame Select pin pin 11 8 IoO to Io31 General purpose external I O pins pins 29 to 36 42 to 49 53 to 60 64 to 71 Using the following pins enables the user system circuit designer to c
207. t data hazards that occur when handling data exceeding the bus width Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 2 2 1 Window Lock Addresses 000H to 1FFH shown in the memory map of the MKY40 are the Global Memory Primary Window GMPW to access GM from the user CPU The window lock primarily locks the GMPW 4 2 2 2 GMPW Read Window Lock The MKY40 has a Primary Window Read Control Register PWRCR to set a read count to lock the GMPW An example of locking the GMPW primarily for read access locking during two read accesses is shown below 1 Write the read count 02H to lock the GMPW to bits 0 to 3 ACO to AC3 of the PWRCR 2 Perform the first read access from the GMPW One 8 byte memory block of data is all saved in the Primary Window Read Temporarily PWRT in the MKY40 The PWRCR count is decremented by 1 to 01H 3 Perform the second read access from the GMPW In this case the data saved in the PWRT is output to the data bus for transfer to the user CPU The PWRCR count is decremented by 1 to OOH This unlocks the GMPW The user CPU obtains correct data at the first reading The PWRCR write up to 8 count values 1 Read 64 bit data Fig 4 8 because the PWRT in the MK Y40 corresponds to the size 8 bytes of one mem Y Write 8 to PWRCR ory block Consequently the user CPU con d he MKY40 via the 8 bit width d Y Data transferred
208. t is written as to BCR If the user system program sets the BCR before starting the network the dashed part does not have to be implemented M Fig 3 9 Example of Owned Area Setting Reference The 4OWNO to OWNS pins can be fixed at any level regardless of the OWN width values phate ant ar only when the user system program writes the OWN width values to the BCR before start ing the MKY40 network This helps reduce component such DIP SW In this case leave the OWNO to OWNS pins open or keep High or Low The 4OWNO to OWNS pins are connected pull up resistor in the MKY40 Leaving these pins open is comparable to keeping them High Chapter 3 Connections in MEM Mode 3 8 Connecting LED Indication Pins The MKY40 has three output pins for LED indication MON pin 92 LCARE pin 93 and MCARE pin 94 each of which outputs active Low signals active at Low level These pins can drive a current of 8 mA If LEDs can be turned on at a current of 8 mA or less they can be con nected to go on at a Low level Fig 3 10 The user sys tem hardware designer should determine the value of each current limiting resistor R in Figure 3 10 accord ing to the LED ratings The green LED indicating stable operation should be connected to the MON pin and the orange LED indicat 2 S TECHNICA CO LTD MKY40 510 approx 8 mA 5 0 V 5 0 V LCARE p LED Orange 5 0 V LED Red
209. tasets using the mail send buffer and mail receive buffer Function STECHNICA CO LTD 40 User s Manual 4 1 4 Responses to Each Phase The MKYAO changes to any of the CALL phase RUN phase or BREAK phase in 2 or 3 cycles in the START phase after the network is started in accordance with the phase transition defined in the CUnet pro tocol Each phase of the MK Y40 indicated by RUN CALL and BRK bits of the SCR System Control Register can be recognized by reading the SCR using the user system program Fig 4 2 2 3 Cycle times Cycle not ra CALL phase Bit 11 10 9 8 SCR 2 CALL START E Resizing of Final SA 2 R W R R R RW Self SA detected New entry of station RUN phase Cycle of Final SA lt Self SA detected START phase Cycle of Final 5 2 Self SA or CUnet station detected in CALL phase BREAK phase 1 Bit corresponding to phase goes to 1 Three bits are 0 while MKY40 is in Start phase Start instruction bit Fig 4 2 Phase Transition of MKY40 and Corresponding Bits of SCR The RUN phase means the stage in which the CUnet operates normally Bit 9 RUN of the SCR changes to 1 When the MKYAO is in the RUN phase the user system program can use the following communica tions 1 When data transferred to other CUnet stations is written to the owned area of the self station in Glo bal Memory GM the data is c
210. tation Address SA of the PING signal to bits 0 to 5 Target Station TSO to TS5 of the Query Control Register QCR and 1 to bit 7 PING 2 When the PING instruction is issued to a network bit 7 PING returns to 0 C N Bit 7 6 5 4 3 2 4 0 Pme rss 154 153 152 151 Tso Rw RW RW RW RW RW RW RW Po Write the destination SA where the PING instruction is issued to Write 1 when issuing the PING instruction When 1 is written to both bits 7 and 6 writing is disabled When the PING instruction is issued to a network bit 7 returns to Fig 4 36 Issuing PING Instruction Caution The PING instruction can also be issued even to the SA of a CUnet station that does not exist on the network However the transition of the target PING pin output to High level is not guaranteed Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 4 7 Function to Detect Mode of Each Station Operating the QCR of the MKY40 enables the user system to recognize the current mode of each CUnet sta tion corresponding to SAs based on the type codes shown in Table 4 2 To check the mode of other CUnet station connected to a network proceed as follows Fig 4 37 1 Write the target station addresses to bits 0 to 5 Target Station TSO to TS5 of the QCR and 1 to bit 6 TQ Try Query 2 At completion of checking bit 6 TQ returns to 0
211. ter Reference in MEM Mode T 5 11 Member Group Register MGR Address 32 bit address 440H big amp little 16 bit address 442H big 440 little 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RW RW RW RAW RW RW RW RAW RW RW Bit Address 32 bit address 440H big amp little 16 bit address 440H big 442 little 15 31 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RAW RW RW RW RW RW RW RW RW RAW RW RW Bit Address 32 bit address 444H big amp little 16 bit address 446H big 4444 little 15 47 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RW RW RW RAW RW RW RW RAW RW RW RW RW RAW RW RW Bit Address 32 bit address 444H big amp little 16 bit address 444 big 446 little 15 63 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR MGR 62 61 60
212. ter are decremented at every read access to the GMPW after they are written If a value other than is stored this register is write protected 5 15 Primary Window Write Control Register PWWCR Address 32 bit address 404H big amp little 16 bit address 406H big 404d little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R RW RW RW RW Functional description This register executes the write window lock function that freezes a GMPW Global Memory Pri mary Window primarily until a specified number of write accesses are completed when writing data to Global Memory GM via the GMPW A hexadecimal write access count of less than 08H can be written to the to ACO Access Count bits of this register When a value of more than 08H is written to this register 8 is forcibly set The values stored in this register are decremented at every write access to the GMPW after they are written If a value other than is stored this register is write protected Chapter 5 Register Reference in MEM Mode ST CO LTD 5 16 Secondary Window Read Control Register SWRCR Address 32 bit address 408H big amp little 16 bit address 40AH big 408 little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R R R R RW RW RW RW Functional description This register executes the read window lock function th
213. the MKYAO in IO mode a network is started immediately after a hardware reset is released from being acti vated the user system needs not start the network The MKY40 in IO mode changes to any of the CALL RUN and BREAK phases after two or three cycle times in the START phase when a network is started 7 41 Operation in RUN Phase The RUN phase is a normal operating state of a CUnet A link with other CUnet stations connected to a net work is performed constantly Regarding the state where a link defined in the CUnet protocol is consecutively established three or more times as a link with other CUnet stations being stable MK Y40 outputs a Low level to the MON pin When the MK Y40 in IO mode is in the RUN phase packets are periodically sent to send the setting state of and data in internal input pins 010 to Di31 to a network after the MON pin changes to Low level When CUnet stations at station addresses matching the setting of DOSAO to 1DOSAS pins exist among the other linked CUnet stations the MK Y40 in IO mode outputs pulses from the STBI pin and updates data in internal output pins Do0 to Do31 In this case the standard state of an I O station has the following features 1 The MON pin changes to a Low level 2 The DOA pin changes to a High level and the DONA pin changes to a Low level 3 The STBI pin outputs periodically pulses synchronized with a cycle 4 The STB2 pin outputs periodically pulses synchronize
214. the CUnet station with the station address corre sponding to that bit is operating on the network Caution When other CUnet stations are not in operation the ST that can be obtained in 2 above is in the free running state and is not synchronized with other CUnet stations Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 4 2 Resizing of Cycle Time The MKY40 can perform resizing defined in Increased Practicality in the CUnet protocol In a CUnet consisting of the MKY40 with the CUnet protocol the initial value of a Final Station FS is 63 Resizing is useful when 64 frames are not needed in the user system For example in a user system using only two MEM stations with SA 0 and SA 1 a large network is not in use during the Station Time ST with SA 2 to 63 constituting a cycle In this case changing the FS value to 1 provides the most efficient cycle For example in operation at 12 Mbps the response time of memory data sharing increases from 2 365 ms to 102 us Fig 4 27 FS 63 Cycle time 2 365 ms 12 Mbps ST 64 ST 65 ST Ost 1 FS 1 01h Cycle time 102 us 12 Mbps Resizing Fig 4 27 Resize S TECHNICA Co LTD 4 4 2 1 Resizing MKY40 User s Manual Resizing is performed when the user system program writes a new Final Station FS value to the New Final Station Register NFSR It may be affected by reject
215. the DR of the INTICR is 1 Refer to the generation timing of data renewal interrupt described in 4 5 6 Precautions for Specifying Timing of Interrupt Trigger Generation and 4 5 7 Precautions for Use of Data Renewal DR Interrupt Triggers However if the data renewal interrupt triggers described in 4 5 Interrupt Trigger Generation Function is activated bit 11 DR and the DRFR bits freeze remain unchanged without changing to 0 When the generation of data renewal interrupt triggers is cancelled by the user register opera tion the status is reflected in the DRFR For details refer to 4 5 8 Register Freezing in Synchro nization with Interrupt Trigger Generation When bit 15 of the SCR System Control Register described in 4 4 9 Global Memory Monitor GMM Function is 1 bit 11 DR and DRFR bits change from 1 to 0 at the lead point of the cycle cycle time 0 This occurs due to the non existence of the self station time of the MKY40 used as the GMM S TECHNICA Co LTD Ms MKY40 User s Manual When Data renewal DR interrupt function not used Write by packet reception Station time 40H 64 Write by packet reception AAAAH GM DRCR BBBBH xN AAAAH 0 1 0 CCCCH N BBBBH 1 011 Ra CCCCH 2 112 DDDDH 1 3 EEEEH 4 114 5 15 ITOCR or IT1CR 0040H DR interru
216. the operation timing of the user CPU if necessary by adding a WAIT gener ating circuit Check the level of signals connected to the user CPU by referring to the electrical characteristics of pins described in Chapter 2 Hardware in MEM Mode When connecting interrupt trigger signals from the MKY40 to the user CPU refer to 3 12 8 Con nection of Interrupt Trigger Signals Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD User CPU A2 to A10 TEI G A2 to A10 17 18 19 20 21 Network I F circuit Clock input pin used as the baud rate depends on the external clock 29 to 36 Should be fixed Hi or Lo level when external clock not used 42 to 49 DO to D31 E E DO to D31 Connection of LED 92 Green LCARE eee Orange p 0 Red Driving clock 48 MHz of MKY40 24 Hardware reset of MKY40 Requiring Xi of 10 or more clocks when Low Interrupt input 80to85 Setting of station addresses 5 0 V S wBO SA0 to SA5 5 0 V wet 2 H MODE ZOWNO 861091 Setting of OWN widths 5 to OWN5 Fig 3 11 Connection to 32 bit Wide User CPU S TECHNICA Co LTD MKY40 User s Manual 3 12 2 Connection of 16 bit Wide User CPU The co 1 2 3 4 5 6 7 8 9 10 11 nnection between the MK Y40 and 16 bit wide user CPU is described below Fig 3 12
217. this state as that hardware reset is activated The RST pin is connected to an internal Schmitt type input buffer so a constant rise time circuit can be connected directly at power on FK S EH NE E NN EH EH IH IH IH RST No response to Must be kept Low for 10 or more clock periods less than 1 clock Y Fig 3 3 Hardware Reset Caution Design the circuit so that a hardware reset is surely activated immediately after MKY40 power on Chapter 3 Connections in MEM Mode TEP S TECHNICA CO LTD 3 3 Connecting Network Interface The network interface network I F pins of the MK Y40 consist of RXD pin 77 pin 78 and TXD pin 79 3 3 4 Recommended Network Connection Figure 3 4 shows the recommended network connection The TRX driver receiver components consists of an RS 485 based driver receiver and a pulse transformer Recommended network cables include Ethernet LAN cable 10 5 Category 3 or higher and shielded network cables Use one twisted pair cable in the network cable Va ERR RETE 1 One twisted pair cables with impedance of 100 Pulse t f USE ransiormer Network cable C 1 NA o v Connect a 100 Q termination resistor to the end of the network cables Connecting the resistor before or after the pulse transformer has the same effect Fig 3 4 Recommended Network Connection pin may be output directly to the
218. tion in the CUnet 3 1 Drvihd GIOCK auia TE cun E Id aoc CEU EE 3 2 Hardware Kaka sana 3 3 Connecting Network 3 4 Setting Baud eek rae 3 5 Network Cable Length eee rreeeeeee 3 6 Setting Station Addresses esee 3 7 Expansion Setting for Owned 3 8 Connecting LED Indication Pins 3 9 Connection of Timing Notification Signal STB Pin 3 10 Connecting PING Signal eene 3 11 Connecting General purpose Output Ports 3 12 Connecting User Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD Chapter 3 Connections in MEM Mode This chapter describes the pin functions and connections required for the MKY40 in MEM mode to function in the CUnet When connecting the MKY40 in MEM mode always connect the MODE pin pin 2 to GND Low level of the power supply Be sure to connect the VDD pin pins 26 37 50 61 76 100 to 5 0 V of the power sup ply the GND pin pins 1 25 38 39 51 62 72 7
219. tion of mail reception The RDY bit bit 6 changes to 0 when this bit goes to 1 When 1 is written to the RDY bit this bit is set to 0 This bit can be forcibly set to 0 by writing 0 directly to it instead of writing 1 to the RDY bit If the RUN bit of the SCR changes to 0 when this bit is 1 this bit also changes to 0 SouRCe station address SRCO to SRC5 bit bits 8 to 13 Function The source station addresses hexadecimal are set to these bits when dataset is stored in the MRBO Mail Receive Buffer 0 Chapter 5 Register Reference in MEM Mode ST ECHNICA CO LTD 5 19 Mail Receive 1 Control Register MR1CR Address 32 bit address 490H big amp little 16 bit address 492H big 490 little Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R R R R R R R R R W R R R R R R Functional description This register controls the mail reception corresponding to the MRB1 Mail Receive Buffer 1 Bit description receive SiZe 520 to SZ5 bit bits O to 5 Function These are bits where the dataset size hexadecimal of the received mail is set when the MRBI receives mail The dataset size uses 8 bytes as one unit receive ReaDY RDY bit bit 6 Function This bit sets permission for the MRB1 Mail Receive Buffer 1 to receive mail This bit can be operated when the RUN bit of the SCR is 1 When 1 is written to this bit the i
220. ts 0 to 5 all bits are cleared to 0 Bit description destination NOt ReaDY NORDY bit bit 0 Function This bit indicates that a mail sending error occurred because a destination receive buffer is not ready for reception destination NOt EXist NOEX bit bit 1 Function This bit indicates that a mail sending error occurred because the destination CUnet station set in the MSCR Mail Send Control Register does not exist limit Time OUT TOUT bit bit 2 Function This bit indicates that a mail sending error occurred because mail sending is completed even after the cycle count set in the MSLR Mail Send Limit time Register is reached SiZe FauLT SZFLT bit bit 3 Function This bit indicates that a mail sending error occurred because the set mail sending size set in the MSCR Mail Send Control Register is invalid LiMit time FauLT bit bit 4 Function This bit indicates that a mail sending error occurred because the value set in the MSLR Mail Send Limit time Register is invalid communication STOPped STOP bit bit 5 Function This bit indicates that a mail sending error occurred because the network stopped during mail sending Chapter 5 Register Reference in MEM Mode ST CO LTD 5 23 Mail Send Result Register MSRR Address 32 bit address 488H big amp little 16 bit address 48AH big 488 little Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial
221. updates data in MBs owned by other CUnet stations as data in internal output pins Do0 to Do31 as follows Fig 7 1 1 The MKY40 in IO mode generates a receive strobe signal when receiving packets sent from other CUnet stations to update data in MBs 2 In this case either of the upper 32 bits or the lower 32 bits of receive data 64 bits for update in the received MB is input to two 16 bit latches according to the levels High or Low input to the DOHL pin 3 An MB is selected by the combination of High or Low levels that the user inputs to the 4DOSAO to DOSAS pins If a received packet is data in this MB an STB1 output update strobe signal is gen erated from the receive strobe signal The MKY40 drives two 16 bit latches with this STB1 signal to update data in internal output pins Do0 to Do31 4 When the user inputs a Low level to the CLRL pin the lower 16 bits of data in internal output pins Do0 to Do31 can be cleared forcibly to Low level in preference to the 3 above 5 When the user inputs a Low level to the CLRH pin the upper 16 bits of data in internal output pins Do0 to Do31 can be cleared forcibly to Low level in preference to 3 above 6 When a hardware reset is activated data in internal output pins DoO to Do31 is cleared forcibly to Low level in preference to 3 above Because the STB1 signal is output to external pins the user can recognize the output updating time STECHNICA Co LTD MK
222. use the mail sending reception function through the following basic operations and processing 1 Permission for mail reception 2 Operation for mail reception 3 Operation for mail sending and after completion of sending 4 Operation against mail sending errors The MKY40 has registers and user support functions that help the above basic operations for mail sending and reception Chapter 4 Software in MEM Mode SF ECHNICA CO LTD 4 3 1 Permission for Mail Reception The MKY40 has two mail receive buffers MRBO Mail Receive Buffer Global Memory 0 and 1 Mail Receive Buffer 1 shown in 4 1 1 Memory Map eet The MRBO consist of 256 bytes each Fig 4 19 R Global Memory The Mail Receive 0 Control Register permits the to receive mail The MRICR Mail Receive Control 1 Register permits 400H the to receive mail Fig 4 20 Registers reserved by manufacturer 500H Mail send buffer MSB 600 Mail receive buffer 0 MRBO 700H Mail receive buffer 1 MRB1 When the user system program writes 1 to bit 6 RDY ReaDY of the V MROCR the MRBO is permitted to receive mail The RDY bit returns Fig 4 19 Mail Receive Buffers to 0 upon mail reception When the RDY bit of the MROCR is 7 1 mai i inhibi Bit 7 6 1 mail reception can be inhibited by MROCR RCV
223. utput hold 15 25 Data transition period 23 10 STB2 High level width 1 8 x TBPS 2 TBPS 2 2 5 Data input setup 50 Data input hold 0 Chapter 8 Ratings TEC HNICA CO LTD 8 3 Package Dimensions MKY40 100 pins TQFP 16 00 0 20 1 70 max 14 00 0 10 HL LB LILIL LIBI I LI I LI ULL LL LL LL A 0 10 0 10 Z 14 00 0 10 16 00 0 20 INDEX MARK LL LL LL LL LL LL LL LL LL L Mirror finish 5 1 0 0 20 0 05 1 00 T 0 to 10 P 0 50 40 20 SEATING PLANE 8 9 S TECHNICA CO LTD MKY40 User s Manual 8 4 Recommended Soldering Conditions Parameter Symbol Reflow Manual soldering iron Peak temperature resin surface 260 C max 350 C max Peak temperature holding time tp 10 s max 3 s max Caution 1 Product storage conditions 30 C max RH 70 for prevention of moisture absorption 2 Manual soldering Temperature of the tip of soldering iron 350 C 3 s max Device lead temperature 270 C 10 s max 3 Reflow Twice max 4 Flux Non chlorine flux should be cleaned sufficiently 5 Ultrasonic cleaning Depending on frequencies and circuit board shapes ultrasonic cleaning may cause resonance affecting l
224. val The tristate bus must not enter the floating state 2 When preventing the tristate bus entering the floating state using pull up resistors if the resistance value is too small particularly at a wide bus width it causes current changes in some bus lines Take preventive measures against power supply variations and malfunctions in other circuits Do not set the value of the pull up resistor to a lower value than required 3 Take preventive measures against collisions between output states when the bus direction changes In particular a wide bus width can cause system wide malfunctions instantaneous power supply variations and can damage the LSI in the worst case Fig 3 14 Precautions for User Bus Connection Vaesasessesessacsasasasesaat 4 ing Chapter 3 Connections in MEM Mode SF ECHNICA CO LTD 3 12 6 Access Test after Embedding MKY40 For details of how to check the address and access test after embedding the MKY40 in an MEM station user equipment refert to 4 1 2 Checking Connection of MKY40 3 12 7 Data Storage Method All the registers of the 40 are aligned on 4 byte boundary to optimize doubleword access with the 32 bit wide bus Fig 3 15 a At other access from the 32 bit wide data bus register addresses differ accord ing to the user CPU endian type In this manual addresses at doubleword access from the 32 bit wide bus addresses on common 4 byte boundary b
225. vel cx when external clock not used Connection of LED DO to D15 DO to D15 HOC approx EmA NUN y 23 LCARE p Orange WRLH ibis Woi MCARE Red WRL E WRLL 99 m 41 4 INTO Driving clock 48 MHz of MKY40 Interrupt input 52 o INT1 24 83 4 INT2 O Hardware reset of 40 Requiring Xi of 10 or more clocks when Low 5 0 V WBO 3 WB1 222 SA0 to SA5 80 to 85 Setting of station addresses Big endian selected High 11 ESEL Little endian selected Low 2 OWNO 86 to 91 Setting of OWN widths MODE OWN5 uw Fig 3 42 Connection to 16 bit Wide User CPU S TECHNICA Co LTD MKY40 User s Manual 3 12 3 Connection of 8 bit Wide User CPU The connection between the 40 and the 8 bit wide user CPU is described below Fig 3 13 1 2 3 4 5 6 7 8 9 10 11 Fix the BWO pin pin 9 and the BW1 pin pin 10 of the MKY40 Low The WRHH ESEL pin pin 11 functions as the ESEL pin Fix the WRHH ESEL pin High when the user CPU is big endian and Low when the user CPU is little endian The WRHL AI pin pin 12 functions as the Al pin Connect the address bus pin A1 output from the user CPU to the WRHL A1 pin The WRLH AO pin pin 40 functions as the AO pin Connect the address bus pin AO output from the user CPU to the WRLH AO pin Connect the address bus pins A2 to A10 output from the u
226. vels connected to the Write 0 to GMM of SCR SA1 to SA5 pins ZOWNO to OWNS pins 1 BPSO pin and BPS1 pin to the BCR Basic Con trol Register If this combination of High and Low levels is the value that the user system wants there is no need to set registers using the user system program To prevent accidental writing during network operation the BCR can be written only when bit 15 GMM of the SCR Fig 4 1 Start Algorithm System Control Register is 1 To write setting values to the BCR using the user system program follow the procedure below 1 Check that bit 8 START of the SCR is 0 2 Write 1 to bit 15 GMM of the SCR 3 Write the SA values to bits 0 to 5 SAO to SA5 of the BCR the baud rate values to bits 6 and 7 BPSO and BPS1 and the OWN width OWN values to bits 8 to 13 OWNO to OWNS 4 Write 0 to bit 15 GMM of the SCR 3 Write 1 to bit 8 START of the SCR The CUnet network starts and the MK Y40 enters the START phase 4 Read the SCR to check that bit 9 RUN is 1 which means the MK Y40 enters the RUN phase If bit 9 RUN of the SCR does not go to 1 and bit 10 CALL or bit 11 BRK goes to 1 when the MKY40 is in any phase other than RUN follow the description in 4 1 4 Responses to Each Phase 5 When bit 9 RUN of the SCR is 1 the user system can use sharing memory data using GM and CUnet communication by mail sending receiving of da
227. vides the MFR with a management function similar to general communi cations management When the user system accepts instantaneous Dead Link as long as it is recovered by the cycle based on cyclic time sharing the user system can recognize the assured state including global memory data recovery by reading the MFR The MFR register is also effective for management of disconnection of CUnet sta tion If a CUnet station disconnects the MFR bit corresponding to the CUnet station changes from 1 to 0 4 2 3 6 Member Group Register MGR The Member Flag Register MFR status is updated at the starting point of status management according to the consecutively repeated cycle The MK Y40 has a function 64 bit MGR to reduce the burden on user system program detailed management of the MFR status The MGR monitors the MFR status Each MGR bit corresponds to each bit The user system program can arbitrarily write 1 or 0 to the MGR bits The MK Y40 judges the following two items at every one cycle immediately before the starting point of status management Fig 4 16 1 The MGR does not match the MFR MGR MFR 2 The MER bits corresponding to the MGR bits at 1 are at 0 MGR gt MFR This result is notified to the user system by the following two methods 1 Indicating the result where 1 15 true in bit 4 Member group Not Equal and bit 5 MGNC Member group Not Collect The MGNE
228. when resizing described in 4 4 2 Resizing of Cycle Time disables a link with the CUnet station with which the link has been established STECHNICA CO LTD 40 User s Manual 4 4 5 2 MCARE Signal Output In a CUnet dead link occurs consecutively three times in the same CUnet station when CUnet station disconnects when a system is in a poor operating environment and when network has marginal per formance In the MKYAO the occurrence of three consecutive dead links is controlled by the MFR described in 4 2 3 5 Member Flag Register MFR and is considered to be Member decrease described in 4 2 3 7 Detection of Member Increase and Decrease Member decrease is also called MCARE Member CARE The MKY40 outputs pulse signals that go Low for a given time from the MCARE pin regardless of the bit status stored in the MGR described in 4 2 3 6 Member Group Register MGR The occurrence of MCARE can be checked visually by connecting an LED indicator to this MCARE pin For details of con necting the LED indicator refer to 3 8 Connecting LED Indication Pins It is possible to identify what caused MCARE when a system is in an extremely bad environment or when a network has marginal performance except when a CUnet station is disconnected intentionally by the user system Network hardware and environmental quality can be recognized by controlling the occur rence o
229. write protected 3 The BCR Basic Control Register can be written only when the START bit of the SCR is 0 and the GMM bit is 1 4 Dataset can be sent and received only when the RUN bit of the SCR is 1 RUN phase 2 ES Write data to any memory area other than the owned area in GM Write 1 to bit 15 GMM of the SCR O Bit 8 Write data to any memory area other than the owned area in GM gt 1 gt Write 1 to bit 15 GMM of the SCR Write setting values to the BCR SCR Write setting values to the BCR gt Send and receive mails 1 Send and receive mails Fig 4 3 Write Protection STECHNICA CO LTD 40 User s Manual 4 1 6 Cycle Time of CUnet The cycle time of a CUnet consisting of the 40 is determined by Equations 4 1 and 4 2 defined by the CUnet protocol The CUnet cycle time is the response time for memory data sharing Equation 4 1 Frame Time LOF FS 1 x 2x TBPS s Equation 4 2 Cycle Time Frame Time x FS PFC 1 s For example when FS 03H LOF 151 PFC 2 and baud rate 12 Mbps TBPs 1 12 x 106 83 3 ns the frame time and cycle time are calculated as follows Frame Time 151 3 1 x 2 x 1 12 x 106 25 833 Cycle Time 25 833 us x 3 2 1 155 us In a CUnet LOF Length Of Frame is fixed at 151 and PFC Public Frame Count is fixed at 2
230. x 2 Internal Equivalent Block Diagram in IO Mode App 4 Appendix 3 Register List in Address Order eese App 5 CORD MKY40 User s Manual Figures Fig 1 1 CUnet Station with MKY40 in MEM Mode MEM Station 1 3 Fig 1 2 CUnet Connecting Four MEM Stations eere 1 3 Fig 1 3 l O Slall h ete toni tepore tlie eia ice ba Ue demas ac eee 1 5 Fig 1 4 CUnet Connecting Two Modes eene nnns 1 5 Fig 2 1 Pin Assignment in MEM 2 3 Fig 2 2 Pin Electrical Characteristics I O Circuit Types in MEM Mode 2 8 Fig 3 1 Self generation of Driving eere 3 4 Fig 3 2 Supplying Generated Driving Clock eene 3 5 Fig 3 3 Hardware Id IR SEE URL Yt Spa 3 6 Fig 3 4 Recommended Network Connection eene 3 7 Fig 3 5 Example of Adding Cable for GMM 3 8 Fig 3 6 Example of Direct Connection to HUB IC eene 3 8 Fig 3 7 Setting of Baud epe
231. xternal I O pins Four pins can be set to input or output at a time by IOS Four pins can be logically inverted at a time by INVO to of 4lOSWAP Pulse transformer 29 to 36 42 to 49 53 to 60 64 to 71 Baud rate setting INV7 o6 Baud rate setting 1 Baud rate setting 0 Set logic inversion of general purpose 131020 gt 95 Hi Lo external I O pins Clock input for Lo Hi 28 external baud rate Lo Lo Output update strobe 41 e Maximum EXC frequency Xi x 1 4 bps value EXC x 1 4 Input update strobe 9 SA0 to Clear 1016 to lo310utput levels SA5 O 80 to 85 Set I O station addresses Clear 100 to 1015 output levels 2215 O i 8 Green Output availability signal 92 5100 DOA Data Out Available 16 Indicate data sending status Indicates that bits at 1 exist in the MFR Member Flag Register Select memory block MB to DOSAO indicates that data in internal input pins can be sent to other be output to internal output pins 86 to 91 Ol to 4DOSA5 CUnet stations connected to a network Green 12 93 c Ps Select upper lower bits of MB O DONA aJ Indicate output availability DOHL Data Out Hi bit Lo bit 1 DONA Data Out Not Available Notify PING Indicates that packets can be received from the CUnet station specified by DOSA within 16 cycle times 11 Set frame option O Usually keep this pin High Set IO mode Keep this pin Low for a system consisting of 10 mode alone and when a fr
232. ystem with user CPUs of the same endian type Fig 3 15 a However when sharing byte and word data between user CPUs with different endian types note that addresses expressed by their lower 2 bits AO and A1 are different Fig 3 15 b Take care when handling character string data STECHNICA Co LTD MKY40 User s Manual 3 12 8 Connection of Interrupt Trigger Signals The MKY40 has three output pins INTO to INT2 pins 41 52 63 that supply interrupt trigger signals to the interrupt start pin of the user CPU When a hardware reset is activated the INTO to INT2 pins are all set High When the trigger occurs the INTO to INT2 pins change to Low level The INTO to INT2 pins can be returned to High level by accessing specific MK Y40 registers from the user system program Meet the user CPU specifications when connecting the INTO to INT2 pins or one or two to the interrupt start pin of the user CPU Leave these pins open when not used Multiple interrupt factors can be set for each of the INTO to INT2 pins If the user system program uses the state where two or more interrupt factors are set for one pin the pin may be returned temporarily to a High level by the retrigger function of the MK Y40 and may output Low level again immediately after 5 clocks have elapsed about 104 us for a 48 MHz driving clock When setting two or more interrupt factors for one pin in this way hardware receiving interrupts from the
233. zgoizooroooondr cao 2 6 ui I X Q rz 3k gt N C No connect Note Pins prefixed with are negative logic active Low Fig 2 1 Pin Assignment in MEM Mode S TECHNICA CO LTD MKY40 User s Manual Table 2 1 lists the pin functions in MEM mode of the MK Y40 Table 2 1 Pin Functions in MEM Mode Positive Input pin that sets MKY40 mode In MEM mode always fix this pin at Low Positive General purpose output ports to which bits 0 to 3 of data written from user CPU to SSR System Status Register in MK Y40 output When a hardware reset becomes active these pins are kept Low until data is written from the user CPU to the SSR in the MKY40 Positive Output pin with PING function that goes High when PING instruc tion received from another CUnet station When a hardware reset is activated this pin is kept Low in prefer ence to the PING instruction from another CUnet station Negative Output pin for timing notification that outputs Low level for given time at beginning of cycle time Positive Input pins that set width of bus connected to user CPU When the BW1 pin is High a 32 bit bus width is selected When the BW1 pin is Low and BWO pin is High a 16 bit bus width is selected When both the BW1 and BWO pins are Low an 8 bit bus width is selected Negative Positive This pin functions as the WRHH input pin when the BW1 pin is High Connect a si

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