USB2817 User`s Manual
Contents
1. Fa m 13 Chapter 6 Continuous And Grouping Sampling 16 6 1 AD Continuum Sampling Function pe 16 DIGGIOUDisannlnEunenoi r E EEEE E EEE 16 Chapter Timer on 20 8 Notes Calibration and Warranty Policy 23 T T 23 ww Amalos loput 23 8 3 Analog Signal Output Calibration pp 23 SAFDA H MP 23 Wai 24 Products Rapid Installation UC NG Ciao 25 25 C 22 PSV Vrone Installato 25 USB2817 Data Acquisition V6 004 Chapter I Overview In the fields of Real time Signal Processing Digital Image Processing and others high speed and high precision data acquisition modules are demanded ART USB2817 data acquisition module which brings in advantages of similar products that produced china and other countries 15 convenient for use high cost and stable performance ART USB2817 is a data acquisition module based on USB bus It can be directly inserted into IBM PC AT or a computer which is compatible with USB2817 to constitute the laboratory product quality testing2. n 4 3 2 1 0 2 03 Figure 1 Mode 1 Hardware retriggerable one shot The mode can work under the role of GATE After given the initial count value N OUT becomes high level the counter begins to count until the appearance of the rising edge of GATE at this moment OUT turns into low level when the count ends and the count value becomes 0 OUT becomes high level that is the output one shot pulse width is determined by the initial count value N If the current operation does not end and another rising edge of GATE appears then the current count stops the counter begins to count from N once again and then the output one shot pulse will be widened When the count reduction of the counter has not yet reached zero but it is given a new value N1 Only when it is the rising edge of GATE the counter starts to count from N1 Time diagram is shown in Figure 2 Mode 1 CLK ITLI LI WR n 4 Figure 2 USB2817 Data Acquisition V6 004 Mode 2 Rate Generator Under this mode the counter is given the initial count value N and begins to count from N 1 OUT becomes high level When the count value becomes 0 OUT turns into low level After CLK cycle OUT resumes high level and the counter automatically load the initial value N and begin to count from N 1 Thus the output will continue to output a negative pulse its width is equal to one clock cycle the clock number between the two negative pul
3. 2 2 4 Jumper 1 Analog input range selected Single ended Differential Inputs 2 2 5 Status indicator EF FIFO non empty status indicator FF FIFO overflow status indicator HF FIFO half full status indicator LEDS OV 5 0V power supply indicator on for normal USB2817 Data Acquisition V6 004 Chapter 3 Signal Connectors 3 1 The Definition of Signal Input and Output Connectors 37 core plug on the CN1 pin definition 19 NC DTR 37 18 ATR AGND 36 17 AGND 10 35 16 AII AI2 34 15 14 33 14 15 16 32 13 18 31 P 12 19 30 11 AI12 29 10 AI13 4 28 9 5 AGND 27 8 AGND AGND 26 7 AGND 25 0 AGND AGND 24 B 5 2 AGND 23 4 AGND AGND 22 2 3 AOI AGND 21 gt 2 AGND AGND 20 1 0 Pin definition about 10 115 Analog input reference ground is AGND Analog output reference ground is AGND Analog trigger signal input reference ground is AGND DTR DIR Digital trigger signal input reference ground is DGND AGND GND Analog ground This AGND pin should be connected to the system s AGND plane NC Notconecied 3 2 Digital Input Output Connector 50 core plug P1 pin definition USB2817 Data Acquisition V6 004 DOO _ 2 DOI DO2 3 o o4 DO3 DO4 5 ol DO5 DO6 71 018 DO7 DOS 9
4. Under the fixed frequency external clock mode for example when sampling data of two channel 0 1 then channel 0 and channel consist of a group Sampling frequency Frequency 100000Hz the cycle is 10us Loops of group is 2 then the acquisition process 15 to collect the first set of data including two data of channel 0 and two data of channel 1 the order of conversion 0 1 0 1 We need 10us to sample the four data and 40us to convert of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the next edge of the external clock triggers AD to do the next acquisition and the conversion is going on in this way as the diagram following shows USB2817 Data Acquisition V6 004 Start Enabled External Clock Convert Pulse The external clock before the start pulse is ignored Figure 6 3 Grouping sampling under the fixed frequency external clock mode Notes a internal clock sample cycle b AD chips conversion time d group cycle external clock cycle Under an unfixed frequency external clock mode for example the grouping sampling principle is the same as that of the fixed frequency external clock mode Under this mode users can control any channel and any number of data Users will connect the control signals with the clock input of the card CLKIN set the sampling channels and Loops of group When there are external clock s
5. USB2817 Data Acquisition V6 004 Chapter 5 The Instruction Trigger Function 5 1 Internal Trigger Mode When AD is in the initialization if the AD hardware parameter ADPara TriggerMode USB2817 TRIGMODE SOFT we can achieve the internal trigger acquisition In this function when calling the StartDeviceProAD function it will generate AD start pulse AD immediately access to the conversion process and not wait for the conditions of any other external hardware It also can be interpreted as the software trigger As for the specific process please see the figure below the cycle of the AD work pulse is decided by the sampling frequency The first working pulse after the AD 3 start pulse Figure 5 1 Internal Trigger Mode 5 2 External Trigger Mode When A D 15 in the initialization if the A D hardware parameter ADPara TriggerMode USB2817 TRIGMODE POST we can achieve the external trigger acquisition In this function when calling the startDeviceProAD function AD will not immediately access to the conversion process but wait for the external trigger source signals accord with the condition then start converting the data It also can be interpreted as the hardware trigger Trigger source includes the DTR Digital Trigger Source and ATR Analog Trigger Source The trigger modes include the edge trigger and level trigger 1 Edge trigger function Edge trigger is to capture the characteristics of the changes between the trigger so
6. Differential Inputs Double ended input mode which was also called differential input mode uses positive and negative channels to input a signal This mode is mostly used when biggish interference happens and the channel numbers are few Single ended double ended mode can be set by the software please refer to USB2817 software manual According to the diagram below USB2817 board can be connected as analog voltage double ended input mode which can effectively suppress common mode interference signal to improve the accuracy of acquisition Positive side of the 8 channel analog input signal is connected to AIO AI7 the negative side of the analog input signal is connected to AI8 AI15 equipments in industrial sites share the AGND with USB2817 board 10 analog signal device xis 99 L device AI9 AI7 5 99 dozens of to hundreds of AGND E Figure 4 2 Differential inputs connection USB2817 Data Acquisition V6 004 4 3 Other Connections analog signal Eg 5 515 AOI 27 C2 e ROR device gt device QJ UN AGND Figure 4 3 analog signal output connection DIO switch signal we DII 1 115 switch device switch device DGND Figure 4 5 digital signal input connectio
7. condone the use of pirated software and will not service systems using such software ART will not be held legally responsible for products shipped with unlicensed software installed by the user 3 Our repair service is not covered by ART s guarantee ln the following situations Damage caused by not following instructions in the User s Manual Damage caused by carelessness on the user s part during product transportation Damage caused by unsuitable storage environments 1 high temperatures high humidity or volatile chemicals Damage from improper repair by unauthorized ART technicians gt Products with altered and or damaged serial numbers are not entitled to our service 4 Customers are responsible for shipping costs to transport damaged products to our company or sales office 5 To ensure the speed and quality of product repair please download an RMA application form from our company website BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 24 USB2817 Data Acquisition V6 004 Products Rapid Installation and Self check Rapid Installation Product driven procedure is the operating system adaptive installation mode After inserting the disc you can select the appropriate board type on the pop up interface click the button driver installation or select CD ROM drive in Resource Explorer locate the product catalog and enter into the APP folder and implement Setup exe file Aft
8. high level and low level VV Counter output OUTn high level and low level Other features Board Clock Oscillation 40MHz Dimension 158 8mm L x 117 2mm W x 17mm H USB2817 Data Acquisition V6 004 Chapter 2 Components Layout Diagram and a Brief Description 2 1 Main Component Layout Diagram E f 2 gt nun TI i 1 2 2 The Function Description for the Main Component 2 2 1 Signal Input and Output Connectors Analog signal input and output connectors P1 Digital input output timer counter signal input output port 2 2 2 Potentiometer Analog signal input zero point adjustment potentiometer RP2 Analog signal input full scale adjustment potentiometer RP7 Analog signal output zero point adjustment potentiometer RP3 AOO analog output full scale adjustment potentiometer RP4 AOI analog output full scale adjustment potentiometer 5 AO2 analog output full scale adjustment potentiometer RP6 AO3 analog output full scale adjustment potentiometer 2 2 3 Physical ID of DIP Switch DIDI Set physical ID number When the PC 15 installed more than one USB2817 you can use the DIP switch to set a physical ID number for each board which makes it very convenient for users to distinguish and visit each board in the progress of the hardware configuration and software programming The following four place numbers are expressed by the binary system Wh
9. must keep quality guarantee card carefully if the products have some problems and need repairing please send products together with quality guarantee card to ART we will provide good after sale service and solve the problem as quickly as we can When using USB2817 in order to prevent the IC chip from electrostatic harm please do not touch IC chip in the front panel of USB2817 module 8 2 Analog Signal Input Calibration Every device has to be calibrated before sending from the factory It is necessary to calibrate the module again if users want to after using for a period of time or changing the input range USB2817 default input range 10V the manual we introduce how to calibrate USB2817 in 10 calibrations of other input ranges are similar Prepare a digital voltage instrument which the resolution is more than 5 5 bit install the USB2817 module and then power on warm up for fifteen minutes 1 Zero adjustment Select AIO for example connect a DC voltage source with value equal to to AIO Adjust until the actual input value 0 000V 2 Full scale adjustment Select AIO for example connect a DC voltage source with value equal to 9999 69mV to Adjust RP2 until the actual input value 9999 69mV 3 Repeat steps above until meet the requirement 8 3 Analog Signal Output Calibration In the manual we introduce how to calibrate USB2817 in 5V output range calibrations of other output ranges are similar
10. 1 Zero adjustment set the output value to OV Adjust RP7 until the actual output value of is 0 000V 2 Full scale adjustment Select AOO for example set its output value to 4997 55mV Adjust until the actual output value 9997 55mV RP4 5 RP6 correspond to AOI AO2 AO3 3 Repeat steps above until meet the requirement 8 4 DA use In demonstration program the continuous output interval of waveform output can not be carried out the main objective is to test the strength of analog output 222200000000 BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 23 USB2817 Data Acquisition V6 004 8 5 Warranty Policy Thank you for choosing ART To understand your rights and enjoy all the after sales services we offer please read the following carefully 1 Before using ART s products please read the user manual and follow the instructions exactly When sending in damaged products for repair please attach an RMA application form which can be downloaded from www art control com 2 All ART products come with a limited two year warranty gt The warranty period starts on the day the product is shipped from ART s factory gt For products containing storage devices hard drives flash cards etc please back up your data before sending them for repair ART 15 not responsible for any loss of data gt Please ensure the use of properly licensed software with our systems ART does not
11. 4861583 CN 21 USB2817 Data Acquisition V6 004 Mode 4 Software triggered strobe Under this mode the counter is given the initial count value N and begins to count the output OUT becomes high level When the count value becomes 0 it immediately outputs a negative pulse which is equal to the width of one clock cycle If given a new count value when counting it will be effective immediately GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT Time diagram is shown in figure 5 Mode 4 Figure 5 Mode 5 Hardware triggered strobe Under this mode when the signal of GATE is on the rising edge the counter starts to count so it 1s called hardware trigger the output OUT has remained high level When the count value becomes 0 it outputs a negative pulse which is equal to the width of one clock cycle And then the rising edge of GATE signal can re trigger the counter starts to count from the initial count value again in the count period the output has remained high level When the count reduction of the counter has not yet reached zero but it is given a new value 1 Only when it 15 the rising edge of GATE the counter starts to count from N1 Time diagram is shown in figure 6 Mode 5 Figure 6 USB2817 Data Acquisition V6 004 Chapter8 Notes Calibration and Warranty Policy 8 1 Notes In our products packing user can find a user manual a USB2817 module and a quality guarantee card Users
12. USB2817 User s Manual Beijing Technology Development Co Ltd USB2817 Data Acquisition V6 004 Contents Owen 2 CHOICE L QVC 3 Chapter 2 Components Layout Diagram and a Brief 5 2 1 The Main Component Layout Diagram ee 3 2 2 The Function Description for the Main Component nnn nnn nhan ananas 3 2 2 1 Signal Input and Output Connectors inori eine in EEE Ene EEEE E ar EEEREN Er Ene Eit 5 OU 5 we 5 PAN 7 WTA 7 8 3 1 The Definition of Signal Input and Output ConnectoTS 8 2 2 Digital iui OG ORCC LOE gece sect cece _ ___ 8 Chapter 4 Connection Ways for Each Signal 10 4 es ie 10 renal pU ear A 10 23 Other 11 4 4 Methods of Realizing the Multi card Synchronization pp 11 Chapter 3 The Instruction 111 2 COP EE PME e E EUH 13 snemal 2 Mode 13
13. VV VV ON V Loops of Group software configurable minimum value is one time maximum value is 255 times BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 3 USB2817 Data Acquisition V6 004 Trigger Mode edge trigger and level trigger Trigger Direction positive negative either positive or negative Trigger Source ATR and DTR ATR Range 10 10 Programmable Amplifier AD8251 default AD8250 AD8253 compatible Programmable Gain 1 2 4 8 AD8251 default or 1 2 5 10 AD8250 or 1 10 100 1000 AD8253 Analog Input Impedance Non linear error 3LSB Maximum System Measurement Accuracy 0 01 Operating Temperature Range 0 55 VV VV VV VV ON ON WV Storage Temperature Range 20 70 Analog Output Output Range 10 5V default 0 10 0 5 12 bit resolution Set up Time 10uS Output Channels 4 Non linear error 1 LSB Maximum Output error full range 1LSB VV Digital Input Channel No 16 channel gt Electric Standard TTL compatible gt High Voltage 2V gt Low Voltage 0 8V Digital Output Channel No 16 channel Electrical Standard CMOS compatible High Voltage 4 45V Low Voltage 0 5V Power on output low level VV VV V Timer Counter Counter Channels 3 independent counter Counter Mode subtract count Counter Resolution 32 bit Count Mode 6 count modes software configurable GATEn rising edge
14. __ 10 X Doo DO10 ul 2112 Do DO12 13 a l4 Dol13 DO14 15 6__ DGND 171 a 18 DGND DIO 19 _ 20 DI DI2 21 22 DI4 2316 6124 ___ 015 016 2516 426 DI DI8 27 o o 128 D9 29 _ __ 30 DIII DI12 31 _ _ 32 DI14 33 _ _ 34 ___ 5 DGND 351 _ 36 DGND OUTO 37 _ 38 ___ CLKO 39 _ 40 GATE _ 4l 5g5 42 CIKI OUT2 43 44 GATE CLK2 45 _ 46 ___ DGND 471 48 __ 5V 49 50 ___ 5 pins definition DIO DI15 Digital signal input pins reference ground is DGND DO0 DOI5 Digital signal output pins reference ground is DGND CLKO CLK2 Input Timer counter clock source input reference ground 15 DGND GATE0 GATE2 Timer counter GATE input reference ground is DGND OUTO OUT2 Timer counter output reference ground is DGND CLK Output On board 2MHz clock oscillator pulse output output cycle is 0 59 DGND Digital signal ground 5 power supply USB2817 Data Acquisition V6 004 Chapter 4 Connection Ways for Each Signal 4 1 Analog Single ended Connection Single ended mode can achieve a signal input by one channel and several signals use the common reference ground This mode is widely applied in occasions of the small interference and relatively many channels AIO analog signal 12 5 we Tei 1 DJ NON Figure 4 1 single ended input connection 4 2 Analog
15. center and systems for different areas of data acquisition waveform analysis and processing It may also constitute the monitoring system for industrial production process Software Analysis Software ART USB2817 module is well suited for precision data acquisition analysis applications which you can specifically address with the ART Data Acquisition Measurement Suite The suite has two components digital and graphics mode analysis functions for voltage any signal can be transformed into the voltage signal frequency response and other analysis Unpacking Checklist Check the shipping carton for any damage If the shipping carton and contents are damaged notify the local dealer or sales for a replacement Retain the shipping carton and packing material for inspection by the dealer Check for the following items 1 the package If there are any missing items contact your local dealer or sales gt USB2817 Data Acquisition Board gt Disk a user s manual pdf b drive c catalog gt Warranty Card FEATURES Analog Input Input Range 10 5V default 2 5 0 10 0 5 16 bit resolution sampling Rate 31HZ S00KHz Analog Input Mode 16SE 8DI Data Read Mode non empty and half full inquire mode FIFO Size 8K word Memory Sign non empty half full Sample Mode continuous sampling and group sampling Group Interval software configurable minimum value 15 sampling period maximum value is 32767uS VV VV
16. diagram following shows Start Enabled Pulse Figure 6 1 Grouping Sampling which grouping cycle No is 1 under the Internal Clock Mode Note a internal clock sample cycle b AD chips conversion time c Group Interval d group cycle USB2817 Data Acquisition V6 004 Change the loops of group into 2 then the acquisition process 15 to collect the first set of data including two data of channel 0 and two data of channel 1 the conversion order is 0 1 0 1 We need 10us to sample each of the four data After the conversion time of an AD chip AD will automatically stop to enter into the waiting state until the 50us Group Interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the diagram following shows Start Enabled Convert Pulse _ es ibi c d Figure 6 2 Grouping Sampling which grouping cycle No is 2 under the Internal Clock Mode Notes a internal clock sample cycle b AD chips conversion time c Group Interval d group cycle Under the external clock mode the requirement is the external clock cycle gt the internal clock sampling period x the total number of sampling channelsx Loops of group AD chip conversion time otherwise the external clock appearing in the group conversion time will be ignored
17. en DIP switch points to ON that means 1 and when it points to the other side that means BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 5 USB2817 Data Acquisition V6 004 As they are shown in the following diagrams place ID3 is the high place IDO is the low place and the black part in the diagram represents the location of the switch Test softwares of the company often use the logic ID management equipments and at this moment the physical ID DIP switch is invalid If you want to use more than one kind of the equipments in one and the same system at the same time please use the physical ID as much as possible As for the differences between logic ID and physical ID please refer to the function explanations of CreateDevice and CreateDeviceEx of The Prototype Explanation of Device Object Management Function in USB2817S software specification ID3 102 IDO DIDI O _ 2 IN The chart shows 1111 so it means that the physical ID is 15 ID3 102 IDI IDO DIDI 2 The chart shows 0111 so it means that the physical ID is 7 103 102 101 IDO ON DIDI Z Z P The chart shows 0101 so it means that the physical ID is 5 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 OFF 0 ON D ON D oN ON D ON D ON D ON D ON D USB2817 Data Acquisition V6 004
18. er the installation pop up CD ROM shut off your computer insert the PCI card If it is a USB product it can be directly inserted into the device When the system prompts that it finds a new hardware you do not specify a drive path the operating system can automatically look up it from the system directory and then you can complete the installation Self check At this moment there should be installation information of the installed device in the Device Manager when the device does not work you can check this item Open Start gt Programs gt ART Demonstration Monitoring and Control System gt Corresponding Board gt Advanced Testing Presentation System the program is a standard testing procedure Based on the specification of Pin definition connect the signal acquisition data and test whether AD is normal or not Connect the input pins to the corresponding output pins and use the testing procedure to test whether the switch is normal or not Delete Wrong Installation When you select the wrong drive or viruses lead to driver error you can carry out the following operations In Resource Explorer open CD ROM drive run Others gt SUPPORT gt PCI bat procedures and delete the hardware information that relevant to our boards and then carry out the process of section I all over again we can complete the new installation BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 25
19. ignals it will sample the data which is set by users Because the external clock frequency is not fixed the size of external clock cycle is inconsistent but to meet the external clock cycle gt the internal clock sampling period x the total number of sampling channels x Loops of group AD chip conversion time otherwise the external clock edge appearing in the group conversion time will be ignored Start Enabled External Clock _ Convert Pulse Figure 6 4 Grouping sampling under the not fixed frequency external clock mode Note a internal clock sample cycle b AD chips conversion time USB2817 Data Acquisition V6 004 Chapter7 Timer Counter Mode 0 Interrupt on terminal count Under this mode when given the initial value if GATE is high level the counter immediately begins to count by subtracting 1 each time the counter output OUT turns into low level when the count ends and the count value becomes 0 the counter output OUT becomes and keeps high level until given the initial value or reset If a counter which 15 counting is given a new value the counter will begin to count from the new value by subtracting 1 each time GATE can be used to control the count GATE 1 enables counting GATE 0 disables counting OUT signal changes high from low can be used as interrupt request Time diagram is shown in Figure 1 Mode ok LU LIL Lili WR 4 3 OUT
20. is and the better the relative synchronization signal 1s The sampling frequency in group depends on ADPara Frequency Loops of group depends ADPara LoopsOfGroup the Group Interval depend on ADPara Group Interval Based on the grouping function it can be divided into the internal clock mode and the external clock mode Under the internal clock mode the group cycle is decided by the internal clock sampling period the total number of sampling channels Loops of group and Group Interval together In each cycle of a group AD only collects a set of data Under the external clock mode external clock cycle internal clock sampling cycle x the total number of sampling channels Loops of group AD chip conversion time AD data acquisition 15 controlled and triggered by external clock The external clock mode is divided into fixed frequency external clock mode and unfixed frequency external clock mode Under the fixed frequency external clock mode the group cycle is the sampling period of the external clock The formula for calculating the external signal frequency is as follows BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 16 USB2817 Data Acquisition V6 004 Under the internal clock mode Group Cycle the internal clock sampling period x the total number of sample channels x Loops of group AD chips conversion time Group Interval External signal cycle cycle signal points Loops of group x Gr
21. n DTR ATR AGND DGND cto Figure 4 7 trigger signal connection DOO Switch signal DO2 5015 switch device switch DGND jj Figure 4 4 digital signal output connection GATE 4 CLK 4 OUT i DGND Figure 4 6 Clock Input Output and Trigger Signal Connection 4 4 Methods of Realizing the Multi card Synchronization When using the common external trigger please make sure all parameters of different USB2817 are the same At first configure hardware parameters and use analog or digital signal triggering ATR or DTR then connect the sampled signal input triggering signal from ART pin or DTR pin then click Start button at this time USB2817 does not sample any signal but waits for external trigger signal When each module is waiting for external trigger signal use the common external trigger signal to startup modules at last we can realize synchronization data acquisition in this way See the following figure BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 11 USB2817 Data Acquisition V6 004 USB2817 External Trigger Signal ATR DTR ATR DTR gt USB2817 Amr USB2817 BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 12
22. ollow up changes have no effect on A D acquisition When ADPara TriggerDir USB2817 TRIGDIR POSIT NEGAT choose the trigger mode as either rising or falling edge trigger That is when the trigger signal 1s on the rising or falling edge A D will immediately access to the conversion process and its follow up changes have no effect on A D acquisition This function can be used in the case that the acquisition will occur if the exoteric signal changes 2 Level trigger function Level trigger 1s to capture the condition that trigger signal is higher or lower than the trigger level to trigger AD conversion When ADPara TriggerType USB2817 TRIGTYPE PULSE it is level trigger When ADPara TriggerDir USB2817 TRIGDIR NEGATIVE it means the trigger level is low When trigger signal is low level AD is in the conversion process once the trigger signal is in the high level A D conversion will 222000000000 BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 14 USB2817 Data Acquisition V6 004 automatically stop when the trigger signal is in the low level again A D will re access to the conversion process that is only converting the data when the trigger signal 15 in the low level A D Start Pulse Digital Trigger Si rial oo The high level before 1 lt waiting time gt the A D started is invalid l The first working pulse D Working Pulse A D Start P
23. oup Cycle External signal frequency 1 external signal cycle Under the external clock mode a fixed frequency external clock Group Cycle external clock cycle External signal cycle cycle signal points Loops of group x Group Cycle External signal frequency 1 external signal cycle Formula Notes The internal sampling clock cycle 1 AD Para Frequency The total number of sampling channels AD Para Last Channel AD Para First Channel 1 Loops of group ADPara LoopsOfGroup AD Chips conversion time see AD Analog Input Function parameter Group Interval AD Para Group Interval Signal Cycle Points with the display of the waveform signal in test procedures we can use the mouse to measure the signal cycle points Under the internal clock mode for example sample two channel 0 1 and then 0 and 1 become a group Sampling frequency Frequency 100000Hz cycle is 10us Loops of group is 1 Group Interval 50us then the acquisition process is to collect a set of data first including a data of channel 0 and a data of channel 1 We need 10uS to sample the two data 20us to convert the data from the two channels After the conversion time of an AD chip AD will automatically cut off to enter into the waiting state until the 50us group interval ends We start the next group begin to convert the data of channel 0 and 1 and then enter into the waiting state again and the conversion is going on in this way as the
24. s ADPara Frequency 100000 100KHz should be installed and 10 microseconds after the AD converts the first data point the second data point conversion starts and then 10 microseconds later the third data point begins to convert and so on 6 2 AD Grouping Sampling Function Grouping acquisition pseudo synchronous acquisition function refers to the sampling clock frequency conversion among the channels of the group in the AD sampling process and also a certain waiting time exists between every two groups this period of time is known as the Group Interval Loops of group refer to numbers of the cycle acquisition for each channel the same group In the internal clock mode and the fixed frequency external clock mode the time between the groups is known as group cycle The conversion process of this acquisition mode as follows a short time stop after the channels conversion in the group that is Group Interval and then converting the next group followed by repeated operations in order so we call it grouping acquisition The purpose of the application of the grouping acquisition is that at a relatively slow frequency to ensure that all of the time difference between channels to become smaller in order to make the phase difference become smaller thus to ensure the synchronization of the channels so we also say it is the pseudo synchronous acquisition function In a group the higher the sampling frequency is the longer Group Interval
25. ses is equal to the initial value that is given to the counter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT If change the initial count when counting it will be effective next time Time diagram is shown in figure 3 Mode 2 OUT GATE H GATE 3 2 1 D 3 d 2 8 OUT 4 Figure 3 Mode 3 Square wave mode Similar to Mode 2 the counter 15 given the initial count value N and begins to count from N 1 When the signal of GATE 15 high level it starts to count timer counter begins to count by subtracting 1 each time more than half the initial count value The output OUT has remained high level when the count value is more than half of the initial count value but the output OUT becomes low level when the count value is less than half of the initial value If the initial count value N is an even number the output is 1 1 square wave if the initial count value N is an odd number the output OUT has remained high level during the previous n 1 2 count period but the output OUT becomes low level during the post n 1 2 count period that is the high level has one clock cycle more than the low level If change the initial count when counting it will be effective next time When GATE 0 the count is prohibited when GATE 1 the count 15 permitted Time diagram 15 shown in figure 4 Mode 3 Figure 4 BUY ONLINE at art control com englishs or CALL 86 10 64862359 6
26. ulse A D Working Pulse Analog Trigger Signal meme EN 3 4 The waiting time aon ie The low level before i The first low level after the m 3 E 2 Low level after the A D invalid 1 3 started is valid Figure5 4 Digital Trigger Source Low Level Trigger When ADPara TriggerDir USB2817 TRIGDIR POSITIVE it means the trigger level is high When trigger signal is in high level AD 15 in the conversion process once the trigger signal 15 in the low level A D conversion will automatically stop when the trigger signal is in the high level again A D will re access to the conversion process that is only converting the data when the trigger signal is in the high level When ADPara TriggerDir USB2817 TRIGDIR POSIT NEGAT it means the trigger level is low The effect is the same as choosing the internal software trigger USB2817 Data Acquisition V6 004 Chapter 6 Continuous and Grouping Sampling Function 6 1 AD Continuum Sampling Function The continuous acquisition function means the sampling periods for every two data points are completely equal in the sampling process of AD that is completely uniform speed acquisition without any pause so we call that continuous acquisition To use the continuous acquisition function the hardware parameters ADPara ADMode USB2817 ADMODE SEQUENCE should be installed in the software For example in the internal clock mode hardware parameter
27. urce signal and the trigger level signal to trigger AD conversion When TriggerType USB2817 TRIGTYPE EDGE it is edge trigger When ADPara TriggerDir USB2817 TRIGDIR NEGATIVE choose the trigger mode as the falling edge trigger That is when the trigger signal 15 on the falling edge A D will immediately access to the conversion process and its follow up changes have no effect on A D acquisition 222200000000 BUY ONLINE at art control com englishs or CALL 86 10 64862359 64861583 CN 13 USB2817 Data Acquisition V6 004 A D Start Pulse Digital Trigger Signal 4 4 4 4 4 4400 1 The first working pulse after triggered Figure5 2 Digital Trigger Source Falling edge Trigger A D Start Pulse The first working Analog Trigger Signal Trigger Level The falling edge before The first falling edge after the the A D started is AID started is valid invalid c eU Figure5 3 Analog Trigger Source Falling edge Trigger When ADPara TriggerDir USB2817 TRIGDIR POSITIVE choose the trigger mode as rising edge trigger That is when the trigger signal is on the rising edge A D will immediately access to the conversion process and its f
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