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16/32-Bit XC2765X

1. Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 24 P5 3 In A Bit 3 of Port 5 General Purpose Input ADCO CH3 I In A Analog Input Channel 3 for ADCO T3INA In A GPT12E Timer T3 Count Gate Input 28 P5 4 In A Bit 4 of Port 5 General Purpose Input ADCO_CH4 I In A Analog Input Channel 4 for ADCO CCU63 T12 I In A External Run Control Input for T12 of CCU63 HRB TSEUDA In A GPT12E Timer T3 External Up Down Control Input TMS A In A JTAG Test Mode Selection Input 29 P5 5 In A Bit 5 of Port 5 General Purpose Input ADCO CH5 I In A Analog Input Channel 5 for ADCO CCU60_T12 I In A External Run Control Input for T12 of CCU60 HRB 30 P5 8 In A Bit 8 of Port 5 General Purpose Input ADCO CH8 I In A Analog Input Channel 8 for ADCO ADC1 CH8 I In A Analog Input Channel 8 for ADC1 CCU6x T12H In A External Run Control Input for T12 of RC CCU60 1 2 3 CCU6x T13H I In A External Run Control Input for T13 of RC CCU60 1 2 3 U2CO DXOF I In A USIC2 Channel 0 Shift Data Input 31 P5 9 In A Bit 9 of Port 5 General Purpose Input ADCO CH9 I In A Analog Input Channel 9 for ADCO ADC1 CH9 I In A Analog Input Channel 9 for ADC1 CC2 T7IN l In A CAPCOM2 Timer T7 Count Input Data Sheet 19 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information
2. Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 32 P5 10 In A Bit 10 of Port 5 General Purpose Input ADCO CH10 I In A Analog Input Channel 10 for ADCO ADC1 CH10 I In A Analog Input Channel 10 for ADC1 BRKIN A In A OCDS Break Signal Input U2C1 DXOF I In A USIC2 Channel 1 Shift Data Input CCU61 T13 In A External Run Control Input for T13 of CCU61 HRA 33 P5 11 In A Bit 11 of Port 5 General Purpose Input ADCO CH11 I In A Analog Input Channel 11 for ADCO ADC1 CH11 I In A Analog Input Channel 11 for ADC1 34 P5 13 In A Bit 13 of Port 5 General Purpose Input ADCO CH13 In A Analog Input Channel 13 for ADCO CCU63 T13 I In A External Run Control Input for T13 of CCU63 HRF 35 P5 15 In A Bit 15 of Port 5 General Purpose Input ADCO CH15 I In A Analog Input Channel 15 for ADCO 36 P2 12 00 1 St B Bit 12 of Port 2 General Purpose Input Output UOCO SELO 01 SUB USICO Channel 0 Select Control 4 Output 4 UOC1 SELO C2 SUB USICO Channel 1 Select Control 3 Output 3 READY IH SUB External Bus Interface READY Input 37 P2 11 00 1 St B Bit 11 of Port 2 General Purpose Input Output UOCO SELO 0O1 SUB USICO Channel 0 Select Control 2 Output 2 UOC1 SELO C2 SUB USICO Channel 1 Select Control 2 Output 2 BHE WRH OH SUB External Bus Interf High Byte Control Output Can operate either as Byte High Enable BHE or as Write strobe for
3. Parameter Symbol Values Unit Note Min Typ Max Test Condition TCK clock period t4 SR 500 l ns TCK high time t SR 16 ns TCK low time tz SR 16 ns TCK clock rise time t SR 8 ns TCK clock fall time t SR 8 ns TDI TMS setup to TCK tg SR 6 ns rising edge TDI TMS hold after TCK t SR 6 ns rising edge TDO valid from TCK falling t CC 32 36 ns edge propagation delay TDO high impedance to t9 CC 32 36 ns valid output from TCK falling edge 9 TDO valid output to high o CC l 32 36 ns impedance from TCK falling edge TDO hold after TCK falling t 4 CC 5 ns edge 1 The debug interface cannot operate faster than the overall system therefore t 2 tsys Under typical conditions the interface can operate at transfer rates up to 20 MHz 3 The falling edge on TCK is used to generate the TDO timing The setup time for TDO is given implicitly by the TCK cycle time 2 4 Data Sheet 122 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 0 9 Vppe 0 1 Vppe MC JTAG TCK Figure 30 Test Clock Timing TCK ls b 8 lt a TMS I l l l l l l l l l h L l l S S aaa l l TDO MC_JTAG Figure 31 JTAG Timing Data Sheet 123 V2 1 2011 07 oS XC2765X Infineon XC2000 Family Base Line Packag
4. 1 The total output current that may be drawn at a given time must be limited to protect the supply rails from damage For any group of 16 neighboring output pins the total output current in each direction Z o and X Toy must remain below 50 mA Data Sheet 105 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 5 External Bus Timing The following parameters specify the behavior of the XC2765X bus interface Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply Bus Interface Performance Limits The output frequency at the bus interface pins is limited by the performance of the output drivers The fast clock driver used for CLKOUT can drive 80 MHz signals the standard drivers can drive 40 MHz signals Therefore the speed of the EBC must be limited either by limiting the system frequency to fsys S 80 MHz or by adding waitstates so that signal transitions have a minimum distance of 12 5 ns For a description of the bus protocol and the programming of its variable timing parameters please refer to the User s Manual Table 28 EBC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition CLKOUT Cycle Time t CC l 1 fsys ns CLKOUT high time tg CC 2 CLKOUT low time t CC 2 CLKOUT rise time tg CC l
5. Electrical Parameters Table 37 DAP Interface Timing for Lower Voltage Range Parameter Symbol Values Unit Note Min Typ Max Test Condition DAPO clock period tS SR 1250 l ns DAPO high time ty SR 8 ns DAPO low time ta SR 8 ns DAPO clock rise time t4SR 4 ns DAPO clock fall time ts SR 4 ns DAP1 setup to DAPO Hg SR J6 ns pad type stan rising edge dard DAP1 hold after DAPO t17SR 6 ns pad type stan rising edge dard DAP1 valid per DAPO fg CC 12 17 ns pad type stan clock period dard 1 The debug interface cannot operate faster than the overall system therefore t44 2 tsys 2 The Host has to find a suitable sampling point by analyzing the sync telegram response MC DAPO Figure 27 Test Clock Timing DAPO Data Sheet 119 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters DR ch RO DAPO he hz DAP1 MC_DAP1_RX Figure 28 DAP Timing Host to Device MC DAP1 TX Figure 29 DAP Timing Device to Host Note The transmission timing is determined by the receiving debugger by evaluating the sync request synchronization pattern telegram Data Sheet 120 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters Debug via JTAG The following parameters are applicable for communication through the JTAG debug inte
6. e Jd 2 2 2 2 2 2 4A 2 2 2 2 2 2 2 2 2 2 2 2 2 2R 2 2 2 2 2 2 2 fp EP R E M ROME DUE VPE IRE upo c d p F EMENN T HdiM EuEENM a SSeS ES dA 2 2 2 14 eee 10 EE 8 X ce mm 50 MC XY ILKN Leakage Supply Current as a Function of Temperature Figure 15 V2 1 2011 07 85 Data Sheet Cinfineon XC2765X XC2000 Family Base Line 4 3 Analog Digital Converter Parameters Electrical Parameters These parameters describe the conditions for optimum ADC performance Note Operating Conditions apply Table 18 ADC Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Switched capacitance at Cainsw 4 5 pF not subject to an analog input production test Total capacitance at an CANT 10 12 pF not subject to analog input production test Switched capacitance at Carersw 7 9 pF not subject to the reference input CC production test Total capacitance at the Cange 13 15 pF not subject to reference input CC production test Differential Non Linearity EApw 0 8 1 0 LSB not subject to Error CC production test Gain Error IEAgainl 0 4 0 8 LSB not subject to CC production test Integral Non Linearity IEAw 0 8 ie
7. 424 ns Strong driver 90 0 14 x Sharp edge C 11 6 ns Strong driver 0 22 x Medium edge C 20 6 ns Strong driver 0 22 x Slow edge C 23 ns Medium driver 0 6 x C 212 ns Weak driver 1 9x C 1 The total output current that may be drawn at a given time must be limited to protect the supply rails from damage For any group of 16 neighboring output pins the total output current in each direction Z o and X Toy must remain below 50 mA Data Sheet 104 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Table 27 is valid under the following conditions Vopp gt 3 0 V Vopptyp 3 3 V Vopp lt 4 5 V C gt 20 pF C lt 100 pF Table 27 Standard Pad Parameters for Lower Voltage Range Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Maximum output driver Tomax 10 mA Strong driver current absolute value CC s 25 mA Medium driver 0 5 mA Weak driver Nominal output driver Tonom 2 5 mA Strong driver current absolute value CC H Hu 1 0 mA Medium driver 0 1 mA Weak driver Rise and Fall times 10 tgp CC 6 24 jns Strong driver 90 0 24 x Sharp edge C 24 ns Strong driver 0 3 x Medium edge C 34 ns Strong driver 0 3 x Slow edge C 37 ns Medium driver 0 65 x C 500 ns Weak driver 2 5 x CL
8. Program Flash 1 C4 0000 C7FFFF 256 Kbytes Program Flash 0 C0 0000 C3 FFFF 256 Kbytes External memory area 40 0000 BF FFFF 8 Mbytes Available Ext IO area 21 0000 3FFFFF 2Mbytes Minus USIC CAN Reserved 20 BCO0 20 FFFF 17Kbytes USIC alternate regs 20 B000 20 BFFF 4 Kbytes Accessed via EBC MultiCAN alternate 20 8000 20 AFFF 12 Kbytes Accessed via EBC regs Reserved 20 6000 20 7FFF 8 Kbytes USIC registers 20 4000 20 5FFF 8 Kbytes Accessed via EBC MultiCAN registers 20 0000 20 3FFF 16 Kbytes Accessed via EBC External memory area 01 0000 1F FFFF lt 2 Mbytes Minus segment 0 SFR area OO0 FEO0 00 FFFF 0 5 Kbyte E Dual Port RAM 00 F600 00 FDFF 2 Kbytes Reserved for DPRAM 00 F200 00 F5FF 1 Kbyte ESFR area 00 F000 00 F1FF 0 5 Kbyte XSFR area 00 E000 OO EFFF 4 Kbytes z Data Sheet 41 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description Table 8 XC2765X Memory Map cont d Address Area Start Loc End Loc AreaSize Notes Data SRAM 00 A000 00 DFFF 16 Kbytes Reserved for DSRAM 00 8000 00 9FFF 8 Kbytes External memory area 00 0000 00 7FFF 32 Kbytes 1 Accesses to the shaded areas are reserved In devices with external bus interface these accesses generate external bus accesses The ar
9. 3 ns CLKOUT fall time tg CC 3 1 The CLKOUT cycle time is influenced by PLL jitter For longer periods the relative deviation decreases see PLL deviation formula CLKOUT MC X EBCCLKOUT Figure 22 CLKOUT Signal Timing Data Sheet 106 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters Note The term CLKOUT refers to the reference clock output signal which is generated by selecting fsys as the source signal for the clock output signal EXTCLK on pin P2 8 and by enabling the high speed clock driver on this pin Variable Memory Cycles External bus cycles of the XC2765X are executed in five consecutive cycle phases AB C D E F The duration of each cycle phase is programmable via the TCONCSx registers to adapt the external bus cycles to the respective external module memory peripheral etc The duration of the access phase can optionally be controlled by the external module using the READY handshake input This table provides a summary of the phases and the ranges for their length Table 29 Programmable Bus Cycle Phases see timing diagrams Bus Cycle Phase Parameter Valid Values Unit Address setup phase the standard duration of this tpAB 1 2 5 TCS phase 1 2 TCS can be extended by 0 3 TCS if the address window is changed Command delay phase tpC 0 3 TCS Write Data setup MUX Tristate phase tpD 0 TCS Acces
10. Depending on the package option up to 3 External Service Request ESR pins are provided The ESR unit processes their input values and allows to implement user controlled trap functions System Requests SRO and SR1 In this way reset wakeup and power control can be efficiently realized Software interrupts are supported by the TRAP instruction in combination with an individual trap interrupt number Alternatively to emulate an interrupt by software a program can trigger interrupt requests by writing the Interrupt Request IR bit of an interrupt control register 3 7 On Chip Debug Support OCDS The On Chip Debug Support system built into the XC2765X provides a broad range of debug and emulation features User software running on the XC2765X can be debugged within the target system environment The OCDS is controlled by an external debugging device via the debug interface This either consists of the 2 pin Device Access Port DAP or of the JTAG port conforming to IEEE 1149 The debug interface can be completed with an optional break interface The debugger controls the OCDS with a set of dedicated registers accessible via the debug interface DAP or JTAG In addition the OCDS system can be controlled by the CPU e g by a monitor program An injection interface allows the execution of OCDS generated instructions by the CPU Multiple breakpoints can be triggered by on chip hardware by software or by an external trigger input
11. oS XC2765X Infineon XC2000 Family Base Line Package and Reliability 5 2 Thermal Considerations When operating the XC2765X in a system the total heat generated in the chip must be dissipated to the ambient environment to prevent overheating and the resulting thermal damage The maximum heat that can be dissipated depends on the package and its integration into the target board The Thermal resistance Roy quantifies these parameters The power dissipation must be limited so that the average junction temperature does not exceed 150 C The difference between junction temperature and ambient temperature is determined by AT Pint Piosrar Piopyn X Rosa The internal power consumption is defined as Pint Vopr Ippp Switching current and leakage current The static external power consumption caused by the output drivers is defined as Piostat Vopp Vor x loy Voi x loi The dynamic external power consumption caused by the output drivers Pigpyn depends on the capacitive load connected to the respective pins and their switching frequencies If the total power dissipation for a given system configuration exceeds the defined limit countermeasures must be taken to ensure proper system operation e Reduce Vppp if possible in the system Reduce the system frequency Reduce the number of output pins Reduce the load on active output drivers Data Sheet 126 V2 1 2011 07 e XC2765X Infineon XC2000 Fa
12. 3 8 11 ns Data output hold time for t CC 3 8 10 ns D15 DO and AD15 ADO Input setup time for f SR 29 17 ns READY D15 DO AD15 ADO Input hold time READY t SR O 9 ns D15 DO AD15 ADO 1 Read data are latched with the same internal Data Sheet al clock edge that triggers the address change and the rising edge of RD Address changes before the end of RD have no impact on demultiplexed read cycles Read data can change after the rising edge of RD V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters tPaB tpc ta gt ja t24 High Address l l to l AD15 ADO read Low Address l t13 l t15 t25 l t I gt ADIADO I Low Address X Data Out write MC X EBCMUX Figure 23 Data Sheet Multiplexed Bus Cycle 110 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters l l l l l l ALE fitu l l ta I I l l l he l tos l l l l l l l D15 D0 write Data Out MC_X_EBCDEMUX Figure 24 Demultiplexed Bus Cycle Data Sheet 111 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 5 1 Bus Cycle Control with the READY Input The duration of an external bus cycle can be controlled by t
13. 6 49 P4 3 O0 I SUB Bit 3 of Port 4 General Purpose Input Output UOC1 DOUT 01 St B USICO Channel 1 Shift Data Output CC2 CC27 03 1 St B CAPCOM2 CC27I0 Capture Inp Compare Out CS3 OH SUB External Bus Interface Chip Select 3 Output T2EUDA SUB GPT12E Timer T2 External Up Down Control Input CCU62_CCP St B CCU62 Position Input 2 OS2B Data Sheet 23 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 53 PO 0 O0 I SUB Bit 0 of Port 0 General Purpose Input Output U1CO DOUT 01 SU B USIC1 Channel 0 Shift Data Output CCU61_CC6 O3 St B CCU61 Channel 0 lOutput 0 AO OH Si B External Bus Interface Address Line 0 U1CO DXOA SUB USIC1 Channel 0 Shift Data Input CCU61 CO6 I SUB CCU61 Channel 0 Input OINA ESR1 11 SUB ESR1 Trigger Input 11 54 P27 O0 I SUB Bit 7 of Port 2 General Purpose Input Output UOC1 SELO O1 SUB USICO Channel 1 Select Control 0 Output 0 UOCO SELO C2 SUB USICO Channel 0 Select Control 1 Output 1 CC2 CC20 0O3 1 St B CAPCOM2 CC20I0 Capture Inp Compare Out A20 OH SUB External Bus Interface Address Line 20 UOC1 DX2C St B USICO Channel 1 Shift Control Input RxDC1C SUB CAN Node 1 Receive Data Input ESR2 7 SUB ESR2 Trigger Input 7 55
14. Arithmetic sign bit shift right direct word GPR 2 MOV B Move word byte data 2 4 MOVBS Z Move byte operand to word op with sign zero extension 2 4 JMPA I R Jump absolute indirect relative if condition is met 4 JMPS Jump absolute to a code segment 4 JB C Jump relative if direct bit is set and clear bit 4 JNB S Jump relative if direct bit is not set and set bit 4 CALLA I R Call absolute indirect relative subroutine if condition is met 4 CALLS Call absolute subroutine in any code segment 4 PCALL Push direct word register onto system stack and call 4 absolute subroutine TRAP Call interrupt service routine via immediate trap number 2 PUSH POP Push pop direct word register onto from system stack 2 SCXT Push direct word register onto system stack and update 4 register with word operand RET P Return from intra segment subroutine 2 and pop direct word register from system stack RETS Return from inter segment subroutine 2 RETI Return from interrupt service subroutine 2 SBRK Software Break 2 SRST Software Reset 4 IDLE Enter Idle Mode 4 PWRDN Unused instruction 4 SRVWDT Service Watchdog Timer 4 DISWDT ENWDT Disable Enable Watchdog Timer 4 EINIT End of Initialization Register Lock 4 ATOMIC Begin ATOMIC sequence 2 EXTR Begin EXTended Register sequence 2 EXTP R Begin EXTended Page and Register sequence 2 4 EXTS R Begin EXTended Segment and Register sequence 2 4 Data Sheet 69 V2 1 2011 07 XC2765X Infineon XC2000 Fami
15. B USIC1 Channel 1 Shift Control Input RxDC1B SUB CAN Node 1 Receive Data Input ESR2 8 SUB ESR2 Trigger Input 8 65 P2 13 00 1 St B Bit 13 of Port 2 General Purpose Input Output U2C1_SELO O1 SUB USIC2 Channel 1 Select Control 2 Output 2 66 P2 10 00 1 SUB Bit 10 of Port 2 General Purpose Input Output UOC1 DOUT 01 St B USICO Channel 1 Shift Data Output UOCO SELO C2 SUB USICO Channel 0 Select Control 3 Output 3 CC2 CC23 O3 I SU B CAPCOM2 CC23IO Capture Inp Compare Out A23 OH SUB External Bus Interface Address Line 23 UOC1 DXOE St B USICO Channel 1 Shift Data Input CAPINA SUB GPT12E Register CAPREL Capture Input Data Sheet 27 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 67 P10 3 O0 I SUB Bit 3 of Port 10 General Purpose Input Output CCU60 COU O2 St B CCU60 Channel 0 Output T60 AD3 OH St B External Bus Interface Address Data Line 3 IH UOCO DX2A I SUB USICO Channel 0 Shift Control Input UOC1 DX2A I SUB USICO Channel 1 Shift Control Input 68 PO0 5 O0 I SUB Bit 5 of Port 0 General Purpose Input Output U1C1 SCLK O1 SUB USIC1 Channel 1 Shift Clock Output OUT U1CO SELO C2 SUB USIC1 Channel 0 Select Control 2 Output 2 CCU61 COU O3 SUB CCU61 Channel 2
16. CAN nodes with Full CAN functionality which are able to exchange Data and Remote Frames using a gateway function Transmission and reception of CAN frames is handled in accordance with CAN specification V2 0 B active Each CAN node can receive and transmit standard frames with 11 bit identifiers as well as extended frames with 29 bit identifiers All CAN nodes share a common set of message objects Each message object can be individually allocated to one of the CAN nodes Besides serving as a storage container for incoming and outgoing frames message objects can be combined to build gateways between the CAN nodes or to set up a FIFO buffer Note The number of CAN nodes and message objects depends on the selected device type The message objects are organized in double chained linked lists where each CAN node has its own list of message objects A CAN node stores frames only into message objects that are allocated to its own message object list and it transmits only messages belonging to this message object list A powerful command driven list controller performs all message object list operations MultiCAN Module Kernel Clock Control Linked List Control PON Control Decoder Interrupt Control CAN Control mc_multican_block vsd Figure 12 Block Diagram of MultiCAN Module Data Sheet 64 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description MultiCAN Feature
17. LSB not subject to CC production test Offset Error EAorrl 0 5 0 8 LSB not subject to CC production test Analog clock frequency fapc SR 0 5 20 MHz Upper voltage range 0 5 16 5 MHz Lower voltage range Input resistance of the Ran CC 2 kOh not subject to selected analog channel m production test Input resistance of the Rarer 2 kOh not subject to reference input m production test Data Sheet 86 V2 1 2011 07 Infineon XC2765X XC2000 Family Base Line Table 18 ADC Parameters cont d Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Broken wire detection fewa CC 50 3 delay against VAGND Broken wire detection towa CC 50 a delay against VAREF Conversion time for 8 bit ts CC 11 STC x tanci result 2 X love Conversion time for 10 bit t 49 CC 13 STC x tanci result 2 X tsys Total Unadjusted Error TUE 1 2 LSB CC Wakeup time from analog twar CC 4 us powerdown fast mode Wakeup time from analog twas CC 15 us powerdown slow mode Analog reference ground Vaaup Vas 1 5 V SR 0 05 Analog input voltage Van SR Vann Varer V 9 range Analog reference voltage Varner VaGND VpppA V 9 1 0 0 05 1 v Sg These parameter values cover the complete operating range Under relaxed operating conditions room tempe
18. Line 1 IH CCU60 CO6 I St B CCU60 Channel 1 Input 1INA UOCO DX1A I St B USICO Channel 0 Shift Clock Input UOCO DXOB I St B USICO Channel 0 Shift Data Input 61 P0 3 O0 I SUB Bit 3 of Port 0 General Purpose Input Output U1CO SELO O1 SUB USIC1 Channel 0 Select Control 0 Output 0 U1C1 SELO C2 SUB USIC1 Channel 1 Select Control 1 Output 1 CCU61 COU OS SUB CCU61 Channel 0 Output T60 A3 OH SUB External Bus Interface Address Line 3 U1CO DX2A I SUB USIC1 Channel 0 Shift Control Input RxDCOB SUB CAN Node 0 Receive Data Input Data Sheet 26 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 62 P10 2 O0 I SUB Bit 2 of Port 10 General Purpose Input Output UOCO SCLK O1 St B USICO Channel 0 Shift Clock Output OUT CCU60 CC6 O2 St B CCU60 Channel 2 Output 2 AD2 OH St B External Bus Interface Address Data Line 2 IH CCU60_CCE St B CCU60 Channel 2 Input 2INA UOCO_DX1B SUB USICO Channel 0 Shift Clock Input 63 P0 4 00 1 St B Bit 4 of Port 0 General Purpose Input Output U1C1 SELO O1 SUB USIC1 Channel 1 Select Control 0 Output 0 U1CO SELO C2 SUB USIC1 Channel 0 Select Control 1 Output 1 CCU61 COU O3 St B CCU61 Channel 1 Output T61 A4 OH SUB External Bus Interface Address Line 4 U1C1 DX2A I St
19. N o o t e N T Supply Current in Active Mode as a Function of Frequency Note Operating Conditions apply Figure 14 Data Sheet Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters Table 17 Leakage Power Consumption Parameter Symbol Values Unit Note Min Typ Max Test Condition Leakage supply current CC 0 03 0 05 mA T7 25 C DMP_1 powered 05 1 3 mA T 85 C 24 6 2 mA Ty 125 C 4 4 13 7 mA_ Tj 150 C 1 All inputs including pins configured as inputs are set at 0 V to 0 1 V or at Vppp 0 1 V to Vppp and all outputs including pins configured as outputs are disconnected Note A fraction of the leakage current flows through domain DMP_A pin Vppp This current can be calculated as 7 000 x e with a 5 000 273 1 3xT For T 150 C this results in a current of 160 4A The leakage power consumption can be calculated according to the following formulas Tiko 500 000 x e with a 3 000 273 BxT Parameter B must be replaced by 1 0 for typical values 1 6 for maximum values Ij4 600 000 x e with a 5 000 273 BxT Parameter B must be replaced by 1 0 for typical values 1 3 for maximum values Data Sheet 84 V2 1 2011 07 XC2765X XC2000 Family Base Line Infineon Electrical Parameters Jikimax M
20. On Reset Input A low level at this pin resets the XC2765X completely A spike filter suppresses input pulses 10 ns Input pulses gt 100 ns safely pass the filter The minimum duration for a safe recognition should be 120 ns An internal pull up device will hold this pin high when nothing is driving it Data Sheet 36 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 98 ESR1 00 1 SUB External Service Request 1 After power up an internal weak pull up device holds this pin high when nothing is driving it RxDCOE SUB CAN Node 0 Receive Data Input U1CO DXOF I SUB USIC1 Channel 0 Shift Data Input U1CO DX2C I SUB USIC1 Channel 0 Shift Control Input U1C1 DXOC I SUB USIC1 Channel 1 Shift Data Input U1C1 DX2B SUB USIC1 Channel 1 Shift Control Input U2C1 DX2C I SUB USIC2 Channel 1 Shift Control Input 99 ESRO 00 1 St B_ External Service Request 0 After power up ESRO operates as open drain bidirectional reset with a weak pull up U1CO DXOE SUB USIC1 Channel 0 Shift Data Input U1CO DX2B I SUB USIC1 Channel 0 Shift Control Input 10 Voom PS M Digital Core Supply Voltage for Domain M Decouple with a ceramic capacitor see Data Sheet for details 38 Vppu PS 1 Digital Core Supply Voltage for Domain 1 64 Decouple with a ceramic capacitor
21. SUB CCU60 Position Input 2 OS2A TCK B IH SUB DAPO JTAG Clock Input If JTAG pos B is selected during start up an internal pull up device will hold this pin high when nothing is driving it If DAP pos 1 is selected during start up an internal pull down device will hold this pin low when nothing is driving it TSINB l SUB GPT12E Timer T3 Count Gate Input Data Sheet 31 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 81 P1 1 O0O I SUB Bit 1 of Port 1 General Purpose Input Output CCU62 COU O1 SUB CCU62 Channel 2 Output T62 U1CO SELO O2 St B USIC1 Channel 0 Select Control 5 Output 5 U2C1 DOUT O3S SUB USIC2 Channel 1 Shift Data Output A9 OH SUB External Bus Interface Address Line 9 ESR2 3 SUB ESR2 Trigger Input 3 U2C1 DXOC I SUB USIC2 Channel 1 Shift Data Input 82 P10 10 O0 I StB Bit 10 of Port 10 General Purpose Input Output UOCO SELO 01 SUB USICO Channel 0 Select Control 0 Output 0 CCU60 COU O2 St B CCU60 Channel 3 Output T63 AD10 OH SUB External Bus Interface Address Data Line 10 IH UOCO DX2C I SUB USICO Channel 0 Shift Control Input UOC1 DX4A I SUB USICO Channel 1 Shift Clock Input TDI B IH SUB JTAG Test Data Input If JTAG pos B is selected during start up an internal pull up d
22. Select 0 Output Data Sheet 21 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 43 P2 3 O0 I SUB Bit 3 of Port 2 General Purpose Input Output UOCO DOUT O1 St B USICO Channel 0 Shift Data Output CCU63 COU O2 SUB CCU63 Channel 3 Output T63 CC2 CC16 0O3 I SUB CAPCOM 2 CC161O Capture Inp Compare Out A16 OH SUB External Bus Interface Address Line 16 ESR2 0 SUB ESR2 Trigger Input 0 UOCO DXOE SUB USICO Channel 0 Shift Data Input UOC1 DXOD SUB USICO Channel 1 Shift Data Input RxDCOA l SUB CAN Node 0 Receive Data Input 44 P4 1 O0O I SUB Bit 1 of Port 4 General Purpose Input Output CC2 CC25 03 1 St B CAPCOM2 CC25IO Capture Inp Compare Out CS1 OH SUB External Bus Interface Chip Select 1 Output CCU62 CCP I SUB CCU62 Position Input 0 OSOB T4EUDB SUB GPT12E Timer T4 External Up Down Control Input ESR1_8 SUB ESR1 Trigger Input 8 45 P2 4 00 1 St B Bit 4 of Port 2 General Purpose Input Output UOC1 DOUT 01 St B USICO Channel 1 Shift Data Output TxDCO O2 SUB CAN Node 0 Transmit Data Output CC2 CC17 03 1 St B CAPCOM2 CC17I0 Capture Inp Compare Out A17 OH SUB External Bus Interface Address Line 17 ESR1 0 SUB ESR1 Trigger Input 0 UOCO DXOF SU B USICO Channel
23. Sept 2 4 Basic Clock Interrupt Request Aux Timer T2 T2IRQ TN J T2 Mode T2EUD J gt Contro 2024 Capture Interrupt gt Request T3IRQ T3 TN J Mode i rsour Control Capture TAN J T4 _ Mode Interrupt T4EUD Control Aux Timer T4 gt Request T4IRQ MC_GPT_BLOCK1 Figure 8 Block Diagram of GPT1 Data Sheet 56 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description With its maximum resolution of 2 system clock cycles the GPT2 module provides precise event control and time measurement It includes two timers T5 T6 and a capture reload register CAPREL Both timers can be clocked with an input clock which is derived from the CPU clock via a programmable prescaler or with external signals The counting direction up down for each timer can be programmed by software or altered dynamically with an external signal on a port pin TXEUD Concatenation of the timers is supported with the output toggle latch T6OTL of timer T6 which changes its state on each timer overflow underflow The state of this latch may be used to clock timer T5 and or it may be output on pin T6OUT The overflows underflows of timer T6 can also be used to clock the CAPCOM2 timers and to initiate a reload from the CAPREL register The CAPREL register can capture the contents of timer T5 based on an external signal transition on the
24. Sheet CAPCOM2 Unit Block Diagram 52 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 9 Capture Compare Units CCU6x The XC2765X types feature the CCU60 CCU61 CCU62 and CCU63 unit s The CCU6 is a high resolution capture and compare unit with application specific modes It provides inputs to start the timers synchronously an important feature in devices with several CCU6 modules The module provides two independent timers T12 T13 that can be used for PWM generation especially for AC motor control Additionally special control modes for block commutation and multi phase machines are supported Timer 12 Features Three capture compare channels where each channel can be used either as a capture or as a compare channel Supports generation of a three phase PWM six outputs individual signals for high side and low side switches 16 bit resolution maximum count frequency peripheral clock Dead time control for each channel to avoid short circuits in the power stage Concurrent update of the required T12 13 registers Center aligned and edge aligned PWM can be generated Single shot mode supported Manyinterrupt request sources Hysteresis like control mode Automatic start on a HW event T12HR for synchronization purposes Timer 13 Features One independent compare channel with one output 16 bit resolution maximum count frequency peripheral c
25. and Port 6 Power domain B Vpppg supplies the on chip EVVRs and all other ports During operation domain A draws a maximum current of 1 5 mA for each active A D converter module from Vpppa In Fast Startup Mode with the Flash modules deactivated the typical current is reduced to 3 0 6xfgyg mA Data Sheet 82 V2 1 2011 07 XC2765X XC2000 Family Base Line Electrical Parameters MC XC2XM IS V2 1 2011 07 83 Infineon x o I lt E Z n A A EE F N TN 3 DO T y eM MAS aa S 1 1 1 1 BJ 1 1 1 1 1 1 I LN I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EN V o T P E ees NU MESES d r 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 I I 1 1 I 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 o BH w ta qp mm oe rN pore Eom 1 D t 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EM 0 E v 4 1 1 1 1 1 I 1 1 1 1 1 1 1 1 1 1 EM 0 Sw NE ita NE E ae eae ges aioe Canine ees re cem dones N 1 1 1 1 1 1 1 1 q 1 1 1 1 1 1 1 1 1 i 1 1 1 1 1 1 1 1 1 1 EE 5 00 0 0 0 ENA r i 1 1 I 1 I 1 1 1 1 lt M 5 00 0 0 j EREE 0 0 0 0 0 MM 0 0 0 0 00 EN E i i i i i i i i i at tt tt Ht Ht Ht eo e eo o eo eo e o e eo e o ceo
26. banks Fast context switching support with two additional local register banks 16 Mbytes total linear address space for code and data 1024 Bytes on chip special function register area C166 Family compatible Integrated Memory Protection Unit MPU Interrupt system with 16 priority levels for up to 96 sources Selectable external inputs for interrupt generation and wake up Fastest sample rate 12 5 ns Eight channel interrupt driven single cycle data transfer with Peripheral Event Controller PEC 24 bit pointers cover total address space Clock generation from internal or external clock sources using on chip PLL or prescaler Hardware CRC Checker with Programmable Polynomial to Supervise On Chip Memory Areas On chip memory modules 8 Kbytes on chip stand by RAM SBRAM 2 Kbytes on chip dual port RAM DPRAM Up to 16 Kbytes on chip data SRAM DSRAM Up to 32 Kbytes on chip program data SRAM PSRAM Up to 832 Kbytes on chip program memory Flash memory Memory content protection through Error Correction Code ECC On Chip Peripheral Modules Multi functional general purpose timer unit with 5 timers 16 channel general purpose capture compare unit CAPCOM2 Up to 4 capture compare units for flexible PWM signal generation CCU6x Data Sheet 7 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Summary of Features Two Synchronizable A D Converters with a total of up to 16 channe
27. cannot vary across the full operating voltage range Because of the supply voltage restriction and because electrical behavior depends on the supply voltage the parameters are specified separately for the upper and the lower voltage range During operation the supply voltages may only change with a maximum speed of dV dt lt 1 V ms During power on sequences the supply voltages may only change with a maximum speed of dV dt 5 V us i e the target supply voltage may be reached earliest after approx 1 us Note To limit the speed of supply voltage changes the employment of external buffer capacitors at pins V pppA V pppg iS recommended Data Sheet 75 V2 1 2011 07 oS XC2765X Infineon XC2000 Family Base Line Electrical Parameters Pullup Pulldown Device Behavior Most pins of the XC2765X feature pullup or pulldown devices For some special pins these are fixed for the port pins they can be selected by the application The specified current values indicate how to load the respective pin depending on the intended signal level Figure 13 shows the current paths The shaded resistors shown in the figure may be required to compensate system pull currents that do not match the given limit values VopP Pullup l Puldow y I Vss e f MC XC2X PULL Figure 13 Pullup Pulldown Current Definition Data Sheet 76 V2 1 2011 07 e XC2765X Infineon XC2000 Fa
28. conditions Precondition The Stopover mode has been entered using the procedure defined in the Programmer s Guide Start condition Pin toggle on ESR pin triggering the startup sequence End condition External pin toggle caused by first user instruction executed from PSRAM after startup Coding of bit fields LEVxV in SWD and PVC Configuration Registers Table 21 Coding of bit fields LEVxV in Register SWDCONO Code Default Voltage Level Notes 0000 2 9V 0001 3 0 V LEV1V reset request 0010 3 1V 0011 3 2 V 01005 3 3 V 0101 3 4 V 0110 3 6 V 0111 4 0V 1000 4 2 V Data Sheet 91 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters Table 21 Coding of bit fields LEVxV in Register SWDCONO cont d Code Default Voltage Level Notes 1001 4 5V LEV2V no request 1010 4 6V 1011 4 7 V 1100g 4 8 V 11015 4 9 V 1110 5 0 V 1111 5 5 V 1 The indicated default levels are selected automatically after a power reset Table 22 Coding of Bitfields LEVxV in Registers PVCyCONz Code Default Voltage Level Notes 000g 0 95 V 001 1 05 V 010 1 15 V 011g 1 25 V 100g 1 35 V LEV1V reset request 101 1 45V LEV2V interrupt request 110 1 55 V 111 1 65 V 1 The indicated default levels are selected automatically after a power reset 2 Due to variations
29. in Table 5 Analog input channels are listed for each Analog Digital Converter module separately ADCO ADC1 wo m EN Data Sheet 9 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Summary of Features 1 2 Special Device Types Special device types are only available for high volume applications on request Table 2 Synopsis of XC2765X Special Device Types Derivative Flash PSRAM Capt Comp ADC Interfaces Memory DSRAM Modules Chan XC2765X 576 Kbytes 32 Kbytes CC2 114 5 2 CAN Nodes 72FxxL 16 Kbytes CCU60 1 2 38 6 Serial Chan 1 xxis a placeholder for the available speed grade in MHz Specific information about the on chip Flash memory in Table 3 3 All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM Specific information about the available channels in Table 5 Analog input channels are listed for each Analog Digital Converter module separately ADCO ADC1 Data Sheet 10 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Summary of Features 1 3 Definition of Feature Variants The XC2765X types are offered with several Flash memory sizes Table 3 describes the location of the available memory areas for each Flash memory size Table 3 Flash Memory Allocation Total Flash Size Flash Area A Flash Area B Flash Area C 832 Kbytes C0 0000 C1 0000 n a CO EFFF CC FFFF 57
30. incorrect data or executing incorrect instructions The ECC mechanism can detect and automatically correct single bit errors This supports the stable operation of the system It is strongly recommended to activate the ECC mechanism wherever possible because this dramatically increases the robustness of an application against such soft errors 1 To save control bits sectors are clustered for protection purposes they remain separate for programming erasing Data Sheet 43 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 2 External Bus Controller All external memory access operations are performed by a special on chip External Bus Controller EBC The EBC also controls access to resources connected to the on chip LXBus MultiCAN and the USIC modules The LXBus is an internal representation of the external bus that allows access to integrated peripherals and modules in the same way as to external components The EBC can be programmed either to Single Chip Mode when no external memory is required or to an external bus mode with the following selections Address Bus Width with a range of 0 24 bit Data Bus Width 8 bit or 16 bit Bus Operation Multiplexed or Demultiplexed The bus interface uses Port 10 and Port 2 for addresses and data In the demultiplexed bus modes the lower addresses are output separately on Port 0 and Port 1 The number of active segment address lines is se
31. package is optimized for the device it houses Therefore there may be slight differences between packages of the same pin count but for different device types In particular the size of the Exposed Pad if present may vary If different device types are considered or planned for an application it must be ensured that the board layout fits all packages under consideration Data Sheet 124 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Package and Reliability Package Outlines fmm 7 0 5 los 0 15 gip 0 08 C 100x 7 22 0 05 0 22 20 09 lt 0 08 8 A B D C 100x 16 ij T 0 2 A B D 100x Bottom View 7 150 2 A B D H 4x Ex D t AAAAARRARARAJAAARAARARARE T T ibi o o bbb AR A E i E 8 i 9 Ali E B 2 A 1 B E Oo o 100 100 rum HUTETEETEHE EEE EE pg Index Marking Exposed Diepad 1 Does not include plastic or metal protrusion of 0 25 max per side PG LQFP 100 3 4 8 PO V11 Figure 32 PG LQFP 100 8 Plastic Green Thin Quad Flat Package All dimensions in mm You can find complete information about Infineon packages packing and marking in our Infineon Internet Page Packages htip www infineon com packages Data Sheet 125 V2 1 2011 07
32. pin high when nothing is driving it If DAP pos 0 is selected during start up an internal pull down device will hold this pin low when nothing is driving it 58 P0 2 O0O I SUB Bit 2 of Port 0 General Purpose Input Output U1CO SCLK O1 SUB USIC1 Channel 0 Shift Clock Output OUT TxDCO O2 SUB CAN Node 0 Transmit Data Output CCU61 CC6 OS St B CCU61 Channel 2 Output 2 A2 OH SUB External Bus Interface Address Line 2 U1CO DX1B I SUB USIC1 Channel 0 Shift Clock Input CCU61 CC6 SUB CCU61 Channel 2 Input 2INA Data Sheet 25 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 59 P10 0 O0 I SUB Bit 0 of Port 10 General Purpose Input Output UOC1 DOUT 01 St B USICO Channel 1 Shift Data Output CCU60 CC6 O2 St B CCU60 Channel 0 Output 0 ADO OH St B External Bus Interface Address Data Line 0 IH CCU60 CO6 I SUB CCU60 Channel 0 Input OINA ESR1_2 SUB ESR1 Trigger Input 2 UOCO DXOA I St B USICO Channel 0 Shift Data Input UOC1 DXOA I StI B USICO Channel 1 Shift Data Input 60 P10 1 O0 I SUB Bit 1 of Port 10 General Purpose Input Output UOCO DOUT 01 SUB USICO Channel 0 Shift Data Output CCU60 CC6 O2 SUB CCU60 Channel 1 Output 1 AD1 OH St B External Bus Interface Address Data
33. see Data 88 Sheet for details All V5pi pins must be connected to each other 14 Voppa PS A Digital Pad Supply Voltage for Domain A Connect decoupling capacitors to adjacent Vppe Vss pin pairs as close as possible to the pins Note The A D Converters and ports P5 P6 and P15 are fed from supply voltage V ppp Data Sheet 37 V2 1 2011 07 oS XC2765X Infineon XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 2 Vopps PS B Digital Pad Supply Voltage for Domain B 25 Connect decoupling capacitors to adjacent 27 Vbpp Vss pin pairs as close as possible to the pins Note The on chip voltage regulators and all ports except P5 P6 and P15 are fed from supply 75 voltage Vpppg 77 ge V pppg 100 1 Vas PS Digital Ground 26 All Vas pins must be connected to the ground line 51 or ground plane 76 Note Also the exposed pad is connected internally to Vss To improve the EMC behavior it is recommended to connect the exposed pad to the board ground For thermal aspects please refer to the Data Sheet Board layout examples are given in an application note 1 To generate the reference clock output for bus timing measurement fsys must be selected as source for EXTCLK and P2 8 must be selected as output pin Also the high speed clock pad must be enabled This configuration is referred
34. standard operating conditions are exceeded i e the voltage on any pin exceeds the specified range Voy gt Vihmax loy gt 0 or Voy lt Vilmin oy lt 0 The absolute sum of input overload currents on all pins may not exceed 50 mA The supply voltages must remain within the specified limits Proper operation under overload conditions depends on the application Overload conditions must not occur on pin XTAL1 powered by Vppiy An overload current Joy through a pin injects a certain error current Jy into the adjacent pins This error current adds to the respective pins leakage current 57 The amount of error current depends on the overload current and is defined by the overload coupling factor Koy The polarity of the injected error current is inverse compared to the polarity of the overload current that produces it The total current through a pin is o7 ozl Hoy Koy The additional error current may distort the input voltage on analog inputs Value is controlled by on chip regulator Data Sheet 73 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 1 3 Pad Timing Definition If not otherwise noted all timing parameters are tested and are valid for the corresponding output pins operating in strong driver fast edge mode See also Pad Properties on Page 103 4 1 4 Parameter Interpretation The parameters listed in the following include both the characteristics of the XC2765X a
35. with a selectable data word width from 1 to 16 bits in each of the following protocols UART asynchronous serial channel module capability maximum baud rate fays 4 data frame length programmable from 1 to 63 bits MSB or LSB first LIN Support Local Interconnect Network module capability maximum baud rate fays 16 checksum generation under software control baud rate detection possible by built in capture event of baud rate generator SSC SPI synchronous serial channel with or without data buffer module capability maximum baud rate fsys 2 limited by loop delay number of data bits programmable from 1 to 63 more with explicit stop condition MSB or LSB first optional control of slave select signals IC Inter IC Bus supports baud rates of 100 kbit s and 400 kbit s IIS Inter IC Sound Bus module capability maximum baud rate fsys 2 Note Depending on the selected functions such as digital filters input synchronization stages sample point adjustment etc the maximum achievable baud rate can be limited Please note that there may be additional delays such as internal or external propagation delays and driver delays e g for collision detection in UART mode for IIC etc Data Sheet 63 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 14 MultiCAN Module The MultiCAN module contains independently operating
36. 0 Shift Data Input RxDC1A SUB CAN Node 1 Receive Data Input Data Sheet 22 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 46 P2 5 O0 I SUB Bit 5 of Port 2 General Purpose Input Output UOCO SCLK O1 St B USICO Channel 0 Shift Clock Output OUT TxDCO O2 SUB CAN Node 0 Transmit Data Output CC2 CC18 0O3 I SUB CAPCOM2 CC181O Capture Inp Compare Out A18 OH SUB External Bus Interface Address Line 18 UOCO DXID St B USICO Channel 0 Shift Clock Input ESR1 10 l St B ESR1 Trigger Input 10 47 P4 2 O0 I SUB Bit 2 of Port 4 General Purpose Input Output CC2 CC26 10O3 I SUB CAPCOM2 CC2610 Capture Inp Compare Out CS2 OH SUB External Bus Interface Chip Select 2 Output T2INA SUB GPT12E Timer T2 Count Gate Input CCU62 CCP I SUB CCU62 Position Input 1 OS1B 48 P2 6 00 1 St B Bit 6 of Port 2 General Purpose Input Output UOCO SELO 0O1 SUB USICO Channel 0 Select Control 0 Output 0 UOC1 SELO C2 SUB USICO Channel 1 Select Control 1 Output 1 CC2 CC19 0O3 I SUB CAPCOM2 CC191O Capture Inp Compare Out A19 OH SUB External Bus Interface Address Line 19 UOCO DX2D I SUB USICO Channel 0 Shift Control Input RxDCOD SUB CAN Node 0 Receive Data Input ESR2 6 SUB ESR2 Trigger Input
37. 1 Channel 1 Shift Data Input CCU61_CTR I SUB CCU61 Emergency Trap Input APA U1C1 DX1B St B USIC1 Channel 1 Shift Clock Input 72 P10 6 O0 I SUB Bit 6 of Port 10 General Purpose Input Output UOCO DOUT O1 SU B USICO Channel 0 Shift Data Output U1CO SELO O3 SUB USIC1 Channel 0 Select Control 0 Output 0 AD6 OH St B External Bus Interface Address Data Line 6 IH UOCO DXOC I SUB USICO Channel 0 Shift Data Input U1CO DX2D I SUB USIC1 Channel 0 Shift Control Input CCU60_CTR I SUB CCU60 Emergency Trap Input APA Data Sheet 29 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 73 P10 7 O0 I SUB Bit 7 of Port 10 General Purpose Input Output UOC1 DOUT O1 St B USICO Channel 1 Shift Data Output CCU60 COU O2 SUB CCU60 Channel 3 Output T63 AD7 OH St B External Bus Interface Address Data Line 7 IH UOC1 DXOB SUB USICO Channel 1 Shift Data Input CCU60 CCP I SUB CCU60 Position Input 0 OSO0A T4INB l SUB GPT12E Timer T4 Count Gate Input 74 PO 7 00 1 St B Bit 7 of Port 0 General Purpose Input Output U1C1 DOUT O1 SUB USIC1 Channel 1 Shift Data Output U1CO SELO C2 SUB USIC1 Channel 0 Select Control 3 Output 3 A7 OH SUB External Bus Interface Address Line 7 U1C1 DXOB I SUB USIC1 Channel 1 Shift Data Input CCU6
38. 11 ns Data output hold time for t CC 3 6 8 ns D15 DO and AD15 ADO Input setup time for fy SR 25 15 ns READY D15 DO AD15 ADO Input hold time READY t SR O 7 ns D15 DO AD15 ADO 1 Read data are latched with the same internal change after the rising edge of RD Data Sheet clock edge that triggers the address change and the rising edge of RD Address changes before the end of RD have no impact on demultiplexed read cycles Read data can V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Table 31 EBC External Bus Timing for Lower Voltage Range Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Output valid delay for RD o CC 11 20 ns WR L H Output valid delay for t4 CC 10 21 ns BHE ALE Address output valid delay t CC 11 22 ns for A23 A0 Address output valid delay 5 4 CC 10 22 ns for AD15 ADO MUX mode Output valid delay for CS 44CC 10 13 ns Data output valid delay for ti CC 10 22 ns AD15 ADO write data MUX mode Data output valid delay for ti CC 10 22 ns D15 DO write data DEMUX mode Output hold time for RD t CC 2 8 10 ns WR L H Output hold time for BHE t CC 2 8 10 ns ALE Address output hold time t 4 CC 3 8 10 ns for AD15 ADO Output hold time for CS t CC
39. 12E Timer T3 Toggle Latch Output T6OUT O2 SUB GPT12E Timer T6 Toggle Latch Output TDO A OH SUB JTAG Test Data Output DAP1 Input Output IH If DAP pos 0 or 2 is selected during start up an internal pull down device will hold this pin low when nothing is driving it ESR2 1 SUB ESR2 Trigger Input 1 7 P7 3 00 1 St B Bit 3 of Port 7 General Purpose Input Output EMUX1 O1 SUB External Analog MUX Control Output 1 ADC1 UOC1 DOUT O2 SUB USICO Channel 1 Shift Data Output UOCO DOUT O3 St B USICO Channel 0 Shift Data Output CCU62 CCP SUB CCU62 Position Input 1 OS1A TMS C IH SUB JTAG Test Mode Selection Input If JTAG pos C is selected during start up an internal pull up device will hold this pin low when nothing is driving it UOC1 DXOF I SUB USICO Channel 1 Shift Data Input 8 P7 1 00 1 St B Bit 1 of Port 7 General Purpose Input Output EXTCLK O1 SUB Programmable Clock Signal Output CCU62_CTR I SUB CCU62 Emergency Trap Input APA BRKIN C SUB OCDS Break Signal Input Data Sheet 16 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 9 P7 4 00 1 St B Bit 4 of Port 7 General Purpose Input Output EMUX2 O1 SUB External Analog MUX Control Output 2 ADC1 UOC1 DOUT O2 SUB USICO Channel 1 Shift Dat
40. 1_CTR I SUB CCU61 Emergency Trap Input APB 78 P1 0 O0 I SUB Bit 0 of Port 1 General Purpose Input Output U1CO MCLK O1 SUB USIC1 Channel 0 Master Clock Output OUT U1CO SELO C2 SUB USIC1 Channel 0 Select Control 4 Output 4 A8 OH SUB External Bus Interface Address Line 8 ESR1 3 SUB ESR1 Trigger Input 3 CCU62_CTR I SUB CCU62 Emergency Trap Input APB T6INB SUB GPT12E Timer T6 Count Gate Input Data Sheet 30 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 79 P10 8 O0 I SUB Bit 8 of Port 10 General Purpose Input Output UOCO MCLK O1 SUB USICO Channel 0 Master Clock Output OUT UOC1 SELO O2 St B USICO Channel 1 Select Control 0 Output 0 U2C1 DOUT O3 St B USIC2 Channel 1 Shift Data Output AD8 OH Si B External Bus Interface Address Data Line 8 IH CCU60 CCP SUB CCU60 Position Input 1 OS1A UOCO DX1C I SUB USICO Channel 0 Shift Clock Input BRKIN B SUB OCDS Break Signal Input TSEUDB SUB GPT12E Timer T3 External Up Down Control Input 80 P10 9 O0 I SUB Bit 9 of Port 10 General Purpose Input Output UOCO SELO 01 SUB USICO Channel 0 Select Control 4 Output 4 UOC1 MCLK O2 St B USICO Channel 1 Master Clock Output OUT AD9 OH St B External Bus Interface Address Data Line 9 IH CCU60 CCP
41. 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters Table 14 DC Characteristics for Upper Voltage Range cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Output Low Voltage Vg CC 1 0 M Io S Ioma 0 4 V Io Sdn 1 2 2 Bed S Because each double bond pin is connected to two pads standard pad and high speed pad it has twice the normal value For a list of affected pins refer to the pin definitions table in chapter 2 Not subject to production test verified by design characterization Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It cannot suppress switching due to external system noise under all conditions If the input voltage exceeds the respective supply voltage due to ground bouncing Vin lt Vss or supply ripple Vin gt Vppp a certain amount of current may flow through the protection diodes This current adds to the leakage current An additional error current j will flow if an overload current flows through an adjacent pin Please refer to the definition of the overload coupling factor Koy The given values are worst case values In production test this leakage current is only tested at 125 C other values are ensured by correlation For derating please refer to the following descriptions Leakage derating depending on temperature T junction temp
42. 58 x K2 x T 1 0 83 x fays 1 0 058 x K2 fsvs in MHz in all formulas Example for a period of 3 TCSs 33 MHz and K2 4 Dmax t 220 4 x 33 4 3 5 97 ns Not applicable directly in this case D 5 97 x 1 0 058 x 4 x 3 1 0 83 x 33 1 0 058 x 4 5 97 x 0 768 x 2 26 39 0 232 1 7 ns Example for a period of 3 TCSs 33 MHz and K2 2 Dmax 220 2 x 33 4 3 7 63 ns Not applicable directly in this case D 7 63 x 1 0 058 x 2 x 3 1 0 83 x 33 1 0 058 x 2 7 63 x 0 884 x 2 26 39 0 116 1 4ns Data Sheet 98 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters Acc jitter Dr Ans 9 ai 84 7 167 57 47 34 24 i fevs 33 MHz fsys 66 MHz fico 66 MHz On Cycles T 20 40 60 80 100 MC XC2X JITTER Figure 20 Approximated Accumulated PLL Jitter Note The specified PLL jitter values are valid if the capacitive load per pin does not exceed C 20 pF The maximum peak to peak noise on the pad supply voltage measured between Vpppg pin 100 and Vss pin 1 is limited to a peak to peak voltage of Vpp 50 mV This can be achieved by appropriate blocking of the supply voltage as close as possible to the supply pins and using PCB supply and ground planes Data Sheet 99 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters PL
43. 6 Kbytes C0 0000 C1 0000 CC 0000 CO EFFF C7 FFFF CC FFFF 1 The uppermost 4 Kbyte sector of the first Flash segment is reserved for internal use CO F000 to CO FFFF Table 4 Flash Memory Module Allocation in Kbytes Total Flash Size Flash 0 Flash 1 Flash 2 Flash 3 832 Kbytes 256 256 256 64 576 Kbytes 256 256 64 1 The uppermost 4 Kbyte sector of the first Flash segment is reserved for internal use CO F000 to CO FFFF The XC2765X types are offered with different interface options Table 5 lists the available channels for each option Table 5 Total Number 11 ADCO channels 5 ADC1 channels 2 CAN nodes Interface Channel Association Available Channels CHO CH2 CH5 CH8 CH11 CH13 CH15 CHO CH2 CH4 CH5 CH6 overlay CH8 CH11 CANO CAN1 128 message objects UOCO UOC1 U1C0 U1C1 U2CO0 U2C1 6 serial channels Data Sheet 11 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Summary of Features The XC2765X types are offered with several SRAM memory sizes Figure 1 shows the allocation rules for PSRAM and DSRAM Note that the rules differ PSRAM allocation starts from the lower address DSRAM allocation starts from the higher address For example 8 Kbytes of PSRAM will be allocated at E0 0000h E0 1FFFh and 8 Kbytes of DSRAM will be at 00 C000h 00 DFFFh E7 FFFFh EF
44. 65X Infineon XC2000 Family Base Line Table of Contents Table of Contents n On 4 1 4 1 1 4 1 2 4 1 3 4 1 4 4 2 4 2 1 4 2 2 4 2 3 4 3 4 4 Data Sheet Summary of Features 0 00 c eee tae 7 Basic Device Types eresien ii 2 0 eee eee eee eee 9 Special Device Types 0 ccc eee ttt 10 Definition of Feature Variants 0000 eee eee 11 General Device Information 0 000 e eens 13 Pin Configuration and Definition 00000 c eee eee 14 Identification Registers liliis 39 Functional Description 0 cee eee 40 Memory Subsystem and Organization 00000 eee eee 41 External Bus Controller llle 44 Central Processing Unit CPU lsllseieeeeeeeen 45 Memory Protection Unit MPU 00 0 0 0c eee n 47 Memory Checker Module MCHK 0000 e eee eee eee 47 Interrupt System sense perpe Dec Gat pada edna eth gale bes 48 On Chip Debug Support OCDS 2 20 00 eee eee 49 Capture Compare Unit CAPCOM2 00 00 cee eee 50 Capture Compare Units CCU6X 2 2 e eee 53 General Purpose Timer GPT12E Unit 0000000 55 Real Time Clock aiccc2 5 eee icis bebe sees dae dave y eee es on 59 A D GONVETEIS susto t EnaA ea EU duda aes oe os 61 Universal Serial Interface Channel Modules USIC 62 MultiCAN Module 0 000 e cece 64 S
45. 94 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 AC Parameters These parameters describe the dynamic behavior of the XC2765X 4 6 1 Testing Waveforms These values are used for characterization and production testing except pin XTAL1 Output delay Output delgy Hold time Hold time 0 8 Vopp 0 7 Vopp Input Signal driven by tester 0 3 Vpop 0 2 Vpop Output Signal L2l22 4 measured a E Output timings refer to the rising edge of CLKOUT Input timings are calculated from the time when the input signal reaches V4 or V respectively MCD05556C Figure 17 Input Output Waveforms Voag 0 1 V Voy 0 1 V Timing Reference Points V 0 1 V Vg 01V Load For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs but begins to float when a 100 mV change from the loaded Vop Vo level occurs loy Io 20 mA MCA05565 Figure 18 Floating Waveforms Data Sheet 95 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 2 Definition of Internal Timing The internal operation of the XC2765X is controlled by the internal system clock fsys Because the system clock signal fsys can be generated from a number of internal and external sources using different mechanisms the duration of the system clock peri
46. FFFFh 00 DFFFh Reserved for PSRAM Available DSRAM Available PSRAM Reserved for DSRAM E0 0000h MC XC SRAM ALLOCATION Figure 1 SRAM Allocation Data Sheet 12 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line General Device Information 2 General Device Information The XC2765X series 16 32 Bit Single Chip Microcontroller with 32 Bit Performance is a part of the Infineon XC2000 Family of full feature single chip CMOS microcontrollers These devices extend the functionality and performance of the C166 Family in terms of instructions MAC unit peripherals and speed They combine high CPU performance up to 80 million instructions per second with extended peripheral functionality and enhanced IO capabilities Optimized peripherals can be adapted flexibly to meet the application requirements These derivatives utilize clock generation via PLL and internal or external clock sources On chip memory modules include program Flash program RAM and data RAM VareFVacnn Voom Voon Vpop Vss 0 0 0 3 9 4 Port 0 XTAL1 8 bit XTAL2 drin Port 1 ESRO 8 bit Port 2 Port 10 Tibit 16 bit Port 6 Port15 2 bit 2 bit Port 7 7 bit PORST TRST DAP JTAG Debug TESTM l ec at zu via Port Pins MC XY LOGSYMB 100 Figure 2 XC2765X Logic Symbol Data Sheet 13 V2 1 2011 07 Cinfineon 2 1 XC2765X XC2000 Family Base Line Pin Configuration and Definition General D
47. Gatineon 16 32 Bit Architecture XC2765X 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2000 Family Base Line Data Sheet V2 1 2011 07 Microcontrollers Edition 2011 07 Published by Infineon Technologies AG 81726 Munich Germany 2011 Infineon Technologies AG All Rights Reserved Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics With respect to any examples or hints given herein any typical values stated herein and or any information regarding the application of the device Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind including without limitation warranties of non infringement of intellectual property rights of any third party Information For further information on technology delivery terms and conditions and prices please contact the nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact the nearest Infineon Technologies Office Infineon Technologies components may be used in life support devices or systems only with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effecti
48. High Byte WRH Data Sheet 20 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 39 P2 0 00 1 St B_ Bit 0 of Port 2 General Purpose Input Output CCU63_CC6 O2 St B CCU63 Channel 0 Output 0 AD13 OH St B_ External Bus Interface Address Data Line 13 IH RxDCOC SUB CAN Node 0 Receive Data Input CCU63 CO6 I SUB CCU63 Channel 0 Input OINB T5INB SUB GPT12E Timer T5 Count Gate Input 40 P2 1 00 1 St B_ Bit 1 of Port 2 General Purpose Input Output TxDCO O1 SUB CAN Node 0 Transmit Data Output CCU63 CC6 O2 SUB CCU63 Channel 1 Output 1 AD14 OH SU B External Bus Interface Address Data Line 14 IH CCU63 CC6 SUB CCU63 Channel 1 Input 1INB T5EUDB SUB GPT12E Timer T5 External Up Down Control Input ESR1 5 SUB ESR1 Trigger Input 5 41 P2 2 O0 I SUB Bit 2 of Port 2 General Purpose Input Output TxDC1 O1 SUB CAN Node 1 Transmit Data Output CCU63 CC6 O2 SUB CCU63 Channel 2 Output 2 AD15 OH SUB External Bus Interface Address Data Line 15 IH CCU63 CC6 SU B CCU63 Channel 2 Input 2INB ESR2_5 SUB ESR2 Trigger Input 5 42 P4 0 00 1 St B_ Bit 0 of Port 4 General Purpose Input Output CC2 CC24 O3 I SUB CAPCOM2 CC24IO Capture Inp Compare Out cso OH SUB External Bus Interface Chip
49. L frequency band selection Different frequency bands can be selected for the VCO so that the operation of the PLL can be adjusted to a wide range of input and output frequencies Table 24 System PLL Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition VCO output frequency Juco CC 50 110 MHz VCOSEL 00 VSO contelled 100 160 MHz VCOSEL 01 VCO output frequency fuco CC 10 40 MHz VCOSEL 00 VCO free running 20 80 MHz VCOSEL 01 4 6 2 2 Wakeup Clock When wakeup operation is selected SYSCONO CLKSEL 00g the system clock is derived from the low frequency wakeup clock source fsvs fwu In this mode a basic functionality can be maintained without requiring an external clock source and while minimizing the power consumption 4 6 2 3 Selecting and Changing the Operating Frequency When selecting a clock source and the clock generation method the required parameters must be carefully written to the respective bit fields to avoid unintended intermediate states Many applications change the frequency of the system clock fgys during operation in order to optimize system performance and power consumption Changing the operating frequency also changes the switching currents which influences the power supply To ensure proper operation of the on chip EVRs while they generate the core voltage the operating frequency shall only be chan
50. Output T62 A5 OH SUB External Bus Interface Address Line 5 U1C1 DX1A I StI B USIC1 Channel 1 Shift Clock Input U1CO DX1C SU B USIC1 Channel 0 Shift Clock Input 69 P10 4 O0 I SUB Bit 4 of Port 10 General Purpose Input Output UOCO SELO 0O1 SUB USICO Channel 0 Select Control 3 Output 3 CCU60 COU O2 SUB CCU60 Channel 1 Output T61 AD4 OH St B External Bus Interface Address Data Line 4 IH UOCO DX2B I SUB USICO Channel 0 Shift Control Input UOC1 DX2B I SUB USICO Channel 1 Shift Control Input ESR1 9 SUB ESR1 Trigger Input 9 Data Sheet 28 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 70 P10 5 O0 I StB Bit 5 of Port 10 General Purpose Input Output UOC1 SCLK O1 St B USICO Channel 1 Shift Clock Output OUT CCU60 COU O2 SUB CCU60 Channel 2 Output T62 U2CO DOUT O3 StB USIC2 Channel 0 Shift Data Output ADS OH St B External Bus Interface Address Data Line 5 IH UOC1 DX4B I SUB USICO Channel 1 Shift Clock Input 71 P0 6 00 1 St B Bit 6 of Port 0 General Purpose Input Output U1C1 DOUT O1 SUB USIC1 Channel 1 Shift Data Output TxDC1 O2 SUB CAN Node 1 Transmit Data Output CCU61 COU O3 St B CCU61 Channel 3 Output T63 A6 OH SUB External Bus Interface Address Line 6 U1C1 DXOA I SUB USIC
51. P0 1 O0 I SUB Bit 1 of Port 0 General Purpose Input Output U1CO DOUT O1 St B USIC1 Channel 0 Shift Data Output TxDCO O2 SUB CAN Node 0 Transmit Data Output CCU61 CC6 O3 SUB CCU61 Channel 1 Output 1 A1 OH SUB External Bus Interface Address Line 1 U1CO DXOB SUB USIC1 Channel 0 Shift Data Input CCU61 CC6 SUB CCU61 Channel 1 Input 1INA U1CO DX4A I SUB USIC1 Channel 0 Shift Clock Input Data Sheet 24 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 56 P2 8 O0 I DP B Bit 8 of Port 2 General Purpose Input Output UOC1 SCLK O1 DP B USICO Channel 1 Shift Clock Output OUT EXTCLK 02 DP B Programmable Clock Signal Output 1 CC2_CC21 03 DP B CAPCOM2 CC211O Capture Inp Compare Out A21 OH DP B External Bus Interface Address Line 21 UOC1 DX1D I DP B USICO Channel 1 Shift Clock Input 57 P2 9 O0O I SUB Bit 9 of Port 2 General Purpose Input Output UOC1 DOUT O1 SUB USICO Channel 1 Shift Data Output TxDC1 O2 SUB CAN Node 1 Transmit Data Output CC2_CC22 O3 I SUB CAPCOM2 CC22I0 Capture Inp Compare Out A22 OH SUB External Bus Interface Address Line 22 CLKIN1 SUB Clock Signal Input 1 TCK_A IH SUB DAPO JTAG Clock Input If JTAG pos A is selected during start up an internal pull up device will hold this
52. PU speed Result data can be reduced by limit checking or accumulation of results The Peripheral Event Controller PEC can be used to control the A D converters or to automatically store conversion results to a table in memory for later evaluation without requiring the overhead of entering and exiting interrupt routines for each data transfer Each A D converter contains eight result registers which can be concatenated to build a result FIFO Wait for read mode can be enabled for each result register to prevent the loss of conversion data In order to decouple analog inputs from digital noise and to avoid input trigger noise those pins used for analog input can be disconnected from the digital input stages This can be selected for each pin separately with the Port x Digital Input Disable registers The Auto Power Down feature of the A D converters minimizes the power consumption when no conversion is in progress Broken wire detection for each channel and a multiplexer test mode provide information to verify the proper operation of the analog signal sources e g a sensor system Data Sheet 61 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 13 Universal Serial Interface Channel Modules USIC The XC2765X features the USIC modules USICO USIC1 USIC2 Each module provides two serial communication channels The Universal Serial Interface Channel USIC module is based on a generic data
53. Single stepping is supported as is the injection of arbitrary instructions and read write access to the complete internal address space A breakpoint trigger can be answered with a CPU halt a monitor call a data transfer or and the activation of an external signal Tracing data can be obtained via the debug interface or via the external bus interface for increased performance Tracing of program execution is supported by the XC2000 Family emulation device The DAP interface uses two interface signals the JTAG interface uses four interface signals to communicate with external circuitry The debug interface can be amended with two optional break lines Data Sheet 49 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 8 Capture Compare Unit CAPCOM2 The CAPCOM2 unit supports generation and control of timing sequences on up to 16 channels with a maximum resolution of one system clock cycle eight cycles in staggered mode The CAPCOM2 unit is typically used to handle high speed I O tasks such as pulse and waveform generation pulse width modulation PWM digital to analog D A conversion software timing or time recording with respect to external events Two 16 bit timers T7 T8 with reload registers provide two independent time bases for the capture compare register array The input clock for the timers is programmable to several prescaled values of the internal system clock or may
54. T valid CC 7 11 ns time Data Sheet 114 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters Table 33 USIC SSC Master Mode Timing for Lower Voltage Range cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Receive data input setup t SR 40 ns time to SCLKOUT receive edge Data input DXO hold time t SR 5 ns from SCLKOUT receive edge 1 tsys 1 fsys Table 34 USIC SSC Slave Mode Timing for Upper Voltage Range Parameter Symbol Values Min Typ Max Unit Note Test Condition Select input DX2 setup to first clock input DX1 transmit edge tio SR ns Select input DX2 hold after last clock input DX1 receive edge t44 SR ns Receive data input setup time to shift clock receive edge ty SR ns Data input DXO hold time from clock input DX1 receive edge 144 SR ns Data output DOUT valid time ty4 CC 33 ns 1 These input timings are valid for asynchronous input signal handling of slave select input shift clock input and receive data input bits DXnCR DSEN 0 Data Sheet 115 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters Table 35 USIC SSC Slave Mode Timing for Lower Voltage Range Parameter Symbol Values Min Ty
55. a Output TDO B OH St B JTAG Test Data Output DAP1 Input Output IH If DAP pos 1 is selected during start up an internal pull down device will hold this pin low when nothing is driving it AD12 OH SUB External Bus Interface Address Data Line 12 IH U1CO DXOC I SUB USIC1 Channel 0 Shift Data Input U1CO DX4E I SUB USIC1 Channel 0 Shift Clock Input 86 P10 13 O0 I StB Bit 13 of Port 10 General Purpose Input Output U1CO DOUT 01 SUB USIC1 Channel 0 Shift Data Output U1CO SELO O3 SUB USIC1 Channel 0 Select Control 3 Output 3 WR WRL OH SUB External Bus Interface Write Strobe Output _ Active for each external write access when WR active for ext writes to the low byte when WRL U1CO DXOD SUB USIC1 Channel 0 Shift Data Input Data Sheet 33 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 87 P1 3 00 1 St B_ Bit 3 of Port 1 General Purpose Input Output CCU62_COU 01 St B CCU62 Channel 3 Output T63 U1CO SELO C2 SUB USIC1 Channel 0 Select Control 7 Output 7 U2CO SELO O3 St B USIC2 Channel 0 Select Control 4 Output 4 A11 OH SUB External Bus Interface Address Line 11 ESR2 4 SUB ESR2 Trigger Input 4 CCU62_T12 SUB External Run Control Input for T12 of CCU62 HRB 89 P10 14 O0 I StB Bit 14 of Port 10 General Pu
56. a Output UOC1 SCLK O3 SUB USICO Channel 1 Shift Clock Output OUT CCU62 CCP SUB CCU62 Position Input 2 OS2A TCK C IH SUB DAPO JTAG Clock Input If JTAG pos C is selected during start up an internal pull up device will hold this pin high when nothing is driving it If DAP pos 2 is selected during start up an internal pull down device will hold this pin low when nothing is driving it UOCO DXOD I SUB USICO Channel 0 Shift Data Input U0C1_DX1E I SUB USICO Channel 1 Shift Clock Input 11 P6 0 O0 1 DA A Bit 0 of Port 6 General Purpose Input Output EMUXO O1 DA A External Analog MUX Control Output 0 ADCO BRKOUT OS DA A OCDS Break Signal Output ADCx_REQG I DA A External Request Gate Input for ADCO 1 TyG U1C1 DXOE I DA A USIC1 Channel 1 Shift Data Input 12 P6 1 00 I DA A Bit 1 of Port 6 General Purpose Input Output EMUX1 O1 DA A External Analog MUX Control Output 1 ADCO T3OUT O2 DA A GPT12E Timer T3 Toggle Latch Output U1C1 DOUT O3 DA A USIC1 Channel 1 Shift Data Output ADCx_REQT I DA A External Request Trigger Input for ADCO 1 RyE ESR1 6 DA A ESR1 Trigger Input 6 Data Sheet 17 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 13 P62 00 1 DAA Bit 2 of Port 6 General Purpose Input Outp
57. a checksum fractional polynomial division on a block of data often called Cyclic Redundancy Code CRC It is based on a 32 bit linear feedback shift register and may therefore also be used to generate pseudo random numbers The Memory Checker Module is a 16 bit parallel input signature compression circuitry which enables error detection within a block of data stored in memory registers or communicated e g via serial communication lines It reduces the probability of error masking due to repeated error patterns by calculating the signature of blocks of data The polynomial used for operation is configurable so most of the commonly used polynomials may be used Also the block size for generating a CRC result is configurable via a local counter An interrupt may be generated if testing the current data block reveals an error An autonomous CRC compare circuitry is included to enable redundant error detection e g to enable higher safety integrity levels The Memory Checker Module provides enhanced fault detection beyond parity or ECC for data and instructions in volatile and non volatile memories This is especially important for the safety and reliability of embedded systems Data Sheet 47 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description 3 6 Interrupt System The architecture of the XC2765X supports several mechanisms for fast and flexible response to service requests these can be gener
58. ains l i i eee eee eee eee eee eee eee ee J MCS05570 Figure 16 Equivalent Circuitry for Analog Inputs Data Sheet 88 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters Sample time and conversion time of the XC2765X s A D converters are programmable The timing above can be calculated using Table 19 The limit values for fapc must not be exceeded when selecting the prescaler value Table 19 A D Converter Computation Table GLOBCTR 5 0 A D Converter INPCRx 7 0 Sample Time DIVA Analog Clock fpc STC ts 000000 favs 004 tanci X 2 000001 fave 2 01 tanci X 3 000010 fave 3 02 tanci X 4 fsys DIVA 1 tanci x STC 2 111110 favs 63 FE tanci X 256 1111115 Jays 64 FF tanci X 257 1 The selected sample time is doubled if broken wire detection is active due to the presampling phase Converter Timing Example A 80 MHZ i e fgyg 12 5 ns DIVA 03 STC 00 fsys 4 20 MHZ i e tapc 50 ns fapci X 2 100 ns Assumptions fsys Analog clock Saoci Sample time ts Conversion 10 bit toig 13 x tang 2 X tsys 13 x 50 ns 2x 12 5 ns 0 675 us Conversion 8 bit tog 11 X tanci 2 X tsys 11 x 50 ns 2x 12 5 ns 0 575 us Converter Timing Example B Assumptions fsys 40 MHz i e tsys 25 ns DIVA 024 STC 03 Analog clock f apci fsys 3 13 3 MHZ i e tapc 75
59. ameters 4 2 3 Power Consumption The power consumed by the XC2765X depends on several factors such as supply voltage operating frequency active circuits and operating temperature The power consumption specified here consists of two components The switching current Z s depends on the device activity The leakage current depends on the device temperature To determine the actual power consumption always both components switching current Is and leakage current 7 must be added Ippp Is liy Note The power consumption values are not subject to production test They are verified by design characterization To determine the total power consumption for dimensioning the external power supply also the pad driver currents must be considered The given power consumption parameters and their values refer to specific operating conditions Active mode Regular operation i e peripherals are active code execution out of Flash Stopover mode Crystal oscillator and PLL stopped Flash switched off clock in domain DMP 1 stopped Note The maximum values cover the complete specified operating range of all manufactured devices The typical values refer to average devices under typical conditions such as nominal supply voltage room temperature application oriented activity After a power reset the decoupling capacitors for V ppm and V ppn are charged with the maximum possible current For additional information please re
60. ands with Carry 2 4 SUB B Subtract word byte operands 2 4 SUBC B Subtract word byte operands with Carry 2 4 MUL U Un Signed multiply direct GPR by direct GPR 2 16 x 16 bit DIV U Un Signed divide register MDL by direct GPR 16 16 bit 2 DIVL U Un Signed long divide reg MD by direct GPR 32 16 bit 2 CPL B Complement direct word byte GPR 2 NEG B Negate direct word byte GPR 2 AND B Bitwise AND word byte operands 2 4 OR B Bitwise OR word byte operands 2 4 XOR B Bitwise exclusive OR word byte operands 2 4 BCLR BSET Clear Set direct bit 2 BMOV N Move negated direct bit to direct bit 4 BAND BOR BXOR AND OR XOR direct bit with direct bit 4 BCMP Compare direct bit to direct bit 4 BFLDH BFLDL Bitwise modify masked high low byte of bit addressable 4 direct word memory with immediate data CMP B Compare word byte operands 2 4 CMPD1 2 Compare word data to GPR and decrement GPR by 1 2 2 4 CMPI1 2 Compare word data to GPR and increment GPR by 1 2 2 4 PRIOR Determine number of shift cycles to normalize direct 2 word GPR and store result in direct word GPR SHL SHR Shift left right direct word GPR 2 Data Sheet 68 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description Table 11 Instruction Set Summary cont d Mnemonic Description Bytes ROL ROR Rotate left right direct word GPR 2 ASHR
61. ated from various sources internal or external to the microcontroller Any of these interrupt requests can be programmed to be serviced by the Interrupt Controller or by the Peripheral Event Controller PEC Where in a standard interrupt service the current program execution is suspended and a branch to the interrupt vector table is performed just one cycle is stolen from the current CPU activity to perform a PEC service A PEC service implies a single byte or word data transfer between any two memory locations with an additional increment of either the PEC source pointer the destination pointer or both An individual PEC transfer counter is implicitly decremented for each PEC service except when performing in the continuous transfer mode When this counter reaches zero a standard interrupt is performed to the corresponding source related vector location PEC services are particularly well suited to supporting the transmission or reception of blocks of data The XC2765X has eight PEC channels each whith fast interrupt driven data transfer capabilities With a minimum interrupt response time of 7 11 CPU clocks the XC2765X can react quickly to the occurrence of non deterministic events Interrupt Nodes and Source Selection The interrupt system provides 96 physical nodes with separate control register containing an interrupt request flag an interrupt enable flag and an interrupt priority bit field Most interrupt sources are assigned to a d
62. ating Conditions cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Absolute sum of overload X oy 50 mA not subject to currents SR production test Digital core supply voltage Vppim 1 5 for domain M9 CC Digital core supply voltage Vopn 1 5 for domain 19 CC Digital supply voltage for Vppp SR 4 5 5 5 V IO pads and voltage regulators Digital ground voltage Vss SR 0 V 1 To ensure the stability of the voltage regulators the EVRs must be buffered with ceramic capacitors Separate buffer capacitors with the recomended values shall be connected as close as possible to each Vopiy and Vpp pin to keep the resistance of the board tracks below 2 Ohm Connect all Vpbp pins together The minimum capacitance value is required for proper operation under all conditions e g temperature Higher values slightly increase the startup time Use one Capacitor for each pin This is the reference load For bigger capacitive loads use the derating factors listed in the PAD properties section The timing is valid for pin drivers operating in default current mode selected after reset Reducing the output current may lead to increased delays or reduced driving capability C The operating frequency range may be reduced for specific device types This is indicated in the device designation FxxL 80 MHz devices are marked F80L Overload conditions occur if the
63. ating Frequency 100 4 6 3 External Clock Input Parameters llis esses 101 4 6 4 Pad Properties cta R Wu ERG PER RR EGRE RE E 103 4 6 5 External Bus Timing sss 106 4 6 5 1 Bus Cycle Control with the READY Input 112 4 6 6 Synchronous Serial Interface Timing 000 cee eee 114 4 6 7 Debug Interface Timing 0 eee ee 118 5 Package and Reliability 0 0 cee eee eee 124 5 1 Packaging ime RUE E de Rad N ERR ganas EENG 124 5 2 Thermal Considerations u llle 126 5 3 Quality Declarations 0 0 0 0 B 127 Data Sheet 6 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Summary of Features 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2765X XC2000 Family 1 Summary of Features For a quick overview and easy reference the features of the XC2765X are summarized here High performance CPU with five stage pipeline and MPU 12 5 ns instruction cycle at 80 MHz CPU clock single cycle execution One cycle 32 bit addition and subtraction with 40 bit result One cycle multiplication 16 x 16 bit Background division 32 16 bit in 21 cycles One cycle multiply and accumulate MAC instructions Enhanced Boolean bit manipulation facilities Zero cycle jump execution Additional instructions to support HLL and operating systems Register based design with multiple variable register
64. be derived from an overflow underflow of timer T6 in module GPT2 This provides a wide range or variation for the timer period and resolution and allows precise adjustments to the application specific requirements In addition an external count input allows event scheduling for the capture compare registers relative to external events The capture compare register array contains 16 dual purpose capture compare registers each of which may be individually allocated to either CAPCOM timer and programmed for capture or compare function All registers have each one port pin associated with it which serves as an input pin for triggering the capture function or as an output pin to indicate the occurrence of a compare event When a capture compare register has been selected for capture mode the current contents of the allocated timer will be latched captured into the capture compare register in response to an external event at the port pin which is associated with this register In addition a specific interrupt request for this capture compare register is generated Either a positive a negative or both a positive and a negative external signal transition at the pin can be selected as the triggering event The contents of all registers which have been selected for one of the five compare modes are continuously compared with the contents of the allocated timers When a match occurs between the timer value and the value in a capture compare reg
65. ced internal bus structure of the XC2765X EA Support apo EBC K_ _ _ LXBus Control External Bus Control mac unit Unit k System Functions Clock Reset Power meu n m PEC E RT Control StandBy RAM Interrupt Bus Peripheral Data Bus Rm d MC BL BLOCKDIAGRAM Figure 4 Block Diagram Data Sheet 40 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Functional Description 3 1 Memory Subsystem and Organization The memory space of the XC2765X is configured in the von Neumann architecture In code memory data memory registers and I O ports are organized in the same linear address space this architecture all internal and external resources including Table 8 XC2765X Memory Map Address Area Start Loc End Loc AreaSize Notes IMB register space FFFF00 FFFFFF 256 Bytes i Reserved Access trap F0 0000 FF FEFF lt 1 Mbyte Minus IMB registers Reserved for EPSRAM E8 8000 EF FFFF 480 Kbytes Mirrors EPSRAM Emulated PSRAM E8 0000 E8 7FFF 32 Kbytes With Flash timing Reserved for PSRAM E0 8000 E7 FFFF 480 Kbytes Mirrors PSRAM Program SRAM E0 0000 E0 7FFF 32 Kbytes Maximum speed Reserved for Flash CD 0000 DF FFFF lt 1 25 Mbytes Program Flash 3 CC 0000 CC FFFF 64 Kbytes Program Flash 2 C8 0000 CB FFFF 256 Kbytes
66. corresponding port pin CAPIN timer T5 may optionally be cleared after the capture procedure This allows the XC2765X to measure absolute time differences or to perform pulse multiplication without software overhead The capture trigger timer T5 to CAPREL can also be generated upon transitions of GPT1 timer T3 inputs T3IN and or T3EUD This is especially advantageous when T3 operates in Incremental Interface Mode 1 Exception T5EUD is not connected to a pin Data Sheet 57 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description r T6CON BPS2 Sept 2 4 Basic Clock Interrupt GPT2 Timer T5 Request T5IRQ T5IN T5 Mode TSE OR Control Capture v CAPIN 1 7 CAPREL GPT2 CAPREL Interrupt Mode Request T3IN Control Reload v CRIRQ T3EUD Clear Interrupt Request T6IRQ Toggle FF GPT2 Timer T6 T6OTL TeOUT Mode T6IN Control TOSUE TeEUD MC GPT BLOCK2 Figure 9 Block Diagram of GPT2 Data Sheet 58 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 11 Real Time Clock The Real Time Clock RTC module of the XC2765X can be clocked with a clock signal selected from internal sources or external sources pins The RTC basically consists of a chain of divider blocks Selectable 32 1 and 8 1 dividers on off Thereloadable 16 b
67. cycles Drain disturb limit Npp SR 32 cycle S Data Sheet 93 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Table 23 Flash Parameters cont d Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Number of erase cycles Ng SR 15 000 cycle tper 2 5 years S Valid for up to 64 user selected sectors data storage 1000 cycle tae 2 20 years S All Flash module s can be erased programmed while code is executed and or data is read from only one Flash module or from PSRAM The Flash module that delivers code data can of course not be erased programmed 9 module DL Value of IMB_IMBCTRL WSFLASH Programming and erase times depend on the internal Flash clock source The control state machine needs a Flash module 3 can be erased programmed while code is executed and or data is read from any other Flash few system clock cycles This increases the stated durations noticably only at extremely low system clock frequencies Access to the XC2765X Flash modules is controlled by the IMB Built in prefetch mechanisms optimize the performance for sequential access Flash access waitstates only affect non sequential access Due to prefetch mechanisms the performance for sequential access depending on the software structure is only partially influenced by waitstates Data Sheet
68. d pad Sp Special pad e g XTALx DP Double pad can be used as standard or high speed pad In Input only pad PS Power supply pad Table 6 Pin Definitions and Functions Pin Symbol Ctrl Type Function 3 TESTM l In B Testmode Enable Enables factory test modes must be held HIGH for normal operation connect to Vpppg An internal pull up device will hold this pin high when nothing is driving it 4 P7 2 00 1 St B Bit 2 of Port 7 General Purpose Input Output EMUXO O1 SUB External Analog MUX Control Output 0 ADC1 CCU62 CCP I SUB CCU62 Position Input 0 OS0A TDI C IH SUB JTAG Test Data Input If JTAG pos C is selected during start up an internal pull up device will hold this pin high when nothing is driving it 5 TRST In B Test System Reset Input For normal system operation pin TRST should be held low A high level at this pin at the rising edge of PORST activates the XC2765X s debug system In this case pin TRST must be driven low once to reset the debug system An internal pull down device will hold this pin low when nothing is driving it Data Sheet 15 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 6 P7 0 00 1 St B Bit O of Port 7 General Purpose Input Output T3OUT O1 SUB GPT
69. directly connected to the incremental position sensor signals A and B through their respective inputs TxIN and TxEUD Direction and counting signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position The third position sensor signal TOPO can be connected to an interrupt input Timer T3 has an output toggle latch T3OTL which changes its state on each timer overflow underflow The state of this latch may be output on pin T3OUT e g for time out monitoring of external hardware components It may also be used internally to clock timers T2 and T4 for measuring long time periods with high resolution In addition to the basic operating modes T2 and T4 may be configured as reload or capture register for timer T3 A timer used as capture or reload register is stopped The contents of timer T3 is captured into T2 or T4 in response to a signal at the associated input pin TxIN Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or a selectable state transition of its toggle latch T3OTL When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal this signal can be continuously generated without software intervention Data Sheet 55 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description r T3CON BPS1
70. e and Reliability 5 Package and Reliability The XC2000 Family devices use the package type PG LQFP Plastic Green Low Profile Quad Flat Package The following specifications must be regarded to ensure proper integration of the XC2765X in its target environment 5 1 Packaging These parameters specify the packaging rather than the silicon Table 40 Package Parameters PG LQFP 100 8 Parameter Symbol Limit Values Unit Notes Min Max Exposed Pad Dimension Ex x Ey 6 2x6 2 mm Power Dissipation Poiss 1 0 W Thermal resistance Roja 47 K W No thermal via Junction Ambient 29 K W 4 layer no pad 23 K W 4 layer pad 1 Device mounted on a 2 layer JEDEC board according to JESD 51 3 or a 4 layer board without thermal vias exposed pad not soldered 2 Device mounted on a 4 layer JEDEC board according to JESD 51 7 with thermal vias exposed pad not soldered 3 Device mounted on a 4 layer JEDEC board according to JESD 51 7 with thermal vias exposed pad soldered to the board Note To improve the EMC behavior it is recommended to connect the exposed pad to the board ground independent of the thermal requirements Board layout examples are given in an application note Package Compatibility Considerations The XC2765X is a member of the XC2000 Family of microcontrollers It is also compatible to a certain extent with members of similar families or subfamilies Each
71. eas marked with lt are slightly smaller than indicated See column Notes The uppermost 4 Kbyte sector of the first Flash segment is reserved for internal use CO F000 to CO FFFF Several pipeline optimizations are not active within the external IO area This is necessary to control external peripherals properly 2 3 4 This common memory space consists of 16 Mbytes organized as 256 segments of 64 Kbytes each segment contains four data pages of 16 Kbytes The entire memory space can be accessed bytewise or wordwise Portions of the on chip DPRAM and the register spaces ESFR SFR additionally are directly bit addressable The internal data memory areas and the Special Function Register areas SFR and ESFR are mapped into segment 0 the system segment The Program Management Unit PMU handles all code fetches and therefore controls access to the program memories such as Flash memory and PSRAM The Data Management Unit DMU handles all data transfers and therefore controls access to the DSRAM and the on chip peripherals Both units PMU and DMU are connected to the high speed system bus so that they can exchange data This is required if operands are read from program memory code or data is written to the PSRAM code is fetched from external memory or data is read from or written to external resources These include peripherals on the LXBus such as USIC or MultiCAN The system bus allows concurrent two way communica
72. edicated node A particular subset of interrupt sources shares a set of nodes The source selection can be programmed using the interrupt source selection ISSR registers External Request Unit ERU A dedicated External Request Unit ERU is provided to route and preprocess selected on chip peripheral and external interrupt requests The ERU features 4 programmable input channels with event trigger logic ETL a routing matrix and 4 output gating units OGU The ETL features rising edge falling edge or both edges event detection The OGU combines the detected interrupt events and provides filtering capabilities depending on a programmable pattern match or miss Trap Processing The XC2765X provides efficient mechanisms to identify and process exceptions or error conditions that arise during run time the so called Hardware Traps A hardware trap causes an immediate system reaction similar to a standard interrupt service branching 1 Depending if the jump cache is used or not Data Sheet 48 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description to a dedicated vector table location The occurrence of a hardware trap is also indicated by a single bit in the trap flag register TFR Unless another higher priority trap service is in progress a hardware trap will interrupt any ongoing program execution In turn hardware trap services can normally not be interrupted by standard or PEC interrupts
73. erature C Joz 0 05 x e 15 0 028 x 2 uA For example at a temperature of 95 C the resulting leakage current is 3 2 pA Leakage derating depending on voltage level DV Vppp Vein V Joz loziempmax 1 6 x DV pA This voltage derating formula is an approximation which applies for maximum temperature Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device Vpin S Vitmax for a pullup Vei 2 Viii for a pulldown These values apply to the fixed pull devices in dedicated pins and to the user selectable pull devices in general purpose IO pins Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level Vpn 2 Vig for a pullup Vpn S Vi sa for a pulldown The maximum deliverable output current of a port driver depends on the selected output driver mode This specification is not valid for outputs which are switched to open drain mode In this case the respective output will float and the voltage is determined by the external circuit As a rule with decreasing output current the output levels approach the respective supply level Vo Vas Vou Vppp However only the levels for nominal output currents are verified Data Sheet 78 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 2 2 DC Parameters for Lower Voltage Area Keeping signal levels within the limit
74. eristics for Lower Voltage Range cont d Parameter Symbol Values Unit Note Min Typ Max Test Condition Output Low Voltage Vg CC 1 0 M UE dass 0 4 V Io donas 1 2 2 A 2 Because each double bond pin is connected to two pads standard pad and high speed pad it has twice the normal value For a list of affected pins refer to the pin definitions table in chapter 2 Not subject to production test verified by design characterization Hysteresis is implemented to avoid metastable states and switching due to internal ground bounce It cannot suppress switching due to external system noise under all conditions If the input voltage exceeds the respective supply voltage due to ground bouncing Vin lt Vss or supply ripple Vin gt Vppp a certain amount of current may flow through the protection diodes This current adds to the leakage current An additional error current j will flow if an overload current flows through an adjacent pin Please refer to the definition of the overload coupling factor Koy The given values are worst case values In production test this leakage current is only tested at 125 C other values are ensured by correlation For derating please refer to the following descriptions Leakage derating depending on temperature T junction temperature C Joz 0 05 x e 15 0 028 x 72 uA For example at a temperature of 95 C the resulting lea
75. evice Information The pins of the XC2765X are described in detail in Table 6 which includes all alternate functions For further explanations please refer to the footnotes at the end of the table The following figure summarizes all pins showing their locations on the four sides of the package go Do y T p ES ET oo g dope ccc occ ee ee Sg ulum aonnonnao nnunauanadnnunucnnasr Vss L 1 Vopps Voos 2 P0 7 TESTM 3 P10 7 P72 4 P10 6 TRST 15 P0 6 P7 00 6 P10 5 P73 7 P10 4 P7118 68 _ P0 5 P74 9 67 1 P10 3 Voom 66 P2 10 P6 0 65 L3 P2 13 P6 1 64 Vopn P6 2 LQFP 100 63 P0 4 VopPA 62 P10 2 P15 0 61 O P0 3 P15 2 60 P10 1 P15 4 59 7 P10 0 P15 5 58 P0 2 P15 6 57 P2 9 VaREF 56 P2 8 Vienn 55 Po 1 P5 0 54 P2 7 P5 2 58 7 P0 0 P5 3 52 Vopra Vopres 51 Vss BRETMDMOMM DAT z O NOOr xYI0NOO p gt BEPPEEGGO Gan ChAT 0 Gd aa 8 ooo gno MC XY PIN100 Figure 3 XC2765X Pin Configuration top view Data Sheet 14 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Key to Pin Definitions General Device Information Ctrl The output signal for a port pin is selected by bit field PC in the associated register Px IOCRy Output OO is selected by setting the respective bit field PC to 1x00g output O1 is selected by 1x015 etc Output signal OH is controlled by hardware Type Indicates the pad type and its power supply domain A B M 1 St Standar
76. evice will hold this pin high when nothing is driving it 83 P10 11 O0O I SUB Bit 11 of Port 10 General Purpose Input Output U1CO SCLK O1 SUB USIC1 Channel 0 Shift Clock Output OUT BRKOUT O2 SUB OCDS Break Signal Output AD11 OH SU B External Bus Interface Address Data Line 11 IH U1CO DX1D SUB USIC1 Channel 0 Shift Clock Input TMS B IH SUB JTAG Test Mode Selection Input If JTAG pos B is selected during start up an internal pull up device will hold this pin high when nothing is driving it Data Sheet 32 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 84 P1 2 O0O I SUB Bit 2 of Port 1 General Purpose Input Output CCU62 CC6 O1 SUB CCU62 Channel 2 Output 2 U1CO SELO C2 SUB USIC1 Channel 0 Select Control 6 Output 6 U2C1 SCLK O3 SUB USIC2 Channel 1 Shift Clock Output OUT A10 OH ISB External Bus Interface Address Line 10 ESR1 4 SUB ESR1 Trigger Input 4 CCU61_T12 SUB External Run Control Input for T12 of CCU61 HRB CCU62 CC6 St B CCU62 Channel 2 Input 2INA U2C1 DXOD I SUB USIC2 Channel 1 Shift Data Input U2C1 DX1C St B USIC2 Channel 1 Shift Clock Input 85 P10 12 O0 I StB Bit 12 of Port 10 General Purpose Input Output U1CO DOUT O1 SUB USIC1 Channel 0 Shift Dat
77. fer to Section 5 2 Thermal Considerations Note Operating Conditions apply Table 16 Switching Power Consumption Parameter Symbol Values Unit Note Min Typ Max Test Condition Power supply current Isact 10 10 mA active with all peripherals CC 0 6x 1 0x active and EVVRs on favs favs Power supply currentin Iggq CC 0 7 2 0 mA stopover mode EVVRs on 1 feys in MHz Data Sheet 81 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 2 The pad supply voltage pins Vpppg provide the input current for the on chip EVVRs and the current consumed by the pin output drivers A small current is consumed because the drivers input stages are switched In Fast Startup Mode with the Flash modules deactivated the typical current is reduced to 3 0 6 x fsys 3 Please consider the additional conditions described in section Active Mode Power Supply Current Active Mode Power Supply Current The actual power supply current in active mode not only depends on the system frequency but also on the configuration of the XC2765X s subsystem Besides the power consumed by the device logic the power supply pins also provide the current that flows through the pin output drivers A small current is consumed because the drivers input stages are switched The IO power domains can be supplied separately Power domain A Vpppa supplies the A D converters
78. g conditions unless otherwise noticed Note Typical parameter values refer to room temperature and nominal supply voltage minimum maximum parameter values also include conditions of minimum maximum temperature and minimum maximum supply voltage Additional details are described where applicable Table 13 Operating Conditions Parameter Symbol Values Unit Note Min Typ Max Test Condition Voltage Regulator Buffer Cgyay 1 0 4 7 uF Capacitance for DMP M SR Voltage Regulator Buffer Ceya 0 47 l 2 2 uF 02 Capacitance for DMP 1 SR External Load CSR l 209 pF pin out Capacitance driver default 4 System frequency fes SR 100 MHz 9 Overload current for Tova SR 2 5 mA not subject to analog inputs production test Overload current for digital Joyp SR 5 5 mA not subject to inputs production test Overload current coupling Kova 25x 15x Toy lt 0 mA factor for analog inputs CC 10 10 not subject to production test 1 0 x 1 0x Toy gt 0 mA 106 10 not subject to production test Overload current coupling Kovp 10x 3 0x Toy lt 0 mA factor for digital I O pins CC 10 10 not subject to production test 1 0x 50x Toy gt 0 mA 10 10 not subject to production test Data Sheet 72 V2 1 2011 07 infir XC2765X nrineon XC2000 Family Base Line Electrical Parameters Table 13 Oper
79. ged in certain steps This prevents overshoots and undershoots of the supply voltage To avoid the indicated problems recommended sequences are provided which ensure the intended operation of the clock system interacting with the power system Please refer to the Programmer s Guide Data Sheet 100 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 3 External Clock Input Parameters These parameters specify the external clock generation for the XC2765X The clock can be generated in two ways Byconnecting a crystal or ceramic resonator to pins XTAL1 XTAL2 Bysupplying an external clock signal This clock signal can be supplied either to pin XTAL1 core voltage domain or to pin CLKIN1 IO voltage domain If connected to CLKIN1 the input signal must reach the defined input levels Vi and Vi If connected to XTAL1 a minimum amplitude Vay peak to peak voltage is sufficient for the operation of the on chip oscillator Note The given clock timing parameters t t4 are only valid for an external clock input signal Note Operating Conditions apply Table 25 External Clock Input Characteristics Parameter Symbol Values Unit Note Min Typ Max Test Condition Oscillator frequency fosc SR 4 40 MHz Input clock signal 4 16 MHz Input crystal or ceramic resonator XTAL1 input current Z CC 20 uA absolute value Input clock hig
80. h time t SR 6 ns Input clock low time t SR 6 ns Input clock rise time tz SR 8 ns Input clock fall time t SR 8 ns Input voltage amplitude on Vay SR O 3x V 4to 16 MHz XTAL1 Voom 04x V 16 to 25 MHz Voom 0 5x V 25 to 40 MHz Voom Input voltage range limits Vy SR 1 7 1 7 V 2 for signal on XTAL1 Vopim Data Sheet 101 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 1 The amplitude voltage Vay refers to the offset voltage Vorr This offset voltage must be stable during the operation and the resulting voltage peaks must remain within the limits defined by Vix 2 Overload conditions must not occur on pin XTAL1 Note For crystal or ceramic resonator operation it is strongly recommended to measure the oscillation allowance negative resistance in the final target system layout to determine the optimum parameters for oscillator operation The manufacturers of crystals and ceramic resonators offer an oscillator evaluation service This evaluation checks the crystal resonator specification limits to ensure a reliable oscillator operation Vorr tosc l fosc MC_EXTCLOCK Figure 21 External Clock Drive XTAL1 Data Sheet 102 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 4 Pad Properties The output pad drivers of the XC2765X can operate in several user se
81. he external circuit using the READY input signal The polarity of this input signal can be selected Synchronous READY permits the shortest possible bus cycle but requires the input signal to be synchronous to the reference signal CLKOUT An asynchronous READY signal puts no timing constraints on the input signal but incurs a minimum of one waitstate due to the additional synchronization stage The minimum duration of an asynchronous READY signal for safe synchronization is one CLKOUT period plus the input setup time An active READY signal can be deactivated in response to the trailing rising edge of the corresponding command RD or WR If the next bus cycle is controlled by READY an active READY signal must be disabled before the first valid sample point in the next bus cycle This sample point depends on the programmed phases of the next cycle Data Sheet 112 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters RD WR D15 DO read Asynchron tpo tpe tproY tpr j tio l CLKOUT t20 l I tos MC X EBCREADY Figure 25 READY Timing Note If the READY input is sampled inactive at the indicated sampling point Not Rdy a READY controlled waitstate is inserted toRDY sampling the READY input active at the indicated sampling point Ready terminates the currently running bus cycle Note the different samp
82. ings are used Data Sheet 44 V2 1 2011 07 infir XC2765X nrineon XC2000 Family Base Line Functional Description 3 3 Central Processing Unit CPU The core of the CPU consists of a 5 stage execution pipeline with a 2 stage instruction fetch pipeline a 16 bit arithmetic and logic unit ALU a 32 bit 40 bit multiply and accumulate unit MAC a register file providing three register banks and dedicated SFRs The ALU features a multiply and divide unit a bit mask generator and a barrel shifter PSRAM Flash ROM Prefetch TFR Pipeline PUCON1 Branch CPUCON2 Unit Injection Exception Handler Multiply Unit MDC BE ALU Peripherals PE eee A mca04917_x vsd Figure 5 CPU Block Diagram Data Sheet 45 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description With this hardware most XC2765X instructions are executed in a single machine cycle of 12 5 ns with an 80 MHz CPU clock For example shift and rotate instructions are always processed during one machine cycle no matter how many bits are shifted Also multiplication and most MAC instructions execute in one cycle All multiple cycle instructions have been optimized so that they can be executed very fast for example a 32 16 bit division is started within 4 cycles while the remaining cycles are executed in the background Another pipeline optimization the branch target prediction eliminates the executio
83. ister specific actions will be taken based on the selected compare mode Table 9 Compare Modes Compare Modes Function Mode 0 Interrupt only compare mode Several compare interrupts per timer period are possible Mode 1 Pin toggles on each compare match Several compare events per timer period are possible Data Sheet 50 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Functional Description Table 9 Compare Modes cont d Compare Modes Function Mode 2 Interrupt only compare mode Only one compare interrupt per timer period is generated Mode 3 Pin set 1 on match pin reset 0 on compare timer overflow Only one compare event per timer period is generated Double Register Mode Two registers operate on one pin Pin toggles on each compare match Several compare events per timer period are possible Single Event Mode Generates single edges or pulses Can be used with any compare mode Data Sheet 51 V2 1 2011 07 Infineon uU XC2765X XC2000 Family Base Line Functional Description fcc T7IN T6OUF CC16lO CC171O CC31IO fcc TeOUF T7 Input Control Mode Control Capture or Compare T8 Input Control Reload Reg T7REL T7IRQ gt CC16IRQ CC17IRQ Sixteen 16 bit Capture Compare Registers CC31IRQ gt TSIRQ Reload Reg T8REL MC_CAPCOM2_BLOCKDIAG Figure 6 Data
84. it timer T14 The 32 bit RTC timer block accessible via registers RTCH and RTCL consisting of areloadable 10 bit timer areloadable 6 bit timer areloadable 6 bit timer areloadable 10 bit timer All timers count up Each timer can generate an interrupt request All requests are combined to a common node request er MUX RUN RTCINT Interrupt Sub Node CNT INT1 CNT INT2 CNT CNT INTO REL Register 10 Bits 10 10 Bits arx ES pappas ha T14 Register MCB05568B Figure 10 RTC Block Diagram Note The registers associated with the RTC are only affected by a power reset Data Sheet 59 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description The RTC module can be used for different purposes System clock to determine the current time and date Cyclic time based interrupt to provide a system time tick independent of CPU frequency and other resources 48 bit timer for long term measurements Alarm interrupt at a defined time Data Sheet 60 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 12 A D Converters For analog signal measurement up to two 10 bit A D converters ADCO ADC1 with 11 5 multiplexed input channels and a sample and hold circuit have been integrated on chip 4 inputs can be converted by both A D converters Conversio
85. kage current is 3 2 pA Leakage derating depending on voltage level DV Vopp Vein V oz loziempmax 1 6 x DV pA This voltage derating formula is an approximation which applies for maximum temperature Drive the indicated minimum current through this pin to change the default pin level driven by the enabled pull device Vpiy lt Vi for a pullup Vpn gt Vip for a pulldown These values apply to the fixed pull devices in dedicated pins and to the user selectable pull devices in general purpose IO pins Limit the current through this pin to the indicated value so that the enabled pull device can keep the default pin level Vey gt Vi for a pullup Vpn lt Vi for a pulldown The maximum deliverable output current of a port driver depends on the selected output driver mode This specification is not valid for outputs which are switched to open drain mode In this case the respective output will float and the voltage is determined by the external circuit As a rule with decreasing output current the output levels approach the respective supply level VOL gt VSS VOH gt VDDP However only the levels for nominal output currents are verified 10 As a rule with decreasing output current the output levels approach the respective supply level Vo Vas Vou Vppp However only the levels for nominal output currents are verified Data Sheet 80 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Par
86. l for maximum system performance from standard crystals a clock input signal or from the on chip clock source See also Section 4 6 2 The Oscillator Watchdog OWD generates an interrupt if the crystal oscillator frequency falls below a certain limit or stops completely In this case the system can be supplied with an emergency clock to enable operation even after an external clock failure All available clock signals can be output on one of two selectable pins Data Sheet 66 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 18 Parallel Ports The XC2765X provides up to 76 I O lines which are organized into 7 input output ports and 2 input ports All port lines are bit addressable and all input output lines can be individually bit wise configured via port control registers This configuration selects the direction input output push pull or open drain operation activation of pull devices and edge characteristics shape and driver characteristics output current of the port drivers The I O ports are true bidirectional ports which are switched to high impedance state when configured as inputs During the internal reset all port pins are configured as inputs without pull devices active All port lines have alternate input or output functions associated with them These alternate functions can be programmed to be assigned to various port pins to support the best utilization for a given a
87. lectable restricting the external address space to 8 Mbytes 64 Kbytes This is required when interface lines shall be assigned to Port 2 External CS signals address windows plus default can be generated and output on Port 4 in order to save external glue logic External modules can be directly connected to the common address data bus and their individual select lines Important timing characteristics of the external bus interface are programmable with registers TCONCSxX FCONCSY to allow the user to adapt it to a wide range of different types of memories and external peripherals Access to very slow memories or modules with varying access times is supported by a special Ready function The active level of the control input signal is selectable In addition up to four independent address windows may be defined using registers ADDRSELx to control access to resources with different bus characteristics These address windows are arranged hierarchically where window 4 overrides window 3 and window 2 overrides window 1 All accesses to locations not covered by these four address windows are controlled by TCONCSO FCONCSO The currently active window can generate a chip select signal The external bus timing is based on the rising edge of the reference clock output CLKOUT The external bus protocol is compatible with that of the standard C166 Family 1 Bus modes are switched dynamically if several address windows with different mode sett
88. lectable modes Strong driver mode allows controlling external components requiring higher currents such as power bridges or LEDs Reducing the driving power of an output pad reduces electromagnetic emissions EME In strong driver mode selecting a slower edge reduces EME The dynamic behavior i e the rise time and fall time depends on the applied external capacitance that must be charged and discharged Timing values are given for a capacitance of 20 pF unless otherwise noted In general the performance of a pad driver depends on the available supply voltage Vppe The following table lists the pad parameters Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply Data Sheet 103 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Table 26 is valid under the following conditions Vopr 2 4 5 V Vopptyp 5 V Vppp 5 5 V C 2 20 pF C lt 100 pF Table 26 Standard Pad Parameters for Upper Voltage Range Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Maximum output driver lomax 10 mA Strong driver current absolute value CC s 4 0 mA Medium driver 0 5 mA Weak driver Nominal output driver Tonom 2 5 mA Strong driver current absolute value CC H Hu 1 0 mA Medium driver 0 1 mA Weak driver Rise and Fall times 10 tgp CC
89. ling points for synchronous and asynchronous READY This example uses one mandatory waitstate see tpE before the READY input value is Data Sheet used 113 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 6 Synchronous Serial Interface Timing The following parameters are applicable for a USIC channel operated in SSC mode Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply C 20 pF Table 32 USIC SSC Master Mode Timing for Upper Voltage Range Parameter Symbol Values Unit Note Min Typ Max Test Condition Slave select output SELO t CC tsys ns active to first SCLKOUT 8 transmit edge Slave select output SELO t CC tsys ns inactive after last 61 SCLKOUT receive edge Data output DOUT valid t CC 6 9 ns time Receive data input setup t SR 31 ns time to SCLKOUT receive edge Data input DXO hold time t SR 4 ns from SCLKOUT receive edge 1 tsys 1 favs Table 33 USIC SSC Master Mode Timing for Lower Voltage Range Parameter Symbol Values Unit Note Test Condition Min Typ Max Slave select output SELO t CC toys ns active to first SCLKOUT 10 transmit edge Slave select output SELO t CC toys ns inactive after last 9 SCLKOUT receive edge Data output DOU
90. lock Can be synchronized to T12 Interrupt generation at period match and compare match Single shot mode supported Automatic start on a HW event T13HR for synchronization purposes Additional Features Block commutation for brushless DC drives implemented Position detection via Hall sensor pattern Automatic rotational speed measurement for block commutation Integrated error handling Fastemergency stop without CPU load via external signal CTRAP Control modes for multi channel AC drives Output levels can be selected and adapted to the power stage Data Sheet 53 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description CCU6 Module Kernel fey compare ET Dead Multi T TxHR T12 Channeli 1 7 time channel rap Control Control control Channel 2 4 1 output select Hal li nput output select Input Output Control COUT63 mc ccu6 blockdiagram vsd Figure 7 CCU6 Block Diagram Timer T12 can work in capture and or compare mode for its three channels The modes can also be combined Timer T13 can work in compare mode only The multi channel control unit generates output patterns that can be modulated by timer T12 and or timer T13 The modulation sources can be selected and combined for signal modulation Data Sheet 54 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 10 General P
91. ls 10 bit resolution conversion time below 1 us optional data preprocessing data reduction range check broken wire detection Up to 6 serial interface channels to be used as UART LIN high speed synchronous channel SPI IIC bus interface 10 bit addressing 400 kbit s IIS interface On chip MultiCAN interface Rev 2 0B active with up to 128 message objects Full CAN Basic CAN on up to 2 CAN nodes and gateway functionality On chip system timer and on chip real time clock Upto 12 Mbytes external address space for code and data Programmable external bus characteristics for different address ranges Multiplexed or demultiplexed external address data buses Selectable address bus width 16 bit or 8 bit data bus width Four programmable chip select signals Single power supply from 3 0 V to 5 5 V Programmable watchdog timer and oscillator watchdog Up to 76 general purpose I O lines On chip bootstrap loaders Supported by a full range of development tools including C compilers macro assembler packages emulators evaluation boards HLL debuggers simulators logic analyzer disassemblers programming boards On chip debug support via Device Access Port DAP or JTAG interface 100 pin Green LQFP package 0 5 mm 19 7 mil pitch Data Sheet 8 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Summary of Features Ordering Information The ordering code for an Infineo
92. ltage 0 15 0 15 range 1 The short term frequency deviation refers to a timeframe of a few hours and is measured relative to the current frequency at the beginning of the respective timeframe This parameter is useful to determine a time span for re triggering a LIN synchronization 2 This parameter is tested for the fastest and the slowest selection The medium selections are not subject to production test verified by design characterization Data Sheet 90 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 3 fwyin MHz 4 This value includes a hysteresis of approximately 50 mV for rising voltage 5 Vy selected SWD voltage level 6 The limit V 0 10 V is valid for the OK1 level The limit for the OK2 level is V 0 15 V Conditions for tsp Timing Measurement The time required for the transition from Power On to Base mode is called fgpo It is measured under the following conditions Precondition The pad supply is valid i e Vpppg is above 3 0 V and remains above 3 0 V even though the XC2765X is starting up No debugger is attached Start condition Power on reset is removed PORST 1 End condition External pin toggle caused by first user instruction executed from FLASH after startup Conditions for tss Timing Measurement The time required for the transition from Stopover to Stopover Waked Up mode is called tasso It is measured under the following
93. ly Base Line Functional Description Table 11 Instruction Set Summary cont d Mnemonic Description Bytes NOP Null operation 2 CoMUL CoMAC Multiply and accumulate 4 CoADD CoSUB Add Subtract 4 Co A SHR Arithmetic Shift right 4 CoSHL Shift left 4 CoLOAD STORE Load accumulator Store MAC register 4 CoCMP Compare 4 CoMAX MIN Maximum Minimum 4 CoABS CoRND Absolute value Round accumulator 4 CoMOV Data move 4 CoNEG NOP Negate accumulator Null operation 4 1 The Enter Power Down Mode instruction is not used in the XC2765X due to the enhanced power control scheme PWRDN will be correctly decoded but will trigger no action Data Sheet 70 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 Electrical Parameters The operating range for the XC2765X is defined by its electrical parameters For proper operation the specified limits must be respected when integrating the device in its target environment 4 1 General Parameters These parameters are valid for all subsequent descriptions unless otherwise noted 4 1 1 Absolut Maximum Rating Conditions Stresses above the values listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only Functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Ex
94. mily Base Line Electrical Parameters 4 2 1 DC Parameters Keeping signal levels within the limits specified in this table ensures operation without overload conditions For signal levels outside these specifications also refer to the specification of the overload current Joy Note Operating Conditions apply Table 14 is valid under the following conditions Vppe 2 4 5 V Vopptyp 5 V Vppp lt 5 5 V Table 14 DC Characteristics for Upper Voltage Range Parameter Symbol Values Unit Note Min Typ Max Test Condition Pin capacitance digital Co CC 10 pF not subject to inputs outputs To be production test doubled for double bond pins Input Hysteresis HYS CC 0 11 x V R 0 Ohm Vope Absolute input leakage Uozil i 10 200 nA Vy gt OV current on pins of analog CC Vin lt Vppp ports Absolute input leakage ozel 0 2 5 uA T lt 110 C current for all other pins CC Vin lt Vopr To be doubled for double Vin gt Vss ine 3 1 4 bond pins 02 5 pA 7 lt 150 C Vin lt Vopr Vn gt Vss Pull Level Force Current F SR 250 pA Pull Level Keep Current o 30 pA 9 SR Input high voltage VSR 07x Vope V all except XTAL1 Vppp 0 3 Input low voltage V SR 0 3 03x IV all except XTAL1 Vppp Output High voltage Vou CC Vppp V lu 2 lohmax 1 0 Vopp a V Tou 2 Iounom 0 4 Data Sheet 77 V2 1
95. mily Base Line Package and Reliability 5 3 Quality Declarations The operation lifetime of the XC2765X depends on the applied temperature profile in the application For a typical example please refer to Table 42 for other profiles please contact your Infineon counterpart to calculate the specific lifetime within your application Table 41 Quality Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Operation lifetime top CC 20 a See Table 42 and Table 43 ESD susceptibility Venu 2000 V EIA JESD22 according to Human Body SR A114 B Model HBM Moisture sensitivity level MSL CC 3 JEDEC J STD 020C Table 42 Typical Usage Temperature Profile Operating Time Sum 20 years Operating Temperat Notes 1200h T 150 C Normal operation 3 600 h T 125 C Normal operation 7 200 h T 2 110 C Normal operation 12000h T 100 C Normal operation 7 x 21 600h T 0 10 Power reduction 60 70 C Table 43 Long Time Storage Temperature Profile Operating Time Sum 20 years Operating Temperat Notes 2 000 h T 150 C Normal operation 16 000 h T 125 Normal operation 6 000 h T 110 C Normal operation 151 200 h T lt 150 C No operation Data Sheet 127 V2 1 2011 07
96. n microcontroller provides an exact reference to a specific product This ordering code identifies the function set of the corresponding product type the temperature range SAF 40 C to 85 C SAH 40 C to 110 C SAK 40 C to 125 C the package and the type of delivery For ordering codes for the XC2765X please contact your sales representative or local distributor This document describes several derivatives of the XC2765X group Basic Device Types are readily available and Special Device Types are only available on request As this document refers to all of these derivatives some descriptions may not apply to a specific product in particular to the special device types For simplicity the term XC2765X is used for all derivatives throughout this document 1 1 Basic Device Types Basic device types are available and can be ordered through Infineon s direct and or distribution channels Table 1 Synopsis of XC2765X Basic Device Types Derivative Flash PSRAM Capt Comp ADC Interfaces Memory DSRAM Modules Chan XC2765X 832 Kbytes 32 Kbytes CC2 11 5 2 CAN Nodes 104FxxL 16 Kbytes CCU60 1 2 38 6 Serial Chan xx is a placeholder for the available speed grade in MHz Specific information about the on chip Flash memory in Table 3 All derivatives additionally provide 8 Kbytes SBRAM and 2 Kbytes DPRAM Specific information about the available channels
97. n time of branch instructions if the prediction was correct The CPU has a register context consisting of up to three register banks with 16 word wide GPRs each at its disposal One of these register banks is physically allocated within the on chip DPRAM area A Context Pointer CP register determines the base address of the active register bank accessed by the CPU at any time The number of these register bank copies is only restricted by the available internal RAM space For easy parameter passing a register bank may overlap others A system stack of up to 32 Kwords is provided for storage of temporary data The system stack can be allocated to any location within the address space preferably in the on chip RAM area it is accessed by the CPU with the stack pointer SP register Two separate SFRs STKOV and STKUN are implicitly compared with the stack pointer value during each stack access to detect stack overflow or underflow The high performance of the CPU hardware implementation can be best utilized by the programmer with the highly efficient XC2765X instruction set This includes the following instruction classes Standard Arithmetic Instructions DSP Oriented Arithmetic Instructions Logical Instructions Boolean Bit Manipulation Instructions Compare and Loop Control Instructions Shift and Rotate Instructions Prioritize Instruction Data Movement Instructions System Stack Instructions Jump and Call Instructi
98. nd its demands on the system To aid in correctly interpreting the parameters when evaluating them for a design they are marked accordingly in the column Symbol CC Controller Characteristics The logic of the XC2765X provides signals with the specified characteristics SR System Requirement The external system must provide signals with the specified characteristics to the XC2765X Data Sheet 74 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 2 DC Parameters These parameters are static or average values that may be exceeded during switching transitions e g output current Leakage current is strongly dependent on the operating temperature and the voltage level at the respective pin The maximum values in the following tables apply under worst case conditions i e maximum temperature and an input level equal to the supply voltage The value for the leakage current in an application can be determined by using the respective leakage derating formula see tables with values from that application The pads of the XC2765X are designed to operate in various driver modes The DC parameter specifications refer to the pad current limits specified in Section 4 6 4 Supply Voltage Restrictions The XC2765X can operate within a wide supply voltage range from 3 0 V to 5 5 V However during operation this supply voltage must remain within 10 percent of the selected nominal supply voltage It
99. ns Sample time ts tapoi X 5 375 ns Conversion 10 bit fcio 16 x tanci 2 x fsyg 16 x 75 ns 2 x 25 ns 1 25 us Conversion 8 bit tog 14 x tanci 2 x tsys 14 x 75 ns 2 x 25 ns 1 10 us Data Sheet 89 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 4 System Parameters The following parameters specify several aspects which are important when integrating the XC2765X into an application system Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply Table 20 Various System Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Short term deviation of Afint CC 1 1 96 AT S 10 C internal clock source frequency Internal clock source fw CC 48 5 0 5 2 MHz frequency Wakeup clock source Fwy CC 400 700 kHz FREQSEL 00 frequency 210 390 kHz FREQSEL 01 140 260 kHz FREQSEL 10 110 200 kHz FREQSEL 11 Startup time from power tspo CC 1 8 2 2 2 7 ms fwy 500 kHz on with code execution from Flash Startup time from stopover tsso CC 11 12 us mode with code execution du du from PSRAM Core voltage PVC Vee CC Viy Viv Viv V 5 supervision level 0 03 0 07 4 Supply watchdog SWD Vawp Viv Viv Viv V Lower voltage supervision level CC 0 109 0 15 range Viv Viv Viv V Upper vo
100. ns use the successive approximation method The sample time to charge the capacitors and the conversion time are programmable so that they can be adjusted to the external circuit The A D converters can also operate in 8 bit conversion mode further reducing the conversion time Several independent conversion result registers selectable interrupt requests and highly flexible conversion sequences provide a high degree of programmability to meet the application requirements Both modules can be synchronized to allow parallel sampling of two input channels For applications that require more analog input channels external analog multiplexers can be controlled automatically For applications that require fewer analog input channels the remaining channel inputs can be used as digital input port pins The A D converters of the XC2765X support two types of request sources which can be triggered by several internal and external events Parallel requests are activated at the same time and then executed in a predefined sequence Queued requests are executed in a user defined sequence In addition the conversion of a specific channel can be inserted into a running sequence without disturbing that sequence All requests are arbitrated according to the priority level assigned to them Data reduction features reduce the number of required CPU access operations allowing the precise evaluation of analog inputs high conversion rate even at a low C
101. ntroller from malfunctioning for longer periods of time The Watchdog Timer is always enabled after an application reset of the chip It can be disabled and enabled at any time by executing the instructions DISWDT and ENWDT respectively The software has to service the Watchdog Timer before it overflows If this is not the case because of a hardware or software failure the Watchdog Timer overflows generating a prewarning interrupt and then a reset request The Watchdog Timer is a 16 bit timer clocked with the system clock divided by 16 384 or 256 The Watchdog Timer register is set to a prespecified reload value stored in WDTREL in order to allow further variation of the monitored time interval Each time it is serviced by the application software the Watchdog Timer is reloaded and the prescaler is cleared Time intervals between 3 2 us and 13 42 s can be monitored 80 MHz The default Watchdog Timer interval after power up is 6 5 ms 10 MHz 3 17 Clock Generation The Clock Generation Unit can generate the system clock signal fsys for the XC2765X from a number of external or internal clock sources External clock signals with pad voltage or core voltage levels External crystal or resonator using the on chip oscillator On chip clock source for operation without crystal resonator Wake up clock ultra low power to further reduce power consumption The programmable on chip PLL with multiple prescalers generates a clock signa
102. ods TCSs and their variation as well as the derived external timing depend on the mechanism used to generate fsys This must be considered when calculating the timing for the XC2765X Phase Locked Loop Operation 1 N TA fsvs Direct Clock Drive 1 1 fsvs Prescaler Operation N 1 Tac EST Sra e Ps ee qe gr fsvs TCS MC XC2X CLOCKGEN Figure 19 Generation Mechanisms for the System Clock Note The example of PLL operation shown in Figure 19 uses a PLL factor of 1 4 the example of prescaler operation uses a divider factor of 2 1 The specification of the external timing AC Characteristics depends on the period of the system clock TCS Data Sheet 96 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Electrical Parameters Direct Drive When direct drive operation is selected SYSCONO CLKSEL 11g the system clock is derived directly from the input clock signal CLKIN1 fsvs fin The frequency of fsys is the same as the frequency of fin In this case the high and low times of fsys are determined by the duty cycle of the input clock fiy Selecting Bypass Operation from the XTAL1 input and using a divider factor of 1 results in a similar configuration Prescaler Operation When prescaler operation is selected SYSCONO CLKSEL 105 PLLCONO VCOBY 1g the system clock is derived either from the crystal oscillator input clock signal XTAL1 or from the internal clock so
103. of the tolerance of both the Embedded Voltage Regulators EVR and the PVC levels this interrupt can be triggered inadvertently even though the core voltage is within the normal range It is therefore recommended not to use the this warning level Data Sheet 92 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 5 Flash Memory Parameters The XC2765X is delivered with all Flash sectors erased and with no protection installed The data retention time of the XC2765X s Flash memory i e the time after which stored data can still be retrieved depends on the number of times the Flash memory has been erased and programmed Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply Table 23 Flash Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Parallel Flash module Npp SR 49 Ng gp lt 1 program erase limit fsvs lt 80 MHz depending on Flash read 19 Ng gp 1 activity al Flash erase endurance for Ngec SR 10 cycle fgg 2 20 years security pages S Flash wait states Nweetas 1 fays 8 MHz HSR p 7 feys lt 13 MHz 3 fsys 17 MHz 4 Joys gt 17 MHz Erase time per tea CC l 79 8 0 ms sector page Programming time per tgp CC l 34 3 5 ms page Data retention time trer CC 20 year Ng x 1 000 S
104. ons Return Instructions System Control Instructions Miscellaneous Instructions The basic instruction length is either 2 or 4 bytes Possible operand types are bits bytes and words A variety of direct indirect or immediate addressing modes are provided to specify the required operands Data Sheet 46 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 4 Memory Protection Unit MPU The XC2765X s Memory Protection Unit MPU protects user specified memory areas from unauthorized read write or instruction fetch accesses The MPU can protect the whole address space including the peripheral area This completes establisched mechanisms such as the register security mechanism or stack overrun underrun detection Four Protection Levels support flexible system programming where operating system low level drivers and applications run on separate levels Each protection level permits different access restrictions for instructions and or data Every access is checked if the MPU is enabled and an access violating the permission rules will be marked as invalid and leads to a protection trap A set of protection registers for each protection level specifies the address ranges and the access permissions Applications requiring more than 4 protection levels can dynamically re program the protection registers 3 5 Memory Checker Module MCHK The XC2765X s Memory Checker Module calculates
105. p Max Unit Note Test Condition Select input DX2 setup to first clock input DX1 transmit edge tio SR ns Select input DX2 hold after last clock input DX1 receive edge t44 SR ns Receive data input setup time to shift clock receive edge ty SR ns Data input DXO hold time from clock input DX1 receive edge tyg SR ns Data output DOUT valid time t44 CC 41 ns 1 These input timings are valid for asynchronous input signal handling of slave select input shift clock input and receive data input bits DXnCR DSEN 0 Data Sheet 116 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters Master Mode Timing Active eee Output Inactive Clock Output First Transmit Receive SCLKOUT Edge Edge Data Output DOUT X Data Input DXO Slave Mode Timing Active Inactive Select Input DX2 Clock Input DX1 Data Input DXO Data Output DOUT Transmit Edge with this clock edge transmit data is shifted to transmit data output Receive Edge with this clock edge receive data at receive data input is latched Drawn for BRGH SCLKCFG 00g Also valid for for SCLKCFG 01g with inverted SCLKOUT signal USIC SSC TMGX VSD Figure 26 USIC SSC Master Slave Mode Timing Note This timing diagram shows a standard config
106. posure to absolute maximum rating conditions for an extended time may affect device reliability During absolute maximum rating overload conditions Vin gt Vpop or Vi lt Vss the voltage on Vppp pins with respect to ground Vas must not exceed the values defined by the absolute maximum ratings Table 12 Absolute Maximum Rating Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Output current on a pin Ig SR 30 mA when high value is driven Output current on a pin Io SR 30 mA when low value is driven Overload current Toy SR 10 10 mA Absolute sum of overload oy 100 mA currents SR Junction Temperature T SR 40 150 C Storage Temperature Ts SR 65 150 C Digital supply voltage for Vpppa 0 5 6 0 V IO pads and voltage Vopps regulators SR Voltage on any pin with Vin SR 0 5 Vppe V Vin Vopp max respect to ground Vss 0 5 1 Overload condition occurs if the input voltage Vi is out of the absolute maximum rating range In this case the current must be limited to the listed values by design measures Data Sheet 71 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line 4 1 2 Operating Conditions Electrical Parameters The following operating conditions must not be exceeded to ensure correct operation of the XC2765X All parameters specified in the following sections refer to these operatin
107. pplication For this reason certain functions appear several times in Table 10 All port lines that are not used for alternate functions may be used as general purpose I O lines Table 10 Summary of the XC2765X s Ports Port Width I O Connected Modules PO 8 VO EBC A7 A0 CCU6 USIC CAN P1 8 lO EBC A15 A8 CCU6 USIC P2 14 lO EBC READY BHE A23 A16 AD15 AD13 D15 D13 CAN CC2 GPT12E USIC DAP JTAG P4 4 VO EBC CS3 CS0 CC2 CAN GPT12E USIC P5 11 l Analog Inputs CCU6 DAP JTAG GPT12E CAN P6 3 O ADC CAN GPT12E P7 5 lO CAN GPT12E SCU DAP JTAG CCU6 ADC USIC P10 16 VO EBC ALE RD WR AD12 ADO D12 D0 CCU6 USIC DAP JTAG CAN P15 5 l Analog Inputs GPT12E Data Sheet 67 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description 3 19 Instruction Set Summary Table 11 lists the instructions of the XC2765X The addressing modes that can be used with a specific instruction the function of the instructions parameters for conditional execution of instructions and the opcodes for each instruction can be found in the Instruction Set Manual This document also provides a detailed description of each instruction Table 11 Instruction Set Summary Mnemonic Description Bytes ADD B Add word byte operands 2 4 ADDC B Add word byte oper
108. rature nominal supply voltage the typical values can be used for calculation This parameter includes the sample time also the additional sample time specified by STC the time to determine the digital result and the time to load the result register with the conversion result Values for the basic clock t4pc depend on programming The broken wire detection delay against V4cyp is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 500 us Result below 10 66 The broken wire detection delay against Varer is measured in numbers of consecutive precharge cycles at a conversion rate of not more than 10 us This function is influenced by leakage current in particular at high temperature Result above 80 3324 TUE is tested at Varer Vpppa 5 0 V Vaawp 0 V It is verified by design for all other voltages within the defined voltage range The specified TUE is valid only if the absolute sum of input overload currents on analog port pins see Joy specification does not exceed 10 mA and if Varer and Vagnp remain stable during the measurement time Vain may exceed Vagnp OF Varer up to the absolute maximum ratings However the conversion result in these cases will be X000 or X3FF respectively Data Sheet 87 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters A D Converter 1 Source AIN On Da iP Vas Cg ji C ar 7 Cains C
109. rface The JTAG module is fully compliant with IEEE1149 1 2000 Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply C 20 pF Table 38 JTAG Interface Timing for Upper Voltage Range Parameter Symbol Values Unit Note Min Typ Max Test Condition TCK clock period t4 SR J500 l ns 3 TCK high time t SR 16 ns TCK low time tz SR 16 ns TCK clock rise time t SR 8 ns TCK clock fall time t SR 8 ns TDI TMS setup to TCK tg SR 6 ns rising edge TDI TMS hold after TCK t SR 6 ns rising edge TDO valid from TCK falling t CC 25 29 ns edge propagation delay TDO high impedance to tg CC 25 29 ns valid output from TCK falling edge 9 TDO valid output to high t CC 25 29 ns impedance from TCK falling edge TDO hold after TCK falling ti CC 5 ns edge 1 The debug interface cannot operate faster than the overall system therefore t 2 tsys 2 Under typical conditions the interface can operate at transfer rates up to 20 MHz 3 The falling edge on TCK is used to generate the TDO timing 4 The setup time for TDO is given implicitly by the TCK cycle time Data Sheet 121 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Electrical Parameters Table 39 JTAG Interface Timing for Lower Voltage Range
110. rpose Input Output U1CO SELO 0O1 SUB USIC1 Channel 0 Select Control 1 Output 1 UOC1 DOUT O2 StB USICO Channel 1 Shift Data Output RD OH SUB External Bus Interface Read Strobe Output ESR2 2 SUB ESR2 Trigger Input 2 UOC1 DXOC I SUB USICO Channel 1 Shift Data Input 90 P1 4 00 1 St B Bit 4 of Port 1 General Purpose Input Output CCU62_COU 01 St B CCU62 Channel 1 Output T61 U1C1 SELO C2 SUB USIC1 Channel 1 Select Control 4 Output 4 U2CO SELO O3 St B USIC2 Channel 0 Select Control 5 Output 5 A12 OH SUB External Bus Interface Address Line 12 U2CO DX2B I SUB USIC2 Channel 0 Shift Control Input Data Sheet 34 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 91 P10 15 00 1 St B Bit 15 of Port 10 General Purpose Input Output U1CO SELO O1 SUB USIC1 Channel 0 Select Control 2 Output 2 UOC1 DOUT O2 StB USICO Channel 1 Shift Data Output U1CO DOUT OS StB USIC1 Channel 0 Shift Data Output ALE OH SUB External Bus Interf Addr Latch Enable Output UOC1 DX1C St B USICO Channel 1 Shift Clock Input 92 P1 5 O0 I SUB Bit 5 of Port 1 General Purpose Input Output CCU62 COU O1 SUB CCU62 Channel 0 Output T60 U1C1 SELO C2 SUB USIC1 Channel 1 Select Control 3 Output 3 BRKOUT OS StB OCDS Break Signal O
111. rs The timing in the AC Characteristics refers to TCSs Timing must be calculated using the minimum TCS possible under the given circumstances The actual minimum value for TCS depends on the jitter of the PLL Because the PLL is constantly adjusting its output frequency to correspond to the input frequency from crystal or oscillator the accumulated jitter is limited This means that the relative deviation for periods of more than one TCS is lower than for a single TCS see formulas and Figure 20 This is especially important for bus cycles using waitstates and for the operation of timers serial interfaces etc For all slower operations and longer periods e g pulse train generation or measurement lower baudrates etc the deviation caused by the PLL jitter is negligible The value of the accumulated PLL jitter depends on the number of consecutive VCO output cycles within the respective timeframe The VCO output clock is divided by the output prescaler K2 to generate the system clock signal fgys The number of VCO cycles is K2 x T where T is the number of consecutive fsys cycles TCS The maximum accumulated jitter long term jitter Dmax is defined by D max ns 220 K2 x foys 4 3 This maximum value is applicable if either the number of clock cycles T gt fgyg 1 2 or the prescaler value K2 gt 17 In all other cases for a timeframe of T x TCS the accumulated jitter D is determined by D ns D max x 1 0 0
112. rved for future members of the XC2000 Family In order to ensure upward compatibility they should either not be accessed or written with zeros The on chip Flash memory stores code constant data and control data The on chip Flash memory consists of 1 module of 64 Kbytes preferably for data storage and modules with a maximum capacity of 256 Kbytes each Each module is organized in sectors of 4 Kbytes The uppermost 4 Kbyte sector of segment O located in Flash module 0 is used internally to store operation control parameters and protection information Note The actual size of the Flash memory depends on the chosen device type Each sector can be separately write protected erased and programmed in blocks of 128 Bytes The complete Flash area can be read protected A user defined password sequence temporarily unlocks protected areas The Flash modules combine 128 bit read access with protected and efficient writing algorithms for programming and erasing Dynamic error correction provides extremely high read data security for all read access operations Access to different Flash modules can be executed in parallel For Flash parameters please see Section 4 5 Memory Content Protection The contents of on chip memories can be protected against soft errors induced e g by radiation by activating the parity mechanism or the Error Correction Code ECC The parity mechanism can detect a single bit error and prevent the software from using
113. s e CAN functionality conforming to CAN specification V2 0 B active for each CAN node compliant to ISO 11898 Independent CAN nodes Set of independent message objects shared by the CAN nodes Dedicated control registers for each CAN node Data transfer rate up to 1 Mbit s individually programmable for each node Flexible and powerful message transfer control and error handling capabilities Full CAN functionality for message objects Can be assigned to one of the CAN nodes Configurable as transmit or receive objects or as message buffer FIFO Handle 11 bit or 29 bit identifiers with programmable acceptance mask for filtering Remote Monitoring Mode and frame counter for monitoring Automatic Gateway Mode support 16 individually programmable interrupt nodes Analyzer mode for CAN bus monitoring 3 15 System Timer The System Timer consists of a programmable prescaler and two concatenated timers 10 bits and 6 bits Both timers can generate interrupt requests The clock source can be selected and the timers can also run during power reduction modes Therefore the System Timer enables the software to maintain the current time for scheduling functions or for the implementation of a clock Data Sheet 65 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 16 Watchdog Timer The Watchdog Timer is one of the fail safe mechanisms which have been implemented to prevent the co
114. s phase tpE 1 32 TCS Address Write Data hold phase tpF 0 3 TCS Note The bandwidth of a parameter from minimum to maximum value covers the whole operating range temperature voltage as well as process variations Within a given device however this bandwidth is smaller than the specified range This is also due to interdependencies between certain parameters Some of these interdependencies are described in additional notes see standard timing Note Operating Conditions apply C 20 pF Data Sheet 107 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line Table 30 EBC External Bus Timing for Upper Voltage Range Electrical Parameters Parameter Symbol Values Unit Note Min Typ Max Test Condition Output valid delay for RD j CC 7 13 ns WR L H Output valid delay for t4 CC 7 14 ns BHE ALE Address output valid delay t CC 8 14 ns for A23 A0 Address output valid delay 5 4 CC 8 15 ns for AD15 ADO MUX mode Output valid delay for CS 44CC 7 13 ns Data output valid delay for ti CC 8 15 ns AD15 ADO write data MUX mode Data output valid delay for ti CC 8 15 ns D15 DO write data DEMUX mode Output hold time for RD t CC 2 6 8 ns WR L H Output hold time for BHE t CC 2 6 10 ns ALE Address output hold time t 4 CC 3 6 8 ns for AD15 ADO Output hold time for CS t CC 3 6
115. s specified in this table ensures operation without overload conditions For signal levels outside these specifications also refer to the specification of the overload current Joy Note Operating Conditions apply Table 15 is valid under the following conditions Vppe 2 3 0 V Vpppy 3 3 V Vopp lt 4 5 V Table 15 DC Characteristics for Lower Voltage Range Parameter Symbol Values Unit Note Min Typ Max Test Condition Pin capacitance digital Co CC 10 pF not subject to inputs outputs To be production test doubled for double bond pins Input Hysteresis HYS CC 0 07 x V Rs 0 Ohm Vope Absolute input leakage Uozil 10 200 nA Vin gt Vss current on pins of analog CC Vin lt Vppp ports Absolute input leakage ozel 0 2 2 5 uA T 110 C current for all other pins CC Vin lt Vopr To be doubled for double Vin gt Vss bond pins 02 8 uA T 150 6 Vin lt Vopr Vin gt Vss Pull Level Force Current g F SR 150 8 Pull Level Keep Current Zp 10 pA 9 SR Input high voltage VSR 07x Vope V all except XTAL1 Vppp 0 3 Input low voltage V SR 0 3 03x IV all except XTAL1 Vppp Output High voltage Vou CC Vppp V lu 2 lohmax 1 0 Vopp a V Tou 2 Iounom 0 4 Data Sheet 79 V2 1 2011 07 XC2765X ec Infineon XC2000 Family Base Line Electrical Parameters Table 15 DC Charact
116. shift and data storage structure which is identical for all supported serial communication protocols Each channel supports complete full duplex operation with a basic data buffer structure one transmit buffer and two receive buffer stages In addition the data handling software can use FIFOs The protocol part generation of shift clock data control signals is independent of the general part and is handled by protocol specific preprocessors PPPs The USIC s input output lines are connected to pins by a pin routing unit The inputs and outputs of each USIC channel can be assigned to different interface pins providing great flexibility to the application software All assignments can be made during runtime Bus Buffer amp Shift Structure Protocol Preprocessors Pins Control 0 a DIM e PPP A U DSU PPP B ET ba o RJ x o n 2 e Baud rate Generators USIC_basic vsd Figure 11 General Structure of a USIC Module The regular structure of the USIC module brings the following advantages Higher flexibility through configuration with same look and feel for data management Reduced complexity for low level drivers serving different protocols Wide range of protocols with improved performances baud rate buffer handling Data Sheet 62 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description Target Protocols Each USIC channel can receive and transmit data frames
117. tion for maximum transfer performance Up to 32 Kbytes of on chip Program SRAM PSRAM are provided to store user code or data The PSRAM is accessed via the PMU and is optimized for code fetches A section of the PSRAM with programmable size can be write protected Up to 16 Kbytes of on chip Data SRAM DSRAM are used for storage of general user data The DSRAM is accessed via a separate interface and is optimized for data access 2 Kbytes of on chip Dual Port RAM DPRAM provide storage for user defined variables for the system stack and for general purpose register banks A register bank can consist of up to 16 word wide RO to R15 and or byte wide RLO RHO RL7 RH7 General Purpose Registers GPRs The upper 256 bytes of the DPRAM are directly bit addressable When used by a GPR any location in the DPRAM is bit addressable Data Sheet 42 V2 1 2011 07 m XC2765X Infineon XC2000 Family Base Line Functional Description 8 Kbytes of on chip Stand By SRAM SBRAM provide storage for system relevant user data that must be preserved while the major part of the device is powered down The SBRAM is accessed via a specific interface and is powered in domain M 1024 bytes 2 x 512 bytes of the address space are reserved for the Special Function Register areas SFR space and ESFR space SFRs are word wide registers which are used to control and monitor functions of the different on chip units Unused SFR addresses are rese
118. to as reference clock output signal CLKOUT Data Sheet 38 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information 2 2 Identification Registers The identification registers describe the current version of the XC2765X and of its modules Table 7 XC2765X Identification Registers Short Name Value Address SCU IDMANUF 1820 00 F07E SCU IDCHIP 38014 00 F07C SCU IDMEM 30D0 00 F07A SCU_IDPROG 1313 00 F078 JTAG_ID 0017 E083 marking EES AA ES AA or AA Data Sheet 39 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Functional Description 3 Functional Description The architecture of the XC2765X combines advantages of RISC CISC and DSP processors with an advanced peripheral subsystem in a well balanced design On chip memory blocks allow the design of compact systems on silicon with maximum performance suited for computing control and communication The on chip memory blocks program code memory and SRAM dual port RAM data SRAM and the generic peripherals are connected to the CPU by separate high speed buses Another bus the LXBus connects additional on chip resources and external resources see Figure 4 This bus structure enhances overall system performance by enabling the concurrent operation of several subsystems of the XC2765X The block diagram gives an overview of the on chip components and the advan
119. uration where the slave select signal is low active and the serial clock signal is not shifted and not inverted Data Sheet 117 V2 1 2011 07 e XC2765X Infineon XC2000 Family Base Line Electrical Parameters 4 6 7 Debug Interface Timing The debugger can communicate with the XC2765X either via the 2 pin DAP interface or via the standard JTAG interface Debug via DAP The following parameters are applicable for communication through the DAP debug interface Note These parameters are not subject to production test but verified by design and or characterization Note Operating Conditions apply C 20 pF Table 36 DAP Interface Timing for Upper Voltage Range Parameter Symbol Values Unit Note Min Typ Max Test Condition DAPO clock period tS SR 1250 l ns DAPO high time ty SR 8 ns DAPO low time ta SR 8 ns DAPO clock rise time H SR x 4 ns DAPO clock fall time tis SR 4 ns DAP1 setup to DAPO Hg SR J6 ns pad type stan rising edge dard DAP1 hold after DAPO t SRH J6 ns pad type stan rising edge dard DAP1 valid per DAPO fg CC 17 20 ns pad type stan clock period dard 1 The debug interface cannot operate faster than the overall system therefore t44 2 tsys 2 The Host has to find a suitable sampling point by analyzing the sync telegram response Data Sheet 118 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line
120. urce through the output prescaler K1 K1DIV 1 sys 7 fosc K1 If a divider factor of 1 is selected the frequency of fsys equals the frequency of fosc In this case the high and low times of fsys are determined by the duty cycle of the input clock fosc external or internal The lowest system clock frequency results from selecting the maximum value for the divider factor K1 fsys fosc 1024 4 6 2 1 Phase Locked Loop PLL When PLL operation is selected SYSCONO CLKSEL 103 PLLCONO VCOBY 0g the on chip phase locked loop is enabled and provides the system clock The PLL multiplies the input frequency by the factor F foys fn x F F is calculated from the input divider P PDIV 1 the multiplication factor N NDIV 1 and the output divider K2 K2DIV 1 F2 N P x K2 The input clock can be derived either from an external source at XTAL1 or from the on chip clock source The PLL circuit synchronizes the system clock to the input clock This synchronization is performed smoothly so that the system clock frequency does not change abruptly Adjustment to the input clock continuously changes the frequency of fsys so that it is locked to fin The slight variation causes a jitter of fsys which in turn affects the duration of individual TCSs 1 Voltages on XTAL1 must comply to the core supply voltage Vppi Data Sheet 97 V2 1 2011 07 ec XC2765X Infineon XC2000 Family Base Line Electrical Paramete
121. urpose Timer GPT12E Unit The GPT12E unit is a very flexible multifunctional timer counter structure which can be used for many different timing tasks such as event timing and counting pulse width and duty cycle measurements pulse generation or pulse multiplication The GPT12E unit incorporates five 16 bit timers organized in two separate modules GPT1 and GPT2 Each timer in each module may either operate independently in a number of different modes or be concatenated with another timer of the same module Each of the three timers T2 T3 T4 of module GPT1 can be configured individually for one of four basic modes of operation Timer Gated Timer Counter and Incremental Interface Mode In Timer Mode the input clock for a timer is derived from the system clock and divided by a programmable prescaler Counter Mode allows timer clocking in reference to external events Pulse width or duty cycle measurement is supported in Gated Timer Mode where the operation of a timer is controlled by the gate level on an external input pin For these purposes each timer has one associated port pin TxIN which serves as a gate or clock input The maximum resolution of the timers in module GPT1 is 4 system clock cycles The counting direction up down for each timer can be programmed by software or altered dynamically by an external signal on a port pin TxEUD e g to facilitate position tracking In Incremental Interface Mode the GPT1 timers can be
122. ut EMUX2 O1 DA A External Analog MUX Control Output 2 ADCO T6OUT 02 DA A GPT12E Timer T6 Toggle Latch Output U1C1 SCLK O3 DA A USIC1 Channel 1 Shift Clock Output OUT U1C1 DX1C I DA A USIC1 Channel 1 Shift Clock Input 15 P15 0 l In A Bit 0 of Port 15 General Purpose Input ADC1 CHO I In A Analog Input Channel 0 for ADC1 16 P15 2 l In A Bit 2 of Port 15 General Purpose Input ADC1 CH2 I In A Analog Input Channel 2 for ADC1 T5INA In A GPT12E Timer T5 Count Gate Input 17 P15 4 l In A Bit 4 of Port 15 General Purpose Input ADC1 CH4 I In A Analog Input Channel 4 for ADC1 T6INA In A GPT12E Timer T6 Count Gate Input 18 P15 5 l In A Bit 5 of Port 15 General Purpose Input ADC1 CH5 I In A Analog Input Channel 5 for ADC1 T6EUDA In A GPT12E Timer T6 External Up Down Control Input 19 P15 6 l In A Bit 6 of Port 15 General Purpose Input ADC1 CH6 I In A Analog Input Channel 6 for ADC1 20 Varer PS A Reference Voltage for A D Converters ADCO 1 21 VAGND PS A Reference Ground for A D Converters ADCO 1 22 P5 0 In A Bit 0 of Port 5 General Purpose Input ADCO CHO I In A Analog Input Channel 0 for ADCO 23 P5 2 In A Bit 2 of Port 5 General Purpose Input ADCO CH2 I In A Analog Input Channel 2 for ADCO TDI A In A JTAG Test Data Input Data Sheet 18 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information
123. utput A13 OH SUB External Bus Interface Address Line 13 U2CO DXOC I SUB USIC2 Channel 0 Shift Data Input 93 P1 6 O0 I SUB Bit 6 of Port 1 General Purpose Input Output CCU62 CC6 O1 l SUB CCU62 Channel 1 Output 1 U1C1 SELO C2 SUB USIC1 Channel 1 Select Control 2 Output 2 U2CO0 DOUT OS StB USIC2 Channel 0 Shift Data Output A14 OH SUB External Bus Interface Address Line 14 U2CO DXOD SUB USIC2 Channel 0 Shift Data Input CCU62 CC6 SUB CCU62 Channel 1 Input 1INA Data Sheet 35 V2 1 2011 07 Cinfineon XC2765X XC2000 Family Base Line General Device Information Table 6 Pin Definitions and Functions cont d Pin Symbol Ctrl Type Function 94 P1 7 00 1 St B Bit 7 of Port 1 General Purpose Input Output CCU62 CC6 O1 SUB CCU62 Channel 0 Output 0 U1C1 MCLK O2 St B USIC1 Channel 1 Master Clock Output OUT U2CO SCLK O3 StB USIC2 Channel 0 Shift Clock Output OUT A15 OH SUB External Bus Interface Address Line 15 U2CO DX1C I SUB USIC2 Channel 0 Shift Clock Input CCU62_CCE I SUB CCU62 Channel 0 Input OINA 95 XTAL2 O Sp M Crystal Oscillator Amplifier Output 96 XTAL1 Sp M Crystal Oscillator Amplifier Input To clock the device from an external source drive XTAL1 while leaving XTAL2 unconnected Voltages on XTAL1 must comply to the core supply voltage Vppi ESR2 9 SUB ESR2 Trigger Input 9 97 PORST l In B Power
124. veness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered Gatineon 16 32 Bit Architecture XC2765X 16 32 Bit Single Chip Microcontroller with 32 Bit Performance XC2000 Family Base Line Data Sheet V2 1 2011 07 Microcontrollers e XC2765X Infineon XC2000 Family Base Line XC2765X Revision History V2 1 2011 07 Previous Version s V2 0 2009 03 V1 31 2008 11 V1 3 2008 11 V1 2 2008 09 V1 1 2008 06 Preliminary V1 0 2008 06 Intermediate version Page Subjects major changes since last revisions 39 ID registers added 86 ADC capacitances corrected typ vs max 90 Conditions relaxed for Afi Range for fy adapted according to PCN 2010 013 A Added startup time from power on fspo 127 Quality declarations added Trademarks C166 TriCore and DAVE are trademarks of Infineon Technologies AG We Listen to Your Comments Is there any information in this document that you feel is wrong unclear or missing Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to B mcdocu comments infineon com Data Sheet V2 1 2011 07 e XC27
125. ystem VME so ese eee ed ER DUE a een eae Nee bees 65 Watchdog TImt x sse d asi E kee ee wae ES ee Eo eee eee 66 Clock Generation llle ee 66 Parallel Ports vise taey cs IIR exea Xn eg Res eh ans a s 67 Instruction Set Summary 000 cece eee 68 Electrical Parameters 000 0c eee ees 71 General Parameters 000 cee cece eee eee ees 71 Absolut Maximum Rating Conditions 0 0 0c eee eee 71 Operating Conditions 0 00 cece eee ee 72 Pad Timing Definition llle 74 Parameter Interpretation 0000 00 eee eee eee 74 DC Parameters iiseveiou vu Re Ge dees Bag LE REEERE DAE RE aes 75 DG Parameters 1 uxores We bw ds al SS ww RR Ue ROV weed 77 DC Parameters for Lower Voltage Area 000 eee eee 79 Power Consumption 0 000 cece eect eee 81 Analog Digital Converter Parameters llli esr 86 System Parameters 00 00 cece eee eee eee ees 90 5 V2 1 2011 07 oS XC2765X Infineon XC2000 Family Base Line Table of Contents 4 5 Flash Memory Parameters sesseeee eee 93 4 6 AC Parameters socle ls eid eb x deem re be de paced 95 4 6 1 Testing Waveforms 00 eee ellen 95 4 6 2 Definition of Internal Timing sels eee eee 96 4 6 2 1 Phase Locked Loop PLL 0 00 e eee eee eee eee 97 4 6 2 2 Wakeup Glock 5 bela be ede mn e a a a nn 100 4 6 2 3 Selecting and Changing the Oper

16/32-Bit XC2765X

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