DRS4 Evaluation Board User`s Manual
Contents
1. ai 8 N N 8 8 i e R109 ah S ll E W l a Sie 8 8 EE fa 2TADS6GSART O ls acm T d ape em T10 ag REFT We t wegl a 28 9 AD9245 E aoc P ze Pe 39 VIN 2 m B 8 ir 30 VN 1 D oS 31 GND 3 8 4 DI U20 Su 2 40V tE me 32 AVDD i a 1 475 ouors R112 AN tt 4 ADB6QSARI pi poeu ATA gt a 8 ii T12 Lt 5 GND Div 3 8 am KETO S be bi adr X hai sai air cwm ue J7 5T 3 1U22 8 8 SE R15 aa pi 21 AD8061ART ex 3 lil N Temp Sensor DRS4 8 9 70 10 2 500V RIO ae EEPROM 16 bit DAC ni U24 PT U23 o i swe ET v 1 deen vcc H8 WP U26 U25 TEMP TRIM VOUTA VOUTH s 5 ES Les vecl8 1 8 LLENA 3 NoUIB vome 4 5 gt pue I cs AS i misako vcc 4 13 500 SO Hold CS 3 IVOUTC VOUTF s 2 Ge 3 Wb sek a 2 3 ALS 116 59 5 MoUTD VOUTELI2 fans 8 WP SCKHz Sex 8 sio AL 4 6 UTE e yi 4 vss a so L Zou OMS UREF gt 10E MN VOUT 7 REF CURAS pum2. 25v we to ADC U35 1 VBUSH p 2 25v D PETO 1 cuo e Er EE 1 si Tete a 8 te ta USB_CONN_B al 5580 318188 U36 swe ER 8 8 8 3 8 8 8 8 Eos 2 27 amp mes Lu 22 HOS 41 OT19 3 Em ER 107 i 3 UND Ki UND n M A S Ki a pei E aem Kan 1410 y m9 lO 8 ND o ma 10 jo Faz I O st pereo Lo 4 0 sav FIFORDR 13 o ke HEOADRO Ho a PAS 15 lo a 3 Di x 2 js a ES LO XC3S400 TQ144 2 Hi O Pat Hod c 2 2 ko a O 3 m 2l ho d 22 we ad 23 D gt FLAGB Fe Flaca 24 YO n For Ao de me 35 ug N PBQ FDO 5 e F05 5g o uo RESET PB1 FD1 55 fa FD4 29 o PB2 FD2 27 r2 0 433v 3 2 GND AKEUP PB3 FD3 28 ros CU D PB4 FD4 Sa o LKOUT 1 PBS FD 31 FOS EEPROM 33 po mo PBG FDS S Pos E Io 36 PB7 FD7 S ror WA e 1 eco TLO FLAGA PD FDE 35 ma 5 Sa lgl a9 gu D x TLI FLAGB 0D PD1 FD9 2S Gi ao vechi Sei po SO E EZ 2 gy P TLZ FLAGC PD2 FD10 SE Er Al WP 99890 2 Ga 08980 Z4 O PD3 F01155 mn Ai SC 58550500880Z59Z00085 E PDA FD12 miz VSS SDA GEES PAQ INTO 5 PD5 rDI3 5 sis JP2 Serial REGER S PA1 INT1 PD6 FD14 mu IL 24LC128 SN jo ieu E EM PD7 FD18 ris N zi WP GND master E x amm ms Sc mode 8g 8 d 3 22 ae Era Je i 3 PES Scu 22 N ye S 3 SD O oc x GND GND GND GND mua l Qu la E SIRO DYO SLRD DMINU Des an Des Qe cl 8 8 UND sum DY1 SLWR Qax
3. co om a a 8 8 EA 3 E 3 8 Ei amp 4 o c64 ces R89 5 c66 o p zl A A A e n e Rors GND GND 3 ROFS T8 0 OFS Ze 1 250V R96 1k REF25 R97 D R105 R106 ES DRS INZ4 DRS_IN2 DRS Ri ms DRS_IN4 DRS_ INTE DRS R98 100 por 3 4 RSS 5 R100 6 7 B Ri i 39 E RIG2 10 n 12 RIGS 13 R104 1 15 16 L Ce a KS ES DRS4 Evaluation Board V4 i i Paul Scherrer Institut Rev Department TEM Lab for Electronics 1414 DRS4 0 1 5232 Villigen PSI 2 Date Mai 2011 Drawn by HU32 RS32 Filename DRS4_ Evaluation Board SWe amp t sch of 6 Se li gx V A jn X fp loc a VERA Page 25 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual A B C D REMO i an FADC pun lame TAD8605ART d au cmo c78 R107 3 8 E C ADC el m M a8 T9 Las ime sl 81 3L BI H ay ET 8 MUN 3 3VANA 3 3VANA o Ny 100 C87 9 1
4. Hz o mus S KE 34 xtaLou H a la la T32 G4 x z RESERVED 12 Q1 ar BE E xau E A N 29 E Option Platform Flash XO o sou a amp SL amme JTAG FPGA SRS SI gt ES e Bad o bad Pi U42 4 1 sis svi zi 8 amp RS Fi see ENTZ STI SJ S a J45 a 1 oo ve sc OUTGND NS NE IND NC NC VCC 5 a w ew wi o 3 ET VCCINT ki Mei T jeND TDI 4 4 TDI TDI 8 as au 5 END TDO Nous A Zenn k E CH NI ND ap GND TMS NC ap 1 2 ont N GND Vref CEOH3 NOH2 4 oli 4 NO ei XCF02S V020 taw ec T DRS4 Evaluation Board V4 Ka El Paul Scherrer Institut Rev Le Department TEM a le Lab or Electronics 1414 USB FPGA 0 1 5232 Villigen PSI t 3 3v xO Date Mai 2011 Drawn by HU32 RS32 Filename DRS4 Evaluation Board SWe t sch of 6 Page 28 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual A B C D EO SND T cr E Pete m 3 3V 3 2 1 U43 LMZ10503 WOU x de lio De aig 1 xu T IN a oU i i j i i e 3 3V CPU FPGA ADC digital mM ENg Z F 75k a 813 155 9 oi g ale Ok 318 WA 1k 5 5 A 3T aT y
5. DESA Evaluation Board E Bee 24 6 DRS4 Evaluation Board V3 Bill of Matenals sese 30 Page 3 of 36 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 1 Introduction The DRS4 chip which has been designed at the Paul Scherrer Institute Switzerland by Stefan Ritt and Roberto Dinapoli is a Switched Capacitor Array SCA capable of digitizing eight channels at sampling speeds up to 5 GSPS This chip is available through the PSI technology transfer program for other institutes and organizations In order to simplify the design process to integrate the DRS4 chip into custom electronics an evaluation board has been designed which demonstrates the basic operation of the chip It has SMA connectors for four input channels CH1 to CHA an USB 2 0 connector and a LEMO trigger input Figure 1 The board is powered through the USB port and contains an on board trigger logic It comes with MS Windows and Linux drivers and two application programs It is basically equivalent to a four channel 5 GSPS digital oscilloscope This manual describes the software installation the usage of the application programs and gives hints for developers seeking to build new electronics around the DRSA chip 1 1 Board description Since the DRS4 chip has differential inputs the board uses four active buffers THS4508 from Texas Instruments to convert the 50 Ohm terminated single ended inputs into differential signals Analog switches in fr
6. Here is a snipped of such an XML file lt xml version 1 0 encoding ISO 8859 1 lt created by MXML on Tue Feb 15 13 05 04 2011 gt lt DRSOSC gt lt Event gt lt Serial gt 1 lt Serial gt lt Time gt 2011 02 15 13 05 04 758 lt Time gt lt HUnit gt ns lt HUnit gt lt VUnit gt mV lt VUnit gt lt CHN1 gt lt Data gt 20 7 63 7 lt Data gt lt Data gt 21 7 62 3 lt Data gt lt Data gt 1033 4 424 9 lt Data gt lt Data gt 1034 4 423 3 lt Data gt CHN1 lt CHN2 gt lt Data gt 20 7 8 5 lt Data gt lt Data gt 21 7 7 0 lt Data gt lt Data gt 1033 4 8 3 lt Data gt lt Data gt 1034 4 8 2 lt Data gt lt CHN2 gt lt Event gt lt Event gt lt Serial gt 2 lt Serial gt lt Time gt 2011 02 15 13 05 04 883 lt Time gt lt HUnit gt ns lt HUnit gt lt VUnit gt mV lt VUnit gt lt CHN1 gt lt Data gt 20 6 63 0 lt Data gt lt Data gt 21 6 63 8 lt Data gt Each individual event contains a header with the serial number of that event starting with 1 and the date time it was recorded Then there is the channel data with pairs of time in ns and voltage in mV The number of channels depend on which channel was on when the data was recorded It might be a single channel CHNI or all four channels CHN1 CHN4 Please note that the XML format requires more space on your storage and takes also more CPU power to be written so the maximum data rate is limited P
7. OE OE 15E 15E 15E 15E 15E Microcontroller DRS4 Inductor Inductor Inductor Inductor Inductor Inductor Inductor Inductor Inductor Jumper Jumper HSMN A400 S8PM2 HSMM A400 U4QM2 HSMA A401 U45M1 Power Module 3A 150mA Low Dropout 150mA Low Dropout DAC Temp Sensor 24MHz MQ 30 30 40 12pf ESD Protection ESD Protection ESD Protection ESD Protection REG 1117A Low Dropout Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Page 33 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual RES 0402 R52 15E Resistor RES_0402 R59 15E Resistor RES_0402 R60 15E Resistor 16 RES 0402 R29 22E Resistor RES_0402 R30 22E Resistor RES_0402 R31 22E Resistor RES_0402 R32 22E Resistor RES_0402 R33 22E Resistor RES_0402 R34 22E Resistor RES_0402 R35 22E Resistor RES_0402 R36 22E Resistor RES_0402 R69 22E Resistor RES_0402 R70 22E Resistor RES_0402 R71 22E Resistor RES_0402 R72 22E Resistor RES_0402 R73 22E Resistor RES_0402 R74 22E Resistor RES_0402 R75 22E Resistor RES_0402 R76 22E Resistor 4 RES_0402 R5 49 9E Resistor RES 0402 R8 49 9E Resistor RES 0402 R45 49 9E Resistor RES 0402 R48 49 9E Resistor 8 RES 0402 R7 61 9E Resistor RES_0402 R10 61 9E Resistor RES_0402 R24 61 9E Resistor RES_0402 R28 61 9E Resisto
8. drs 1 0 doc manual pdf drs 1 0 include drs 1 0 include ConfigDialog h drs 1 0 include DOFrame h drs 1 0 include DOScreen h Then change the directory and do a make Note that to compile the oscilloscope application it is necessary to have the wxWidgets package version 2 8 9 or later installed You can obtain this package in source form from http www wxwidgets org downloads If this package is present you can change to the drs directory and issue a make usr local ed drs 1 0 usr local drs 1 0 make g g 02 Wall Wuninitialized fno strict aliasing Iinclude DOS LINUX DHAVE LIBUSB c src musbstd c g g 02 Wall Wuninitialized fno strict aliasing Iinclude DOS LINUX DHAVE LIBUSB c src mxml c Now you can connect the DRS4 board to the PC On systems where the Isusb tool is installed one should be able to find the DRS4 evaluation board after connecting it with following command usr local drs 1 0 sbin lsusb d 04b4 1175 v Bus 005 Device 005 ID 04b4 1175 Cypress Semiconductor Corp Device Descriptor bLength 18 bDescriptorType L bcdUSB 2 00 bDeviceClass 0 Defined at Interface level bDeviceSubClass 0 bDeviceProtocol 1 bMaxPacketSize0 64 idVendor 0x04b4 Cypress Semiconductor Corp idProduct 0x1175 bcdDevice 0 01 iManufacturer I iS Ritt PSI iProduct 2 DRS4 Evaluation Board iSerial 3 REVI bNumConfigurations 1 Configuration Des
9. will start a simple application which connects to the DRS4 Evaluation Board If it finds the board it displays the board serial number and the firmware revision as on the following screen shot ex DRS Command Line Interface DRS command line tool Revision 15584 Type help for a list of available commands Found DRS4 board on USB serial 2056 firmware revision 15158 BO Now you are ready to issue your first command info which shows some more information like the current board temperature The temperature sensor is on the bottom side just below the DRS4 chip If you keep issuing info commands and touch that sensor with your finger you should see the temperature increase ex DRS Command Line Interface DRS command line tool Revision 15584 Type help for a list of available commands ound DRS4 board on USB serial 2056 firmware revision 15158 typ Board type Serial number irmware revision Temperature Input range alibrated range 5U 6 Calibrated frequency 1 617 GHz Status reg 66660618 Domino wave running PLL locked ontrol reg D g 66666616 ODE circular requency 1 617 GHz a 3 2 Oscilloscope application drsosc The second application is an oscilloscope like program which connects to the DRS4 board and works pretty much like a normal oscilloscope You can select the trigger mode trigger level and trigger source On Rev 1 1 of the DRS4 evaluati
10. 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 C14 C25 C27 C28 C30 C33 C34 C37 C38 C11 C12 C35 C36 C76 C77 C104 C75 C74 C23 C24 C47 C48 C144 C153 C133 C134 C135 C91 C94 C54 C65 C66 C67 C69 C70 C71 C73 C78 C82 C83 C84 C85 C87 C89 C90 C92 C95 C96 C98 C100 C102 C103 C105 C106 C107 C108 C109 C110 220n 220n 220n 220n 220n 220n 220n 220n 220n 1u 1u 1u 1u 1u 1u 1u 4 7n 5 6n 10n 10n 10n 10n 10n 10n 12p 12p 15p 56p 56p 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Ca
11. FE J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual DRS4 Evaluation Board User s Manual Board Revision 4 0 as of February 2012 Last revised February 17 2012 Stefan Ritt Paul Scherrer Institute CH 5232 Villigen PSI Switzerland Email stefan ritt psi ch Phone 41 56 310 3728 Please check for possible updates of this manual under http drs web psi ch datasheets SL Jo PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Revision History Date Modification 2 March 09 Initial Revision 27 April 09 Mention input range added timing calibration description 3 Aug 09 Added LED description 12 July 10 Updated documentation for evaluation board V3 12 Sept 10 Added maximum input voltage 16 Feb 12 Added info for external connectors Page 2 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Table of Contents Revision deet 2 A AS 3 l o A OS 4 1 1 Board des Cri pt Ostrea 4 12 LEDS wA A a AA AI IA 6 1 3 Firmware DESCA EE 7 PME Mt g tt en AAA Een deiere ie tee H 2 1 Windows XP EE 9 2 2 EE 12 2 3 Ee 13 3 Running the BOSE sieut bebes ME bee dite reg 15 3 1 Command Re E EE 15 3 2 Oscilloscope application drsoSe iii rester ka vese da ea ad aeo rer cat 15 4 Development tics 21 4 1 ee OT 22 4 2 Analog E A s AAA EN MINGI MAA NAI kaa Aden 23 4 3 Conttol VoltaBes steet set un atis oda 28 4 4 ADC Clock EE 23 2
12. library files from the Cypress EZ USB development kit plus some DRS specific files CY7C68013A drs eval c Main micro controller firmware file CY7C68013A dscr a51 USB descriptor tables CY7C68013A drs eval hex Compiled firmware file Intel HEX format CY7C6801 3A drs evall iic Compiled firmware file For Cypress EZ USB Console download CY7C6801 4A Remaining files are standard files from EZ USB development kit Page 7 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual The FPGA firmware implements a set of control and status registers through which the DRS4 can be controlled and read out The mapping of the control registers is as follows Ofs Bit Name Comment 0 0x00 0 start trig Write a 1 to start the domino wave 0 0x00 1 reinit trig Write a 1 to stop amp reset the DRS chip 0 0x00 2 soft trig Write a 1 to stop the DRS chip amp read the data to RAM O 0x00 3 eeprom write trig Write contents of RAM into EEPROM 32kB page O 0x00 4 eeprom read trig Read contents of EEPROM into RAM 32kB page 0 0x02 18 led 1 on O blinks once at beginning of DRS chip readout 0 0x02 19 tcal en Switch on 1 off 0 264 MHz calib sig for DRS chips 0 0x02 20 tcal source System clock 0 or separate quartz 1 clock source 0 0x02 21 trans
13. points during the reflow process 4 2 Analog Input If non differential signals should be digitized with the DRS4 chip they must be converted into differential signals for the DRS4 inputs The simplest solution is to connect the IN inputs to AGND and to connect the signals directly to the IN inputs This method has however the disadvantage that the crosstalk and noise immunity of the DRS4 chip are worsened The evaluation board V3 uses differential drivers THS4508 from Texas Instruments for this purpose These drivers were carefully selected since they have to drive the relatively high DRS4 input current of almost 1 mA and capacitive load without compromising the analog bandwidth The current design gives about 700 MHz 3 dB with moderate power consumption so that the evaluation board can still be powered from the USB power 500 mA 5 V The linear regulator of the evaluation board V2 could however not be used since the efficiency would be too low Instead a switching regulator LMZ10503 from National Semiconductor is used on the board It has an efficiency of more than 95 and a low output ripple The output voltage of 3 3V is then converted using traditional linear regulators into two 2 5V low noise power supplies which power the analog part of the board Other designs are possible which push the analog bandwidth to 800 or 900 MHz close to the theoretical limit of 950 MHz of the DRS4 chip but they require more power The usual d
14. se hoon cas Di Ea ao TA R79 4 4 Sr EC M y H 3 a a ou an PA sL8 8 ES o THS4508 g 8 amp A R4 ES ca 1 ETA 6 del efe e ass den c8 ele sj ois 2200 og RI2 500hm 8 DRS_INZ R14 15 DRS INZ4 0 25dB eee us SUE R17 R18 1 feje sr ESL zo CM Rog se em ox Ris ois SE SE z dle Bis 1 Se apcge1 Y lel 3 Sx gei GND ols es als es GND GND 8 00 M en GND hoan C22 2 8 GND E KR COND R40 T O ES 3 a 3 n E E El 8 8 n n g NM ou an own 818 w THS4508 ms R44 SC Ta Er uw d j gl al SH bei P den 034 es als os 22 CM Rs 580hm S 8 SCT pss max J5 R57 R58 u1 1 Tee h 2 100 Been css R60 TA pen wx ml Sui s gi EL 3 ele Ss 1 ji GC HERE 6 m zi wj co sl zh sl ge GND e 4 fS f als ape o 5 er 3 UND gy Pt E heen ces KR o ki a R80 a a EH ei gt E I
15. 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 R81 R82 R85 R91 R118 R119 R123 R124 R127 R128 R131 R132 R149 R94 R95 R97 R117 R143 R155 R15 R17 R55 R57 R114 R139 R140 R21 R22 R25 R26 R61 R62 R65 R66 R151 R152 R153 R142 R108 R109 R111 R115 R116 R120 R133 R150 R110 R112 R156 R141 R154 R90 R98 R113 R137 R138 R92 R144 OE OE OE OE OE OE OE OE OE OE OE OE OE 1k 1k 1k 1k 1k 1k 1 5E 1 5E 1 5E 1 5E 2k4 2 2k 2 2k 3 6k 3 6k 3 6k 3 6k 3 6k 3 6k 3 6k 3 6k 4k7 4k7 4k7 4k7 4 7E 4 7E 4 7E 4 7E 10E 10k 10k 10k 22bE 22bE 23 7k 49 9E 75k 100E 100E 100E 100k 100k 130E 220E Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Page 35 of 36 EE PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 2 RES_0603 RES_0603 RES_0805 RES_0805 RES_0805 RES_0805 RES_0805
16. 2 LEDs The DRSA evaluation board is equipped with four LEDs They are operated by the micro controller and the FPGA and have following meaning LED Meaning Green This LED becomes green when the on board micro controller booted successfully If this LED stays dark there is either no power or the micro controller lost it s program which requires a re programming of the EEPROM Yellow When the on board FPGA boots correctly this LED becomes lit If it stays dark it might be that the FPGA program was lost and requires re programming After booting this LED indicates the board status If lit the DRS4 chip is active and sampling data If stopped by software or a trigger this LED turns off A special pulse stretcher ensures that even in high trigger rate environments this LED does not flash with more than 10Hz so the blinking can still be seen by eye Red When lit this LED indicates a error condition Page 6 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 1 3 Firmware Description Both the Windows and the Linux distribution contain a subdirectory firmware which contains the FPGA and Microcontroller firmware for the DRS4 Evaluation Board The FPGA firmware is written in pure VHDL thus making it easy to port it to other FPGA devices such as Altera or Lattice Only a few Xilinx basic components such as clock managers and I O blocks have been instantiated and
17. B first as in all Intel PC systems Page 21 of 36 J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 4 Development Hints The idea behind the evaluation board is to make first steps in using the DRS4 chip but then develop your own custom electronics around the chip The first thing to do there is to study carefully the DRS4 data sheet which can be obtained from http drs web psi ch datasheets Then have a look at the DRS4 Evaluation Board Reference Design which schematics is supplied at the end of this document When you start to design your own electronics there are however some important points which are not necessarily obvious from the data sheet or from the reference design These points together with some design tips are explained in this section 4 1 Power Supply As with any analog design the quality of the power supply is very important since it has an influence of the noise level measured by the DRS4 chip Low noise linear regulators together with the usual decoupling capacitors are recommended for all power supplies The analog power supply AVpp powers only the domino circuit of the DRS4 chip and directly influences the jitter of the sampling frequency Long term variations in this power supply seconds are regulated by the on chip PLL but high frequency noise in the MHz region leads directly to an increase of the PLL jitter Therefore the evaluation board contains two separate 2 5V linear regula
18. Channels 9 1to4 ES lower half Horizontal C V Connect reference clock to channel 4 A 20 ns div Input Range 0 5Yto 0 5Y O 0 05vto 0 95Y O OVto 1V Sampling Speed 2 GsPS v Actual speed 1 982 GSPS Voltage Calibration Voltage on 0 Apply Primary Calibration Cell 100mV 10mY Apply Secondary Calibration Readout w Remove Spikes Cursor Execute Voltage Calibration A Snap Utility i Save Print Timing Calibration Measure Display Rotate waveforms relative to trigger A Gees Config Display timing calibrated waveforms Correct horizontal trigger position Execute Timing Calibration About e jJ 100 mv div Connected to USB board 0 serial 3000 firmware revision 15158 T 46 2 C The effect of the timing calibration can be tested by turning the timing calibration on and off via the Display timing calibrated waveforms check box Page 19 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual You can save a waveform in an ASCII and a binary format by pressing the Save button After you open a file each trigger will write the waveform of the active channel s to that file When you are continuously running the file will grow very quickly If the file has the extension xml it will be written in ASCII form using XML encoding otherwise a raw binary file will be written
19. E Magic number for DRS board identification o 0x02 15 8 board type 5 Eval Board V2 7 Eval Board V3 0 0x02 7 0 dre type 4 for DRS4 1 0x04 8 running while domino wave running or readout in progress __ 8 0x20 31 16 temperature temperature in 0 0625 deg units 9 0x4 31 16 serial ame Serial number CMC board o 0x26 15 0 version fw firmware version SVN revision All registers are implemented as 32 bit registers so they can be mapped easily into some VME address space for example if one decides to build a VME board containing the DRS4 Page 8 of 36 FE J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 2 Installation 2 1 Windows XP Under MS Windows it is important to install the necessary driver before connection the DRS4 Evaluation Board with the PC The current distribution can be downloaded from http drs web psi ch download The Windows version contains a single program drs xx exe where xx is the version which can be executed to install the driver applications documentation and source code Executing this file starts the installer DRS Setup Welcome to the DRS Setup Wizard This wizard will guide you through the installation of DRS It is recommended that you close all other applications before starting Setup This will make it possible to update relevant system files without having to reboot your computer Click Next to c
20. F4 ay ay e738 ge le e N za N S SN 3 3V 5 wid U44 Si Hi vn e 3 3VANA ADC DAC 2 3 SR ie BY lg sla 518 5138 LP2985 3 3 5 1 518 2738 erh ST e738 GND OD GND o aw 2 5V Be U45 Se 1 1 vk vom 7 E 2 5V AVDD DRS4 analog bore BYA 4 XE d LP2985 25 18 218 273 ST 273 OD KZ a 2 5V 25 3 U46 dT 3 t T N ot e 2 5V DVDD DRS4 FPGA digital M LEN 2 wd PA 55 SI Be TPS79625 Be FP1 FP2 1 2V 35 Gi Gi U47 a FP_1MM FP_1MM T T QU 1 1 2V FPGA INT ld REG1117 1 2 9 1 5 e 273 a T ZE E _ 4 E HU32 11 2 2 DRS4 Evaluation Board V4 EE em s 5232 Viligen PSI 9 1 Date Mai 2011 Drawn by HU32 RS32 Filename DRS4_ Evaluation Board SWe amp t scB of 6 A B C D Page 29 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 6 DRSA Evaluation Board V3 Bill of Materials Count ComponentName RefDes Value Description 1 24LC128 SN U38 EEPROM 16k x 8 1 25LC1024SM U26 EEPROM 1 AD8061ART U22 Amplifier 3 AD8605ART U18 Amplifier AD8605ART U19 Amplifier AD8605ART U20 Amplifier 1 AD9245 U21 ADC 4 ADCMP601 U13 Comparator ADCMP601 U14 Comparator ADCMP601 U15 Comparator ADCMP601 U16 Comparator 4 ADG901 U1 Wideband SPST Switches ADG901 U3 Wideband SPST Switches ADG901 U7 Wideband SPST Switches ADG901 U9 Wideband SPST Switches 1 ADRO3 U24 2 5V Ref 4 BAV99 U28 Diode BAV99 U30 Diode BAV99 U32 Diode BAV99 U34 Diode 1 CAPP C138 220u Tantal gt 10V 4 CAP 0402 C51 10n Capacito
21. RES_0805 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 RES_1206 SMA_SMD_S SMA_SMD_S SMA_SMD_S SMA_SMD_S SN74LVC1T45DB SN74LVC1T45DB SN74LVC1T45DB SN74LVC1T45DB THS4508 THS4508 THS4508 THS4508 TPS79625 USB CONN B VX3 XC3S400 TQ144 XCF02S V020 Page 36 of 36 R145 R87 R88 R89 R93 R107 R136 R96 R121 R122 R125 R126 R129 R130 R134 R135 R157 J1 J2 J4 J5 U27 U29 U31 U33 U2 U4 U8 U10 U46 U35 Q2 U36 U42 220E 390k OE OE OE OE OE 1k 51E 51E 51E 51E 51E 51E 51E 51E 120E Transceiver Transceiver Transceiver Transceiver 66MHz Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor SMA Connector SMA Connector SMA Connector SMA Connector Bus Transceiver Bus Transceiver Bus Transceiver Bus Transceiver Amplifier Amplifier Amplifier Amplifier Low Dropout Oszillator VX3 3 3V FPGA EEPROM
22. age 20 of 36 BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual The binary format requires less space and can be written faster but it requires a special program to read and analyze the data Word Byte 0 Byte 1 Byte 2 Byte 3 Contents 0 YE gi pr RI Event Header 1 Serial number Serial number starting with 1 2 Month 3 Hour A Event date time 16 bit values 4 Minute Second 5 Millisecond reserved 6 Time Bin 0 7 moo Time of sample bins in ns encoded in 4 Byte floating point format 1029 Time Bin 1023 1030 Yo ud Ki E Channel 1 header 1031 Voltage Bin 0 Voltage Bin 1 1032 Voltage Bin 2 Voltage Bin 43 Channel 1 waveform data encoded in 2 Byte integers 0 0 5V and 65535 0 5V 1542 Voltage Bin 1022 Voltage Bin 1023 1543 SN YO YO SCH Channel 2 header 1544 Voltage Bin 0 Voltage Bin 1 1545 Voltage Bin 2 Voltage Bin 43 Channel 2 waveform data encoded in 2 Byte integers 0 0 5V and 65535 0 5V 2055 Voltage Bin 1022 Voltage Bin 41023 2056 YE H p RI Next Event Header Depending on the number of channels which are on during data acquisition the file contains up to four channels which can be identified by their channel headers Then the next event follows which can be identified by the event header EHDR All multi byte data is encoded with LS
23. cations appear Make sure that you are logged in as an administrator to install the software During the installation process you will see a notice about some unverified driver software Please select Install this driver software anyway to install the driver r ta Windows Security mm Kl Windows can t verify the publisher of this driver software Don t install this driver software You should check your manufacturer s website for updated driver software for your device 3 Install this driver software anyway Only install driver software obtained from your manufacturer s website or disc Unsigned software from other sources may harm your computer or steal information v See details After the software has been installed you can connect the DRS4 Evaluation Board to the computer The driver installation should then start automatically and you will see this notification r _ Driver Software Installation x Installing device driver software DRS4 Evaluation Board Installing driver software Close When this has finished you can start the drscl and drsosc programs Page 12 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 2 3 Linux The drivers and applications are distributed for Linux in source code and must be compiled on each system First untar the tar ball usr local tar xzvf drs 1 0 tar gz drs 1 0 drs 1 0 doc drs 1 0 doc DRS4 rev06 pdf
24. ch C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C124 C125 C126 C127 C128 C129 C130 C132 C137 C147 C150 C143 C79 C86 C93 C99 C101 C140 C145 C146 C148 C149 C151 C152 C154 C156 C17 C18 C41 C42 C64 C68 C72 C80 C81 C88 C97 C122 C123 C136 C141 C155 C139 C131 C142 C57 C61 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100n 100p A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu A Cu 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 10u 22u 100n 47u 100u 100u Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V
25. criptor bLength 9 bDescriptorType 2 wTotalLength 46 bNumInterfaces i bConfigurationValue i iConfiguration 0 bmAttributes 0x80 MaxPower 500mA Page 13 of 36 FL Jo PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual If the board is correctly recognized one can access it with the command line program Under most Linux distributions however only the root user can directly access USB devices Some systems can be configured to allow non root access via the udev system but the exact instructions vary from distribution to distribution and can therefore not be given here If the command line program works the oscilloscope application drsosc can be started It will open a X window and show exactly the same functionality as its Windows counterpart ritt pc6562 1 afs psi ch user r ritt meg online driver f A Session Edit View Bookmarks Settings Help root pc6562 1 drsosc drsosc a Start Here 5 DRS Oscilloscope Trigger Stop L Single Elopp FEY Force Trigger D Normal 4 Horizontal q 100 ns div Vertical Utility Save Print Config Measure About Exit 13 10 1 E a q e Mond a S gua a 2009 03 02 Page 14 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 3 Running the Board 3 1 Command line Interface drscl Clicking on DRS Command Line Interface Windows or entering drscl Linux
26. d to generate the phase shift between these two clocks with a low jitter delay circuit Page 23 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 5 Option DRS4 Evaluation Board V4 Schematics op n ou 5 8 8 1 TE THS4508 ENN 8 R2 ET w 3 e 3 P a MOES e 560hm Ta 1 R13 ae GEES 25dB 169E R15 R16 1 5E o e 169 zen CH pg ise ee Je Em Be al ER ele i 1 ADG901 zg al Su lu S ND SN 28 28 us Ga ee N l ND gt heon c21 9 CIE a R39 d a EIS bani VE IR A 8 2 T iz je ITT T n E H B mp op ou 818 Fe i THS4508 gi 8 8 8 R42 ES pa ET E 8 gfe Cuore ois R51 560hm e R53 GL ons Nc 0 25dB 4 e esr e R55 R56 La er l se R59 13E d SEE 3 as EE GE 3 els 1 giu Su Cal eue an mo es sg RIS ES To Ga 3 n
27. esign rules like proper termination matched impedance PCB traces and separate power supply PCB planes apply as in any high frequency analog design 4 3 Control Voltages The DRSA chip requires certain control voltages ROFS O OFS and BIAS The latter two are generated internally with some default voltage but can be overwritten by an external low impedance source It is recommended to connect these lines to an external 16 bit DAC so that the DRS4 input range can be fine tuned on a board by board basis to compensate for chip variations The ROFS signal should be driven by a high speed low noise buffer If this signal would be directly connected to the DAC output the signal height would change slightly during the chip readout and the measurement would show a varying baseline level 4 4 ADC Clock There is a very strict relation between the DRS4 output shift register clock SRCLK and the ADC clock see DRS4 data sheet WAVEFORM READOUT In order to reduce the noise due to aperture jitter the phase shift between these two clocks must be fixed and contain very small jitter 10ps The easiest way to generate this phase shift is to use the digital clock managers DCM in the FPGA as it is done on the evaluation board Since the DCMs have however an inherent phase jitter of up to 150ps this introduces some noise in form of a baseline variation when sampling a DC signal in the order of up to a few mV If this becomes a problem it is recommende
28. f 36 FL Jo PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual i E DRS Oscilloscope Trigger Stop Single Force Trigger Connected to USB board 0 serial 3000 firmware revision 15158 T 46 6 C This calibration data both for voltage and timing is then stored in the EEPROM on the evaluation board from where it is obtained each time the oscilloscope gets started This assures that a board is calibrated even when used on different computers Note however that the timing calibration is only valid for some sampling speed So if you want to run the board at a different speed you have to redo the timing calibration at that speed The voltage calibration is a bit less dependent on the sampling speed there is however some dependence on temperature It is advised to keep the board running for a few minutes until the temperature shown in the status bar stabilizes before doing a voltage calibration Page 18 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual For test purposes an internal 60 MHz reference clock signal can be connected to channel 4 via the Config menu To do so activate channel 4 then select the Config menu and click on Connect reference clock to channel 4 i A DRS Oscilloscope Trigger Period CH4 16 as 16 489 16 916 16 696 fa 8 100 n stp USB DRS 0 serial 3000 v ONormal Auto i010203 40ExT
29. gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual CO A AA N a N haa CONN_MOLEX_JTAG_FPGA CY7C68013 56 DRS4_76 IND_0603 IND_0603 IND_0603 IND_0603 IND_0603 IND_0603 IND_0603 IND_0603 IND_1008 IND_1812 IND_1812 JMP2MM JMP2MM LED_PLCC 4 LED_PLCC 4 LED_PLCC 4 LMZ10503 LP2985 2 5 LP2985 3 3 LTC2600 MAX6662 MMCX 90 MMCX 90 MMCX 90 MMCX 90 QUARZ_NKS7 RCLAMP0502B RCLAMP0502B RCLAMP0502B RCLAMP0502B REG1117 1 2 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 RES 0402 U41 U43 U45 U44 U23 U25 J18 J30 J39 J41 Q1 U5 U11 U12 U47 R1 R3 R37 R38 R41 R43 R77 R78 R99 R100 R101 R102 R103 R104 R105 R106 R146 R147 R148 R11 R12 R19 R20 R51 JTAG 220nH 220nH 220nH 220nH 220nH 220nH 10u 10u 10u WP WP green yellow 24MHz OE OE OE OE OE OE OE OE OE OE OE OE OE OE OE OE
30. hannel 4 Input Range 0 5Yto 0 5Y O 0 05Yto 0 95Y 0Yto 1Y Sampling Speed 5 GSPS v Lock Actual speed 5 12 GSPS Voltage Calibration Voltage on 0 Apply Primary Calibration Cell Apply Secondary Calibration Reado Remove Spikes Execute Voltage Calibration Timing Calibration Rotate waveforms relative to trigger Display timing calibrated waveform Correct horizontal trigger position Execute Timing Calibration The calibration can be re done any time by clicking on the Execute Voltage Calibration and Execute Timing Calibration buttons For the voltage calibration the inputs are switched to a calibration voltage generated by a DAC Three calibration points 0 4V OV 0 4V are taken and an offset and gain is evaluation For the timing calibration an internal 240 MHz clock is sampled in one channel and the deviation from the expected period to the measured period is used to determine the effective width of each cell Following picture shows the result of such a timing calibration done at 2 GSPS The effective bin width deviates only slightly from the nominal value of 0 5 ns but the integral timing nonlinearity adds up to almost 1 ns which is typical for the DRS4 chip Since transistor parameters have normally gradients over the chip wafer SCA chips are usually faster on one side compared to the other Page 17 o
31. location Advanced Click Next to continue Where you can click Install the software automatically and then click Next Page 10 of 36 FE J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual After successful installation of the driver you will see the following window Found New Hardware Wizard Completing the Found New Hardware Wizard The wizard has finished installing the software for e DRS4 evaluation board Click Finish to close the wizard And a new group in your Start Menu DRS Oscilloscope ll DRS Command Line Interface T DRS4 Datasheet X Evaluation Board Manual All Programs Uninstall DRS Software The software comes with two applications a command line interface and an oscilloscope These applications are explained in section 3 Page 11 of 36 FL J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 2 2 Windows 7 The installation under Windows 7 32 and 64 bit is basically the same than for Windows XP You need the DRS software version 3 0 1 or later if you are using a 64 bit system since version 3 0 0 and prior does not contain the 64 bit version of the libusb library When you start the software installation you get an additional screen which you have to confirm Tei User Account Control EJ Program name drs301 exe Publisher Unknown File origin Downloaded from the Internet vV Show details Yes Change when these notifi
32. must be adapted when another FPGA manufacturer than Xilinx is chosen The FPGA source code is contained in several files with following contents src drs4 evall vhd Top level entity Routing of clock signals global reset signal LEDs and LEMO input src drs4 evall app vhd Main file containing state machines for DRS4 readout serial interface to DAC EEPROM and temperature sensor trigger logic and reference clock generation src usb dpram vhd Instantiates block ram for waveform storage src usb racc vhd Interface to CY2C68013A microcontroller in slave FIFO mode Implements a set of status and control registers through which the main application can be controlled src usr clocks vhd Generates 66 MHz 132 MHz 264 MHz and a phase shifted 66 MHz clock out of the 33 MHz quartz input frequency via the Xilinx Digital Clock Managers DCM ucf drs4 evall ucf Constraint file Assigns package pins and defines clock constraints 3s400 drs4 evall ise Xilinx ISE 9 2i project file 3s400 drs4 evall bit Compiled firmware image directly for Spartan 35400 FPGA 3s400 drs4 evall mcs Compiled firmware image for FPGA EEPROM XCF02S 3s400 drs4 evall ipf Xilinx Impact project file to program FPGA via download cable The firmware for the USB microcontroller from Cypress is written in C and must be compiled with the Keil 8051 C compiler It contains the standard include and
33. nput a commercial adapter can be used like the one shown in Figure 2 MMCX SMA adapter which can be obtained for example form www digikey com part number ACX1352 ND The Trigger OUT and the Clock IN OUT signals will be supported in a later firmware version and will allow for inter board triggering so that small synchronized DAQ systems with several evaluation boards can be made Four on board discriminators with programmable level allows for self triggering on any of the four input channels or a combination of channels supporting coincidences for example A 1 MBit EEPROM 25LC1025 from Microchip is used to store the board serial number and calibration information Two 14 pin headers carry all important logical signals which allow easy debugging with a logic analyzer or oscilloscope A JTAG adapter can be used to update the FPGA firmware through a Xilinx Platform Cable Adapter The specifications of the board inputs is summarized in following table Analog inputs Termination 50 Q Input range 1 V p p AC coupled Maximum allowed input voltage DC 10V Long pulse 2us 20V Short pulse 200ns 30V Trigger input Clock input Termination high impedance optionally 50 Q Maximum allowed input voltage 0 5Vto 5 5V 5V TTL compatible High Level Input Voltage 2 5 V min Trigger output Clock output Level 5V TTL Page 5 of 36 BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 1
34. on board only CHI can be selected as trigger source You enable a channel by clicking on the number 1 to 4 There are two cursors and a few utilities Page 15 of 36 FL Jo PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Stop Single Force Trigger Normal 2 Auto 1 20304 EXT A B Msna Save Print Measure Display Config About Exit Let Connected to USB board 0 serial 3000 firmware revision 15158 T 45 5 C The picture above shows an un calibrated evaluation board which shows a noise level of about 8 mV RMS After offset and gain calibrations the noise level is reduced significantly Single Force Trigger Normal 2 Auto Print Display About Ext Tech Connected to USB board 0 serial 3000 firmware revision 15158 T 44 7 C The evaluation board Rev 3 still shows some small random spikes It is expected that future versions will improve this and reduce the noise level further Page 16 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual The DRS4 evaluation board is shipped pre calibrated in amplitude and time This calibration can be turned on or off using the check boxes Display calibrated waveforms and Display timing calibrated waveforms in the Config Dialog Configuration Board EERSTE y _Rescao Info Channels O 1to4 lower half Connect reference clock to c
35. ont of the buffers ADG901 form Analog Devices are used to de couple the inputs during calibration Two reference voltages are generated by the on board 16 bit DAC to measure the offset and gain of all DRS4 storage cells for calibration The four analog inputs are AC coupled and have a input range of 1 V peak to peak The absolute maximum input voltage range is 0 5V to 2 8V The DRSA is read out with a 14 bit ADC AD9245 from Analog Devices and a FPGA Xilinx Spartan 3 The USB connection is implemented with a micro controller Cypress CY2C68013A The high speed modus of the USB 2 0 bus allows for data transfer rates of more than 20 MB sec Switching SS QUO ye BE mr Tscs SC ER on H ee SRCLK SRIM RSRLOADI AG A2 A1 Figure 1 Picture of the DRS4 Evaluation Board V4 with different components Page 4 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual For trigger purposes and inter board synchronization four MMCX connectors are available which can be seen on the right side of Figure 1 The Trigger IN works as an external trigger much like the one of an oscilloscope The electrical standard is 5V TTL Although a 50 Q termination is possible the resistor is not soldered by default This allows using weaker sources which cannot drive 5V into a 50 Q load Reflections on this line usually do not matter since the first leading edge of the trigger is used To connect a SMA cable to the trigger i
36. ontinue Cancel You can select which components to be installed DRS Setup Choose Components Choose which Features of DRS you want to install This will install the DRS software on your computer Select which optional things you want installed Select components to install Space required 2 8MB Description IM DRS software required pa E Se v Start Menu Shortcuts v DRS source code Page 9 of 36 FE J PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Then you can select the installation directory DRS Setup Choose Install Location Choose the folder in which to install DRS Choose a directory to install in to Destination Folder Program FilesiDRS Space required 2 8MB Space available 148 3GB After the installer has finished you can connect the DRS4 Evaluation Board to the Computer DRS Setu ae Installation Complete E Setup was completed successfully A Completed T Show details DRS Setup Setup has completed You can now connect the DRS4 evaluation board Now you will see the Found New Hardware dialog Found New Hardware Wizard Welcome to the Found New Hardware Wizard This wizard helps you install software for DAS4 evaluation board DI If your hardware came with an installation CD S or floppy disk insert it now What do you want the wizard to do O Install from a list or specific
37. p mode 1 send DRS inputs to outputs transparent mode O 0x02 22 enable trigger1 Write a 1 to enable external trigger LEMO O 0x02 23 readout mode O start from first bin 1 start from domino stop 0 0x02 24 neg trigger 1 trigger on high to low transition O 0x02 25 acalib Write 1 to enable amplitude calibration 0 0x02 27 dactive O stop domino wave during readout 1 keep it running 0 0x02 28 standby 1 put chip in standby mode 1 0x04 31 16 DACO Set DAC 0 2A ROFS 1 0x06 15 0 DAC1 Set DAC 1 B CMOFS 2 0x08 31 16 DAC2 Set DAC 2 C CAL 2 OxOA 15 0 DAC3 Set DAC 3 D CAL 3 0x0C 31 16 DAC4 Set DAC 4 E BIAS 3 OxOE 15 0 DAC5 Set DAC 5 F TLEVEL 4 0x10 31 16 DAC6 Set DAC 6 G O OFS 4 0x12 15 0 DAC7 Set DAC 7 H 5 0x14 31 24 configuration Bit0 DMODE Bit1 PLLEN Bit2 WSRLOOP 5 Ox14 23 16 channel config 1 1x8k 0x11 2x4k 0x33 4x2k 0xFF 8x1k 5 0x16 7 4 first chn First channel address to read out 0 9 5 0x16 3 0 last chn Last channel address to read out 1 9 6 0x18 31 16 trigger delay Trigger delay in ticks of roughly 2 3 ns 6 Ox1A 15 0 sampling freq Sampling frequency in ticks 1024 fsamp 0 120 2 7 Ox1E 31 16 trigger config Trigger configuration 7 Ox1E 15 0 eeprom_page Page number for EEPROM communication While the mapping of the status registers is like this Tor Comment o 0x00 31 16 OxCOD
38. paces CS LD SDO LES MAX6662 m 5 L uw YA Silene SOS su D gu 25LC1024SM E MAN 4 i 8 M LTC2600 n Ko K A N von iD 27 ADRO3 ET 8 m 5 4 a Ca s DRS4 Evaluation Board V4 Paul Scherrer Institut Rev 5232 Villigen PSI Date Moi 2011 Drawn by HU32 RS32 Filename DRS4 Evaluation Board SWe t sch of 6 A B E D Page 26 of 36 BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual A B D TTL INPUT OUTPUT ii SN74LVC1T45DB U27 1 m d o tak ME roa n R120 DIR m Non 10015 J18 5 m TOJIB a2 Ext Trigger INPUT Ja 1 418 gt Al ERE 10417 AB Mwox sa d AT GND ons OU19 REFCLK_P 4 1 OU20 REFCLK_M TOJ21 PLLLCK se ap 10422 DWRITE QJ23 DENABLE NW to DRS4 Bea Pie SN74LVC1T45DB 1 1 OU25 WSROUT U29 gt 1000 ce TOU26 SROUT 2 m ya LE eee 10027 SRN DIRT Cour o 7OJ28 SRCLK RSRLOAD J32 Rus Al 2 0129 4 Ext T
39. pacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V gt 10V Page 31 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 1 CAP 0603 14 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 CAP 0805 16 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1206 CAP 1210 CAP 1210 CAP 1210 Page 32 of 36 N sch s
40. r RES_0402 R47 61 9E Resistor RES 0402 R50 61 9E Resistor RES 0402 R64 61 9E Resistor RES 0402 R68 61 9E Resistor 8 RES 0402 R6 64 9E Resistor RES 0402 R9 64 9E Resistor RES 0402 R23 64 9E Resistor RES 0402 R27 64 9E Resistor RES 0402 R46 64 9E Resistor RES 0402 R49 64 9E Resistor RES 0402 R63 64 9E Resistor RES 0402 R67 64 9E Resistor 8 RES 0402 R13 169E Resistor RES 0402 R14 169E Resistor RES 0402 R16 169E Resistor RES 0402 R18 169E Resistor RES 0402 R53 169E Resistor RES 0402 R54 169E Resistor RES 0402 R56 169E Resistor RES 0402 R58 169E Resistor 8 RES 0402 R2 348E Resistor RES 0402 R4 348E Resistor RES 0402 R39 348E Resistor RES 0402 R40 348E Resistor RES 0402 R42 348E Resistor RES 0402 R44 348E Resistor RES 0402 R79 348E Resistor RES_0402 R80 348E Resistor 3 RES 0402 R83 390k Resistor RES 0402 R84 390k Resistor RES 0402 R86 390k Resistor Page 34 of 36 BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 13 own a RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES 0603 RES
41. r gt 10V CAP_0402 C52 10n Capacitor gt 10V CAP_0402 C55 10n Capacitor gt 10V CAP_0402 C56 10n Capacitor gt 10V 15 CAP 0402 C7 100n Capacitor gt 10V CAP_0402 C8 100n Capacitor gt 10V CAP_0402 C15 100n Capacitor gt 10V CAP_0402 C16 100n Capacitor gt 10V CAP_0402 C21 100n Capacitor gt 10V CAP_0402 C22 100n Capacitor gt 10V CAP_0402 C31 100n Capacitor gt 10V CAP_0402 C32 100n Capacitor gt 10V CAP_0402 C39 100n Capacitor gt 10V CAP_0402 C40 100n Capacitor gt 10V CAP_0402 C45 100n Capacitor gt 10V CAP_0402 C46 100n Capacitor gt 10V CAP_0402 C49 100n Capacitor gt 10V CAP_0402 C50 100n Capacitor gt 10V CAP_0402 C53 100n Capacitor gt 10V 5 CAP 0402 C58 100p Capacitor gt 10V CAP_0402 C59 100p Capacitor gt 10V CAP_0402 C60 100p Capacitor gt 10V CAP_0402 C62 100p Capacitor gt 10V CAP_0402 C63 100p Capacitor gt 10V 24 CAP_0402 C1 220n Capacitor gt 10V CAP_0402 C3 220n Capacitor gt 10V CAP_0402 C4 220n Capacitor gt 10V CAP_0402 C6 220n Capacitor gt 10V CAP_0402 C9 220n Capacitor gt 10V CAP_0402 C10 220n Capacitor gt 10V CAP_0402 C13 220n Capacitor gt 10V Page 30 of 36 BSI PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual 51 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0402 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP 0603 CAP
42. r Li Hi E 8 8 jan 00 zem I TO Evaluation Board V4 Paul Scherrer Institut Department TEM DRS4 Lab for Electronics 1414 f El 5232 Villigen PSI Rev INPUT SMA 0 1 Date Mai 2011 Drawn by HU32 RS32 Filename DRS4 Evaluation Board SWeetsch of 6 D Page 24 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual D DRS 4 2 5V_ORS_A OTI Bl cst neva 2 ton reve 3 e 3 Si C 6 I T3 ADCMP601 160n c53 T4 GND ADCMP601 5 2 8 2 as sisplslsis e eis eese mn m zi sa OD ii OD s k d di ka kad al ks od mm 8 8 8 8 a KUI EA REB i E p BSBEEBBDDOEEBBE 3 VOD 223222222492 OOOOOOOOOOOOO VDD z E 8 VDD em cd D e 60 1 DD g 5 5 T EFCLK DTAPA EFCLK DSPEED 63 DTAP T7 Ke 68 PLLLCK OA 69 PLLOUT 1 z SPEED DRS4 76 fw 5 SB s pen 73 DWRITE Si a DENABLE ENABLE ST WSRIN RIN bi R93 2 xf vo KE GNI GNI el e me A SOLLAgMMTTHMNOON ZZZZZZZZZZZZZZZ
43. rigger OUTPUT tt 1 i gt E OU Ta MMCX 90 GND LOT16 70J32 TCA 0433 DTAPA se ap uti SN74LVC1T45DB GND TP u31 mem tht svece veca ic Gees 3 R133 Ew ee t a 959 a R129 8 A J340 1 amp REF CLK INPUT E 4 gt EN ako MMCX 90 Su D O T5 117 al a 1 J400 6 35 ep m SN74LVC1T45DB EES tenn cus 3 E vccB veca h HA DIR DIR Gu our ae L BtoA J41 H AtoB REF CLK OUTPUT Gi B 4 B gt AL w EX CU S 4 Au A DRS4 Evaluation Board V4 oc Ze PE 70718 Rev SSES ESL cl Testeo f To ND Date Mai 2011 Drawn by HU32 RS32 Filename DRS4 Evaluation Board SWe t sch of 6 A B D Page 27 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual
44. tors for the DRS4 chip one for the AVpp power and one for the DVpp power Although the DVpp power is called digital power it powers also the analog output buffers of the DRS4 chip and needs the same good quality than the AVpp power in order to minimize the noise of the board The DRS4 chip also contains two grounds AGND and DGND They can be either routed separately on the board and be connected at the power source or they can be directly connected to an overall dedicated ground plane of the PCB Tests have been shown that the latter choice gives slightly less noise The bottom of the QFN76 package of the DRS4 has an exposed paddle connected to the internal DGND It is recommended that this paddle is matched by a PCB pad of similar size connected to analog ground to achieve the best electrical and thermal performance of the DRS4 The copper plane should have several vias to achieve a good heat dissipation to flow through the PCB as shown in Figure 3 04 mum Page 22 of 36 PAUL SCHERRER INSTITUT DRS4 Evaluation Board User s Manual Figure 3 PCB pad under the DRS4 chip These vias should be solder filled or plugged The maximum power dissipation of the DRS4 chip is not critical 350 mW but an improved thermal stability helps the performance of any analog chip To maximize the coverage and adhesion between the DRS4 and the PCB the copper plane could be partitioned into several uniform sections providing several tie
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