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1. PUC_TORT CEREN isplay CHI i Clock Operation Filter ane Offset en Figure 5 29 AWG test setup three phase 480Hz capacitor switching transient 5 i I Figure 5 30 Output of programmable source three phase 480Hz capacitor switching transient 65 5 3 2 11kVA ASD Internal Power Supply from DC Bus This test setup consisted of an 11kVA 460V line to line ASD supplying a four pole 10hp induction motor The rest of the test setup remained the same as in the previous two ASD ride through tests Similar to the 5 5kVA ASD with internal power supply from the dc bus most of the ASD configurations and settings were kept to the factory preset conditions The same operating parameters were changed as in the 5 5kVA ASD test setup 5 3 2 1 9596 Single Phase Voltage Sag Table 5 11 shows the results of the 95 single phase voltage sag test For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E It can be seen that during the voltage sag the ripple voltage on the dc bus increases and the motor load speed reduces slightly The results are very close to the 5 5kVA ASD 90 and 100 single phase voltage sag results Table 5 11 95 single phase voltage sag results 100 Load AppliedTorque Nm 0 2 4 Speed during sag Reduction 5 3 2 2 100 Single Phase Voltage Sag Table
2. V 2662120 V 450V rms 636V peak Table 5 2 Data from a 5 single phase sag Description of Input Current in N A Single pulsed Largely unbalanced Sagged Phase two pulsed 5 2 2 1 No Load Similar to the case for a 2 single phase voltage sag a 5 single phase voltage sag on phase a during a no load condition results in the sagged phase current dropping out At no load the sagged phase current drops out for any single phase voltage sag with a magnitude greater than 2 5 2 2 2 50 Load For a 5 single phase voltage sag on phase a the input current drawn during a 50 load condition is shown in Fig 5 9 The current in phase a sagged phase has reduced to a single pulse pattern This is because the average dc bus voltage at 50 load 636 6V is very close to the peak value of the sag affected line to line voltage 636V Since the average dc bus voltage is 636 6V taking the ripple into account the minimum voltage is less than 636V and the maximum voltage is greater than 636V Again current pulse i Va is the highest and the dc bus voltage is charged to its peak value The next current pulse i Va has dropped out because the dc bus 46 voltage has not yet discharged below 636V The following current pulse i Vac is lower because Vac is sagged 636V The next current pulse i Vi is again the highest current pulse since Vy is not sagged In this load condition the double
3. 00 i i 600 09 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 3 ASD dc bus voltage 2 single phase sag no load at 0 02 seconds i MJ not shown i X L X 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 4 Input current 2 single phase sag no load phases a and c shown E de bus average 656 25 637 50 1 A 637 50 n 618 75 618 75 N Y 4 603 ag 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 5 ASD dc bus voltage 2 single phase sag 50 load i X not shown i Wa not shown i V da Me 10 789 13 JL i i e J T 0 00000 0 02000 12 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 6 Input current 2 single phase sag 50 load phases a and c shown dc bus average Los SEEN os ria 6 a 60 jo 20 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 7 ASD dc bus voltage 296 single phase sag full load l NW A ll nn Figure 5 8 Input current 2 single phase sag full load phases a and c 15 714 c shown 45 5 2 2 5 Single Phase Voltage Sag For a 5 single phase voltage sag on phase a the corresponding input phase and line to line voltages are V 25320 450V rms 636V peak V 2662240 V 460V rms 650V peak 5 2
4. 13 single phase sag 50 load 51 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 7 Seconds Figure 5 14 Input current 13 single phase sag full load 5 2 5 17 Single Phase Voltage Sag For a 17 single phase voltage sag on phase a the corresponding input phase and line to line voltages are V 22120 V 422V rms 597V peak V 2662240 V 460V rms 650V peak 5 5 V 2662120 V 422V rms 597V peak Table 5 5 Data from a 17 single phase sag 100 Load ENE s N Description of Input Current in N A N A N A Sagged Phase 52 5 2 5 1 5096 Load For a 17 single phase voltage sag on phase a the input current drawn during a 50 load condition is shown in Fig 5 15 Again the input current on the sagged phase has completely dropped out and only two of the six line to line voltage pulses are conducting current meaning the three phase rectifier is operating as a single phase rectifier The average dc bus voltage during the voltage sag 636 1V is higher than the peak sagged line to line voltage 597V 5 2 5 2 100 Load The input current for a 17 single phase voltage sag on phase a during a 100 load condition is shown in Fig 5 16 The current drawn by the sagged phase now has completely dropped out and the three phase rectifier is operating as a single phase rectifier The average dc bus voltage during the voltage sag 620 7V is much higher than the pea
5. 4 12 In the case of an unbalanced voltage sag the motor terminal voltages are significantly less affected than the supply terminal voltages and the unbalance is dependent on the size of the dc bus capacitor and the motor speed The motor voltages for a dc bus voltage V t are the product of the required motor voltage and the per unit dc bus voltage V V t XV cos 22f 1 V V t XV cos 27f t 120 4 13 V V t XV cos 2zf t 120 If the motor frequency is not equal to the system frequency the ripple in the dc bus voltage is not synchronized with the motor voltages possibly leading to unbalances and interharmonics in the motor terminal voltages It was shown in 2 that for most unbalanced voltage sags even a small dc bus capacitance significantly reduces voltage unbalance and the motor frequency only contributes to voltage unbalances and interhamonics over a small range Therefore it is reasonable to assume that in most cases of voltage unbalance at the supply terminals the voltage at the motor terminals is relatively balanced especially for ASDs with larger dc bus capacitances The calculations for motor slip with balanced voltage sags are then still applicable for unbalanced voltage sags In cases where there is a serious voltage unbalance at the motor terminals the motor slip approximation should be calculated with positive sequence voltages In general the affect of unbalanced voltage sags on motor speed
6. 5 16 65 single phase voltage sag phase a regular configuration st 69 5 17 100 single phase voltage sag phase a regular configuration 70 5 18 30 two phase voltage sag phases a and b regular configuration 71 5 19 20 two phase voltage sag phases b and c regular configuration 71 5 20 20 three phase voltage sag regular configuration a 12 5 21 50 two phase voltage sag phases b and c modified configuration 72 5 22 30 three phase voltage sag modified configuration LLL 73 5 23 Summary of ASD Ride Through Results 75 LIST OF APPENDICES Page Appendix A Procedure to Operate Program AWG LLL 87 Appendix B LabVIEW Individual Function Blocks LLL 93 Appendix C LabVIEW Instrument Driver Profile Blocks Ls 95 Appendix D Procedure to Create New Instrument Driver Profile Blocks ose 105 Appendix E ASD Ride Through Characterization Figures ooo eee eee cee 109 El 11kVA ASD Internal Power Supply Derived from DC Bus 109 E2 5 5kVA ASD Internal Power Supply Derived from 1 Phase Transformer 114 E3 5 5kVA ASD Internal Power Supply Derived from 3 Phase Transformer 122 LIST OF APPENDIX FIGURES Figure C1 1 Front panel window for Query Internal Memory profile block C2 1 Front panel window for Upload All Waveform Files profile block C3 1 Front panel window for Upload Waveform File profile block C4 1 Front panel window for Upload All Sequence Equat
7. Square D ALTIVAR 58 Adjustable Speed Drive Controllers Installation Guide Bulletin No VVDED397048US Revision 4 April 1999 Jose L Duran Gomez Prasad N Enjeti and Byeong O Woo Effect of Voltage Sags on Adjustable Speed Drives A Critical Evaluation and An Approach to Improve its Performance IEEE APEC Conference pp 774 780 June 1999 Powerex Inc Three Phase Diode Bridge Modules ME701603 Datasheet Mark McGranaghan Power Quality Standards An Industry Update Power Quality Assurance vol 12 no 3 pp 34 40 March 2001 43 44 45 46 47 48 49 85 Doug Dorr Resolving Voltage Problems with AC Induction Motors Power Quality Assurance vol 12 no 3 pp 41 45 March 2001 J Duncan Glover and Mulukutla Sarma Power System Analysis and Design PWS Publishing Company 1994 E R Collins Jr and R L Morgan A Three Phase Sag Generator for Testing Industrial Equipment JEEE Transactions on Power Delivery vol 11 no 1 pp 526 532 January 1996 Abdurrahman Unsal 4 DSP Controlled Resonant Active Filter for Current Harmonic Mitigation in Three Phase Power Systems Ph D thesis Oregon State University 2000 Marcel Merk Active Power Filter for the Cancellation of Harmonic Line Current Distortion M S thesis Oregon State University 2000 Christopher J Melhorn Aubrey Braz Peter Hofmann and Ralph J Mauro An Evaluation of Energy Storage Techniques for Improv
8. phase to phase voltages is not affected the dc bus voltage is able to maintain a voltage above typical undervoltage trip levels Therefore under no condition will the dc bus voltage of an ASD fall below the undervoltage trip point due to a single phase voltage sag The reason then that ASDs trip offline during single phase voltage sags has to do with the internal power supply and other external circuits that interface with an ASD to control its functions and operations In many cases the internal power supply and external circuitry is powered by single phase sources that are susceptible to single phase voltage sags 31 34 The relationship between input voltage sag magnitude and dc bus voltage level will be analyzed in more detail in the next section 28 43 Voltage Sags and DC Bus Voltage In some cases ASDs trip offline due to a low voltage on the dc bus The dc bus voltage is maintained from the three input ac voltages through the diode rectifier The dc bus capacitance acts to smoothen the ripple voltage seen on the dc bus The dc bus capacitor is charged by the three phase rectifier six times in every cycle Fig 4 2 shows the dc bus voltage during normal operation for various capacitor sizes The dc bus voltage ripple is larger for a smaller dc bus capacitance The solid line shows the dc bus voltage for a large dc bus capacitance and the dashed line shows the dc bus voltage for a small dc bus capacitance The largest ripple voltage shown
9. 0 10 2 Drive Trip Y N With the modified ASD configuration that replaced the single phase internal power supply transformer with a three phase transformer it was determined that the ASD can ride through a complete single phase voltage sag on any of the three input phases The test results for a complete single phase sag on any phase with the modified ASD configuration match very closely with the results in Table 5 17 5 3 3 2 Two Phase Voltage Sags Regular Configuration The test results for a 30 two phase voltage sag on phases a and b supplying the ASD are shown in Table 5 18 For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E For this magnitude of voltage sag the drop in speed and dc bus voltage is greater than for any magnitude single phase voltage sag When either a 25 or a 30 two phase voltage sag was applied to phases b and c the ASD tripped offline due to a control power low error Also when a 50 two phase voltage sag was applied to phases a and b the ASD tripped offline due to a control power low error 71 Table 5 18 30 two phase voltage sag phases a and b regular configuration Nolo 50 Load Applied Torque Wm o 10 20 The test results for a 20 two phase voltage sag on phases b and c supplying the ASD
10. 8 2001 Commencement June 2002 Master of Science thesis of Evelyn Matheson presented on June 8 2001 APPROVED Redacted for privacy Major Prdfessor reprefenting Electrical and Computer Engineering Redacted for privacy Head of Department of Electrighl and Computer Engineering Redacted for privacy Dean of Grad te School I understand that my thesis will become part of the permanent collection of Oregon State University libraries My signature below authorizes release of my thesis to any reader upon request Redacted for privacy 7 Evelyn Matheson Author ACKNOWLEDGMENT First I would like to thank my major professor Dr Annette von Jouanne for her guidance support and enthusiasm during the time that I have been a part of the energy systems group I would also like to thank Dr Alan Wallace for providing me with the opportunity to be involved in numerous research and testing projects in the MSRF I would also like to thank the other members of my program committee Dr Molly Shor and Dr Roger Graham I would like to express my gratitude to the American Association of University Women Educational Foundation for substantially funding my first year of graduate studies through a Selected Professions Fellowship I would like to thank energy systems group my fellow peers in the who have given me much assistance motivation and friendship during the past several years especially Manfred Dittrich Richard Jeffryes An
11. Commercial Facilities Power Quality Assurance vol 11 pp 48 54 July August 2000 Mark McGranaghan and Jeff Smith Controlling Harmonics on the Distribution System Power Quality Assurance vol 11 pp 40 44 May June 2000 William E Brumsickle Robert S Schneider Glen A Luckjiff Deepak M Divan and Mark F McGranaghan Dynamic Sag Correctors Cost Effective Industrial Power Line Conditioning IEEE Transactions on Industry Applications vol 37 no 1 pp 212 217 January February 2001 Square D REACTIVAR Power Quality Protection www squared com Behlman Electronics Inc Operating Manual PA Plus Series AC Power Source Revision B July 1996 Jaye Killian Using the AWG2005 with the Behlman PA Plus Series Amplifiers June 1999 IOtech Inc PowerVista 312 User s Manual August 1998 Sony Tektronix Corporation User Manual AWG2005 Arbitrary Waveform Generator National Instruments Corporation LabVIEW User Manual January 1998 Sony Tektronix Corporation Programmer Manual AWG2000 Series Arbitrary Waveform Generator 1994 29 30 31 32 33 34 35 36 37 38 39 40 41 42 84 Annette von Jouanne and Ben Banerjee Ride Through Alternatives for AC and DC Drives Including Medium Voltage Multi Level Inverters PQA Conference May 2000 Math H J Bollen and Lidong D Zhang Analysis of Voltage Tolerance of AC Adjustable Speed Drives for Three Phas
12. Table 5 20 20 three phase voltage sag regular configuration No Load L MeasuredParameter T NoLoad T ss Load 100 Load_ AplidToqe N 0 0 20 Speed during sag Reduction 1798 0 0 5 3 3 4 Two Phase Voltage Sag Modified Configuration The test results for a 5096 two phase voltage sag supplying the ASD are shown in Table 5 21 This two phase voltage sag was applied to phases b and c under the modified configuration which has improved the ride through capability of the ASD and prevented it from tripping offline due to a control power low error for the three load conditions For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E The drop in speed and dc bus voltage is greater than for any of the two or three phase voltage sags tested in the previous sections Under the full load condition the average dc bus voltage falls to 73 of its nominal value The speed of the motor during the voltage sag also decreased by a significant amount dropping by over 4 from its nominal value Table 5 21 50 two phase voltage sag phases b and c modified configuration Applied Torque Nm 0 1 20 Drive Trip Y N 73 5 3 3 5 Three Phase Voltage Sag Modified Configuration The test results for a 30 three phase voltage sag supplying the ASD are shown in Table 5 22 The modified configuration has improved the r
13. a subsystem VI in the Load All Channels profile block 102 12 Set AWG Operation Mode error out error in no error Figure C12 1 Front panel window for Set Operation Mode profile block The Set Operation Mode profile block selects the output file operation mode of the AWG The options are e Continuous Mode e Waveform Advance Mode Continuous Mode is used when waveform files are loaded into channels 1 through 4 and a continuous repetition of the waveform files is desired common for simulating steady state conditions Waveform Advance Mode is used when sequence files are loaded into channels 1 through 4 The first waveform in each sequence file is repeated continuously and the following waveforms are executed in consecutive order when the trigger is pushed or started When the last waveform in the sequence file has been executed the first nominal waveform is again repeated continuously Waveform Advance Mode is commonly used to simulate transient conditions 103 13 Set AWG Channel Output error in no error Copy to Filepath Hard Copy To selected port Continuous mode Master Running computer Figure C13 1 Front panel window for Set Channel Output profile block The Set Channel Output profile block turns the output of the four AWG channels on or off For all testing configurations the output of channels 1 3 and 4 should be turned on as is shown in Fig C13 1 when using the AWG to pro
14. conditions the ASD did trip offline nearly immediately due to an undervoltage error The 50 load and full load tests were performed with and without the regenerate the kinetic energy from the machine inertia parameter set and in all cases the ASD immediately tripped offline For the test at no load the ASD input voltage current and dc bus voltage are shown in Appendix E Again the increase in the ripple voltage on the dc bus and the decrease in motor load speed are more dramatic than for 67 the single phase voltage sags and the results are similar to the 5 SkVA ASD 50 three phase voltage sag results Table 5 14 50 three phase voltage sag results Applied Torque Nm o 2 4 Speed during sag Reduction 5 3 2 5 Three Phase Capacitor Switching Transient The capacitor switching transient test was also performed on the 11kVA ASD The output voltage of the programmable source recorded at the input of the ASD as well as the input current and dc bus voltage waveforms are shown in Appendix E Again the peak phase voltage value of the transient was approximately 450V The ASD was not at all affected by the capacitor switching transient under all load conditions The dc bus voltage and the motor speed were both maintained at their normal levels similar to the 5 5kVA ASD capacitor switching transient test results 5 3 3 5 5kVA ASD Internal Power Supply from AC Input The test setup c
15. have been inserted and wired together parameter ranges default values and help files can be created In the front panel window by right clicking on any parameter a written description can be given default value set and range of possible inputs specified A new profile block VI should be saved as a vi file in same directory as the subVIs contained within the profile block Currently the AWG005 instrument driver library is located at C Program Files National Instrument LabVIEW Instr lib Tek2005 Additional detail on the LabVIEW programming environment and the construction of instrument driver VIs is provided in the LabVIEW User Manual Additional detail on the AWG2005 command syntax and processing conventions is provided in the AWG2000 Series Programmer Manual 109 APPENDIX E ASD RIDE THROUGH CHARACTERIZATION FIGURES 1 11kVA ASD Internal Power Supply Derived from DC Bus MAU v 0 00000 0 02000 0 0 10000 Figure E1 1 ASD input voltage 95 single phase voltage sag E1 Zone 489 00 gt 432 0C 0 00000 0 03799 0 07599 0 11398 0 15198 0 18997 Figure E1 3 ASD dc bus voltage full load 110 i oomed 0 00000 0 01799 0 03599 0 05398 0 07198 0 08997 i A S N om 6 60 0 00000 0 02245 0 04490 0 06734 0 08979 0 11224 Seconds Figure E1 6 ASD dc bus voltage full load 4 355 00 cored gt 355 00 0 00000 0 04474 0 08948 0 13422 0 17896 0 223
16. high impedance at its tuned frequency thereby blocking the flow of harmonic currents into the power system Passive filters must be carefully designed and derated to allow for harmonics also absorbed from the power system as well as possible resonance problems with power factor correction capacitors Active filters monitor the load current to be filtered and use pulse width modulation inverter technology to inject compensating current equal to the load harmonic current but with the opposite phase in order to cancel the harmonic currents flowing in the power system Hybrid filters use a combination of both passive and active filters to cancel load harmonics with the goal of reducing initial costs and component rating requirements enabling their use for high power nonlinear loads 14 Research Project With the increased attention on high efficiency and controllability of industrial processes as well as reduced weight volume and cost of consumer products the applications of power electronic converters such as adjustable speed drives ASDs switch mode power supplies and programmable logic controllers PLCs are showing a rapid rise Investigating and mitigating power quality issues pertaining to the input supply of power electronic equipment are extremely important in maintaining a high level of reliability and productivity In response to these 1 5 Organization of Thesis The thesis is organized according to the following description of cha
17. link PWM Inverter Input 3ph Source Figure 4 1 Topology of an ac adjustable speed drive 26 An ASD is considered a nonlinear load because the diode rectifier front end draws non sinusoidal current when supplied with a balanced sinusoidal input voltage Typical ASD input currents contain odd harmonics which can be determined by h kg k 4 1 The order of the harmonic is A k is an integer beginning with k 1 and q is the number of pulses of the rectifier system The topology of the ASD shown in Fig 4 1 has a conventional six pulse rectifier because the dc bus voltage is defined by portions of the line to line input voltage that repeat with a 60 duration one 360 cycle contains six pulses of the input voltage 13 14 Power quality problems associated with harmonics and harmonic mitigation technologies were discussed in Chapter 1 4 2 ASD Susceptibility As a critical component of manufacturing processes ASD downtime due to offline tripping caused by power quality disturbances contributes substantially to lost productivity and revenue for industrial customers Voltage sags transients and momentary interruptions of power together constitute 92 of the power quality problems encountered by typical industrial customers according to a study sponsored by the Electric Power Research Institute EPRI in collaboration with 24 utilities Productivity loss due to deep voltage sags and brief power interruptions has been calle
18. much of the driver VI modification involved incorporating additional functionality and changing the programming syntax that was different between the two models 28 Action Status Figure 3 1 Tree of AWG2041 instrument driver VIs 3 4 LabVIEW Virtual Instrument Overview LabVIEW is a general purpose programming system with extensive libraries of functions and development tools specifically designed for data acquisition and instrument control LabVIEW uses its own graphical programming language G to create programs in a block diagram form 27 Each VI consists of three main parts the front panel the block diagram and the icon connector The front panel is the user interface and can be designed to simulate the instrument front panel The front panel can contain knobs push buttons graphs and other controls and indicators where information is entered and displayed The block diagram consists of executable source code that is created using nodes terminals and wires The VI receives instructions from the block diagram in the form of function blocks routines and control elements that constitute the VI code A VI within another VI is called a subVI The icon connector of a VI is a graphical parameter list so that other VIs can pass data to a subVI Figs 3 2 3 3 and 3 4 show the front 18 panel block diagram and icon connector windows respectively for the AWG initialization VI This VI initializes communication with the AWG by writ
19. normal 120 or 240 degrees between three phase voltages 10 Voltage and phase unbalance is caused by unequal loading of single phase loads on a three phase system Waveform Distortion Waveform distortion is a steady state deviation from an ideal sine wave Four primary types of waveform distortion are dc offset harmonics interharmonics and notching Voltage harmonic distortion is usually less than 20 while current harmonic distortion is usually less than 100 The main contribution to harmonic voltage and current distortion is due to nonlinear loads which draw a nonsinusoidal current Some of the effects of voltage and current harmonics are heating losses interference leading to misoperation of solid state devices and additional stresses on system capacitors Interharmonics are caused by equipment such as cycloconverters and arc furnaces Normally they do not cause significant problems but sometimes can lead to saturation of transformers resonances between transformers and capacitors and subsynchronous resonance in synchronous generators Voltage Fluctuations Voltage fluctuations are systematic variations of voltage or a series of random voltage changes of relatively small magnitude typically less than 0 lpu Voltage fluctuations are also referred to as flicker and noise Loads creating continuous rapid variations in the load current magnitude cause voltage fluctuations Power Frequency Variations Power frequency variations are
20. points With a set sampling rate of 128 points per cycle 225 cycles at 60Hz can be recorded to a data file The number of event capture data files is only limited by the laptop PC hard drive disk capacity 25 16 3 LABVIEW INSTRUMENT DRIVER FOR AWG 3 1 Introduction Initially all of the programming setup for the arbitrary waveform generator AWG was performed manually through the front panel interface Most of the functionality available through the front panel interface can be programmed remotely through the AWG s GPIB communication port National Instruments LabVIEW was chosen as the software interface for programming the AWG remotely LabVIEW has a descriptive front panel graphical user interface and is used as a standard data acquisition and control program for most instrumentation in the MSRF at OSU LabVIEW also has the capability for remote data acquisition and control over the internet enabling future coordination work with other research facilities and universities 3 2 LabVIEW Instrument Driver Objectives Three main goals existed in the development of a LabVIEW driver database for the AWG and programmable source First since the AWG has limited storage capabilities and has its internal memory cleared whenever reset the driver must provide a method for storing waveform equation and sequence profiles and transferring these profiles to and from the AWG as they are needed Second the driver must have the capability to creat
21. pulse pattern current in phase c non sagged phase is more unbalanced than for the 2 single phase voltage sag 5 2 2 3 100 Load The input current for a 5 single phase voltage sag on phase a during a 100 load condition is shown in Fig 5 10 This case is similar to the 2 single phase voltage sag during a 50 load condition The current drawn by the sagged phase is highly unbalanced and still has a double pulsed pattern The average dc bus voltage during the voltage sag 630V is still lower than the peak value of the sagged line to line voltage 636V i V would be here dropped out 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Figure 5 9 Input current 5 single phase sag 50 load 47 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Figure 5 10 Input current 5 single phase sag full load 5 2 3 10 Single Phase Voltage Sag For a 10 single phase voltage sag on phase a the corresponding input phase and line to line voltages are V 23920 IV 438V rms 619V peak V 2662240 V 460V rms 650V peak 5 3 V 2667120 Wal 438V rms 619V peak Table 5 3 Data from a 10 single phase sag Input Current in Sagged Phase N N Y O in N Description of Input Current in N A N A Single pulsed Sagged Phase 48 5 2 3 1 5096 Load For a 10 single phase voltage sag on phase a the input current drawn during a 50 load condition is shown
22. see Fig 5 26 voltage sags both at 50 of nominal voltage In all cases the voltage sag disturbance sequences were generated for 300 cycles or 5 seconds The ASD was also tested with a three phase transient waveform similar to a three phase capacitor switching transient operation see Fig 5 30 The switching transient had a frequency of 480Hz and was four cycles therefore 8 33ms in duration 5 3 1 1 9096 Single Phase Voltage Sag Table 5 7 shows the results of the 90 single phase voltage sag test This test and all tests was performed at no load 50 load and at full load For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Figs 5 17 5 18 and 5 19 respectively It can be seen that during the voltage sag the ripple voltage on the dc bus increases the motor load speed reduces slightly and the input current drawn by the non sagged phases increases Table 5 7 90 single phase voltage sag results L AppiedToqe N 0 10 20 Sped apm 180 1785 1769 58 382 00 v3 DH v2 A 0 00000 0 02000 0 04000 Figure 5 17 ASD input voltage 9096 single phase voltage sag 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Figure 5 18 ASD input current full load two phases shown Figure 5 19 ASD dc bus voltage full load 59 5 3 1 2 100 Single P
23. the light dotted line approximately 0 13pu shows the dc bus voltage when there is no dc bus capacitance When one or more phases of the input ac voltage drops below the dc bus voltage constituting a voltage sag one or more branches of the diode rectifier stops conducting and the dc bus is supplied by the dc bus capacitor during this time Since the dc bus capacitor has limited energy content it will not be able to supply the load for much longer than a few cycles o o amp 8 Ld DC bus voltage in pu e o e amp S e S e R 0 0 2 0 4 0 6 0 8 1 Time in cycles Figure 4 2 ASD dc bus voltage during normal operation It is a common misconception in industry that single phase voltage sags cause ASDs to trip offline due to a dc bus undervoltage condition Since single phase voltage sags are the most common type of power quality disturbance it is important to characterize ASD operation under this type of disturbance In this thesis it will be demonstrated through experimental testing that the dc bus voltage supplied by a three phase diode bridge rectifier does not fall below the undervoltage trip level for any magnitude of single phase voltage sag 29 The majority of voltage sags that result in electronic equipment malfunction are caused by either short circuit faults or the starting of large induction motors 2 9 30 There are three types of voltage sags that are most commonly seen by ASDs including balanced and unbala
24. to either of the two phases from which control power was derived would cause the ASD to trip offline for single phase sags greater than 63 and for two and three phase sags greater than 20 On the other hand even with a complete single phase outage applied to the line from which control power was not derived the ASD did not trip offline It was also shown that for a simple modification of feeding the internal power supply through a three phase transformer the ride through capability of the ASD was improved to withstand complete single phase outages two phase sags of 50 magnitude and three phase sages of 30 magnitude It was seen that the ride through capabilities of the two ASDs 5 5kVA and 11kVA with internal power supplied by the dc bus was more substantial than ride through capabilities of the 5 5kVA ASD with internal power supplied from the ac input The 5 5kVA and 11kVA ASDs were able to ride through complete single phase sags and two phase sags of 50 The two ASDs did trip offline due to an undervoltage fault for a 50 three phase voltage sag 5 5 AWG Equation to Waveform Test The equation to waveform test setup included a three phase 460V line to line Shp induction motor which was directly supplied by the programmable source Shown in Fig 5 31 is the output of the programmable source where the AWG was set up in the continuous mode with 10 total harmonic distortion on the voltage consisting of 5 and 7 harmonics This test was
25. 0 Seconds Figure E2 6 ASD dc bus voltage full load ASD tripped offline 116 400 00 W 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 200 00 0 e eo Vv 200 00 l Seconds Figure E2 7 ASD input voltage 65 single phase voltage sag phase a 000 i 0 00000 0 04000 0 08000 0 12000 0 16000 0 70000 Figure E2 8 ASD input current full load two phases shown ASD did not trip offline 559 00 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 Figure E2 9 ASD dc bus voltage full load ASD did not trip offline 117 200 00 v3 Don v2 Figure E2 10 ASD input voltage 100 single phase voltage sag on phase a 04000 0 08000 0 10000 Seconds 0 08000 0 10000 350 06 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Figure E2 12 ASD dc bus voltage full load ASD did not trip offline 118 Ju Seconds Figure E2 13 ASD input voltage 30 two phase voltage sag on phases a and b 0 00000 0 06000 0 12000 0 18000 0 24000 0 30000 Seconds Figure E2 14 ASD input current full load two phases shown ASD did not trip offline 450 00 i i i 450 00 0 00000 0 06000 0 12000 0 18000 0 24000 0 30000 Figure E2 15 ASD dc bus voltage full load ASD did not trip offline 119 200 41 v3 v2 200 41 MOM Seconds Figure E2 16 ASD input vol
26. 000 Seconds Figure E3 3 ASD dc bus voltage full load ASD did not trip offline 123 400 00 HARA 7400 00 v3 e ce v2 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure E3 4 ASD input voltage 5096 three phase voltage sag 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 7 Seconds Figure E3 5 400 00 400 006 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 Seconds Figure E3 6 ASD dc bus voltage full load ASD did not trip offline
27. 1 1 U LI LI U 1 1 H Source Torque Speed i 1 U U LI 1 U 1 Li 1 1 1 t 1 1 1 U L Lee ee e A 1 1 1 1 1 1 500 hp Test Bed 1 LI 1 1 LI 1 1 1 Transducer System Under Test 1 Test Loads ASDs motors etc Figure 2 1 Schematic of MSRF including the Power Quality Test Platform 12 A more detailed representation of the PQTP is shown in Fig 2 2 The main hardware and instrumentation comprising the PQTP includes the three phase programmable source with an integrated arbitrary waveform generator AWG a PC for remote control of the AWG and a three phase power analyzer with event capture data logging capabilities 2 2 Three Phase Programmable Source The 120kVA three phase programmable power source is a one of a kind unit made by Behlman Electronics Inc that enables a flexible variable amplitude and frequency output 23 The programmable source is composed of three solid state converters one per phase supplied from a multi tapped input transformer to provide a wide range of output capabilities Each power amplifier has an output range of 0 132Vac rms The output of the power amplifiers is stepped up through a transformer that enables a rated output voltage range of 0 305Vac rms line to neutral a current limit of 144A rms per phase and a frequency range of 45Hz to 2kHz Peak voltage capabilities are 0 460V instantaneous line to neutral and peak current capabilities are 2 9 tim
28. 1 ASD input current no load two phases shown E1 12 ASD dc bus voltage no load Figure E1 13 E1 14 E1 15 E2 1 E2 2 E2 3 E2 4 E2 5 E2 6 E2 7 E2 8 E2 9 E2 13 E2 14 E2 15 E2 16 E2 17 E2 18 E2 19 E2 20 E2 21 E2 22 E2 23 E2 24 E3 1 E3 2 E3 3 E3 4 LIST OF APPENDIX FIGURES Continued ASD input current full load two phases shown ASD did not trip offline ASD dc bus voltage full load ASD did not trip offline ASD input voltage 50 two phase voltage sag on phases b and c ASD input current full load two phases shown ASD did not trip offline ASD dc bus voltage full load ASD did not trip offline ASD input voltage 50 three phase voltage sag Figure Page E3 5 ASD input current full load two phases shown ASD did not trip offline 123 E3 6 ASD dc bus voltage full load ASD did not trip offline l 123 LIST OF APPENDIX FIGURES Continued LIST OF APPENDIX TABLES Table Page Al 1 AWG channel configuration 87 Bl AWG2005 Individual query function blocks 93 A REMOTELY CONTROLLED POWER QUALITY TEST PLATFORM FOR CHARACTERIZING THE RIDE THROUGH CAPABILITIES OF ADJUSTABLE SPEED DRIVES 1 INTRODUCTION 1 1 What is Power Quality Power quality has become an issue of increasing concern to both electric utilities and end users of electrical power since the 1970s The term power quality is applied to a wide range of electromagnetic ph
29. 5 Files in the above mentioned library path that do not begin with TKAWG2005 are instrument profile blocks that contain one or more individual function blocks as subsystems Table B1 AWG2005 Individual query function blocks Individual Query Function Block TKAWG2005 Query Clock vi TKAWG2005 Query Date Time vi TKAWG2005 Query Waveform Settings vi Table B2 AWG2005 Individual action function blocks Individual Action Function Block TKAWG2005 Close vi TKAWG2005 Comment File vi TKAWG2005 Compile Waveform File vi TKAWG2005 Copy File vi TKAWG2005 Define Equation File vi TKAWG2005 Delete File vi TKAWG2005 Download Equ or Seq File vi TKAWG2005 Download Wfm File vi TKAWG2005 Error Message vi TKAWG2005 Initialize vi TKAWG2005 Load Save File vi TKAWG2005 Lock Unlock File vi TKAWG2005 Make Hard Copy vi TKAWG2005 Rename File vi TKAWG2005 Reset vi TKAWG2005 Revision Query vi TKAWG2005 Seif Calibration vi TKAWG2005 Self Test vi TKAWG2005 Set Clock vi TKAWG2005 Set Date Time vi TKAWG2005 Set Debug vi TKAWG2005 Set Disk Drive vi TKAWG2005 Set Display vi TKAWG2005 Set Function Generator vi TKAWG2005 Set Mass Memory vi TKAWG2005 Set Output Channels vi TKAWG2005 Set Trigger Mode vi TKAWG2005 Set Trigger Settings vi TKAWG2005 Set Waveform Points vi TKAWG2005 Start Stop Trigger vi TKAWG2005 Upload Equ Seq File vi TKAWG2005 Upload Wfm File vi 94 95 APPENDIX C LABVIEW INSTRUMENT DRIV
30. 5 12 shows the results of the 100 single phase voltage sag test Again for the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E It can be seen that during the voltage sag the ripple voltage on the dc bus increases and the motor load speed reduces by about the same amount as the previous test The results are very similar to the previous 95 single phase voltage sag results as well as the 5 5kVA ASD 90 and 100 single phase voltage sag results 66 Table 5 12 100 single phase voltage sag results NoLoad Applied Torque Nm o 20 40 5 3 2 3 50 Two Phase Voltage Sag Table 5 13 shows the results of the 50 two phase voltage sag test For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E It can be seen that during the voltage sag the ripple voltage on the dc bus increases and the motor load speed decreases more so than in the 5 5kVA ASD 50 two phase voltage sag results Table 5 13 50 two phase voltage sag results 50 Load 100 Load Applied Torgue Nm 0 20 4 491V 465V 442V Drive Trip Y N 5 3 2 4 50 Three Phase Voltage Sag Table 5 14 shows the results of the 50 three phase voltage sag test For the test at no load the ASD did not trip offline For the 50 load and full load
31. 5 3 1 3 50 Two Phase Voltage Sag Table 5 9 shows the results of the 50 two phase voltage sag test For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Figs 5 23 5 24 and 5 25 respectively The increase in the ripple voltage on the dc bus and the decrease in motor load speed are more dramatic than for the single phase voltage sags The input current is unbalanced and more current is drawn by the non sagged phase 61 Table 5 9 50 two phase voltage sag results 50 Load 100 Load Applied Torque Nm 10 EE ee 20 Speed rpmy 179 177 172 m lala va gt 0 08000 0 10000 Figure 5 23 ASD input voltage 50 two phase voltage sag Figure 5 24 ASD input current full load two phases shown 62 p cored x 380 47 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 Figure 5 25 ASD dc bus voltage full load 5 3 1 4 5096 Three Phase Voltage Sag Table 5 10 shows the results of the 50 three phase voltage sag test For the test at no load the ASD did not trip offline For the 50 load and full load conditions the ASD did trip offline nearly immediately due to an undervoltage error The 50 load and full load tests were performed with and without the regenerate the kinetic energy from the machine inertia parameter set and in all cases the ASD immediately trip
32. 70 Figure E1 9 ASD dc bus voltage full load 111 d 1 Zoomed x gt 365 99 0 00000 0 16000 0 32000 0 48000 0 64000 0 80000 Figure E1 12 ASD dc bus voltage no load 112 113 emed 5 0 00000 0 01000 0 02000 0 03000 0 04000 0 05000 0 00000 0 01000 0 02000 0 03000 0 04000 0 05000 Seconds Figure E1 14 ASD input current full load two phases shown E ned Z 50 99 0 00000 0 01000 0 02000 0 03000 0 04000 0 05000 Seconds Figure E1 15 ASD dc bus voltage full load 114 S SkVA ASD Internal Power Supply Derived From Single Phase Input Transformer AN AAA 400 00 200 00 0 00 200 00 gt 0 00000 0 02000 0 10000 Seconds Figure E2 1 ASD input voltage 63 single phase voltage sag on phase a s 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure E2 2 ASD input current full load phases b and c shown 550 02 v ssc 69 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 5 Seconds Figure E2 3 ASD dc bus voltage full load 115 200 00 v3 v2 200 00 DU Figure E2 4 ASD input voltage 65 single phase voltage sag on phase c i 0 00000 0 06000 0 12000 0 18000 0 24000 0 30000 Seconds Figure E2 5 ASD input current full load phases b and c shown ASD tripped offline E1 550 00 0 00000 0 06000 0 12000 0 18000 0 24000 0 3000
33. AN ABSTRACT OF THE THESIS OF Evelyn Matheson for the degree of Master of Science in Electrical and Computer Engineering presented on June 8 2001 Title A Remotely Controlled Power Quality Test Platform for Characterizing the Ride Through Capabilities of Adjustable Speed Drives Redacted for privacy Abstract approved MOM Annette R von Jouanne With the increased attention on high efficiency and controllability of industrial processes as well as reduced weight volume and cost of consumer products the applications of nonlinear power electronic converters such as adjustable speed drives ASDs are showing a rapid rise Power Quality PQ is becoming an increasing concern with the growth of both sensitive and disturbing nonlinear loads in the residential commercial and industrial levels of the power system where PQ related disruptions can cause system malfunction product loss and hardware damage resulting in costly data loss and downtime Investigating and mitigating PQ issues pertaining to the input supply of ASDs and other sensitive power electronic equipment is extremely important in maintaining a high level of productivity In response to these concerns this research focuses on the development of a power quality test platform PQTP that has been implemented at Oregon State University OSU in the Motor Systems Resource Facility MSRF The central component of the PQTP is a 120kVA programmable ac power source with an integra
34. ER PROFILE BLOCKS 1 Query AWG Internal Memory List Files of Type Bytes Used Bytes Free error in no error E lumber of Files Catalog Information filename DC 10KT WFM file date file size Figure C1 1 Front panel window for Query Internal Memory profile block The Query Internal Memory profile block returns a catalog listing including the name date and size of all files stored in the internal memory of the AWG The type of file to be searched for specified in the List Files of Type parameter should be selected prior to running the VI profile block 2 Upload All Waveform Files From AWG to Computer error in no error Directory in Computer Upload Files of Type EiEveymyest BWAVEFORM JB Catalog Information filename DC_10KT WFM file date file size Filename Being Uploaded ber of Files Unloaded ie Figure C2 1 Front panel window for Upload All Waveform Files profile block 96 The Upload All Waveform Files profile block transfers all WFM files from the internal memory of the AWG into a specified directory in the computer The Directory in Computer and Upload Files of Type parameters should be specified before running the profile block 3 Upload Waveform File From AWG to Computer error in no error Filename in AWG Filename in ComputerfilC Evelyn TekAWG Figure C3 1 Front panel window for Upload Waveform File profile block The Upload Waveform File profile block transfers a singl
35. FM file is open in the Edit Menu the marker signal is shown at the bottom of the screen The marker can be set either HIGH 1 or LOW 0 at any of the waveform points Every WFM file used as a transient waveform including the transient trigger channel waveform should have the marker signal set HIGH 1 near the beginning of the waveform not at the first waveform point but within the first 50 waveform points and the marker signal set LOW 0 near the end of the waveform not at the last waveform point but within the last 50 waveform points The nominal waveforms used in 91 the transient operation should NOT have markers set The markers for these waveforms should always be LOW 0 Also the waveforms used in steady state operation should NOT have markers set The transient waveform for the trigger channel should again have the same number of waveform points as the phase channel waveforms and should maintain a constant dc level throughout Keep in mind the waveform amplitude of the phase channel transient waveforms during their creation During transient waveform operation the amplitude parameters for the AWG channels cannot be changed The sequence feature of the AWG can only step through waveforms it cannot vary the output amplitude multiplier or the clock frequency In most cases the output amplitude of the AWG channels will be maximized at 10 0V peak The magnitude of the transient waveforms should be scaled such that the desired AWG
36. Quality Control Techniques Van Nostrand Reinhold 1993 Jih Sheng Lai and Thomas S Key Effectiveness of Harmonic Mitigation Equipment for Commercial Office Buildings IEEE Transactions on Industry Applications vol 33 no 4 pp 1104 1110 July August 1997 Mark McGranaghan Questions and Answers for Applying IEEE 519 1992 Part 1 Power Quality Assurance vol 9 no 5 pp 50 58 May June 1998 Ned Mohan Tore M Undeland and William P Robbins Power Electronics Converters Applications and Design John Wiley amp Sons Inc 2nd edition 1995 20 21 22 23 24 25 26 27 28 83 Annette von Jouanne and Alan Wallace A Short Course on Adjustable Speed Drives and Utility Applications Issues for Eugene Water and Electric Board March 2001 Mark McGranaghan Applying IEEE 519 Part 2 Controlling Harmonic Distortion Levels Power Quality Assurance vol 9 no 6 pp 55 61 July August 1998 John A Houdek Reactors Maximize Drive System Reliability Power Quality Assurance vol 11 no 2 pp 22 28 February 2000 Robert Arthur Harmonic Canceling Transformers Part 1 Industrial Applications Power Quality Assurance vol 10 no 8 pp 44 50 November 1999 Robert Arthur Harmonic Canceling Transformers Part 2 Commercial Applications Power Quality Assurance vol 10 no 9 pp 46 51 December 1999 Mark McGranaghan Sizing Active Filters for
37. Sagged Phase Description of Input Current in N A Single pulsed Sagged Phase 50 5 2 4 1 5096 Load For a 13 single phase voltage sag on phase a the input current drawn during a 50 load condition is shown in Fig 5 13 Again the input current on the sagged phase has completely dropped out and only two of the six line to line voltage pulses are conducting current meaning the three phase rectifier is operating as a single phase rectifier The average dc bus voltage during the voltage sag 635 8V is higher than the peak sagged line to line voltage 609V 5 2 4 2 10096 Load The input current for a 13 single phase voltage sag on phase a during a 100 load condition is shown in Fig 5 14 This case is similar to the 1096 single phase voltage sag during a full load condition The current drawn by the sagged phase still has a single pulsed pattern with now a lower magnitude Even though the average dc bus voltage during the voltage sag 622 4V is higher than the peak value of the sagged line to line voltage 609V the ripple of the dc bus capacitor still causes the instantaneous dc bus voltage to drop below the sag affected line to line input voltage This is considered the boundary between operating with a sagged phase current in a single pulsed pattern or with the sagged phase current completely dropped out 0 000 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 T Seconds Figure 5 13 Input current
38. ad 60 5 23 ASD input voltage 50 two phase voltagesag LLL 61 5 24 ASD input current full load two phases shown 61 5 25 ASD dc bus voltage full load 62 5 26 ASD input voltage 50 three phase voltage sag 63 5 27 ASD input current no load two phases shown 63 5 28 ASD dc bus voltage no lond 63 5 29 AWG test setup three phase 480Hz capacitor switching transient 64 5 30 Output of programmable source three phase 480Hz capacitor switching transient 64 LIST OF TABLES Table Page 2 1 Measurement display formats for PQ power analyzer 13 3 1 AWG data transfer driver profile blocks 22 3 2 AWG file creation driver profile blocks LLL 23 3 3 AWG setup and operation driver profile blocks 23 5 1 Data from a 2 single phase sag 39 5 2 Data from a 5 single phase sag LLL 45 5 3 Data from a 10 single phase sag LLL 47 5 4 Data from a 13 single phasesag LLL 49 5 5 Data from a l7 6single phasesag LLL 51 5 6 Summary of single phase sag testing LLL 54 5 7 90 single phase voltage sag results 57 5 8 100 single phase voltage sag results occ LLL 59 5 9 50 two phase voltage sag results Lu 61 5 10 50 three phase voltage sag results 62 5 11 95 single phase voltage sag results 65 5 12 100 single phase voltage sag results 66 5 13 50 two phase voltage sag results 66 5 14 50 three phase voltage sag results 67 5 15 63 single phase voltage sag phase a regular configuration 69
39. and ride through characterization The experimental results have in some cases reinforced known operational behaviors of ASDs while also exposing new trends due to the PQ voltage disturbances tested Most of the PQ voltage disturbances generated and applied to the ASDs were single two and three phase voltage sags since these are the most prevalent voltage disturbances experienced by commercial and industrial customers The ASD diode bridge rectifier operation analysis involved supplying the ASD with relatively small magnitude lt 20 single phase voltage sags to observe the transition between operation as a three phase rectifier and as a single phase rectifier It was found that the input three phase rectifier does not immediately change to operation as a single phase rectifier during a single phase voltage sag Instead for increasing single phase voltage sag magnitudes the normal three phase balanced double pulse phase current waveform on the sagged phase changes to an unbalanced double pulsed waveform then to a single pulsed waveform and finally drops out completely When the current in the sagged phase does drop out completely the three phase rectifier operates as a single phase rectifier and the dc bus falls to the same level for any greater magnitude single phase sag including a complete single phase outage From the experimental results it was determined that the sag magnitude at which the three phase rectifier converts to operations as a
40. are shown in Table 5 19 For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E As expected for this magnitude of voltage sag the drop in speed and dc bus voltage is not as great as for the 30 two phase voltage sag on phases a and b Again it is shown that the ability of the ASD to ride through two phase voltage sags is limited by requirements for the internal power supply voltage Table 5 19 20 two phase voltage sag phases b and c regular configuration Applied Torque Nm 0 10 lag S6 Reduction 5 3 3 3 Three Phase Voltage Sag Regular Configuration The test results for a 2096 three phase voltage sag supplying the ASD are shown in Table 5 20 This is the largest magnitude three phase sag that the ASD can ride through since as was shown in the previous section phases b and c of the ASD cannot ride through a sag greater than 20 of nominal voltage For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E As expected for this magnitude of voltage sag the drop in speed and dc bus voltage is greater than 72 for any of the two phase voltage sags tested in the previous section Under the full load condition the average dc bus voltage falls to 80 of its nominal value
41. armonics and enable regenerative braking Disadvantages of a controlled rectifier are increased cost due to more expensive hardware and additional control logic and the ASD would need to be derated to ride through extended sags 4 5 4 Internal Power Supplied From the DC Bus Voltage The ride through capability of an ASD can be significantly improved by specifying that the internal power be supplied from the dc bus voltage As will be shown in Chapter 5 this configuration will enable ASDs to ride through single phase voltage sags of any magnitude and duration This ride through alternative is fairly simple and inexpensive when compared with the previously mentioned ride through solutions since no additional hardware or control logic is required The cost of an ASD with the internal power supplied from the dc bus voltage may be slightly higher than the cost of an ASD with the internal power supplied form two of the three input phases since a dc dc converter power supply must be implemented instead of a more simple linear power supply 38 5 EXPERIMENTAL RESULTS 5 1 PQTP Experimental Test Plan The ability of the programmable source and integrated AWG to simulate PQ disturbances such as voltage fluctuations which is useful in characterizing ASD operation was demonstrated with a series of tests The first series of tests involved applying single phase voltage sags of a relatively small magnitude lt 20 to an ASD under different load con
42. as five measurement display and data logging formats Table 2 1 gives a short description of the different measurement formats 25 Table 2 1 Measurement display formats for PQ power analyzer Phasor Diagram Single cycle measurement with real time display update of all fundamental and rms Detailed Harmonics quantities good for quick viewing Spectrum Analyzer Cycle by Cycle Capture The event capture mode of the PQ power analyzer is very useful for capturing power quality Captures 10 cycles of waveform data and then performs a harmonic decomposition of the data for all signals Performs spectral decomposition on a single waveform captured from a selected input channel Cycle by cycle measurement and data logging of all fundamental and rms quantities enabling detailed trending of all quantities Continuously monitors all channels and captures sub cycle events while continuously logging information disturbances simulated with the PQTP In this mode the PQ power analyzer saves data when triggered according to pre selected setpoints The event capture mode of the PQ power analyzer 15 2 6 PQTP Operation The programmable source can be operated with or without the AWG controlling the output voltage Without the AWG programming the source output the balanced sinusoidal three phase voltage magnitude and frequency can be manually adjusted The output is applied to the te
43. ation The test results for a 63 single phase voltage sag on phase a supplying the ASD are shown in Table 5 15 For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E The two phase currents shown in the input current figure and all subsequent input current figures are phases b and c the two phases that supply the internal power supply through the single phase transformer Similar to the ASDs tested with an internal power supply from the dc bus both the input current in the non sagged phases and the dc bus ripple increase A 63 single phase voltage sag on phases b and c produces the same results as for the sag on phase a 69 Table 5 15 63 single phase voltage sag phase a regular configuration Applied Torque Nm 0 10 20 621 3V Drive Trip Y N The test results for a 65 single phase voltage sag on phase a supplying the ASD are shown in Table 5 16 For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E The resulting drop in dc bus voltage and motor speed are the same as for the 63 single phase voltage sag However a 65 single phase voltage sag on phases b or c causes the ASD to trip offline under all load conditions due to a cont
44. ause different unbalance conditions seen at ASDs based on the type of load connection and the type of possible transformer connections present between the fault and the ASD In a single phase fault one phase voltage drops and the other two voltages remain unchanged and can be described by 35 36 F y a Ss V pA A A8 pu 4 8 V Mo jN3 Fig 4 5 shows the dc bus voltage of an ASD for varying dc bus capacitance sizes during a typical voltage sag caused by a single phase fault 2 Similar to Fig 4 2 the solid line shows the dc bus voltage for a large dc bus capacitance The dashed line shows the dc bus voltage for a small dc bus capacitance and the light dotted line shows the dc bus voltage with no dc bus capacitance DC bus voltage 0 0 5 1 1 5 2 2 5 3 Time in cycles Figure 4 5 ASD dc bus voltage during a single phase fault In a phase to phase fault two phase voltages move towards each other and the third phase voltage remains unchanged and can be described by 35 36 V a 1 pe e V jV N3 pu 4 9 V Vo jV N3 33 Fig 4 6 shows the dc bus voltage of an ASD for varying dc bus capacitance sizes during a typical voltage sag caused by a phase to phase fault 2 Again similar to Figs 4 2 and 4 5 the solid line shows the dc bus voltage for a large dc bus capacitance The dashed line shows the dc bus voltage for a small dc bus capacitance and the light dotted line shows the dc bus voltag
45. capacitors 9 15 Another method is to purchase equipment with reduced harmonic generation This is usually an initial option that is difficult and costly to implement with pre existing equipment An example of this is the application of line reactors inductive chokes in series with the ac input of nonlinear loads such as adjustable speed drives ASDs 9 16 Adding a line reactor in series with the ASD will reduce current harmonics and provide transient protection benefits However a slight voltage drop is then seen at the input of the ASD rectifier Sometimes a reactor is added to the dc link of an ASD which then eliminates the ac voltage drop but does not provide as much overvoltage transient protection Other examples of equipment with reduced harmonic generation are ASDs with higher pulse numbers A six pulse ASD generates predominantly fifth and seventh harmonics Whereas a twelve pulse ASD generates predominantly eleventh and thirteenth harmonics and the magnitudes of these harmonics are much lower 9 Applying technologies that cancel harmonics from different loads is another method for eliminating harmonics This is commonly achieved with standard transformer connections 17 18 Transformers can reduce harmonics in two ways through harmonic attenuation and by harmonic cancellation Transformers have a reactive impedance which increases directly with frequency naturally attenuating harmonics Harmonic cancellation occurs when two or
46. d the most important concern affecting most industrial and commercial customers 21 The most common voltage sags are caused by single line to ground faults These types of faults are caused by weather conditions tree branches animal contact insulation failures automobile accidents or other human activity A few customers near a fault may see a deep voltage sag followed by a complete interruption when utility circuit breakers clear the fault Most other customers connected through the same distribution or transmission system will see a smaller voltage sag with the magnitude based on the customer s distance to the fault location as well as intervening transformer connections that further isolate customers from the fault 2 21 Once the fault has been cleared or isolated the system will return to nominal voltage The IEEE has developed a recommended standard that helps industrial power electronic equipment users evaluate the impact of voltage sags at their facility IEEE 1346 1998 This standard describes a method for combining predictions of voltage sag magnitude duration and 27 rate of occurrence with a characterization of equipment susceptibility to voltage sag events to determine the cost of voltage sag related downtime The cost of incorporating either power conditioning equipment or new process equipment with greater voltage sag tolerance can also be compared with voltage sag related downtime costs 21 Circumstances that ca
47. d in kV and the time has units of milliseconds ms For a given capacitance connected to the dc bus of an ASD typically between 75 and 360 uF kW 4 6 can be used to approximate the maximum voltage sag ride through time for a given voltage sag magnitude Figure 4 4 shows the voltage tolerance curve of ASDs for different capacitance sizes It can been seen that even for relatively small balanced three phase voltage sags the ASD will trip offline due to a low dc bus voltage within a few cycles Figure 4 4 Voltage tolerance curve for ASDs based on dc bus capacitances of 754F kW solid line 1654F kW dashed dotted line 360uF kW dotted line and 670F kW dashed line One way to improve the voltage tolerance curve of an ASD is to lower the undervoltage trip setting parameter Some ASD manufacturers do not allow this parameter to be changed for smaller ASDs e g lt 25kVA Also the undervoltage trip parameter should be set to protect against malfunction of the load process or damage to the ASD components especially due to high currents Another way to improve the ASD voltage tolerance curve is to increase the amount of dc bus capacitance The amount of capacitance needed to obtain a voltage tolerance with a specific Vmin and tmar is given by 2 30 2Pt ax 0 min 32 4 3 2 Unbalanced Voltage Sags Single Phase and Phase to Phase Faults Single phase and phase to phase faults resulting in unbalanced three phase voltage sags c
48. ditions and analyzing the input three phase diode bridge operation A second set of tests involved characterizing the ride through capabilities of ASDs by simulating single two and three phase voltage sags as well as transient disturbances and applying these PQ disturbances to an ASD driving a motor load These tests involved two sizes and configurations of ASDs A third test involved demonstrating the flexible equation to waveform programming ability of the AWG by generating a voltage harmonic distortion condition and applying the waveforms to a line operated motor load 5 2 Single Phase Voltage Sag Affects on ASD Diode Bridge Rectifier Operation The experimental tests were performed on a 5 5kVA ASD with a conventional six pulse diode bridge rectifier supplying the dc bus The nominal input line to line voltage was 460V rms and the nominal corresponding input phase voltage was 266V rms Several magnitudes of single phase voltage sags were generated including a 2 sag 261V rms 5 sag 253V rms 10 sag 239V rms 13 sag 231V rms and 17 sag 221V rms These sag magnitudes were chosen because they demonstrated input current transition operating conditions For each single phase sag magnitude a test was performed at no load 5096 load and full load For each test the dc bus voltage was recorded before the sag and during the sag Three phase diode bridge rectifier operation is altered in three different patterns when relatively low magn
49. dre Ramme Abdurrahman Unsal and Marcel Merk And finally I would like to thank my family Mom Dad Don and Karen for their ongoing encouragement and especially my fianc e Russell for his support 1 TABLE OF CONTENTS Page INTRODUCTION lt sats cutee tele esa tt eal et Leere eee A i See 1 1 1 What is Power Quality 1 1 2 Harmonic Distortion 4 1 3 Harmonic Distortion Mitigation Techniques LLL 7 1 4 Research Project tat rant a cA e tle A oe 8 1 5 Organization of Thesis 10 POWER QUALITY TEST PLATFORM LLL 11 2 1 Equipment Set p 4 4 eon A A een ies Lo sucha Tex 11 2 2 Three Phase Programmable Source 12 2 3 Three Phase PQ Power Analyzer LLL 13 24 AWG Op mlO see enen eran e it ere ae t e E T ac 14 2 5 LabVIEW Instrument Driver 14 2 0 PTP Operation 6 ToT cR Ld ATE net cree cec ot nre Rey ae 15 LABVIEW INSTRUMENT DRIVER FOR AWG s 16 Sob IntroductioB teren ene cte a pt ra asco Petr TE ita 16 3 2 LabVIEW Instrument Driver Objectives ss 16 3 3 Pre Existing Instrument Driver 16 3 4 LabVIEW Virtual Instrument Overview 17 3 5 LabVIEW Profile Block Virtual Instruments n 20 3 6 New Instrument Driver for AWG 21 3 7 Limitations in AWG Programming Functions 24 3 8 Programmable Source Range of Operation Limits for AWG 24 TABLE OF CONTENTS Continued 4 ADJUSTABLE SPEED DRIVE PROPERTIES 4 5 1 Energy Storage Methods 4 5 2 Functional Operation Modes of ASDs 4 5 3 ASD Topology Modif
50. e lightning strikes and capacitor switching operations Short Duration Variations A short duration variation is either a temporary voltage drop sag dip voltage rise swell or complete loss of voltage interruption An interruption occurs when the supply voltage or load current decreases to less than 0 1pu for less than one minute A sag is a decrease in rms voltage or current at the nominal frequency to between 0 1 and 0 9pu Conversely a swell is an increase in rms voltage or current at the nominal frequency to between 1 1 and 1 8pu Voltage sags and swells typically last anywhere from under a cycle up to a couple of minutes Short duration variations are typically caused by system fault conditions short circuits circuit breaker reclosure operations overloads the energizing of large loads that require high starting currents or intermittent loose connections in power wiring Long Duration Variations A long duration variation is a sustained overvoltage undervoltage brownout or interruption lasting longer than two minutes Long duration variations are caused by load variations on the system system switching operations and voltage regulation equipment such as tap settings on transformers Voltage and Phase Unbalance Voltage unbalance is the maximum deviation from the average of the three phase line to line voltage divided by the average of the three phase line to line voltage Phase angle unbalance is the deviation from the
51. e with no dc bus capacitance DC bus voltage 0 0 5 1 1 5 2 2 5 3 Time in cycles Figure 4 6 ASD dc bus voltage during a phase to phase fault 4 4 Motor Deceleration In some circumstances ASDs can ride through voltage sags In such a case the drop in system voltage at the ac input of the ASD usually causes a drop in the voltage at the motor load terminals A voltage sag at the motor terminals causes a drop in torque and thus a drop in speed It is possible to estimate the drop in motor speed for balanced and unbalanced voltage sags based on a simplified motor model where the electrical torque is proportional to the square of the voltage and the mechanical torque is constant It is assumed that for a balanced voltage sag all three phase voltages at the motor terminals drop by the same amount Following a derivation given in 2 the increase in motor slip As due to a voltage sag of magnitude V in per unit and duration Af can be given by ds 1 py As At At 4 10 at 2H In 4 10 H is the inertia constant of the motor load combination and is expressed as the ratio of the kinetic energy and the mechanical output power 34 pu 4 11 It can be seen that the voltage tolerance of an ASD can be improved by adding inertia to the load If the maximum acceptable slip increase is equal to Asma then the minimum acceptable three phase sag magnitude Vmin for a given duration T can be expressed by Vin Em
52. e WFM file from the internal memory of the AWG into a specified directory in the computer The Filename in AWG Filename in Computer and Source parameters should be specified prior to running the profile block VI The Source parameter indicates where the file to be uploaded is located Available options are the internal memory and channels 1 through 4 4 Upload All Sequence Equation Files From AWG to Computer error in no error Directory in Computer Upload Files of Type ed File Type Catalog Information H equation sequence filename DC 30 SEQ file date file size Br BI IC Evelyn test PHC_10K SEQ Filename Being Uploaded lumber of Files Uploaded Figure C4 1 Front panel window for Upload All Sequence Equation Files profile block 97 The Upload All Sequence Equation Files profile block transfers either all SEQ or all EQU files from the internal memory of the AWG into a specified directory in the computer The Filename in Computer Upload Files of Type and File Type parameters should be specified prior to running the profile block VI 5 Upload Sequence Equation File From AWG to Computer error in no error Filename in AWG FPHA_10K2 SEQ File Type FT code H equation eo sequence Filename in Computera C Evelyn TekAWG PHA_10K2 SEQ Figure C5 1 Front panel window for Upload Sequence Equation File profile block The Upload Sequence Equation File profile block transfers either a SEQ or a EQU
53. e Balanced and Unbalanced Sags IEEE Transactions on Industry Applications vol 36 no 3 pp 904 910 May June 2000 Rick Langley and Arshad Mansoor What Causes ASDs to Trip During Voltage Sags Part 1 Power Quality Assurance vol 10 no 6 pp 12 15 September 1999 Rick Langley and Arshad Mansoor What Causes ASDs to Trip During Voltage Sags Part 2 Power Quality Assurance vol 10 no 7 pp 44 50 October 1999 Rick Langley and Arshad Mansoor What Causes ASDs to Trip During Voltage Sags Part 3 Power Quality Assurance vol 10 no 8 pp 36 39 November 1999 Rick Langley and Arshad Mansoor What Causes ASDs to Trip During Voltage Sags Part 4 Power Quality Assurance vol 10 no 9 pp 32 35 December 1999 L D Zhang and Math H J Bollen A Method for Characterizing Unbalanced Voltage Sags with Symmetrical Components JEEE Power Engineering Review vol 18 no 7 pp 50 52 July 1998 Math H J Bollen Characterisation of Voltage Sags Experienced by Three Phase Adjustable Speed Drives IEEE Transactions on Power Delivery vol 12 no 4 pp 1666 1671 October 1997 Rick Langley Arshad Mansoor Tom Geist and Ben Banerjee Advanced Electrochemical Capacitors for ASD Ride Through Power Quality Assurance vol 11 no 2 pp 46 50 February 2000 Toshiba International Corporation Toshiba G3 TOSVERT 130 Transistor Inverter Operation Manual September 1996
54. e and modify the several types of waveform equation and sequence files that are necessary to produce simulated voltage disturbance conditions from the programmable source And third the driver must be able to perform the control functions necessary to load configure execute and trigger simulated voltage disturbance conditions 3 3 Pre Existing Instrument Driver A LabVIEW basic function driver database has been developed by National Instruments for a similar Tektronix AWG model AWG2041 LabVIEW driver databases consist of virtual instruments VIs each of which executes a specific function 27 The VIs for a particular device are grouped together in a library that is located within the LabVIEW instrument library folder instr lib The AWG2041 instrument driver library consists of approximately fifty VIs which are separated into five different categories One category initializes and closes communication with the AWG The other four categories include system configuration action 17 and status data collection and transmission and utility functions Fig 3 1 shows a tree containing all of the VIs in the AWG2041 instrument driver library To begin creating a LabVIEW driver database for the AWG2005 each of the VIs from the AWG2041 database was modified and reconfigured for the AWG2005 One difference between the two AWG models is that the AWG2005 has four output channels compared to the AWG2041 which has two output channels Therefore
55. e error occurred If an error occurs subsequent VIs will not execute and the error cluster will be passed on Progressing from left to right the Initialize VI is executed first followed by the Define Equation VI the Set Waveform Points VI the Compile Equation VI and finally ended with the Close VI To insert a subVI into a new profile block VI open the Instrument Drivers window in the Function menu All instrument driver folders located in the following path will be displayed C Program Files National Instrument LabVIEW Instr lib Choose the Tek2005 driver which will open up a window listing icons for all of the individual function block VIs and profile block VIs in the AWG2005 driver database Selected the desired Vl and drag the icon into the new block diagram window The second common profile block structure consists of multiple command strings concatenated together in series and written to the AWG as shown in Fig D2 2 This program diagram window example is from the Load Channel Phase A VI In this VI the Initialize VI is followed by multiple command strings which are grouped together in a particular order with input data from the front panel The concatenated command string is then sent to the AWG through the VISA write function block The Make Hard Copy and Close VIs follow the VISA write function 107 block Another commonly used VISA command is the VISA read function block which is used in several of the information query VIs i
56. e estimated to cost the company 1 million per minute due to lost production Overall EPRI estimates that lost productivity and downtime ranging from system malfunction product loss and hardware damage to costly data loss due to power outages costs the United States 50 billion annually 7 In an effort to better understand the link between power reliability and economic productivity and to demonstrate technological solutions to current problems that threaten this linkage EPRI began operation of the Consortium for Electric Infrastructure to Support a Digital Society CEIDS in January 2001 CEIDS membership includes utilities equipment manufacturers and representatives of industrial groups that are particularly sensitive to power quality A main task of CEIDS will be to determine which combination of technologies is likely to be most cost effective in optimizing power quality 5 Power quality disturbances can be described according to the following categories 1 2 8 9 Transients A transient is a power system variation that is undesirable but momentary in nature A transient is characterized by a sudden change in the steady state condition of voltage current or both that follows an impulsive or oscillatory behavior Transients can last anywhere from just a few nanoseconds up to 30 cycles in duration oscillate in a frequency range from a few kHz up to a few MHz and peak in magnitudes of up to 5 per unit pu Typical causes of transients ar
57. e ride through capabilities of industrial processes The PQTP also enables a controlled environment where tests can be performed In addition to research benefits the PQTP is also used as a practical educational tool enabling hands on demonstrations for undergraduate and graduate level classes as well as for industry and utility short courses offered in the MSRF The LabVIEW instrument driver library created for the AWG enables the programming and operation functionality of the AWG to be controlled remotely With National Instruments GPIB internet technology it is feasible for a large portion of the PQTP to be configured monitored and even controlled from remote locations outside of the MSRF This capability enables the possibility of future collaborative research with other universities 6 2 Summary of Experimental Results A LabVIEW instrument driver has been developed that enables remote creation and storage of PQ voltage disturbance files as well as setup and operation of the AWG output to the programmable source The LabVIEW instrument driver library consists of individual function virtual instrument VI blocks and combined subsystem profile block VIs As new PQ voltage disturbance tests evolve additional profile block VIs can be easily created from existing VI subsystems 79 The ability of the programmable source to simulate power quality voltage disturbances has been demonstrated with ASD diode bridge rectifier operation analysis
58. ency and channel amplitudes of the AWG while the output of the programmable source is ON This has not been tested Refer to supplied Behlman literature on AWG programming or contact Jaye Killian at Behlman Electronics for more information 5 Transient Waveform Operation The generation of transient waveform conditions with the AWG is somewhat complicated In a transient operation scenario a set of nominal waveforms is continuously output until a trigger signal is sent to the AWG also can be manually triggered from the AWG front panel When a trigger signal is executed the AWG switches from the set of nominal waveforms and outputs a set of transient waveforms and then automatically returns to the steady state waveform set output at the end of the transient waveform cycle s For an entire transient waveform operation a set of eight waveforms must be generated six waveforms for the three output phases and two waveforms for the trigger channel For each of the four channels a nominal waveform and a transient waveform must be generated Instead of loading WFM files into the four AWG channels as was done for steady state operation SEQ files will be loaded into the four AWG channels Each SEQ file will consist of a nominal case waveform the first waveform in the SEQ file and one or more transient waveforms to be executed in sequence when the trigger signal is executed EVERY transient case waveform must include MARKERS When a waveform W
59. enomena that cause voltage and current non idealities to occur on a power system 1 A description of a power quality problem is defined in 1 as A power quality problem is any power problem manifested in voltage current or frequency deviations that results in failure or misoperation of customer equipment A definition of power quality is also given by the IEEE Recommended Practice for Powering and Grounding of Sensitive Electronic Equipment IEEE Standard 1100 1992 as Power quality is the concept of powering and grounding sensitive equipment in a manner that is suitable to the operation of that equipment 2 There are several reasons for the heightened interest in power quality issues both by utilities and consumers The use of electronic and power electronic equipment has proliferated in both industrial and commercial applications In addition to becoming more widely used this equipment is increasingly sensitive to voltage disturbances leading to loss of production time and thereby a reduction in company profit margins Power electronic equipment also causes voltage and current disturbances for other customers and equipment In particular an increased use of converter type nonlinear load equipment ranging from computer power supplies to adjustable speed drives has increased the level of current and voltage distortion seen on the power system 2 4 Interest in power quality is also more important under the deregulation of the electric utility
60. es the rms rating 23 24 A Sony Tektronix model AWG2005 arbitrary waveform generator AWG has been custom integrated with the programmable source The AWG has four output channels three of which are used to represent the desired three output power phases while the fourth channel is used as a trigger source The AWG channels have an output range from 0 10V that are amplified and correspond to a 0 326Vac rms line to neutral 0 564V rms line to line output range of the programmable source 24 PC with LabVIEW instrument driver GPIB interface 120kVA Programmable Source Test Loads ASDs motors etc Figure 2 2 Block diagram of the Power Quality Test Platform PQTP JOtech ESA three phase power analyzer 2 3 Three Phase PQ Power Analyzer The PQTP includes a three phase power analyzer model PowerVista 312 by IOtech Inc The power analyzer consists of a data acquisition box laptop PC and EasyPower Measure Windows software developed by ESA Inc The power analyzer monitors and captures voltage and current information and can calculate and display all relevant quantities V I kW kVAR kVA pf THD etc in a waveform phasor or Fourier analysis format The power analyzer has four differential voltage channels as well as four external shunt current channels enabling three phase power measurements as well as two additional parameter measurements at important test points The EasyPower Measure software h
61. file from the internal memory of the AWG into a specified directory in the computer The Filename in Computer Filename in AWG and File Type parameters should be specified prior to running the profile block VI 6 Download Waveform File From Computer to AWG error in no error ile to Download 3 C Evelyn TekAWG PHA NOM WFM Figure C6 1 Front panel window for Download Waveform File profile block 98 The Download Waveform File profile block transfers a WFM file from a specified directory in the computer into the internal memory of the AWG The File to Download and Filename in AWG parameters should be specified prior to running the profile block VI 7 Download Sequence Equation File From Computer to AWG error in no error File Type equation sequence ile to Download 3 C Evelyn TekAWG DC_30 SEQ Figure C7 1 Front panel window for Download Sequence Equation File profile block The Download Sequence Equation File profile block transfers either a SEQ or a EQU file from a specified directory in the computer into the internal memory of the AWG The File to Download Filename in AWG and File Type parameters should be specified prior to running the profile block VI 8 Define and Compile an Equation File error in no error Equation File FTESTEQU Cd Byte Count Number of Characters Figure C8 1 Front panel window for Define Compile Equation profile block 99 The Define Compile Equation profile bl
62. gram the source output The AWG picture capture VI is also included as a subsystem VI in the Set Channel Output profile block 14 Start Stop AWG Trigger error out error in no error status source i Figure C14 1 Front panel window for Execute Trigger profile block The Execute Trigger profile block executes the AWG trigger function The trigger function is used in Waveform Advance Mode when simulating a power quality transient disturbance When the trigger is started the AWG output switches from the continuously output nominal waveform to the sequence of transient waveforms After the transient waveforms have been executed the output of the AWG returns to the continuous output of the nominal waveform 105 APPENDIX D PROCEDURE TO CREATE NEW INSTRUMENT DRIVER PROFILE BLOCKS 1 Standard Profile Block Subsystems All instrument driver profile blocks should contain a few standard subsystem components These standard subsystems include the Initialize VI and the Close VI If the profile block to be created involves some configuration or setup of the AWG the Make Hard Copy VI is useful if inserted at the end of the VI since it captures the AWG display screen and can be imported into the LabVIEW front panel window Figs D1 1 and D1 2 show the front panel window and block diagram window of a blank template VI which just includes the standard subsystems for a profile block Figure D1 2 Block diagram window of standard subs
63. hase Voltage Sag Table 5 8 shows the results of the 100 single phase voltage sag test These test results are extremely similar to the results of the 90 single phase voltage sag test This is because for any single phase voltage sag greater than 17 the three phase diode bridge rectifier operates as a single phase rectifier for any load condition Again for the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Figs 5 20 5 21 and 5 22 respectively It can be seen that the increased dc bus voltage ripple slight drop in motor speed and increase in input current are all the same as for the 90 single phase voltage sag test Table 5 8 100 single phase voltage sag results 50 Load 100 Load Applied Torque Nm 09 EG CEE BORE 1 Speed rpm 1799 1788 1773 DC Bus Voltage 647V 643V 640V Speed during sag Reduction 1799 0 0 1787 0 06 1769 0 23 DC Bus Voltage during sag 645V 633V 610V n WA 0 08000 0 10000 386 60 380 00 v2 Seconds Figure 5 20 ASD input voltage 100 single phase voltage sag 60 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 7 Seconds Figure 5 21 ASD input current full load two phases shown ec x 590 00 i ac cg 0 00000 0 02398 0 04797 0 07195 0 09594 0 11992 Figure 5 22 ASD dc bus voltage full load
64. ications 4 5 4 Internal Power Supplied From the DC Bus Voltage 5 2 1 2 Single Phase Voltage Sag 5 2 2 5 Single Phase Voltage Sag 5 2 3 10 Single Phase Voltage Sag 5 2 4 13 Single Phase Voltage Sag 5 2 5 17 Single Phase Voltage Sag 5 2 6 Summary of Results 5 2 7 Diode Rectifier Stresses Due to Single Phase Voltage Sags 5 3 1 5 5kVA ASD Internal Power Supply from DC Bus 5 32 11kVA ASD Internal Power Supply from DC Bus 5 3 3 5 5kVA ASD Internal Power Supply from AC Input LIST OF FIGURES Figure Page 1 1 Power system showing location of the PCC where other customers can be supplied 5 2 1 Schematic of MSRF including the Power Quality Test Platform 11 2 2 Block diagram of the Power Quality Test Platform PQTP s 12 3 1 Tree of AWG2041 instrument driver VIs Ls 17 3 2 Front panel window for initialization VI Ln 18 3 3 Block diagram window for initialization VI LLL LLL 18 3 4 Icon connector for initialization VI 18 3 5 Front panel window for AWG screen capture VI 19 3 6 Program diagram window for AWG screen capture VI 20 3 7 Front panel window for Load All Channels profile block k 21 3 8 Program diagram window for Load All Channels profile block ecco cence 21 4 1 Topology of an ac adjustable speed drive 25 4 2 ASD dc bus voltage during normal operation sss 28 4 3 One line diagram of a three phase short circuit fault 29 4 4 Voltage tolerance curve for ASDs based on various dc bus capacitances a 31 4 5 ASD dc bus v
65. ide through capability of the ASD and prevented it from tripping offline due to a control power low error for the three load conditions For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E The drop in speed and dc bus voltage is greater than for any of the two or three phase voltage sags tested in the previous sections Under the full load condition the average dc bus voltage falls to 69 of its nominal value The speed of the motor during the voltage sag also decreased by a significant amount dropping by over 5 from its nominal value Table 5 22 30 three phase voltage sag modified configuration AplidToqe N 0 10 20 447 5V Drive Trip Y N A 50 three phase voltage sag was also applied to the input of the modified configuration ASD For all three load conditions the ASD tripped offline due to a control power low error For this ASD even if the dc bus undervoltage protection fault had been turned on the ASD would not have tripped offline during the 30 three phase voltage sag The undervoltage protection fault is programmed to trip the ASD offline if the dc bus voltage falls below 395V which is approximately 62 of the normal full load dc bus voltage 5 3 3 6 Three Phase Capacitor Switching Transient The capacitor switching transient test was also performed on the S SkVA regular configuration ASD The output voltage of the programmable source recorded a
66. igger button and watch to see that the highlighted position markers cycle through the transient waveform sequences as expected for each channel e Go back to the Setup Menu and turn the output of CH1 CH3 and CH4 ON 92 e Place the programmable source in PROGRAM right side frequency selector switch available options are VAR 400 60 50 and PROG e Press the RESET button on the programmable source e Press the OUTPUT ON OFF button on the programmable source e Press the manual trigger button whenever a transient operation is desired The manual trigger button can also be executed remotely through the Execute Trigger VI in LabVIEW More detailed information concerning the operation and programming of the AWG is given in the AWG2005 User Manual More detailed information concerning the interface between the AWG and the programmable source is given in the technical paper titled Using the AWG2005 with the Behlman PA Series Amplifiers by Jaye Killian 93 APPENDIX B VIRTUAL INSTRUMENT FUNCTION BLOCKS Given in Table B1 is a listing of the individual query function blocks for the AWG2005 LabVIEW instrument driver Table B2 contains a listing of the individual action function blocks for the AWG2005 The individual function blocks are stored in the Tek2005 instrument library that can be found in the following path C Program Files National Instruments LabVIE W Instr lib Tek2005 Each individual function block title begins with TKAWG200
67. igher voltage are performed 10 13 82 BIBLIOGRAPHY Roger C Dugan Mark F McGranaghan and H Wayne Beaty Electrical Power Systems Quality McGraw Hill 1996 Math H J Bollen Understanding Power Quality Problems IEEE Press 2000 Tony Hoevenaars A New Solution for Harmonics Generated by Variable Speed Drives Power Quality Assurance vol 10 no 10 pp 24 30 December 1999 Richard A Epperly Frederick L Hoadley and Richard W Piefer Considerations When Applying ASD s in Continuous Processes IEEE Transactions on Industry Applications vol 33 no 2 pp 389 395 March April 1997 John Douglas Digital Society EPRI Journal vol 25 no 4 pp 18 25 Winter 2000 Mark P Mills and Peter W Huber Silicon Demand and the End of Power Quality Power Quality Assurance vol 11 no 10 pp 18 19 December 2000 Tekla S Perry Fueling the Internet IEEE Spectrum vol 38 no 1 pp 80 84 January 2001 Christopher J Melhorn and Mark F McGranaghan Interpretation and Analysis of Power Quality Measurements IEEE Transactions on Industry Applications vol 31 no 6 pp 1363 1370 November December 1995 Electric Power Research Institute Power Quality Mitigation Technology Demonstration at Industrial Customer Sites Industrial and Utility Harmonic Mitigation Guidelines and Case Studies Palo Alto CA 2000 1000566 Wilson E Kazibwe and Musoke H Sendaula Electric Power
68. in Fig 5 11 In this case the input current on the sagged phase has completely dropped out and only two of the six line to line voltage pulses are conducting current meaning the three phase rectifier is operating as a single phase rectifier This is because the average dc bus voltage during the voltage sag 636 1V is higher than the peak sagged line to line voltage 619V 5 2 3 2 10096 Load The input current for a 10 single phase voltage sag on phase a during a 100 load condition is shown in Fig 5 12 This case is similar to the 596 single phase voltage sag during a 50 load condition The current drawn by the sagged phase now has a single pulsed pattern The average dc bus voltage during the voltage sag 624 5V is only slightly higher than the peak value of the sagged line to line voltage 619V 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Figure 5 11 Input current 10 single phase sag 50 load 49 0 000 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Figure 5 12 Input current 10 single phase sag full load 5 2 4 13 Single Phase Voltage Sag For a 13 single phase voltage sag on phase a the corresponding input phase and line to line voltages are V 23120 431V rms 609V peak V 2662240 V 460V rms 650V peak 5 4 V 2662120 V 431V rms 609V peak Table 5 4 Data from a 1396 single phase sag 5096 Load 100 Load 622 4V Input Current in
69. industry In an open competition market customers can choose their supplier of power With no clear definition of responsibility for power quality and reliability utilities are striving to deliver power with a high reliability to meet customer expectations yet do so in an economical manner 2 5 Among consumers power quality is important to sensitive and disturbing loads of all levels including residential commercial and industrial users One area of particular interest termed the digital economy has been the development and growth of microprocessor based integrated circuit applications ranging from computers to phones to programmable logic controllers PLCs Many of these microprocessor based products are part of a larger infrastructure such as digital networks the internet and broadband telecommunications which demonstrate just a few examples of customers with increasingly exacting demands for power 5 According to the Electric Power Research Institute EPRI information technology accounts for 13 of the electricity consumption in the U S and they believe that it may grow to 50 in the next twenty years 5 6 The main motivator behind improving power quality is economic An increased reliability of electrical power ideally for microprocessors to 9 nines reliability or 99 9999999 reliability equates to increased productivity and profit margins As an example at Sun Microsystems Inc in Palo Alto California outages ar
70. ing Ride Through Capability for Sensitive Customers on Underground Networks IEEE Transactions on Industry Applications vol 33 no 4 pp 1083 1095 July August 1997 Mark Stephens Chuck Thomas Tom Paudert and Bill Moncrief PLC Basics and Voltage Sag Susceptibilities Part 1 Power Quality Assurance vol 12 no 1 pp 43 47 January 2001 APPENDICES 86 87 APPENDIX A PROCEDURE TO PROGRAM OPERATE AWG 1 Hardware Connections The AWG is connected to the programmable source such that three of the four available output channels drive the three PROGRAM inputs of the programmable source Table A1 1 lists the AWG channels and their specific configurations Table A1 1 AWG channel configuration AWG Channel Description Connection To Channel 1 AWG front panel Programmable source Phase A 50 Ohm PROGRAM input EEN qmeenmene Channel 3 AWG front panel Programmable source Phase B 50 Ohm PROGRAM input Channel 4 AWG front panel Programmable source Phase C 50 Ohm PROGRAM input Trigger Ipput AWG front panel Channel 2 MARKER output 50 Ohm located on AWG rear panel The AWG Channel 2 was chosen as a transient envelope generator for voltage transients The Channel 2 MARKER OUTPUT is connected to the TRIGGER INPUT to be used in the generation of transients 2 Programmable Source AWG Configuration In PROGRAM mode each phase of the programmable source is capable of generating a maximum outpu
71. ing the correct GPIB address in the appropriate command string An instrument reset can also be executed in this VI Common to all VI front panel windows are the error in and error out dialog boxes that help to troubleshoot problems when multiple subsystems are used within a VI VISA Session VISA Session for class Instrument Descriptor GPIB0 20 INSTR ID query Reset pe Hres error in no error no no EE status code Iz Rp source m error out status code a source m Figure 3 2 Front panel window for initialization VI Query ID and device type registers l Open instrument Reset instrument Send default setup default setup string EAD OFF VERB ON e L8 VISA Session Es 5 7 error out Figure 3 4 Icon connector for initialization VI Another example of a very useful VI is the AWG picture capture VI The front panel and program diagram windows of this VI are shown in Figs 3 5 and 3 6 respectively This VI takes a snapshot image of the AWG front panel display and sends the image in a specified format back 19 to the computer The image can then be imported into the VI front panel window In Fig 3 5 the imported image shows the AWG setup menu screen where file and configuration information pertaining to the four output channels is displayed In addition to determining which waveforms are programmed into what channels of the AWG the
72. ion Files profile block C5 1 Front panel window for Upload Sequence Equation File profile block C6 1 Front panel window for Download Waveform File profile block C7 1 Front panel window for Download Sequence Equation File profile block C8 1 Front panel window for Define Compile Equation profile block C9 1 Front panel window for Define Sequence File profile block C10 1 Front panel window for General Command profile block C11 1 Front panel window for Load All Channels profile block C12 1 Front panel window for Set Operation Mode profile block C13 1 Front panel window for Set Channel Output profile block C14 1 Front panel window for Execute Trigger profile block D1 1 Front panel window of standard subsystems in a profile block D1 2 Block diagram window of standard subsystems in a profile block D2 1 Program diagram window of a multiple subsystem profile block D2 2 Program diagram window of a command string to write profile block D3 1 Example icon connector E1 1 ASD input voltage 95 single phase voltage sag E1 2 ASD input current full load two phases shown E1 3 ASD dc bus voltage full load El 4 ASD input voltage 100 single phase voltage sag E1 5 ASD input current full load two phases shown E1 6 ASD dc bus voltage full load El 7 ASD input voltage 50 two phase voltage sag E1 8 ASD input current full load two phases shown El 9 ASD dc bus voltage full load E1 10 ASD input voltage 50 three phase voltage sag E1 1
73. is small due to the fact that most sags of this type have at least one phase of the ac supply that does not significantly drop in voltage thereby helping to maintain the dc bus voltage 35 4 5 Improving ASD Ride Through Capabilities Costly production downtime losses can be avoided by using ASDs with ride through capabilities There are several areas of focus for improving ASD ride through These areas can be grouped into the following classifications 4 29 e Energy storage methods e Functional operation modes of ASDs e ASD topology modifications e Internal power supplied from the dc bus voltage 4 5 1 Energy Storage Methods A number of energy storage technologies are available that can be configured to provide dc bus power for an ASD PWM inverter in the event of a voltage sag or power interruption These storage systems can include battery backup systems supercapacitors or ultracapacitors motor generator sets and Superconducting Magnetic Energy Storage SMES 4 29 37 Only a limited amount of additional stored energy needs to be supplied to the dc bus to improve ASD ride through for the most common type of single phase faults Battery backup systems can be installed as an add on module on the dc bus of an ASD They have a much higher energy per volume ratio than standard capacitors Advantages are that they can provide ride through for deep voltage sags have a nearly instantaneous transfer time and are easily obtained Di
74. is the THD of the current using a 15 30 minute averaging measurement period normalized to the maximum rms value demand load current 7 fundamental component 60Hz The TDD allows harmonic currents to be evaluated over a wide range of load conditions with a constant base value Additional expressions commonly used to describe measures of power quality in a power system are displacement power factor DPF and true power factor PF DPF cos 1 3 PF c0s9 2 DPF 1 4 I 7 SP T 1 5 h i In the above equations J is the rms value of the fundamental component of the current J is the total rms value of the current and is the phase angle between the voltage and current Another expression used to indicate the additional eddy current heating losses in a transformer due to current harmonics is the K factor 9 14 S HR dno 1 6 The K factor equation 1 6 indicates that transformer heating losses are proportional to the square of the load current and the square of the frequency 1 3 Harmonic Distortion Mitigation Techniques Harmonic distortion in a power system can be controlled and negatively affected equipment can be protected according to several different methods One method involves resizing or adding components to protect sensitive equipment Examples of this are the use of larger phase and neutral conductors derating of transformers and motors use of K rated transformers and proper sizing and de tuning of
75. itude signal phase voltage sags 2096 are applied at the input In normal operation of a three phase diode bridge rectifier each current phase has a double pulse as can be seen in Fig 5 1 which shows the full load input current when a balanced 460V rms line to line voltage is applied at the input to the ASD Each pulse corresponds to the period of time when the input line to line voltage is higher than the dc bus voltage causing a diode branch in the rectifier to be forward biased It will be shown that for relatively small single phase voltage sags depending on the loading condition which affects the average dc bus voltage the input current 39 may have either a double pulse pattern that is unbalanced a single pulse pattern or a sagged phase current that drops out completely Input Current A 7200 220 240 260 280 300 Time ms Figure 5 1 Input current drawn by an ASD at 100 load one phase shown 5 2 1 296 Single Phase Voltage Sag For a 2 single phase voltage sag on phase a the corresponding input phase and line to line voltages are V 26120 V 456V rms 645V peak V 2662240 V 460V rms 650V peak 5 1 V 2662120 VV 456V rms 645V peak Table 5 1 Data from a 2 single phase sag DC Bus Voltage during sa 646 1V 640 2V 637 4V Input Current in Sagged Phase Description of Input Current in N A Largely unbalanced Unbalanced two Sagged Phase two pulsed pu
76. k value of the sagged line to line voltage 597V 0 10000 0 00000 0 02000 0 04000 0 06000 0 08000 Seconds Figure 5 15 Input current 17 single phase sag 50 load 53 oamed 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 16 Input current 17 single phase sag full load 5 2 6 Summary of Results A summary of the results of the single phase voltage sag affects on ASD three phase diode bridge rectifier operation is presented in Table 5 6 For each single phase voltage sag magnitude and under each load condition a comparison is made between the average nominal dc bus voltage the peak value of the sag affected line to line input voltage and the resulting input current waveform pattern As the sag magnitude increases and the loading factor decreases the input current on the sagged phase drawn by the ASD progresses from a balanced double pulsed pattern to an unbalanced double pulsed pattern to a single pulsed pattern and finally drops out completely For this specific 5 5 kVA ASD tested for a single phase voltage sag of any magnitude over 17 and for any loading factor the three phase diode rectifier operates as a single phase diode rectifier 54 Table 5 6 Summary of single phase sag testing Single Phase Voltage Sag Percentage DC Bus Voltage during sag Peak Value of Voltage Envelope Current Affected by the Sag Pattern 2 50 load 640 2V 645V
77. le to Load in Phase A abc CHTAMPL aks CLOCKFREQ Lats i opy to Filepath Errori no Bro ront Panel Display Image tu Figure D2 2 Program diagram window of a command string to write profile block 3 Subsystem Icon Properties The icon connector for the Load Channel Phase A Vl is shown in Fig D3 1 Icon connectors are used to implement subVIs into a profile block VI The subVI parameters can be wired into the profile block VI through the connector terminals To set the terminal pattern connections for the icon open the subVI and right click on the icon and select Show Connector The wiring tool can then be used to assign control and indicator parameters from the front panel of the VI to the specific terminals on the icon 108 Amplitude VISA Session et dup VISA session File to Load in Phase A error out error in no error Figure D3 1 Example icon connector 4 General Functionality and Setup In addition to subVIs and commands concatenated into strings other functionality for programming profile block VIs is available in the LabVIEW environment The Function menu includes a section divisions for structures string operations Boolean logic numeric operations arrays I O commands data comparison data acquisition instrument drivers clusters and data analysis The blocks available in the Function menus enable specific monitor and control commands to be executed After profile block components
78. lies e Silicon controlled rectifier SCR drives e Arc furnaces and welders e Air conditioners and compressors HVAC e Elevators e Fluorescent lighting electronic ballasts Most of these harmonic generating loads consist of solid state rectifiers at their inputs connected to a dc bus maintained by capacitors Solid state rectifiers draw current in pulses when the input ac line voltage is higher than dc bus voltage across the capacitors As current harmonics are injected back into the system voltage drops are caused at the corresponding harmonic frequencies creating voltage distortion in the power system The voltage distortion is directly proportional to the current harmonic magnitudes and the impedance in the system cables and transformers 9 Some common effects of harmonic distortion are listed below 1 3 9 11 Harmonic voltage stress on system capacitors and equipment capacitors Resonance and overloading problems with power factor correction capacitors Additional heating and losses in conductors transformers as well as induction and synchronous machines Interference with communications circuits Misoperation of circuit breakers PLCs computers and other sensitive solid state loads Voltage distortion at the PCC According to IEEE 519 IEEE Recommended Practices and Requirements for Harmonic Control in Electrical Power Systems harmonic limits are meant to be applied at the point of common coupling PCC between the u
79. load Waveform File vi Transfers a file with a WFM extension from the internal memory of the AWG to a specified directory in the computer Upload Sequence Equation File vi Transfers a file with either a SEQ or EQU extension from the internal memory of the AWG to a specified directory in the computer Download Waveform File vi Transfers a file with a WFM extension from a specified directory in the computer to the internal memory of the AWG file must have been previously uploaded from the AWG Download Sequence Equation File vi Transfers a file with either a SEQ or EQU extension from a specified directory in the computer to the internal memory of the AWG file must have been previously uploaded from the AWG Query Internal Memory vi Returns to the VI front panel window a catalog of each file contained in the internal memory of the AWG 23 Table 3 2 AWG file creation driver profile blocks Virtual Instrument Profile Block Functional Description Define Compile Equation File vi Creates a EQU file from a given equation expression and also compiles the EQU file into a WFM file according to an input number of waveform points Create Sequence File vi Creates a SEQ file from a given combination of WFM files and each associated number of repeat cycles General Command vi Can be used to execute any combination of waveform edit functions Table 3 3 AWG setup and operatio
80. lock executes a general command to the AWG The Command to Execute parameter must be in all caps and should be formatted according to the AWG2005 programmer s manual The General Command profile block also includes the AWG 101 picture capture VI also shown in Figs 3 4 and 3 5 as a subsystem The AWG picture capture VI is useful for ensuring that the AWG has been setup as expected after running a profile block and is therefore included as a subsystem in several profile blocks The Copy to Filepath Hard Copy To and Image Format parameters all pertain to the AWG picture capture VI The AWG screen image must be imported into the Front Panel Display Image window after the profile block has been executed After running the VI select Edit Import Picture from File Select the saved bitmap file and click Open Then right click on the Front Panel Display Image window and select Import Picture 11 Load All AWG Channels Copy to Filepath IRIC Evelyn TekAWG testbmp selected port computer D Continuous mode Master Running ile to Load in DC Trigger PDC NOM WFM PHA NOM NT N Amplitude DC Trigge Filter Amplitude Offset Figure C11 1 Front panel window for Load All Channels profile block The Load All Channels profile block loads either SEQ or WFM files into each of the four channels of the AWG The filename and amplitude for each AWG channel must be specified The AWG picture capture VI is also included as
81. ls and transfer files back and forth between the computer and the AWG A complete listing of the individual function VIs for the AWG2005 instrument driver library is provided in Appendix B 22 The profile blocks created can be divided into three groups as were defined in the main objectives for the driver database The first group of profile blocks includes storage and transfer functionality to download and upload complete voltage disturbance event files to and from the AWG The second group of profile blocks includes the functionality to create new equations sequences and waveforms as well as modify existing files The third group of profile blocks includes setup and control functionality to load a voltage disturbance event configure the mode of operation settings set the channel output and control transient waveform generation Tables 3 1 3 2 and 3 3 show a listing and description of the profile blocks created for the AWG separated into the three main functionality groups Table 3 1 AWG data transfer driver profile blocks Virtual Instrument Profile Block Functional Description Upload All Waveform Files vi Transfers all files with a WFM extension from the internal memory of the AWG to a specified directory in the computer Upload All Sequence Equation Files vi Transfers all files with either a SEQ or EQU extension from the internal memory of the AWG to a specified directory in the computer Up
82. lsed 41 highest value The next current pulse in the cycle i V4 is low causing an unbalance in the phase current pulses because V is sagged 645V peak and the dc bus voltage has not had much time to discharge from its peak value The following current pulse i Vac is higher than the previous pulse since the previous pulse did not recharge the dc bus voltage to its peak value This current pulse is still smaller than the i Va current pulse since Vac is also sagged 645V peak The next current pulse i Vi is again the highest current pulse since Vy is not sagged This cycle continues and results in an unbalanced phase current pattern 5 2 1 3 100 Load The input current drawn during a 2 single phase voltage sag on phase a during a full load condition is shown in Fig 5 8 Similar to the case for a 5096 load condition the double pulse current pattern is unbalanced but not as drastically as in the 50 load condition This is because during full load more current is required by the load and the average dc bus voltage is lower 637 4V Because the average dc bus voltage is lower the i Va current pulse will charge the dc bus for a longer time phase a 205 00 0 0 e 205 VAAN UVVU VUV LUV VU 0 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure 5 2 Input phase voltage 2 single phase sag on phase a 42 675 00 f gt de bus average 646 1V E1 600
83. m points as the other three channels 1000 and is a constant nonzero dc value 4 Basic Steady State Operation With the default conditions configured according to the previous section a continuously repeated three phase sine waveform at a nominal voltage of 266V rms L N can be output from the programmable source The following steps describe steady state operation of the programmable source e Place the AWG2005 in Setup Menu Check to make sure the correct output waveforms are loaded for each channel the clock frequency and channel amplitudes are set correctly and that the outputs of CH1 CH3 and CHA are turned ON turn CH1 CH3 CH4 output ON by pressing the buttons above the output BNC connectors DO NOT TURN THE AWG OUTPUTS ON OR OFF WHEN THE PROGRAMMABLE SOURCE OUTPUT IS ON 90 e Place the programmable source in PROGRAM right side frequency selector switch available options are VAR 400 60 50 and PROG This step assumes that the programmable source itself has already been powered up e Press the RESET button on the programmable source e Press the OUTPUT ON OFF button on the programmable source If changes to the output of the AWG are desired turn the output of the programmable source off switch the frequency selection back to one of the other positions VAR 400 60 50 and press the RESET button Then make any configuration parameter changes to the AWG and repeat the process It may be possible to change the clock frequ
84. m possible programmable source output is 326V rms although the rated maximum output voltage is 305V rms Therefore the maximum peak voltage output of the programmable source is 460V L N 800V L L 3 Default Conditions All setup of the AWG must be completed BEFORE the output of the programmable source is turned ON The default settings of the AWG Setup Menu are listed below e CLOCK 60kHz e WAVEFORM SEQUENCE CHI PHA NOM WFM CH2 DC NOM WFM CH3 PHB NOM WFM CH4 PHC_NOM WFM e CHI OPERATION Normal e FILTER CHI Through CH2 Through CH3 Through CH4 Through e AMPLITUDE CHI 10 0V CH2 1 0V CH3 10 0V TRACK CHI 89 CH4 10 0V TRACK CHI e OFFSET CHI 0 0V CH2 0 0V CH3 0 0V CH4 0 0V e OUTPUT CHI ON CH2 OFF CH3 ON CH4 ON In addition to these default Setup Menu settings the operation mode specified in the Mode Menu should be set to Continuous mode Each WFM file should have a standard of 1000 waveform points The actual output frequency of the AWG 60Hz is equivalent to the clock frequency 60kHz divided by the number of waveform points 1000 The three phase waveforms are each single cycles of a sine wave with a common amplitude 0 815 peak and where each waveform is shifted by the proper phase angle 120 degrees to supply a balanced three phase output The DC NOM WFM in channel 2 serves no real purpose in a steady state operation condition For simplicity it has the same number of wavefor
85. more three phase loads are phase shifted from one another through various types of three phase transformer connections The sum of the current drawn is then less distorted than the original nonlinear current drawn by each individual load For example in a system with several ASD loads some loads can be supplied by delta delta connected transformers and other loads can be supplied by delta wye connected transformers If the loads on each drive isolation transformer are balanced harmonic current distortion can be significantly reduced In some applications where a neutral point for grounding is desired a delta zigzag transformer provides the same harmonic cancellation effect when used with loads also supplied by a delta wye connected transformer Filtering is another method for reducing harmonic currents in a power system Many topologies of harmonic filters are used with three general categories being passive active and hybrid filters 3 9 15 19 20 Passive filters consist of tuned LC filters which can be connected in shunt or in series at a point where nonlinear loads are concentrated or at an individual nonlinear load They can be tuned to block or trap single frequencies or multiple stages can be used for more than one frequency A shunt passive filter creates a low impedance path for harmonic currents at its tuned frequency thereby trapping or diverting the harmonic current from flowing into the power system A series passive filter creates a
86. n cause ASDs to trip offline are as follows 2 14 29 34 e The ASD controller may be programmed to trip the drive offline upon detection of a sudden change in operating conditions e A voltage sag which leads to a drop in the dc bus voltage may cause the ASD controller or the PWM inverter to trip the drive offline e A voltage sag which leads to insufficient voltage for maintaining the ASD s internal power supply voltage used for powering control logic may cause the ASD to trip offline e A voltage sag which leads to insufficient voltage for maintaining the ASD s external interface and control circuitry such as contactors relays and PLCs e A voltage sag can lead to an ASD overcurrent trip due to increased ac current drawn during the voltage sag or due to high current spikes that charge the dc bus capacitor immediately following the voltage sag e An ASD may trip due to motor changes such as a drop in speed or torque variations that the load process cannot tolerate Of the six circumstances listed above that cause ASDs to trip offline the two main causes are reduced dc bus voltage and reduced internal power supply and external circuitry voltage During voltage sag conditions the motor load power level dc bus capacitance internal power supply design and dc bus undervoltage trip level all affect whether or not the drive will trip offline For single phase voltage sags two of the phase to phase voltages are affected Because one of the
87. n driver profile blocks Virtual Instrument Profile Block Functional Description Load All Channels vi Loads either WFM or SEQ files into each of the four AWG channels Also sets channel parameters including clock frequency and amplitude Set Operation Mode vi Sets the AWG operation mode to either continuous used for steady state waveform tests or waveform advance mode used to simulate transient disturbances Set Channel Output vi Turns the output of each of the four AWG channels on or off Start Stop Trigger vi Executes a trigger start operation This is used in waveform advance mode to trigger the transient waveforms in the SEQ files to execute and then return to the nominal waveform set Each of the profile blocks described in Tables 3 1 3 2 and 3 3 is more thoroughly referenced in Appendix C Appendix C shows the front panel windows for each profile block and gives an explanation of how to configure the parameters in each profile block to execute power quality disturbance simulations 25 4 ADJUSTABLE SPEED DRIVE PROPERTIES 4 1 Adjustable Speed Drive Topology Induction motors are the workhorse of industry due to their low cost and rugged construction Over the years the integration of adjustable speed drives ASDs is increasing due to improved efficiency process control and productivity Earlier applications of ASDs were largely in fan and pump loads where speed control resulted in significant energy con
88. nced voltage sags Balanced three phase voltage sags can be caused by the starting of large induction motors or three phase short circuit faults Two common types of unbalanced three phase voltage sags can be caused by single phase short circuit faults or phase to phase short circuit faults 4 3 1 Balanced Three Phase Voltage Sags A balanced three phase short circuit fault can be depicted in a one line diagram as shown in Fig 4 3 All three phases drop in magnitude by the same amount and all six voltage pulses per cycle of the dc bus voltage will drop in magnitude The phase voltages for a three phase fault can by expressed as 35 36 V V V My Miv v3 pu 4 1 V Vv iv v3 Fault Figure 4 3 One line diagram of a three phase short circuit fault In 4 1 V is the per unit magnitude of the sag voltage The three phase short circuit fault results in a voltage sag that can be approximated by Z V _ E u 4 2 sag 3o Z n 2 p 30 It can be assumed that the pre fault source voltage E is equal to lpu Zs is the source impedance at the point of common coupling and Zr is the impedance between the point of common coupling and the fault The results are very similar for a three phase voltage sag caused by the starting of a large induction motor The voltage sag magnitude can be approximated by Zu 4 3 sag 3 Ze Zi pu In 4 3 a source voltage of 1pu has been assumed Zs is the
89. nctionality The development of a LabVIEW driver database for the AWG which creates and executes multiple types of voltage disturbances to be amplified and output by the programmable source is an ongoing project The functionality of the driver database can continue to expand as more power quality research and testing projects occur One proposed remotely operated testing capability has been suggested by local utility companies In this proposed addition voltage disturbance events would be captured in the field by event monitoring equipment These events would then be downloaded and converted into waveform data files for the AWG enabling the programmable source to reproduce events and anomalies that occur in a power system As mentioned in an above section the capability to program monitor and control the PQTP over the internet will open up a wide range of collaborative research efforts For the purposes of this thesis work all LabVIEW control was performed over the GPIB interface through a direct connection between the AWG and PC With new National Instruments GPIB to Ethernet controller hardware available multiple instruments including the AWG can be remotely controlled over the internet through LabVIEW In addition to configuring the hardware to control the AWG over the internet other monitoring instrumentation could be configured for ethernet access through LabVIEW as well It would then be possible to monitor the output of the programmable sou
90. ng portions of every cycle The transition point at which the dc bus voltage is always higher than the peak value of the sag affected line to line voltage is different for every ASD and for different load conditions of the ASD since different load conditions affect the size of the dc bus ripple For the 5 5kVA ASD tested a 17 single phase voltage sag was the transition point where for all load conditions the dc bus voltage was always higher than the sag affected line to line voltage causing the three phase rectifier to operate as a single phase rectifier Through the results of this testing it has been determined that the method of deriving control logic power for an ASD is a critical factor in the ride through capability of many ASDs The control logic power supply supports the control electronics so the drive can perform calculations make decisions and control the inverter switches creating the variable frequency variable voltage output to the motor and the load Many ASD topologies use linear power supplies powered from two phases of the ac input voltage to derive control logic power for the ASD 31 34 as was the case with the second 5 5kVA ASD tested It was determined that ASDs with control logic power derived directly from the input power in general and a single phase line to line in particular are extremely sensitive to voltage disturbances and are much more likely to trip off line due to a control power low condition Many ASD man
91. ock creates a specified EQU file in the internal memory of the AWG A WFM file is generated from the EQU file according to the time range equation expression and number of Waveform Points specified The Equation File Byte Count Number of Characters Waveform Points and Equation Data parameters should be specified prior to running the profile block VI A WFM file will be generated with the same name that is specified in the Equation File parameter Data for Equation File must be written in ASCII code with each expression separated by a Line Feed lt LF gt each expression should be created on a new line The first line should be the waveform range listed in the following format e range Equation Starting Time Equation Ending Time The following lines consist of the equation where e x variable taking on a value from 0 0 to1 0 within the range statement e v variable showing the current value of the waveform data at that position used to begin a new line in the equation The Number of Characters parameter sets the number of characters used in the Equation Data input box Characters include letters numbers punctuation marks and line feeds new lines The equation example in Fig C8 1 has 30 characters and a byte count of 2 9 Define Sequence File Reset Overwrite Sequence File Yes existing error out l TEST sEQ No yes no Byte Count Number of Characters error in no error Figure C9 1 Front panel window f
92. of the 5 5kVA ASD with the internal power supplied from two of the three input phases a modified configuration of the ASD was tested and the ride through capabilities compared with the original regular configuration of the ASD As was demonstrated in this case the PQTP can be used to test different ASD ride through improvement technologies The PQTP is not limited to power quality voltage disturbance testing of ASDs Many other types of commonly used power electronic equipment are sensitive to voltage sags and other disturbances and would benefit from thorough ride through characterization testing Two examples of sensitive power electronic equipment are switch mode power supplies and programmable logic controllers 6 3 3 Additional Proposed PQTP Functionality Currently the maximum peak output voltage capability of the programmable source is approximately 460V line to neutral In program mode the output of the AWG is passed through a set of amplifiers and then fed through a step up transformer to the output of the source The maximum peak output voltage of the source is limited by the step up transformer ratio In some cases it may be desirable to simulate very high voltage transients For extended peak voltage capabilities the step up transformer can be multi tapped or a second step up transformer can be installed Since the amplifier switch ratings would still be the same the overall power output rating would be smaller when tests at a h
93. oltage during a single phase fault 32 4 6 ASD dc bus voltage during a phase to phase fault ss 33 5 1 Input current drawn by an ASD at 100 load one phase shown 39 5 2 Input phase voltage 2 single phase sag on phase 0 eee eee 41 5 3 ASD dc bus voltage 2 single phase sag no load at 0 02 seconds Bee ey enal Kee 42 5 4 Input current 2 single phase sag no load phases a and c shown we 42 5 5 ASD dc bus voltage 2 single phase sag 50 load 43 5 6 Input current 2 single phase sag 50 load phases a and c shown 43 5 7 ASD dc bus voltage 2 single phase sag ull load 44 5 8 Input current 2 single phase sag full load phases a and c shown ee 44 5 9 Input current 5 single phase sag 50 load 46 5 10 Input current 5 single phase sag full load 47 5 11 Input current 10 single phase sag 50 load 48 5 12 Input current 10 single phase sag full load 49 5 13 Input current 13 single phase sag 50 load 50 LIST OF FIGURES Continued Figure Page 5 15 Input current 17 single phase sag 50 load 52 5 16 Input current 17 single phase sag full load 53 5 17 ASD input voltage 90 single phase voltage sag LLL 58 5 18 ASD input current full load two phases shown ss 58 5 19 ASD dc bus voltage full load 58 5 20 ASD input voltage 100 single phase voltage sag j 59 5 21 ASD input current full load two phases shown kkk 60 5 22 ASD dc bus voltage full lo
94. onsisted of a 5 5kVA 460V line to line ASD supplying a four pole Shp induction motor The internal power supply of the second 5 5kVA ASD is derived from two phases of the three input phases to the ASD Again the motor was loaded by a 15hp dc generator where the dc power was dissipated in a 25kW resistive load bank All of the ASD configurations and settings were kept to the factory default conditions The PWM inverter switching frequency was set to 2 2kHz Similar to the previous ASDs tested there are a few ride through options available with this ASD One option is a regeneration power ride through control that uses regenerated energy from the rotating motor when a momentary power failure occurs The maximum regeneration power ride through time can also be specified Another option is auto restart which determines the speed of the motor and outputs a matching frequency and voltage 68 when input power returns to enable a smooth restart of the motor Both of these options were turned off during testing The ASD also has an undervoltage trip selection parameter with a factory set undervoltage trip level When the undervoltage trip selection is on an undervoltage detection time parameter can also be specified During the testing the undervoltage trip selection parameter was turned off As is shown in the testing results the ASD internal power supply is highly susceptible to voltage sags that cause the ASD to trip offline due to a c
95. ontrol power low condition In order to improve the ride through characteristics of the ASD the single phase transformer and rectifier used to step down the input ASD voltage to the internal power supply was replaced with a three phase transformer and rectifier The regular configuration experimental results in this section refer to the ASD configured with a single phase transformer front end to the internal power supply The modified configuration experimental results refer to the ASD configured with a three phase transformer front end to the internal power supply In the regular configuration the two of the three input phases that supply the internal power supply through the single phase transformer shall be referred to as phases b and c Therefore phase a input to the ASD does not affect the magnitude of the internal power supply voltage The ASD was tested with several magnitudes of single two and three phase voltage sag disturbances Different magnitudes of voltage sags were applied to the regular and modified configuration ASD dependent on each configuration s offline trip level sensitivity In all cases the voltage sag disturbance sequences were generated for 300 cycles or 5 seconds The ASD was also tested with a three phase capacitor switching transient waveform The switching transient had a frequency of 480Hz and was four cycles therefore 8 33ms in duration 5 3 3 1 Single Phase Voltage Sags Regular Configur
96. or Define Sequence File profile block 100 The Define Sequence File profile block creates a specified SEQ file in the internal memory of the AWG The SEQ is compiled with a set of WFM files each with a specific repetition number that are listed in the Sequence Waveforms and Repetition Numbers parameter The Sequence File Byte Count and Number of Characters parameters should also be specified prior to running the profile block VI Waveform data for sequence file must be written in ASCII code with each expression separated by a Line Feed lt LF gt each waveform expression must be on a new line The first waveform entered in the sequence should be the nominal continuously output waveform Each successive waveform should be entered on a new line After each waveform is entered the number of repetitions number of times executed of each waveform should be separated by a comma and a space The first waveform nominal is usually repeated once Similar to the Define Compile Equation profile block the Number of Characters parameter includes letters numbers punctuation marks spaces and line feeds new lines 10 General Command Copy to Filepath PIC Evelyn TekAWG testbmp Hard Copy To selected port computer 30 Apr 01 21 22 16 CH4 RC V CR Ed OT Advance ntigure Triggered Gated Waveform autostep uiu Slave Figure C10 1 Front panel window for General Command profile block The General Command profile b
97. output voltage will result with a 10 0V amplitude setting After the nominal and transient waveforms have been created for a specific transient operation SEQ files need to be created for each of the four AWG channels The first WFM file in each sequence should be the nominal case waveform Each successive WFM there can be multiple file should be a transient waveform with markers set accordingly A general list of the steps necessary to create a transient waveform operation is shown below e Generate a nominal case waveform WFM file for each of the four AWG channels e Generate a transient case waveform WFM file for each of the four AWG channels Transient waveforms should be the same length as the nominal case waveforms and have markers set HIGH near the beginning and LOW near the end of the waveform The amplitudes of the transient waveforms must be scaled to end up as desired according to the amplitude factor set with the nominal case waveforms e Generate a sequence SEQ file for each of the four AWG channels The sequence files should include the nominal case waveform as the first file and the transient case waveform as the second file Multiple transient case waveforms can be entered e In the Setup Menu load the SEQ files into each of the four AWG channels Also set the appropriate clock frequency and amplitude factors e Inthe Mode Menu select WAVEFORM ADVANCE and RUN CONTINUOUS e While still in the Mode Menu press the tr
98. ped offline For the test at no load the ASD input voltage current and dc bus voltage are shown in Figs 5 26 5 27 and 5 28 respectively Again the increase in the ripple voltage on the dc bus and the decrease in motor load speed are more dramatic than for the single phase voltage sags Table 5 10 50 three phase voltage sag results Applied Torque Nm 0 1 20 Spedapm aR 1787 172 D vTip YN N v v gt 365 090 00000 0 20000 0 40000 0 60000 0 80000 1 00000 Figure 5 28 ASD dc bus voltage no load 63 53 43 Three Phase Capacitor Switching Transient Shown in Fig 5 29 is the AWG front panel display and test setup to simulate a three phase 480Hz capacitor switching transient These waveforms were created in the AWG by superimposing a damped high frequency 480Hz sine wave with a nominal 60Hz sine wave The peak phase voltage value of the transient was approximately 450V Fig 5 30 shows the output of the programmable source recorded at the input of the ASD It can be seen that the output of the programmable source produces a very good representation of the input waveform sent from the AWG The ASD was not at all affected by the capacitor switching transient under all load conditions The dc bus voltage and the motor speed were both maintained at their normal levels GPIB Wavelorm Advance mode Master Running 5 en aten Riera 18 Dec 00 13 26 24
99. performed by creating a set of three equation files in the AWG that detailed the percentage of each harmonic added to the fundamental component The equation files were compiled into single cycle waveform files which were then output by the programmable source The benefits of conducting this type of analysis are to determine the effects of pre existing harmonics on induction motors This will likely be the focus of future graduate work Figure 5 31 Output of programmable source with 10 voltage total harmonic distortion 77 78 6 CONCLUSIONS 6 1 Benefits of the POTP A unique and versatile Power Quality Test Platform PQTP has been implemented in the MSRF at OSU The central component of the PQTP is a 120kVA programmable ac power source that is interfaced with an AWG When combined with the 500hp test bed 300hp dynamometer and 750kVA dedicated lab transformer the MSRF has the highest power rating and power quality testing capabilities of any educational research facility in the U S Until recently most research relating to the effects of power quality disturbances on sensitive power electronic equipment has been based on theoretical analysis of equipment architecture system simulation industrial customer surveys and monitoring and recording of power quality disturbances in field applications The laboratory creation of realistic voltage disturbance conditions has the advantage of producing a more accurate characterization of th
100. pter 6 is the concluding chapter where experimental and theoretical ASD ride through results are discussed Also future work and recommendations are made pertaining to both the power quality test platform capabilities and ASD ride through research 11 2 POWER QUALITY TEST PLATFORM 2 1 Equipment Setup The power quality test platform PQTP has been implemented in the Motor Systems Resource Facility MSRF at Oregon State University as shown in Fig 2 1 The input of the programmable source is protected through a 200A circuit breaker and the output is directly wired to a three phase terminal connection box The output terminal connection box consists of several types of connectors enabling a variety of test loads to be fed from the programmable source A PQ power analyzer is configured between the output of the programmable source and the input of the test load The PQTP has been installed such that either of the MSRF test beds can be supplied by the programmable source in addition to several of the laboratories in the Dearborn Hall basement For the purpose of this thesis all experimental work has been performed with the 15hp test bed used as a test load for the PQTP Dedicated Utility Supply 750 kVA Auto 480 0 to 600 Transformer Motor Motor 500 h 50 h Starter B Starter di Torque Speed de supply 1 Transducer ot resistive U load System Under Test 120kVA Programmabie t 1 Li LI 1 t 4
101. pters Chapter 1 provides background information on power quality and why it is an important issue among electric utilities and end use consumers Also discussed are the classifications of power quality disturbances causes and effects of waveform harmonics and mitigation techniques for waveform harmonics The definition of the thesis research project is also summarized In Chapter 2 the equipment configuration of the power quality test platform is described The test capabilities of the power quality test platform are outlined and the general operation and control of the test platform is explained Chapter 3 provides a short overview of the LabVIEW programming environment Also presented is a detailed description of the development of a LabVIEW driver database which is used to program monitor and control the power quality test platform s arbitrary waveform generator Included in Chapter 4 is an explanation of the architecture of a three phase voltage source inverter adjustable speed drive Also described is the theoretical background behind the susceptibility of ASDs to voltage sags Additionally methods for improving ASD ride through capability are presented Chapter 5 presents experimental results of ASD ride through characterization obtained from testing with the power quality test platform Comparisons are made between different architectures of ASDs and ride through performance is evaluated for multiple types of voltage sags Finally Cha
102. rce and other various parameters associated with a particular PQ testing program through LabVIEW in local and remote locations 6 3 2 Additional Proposed Ride Through Testing In this thesis the ASD ride through characterization testing was performed on 5 5kVA and l1kVA ASDs supplied from two different manufacturers More supporting results can be obtained by testing ASDs from other manufacturers With the PQTP ASDs can be tested with ratings up to 100kVA and motor loads up to 100hp It would be beneficial to characterize ASD ride through performance over the entire range of 5 5kVA to 100kVA In addition to testing the affects that PQ voltage disturbances have on the ride through capabilities of ASDs it may also be beneficial to characterize the affects that PQ voltage disturbances have on ASD efficiency A research proposal is currently under review that would incorporate both the wide range of ASD 81 ride though testing as well as the characterization of PQ voltage disturbance affects on ASD efficiency DC output ASDs are still very common in many industrial applications requiring wide torque and speed ranges and are also susceptible to many of the same power quality voltage disturbances as ac ASDs The PQTP could be used to characterize the ride though capabilities of a variety of sizes of dc drives The ASDs tested in this thesis were standard mass produced ASD models configured without additional ride through protection In the case
103. rol power low error Table 5 16 65 single phase voltage sag phase a regular configuration Applied Torque Nm 0 10 2 Speed rpm Drive Trip Y N The test results for a 100 single phase voltage sag on phase a supplying the ASD are shown in Table 5 17 For the three load conditions the ASD did not trip offline For the test at full load the ASD input voltage current and dc bus voltage are shown in Appendix E The resulting drop in dc bus voltage and motor speed are again the same as for the 63 and 65 single phase voltage sags Similar to the 65 single phase voltage sag a 100 single phase voltage sag on phases b or c causes the ASD to trip offline under all load conditions due to a control power low error The dc bus voltage maintained during a complete single phase outage for 5 seconds is high enough to support operation of the ASD as was also demonstrated with the 70 earlier tests involving the first 5 5kVA ASD and the 11kVA ASD with internal power supplied from the dc bus voltage However this second 5 5kVA ASD configuration with the internal power supply drawing from two of the three input phases causes the ASD to trip offline due to a control power low error for any single phase sag greater than 63 of nominal on either of 66 5 phases b or c Table 5 17 100 single phase voltage sag phase a regular configuration AppledTorqe N
104. sadvantages are that additional space is required they have a relatively low cycle life and require more maintenance Supercapacitors commonly electrochemical capacitors are similar to batteries in that they use liquid electrolytes and can be configured to meet a wide range of power energy and voltage requirements While they don t have quite the energy density of batteries they do have the highest energy density of any capacitor technology a high cycle life are maintenance free and the lowest cost capacitor technology A motor generator set M G set uses its rotating mass to supply energy to the dc bus during a voltage sag or interruption and a diesel engine can be used to supply energy to the generator during sustained outages M G sets are reliable but require maintenance and are more expensive than battery systems A SMES system circulates a large amount of current in a superconducting coil or magnet that can be supplied to the dc bus during a voltage sag or interruption SMES systems are highly 36 efficient and provide rapid response but also require extensive refrigeration to cool the superconducting system Additional standard capacitors can also be added to the dc bus to improve ASD ride through Calculations for additional capacitance needed to maintain a minimum dc bus level were shown in a previous section and based on conservation of energy Another approximation to calculate additional capacitance needed to enable a
105. sag and is automatically restarted when the dc bus voltage recovers However the inverter is restarted at a user defined preset frequency which usually leads to large drops in motor speed This kind of restart feature is sometimes also referred to as non synchronous restart 37 Flying restart is a more complex form of automatic restart that is also referred to as synchronous restart The flying restart feature attempts to resynchronize the spinning motor after the dc bus voltage has been restored resulting in only a limited drop in motor speed 4 5 3 ASD Topology Modifications An ASD can be modified or a new drive can be designed to include a boost converter which maintains the dc bus during a voltage sag or interruption When the dc bus voltage falls below a certain level the boost converter transistor switch will adjust its duty cycle to regulate the dc bus voltage to the minimum voltage required by the PWM inverter A boost converter circuit can provide ride through capabilities for voltages sags without additional energy storage 4 29 40 In order to provide ride through capabilities for outages an energy storage device would need to be integrated with the boost converter design Another modification that can improve ASD ride through is to replace the front end uncontrolled diode rectifier with a controlled rectifier enabling better regulation of the dc bus voltage A controlled rectifier would also reduce lower order input current h
106. servation with reported values up to 35 with very short payback times and in these applications the dynamics of speed control were not necessarily very fast or precise More recently the cost of ASDs has been decreasing and their performance has been improving Today ASDs are used in many additional industrial applications including semiconductor manufacturing paper machines winders extruders metal casters and overhead cranes 4 29 Currently 18 of all new motor installations and 12 of existing motor systems in the U S are driven by ASDs 14 Speed control of induction motors is commonly achieved through voltage source inverter adjustable speed drives The typical configuration of an ac ASD is shown in Fig 4 1 At the input is an uncontrolled three phase diode bridge rectifier that supplies the dc bus The dc bus ripple voltage is minimized by the dc bus capacitor The dc bus voltage is inverted to a variable frequency variable magnitude ac voltage by a pulse width modulated PWM inverter The speed of an induction motor can be varied by controlling the voltage frequency f applied to the stator For the torque capability to equal the rated torque at any frequency the airgap flux should be kept constant and equal to its rated value by controlling the magnitude of the applied voltage Vs in proportion to the frequency Over a large range of the motor torque speed characteristic the V frelationship is linear 13 Diode Rectifier de
107. single phase rectifier is dependent on the parameters of the ASD primarily the dc bus capacitor size and the load condition of the ASD both of which affect the dc bus ripple voltage The ASD ride through characterization testing involved supplying ASDs under different load conditions with increasing magnitude single two and three phase voltage sags until the ASD tripped offline Through the experimental testing it was found that the architecture of an ASD can withstand a continuous single phase outage without significantly affecting the speed of the motor even under a full load condition The experimental testing results also substantiated the significant differences in ride through capability of an ASD based on the configuration of the internal control power supply It was shown that ASDs with internal power supplied from two of the three input phases to the ASD are much more susceptible to voltage sags than ASDs with internal power supplied from the dc bus voltage For two and three phase voltage sags it was found that ASDs can ride through relatively small two and three phase voltage sags with an increase in the dc bus ripple voltage However for most two and three phase voltage sags ASDs under a full load condition can experience a significant decrease in motor speed in some cases greater than 5 which is unacceptable in some industrial processes 80 6 3 Recommendations for Future Work 6 3 1 Additional Proposed Instrument Driver Fu
108. snapshot picture also enables many other parameters of the AWG to be seen Some of the other parameters include the clock frequency waveform operation mode waveform amplitude and output channel status In this example it can be seen that nominal sinusoid waveforms have been loaded into the three output phase channels the clock frequency is set to 60kHz the operation mode is set to continuous the amplitude of the three output phases is at 10 0V and the output channels for the three phases are turned on Dup VISA Session Format HEMP JO Hard copy to selected port computer Continuous mode Master Running 30 Apr 01 16 57 03 waveform Sequence CHI PHA NOM KEM splay Graphics Text Figure 3 5 Front panel window for AWG screen capture VI 20 Figure 3 6 Program diagram window for AWG screen capture VI 3 5 LabVIEW Profile Block Virtual Instruments Since the AWG requires a specific order of instructions when operated remotely over a GPIB interface it is convenient to combine several of the common sequences of commands into profile blocks After several functional VI blocks had been created it was possible to combine multiple VIs together as subsystems and create profile blocks Each profile block begins with an AWG initialization VI and ends with an AWG close VI In between are the functional VIs needed to carry out a sequence of instructions In most profile blocks a snapshot image of the AWG screen is di
109. source impedance and Zy is the motor impedance during startup Voltage sags due to induction motor starting do not typically drop Vag lower than 85 of the nominal voltage 2 30 Consider an ASD with a motor load P nominal dc bus voltage Vo and capacitance C In the case of a balanced three phase sag when the absolute value of the ac input voltage is less than the dc bus voltage the electrical energy supplying the load comes from the dc bus capacitor In a voltage sag condition conservation of energy dictates that the capacitor energy at time is equal to the initial capacitor energy minus the energy consumed by the load 2 30 1 1 CH CV Pt 4 4 2 A m As long as the dc bus voltage is greater than the absolute value of the ac voltage 4 4 holds true and an expression for the dc bus voltage during the voltage sag can be given as 2P VO V nu 4 5 It is assumed that the load power consumption remains constant during the voltage sag This assumption implies the inverter is ideal when in reality as the dc bus voltage drops due to the voltage sag the output current increases thereby increasing the switching losses during the sag Most ASDs that trip offline due to a voltage sag do so when the dc bus voltage reaches a certain value Vmin The times it takes for the dc bus voltage to reach the trip value can be given as C t ogh P 4 6 31 In 4 6 the capacitance is expressed in UF kW the dc bus voltage is expresse
110. specified ride through time can be given by 14 Cole 4 14 a Vicario In 4 14 Va is the nominal dc bus voltage Z4 is the average dc link current and is the ride through duration Although this is a simple solution to improve ASD ride through the cost and additional space required is high 4 5 2 Functional Operation Modes of ASDs Most ASDs have programming features that allow for voltage sag ride through capability Some of the more common types of programming features are ride through using load inertia automatic restart and flying restart 4 29 38 39 For any of these features to be used it is important that the control power to the ASD remain online This requires the control power to be derived from the dc bus or from separate energy storage means such as batteries Ride through using load inertia can be implemented when the dc bus voltage falls to a minimum level In that circumstance the PWM inverter will operate at a frequency slightly below the motor frequency causing the motor to act as a generator The energy generated is transferred back to the dc bus and after the voltage sag the motor is reaccelerated back to its nominal operating point This method is useful in applications that don t require precise speed regulation and where the ASD internal power supply voltage is derived from the dc bus Automatic restart is the most commonly used ASD programmable feature where the PVM inverter is disabled during a voltage
111. splayed on the VI front panel since it is useful to be able to see exactly what is displayed on the front panel screen of the AWG after a series of instructions has been performed Profile blocks were created to enable the AWG to simulate power quality disturbances entirely by remote operation as defined in the main objectives above Figs 3 7 and 3 8 show the front panel and program diagram windows respectively of a simple profile block VI The profile block VI loads either waveform or sequence files into the four channels of the AWG and also configures the file amplitude settings The waveform or sequence files must already be stored in the internal memory of the AWG The front panel window shown in Fig 3 7 has control indicators for inputting the files to be loaded and their amplitudes for each channel as well as control indicators for the clock frequency and front panel image parameters The program diagram window shown in Fig 3 8 contains subsystem VIs that load files and set parameters for each AWG channel 21 ma Figure 3 8 Program diagram window for Load All Channels profile block 3 6 New Instrument Driver for AWG Once the existing VIs were all functioning correctly with the AWG2005 additional VIs were created to expand primarily the action and status and data transmission capabilities This included VIs to create and compile equation waveforms create sequences of waveforms load files and operation mode setting into channe
112. st load and monitored by the PQ power analyzer When the AWG is not programming the source output the source cannot be controlled via computer with the Lab VIEW GPIB interface When the AWG does program the output voltage of the source each of the three output phase corresponding channels must have a different waveform or sequence file loaded and their output turned on In the continuous operating mode the output of the AWG is amplified by the source and output to the test load In the waveform advance mode a nominal waveform is continuously output by the AWG The nominal waveform is amplified by the source and output to the test load until the trigger signal is applied to the AWG The trigger signal can be executed manually or remotely from the LabVIEW interface The trigger signal causes the waveforms in the sequence following the nominal waveform to each cycle one time in consecutive order After the last waveform in the sequence has been executed the output of the AWG returns to the continuous output of the initial nominal waveform 26 The entire cycle of a waveform advance mode sequence can be captured by the PQ power analyzer One or more event mode trigger parameters can be setup to match the particular power quality disturbance programmed in the waveform advance mode sequence The number of cycles of data to capture and record after the triggered event can also be user defined The maximum possible event length recorded to a data file is 28800
113. t sine wave of 310V rms L N Maximum peak voltage capabilities are actually 1 48 times the maximum rms voltage Care must always be taken to ensure that the AWG does not generate signals that are outside the operation range of the programmable source This includes dc signals and very high frequency signals gt 2kHz The peak current capabilities are 2 9 times the maximum rms rating of 144 amps per phase The maximum rms current rating should never be exceeded 88 The output voltage range of the AWG is 0 10V peak to peak The AWG output voltage is configured with the programmable source amplifier output such that for a sinusoidal waveform a 9 5V peak to peak output voltage from the AWG corresponds to a 310V rms maximum output voltage programmable source output voltage A common nominal phase voltage used in testing motors and power electronic equipment is 266V rms 460V L L An AWG output voltage of 8 15V peak to peak corresponds to a 266V rms programmable source output voltage When creating a waveform file the data point amplitude can range between 1 and 1 To create a simple programming setup for the AWG all nominal waveforms are created with a peak value of 0 815 Therefore the maximum amplitude factor of 10V can be entered into the setup menu of the AWG and the desired AWG output voltage of 8 15V peak to peak will result Since an AWG output voltage of 9 5V peak to peak corresponds to a 310V rms programmable source output the maximu
114. t the input of the ASD as well as the input current and dc bus voltage waveforms are shown in Appendix E Again the peak phase voltage value of the transient was approximately 450V The ASD was not at all affected by the capacitor switching transient under all load conditions The dc bus voltage 74 and the motor speed were both maintained at their normal levels similar to the first 5 5kVA and 11kVA ASD capacitor switching transient test results 5 4 Analysis of ASD Ride Through Testing The ability to create power quality voltage disturbances as just shown in the previous sections enabled a thorough analysis of the ASD operating and ride through characteristics A summary of the ASD ride through characterization is shown in Table 5 23 By conducting these voltage sag and capacitor switching transient tests while monitoring the dc bus voltage and motor speed it was possible to determine under what conditions a particular ASD would ride through a voltage disturbance and under what conditions an ASD would trip off line The results of the lower magnitude single phase voltage sag testing show that the three phase diode bridge rectifier does not always convert to single phase rectifier operation for any magnitude of single phase sag Depending on the parameters of the ASD namely the size of the dc bus capacitor for some smaller magnitude sags the peak value of the affected line to line voltage may still be higher than the dc bus voltage duri
115. tage 20 two phase voltage sag on phases b and c i 0 00000 0 06000 0 12000 0 18000 0 24000 0 30000 Figure E2 17 Figure E2 18 ASD dc bus voltage full load ASD did not trip offline 120 400 00 0 00 200 00 00 2 7400 00 5000 0 02000 0 04000 0 06000 0 08000 0 10000 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 Figure E2 20 ASD input current full load two phases shown ASD did not trip offline 577 50 528 75 528 75 480 86 00 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 Seconds Figure E2 21 ASD dc bus voltage full load ASD did not trip offline 121 525 00 262 50 eo gt 0 00 N gt 262 50 525 00 5 0 00000 0 02198 0 02396 0 03594 0 04792 0 05990 Seconds Figure E2 22 ASD input voltage capacitor switching transient 0 00000 0 01198 0 02396 0 03594 0 04792 0 05990 615 00 0 00000 0 01193 0 02385 0 03578 0 04771 0 05964 Seconds Figure E2 24 ASD dc bus voltage full load capacitor switching transient 122 3 S SkVA ASD Internal Power Supply Derived From Three Phase Input Transformer 409 00 JUA 400 09 0 vi 00000 0 02000 0 04000 0 06000 0 08000 0 10000 Seconds Figure E3 1 ASD input voltage 50 two phase voltage sag on phases b and c 0 00000 0 04000 0 08000 0 12000 0 16000 0 20000 469 000 00000 0 04000 0 08000 0 12000 0 16000 0 20
116. ted arbitrary waveform generator AWG which creates realistic voltage disturbance conditions that can be used to characterize ride through capabilities of industrial processes in a controlled environment Also presented is a command driver database that has been created and tested using LabVIEW which contains the functionality necessary to conduct a wide range of power quality research and testing projects by remotely configuring and controlling the AWG The power quality research and testing capabilities of the POTP are demonstrated with ASD diode bridge rectifier operation analysis and ride through characterization This research shows the transition of an ASD s three phase diode rectifier into single phase diode rectifier operation when relatively small single phase voltage sags are applied to the input Also shown are ride through characterizations of varying sizes and configurations of ASDs when subjected to single two and three phase voltage sags as well as capacitor switching transients In addition ASD topologies providing improved ride through capabilities are determined Copyright by Evelyn Matheson June 8 2001 All rights reserved A Remotely Controlled Power Quality Test Platform for Characterizing the Ride Through Capabilities of Adjustable Speed Drives by Evelyn Matheson A THESIS submitted to Oregon State University in partial fulfillment of the requirements for the degree of Master of Science Presented June
117. the deviation of the power system fundamental frequency from its nominal value typically 60 Hz Power system frequency is directly related to the speed of the generators supplying the system Therefore significant frequency deviations on a large power system are rare Frequency deviations could be caused on an isolated generator load system due to inadequate governor response to abrupt load changes The main goal of electric utilities and end use customers is to minimize the number of power quality problems This can be achieved by limiting the amount of power quality disturbances caused by equipment by improving the performance of the power system and by making equipment less sensitive to power quality disturbances 1 2 Harmonic Distortion Harmonic distortion of voltage and current results from the operation of nonlinear loads and devices in a power system A nonlinear load is one in which the current is not proportional to the applied voltage Nonlinear loads draw currents whose frequencies differ from the frequency of the source Nonlinear loads that cause harmonics can often be represented as current sources of harmonics The system voltage appears stiff to individual loads and the loads draw distorted current waveforms 3 8 Harmonic generating loads that are commonly used in residential commercial and industrial applications are listed below e Adjustable speed drives e Switch mode power supplies e Uninterruptible power supp
118. tility system and multiple customers Fig 1 1 12 A two way responsibility has been proposed for controlling harmonic levels on the power system Customers must limit harmonic currents injected into the power system Utilities must control the harmonic voltage distortion by making sure system resonant conditions do not cause excessive magnification of the harmonic levels Utility System 4 L Other Utility Customers Utility System Other Utility Customers Customer Under Study Figure 1 1 Power system showing location of the PCC where other customers can be supplied The following expressions are commonly used to indicate the harmonic distortion of a waveform 13 The total harmonic distortion THD can be calculated as a percentage for either a voltage or current waveform b 25 THD x 100 1 1 The magnitude of the individual harmonic components is Z where A is the harmonic order and 7 is the rms value of the fundamental current component In some cases THD may not be a very good indicator of the amount of current waveform distortion in a system This is true for circumstances where the current distortion of a light load may be very high yet would not have a significant impact on the power system IEEE Standard 519 1992 uses total demand distortion to evaluate the level of distortion in voltage and current waveforms h n TDD TE x100 L 1 2 The total demand distortion TDD
119. two pulsed unbalanced 2 100 load 637 4V 645V two pulsed unbalanced 5 50 load 636 6V 636V single pulsed 5 100 load 630 0V 636V two pulsed unbalanced 50 load 636 1V 619V dropped out 10 100 load 624 5V 619V single pulsed 50 load 635 8V 609V dropped out pulsed Input dropped out 5 2 7 Diode Rectifier Stresses Due to Single Phase Voltage Sags Single phase voltage sags induce additional stresses on the three phase diode bridge rectifier of an ASD The input current supplied by the phases not affected by the voltage sag is increased in order to continue supplying the motor load and also re charge the dc bus capacitance The increase in input current passing through the diode branches is maximum when the three phase 57 e Fault Menu Parameter Controlled stop set to NMS maintenance of dc bus by regenerating the kinetic energy from the machine inertia during the three phase voltage sag testing only When set to no the drive did immediately trip with due to an undervoltage fault for three phase voltage sag disturbances under all load conditions The ASD was tested with several types of voltage sag disturbances including single phase voltage sags at both 90 see Fig 5 17 and 100 see Fig 5 20 of nominal voltage This means that during the voltage sag there was 10 and 0 respectively remaining voltage on the sagged phase Also tested were two phase see Fig 5 23 and three phase
120. ufacturers are now designing ASDs with dc dc switch mode power supplies that are powered off the dc bus which are less susceptible voltage disturbances 75 Table 5 23 Summary of ASD Ride Through Results S SkVA ASD 10kVA ASD 5 5kVA ASD Parameter S SkVA Description Modified ASD Internal Power Supply dc bus dc bus ac input ac input Configuration voltage voltage single ph TX three ph TX en EE e ae Maximum Sag Ride 100 Through Capability 100 100 63 95 3 89 6 97 0 23 0 68 0 2 0 1 50 50 30 50 72 69 6 83 1 72 9 B E i DC Bus Voltage During Full Load Motor Speed Drop During Full Load Two Phase Sags Maximum Sag Tested Did ASD Trip Offline DC Bus Voltage During Full Load Motor Speed Drop During Full Load Three Phase Sags Maximum Sag Tested Did ASD Trip Offline DC Bus Voltage 7196 69 4 load condition no load no load full load full load Motor Speed Drop 27 5 44 7 2 1 5 1 load condition no load no load full load full load 76 With the AWG and programmable source it was possible to accurately pinpoint the circumstances under which a 5 5kVA ASD with control logic power derived from the input would trip off line By alternating the phase to which a single voltage sag was applied it was seen that a voltage sag applied
121. ystems in a profile block 106 2 Common Profile Block Structures Two common profile block structures can be used to implement most functionality for controlling the AWG2005 Both profile block structures include the three standard subsystems Initialize vi Close vi and Make Hard Copy vi The first common profile block structure consists of multiple subVI profile blocks connected together in series as shown in Fig D2 1 This program diagram window example is from the Define Compile Equation VI To create a new VI place the subVIs in the block diagram in the desired order of execution and then wire the subVIs together using the VISA session and error cluster parameters The Initialize VI opens a VISA session VISA is the standard I O Application Programming Interface API for instrument drivers throughout the instrumentation industry VISA can control GPIB instruments making the appropriate driver calls depending on the type of instrument being controlled The LabVIEW instrument driver blocks consist of VISA function calls The VISA session establishes a link with the AWG and allows for other commands to be executed The VISA session and error signals are connected in series to each subsystem Each of the VISA commands contains error input and error output terminals to pass error clusters from one VI to another An error cluster contains an indication of whether an error has occurred a numeric VISA error code and the location of the VI where th

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