Home

APG013 User Manual

1. 54 Register 6 2 INTE Interrupt Status 56 Register 7 1 TOCNT TimerO Counter 59 Register 7 2 TOPR TimerO Period 59 Register 7 3 TODUTY PWM Mode Duty Width 59 Register 7 4 TimerO Control 60 Register 8 1 Timer1 Counter 67 Register 8 2 TTPR Timer1 Period Register 67 Register 8 3 T1CON Timer1 Control 2 41 01012 0 01 2 14 4 1 1 68 Register 10 1 PBDIR Port B Direction Control Register 72 Register 10 2 PBDATA Port B Pin Data 73 Register 10 3 PBWAK Port B Pin Interrupt Wake up Control 73 Register 10 4 ODCON Open drain Output Control 74 Register 10 5 PUPCON Internal Weak Pull up Control 75 Register 10 6 PDNCON Internal Weak Pull down Control 76 Regi
2. 39 4 1 Power on Reset POR and Low Voltage Reset LVR 43 42 RSTB and Watchdog EE 45 Chapter 5 Clock and Power saving Mode 2 21 4 2 1 21 2 7 1 1 1 47 5 1 System clock uu u 47 5 1 1 Single Oscillator MOI 47 5 1 2 eere err ee 47 5 1 3 System Speed Selection ERR Ades 48 5 2 Power saving mode eerta ene can 48 Dus ue TEEN 51 Chapter 6 Interrupt ege 52 671 CET e EE 55 6 2 TimerO Interr plt u cec at ree e ren en een e Ra sa e e ETRAS NR 56 G RN E 56 6 4 Port B input change 56 Chapter T Timer02 Aa 58 eV dies Em 62 EZ Counter MOG ERRARE TTE 62 eg ERR 63 CA clip 65 Chapter TImerT KE 66 OQ ER Nun lee 70 2011 AppoTech Ltd 3 APG013 UM 100 EN 013 8 bit RISC Microcontroller Rev 10 0 USER MANUAL 8 2 lee EE 70 Chapter 9 Watohdog EE 71 Chapter 10 10 POrt EE 72 10 1 Normal I O port 72 PORT cite Uo Ebo d da ep ute b
3. Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Register 10 2 PBDATA Port B Pin Data Register PBDATA Address 5 4 3 2 1 0 POR Default Port B Pin Data Register General part PBDAT PBDAT PBDAT PBDATA PBDAT PBDAT XXXX XXXX 0x06 A5 4 2 A1 RW RW RW RW RW RW Bit Bit Name Mode Description 7 6 Reserved 5 0 PBDATA R W Port B Data When Port B pin is configured as output PBDATA will be output to pin If PBx is set as output pin Reading PBDATA will return PBDATA value when RDPORT 1 Reading PBDATA will return pin status when RDPORT 0 If Port B pin is configured as input reading PBDATA will return pin state Register 10 3 PBWAK Port B Pin Interrupt Wake up Control Register PBWAK Address 5 4 3 2 1 0 POR Default Port B Pin Input General part PBWAK PBWAK PBWAK PBWAK PBWAK PBWAK 0000 0000 Interrupt Wake up Control 0x09 9 5 3 1 9 Register RW RW RW RW RW RW Bit Bit Name Mode Description 7 6 Reserved 5 0 PBWAK R W Port B Wake up select bit 1 Enable input change interrupt wake up function 0 Disable input change interrupt wake up function 2011 AppoTech Ltd 73 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 10 4 ODCON Open drain Output Control Register
4. ODCON Address 5 4 3 2 1 0 POR Default Open drain Output Control General part PBODS PBOD4 GPR5 PBOD2 PBOD1 PBODO 0000 0000 Register 0x0C RW RW RW RW RW RW Bit Bit Name Mode Description 7 6 Reserved 5 PBOD5 R W PB5 open drain control 1 Enable open drain output 0 Disable open drain output 4 PBOD4 R W PB4 open drain control 1 Enable open drain output 0 Disable open drain output 3 GPR5 R W General purpose register 2 PBOD2 R W PB2 open drain control 1 Enable open drain output 0 Disable open drain output 1 PBOD1 R W PB1 open drain control 1 Enable open drain output 0 Disable open drain output 0 PBODO R W open drain control 1 Enable open drain output 0 Disable open drain output APG013 UM 100 EN 74 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Register 10 5 PUPCON Internal Weak Pull up Control Register PUPCON Address 5 4 3 2 1 0 POR Default Internal Weak Pull up General part PBPUP PBPUP GPR6 2 PBPUP PBPUP 1111 1111 Control Register OxOD 4 1 RW RW RW RW RW RW Bit Bit Name Mode Description 7 6 Reserved 5 PBPUP5 R W 5 internal pull up control 1 Disable internal weak pull up 0 Enable internal weak pull up 4 PBPUP4 R W PB4 internal pull up control 1 Disable internal weak pull up 0 Enable internal weak pull up 3 GPR5 R W General purpose register 2 PBPUP2 R W PB
5. Chapter8 Timer1 Timer1 is an 8 16 bit timer counter Timer1 supports 2 operating modes Timer modeCascade mode In addition TimerO and timer1 can work together in cascade mode to form a 24 bit timer counter Figure 8 1 Timer1 function block diagram Instruction cycle Overflow from TimerO In timer 1 there is no prescaler There are 3 registers for timer1 TTCON T1CNT and T1PR T1CNT and T1PR are written for the LSB first and then write for the MSB The same procedure should be applied for the reading operation to the MCU Writing to TTCNT and In 16 bit mode T1 will be automatically toggled to MSB LSB after writing to LSB MSB The counter will be updated after writing MSB Writing will only be correct if LSB is read written first and then MSB In 8 bit mode T1 IDX toggle function is disabled The 8 bit or 16 bit mode can be set in 15 T1CON register bit Cascade mode TimerO be cascaded with timer1 to form a 24 bit timer counter by setting T1SIZE and T1CS1 to 1 APG013 UM 100 EN 66 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Register 8 1 T1CNT Timer1 Counter Register T1CNT Address 7 5 4 3 2 1 0 POR Default Timer1 Counter Register General part T1CNT XXXX XXXX 0x07 RW RW RW RW RW RW RW RW Bit Bit Name Mode Description 7 0 T1CNT RW Timer1 Counter 16 bit mode Write 19t byte for the LSB of Timer1 Counter and w
6. Register 2 3 PCL PC Low Byte Register 013 has a 10 bit wide Program Counter PC and five levels hardware push pop PC stack The low byte of PC is called PCL PC 9 8 bits are not directly readable or writable As a program instruction is executed the PC will contain the address of the next program instruction to be executed The PC value is increased by one every instruction cycle unless an instruction changes PC For a JMP instruction the new PC value is provided by the JMP instruction word For a CALL instruction PC 1 will be pushed into the Top of PC STACK TOS The new PC value is provided by the CALL instruction word For interrupt condition PC 1 will be pushed into the Top of STACK TOS The new PC value is provided by interrupt vector For a RET RETI or RETW instruction the new PC value is popped from TOS If a RET RETI or RETW executed after all data in PC STACK have been popped out PC will be forced to stack over vector 0x003 For any instruction where the PCL is the destination PC 7 0 is provided by the instruction word or ALU result And PC 9 8 is either remain unchanged or clear to zeros that depends on the smart option PCHSEL These instructions need 2 system clock cycles to execute APG013 UM 100 EN 20 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL When 2 bit 7 READ SMART is set to 1 it can use the CALL instruction to jump to the location in
7. USER MANUAL Register 7 1 Timer0 Counter Register TOCNT Address 7 6 5 4 3 2 1 0 POR Default TimerO Counter Register General part TOCNT 0000 0000 0x01 RW RW RW RW RW RW RW RW Bit Bit Name Mode Description T 0 TOCNT R W Timer0 Counter When TOCNT equals to TOPR and TOEN 1 TOCNT will be cleared and TOIF will be set Register 7 2 TOPR Timer0 Period Register TOPR Address 7 6 5 4 3 2 1 0 POR Default TimerO Period Register Extended part TOPR 1111 1111 0x0D RW RW RW RW RW RW RW RW Bit Bit Name Mode Description T 0 TOPR R W 0 Period Register 7 3 TODUTY Timer0 PWM Mode Duty Width Register TODUTY Address 7 6 5 4 3 2 1 0 POR Default TimerO PWM Mode Duty Extended part TODUTY XXXX XXXX Width Register 0x0C RW RW RW RW RW RW RW RW Bit Bit Name Mode Description T 0 TODUTY R W Timer0 PWM Mode Duty Width TODUTY_BUF will be updated from TODUTY when TOEN 1 or TOCNT equals to TOPR 2011 AppoTech Ltd 59 APG013 UM 100 EN Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Register 7 4 TimerO Control Register TOCON Address POR Default TOMO DE TimerO Register Extended part 0x01 TOEN TOCS TOSE PSA PS2 PS1 PSO 0111 1111 RAN R W RW RW RW RW RW RW Bit Bit Name Mode Description TOMODE Timer0 mode selection bit 1 TimerO works PWM
8. For the difference between devices or pins the Vu are different so all the design should refer to the actual criterion 7 Testing Temperature 259 11 3 Data Retention Characteristics in SLEEP Mode Table 11 2 Data retention characteristics in idle mode parameters Symbol Descriptions Min Typ Max Unit Conditions Data retention supply voltage 0 5 V SLEEP mode 25 Figure 11 1 Data retention supply voltage timing lt SLEEP Mode J at Data Retention Mode gt gt Execution of SLEEP Instruction 11 4 AC Characteristics Table 11 3 AC parameters Symbol Descriptions Min Typ Max Unit Conditions 1 MHz Vpp 2 2V Fore ee Core Operating _ 4 MHz 3 3V requency 7 5 MHz 3 6 Ta 25 C APG013 UM 100 EN 84 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 11 5 Oscillator Characteristics Table 11 4 Oscillators parameters Symbol Descriptions Clock Circuit Conditions Min Typ Max Unit 20 100 kHz n XIN External crystal 0 1 1 MHz oscillator GJ a APGO013 1 7 5 MHz External RC oscillator 20 4000 kHz APG013 RCSEL 11 8 MHz RCSEL 10 4 MHz Internal RC oscillator RCSEL 01 1 MHz RCSEL 00
9. Status Affected None Description Interrupt subroutine call First return address PC 1 is pushed onto the stack The address k is loaded into PC GIE is cleared Cycles 2 SLEEP Enter SLEEP mode Operation 0x00 gt WDTCNT 0x00 gt WDT postscaler If assigned 1 gt 0 gt PD_ Status Affected TO_ PD_ Description Time out status bit is set The power down status bit PD is cleared The WDTONT and its postscaler are cleared The processor is put into SLEEP mode Cycles 1 SUBK k Subtract W from immediate Operands 0 lt k lt 0xFF Operation k W gt W Status Affected C DC Z Description Subtract the data of the W register from the 8 bit immediate k The result is stored in W register Cycles 1 SUBR R W Subtract W from R Operands 0 lt R lt 0x3F Operation R W gt R Status Affected C DC Z Description Subtract the data of the W register from the data of R register The result is 2011 AppoTech Ltd 37 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL stored in R register Cycles 1 SUBWR W Subtract W from R Operands 0 lt R lt 0x3F Operation R W gt W Status Affected C DC Z Description Subtract the data of the W register from the data of R register The result is stored in W register Cycles 1 SWAP W R Swap nibbles in R Operands 0 lt R lt 0x3F Operation R 7 4 gt W 3 0 R 3 0 gt W 7 4 S
10. uuuu uuuu juuuu uuuu uuuu uuuu dddd dddd dddd dddd 1 XXXX XXXX uuuu uuuu juuuu uuuu uuuu uuuu uuuu uuuu dddd dddd PCON1 10xx 0x00 10xx 0x00 10xx 0x00 10xx 0x00 uuuu uuuu uuuu uuuu PBWAK 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 141 1111 118141 11 11119111 1111 1111 uuuu uuuu uuuu uuuu PDNCON 1111 1111 1111 1111 1 2 2 1 1 1 7 2 uuuu uuuu uuuu uuuu ODCON 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu PUPCON 1111 1111 1111 1111 1111 1111 uuuu uuuu uuuu uuuu INTEN 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu INTF 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu CLKCON 000 0000 000 0000 x000 0000 x000 0000 uuuu uuuu uuuu uuuu TOCON 0111 1111 0111 1111 0111 1111 0111 1111 uuuu uuuu uuuu uuuu T1CON 00xx 0x00 00xx 0x00 00xx 0x00 00xx 0x00 uuuu uuuu uuuu uuuu INVCON xx00 0000 00 0000 00 0000 00 0000 uuuu uuuu uuuu uuuu 2011 AppoTech Ltd 17 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Rev 1 0 0 USER MANUAL PCON2 0000 x010 0000 x010 0000 010 10000 010 uuuu uuuu uuuu uuuu PBDIR 1111 1111 1111 1111 T3 pp Ti 1111 1111 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu TODUTY XXXX XXXX uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TOPR 1111 1111 1111 1111 1114 1114 TETIE LTTT uuuu uuuu uuuu uuuu Legend x unknown sta
11. ANDWk AND immediate with W Operands 0 lt k lt OxFF Operation W AND k gt W Status Affected 2 Description The contents of the W register are AND ed with 8 bit immediate k The result is stored in the W register Cycles 1 APG013 UM 100 EN 26 2011 AppoTech Ltd Rey 1 00 APG013 8 bit RISC Microcontroller USER MANUAL BC R b Clear bit in R Operands 0 lt R lt 0x3F 0 lt lt 7 Operation 0 gt R b Status Affected None Description Clear bit in register R Cycles 1 BS R b Set Bit in R Operands 0 lt R lt 0x3F 0 lt lt 7 Operation 12 R b Status Affected None Description Set bit b in register R Cycles 1 CALL k Subroutine call Operation PC 1 gt TOP of Stack k gt PC Status Affected None Description Subroutine call First return address PC 1 is pushed onto the stack The 10 bit immediate address is loaded into PC Cycles 2 CLR R Clear R Operation 0x00 gt R 1 gt Z Status Affected 2 Description The contents of register R are cleared and the Z bit is set Cycles 1 2011 AppoTech Ltd 27 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL CLRW Clear W Operands None Operation 0x00 gt W 1 gt Z Status Affected 2 Description The contents of register W are cleared and the Z bit is set Cycles 1 CLRWDT Clear Watchdog timer Operands None Operation 0x00 gt WDTCNT 0x00 gt WDT postscale
12. Symbol Description R General part data memory address ER Extend part data memory address W Working register b Bit address k Literal field Register bit field gt Assign to Table 3 2 013 instruction set Mnemonic Cycles Opcode Description 2 DC C NOP 1 0 0000 0000 0000 No operation DAA 1 0 0000 0000 0001 Decimal Adjust after addition SLEEP 1 0 0000 0000 0011 Enter SLEEP mode 0 WDTCNT IDLE 1 0 0000 0000 1000 Enter IDLE mode 0 gt WDTCNT CLRWDT 1 0 0000 0000 0100 0 gt WDTCNT RET 2 0 0000 0001 0010 TOS gt PC RETI 2 0 0000 0001 0011 TOS gt PC 1 gt GIE SINT k 2 0 0000 0001 01kk PC gt TOS K gt PC 0 gt GIE EXT W ER 1 0 0000 0010 rrrr ER gt W EXTER W 1 0 0000 0011 rrrr W gt 1 0 0000 01 rr rrrr W gt CLRW 1 0 0000 1000 0000 0 gt W APG013 UM 100 EN 22 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL CLRR 1 0 0000 11rr rrrr 0 gt SBOWR W 1 1 1110 10rr rrrr R W gt W SBCRR W 1 1 1110 11rr rrrr R W gt R i SUBWR W 1 0 0001 00rr rrrr R W gt W SUBRR W 1 0 0001 01rr rrrr R W gt R E ji DECW R 1 0 0001 10rr rrrr R 1
13. result 0 BC R b 1 0 100b bbrr rrrr 0 gt R b BSR b 1 0 101b bbrr rrrr 1 gt R b 1 2 0 110b bbrr rrrr Skip next instruction if R b 0 JBSR b 1 2 0 111b bbrr rrrr Skip next instruction if R b 1 CALL k 2 1 00 PC gt TOS gt PC 2 1 01 gt MOVW 1 1 1000 K gt W ORWk 1 1 1001 kkkk kkkk K W gt W ANDW 1 1 1010 K amp W gt W T 2011 AppoTech Ltd 23 APGO013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL XORW k 1 1 1011 kkkk kkkk gt W RETW 2 1 1100 kkkk kkkk K gt W TOS gt PC SUBK k 1 1 1101 kkkk kkkk W gt W ADCW R 1 1 1110 00rr rrrr R W C gt W S ADC R W 1 1 1110 01 rr rrrr R W C gt R ii ADDW 1 1 1111 K W gt W i i affected unaffected flag APG013 UM 100 EN 24 2011 AppoTech Ltd Rev 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 3 2 Instruction description W R Add W and with Carry Operands 0 lt R lt 0x3F Operation W R C gt W Status Affected C DC Z Description Add the contents of the W register and register R with Carry The result is stored in the W register Cycles 1 ADC R W Add W and R with Carry Operands 0 lt R
14. 100 EN 40 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 0 INTEDGO R W External interrupt 0 edge select bit 0 Interrupt on falling edge of INTOB pin 1 Interrupt on rising edge of INTOB pin 2011 AppoTech Ltd 41 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 4 2 PCON2 Power Control 2 Register Fsys System Frequency is lesser than PCON2 Address 7 6 5 4 3 2 1 0 POR Default Power Control 2 Register Extended part READ PWRSA SCLKSEL 1 0 WDTEN 2 0 0000 x010 0x04 SMART VE RW RW RW RW RW RW RW Bit Name Mode Description 7 READ SMART R W Read Smart ID Set this bit to 1 Use CALL to jump to the location in the smart option Use RETW to read in the smart option table to return a byte This bit will be cleared automatically after execution of RETW 6 PWRSAVE R W Power Saving 1 Power Saving Enable 0 Power Saving Disable 5 4 SCLKSEL 1 0 R W Slow Clock Selection These two bits control the divider of 32KHz XOSC 00 32KHz 01 16KHz 10 8KHz 11 4KHz 3 amp 2 2 0 WDTEN 2 0 R W Watchdog Timer Enable These three bits work together with WDTEN 3 PCON1 to form WDTEN 3 0 See previous page When WDTEN 3 0 0101 it will turn off watchdog timer if it is turned on by the smart option WDTCEN Other setting will turn on watchdog timer if the smart opti
15. 4 LVD SEL 1 Vivos LVD4 Flag Trigger Voltage 2 8 LVD_SEL 1 Ta 25 C Note 1 Vpor and are the start voltages to ensure POR circuit work which generates the internal Power on Reset signal 2 Vivorv is the LVD Out Reset Voltage 2011 AppoTech Ltd 87 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bern USER MANUAL Figure 11 3 LVR reset timing VDD VLVR APG013 UM 100 EN 88 2011 AppoTech Ltd Rev 10 0 APG013 8 bit RISC Microcontroller USER MANUAL Chapter 12 Package Dimensions 12 1 8 pin DIP MILLIMETER SYMBOL MIN NOM MAX A 3 60 3 80 4 00 A1 0 51 mE EN A2 3 00 3 30 3 40 A3 1 55 1 60 1 65 b 0 44 0 53 HIE b1 0 43 0 46 0 48 bJ CR L B1 1 52 BSC e c 0 25 __ 0 31 c1 0 24 0 25 0 26 D 9 05 9 25 9 45 E E1 6 15 6 35 6 55 E1 e 2 54 BSC eA 7 62 BSC Section B B eB 7 62 NN 9 30 eC 0 m 0 84 L 3 00 G __ PDIPOO8L 2011 AppoTech Ltd 89 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL 12 2 8 pin SOP MILLIMETER 1 27 BSC 1 05 BSC SOP8L APG013 UM 100 EN 90 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Appendix Revision History Date Version Comment Revised by 2011 05 26 1 0 0 First Release Raymond Ho The information in this doc
16. APGO13 UM 100 EN Appotech 13 8 bit RISC Microcontroller User Manual Rev 1 0 0 May 2011 AppoTech Limited Add Unit 705 707 7 F IC Development Ctr No 6 Science Park West Ave Hong Kong Science Park Shatin N T HK Tel 852 2607 4090 Fax 852 2607 4096 www appotech com APG013 8 bit RISC Microcontroller CPU 8 bit RISC CPU core e Maximum 7 5 MIPS Instruction Set 43 instructions Most instructions need 1 system clocks to execute Branch instructions need 1 or 2 system clocks to execute Memory 64 byte SRAM 1K x 13 bit internal OTP program memory 10 byte user ID Interrupt Sources hardware interrupt sources 1 software interrupt instruction 5 level hardware stacks UO Ports 5 programmable digital I O 1 input port Programmable internal weak pull up resistor Programmable internal weak pull down resistor Programmable open drain output 0 One general purpose 8 bit timer Timer mode Counter mode PWM mode 8 bit programmable prescaler Timer1 One general purpose 8 16 bit timer Timer mode Cascade mode Watchdog Timer WDT CLRWDT instruction to clear WDT counter Programmable postscaler Programmable overflow timer Oscillation Sources External RC oscillator ERC High Frequency Crystal Resonator Oscillator HF Crystal Resonator Oscillator XT Internal
17. LVDL3 24V LVR LVDL4 2 7V LVR The power on reset is at 1 8V SEL 1 or2 2V LVD SEL 0 The built in LVD is controlled by LVD SEL Smart Option 0 bit 7 The LVD flags are located at the CLKCON register The LVD module is always enabled for power on reset and Brown Out reset The LVD2 LVD3 and LVDA include LVD reset function and flag function to indicate VDD status function L VD flags function can be used as an simple low battery detector For low battery detection application check only LVD2 LVD3 and LVD4 status on battery status Register 4 3 Clock Control Register CLKCON Address 7 6 5 4 3 2 1 0 POR Default Clock Control Register Extended part 5 LVD4 LVD3 LVD2 WDTFL SPEED COUTS COUTS xx00 00xx 0 00 AG EL1 ELO RO RO RO RO RW RW RW Bit Bit Name Mode Description 7 Reserved 6 LVD4 RO LVD4 operating flag 0 VDD gt 2 7V 1 VDD lt 2 7V 5 LVD3 RO LVD3 operating flag 0 VDD gt 2 4V 1 VDD lt 2 4V 4 LVD2 RO LVD2 operating flag 0 VDD gt 2 2V 1 VDD lt 2 2V APG013 UM 100 EN 44 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 3 WDTFLAG RO WDT time out indication Valid with WDTSEL 0 0 No time out 1 WDT time out had occurred This bit will be cleared when executing SLEEP IDLE or CLRWDT instruction 2 SPEED R W
18. RW RW Bit Bit Name Mode Description GIE R W Global interrupt enable bit 0 Disable all interrupts For wake up from SLEEP mode through an interrupt event APG013 will continue execution the instruction next to the SLEEP instruction 1 Enable all un masked interrupts For wake up from SLEEP mode through an interrupt event APG013 will branch to the interrupt address 0x008 R W General purpose register THE R W Timer1 overflow interrupt enable bit 0 Disable timer1 overflow interrupt 1 Enable timer1 overflow interrupt Reserved INT1IE R W External interrupt 1 enable bit 0 Disable external interrupt 1 Enable external interrupt INTOIE R W External interrupt 0 enable bit 0 Disable external interrupt 1 Enable external interrupt 1 PBIE R W Port B input change interrupt enable bit 0 Disable port B input change interrupt 1 Enable port B input change interrupt APG013 UM 100 EN 54 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 0 TOIE R W 0 overflow interrupt enable bit 0 Disable timerO overflow interrupt 1 Enable timerO overflow interrupt and set GIE bit to re enable interrupt Note When an interrupt event occurs or after SINT instruction GIE bit will be cleared by hardware to disable any further interrupts The RETI instruction will exit the interrupt routine 2011 AppoTech Ltd 55
19. VDD 3 3V Supply current SLEEP mode 3 2 JUA VDD 3 6 KEE 2 8 ua VDD 3 3V InputLow Voltage 0 3 VDD IN Vpp7 3 3V Input High Voltage 0 7 VDD Vo 3 3V Vo Output Low Voltage 0 4 lou 8mA 3 3V Output High Voltage 2 5 lou 8mA 3 3V lwr current 3 UA Vop 3 3V Re Internal pull up resistor 60 kO l Rep Internal pull down resistor 120 kO l Notes 1 lee is the supply current when device works It is mainly a function of the operating voltage and frequency Other 2011 AppoTech Ltd 83 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Rer USER MANUAL affecting factors include pin loading and switching rate oscillator type internal code execution pattern and temperature 2 CLKDIV is the system clock division setting It can be set in Smart Option 1 bits 7 6 Please refer to Section 2 3 for detailed descriptions 3 Joe is the supply current when the device is IDLE mode 4 is the supply current when the device is in SLEEP mode At this mode the oscillator stops 5 Input low voltage Vi is the threshold voltage read as logic 0 Higher than Vi may not read as 0 For the difference between devices or pins the are different so all the design should refer to the actual criterion 6 Input high voltage is the threshold voltage read as logic 1 Lower than may not read as 1
20. continue executing instruction after wake up 6 3 Timer1 interrupt When T1CNT is equal to T1IF will be set This interrupt can be disabled by clearing T1IE bit The Timer1 interrupt can wake up the system from IDLE condition if T1IE was set before going to IDLE mode If GIE bit was set the program will execute interrupt service routine after wake up or if GIE bit was cleared the program will continue executing instruction after wake up 6 4 Port B input change interrupt An input change on Port B set PBIF This interrupt can be disabled by clearing PBIE bit Before the Port B input change interrupt is enabled executing TEST PBDATA instruction is needed Any pin with the corresponding PBWAK bit cleared when the instruction is executed will be excluded from this function The corresponding pin must be set as input If PBO pin is configured as INTOB pin PBO will be excluded from this function After input change interrupt is triggered new input change interrupt can only be triggered after all corresponding pin return to the state when TEST instruction is executed or after a new TEST PBDATA instruction is executed Port B input change interrupt can also wake up the system from SLEEP or IDLE mode if bit PBIE was set before going to SLEEP or IDLE mode And GIE bit also decides whether or not the processor branched to the interrupt vector after wake up If GIE bit was set the program will execute interrupt service routine after w
21. set Wake up is regardless of GIE bit If GIE bit is cleared the device will continue execution at the instruction after the IDLE or SLEEP instruction If the GIE bit is set the device will branch to the interrupt address 0x008 In XOSC IRC or ERC mode the system wake up delay time from SLEEP mode is 2 25ms 4 5ms 18ms 72ms 288ms or 17 5us defined by PORSEL If the option WDTSEL is set zero WDT will not reset the system after 1 wake up from SLEEP mode but will set the WDTFLAG in the CLKCON If this bit is not clear after 274 wake up from SLEEP will reset the system WDTFLAG can be cleared by SLEEP IDLE or CLRWDT instruction If the option WDTSEL is set to one WDT will always reset the system after wake up from SLEEP mode APG013 UM 100 EN 50 2011 AppoTech Ltd APG013 8 bit RISC Microcontroller USER MANUAL Table 5 1 RST TO PD status after Reset or Wake up RESET was caused by Power on reset RSTB reset during normal operation RSTB reset during SLEEP or IDLE mode WDT reset during normal operation WDT wake up during SLEEP or IDLE mode Wake up on pin change during SLEEP or HDEE mode Legend unchanged Table 5 2 Events affecting TO PD status bits Event Power on WDT time out SLEEP or IDLE instruction CLRWDT instruction Legend unchanged Note 1 When the clock runs slower than WDT the timer out period will probably be longer th
22. will be set when equals to TOPR Figure 7 2 Timer mode timing Without prescaler 0xA9 Fsys CPU write OxAO to Write l toont ono TOIF 7 2 Counter mode Counter mode is selected by setting the TOCS bit and clearing TOMODE bit In counter mode TOCNT will increase on every rising or falling selected by TOSE bit edge of pin TOCK PSA 1 or every prescaler overflow PSA 0 Prescaler will increase either on every rising or falling selected by TOSE bit edge of pin TOCK if it is assigned to timerO The external clock requirement is due to internal phase clock synchronization Also there is a delay in the actual incrementing of timerO after synchronization When no prescaler is used the external clock input is the same as the prescaler output It is necessary for TOCK to have a period of at least 4 1 Fosc divided by the prescaler value will be cleared when TOCNT equals to TOPR PB2 must be set as input when TimerO works in counter mode APG013 UM 100 EN 62 2011 AppoTech Ltd SSC APG013 8 bit RISC Microcontroller USER MANUAL Figure 7 3 Counter mode timing Without prescaler 0xA4 wa EE Si Su CPU write OxAO to TOCNT l TOPR Write TOCNT 7 3 PWM mode PWM mode is sele
23. 0 gt WDTCNT 0x00 gt WDT postscaler If assigned 1 gt 0 gt PD_ Status Affected TO_ PD_ Description Time out status bit TO_ is set The power down status bit PD_ is cleared The WDTCNT and its postscaler are cleared 013 is put into IDLE mode Cycles 1 APG013 UM 100 EN 30 2011 AppoTech Ltd RSR APG013 8 bit RISC Microcontroller USER MANUAL IJZ W R Increment R Skip if 0 Operands 0 lt R lt 0x3F Operation R 1 gt W skip if result 0 Status Affected None Description The contents of register R are incremented The result is stored W register If the result is 0 then the next instruction which is already fetched is discarded and a is executed making it a two cycle instruction Cycles 1 2 IJZ R Increment R Skip if 0 Operands 0 lt R lt eis Operation R 1 gt R skip if result 0 Status Affected None Description The contents of register R incremented The result is stored in R register If the result is 0 then the next instruction which is already fetched is discarded and a NOP is executed making it a two cycle instruction Cycles 1 2 INC Increment Operands 0 lt R lt 0x3F Operation 1 gt W Status Affected 2 Description The contents of register R are incremented The result is stored W register Cycles 1 INC R Increment R Operands 0 lt R lt 0x3F Oper
24. 00 EN 32 2011 AppoTech Ltd Rey 1 00 APG013 8 bit RISC Microcontroller USER MANUAL Operation W gt R Status Affected None Description Load R register with W register Cycles 1 MOV W R Load W register with R register Operands 0 lt R lt 0x3F Operation R gt W Status Affected None Description Load W register with R register Cycles 1 MOVW k Move immediate to W Operands 0 lt k lt 0xFF Operation k gt W Status Affected None Description The 8 bit immediate k is loaded into the W register Cycles 1 NOP No operation Operands None Operation No operation Status Affected None Description No operation Cycles 1 OR OR W with R Operands 0 lt R lt 0x3F Operation W or R gt W Status Affected 2 Description Inclusive OR the W register with register with register R The result is stored in W register 2011 AppoTech Ltd 33 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Recte USER MANUAL Cycles 1 OR RW OR W with R Operands 0 lt R lt 0x3F Operation Wor R gt R Status Affected 7 Description Inclusive OR the W register with register with register R The result is stored in R register Cycles 1 ORW k OR immediate with W Operands 0 lt k lt 0xFF Operation WOR k gt W Status Affected Z Description Inclusive OR the W register with register with 8 bit immediate k The result is stored in W register Cycles
25. 1 RET Return from Subroutine Operation TOP of Stack gt PC Status Affected None Description The program counter is loaded from the top of the stack the return address Cycles 2 RETI Return from Interrupt Set GIE bit Operation TOP of Stack gt PC 1 gt Status Affected None Description The program counter is loaded from the top of the stack the return address The APG013 UM 100 EN 34 2011 AppoTech Ltd Rey 1 00 APG013 8 bit RISC Microcontroller USER MANUAL GIE bit is set to 1 Cycles 2 Return with immediate in W Operands 0 lt k lt 0xFF Operation k gt W Top of Stack gt PC Status Affected None Description The W register is loaded with the 8 bit immediate k The program counter is loaded from the top of the stack the return address Cycles 2 RLC W R Rotate left R through Carry Operands 0 lt R lt 0x3F Operation C gt RI C R 6 0 gt W 7 1 Status Affected C Description The contents of register R are rotate one bit to the left through the Carry flag The result is stored in the W register Cycles 1 RLC R Rotate left R through Carry Operands 0 lt R lt 0x3F Operation C gt R 7 gt C R 6 0 gt R 7 1 Status Affected C Description The contents of register R are rotate one bit to the left through the Carry flag The result is stored in the R register Cycles 1 RRC W R Rot
26. 2 internal pull up control 1 Disable internal weak pull up 0 Enable internal weak pull up 1 PBPUP1 R W PB1 internal pull up control 1 Disable internal weak pull up 0 Enable internal weak pull up 0 PBPUPO R W PBO internal pull up control 1 Disable internal weak pull up 0 Enable internal weak pull up 2011 AppoTech Ltd 75 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 10 6 PDNCON Internal Weak Pull down Control Register PDNCON Address 7 5 4 3 2 1 0 POR Default Internal Weak Pull down General part GPR4 PBPDN PBPDN PBPDN 1111 1111 Control Register 0x0B 1 0 RW RW RW RW Bit Bit Name Mode Description 7 GPR4 R W General purpose register 6 PBPDN2 R W PB2 pull down control 0 Enable internal weak pull down 1 Disable internal weak pull down 5 PBPDN1 R W PB1 pull down control 0 Enable internal weak pull down 1 Disable internal weak pull down 4 PBPDNO R W PBO pull down control 0 Enable internal weak pull down 1 Disable internal weak pull down 3 0 Reserved APG013 UM 100 EN 76 2011 AppoTech Ltd APG013 8 bit RISC Microcontroller USER MANUAL Figure 10 1 PB0 PB1 function diagram Not include open drain function Analog In INTEDG Ext INT INTOIE INT1IE PBIE C Pul Schmit Register CPU read RDPORT 2011 AppoTech Ltd 77 APG013 UM 100 EN APG01
27. 3 8 bit RISC Microcontroller Rer USER MANUAL Figure 10 2 PB2 function diagram Not include open drain function PUP IO INT Register PBIE CPU read APG013 UM 100 EN 78 2011 AppoTech Ltd Rey 1 00 APG013 8 bit RISC Microcontroller USER MANUAL Figure 10 3 PB3 function diagram VDD 100 Q Analog In C PUP RSTBEN o F CPU read 50K Register IO INT lt Data In Schmitt Figure 10 4 PB4 and PB5 function diagram Not include open drain function 100 Q TT PUP gt o d CPU read Register C IO INT C lt PBIE Schmitt lt Data In i ET l gt PBS RDPORT PX O DIR IL DATA 2011 AppoTech Ltd 79 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL Figure 10 5 Open drain output diagram Pull up resister Other circuit APG013 APG013 UM 100 EN 80 2011 AppoTech Ltd SS APG013 8 bit RISC Microcontroller USER MANUAL 10 2 Inverter output PB1 supports inverter output mode PB1 must be configured as output when inverter output function is enabled If PB1INVEN 1 PB1 normal I O function is disabled by hardware automatically But PBDIR 1 must be cleared to enable inverter output function Register 10 7 INVCON Inver
28. 3 RSTB Input only port System wakeup System reset PB4 XOUT Bidirectional input output port System wakeup System clock output Configurable weak pull up resistor Configurable open drain output XOSC clock output 2011 AppoTech Ltd 7 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Rev 1 0 0 USER MANUAL PB5 XIN I O Bidirectional input output port System wakeup Configurable weak pull up resistor Configurable open drain output External clock input XOSC clock input VDD Power Positive power supply VSS Ground Negative power supply Ground APG013 UM 100 EN 2011 AppoTech Ltd Bes APG013 8 bit RISC Microcontroller USER MANUAL Chapter 2 Memory Organization 2 1 Program memory organization APGO013 has a 10 bit program counter PC capable of addressing 1K x 13 bit program memory space The address range is 0 000 to There is an extra ID space for smart options and user region Smart options range from 0 0 to 0x1 address from 0 2 to 0x5 is reserved The address fromO0x6 to OxF is user ID region The reset vector is 0 000 PC stack over vector is 0x003 Hardware interrupt vector is 0 008 Figure 2 1 APG013 program memory space 10 bit PC Smart option 0 Smart option 1 User ID region Ox3FF 21 2011 AppoTech Ltd 9 APG013 UM 100 EN APG013 8 bit RISC Microcontr
29. 3 UM 100 EN Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Figure 2 3 APG013 Data Memory APG013 Memory Accessed by EXT Accessed by MOV 16 5 OxOF Ox2F Bank 0 Bank 1 Bank 0 Bank 1 SE 1 16 5 Bytes APGO013 data memory space is partitioned into two parts SFR Special Function Registers and SRAM SFR is special registers reserved for CPU core and peripheral usage It is divided into general part and extend part The general part can be accessed either directly or indirectly through the File Select Register FSR The extend part can only be accessed by EXT instruction The Special Function Registers are used by CPU core and peripherals for controlling the desired operation of the device The Special Function Registers can be classified into two sets CPU core and peripheral Those registers associated with the CPU core functions are described in this section and those related to the operation of the peripheral features are described in the section of that peripheral feature SRAM can be used as data storage for user program APG013 UM 100 EN 14 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Table 2 3 APG013 data memory space Table 2 4 Address General Part Extend part 0x00 INDF CLKC
30. 4 5 ms x110 Power on delay time is 18 ms SLEEP mode wake up delay time is 18 ms x101 Power on delay time is 72 ms SLEEP mode wake up delay time is 72 ms x100 Power on delay time is 288 ms SLEEP mode wake up delay time is 288 ms 0011 Power on delay time is 2 25 ms SLEEP mode wake up delay time is 17 5us 1011 Power on delay time is 4 5 ms SLEEP mode wake up delay time is 17 5us x010 Power on delay time is 18 ms SLEEP mode wake up delay time is 17 5 us x001 Power on delay time is 72 ms SLEEP mode wake up delay time is 17 5 us x000 Power on delay time is 288 ms SLEEP mode wake up delay time is 17 5 us LVD SEL LVD select APG013 UM 100 EN 10 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 0 LVD will reset chip if VDD is below 2 2V LVD2 flag is not valid LVD3 will set 1 to indicate VDD lt 2 4V LVD4 will set 1 to indicate VDD lt 2 7V The system will release from reset if VDD is above 2 3V 1 LVD will reset chip if VDD is below 1 8V LVD2 will set 1 to indicate VDD 2 2V LVD3 will set 1 to indicate VDD lt 2 4V LVD4 will set 1 to indicate VDD lt 2 7V The system will release from reset if VDD is above 1 9V PCHSEL PC 9 8 select 1 PC 9 8 will remained unchanged when executing any instructions related to PC 0 PC 9 8 will clear to zero when executing any instructions related to PC PB4CLKO PB4 XOUT pin select 1 PB4 is selec
31. 455 kHz Internal RC variation Vpp 3 3V Ta 25 C 3 Yo Ta 25 C Table 11 5 Capacitor values for external crystal oscillator Loading capacitor C1 C2 Crystal Oscillator Frequency 15p 20 100kHz 30p 100kHz 7 5MHz 2011 AppoTech Ltd 85 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL Table 11 6 RC values for External RC oscillator Rext Cext XIN Freq 10k 100p 846KHz 100k 300p 31 3KHz 1 The frequency drift has a variation of 30 2 The values are only for design reference 11 6 Reset Characteristics Table 11 7 POR Characteristics Symbol Parameter Min Typ Max Unit Condition 2 LVD_SEL 1 POR trigger voltage 24 LVD SEL 0 RSTB low pulse width 50 fus lreset Current under reset 160 uA 0 Ta 25 C APG013 UM 100 EN 86 2011 AppoTech Ltd Ke APG013 8 bit RISC Microcontroller USER MANUAL Figure 11 2 POR trigger timing VDD Internal POR Reset i TRISE Table 11 8 LVR Reset Circuit Characteristics Symbol Descriptions Min Typ Max Unit Conditions 1 8 V LVD SEL 1 LVD Out Trigger Voltage 2 2 V LVD SEL 0 LVD2 Flag Trigger Voltage 2 2 LVD SEL 1 Flag Trigger Voltage 2
32. APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 6 2 INTF Interrupt Status Register INTF Address 7 6 5 4 3 2 1 0 POR Default Interrupt Status Register General part TAIF TOIF 0000 0000 OxOF R W RW RW RW RW Bit Bit Name Mode Description 7 6 Reserved 5 R W Timer1 overflow interrupt flag Set when T1CNT equals to T1PR reset by software Write O will clear the interrupt and write 1 will be unchanged 4 Reserved 3 INT1F R W External interrupt 1 flag Set by rising falling edge selected by INTEDG1 on INT1B pin reset by software Write O will clear the interrupt and write 1 will be unchanged 2 INTOIF R W External interrupt 0 flag External interrupt flag Set by rising falling edge selected by INTEDGO on INTOB pin reset by software Write O will clear the interrupt and write 1 will be unchanged 1 PBIF R W Port B input change interrupt flag Port B input change interrupt flag Set when Port B input changes reset by software Write O will clear the interrupt and write 1 will be unchanged 0 TOIF R W 0 overflow interrupt flag TimerO overflow interrupt flag Set when TOCNT equals to TOPR reset by software Write 0 will clear the interrupt and write 1 will be unchanged NOTE 1 Because of synchronization PBIF and INTO 1IF will be cleared one system clock 1 Fsys after the inst
33. AW Timer1 index An index of TTCNT and T1PR write in 16 bit mode T1 IDX will be automatically toggled to MSB LSB after writing to LSB MSB The counter will be updated after writing MSB Writing will only be correct if LSB is read written first and then MSB Refer to Chapter Timer 1 5 GPRO RAW General purpose register 4 TO RO Time out flag 1 Set after power on or by the CLRWDT or SLEEP or IDLE instruction 0 a watchdog time out occurred 3 PD RO Power down flag 1 Set after power on or by the CLRWDT instruction 0 Clear by the SLEEP or IDLE instruction 2 7 RAW Zero bit 1 The result of a logic operation is zero 0 The result of a logic operation is not zero 2011 AppoTech Ltd 19 APG013 UM 100 EN 013 8 bit RISC Microcontroller Rex 0 0 USER MANUAL 1 DC RAN Half carry half borrow bit After addition operation 1 A carry from 4 low order bit of the result occurred 1 A carry from the an low order bit of the result occurred 0 A carry from the 4th low order bit of the result did not occur After subtraction operation 1 A borrow from the low order bit of the result did not occur 0 A borrow from the low order bit of the result occurred 0 C RAN Carrylborrow bit After addition operation 1 A carry occurred 0 A carry did not occur After subtraction operation 1 A borrow did not occur 0 A borrow occurred After rotate operation C contains the shifted out bit
34. E TOEN TOCS TOSE PSA PS 2 0 T1CON EXT 0x02 T1EN TiSIZE T1CS1 CLKSRC 1 0 INVCON EXT 0x03 S PB1INVS Gei e PCON2 EXT 0x04 READ_SMART r SCLKSEL 1 0 WDTEN 2 0 EXT 0x05 S PBDIR EXT 0x06 PBDIR5 PBDIR4 PBDIR2 PBDIR1 PBDIRO EXT 0x07 EXT 0x08 S 0 09 z EXT E EXT 0x0B 2 TODUTY EXT 0 0 TimerO PWM duty width TOPR EXT 0x0D Timero PWM period width undefined APG013 UM 100 EN 16 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Note Reading to undefined space will return 0 Writing to undefined space will result in nothing GPRx stands for General Purpose Register Special function registers reset status is listed below Table 2 7 Special function registers reset value Register Power on LVR reset WDT reset RSTB reset SLEEP Wake IDLE Wake reset up up uuuu uuuu uuuu uuuu juuuu uuuu uuuu uuuu uuuu uuuu INDF XXXX XXXX XXXX XXXX uuuu uuuu uuuu uuuu TOCNT 0000 0000 0000 0000 0000 0000 10000 0000 uuuu uuuu dddd dddd PCL 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu STATUS 0001 1 000u uuuu 0000 uuuu 1000u uuuu uuuu uuuu uuuu uuuu FSR XXXX XXXX uuuu uuuu uuuu uuuu juuuu uuuu uuuu uuuu uuuu uuuu PBDATA XXXX XXXX
35. ON 0x01 TOCNT TOCON 0x02 PCL T1CON 0x03 STATUS INVCON 0x04 FSR PCON2 0x05 0 06 PBDATA PBDIR 0x07 T1CNT 0x08 1 0 09 PBWAK T1PR 0x0B PDNCON 0x0C ODCON TODUTY 0x0D PUPCON TOPR 0x0E INTEN 0x0F INTF 0x10 0x11 SRAM 0x3F Table 2 6 APG013 Register Table Register Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 INDF 0x00 Indirect addressing to general part data memory TOCNT 0x01 Timer0 counter PCL 0x02 PC low byte STATUS 0x03 RST Ti IDX GPRO PD 7 DC 2011 AppoTech Ltd 15 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bey 1 0 0 USER MANUAL FSR 0x04 GPR3 GPR2 INDA 5 0 0x05 PBDATA 0x06 Port B Pin Data Register T1CNT 0x07 8 16 bit Timer counter PCON1 0x08 WDTEN 3 EIS PANKRE INTEDG1 INTEDGO PBWAK 0x09 PBWAK5 PBWAK4 PBWAK3 PBWAK2 PBWAK1 PBWAKO T1PR 8 16 bit period width PDNCON 0 0 PBPDN2 PBPDN1 ODCON 0 0 PBOD5 4 GPR5 PBOD2 1 PBODO PUPCON 0x0D 5 PBPUP4 GPR6 PBPUP2 PBPUP1 PBPUPO INTEN OxOE GIE GPR7 T IE INT1IE INTOIE PBIE TOIE INTF OxOF T1IF INTIIF INTOIF PBIF TOIF CLKCON EXT 0x00 LVD4 LVD3 LVD2 SE SPEED COUTSEL 1 0 TOCON EXT 0x01 TOMOD
36. RC Oscillator External Resistor Internal Capacitor Oscillator ERIC Power on Reset POR Reset at 2V or 2 4V Low Voltage Detector LVD System Reset Voltage monitor Programmable voltage detection indication levels 1 8V 2 2V 2 4V 2 7V Operating Temperature Range 40 C to 85 C Operating Voltage Range 2 2V to 3 6V at 1 MIPS 3 3V to 3 6V at 4 MIPS Package Type 8 DIP SOP DIE form AppoTech Limited Address Unit 705 707 7 F IC Development Centre No 6 Science Park West Ave Hong Kong Science Park Shatin N T Hong Kong Telephone 852 2607 4090 852 2607 4096 www appotech com AppoTech ES SSC APG013 8 bit RISC Microcontroller USER MANUAL Table of Contents Chapter 1 Architecture Overview 222 2 2 6 1 1 Hardware architechure 6 a 2 A AS SIQUIINIG Mee gee eerte ede te biete parece AAA WA es uud eus 6 1 3 EE LL 6 Chapter 2 Memory Organization U 8 2 1 Program memory OrgabilzallQlks acit roce te la ete iau rbd eee ees 8 2 2 ID space and Smart option 9 2 3 Product ID and Check sum words 11 2 4 Data memory OrganiZation TEE 12 Chapter Instruction Set E 21 3 1 Instruction Set summary eot op oae rule tapes tot 21 3 2 Instruction description 24 Chapter 4 Power Up and Reset
37. System speed selection 0 System runs in normal speed mode 1 System runs in low speed mode Refer to Section 5 1 1 0 COUTSEL 1 0 R W Clock output selection These bits are valid when IRC or ERC is selected 00 as normal I O 01 RC clock output Fosc refer to Figure 5 1 to PB4 10 Output divider clock Fdiv refer to Figure 5 1 11 Reserved Note CLKCON 1 0 default will be 00 when PB4 is selected as normal I O When is selected for XOUT CLKCON 1 0 default will be don t care 2011 AppoTech Ltd 45 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Table 4 2 LVD reset options Smart Hardware Software Option LVD SEL Reset Range LVD2 LVD3 LVD4 1 0 1 8 1 when VDD 2 2V 1 when VDD 2 4V 1 when VDD 2 7V 0 0 2 2V N A 1 when VDD 2 4V 1 when VDD 2 7V Table 4 2 describes how to set LVD SEL in Smart Option 0 to control LVD reset functions The following describes the function in each scenario SEL 0 If VDD 2 2V system will be reset LVD2 flag is not available LVD3 flag will output 1 when VDD 2 4V LVDA flag will output 1 when VDD 2 7V SEL 1 If VDD 1 8V system will be reset LVD2 flag will output 1 when VDD lt 2 2V LVD3 flag will output 1 when VDD 2 4V LVDA flag will output 1 when VDD 2 7V Note 1 LVD2 LVD3 LVD4 flags will be updated according to VDD 2
38. The voltage levels of LVD are for design reference only Don t use the LVD indicator as precise VDD measurement 4 2 RSTB and Watchdog Reset A RSTB or WDT wake up from SLEEP or IDLE mode also results in a device RESET and not a continuation of operation after SLEEP or IDLE The and PD_ bits are set or cleared depending on the different reset conditions A power on reset timer PORCNT provides a normal 2 25ms 4 5ms 18ms 72ms or 288ms selected by PORSEL in Smart Option delay after POR LVR RSTB reset or WDT reset The device is kept in reset state as long as the is active The PORCNT delay will vary from device to device due to VDD temperature and process variation APG013 UM 100 EN 46 2011 AppoTech Ltd BORED APG013 8 bit RISC Microcontroller USER MANUAL However a WDT reset occurred under IRC or dual clock mode have a fixed wake up time of 94us A 16 oscillator cycle delay from XIN is provided after the oscillator start timer OSCCNT has started and has overflown when 013 works with external crystal XOSC This delay ensures that the oscillator or resonator has started and stabilized APGO13 is kept in reset state as long as the and 5 are active Figure 4 1 013 reset circuit On Chip 2011 AppoTech Ltd 47 APG013 UM 100 EN 013 8 bit RISC Microcontroller Rev 10 0 USER MANUAL Chapter 5 Clock and Power saving Mod
39. ake up or if GIE bit was cleared the program will continue executing instruction after wake up Refer to Figure 10 1 to 10 6 in Chapter 10 for Port B function diagrams 2011 AppoTech Ltd 57 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL Chapter 7 TimerO TimerO is an 8 bit timer counter TimerO support 3 operating modes Timer mode Counter mode PWM mode Figure 7 1 0 function block diagram TOIF PB2 PWM zm s ar gt gt lt Prescaler 1 2 R TOCON 5 4 256 Eua m uty compare T1CON 1 0 WDTCLK TODUTY BUF Instruction cycle TODUTY TOMODE In timer mode or counter mode the prescaler is assigned to timerO by clearing the PSA bit In this case the prescaler will be cleared when TOCNT is written with a value Assigning prescaler to timerO is not recommended in PWM mode TimerO has 4 registers TOPR TODUTY There is 1 internal buffer TODUTY BUF for TODUTY In PWM mode TODUTY BUF is updated from TODUTY when TOEN 0 or TOCNT equals to TOPR TimerO has external clock sources external input TOCK watchdog input WDTCLK and oscillator input It can be selected in T1CON 1 0 TimerO can be cascaded with timer1 to form a 16 bit or 24 bit timer counter Refer to Section 8 2 Cascade mode for details APG013 UM 100 EN 58 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller
40. an 17 5us The magnitude of discrepancy depends on frequency difference between the clock and WDT 2011 AppoTech Ltd 51 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL 5 3 System clock output Instruction cycle clock Fsys or oscillator clock Fosc can be output to pin There are 3 control bits for this clock output function PBACLKO in smart option COUTSELO and COUTSEL1 in CLKCON register Table 5 3 clock output function control CONTROL BIT Config bit PB4 XOUT pin Function XOSC COUTSEL1 COUTSELO PBACLKO Configuration D x x External crystal XOUT pin Crystal OSC and Dual Oscillator Mode Output RC oscillator clock Fosc after power IRC ERC up Note This setting is only valid after power up After power up if COUTSEL1 and COUTSELO are written the value in PB4CLKO bit will be ignored Normal UO function default Output RC oscillator clock Fosc Output divider clock Fdiv Reserved APG013 UM 100 EN 52 2011 AppoTech Ltd SSC APG013 8 bit RISC Microcontroller USER MANUAL Chapter6 Interrupt APGO013 has up to five sources of hardware interrupt External interrupt INTOB pin External interrupt INT1B pin TimerO overflow interrupt Timer1 overflow interrupt Port B input change interrupt INTF is the interrupt flag register that records the interrupt requests in the corresponding flags A glo
41. ate right R through Carry 2011 AppoTech Ltd 35 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Rev 10 0 USER MANUAL Operands 0 lt R lt 0x3F Operation gt gt C R 7 1 gt W 6 0 Status Affected C Description The contents of register R are rotate one bit to the right through the Carry flag The result is stored in the W register Cycles 1 RRC R Rotate right R through Carry Operands 0 lt R lt 0x3F Operation C gt R 7 R 0 gt C R 7 1 gt R 6 0 Status Affected C Description The contents of register R are rotate one bit to the right through the Carry flag The result is stored in the R register Cycles 1 SBCW R W Subtract W from R with Carry Operands 0 lt R lt Operation R W C gt W Status Affected C DC Z Description Subtract the data of the W register from the data of R register with Carry The result is stored in W register Cycles 1 SBCR RW Subtract W from R with Carry Operands 0 lt R lt Operation R W C gt R Status Affected C DC Z Description Subtract the data of the W register from the data of R register with Carry The result is stored in W register Cycles 1 APG013 UM 100 EN 36 2011 AppoTech Ltd Revd APG013 8 bit RISC Microcontroller USER MANUAL SINT k Software interrupt Operands 0 lt k lt 0x3 Operation PC 1 gt Top of Stack k gt PC 0 gt GIE
42. ation R 1 R Status Affected 7 Description The contents of register R incremented The result is stored in R register Cycles 1 2011 AppoTech Ltd 31 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL JBC R b Test bit in R skip if clear Operands 0 lt R lt 0x3F 0 lt b lt 7 Operation Skip if R b 0 Status Affected None Description If bit b in register R is 0 then the next instruction is skipped If bit b in register R is 0 then next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a 2 cycle instruction Cycles 1 2 JBS R b Test bit in R skip if set Ti w Hr 4 Operands 0 lt R lt 0x3F Osbs7 Operation Skip if R b 1 Status Affected None Description If bit b in register R is 1 then the next instruction is skipped If bit b in register R is 1 then next instruction fetched during the current instruction execution is discarded and a NOP is executed instead making this a 2 cycle instruction Cycles 1 2 Unconditional Branch TF Operands 0 lt k lt 0x3FF Operation k gt PC Status Affected None Description JMP is an unconditional branch The 10 bit immediate value is loaded into PC Cycles 2 MOV R W Load R register with W register Operands 0 lt R lt 0x3F APG013 UM 1
43. bal interrupt enable bit GIE enables if set an un masked interrupts or disabled if cleared all interrupts Individual interrupts can be enabled or disabled through their corresponding enable bits in INTEN register When an interrupt event occur with GIE bit and its corresponding interrupt enable bit are all set the GIE bit will be cleared by hardware to disable any further interrupts and the next instruction will be fetched from address 0x008 The interrupt flag bits must be cleared by software before re enabling GIE bit to avoid recursive interrupts The RETI instruction exits the interrupt routine and set GIE bit to re enable interrupt The flag bit in INTF register is set by interrupt event regardless of the status of its mask bit When a software interrupt is generated by the SINT k instruction the next instruction will be fetched from 0x00k Steps to enable interrupt source 1 Configure corresponding setting 2 Wait at least 2 system clock cycles 3 Clear corresponding interrupt flag 4 Enable interrupt by setting TOIE T1IE PBIE INTOIE or INT1IE to 1 if suitable 2011 AppoTech Ltd 53 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 6 1 INTEN Interrupt Mask Register INTEN Address 3 2 1 0 POR Default GIE Interrupt Mask Register General part 0 0 GPR7 INT1IE INTOIE PBIE TOIE 0000 0000 RAN RAN R W RW RW
44. cted by clearing TOCS bit and setting TOMODE bit PWM waveform will be output to TOPWM PB2 pin A PWM output has a time base period and a timer that the output stays high duty cycle The frequency of the PWM is the inverse of the period Figure 7 4 timing OxAF 2011 AppoTech Ltd 63 APG013 UM 100 EN 013 8 bit RISC Microcontroller SN USER MANUAL Fsys wow Jee eee 0 Kick start PWM TODUTY 0x00 PWM TODUTY 0x01 PWM TODUTY 0x02 PWM T0DUTY 0xAE Low High PWM TODUTY Low High PWM TODUTY gt OxAF The PWM period is specified by writing to the TOPR register The PWM period can be calculated using the following formula PWM period TOPR 1 1 Fsys prescaler value When is equal to TOPR 3 events will happen is cleared TOIF is set PWM duty cycle is latched from TODUTY into TODUTY BUF When is equal to 0x00 TOPWM PB2 pin will output high The PWM logic high period is specified by writing to the TODUTY register The following equation is used to calculate the PWM duty cycle time PWM logic high period TODUTY 1 Fsys prescaler value TODUTY can be written at any time but the duty cycle value is not latched into TODUTY BUF until after TOCNT equals to TOPR This double buffering is essential for glitchless PWM operation Whe
45. e 5 1 System clock source APG013 can be operated in seven different oscillator modes defined by CLKSEL in smart option External RC ERC External crystal XOSC within frequency from 32KHz ELFC External crystal XOSC within frequency from 100KHz to 1MHz LFC External crystal XOSC within frequency from 1MHz to 8MHz External crystal XOSC within frequency from 8MHz to 16MHz HFC Internal RC IRC Dual oscillator 32kHZ XOSC and IRC 5 1 1 Single Oscillator Mode In XOSC mode a crystal or ceramic resonator in connected to the XIN and XOUT pins to establish oscillation When in XOSC mode APG013 can have an external clock source driving the XIN pin The ERC mode offers additional cost saving for timing insensitive applications The RC oscillator frequency is a function of the resistor R and capacitor C the operating temperature and the process parameter The IRC mode offers the largest cost saving for timing insensitive applications APG013 offers 4 different IRC frequencies 8MHz 4MHz 1MHz and 455 Khz In ERC XOSC IRC modes when SPEED is set to 1 Low Speed Mode is enabled i e Fsys Fdiv 16 When SPEED is set to 0 Low Speed Mode is disabled i e Fsys Fdiv Refer to the following Section 5 1 3 5 1 2 Dual Oscillator Mode The Dual Oscillator Mode supports IRC and 32kHz XOSC When SPEED is set to 0 the IRC is used for system clock and the 32kHz XOSC is used for timer0
46. e selection bits 00 External input 01 Oscillator input 10 Watchdog input 11 Reserved Table 8 1 Clock selection summary table Mode Source T1CS1 Timer mode Clock 0 Cascade mode TimerO overflow 1 8 1 Timer mode Timer mode is selected by clearing the T 1 CS0 and T 1CS1 In timer mode T1CNT will increment system APG013 UM 100 EN 68 2011 AppoTech Ltd APG013 8 bit RISC Microcontroller USER MANUAL clock Fsys cycle New value can be written to T1CNT at any time T1CNT will increase from the new value at next count event T1CNT will be cleared and T1IF will be set when T1CNT equals to T1PR Figure 8 2 Timer mode timing 0xA9 Fsys CPU write OxAO to T1CNT we nc 27020040000 Y OxAO Y OxA1 OxA2 OxA3 5 Y OxA7 OxA8 Y OxA9 Y Y Y oxo2 T1IF 8 2 Cascade mode TimerO be cascaded with timer1 by setting T1CS1 to 1 and clearing T1C S0 When T1SIZE is set to 1 the timers form a 24 bit timer counter When T1SIZE is cleared the timers can form a 16 bit timer counter 2011 AppoTech Ltd 69 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Chapter 9 Watchdog The Watchdog timer WDT is a free running on chip RC oscillator which does not require any external components So the WDT will still run even if the clock on t
47. ete fa altes 72 10 2 Inverter GUIDE o p m et uuu rn reet eoe ave a ee Pd uen a 84 Chapter 11 Electrical Characteristics 85 11 1 Absolute maximum CL ne EE 85 117 2 DC Ee E e 86 11 3 Data Retention Characteristics in SLEEP 87 Nee Elle EE e EE 87 11 5 Oscillator 2 21 61 01000 eene nennen 88 11 6 Reset CiaracteriSticS u uuu activin m De ier pa Ha da 89 Chapter 12 Package Dimensions U U 92 92 1A e i COE E e S Sana Isu asua SAFISHA 93 Appendix Revision History Ee ee 94 APG013 UM 100 EN 4 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Table of Registers Register 2 1 FSR ee E E 18 Register 2 2 STATUS Status Register secessit enne ten enano enhn 18 Register 2 3 PCL PC Low Byte 1 nnne ener emn 20 Register 4 1 PCON1 Power Control 1 40 Register 4 2 PCON2 Power Control 2 42 Register 4 3 Clock Control Register 44 Register 6 1 INTEN Interrupt Mask
48. gt W DECR 1 0 0001 11rr rrrr R 1 gt R ORW R 1 0 0010 00rr rrrr W R gt W T ORR W 1 0 0010 01 rr rrrr W R gt R ANDW R 1 0 0010 10rr rrrr W amp R gt W d AND R W 1 0 0010 11rr rrrr W amp R XORW R 1 0 0011 O0rr rrrr W T XORR W 1 0 0011 01rr rrrr WAR R ADDW R 1 0 0011 10rr rrrr W R gt W T ADD R W 1 0 0011 11rr rrrr W R R MOVW R 1 0 0100 00 gt W TEST 1 0 0100 01 rr rrrr R gt R COMW R 1 0 0100 10rr rrrr gt W COMR 1 0 0100 11rr rrrr R gt R INC WR 1 0 0101 00rr rrrr R 1 gt W T INC R 1 0 0101 01rr rrrr R 1 R DJZ W R 1 2 0 0101 10rr rrrr 1 gt skip next instruction if result 0 DJZ R 1 2 0 0101 11rr rrrr R 1 gt R skip next instruction if result 0 RRCW R 1 0 0110 O0rr rrrr R 7 1 gt W 6 0 C gt W 7 R O gt C i RRCR 1 0 0110 01rr rrrr R 7 1 gt R 6 0 C gt R 7 RIO gt j RLC W R 1 0 0110 10rr rrrr R 6 0 gt W 7 1 C gt W 0 R 7 gt C RLC R 1 0 0110 11rr rrrr R 6 0 gt R 7 1 C gt RIO gt i SWAPW R 1 0 0111 00 R 3 0 gt W 7 4 R 7 4 gt W 3 0 SWAP R 1 0 0111 01rr rrrr R 3 0 gt R 7 4 R 7 4 gt R 3 0 IJZ W R 1 2 0 0111 10rr rrrr R 1 W skip next instruction if result 0 IJZ R 1 2 0 0111 11rr rrrr R 1 gt R skip next instruction if
49. he VDD pin or the maximum current out of the VSS pin It is restricted by the power ground UO port and internal logic circuits bus width Beyond this limited electrical migratory may occur on the power and ground buses which will lead to open buses disconnected with pins if it states some long time make the logic circuits that connected to these buses stop works Therefore beyond the maximum ratings working will affect device s reliability APG013 UM 100 EN 82 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 11 2 DC Characteristics Table 11 1 DC current parameters Symbol Descriptions Min Typ Max Unit Conditions Supply voltage 2 2 3 3 36 V lbp Supply current normal mode 2 3 mA Fosc 8MHz toggle output one I O pin other 3 6V DIV 1 UO have valid state WDT off LVD on 800 uA XOSC Fosc 8MHz 3 6V DIV 8 1 25 mA Fosc AMHz 3 3V DIV 1 630 Fosc AMHz 3 3V DIV 8 65 UA KOSC Fosc 32KHz 3 3V DIV 1 Supply current IDLE mode 650 uA XOSC Fosc 8MHz WDT off LVD on Voo 3 3V DIV 1 520 JUA Fosc 8MHz 3 6V DIV 1 385 JUA Fosc 4MHZ Voo 3 3V DIV 1 ls Supply current SLEEP mode 7 0 JUA VDD 3 6V A 5 8
50. he XIN and XOUT pins is turned off such as in SLEEP mode During normal operation SLEEP mode or IDLE mode a WDT time out will cause the device to reset and the TO bit will be cleared The WDT can be disabled by clearing the control bit WDTEN 3 0 to 0101 Other values presented in WDTEN 3 0 will enable the WDT When the clock is in XOSC mode the WDT has a nominal time out period of 2 25ms 18ms 72ms or 288ms selected PORSEL 1 0 PORSEI 0 2 b11 2 25ms PORSEL 1 0 27610 18ms PORSEL 1 0 201 72ms PORSEL 1 0 2 b00 288ms If a longer time out period is desired a postscaler with a division ratio of up to 1 128 can be assigned to the WDT controlled by the PS bits in TOCON 2 0 register Thus the longest time out period is approximately 36 8 seconds The CLRWDT instruction clears the WDT and the postscaler If assigned to the WDT it is prevented from timing out and generating a device reset The SLEEP and IDLE instructions reset the WDT and the postscaler If assigned to the WDT this gives the maximum SLEEP time before a WDT wake up reset Note 4 1 The WDT should be turned off if external interrupt or port interrupt is used to wake up the system Otherwise it may be reset by WDT before the expected wake up APG013 UM 100 EN 70 2011 AppoTech Ltd SS APG013 8 bit RISC Microcontroller USER MANUAL Chapter 10 IO Port 10 1 Normal I O port function 10 1 1 Port B Port B is a 8 p
51. he location in the User region Then use RETW instruction to return a byte in the User region Only the User region 0x6 OxF can be accessed The addresses 0 0 to 0x5 are reserved READ SMART bit will be cleared automatically after execution of RETW Figure 2 2 shows the proper access method Figure 2 2 Accessing product ID APG013 UM 100 EN 12 2011 AppoTech Ltd Rev 10 0 APG013 8 bit RISC Microcontroller USER MANUAL Program space ID Space 1 set Read smartbitto 1 b 0x0 Smart option 0 0 1 Smart option 1 0x3 User region 4 Read_smart bit is automatically cleared Only RETW should be used to read the product ID If instruction other than RETW is used the execution sequence will jump to an unknown location Note lt 1 2 4 Data memory organization APG013 s memory bank is divided into two banks Memory space from 0x00 to 0x2F can be accessed by Bank 0 and 0x30 0x3F can be accessed by both Bank 0 and Bank 1 0x00 to 0x0F are reserved for SFR Special Function Registers while 0x10 to 0x2F are available as SRAM most SFR in this location can be accessed by MOV instruction Another part of SFR are stored in a separated location which can only accessed by the EXT instruction Data memory space start from 0x30 to 0x3F are separated into two banks bank 0 and bank 1 Each bank provides 16 bytes of SRAM Totally there are 64 bytes of SRAM available for use 2011 AppoTech Ltd 13 APG01
52. in bi directional tri state 1 0 port PB3 is input only Direction Control All UO pins expect PB3 have data direction control registers PBDIR which can configure these pins as output or input If RDPORT bit in smart option is 0 reading from output pin will return the pin status If RDPORT bit in smart option is 1 reading from output pin will return the value in the corresponding output register Inverter Output When PB1 inverter output function is enabled PBDIR 1 must be cleared to set PB1 as output pin When PB2 is used as TOCS PB2 must be set as input pin PB3 is an input only pin When PB3 is used as RSTB internal weak pull up resistor is enabled automatically Pull up and pull down When PB5 and 4 are used as KIN and XOUT PB5 and 4 digital 1 0 function and their internal pull up and open drain output are disabled by hardware All Port B except PB3 pins have their corresponding pull up control bits PUPCON to enable internal weak pull up resistor PB2 PB1 and PBO have their corresponding pull down control bit PDNCON to enable internal weak pull down resistor Internal weak pull up or pull down resistor should be disabled when the pin is configured as output All Port B pins except PB3 have their corresponding open drain output control bit ODCON to enable open drain output Open drain output must be disabled when the pin is configured as input Interrupt Port B provides the input change inte
53. lt eis Operation W R C gt R Status Affected C DC Z Description Add the contents of the W register and register R with Carry The result is stored in the R register Cycles 1 ADD W R Add W andR Operands 0 lt R lt 0x3F Operation W R gt W Status Affected C DC Z Description Add the contents of the W register and register R The result is stored in the W register Cycles 1 ADD R W Add W and R Operands 0 lt R lt 0x3F Operation W R gt R Status Affected C DC Z Description Add the contents of the W register and register R The result is stored in the R register Cycles 1 2011 AppoTech Ltd 25 APG013 UM 100 EN APG013 8 bit RISC Microcontroller Bertone USER MANUAL ADDWk Add W and Immediate Operands 0 lt k lt OxFF Operation W k gt W Status Affected C DC Z Description Add the contents of the W register with the 8 bit immediate The result is stored in the W register Cycles 1 AND W R AND W and R Operands 0 lt R lt 0x3F Operation W and R gt W Status Affected 2 Description The contents of the W register are AND ed with register R The result is stored in the W register Cycles 1 AND R W AND W and R Operands 0 lt R lt Operation W and R gt R Status Affected 2 Description The contents of the W register are AND ed with register R The result is stored in the R register Cycles 1
54. mode 0 TimerO works in timer mode or counter mode TOMODE 0 TOCS Timer mode Timer mode Counter mode PWM mode Invalid setting O O 0 1 1 RW 0 enable bit 1 TimerO enable 0 TimerO disable NOTE Before setting TOEN to 1 other bits in TOCON must be stable TOCS 0 clock source select bit 1 External TOCK WDTCLK XOSC 0 Internal instruction clock cycle NOTE In PWM mode TOCS must be 0 to select internal instruction clock cycle as clock source TOSE 0 source edge select bit 1 Falling edge on TOCK 0 Rising edge on TOCK PSA Scaler assign bit 1 Assign to WDT 0 Assign to timerO APG013 UM 100 EN 60 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 2 0 PS 2 0 R W Prescaler Postscaler rate select bits TimerO Rate WDT Rate 000 1 2 1 1 001 1 4 1 2 010 1 8 1 4 011 1 16 1 8 100 1 32 1 16 101 1 64 1 32 110 1 128 1 64 111 1 256 1 128 2011 AppoTech Ltd 61 APG013 UM 100 EN 013 8 bit RISC Microcontroller Rev 10 0 USER MANUAL 7 1 Timer mode Timer mode is selected by clearing the TOCS bit and TOMODE bit In timer mode TOCNT will increment system clock Fsys cycle PSA 1 or every prescaler overflow PSA 0 New value can be written to TOCNT at any time TOCNT will increase from the new value at next count event TOCNT will be cleared and TOIF
55. n TOCNT equals to TODUTY BUF the 2 will output low If TODUTY 0x00 no low pulse will be generated PWM pin When TODUTY is bigger than TOPR the TOPWM PB2 will always output high PB2 must be set as output when TimerO works in counter mode APG013 UM 100 EN 64 2011 AppoTech Ltd Ke APG013 8 bit RISC Microcontroller USER MANUAL 7 4 Scaler An 8 bit scaler is available as a prescaler for timerO or as a postscaler for WDT Note that the scaler may be used by either the timerO module or the WDT module but not both Thus a prescaler assignment for the timerO means the there is no postscaler for WDT and vice versa The PSA bit TOCON bit 3 determines scaler assignment The PS bits TOCON 2 1 determine scaler ratio Because of synchronization timerO period may have one sample clock width jitter if the scaler is assigned to timerO When the scaler is assigned to timerO all instructions writing to TOCNT register will clear the scaler When it is assigned to WDT a CLRWDT instruction will clear the scaler The scaler is neither readable nor writable On a RESET the scaler value is OxFF To avoid an unintended device reset CLRWDT scaler assigned to WDT or instruction that writes to TOCNT scaler assigned to Timer0 must be executed before changing the scaler assignment from WDT to timerO and vice versa 2011 AppoTech Ltd 65 APG013 UM 100 EN 013 8 bit RISC Microcontroller EES USER MANUAL
56. oller USER MANUAL 2 2 10 space and Smart option Smart option is used to define the starting condition of the APGO13 The reserved bits of smart option must be kept 1 Smart option 0 10 9 8 7 6 5 4 3 2 1t Reserved PB4CLKO PCHSEL DND SEL PORSEL WDTSEL RDPORT RSTBEN Smart option 1 4770 19 qm ps j2 T Reserved WDTCEN CLKDIV RCSEL CLKSEL Table 2 1 Smart option 0 description Name Description RSTBEN RSTB pin enable 1 Set PB3 as normal input pin 0 Set PB3 as reset pin RDPORT Port read selection Valid when the pad is configured as output pin 1 Read output register 0 Read pad WDTSEL Watchdog reset select 0 WDT will not reset the system after 1 wake up from SLEEP mode but will set the WDTFLAG in the CLKCON If this bit is not cleared after 2nd wake up from SLEEP WDT will reset the system WDTFLAG can be cleared by SLEEP IDLE or CLRWDT instruction Notes With this setting WDT will not reset the system after 1st wakeup from IDLE mode too But the WDTFLAG in CLKCON will not be set If one want to enter IDLE mode again after 1st wake up from IDLE mode by WDT CLRWDT instruction must be executed first 1 WDT will always reset the system after wake up from SLEEP mode PORSEL Power up delay time select 0111 Power on delay time is 2 25 ms SLEEP mode wake up delay time is 2 25 ms 1111 Power on delay time is 4 5 ms SLEEP mode wake up delay time is
57. oller Bev nos USER MANUAL When IDLE instruction is executed bit is cleared TO bit is set Watchdog timer will be cleared and keeps running if enabled CPU is stopped TimerO port control and interrupt control keep running All I O pins maintain the status they have before the IDLE instruction was executed 013 can wake up from IDLE mode through one the following events 4 RSTBreset WDT time out reset if enabled Interrupt from INTOB pin Interrupt from INT1B pin Port B input change interrupt TimerO overflow interrupt Timer1 overflow interrupt When SLEEP instruction is executed PD_ bit is cleared TO_ bit is set Watchdog timer will be cleared and keeps running if enabled And the oscillator driver is turned off All I O pins maintain the status they have before the SLEEP instruction was executed APG013 can wake up from SLEEP mode through one the following events RSTBreset WDT time out reset if enabled 4 Interrupt from INTOB pin Interrupt from INT1B pin Port B input change interrupt RSTB reset or WDT reset will cause a device reset The RST PD and TO bits can be used to determine the cause of device reset The PD bit is set on power up and is cleared when SLEEP IDLE instruction is executed The TO bit is cleared if WDT time out occurred For 013 to wake up from IDLE or SLEEP mode through an interrupt event the corresponding interrupt enable bit must be
58. on is turned on Notes Power Saving can only enabled in single clock mode with the 16 times divider active and the or equal to 32KHz In any other conditions Power Saving should be disabled For details please refer to Figure 5 1 Table 4 1 Frequency Setting available for Power Saving Setting Notes A APG013 UM 100 EN 42 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Please notes that the following tables only list the available setting for IRC Clock Source For other clock source Power Saving Setting is also available however user need to do the calculation itself to see whether the Fsys would meet the requirement for Power Saving Setting Clock Source CLKDIV SPEED Fsys System Frequency 4MHz IRC Divided by 8 1 31 25KHz 1MHz IRC Divided by 2 1 31 25KHz 1MHz IRC Divided by 4 1 15 6KHz 1MHz IRC Divided by 8 1 7 8125KHz 455kHz IRC Divided by 1 1 28 4KHz 455kHz IRC Divided by 2 1 14 2KHz 455kHz IRC Divided by 4 1 7 109KHz 455kHz IRC Divided by 8 1 3 55KHz 2011 AppoTech Ltd 43 APG013 UM 100 EN 013 8 bit RISC Microcontroller Rev 10 0 USER MANUAL 4 1 Power on Reset POR and Low Voltage Reset LVR APGO013 has a built in LVD with two levels low voltage reset and total four levels voltage indicator LVDL1 LVDL2 LVDL3 LVDLA LVDL1 1 8V LVR LVDL2 2 2V LVR
59. provided that TOMODE is cleared TOCS is set i e Timer 0 in timer mode and CLKSRC 0601 When SPEED is set to 1 32kHz XOSC will be used for system clock The extra division 16 circuit is not used Refer to the following Section 5 1 3 Notes The Selection should be done when the main oscillator is active No selection should be made when the XOSC clock is already active otherwise error may occur APG013 UM 100 EN 48 2011 AppoTech Ltd APG013 8 bit RISC Microcontroller USER MANUAL 5 1 3 System Speed Selection System speed can be configured at CLKCON 2 Low Speed Mode SPEED 1 Normal Speed Mode SPEED 0 Single Oscillator Mode Fsys Fdiv 16 Fsys Fdiv Dual Oscillator Mode Fsys 32kHZ XOSC Fsys Fdiv Fsys System clock Fdiv Clock input to divider Figure 5 1 013 clock system diagram SPEED CLKSEL Dual Oscillator Mode SCLKSEL Slow Clock Selection CLKDIV CLKSEL Divide 1 IRC 2 4 8 Clock output COUTSEL Note When dual oscillator mode is enabled the CLKSEL for clock output is disabled 5 2 Power saving mode 013 provides two power saving mode IDLE mode and SLEEP mode IDLE mode is entered by executing an IDLE instruction SLEEP mode is entered by executing a SLEEP instruction 2011 AppoTech Ltd 49 APG013 UM 100 EN 013 8 bit RISC Microcontr
60. r if assigned 1 gt 1 gt PD_ Status Affected TO_ PD_ Description The CLRWDT instruction resets the WDT It also resets the postscaler if the postscaler is assigned to the WDT Status bits and PD are set Cycles 1 COM W R Complement R Operands 0 lt R lt Operation R W Status Affected 2 Description The contents of register are complemented The result is stored W register Cycles 1 COM R Complement R Operation R gt R Status Affected Z Description The contents of register R are complemented The result is stored in R register Cycles 1 APG013 UM 100 EN 28 2011 AppoTech Ltd Revd APG013 8 bit RISC Microcontroller USER MANUAL DAA Adjust W s data format from HEX to DEC Addition Operands None Operation W HEX gt W DEC Status Affected C Description Convert the W data from hexadecimal to decimal formal after any addition operation and restored to W Step 0 If DC 1 or W 3 0 W 0x06 gt Step 1 If C 1 or W 7 4 OxA W 0x60 gt and 1 gt C if W 0x60 gt OxFF Cycles 1 DEC W R Decrement R Operands 0 lt R lt 0x3F Operation R 1 gt W Status Affected Z Description Decrement register R The result is stored in the W register Cycles 1 DEC R Decrement R placeholder Operands 0 lt R lt 0x3F Operation R 1 gt R Status Affected Z Description Decrement register R The resul
61. rite 219 time for the MSB of Timer1 Counter 8 bit mode Write one byte only for 8 bit mode T1CNT is cleared when T1CNT equal to T1PR and T1EN 1 T1IF will be set when T1CNT equal to T1PR and T1EN 1 Register 8 2 Timer1 Period Register Address 7 5 4 3 2 1 0 POR Default Timer1 Period Register General part T1PR 1111 1111 OKOA RW RW RW RW RW RW RW RW Bit Bit Name Mode Description 7 0 R W Timer1 Period Register 16 bit mode Write 154 byte for the LSB of Timer1 Period Register and write 2nd byte for the MSB of Timer1 Period Register 8 bit mode Write one byte only for 8 bit mode 2011 AppoTech Ltd 67 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 8 3 T1CON Control Register T1CON Address 7 6 5 4 3 2 1 0 POR Default Timer1 Register Extended part T1EN T1SIZ 1 51 CLKSRC 0011 0x00 0x02 E gt R W 2 RW RW RW RW Bit Bit Name Mode Description 7 Reserved 6 T1EN RAN Timer1 enable bit 1 Timer1 enable 0 Timer1 disable NOTE Before setting T1EN to 1 other bits in must be stable 5 4 Reserved 3 T1SIZE R W Timer1 Size 0 8 bit timer 1 16 bit timer 2 T1CS R W Timer1 clock source select bit 0 Internal instruction clock cycle 1 Overflow from timer O 1 0 CLKSRC 1 0 RAW 0 external clock sourc
62. rrupt wake up function Each pin has its corresponding input change interrupt wake up enable bits PBWAK to select the input change interrupt wake up source The corresponding port should be read once before the port change interrupt is enabled PBO and D I are also external interrupt input signals when the EIS bit 1 6 is set to 1 In this case or PB1 input change interrupt wake up function will be disabled by hardware even if it is enabled by PBWAK Refer to Chapter 6 for details 1 bit Register All Port B pins have a 1 bit register that store the input from pad for port change interrupt 2011 AppoTech Ltd 71 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Register 10 1 PBDIR Port B Direction Control Register PBDIR Address 7 5 4 2 1 0 POR Default Port B Direction Control Extended part PBDIR PBDIR PBDIR PBDIR PBDIR 1111 1111 Register 0x06 5 4 2 1 0 RW RW RW RW RW Bit Bit Name Mode Description 7 6 Reserved c 5 PBDIR5 RAN PB5 Direction Control 1 Input mode 0 Output mode 4 PBDIR4 RAN 4 Direction Control 1 Input mode 0 Output mode 3 Reserved 2 PBDIR2 RAV PB2 Direction Control 1 Input mode 0 Output mode 1 PBDIR1 R W PB1 Direction Control 1 Input mode 0 Output mode 0 PBDIRO R W PBO Direction Control 1 Input mode 0 Output mode APG013 UM 100 EN 72 2011 AppoTech Ltd
63. ruction clearing PBIF or is executed 2 Toclear the interrupt do not use BC instruction directly Use MOV instruction instead as in the following example Example MOVW OxFE MOV INTF W 6 1 External interrupt Two external interrupt are available INTO and INT1 External interrupt on INTOB INT1B pin is rising or falling edge triggered as selected by INTEDGO INTEDG1 Changing INTEDGO INTEDG1 may trigger APG013 UM 100 EN 56 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL fault in INTOIF INT1IF So after changing INTEDGO INTEDG1 clearing INTOIF INT1IF is needed When a valid edge appears on the INTOB INT1B pin the flag bit INTOIF INT1IF is set This interrupt be disabled by clearing INTOIE INT1IE bit The INTOB INT1B pin interrupt can wake up the system from SLEEP condition if INTOIE INT1IE was set before going to SLEEP mode If GIE bit was set the program will execute interrupt service routine after wake up or if GIE bit was cleared the program will continue executing instruction after wake up 6 2 TimerO interrupt When TOCNT is equal to TOPR TOIF will be set This interrupt can be disabled by clearing TOIE bit The TimerO interrupt can wake up the system from IDLE condition if TOIE was set before going to IDLE mode If GIE bit was set the program will execute interrupt service routine after wake up or if GIE bit was cleared the program will
64. s of the W register with the 8 bit immediate k The result is stored in the W register Cycles 1 2011 AppoTech Ltd 39 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Rev 1 0 0 Chapter A Power Up and Reset 013 be RESET in one of the following Power on Reset POR Low voltage Reset LVR RSTB pin Reset WDT time out Reset ways Register 4 1 PCON1 Power Control 1 Register PCON1 Address 7 6 5 4 3 2 1 0 POR Default Power Control 1Register General part WDTEN EIS BANKR INTEDG INTEDG 10xx 0x00 0x08 3 EG 1 0 RW RW RW RW RW Bit Bit Name Mode Description 7 R W Watchdog timer enable bit This bit works together with WDTEN 2 0 on PCON2 to form WDTEN 3 0 See next page When WDTEN 3 0 0101 it will turn off watchdog timer if it is turned on by the smart option WDTCEN Other setting will turn on watchdog timer if the smart option is turned on 6 EIS R W 1 external interrupt function enable bit 0 PBO PB1 external interrupt function disabled 1 PBO PB1 external interrupt function enabled 5 BANKREG R W Bank Register Switch the memory bank in order to use the additional 16 byte SRAM in bank 1 0 Bank 0 1 Bank 1 4 2 Reserved INTEDG1 R W External interrupt 1 edge select bit 0 Interrupt on falling edge of INT1B pin 1 Interrupt on rising edge of INT1B pin APG013 UM
65. ster 10 7 INVCON Inverter Output Control 81 2011 AppoTech Ltd 5 APG013 UM 100 EN Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Chapter 1 Architecture Overview 1 1 Hardware architecture 8 RISC 13 CPU POR LVD CORE TIMERO TIMER1 1K x 13bit 64 byte OTP SRAM 1 2 Pin assignment Figure 1 1 013 8 pin DIP SOP package VDD 1 g VSS PB5 XIN 2 APG013 7 L PBO INTOB XOUT 8 pin 6 DI PB1 INTIB PB3 RSTB 4 5 PB2 TOCK TOPWM APG013 UM 100 EN 6 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL 1 3 Pin description Table 1 1 13 pin description Name Pin 8 pin Direction Function PBO INTOB 7 Bidirectional input output port System wakeup Configurable weak pull down resistor Configurable weak pull up resistor Configurable open drain output External interrupt input PB1 INT1B Bidirectional input output port System wakeup Configurable weak pull down resistor Configurable weak pull up resistor Configurable open drain output External interrupt input 2 Bidirectional input output port System wakeup Configurable weak pull down resistor Configurable weak pull up resistor Configurable open drain output TimerO external clock input TimerO PWM output PB
66. t is stored in the R register Cycles 1 DZ W R Decrement R Skip if 0 Operands 0 lt R lt Operation 1 gt W skip if result 0 Status Affected None Description The contents of register R are decremented The result is stored in W register If the result is 0 the next instruction which is already fetched is discarded and a NOP is executed instead making if a two cycle instruction Cycles 1 2 2011 AppoTech Ltd 29 APG013 UM 100 EN 013 8 bit RISC Microcontroller USER MANUAL DJZ R Decrement R Skip if 0 Operands 0 lt R lt 0x3F Operation R 1 gt R skip if result 0 Status Affected None Description The contents of register R are decremented The result is stored R register If the result is 0 the next instruction which is already fetched is discarded and a NOP is executed instead making if a two cycle instruction Cycles 1 2 EXT W ER Load the W register with ER register in extend memory bank Operands 0 lt ER lt 0xF Operation ER gt W Status Affected None Description Read the ER register in extend memory bank to W register Cycles 1 EXT ER W Load the register in extend memory bank with W register Operands 0 lt ER lt 0xF Operation W gt ER Status Affected None Description Load the ER register in extend memory bank with W register Cycles 1 IDLE Enter IDLE mode Operands None Operation 0x0
67. tatus Affected None Description The upper and lower nibbles of register R are exchanged The result is stored in W register Cycles 1 SWAP Swap nibbles in R Operands 0 lt R lt 0x3F Operation R 7 4 gt R 3 0 R 3 0 gt R 7 4 Status Affected None Description The upper and lower nibbles of register R are exchanged The result is stored in R register Cycles 1 TEST R Test R data Operation Z 1 if the data of R is equal to 0x00 Z 0 if the data of R is not equal to 0 00 Status Affected Z APG013 UM 100 EN 38 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Description Test the data of R register If the data of R is equal to 0x00 Z flag is set If the data of R is not equal to 0x00 Z flag is cleared Cycles 1 XOR W R Exclusive OR W with R Operands 0 lt R lt 0x3F Operation W xor R gt W Status Affected 2 Description Exclusive OR the contents of the W register with register R The result is stored in the W register Cycles 1 XOR R W Exclusive OR W with R Operands 0 lt R lt 0x3F Operation W xor R gt R Status Affected 2 Description Exclusive OR the contents of the W register with register R The result is stored in the R register Cycles 1 XORW k Exclusive OR immediate with W Operands OsksOxFF Operation W xor k gt W Status Affected 2 Description Exclusive OR the content
68. te u unchanged d depends on state before wakeup Unchanged bits in INTF will depend on the interrupt event CLKCON 1 0 default will 00 when PB4 is selected as normal I O CLKCON 1 0 default will be don t care when PB4 is selected for XOUT Register 2 1 FSR File Select Register FSR Address 7 6 5 4 3 2 1 0 POR Default File Select Register General GPR3 GPR2 INDA 5 0 XXXX XXXX 0x04 RW RW RW RW RW RW RW RW Bit Bit Name Mode Description 7 GPR3 RAW General purpose register 6 GPR2 RAW General purpose register 5 0 INDA 5 0 RAW Indirect address to general part data memory space Register 2 2 STATUS Status Register This register contains the arithmetic status of the ALU the RESET status If the STATUS register is the destination for an instruction that affects the Z DC or C bits then writing to these three bits is disabled These bits are set or cleared according to the device logic APG013 UM 100 EN 18 2011 AppoTech Ltd Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL STATUS Address 7 5 4 3 2 1 0 POR Default Status Register General part RST T1 10 PD Z DC 0001 1 0x03 RW RW RW RO RO RW RW RW Bit Bit Name Mode Description 7 RST RAW Wake up type selection bit 1 Wake up from SLEEP on Port B input change 0 Wake up from other reset types 6 T1 IDX R
69. ted to output RC oscillator clock after power up 0 PB4 is selected for IO output RC oscillator or divider clock Please refer to Section 5 3 System clock output for detailed descriptions on the settings Table 2 2 Smart option 1 description Name Description CLKSEL Oscillator selection 111 IRC 110 ERC 101 XOSC 100KHz to 1MHz 100 XOSC 1MHz to 10MHz 011 XOSC 10MHz to 16MHz 2010 XOSC 32KHz 2001 Invalid 72000 Dual Oscillator Mode IRC 32kHz XOSC Both IRC amp 32KHz XOSC could be selected as system clock RCSEL Internal RC oscillator frequency selection 211 8MHz 210 4MHz 201 1MHz 00 455KHz WDTCEN WDT enable 1010 WDT disable 2011 AppoTech Ltd 11 APG013 UM 100 EN APG013 8 bit RISC Microcontroller USER MANUAL Others WDT enable CLKDIV System clock division 11 divide 1 10 divide 2 01 divide 4 00 divide 8 Note 1 When the clock runs slower than WDT the timer out period will probably be longer than 17 5us The magnitude of discrepancy depends on frequency difference between the clock and WDT 2 3 Product ID and Check sum words User information like product ID or check sum words can be stored in User region This information can be read out by APGO13 programmer RETW command at customer firmware Before RETW is called user should first set READ SMART PCON2 7 and use the CALL instruction to jump to t
70. ter Output Control Register INVCON Address 7 6 5 4 3 2 1 0 Inverter Output Control Extended part i 2 Register 0x03 RW RW Bit Bit Name Mode Description 7 4 Reserved 3 PB1INVS R W PB1 invert output source select 0 Select PBO pin 1 Select PB2 pin 2 PB1INVEN R W PB1 invert output enable 0 Invert output disabled 1 Invert output enabled 1 0 Reserved Figure 10 6 PB1 inverter output 1 normal I O data PB1INVS PB1INVEN 2011 AppoTech Ltd 81 APG013 UM 100 EN 013 8 bit RISC Microcontroller Rev 10 0 USER MANUAL Chapter 11 Electrical Characteristics Unless otherwise specified the following standard testing condition is at 25 C and VDD at 3 3V 11 1 Absolute maximum ratings Ambient temperature under bas 40 C to 85 Storage temperature doute erige deu ce pee ua 65 C to 150 C Absolute maximum ratings are defined in the worst working condition These values are not present as the device parameters Exposure to these listings may damage the device These parameters are not lives alone it must meet the other conditions For example the maximum current source sink by any I O pin The total number I O pins that can be used at the same time is decided by the maximum current source sink of the port or the total current of many ports and the maximum current into t
71. the user region and use RETW instruction to return a byte This bit will be cleared automatically after execution of RETW PCL Address 7 6 5 4 3 2 1 0 POR Default PC Low Byte General part PCL 0000 0000 Register Ox02 RW RW RW RW RW RW RW RW Bit Bit Name Mode Description 7 0 PCL RAN PC low byte Note 1 Anyinstruction which write to PCL will need 2 system clock cycles to execute 2 PCL cannot be used as the operator IJZ DJZ instruction 2011 AppoTech Ltd 21 APG013 UM 100 EN Rev 1 0 0 APG013 8 bit RISC Microcontroller USER MANUAL Chapter 3 Instruction Set 3 1 Instruction set summary Each 013 instruction is a 13 bit word Most instruction needs only 1 system clock Fsys cycle Some branch instruction need 2 Fsys cycles The 013 instruction set symbols description is shown in Table 3 1 The 013 instruction set is summarized in Table 3 2 For byte oriented instructions R represents a general part data memory designator The R specifies which data memory byte is to be used by the instruction ER represents an extend part data memory designator For bit oriented instructions b represents a bit field designator which selects the number of the bit affected by the operation For literal and control operations k represents an eight or ten bit constant or literal value Table 3 1 013 instruction set symbols description
72. ument is believed to be accurate in all respects at the time of publication but is subject to change without notice AppoTech assumes no responsibility for errors and omissions and disclaims responsibility for any consequences resulting from the use of information included herein Additionally AppoTech assumes no responsibility for the functioning of undescribed features or parameters AppoTech reserves the right to make changes without further notice AppoTech makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does AppoTech assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages AppoTech products are not designed intended or authorized for use in applications intended to support or sustain life or for any other application in which the failure of the AppoTech product could create a situation where personal injury or death may occur Should Buyer purchase or use AppoTech products for any such unintended or unauthorized application Buyer shall indemnify and hold AppoTech harmless against all claims and damages In case of any questions or comments about this documentation please feel free to contact AppoTech at documents appotech com 2011 AppoTech Ltd 91 APG013 UM 100 EN

APG013 User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents