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ML9636GDZ45A User`s Manual

1. 48 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics Table 7 3 Correspondence between Table 7 4 Correspondence between TPC Values and Bits AMPL ADJ Values and Bits TPC 3 0 TPC DEC AMPL_ADJ 5 0 AMPL_ADJ DEC 110110 110101 110100 110011 110010 110001 110000 101111 101110 101101 101100 101011 101010 101001 101000 100111 100110 100101 100100 100011 100010 100001 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 010000 010001 010010 010011 010100 010101 010110 r al N N D ine erg ry Co Nm o Sa N TO 00 ig o N o Oo i al 4 de 4 N o o O INDOPROIO AO 8 7 6 5 4 3 2 1 0 49 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics 7 1 3 Creating a Standard Temperature Correction Curve At the dispersion temperature points on both ends of the pre selected temperature zone evaluate the transmission power as a system Set or user applied board including the ML9636 and peripheral components such as the ext
2. TPC DEC AMPL_ADJ DEC 67 3 6 68 4 6 69 4 5 70 4 4 71 4 3 72 4 2 73 4 1 74 4 0 75 4 1 76 4 2 77 4 3 78 4 4 79 4 5 80 4 6 81 5 5 82 5 4 83 5 3 84 5 sg 85 5 86 5 0 87 5 1 88 5 2 89 5 3 90 5 4 91 5 5 92 5 6 93 6 5 94 6 4 95 6 3 96 6 2 97 6 1 98 6 0 99 6 1 100 6 2 101 6 3 102 6 4 103 6 5 104 6 6 105 7 5 106 7 4 107 7 3 108 7 2 109 7 a 110 7 0 111 7 1 112 7 2 113 7 3 114 7 4 115 7 5 116 7 6 117 8 5 46 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics AMPL_ADJ DEC 118 8 4 119 8 3 120 8 2 121 8 1 122 8 0 123 8 1 124 8 2 125 8 3 126 8 4 127 8 5 128 8 6 129 9 5 130 9 4 131 9 3 132 9 2 133 9 1 134 9 0 135 9 1 136 9 2 137 9 3 138 9 4 139 9 5 140 10 5 141 10 4 142 10 3 143 10 2 144 10 1 145 10 0 146 10 1 147 10 2 148 10 3 149 10 4 150 10 5 151 11 5 152 11 4 153 11 3 154 11 2 155 11 1 156 11 0 157 11 1 158 11 2 159 11 3 160 11 4 161 11 5 162 12 4 163 12 3 164 12 2 165 12 1 166 12 0 167 12 1 168 12 2 a ZA ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics TPC DEC AMPL_ADJ DEC
3. a le SCEN negate timing Operation When SCEN is negated The command fails before completion of Operates normally at the next command and onwards transmission up to the Command data When SCEN is negated after In the case of a GET command the ML9636 asserts SINT after completion of transmission up completion of the preparation for a read to the Command data When SCEN is asserted The GET_confirm command is not returned from the ML9636 SINT is before SINT is asserted after asserted after SCEN is negated thereby enabling the GET_confirm the GET_request command is command to be read transmitted When one GET_request The ML9636 can hold a maximum of two GET_request commands command is transmitted and Therefore when the first read is executed the GET_confirm command then another GET_request that corresponds to the first GET_request command is transmitted and GET command is transmitted when the second read is executed the GET_confirm command that commande corresponds to the second GET_request command is transmitted If three or more GET_request commands are executed in succession the GET_request command being held at the second time will be overwritten When the reads are executed the GET_confirm command that corresponds to the first GET_request command is transmitted then the GET_confirm command that corresponds to the last GET_request command is transmitted When the GET_request command is transmitted and t
4. __J UU UU UU UL SU UU UL sdin VI MI m LL sdo Request Status Command Data0 A DATAO update Timing Figure 3 6 Data Write Timing Setting Data 1 Byte If a data write is not carried out correctly the ML9636 asserts the SINT signal and notifies the host of a write error When SINT has been asserted the command at the error occurrence and the error contents will be output from the ML9636 by setting the request byte first tranfer byte to Confirm enable set bit 2 to 1 from the host Reading by a SET_confirm command The command at the error occurrence to be output is displayed as a value command of the target SET command incremented by 1 When reading of the error state is completed the SINT signal is negated If reading by a SET_confirm command is not executed upon the assertion of SINT SINT is left asserted So be sure to execute a SET_confirm command read 22 At a read by a SET_confirm SDIN SDO 0x Requests 0x04 Status ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 04 Error y 9 Confirm command Figure 3 7 SET_Confirm Data Format 1 The command at an error occurrence is output as a value command of the target SET command incremented by 1 2 In the actual ML9636 status output Dx0C is always returned in order to support read and write to the host at the same time Details of Confirm Contents
5. 50 pF 20 ns Interval between one SCEN T 450 mas e assert and the next CEUM SCLK output delay time Teckop 40 ns SDO output hold time TDOH 5 ns SCEN enable time TcEON 0 ns SINT disable time TSINTDIS 0 5 us Notes All timings are measured at 20 and 80 of Vppro When SCLK is a positive clock SCEN SCLK SDIN in Sree MSB OUT A rise fall of the SINT pin occurs asynchronously with other clock synchronous serial interface related pins 1 MSB OUT bit is always low because MSB OUT is a first bit of status byte Refer to section 3 2 2 and 3 2 4 2 SDO goes low after LSB OUT output Figure 5 4 Timing Diagram of SCI Interface Positive Clock 36 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics When SCLK is a negative clock SCEN FscLK1 TCEH SCLK SDIN in MSBIN BITS6 1 LSB IN SDO out MSB OUT BITS6 1 X LSB OUT A rise fall of the SINT pin occurs asynchronously with other clock synchronous serial interface related pins Figure 5 5 Timing Diagram of SCI Interface Negative Clock Interval between one SCEN assert and the next SCEN TcerrvL Figure 5 6 Timing Diagram of SCEN Interface When an interrupt occurs TCEON TSINTDIS INTA SCEN CA Figure 5 7 SINT Interface 37 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 6 Reset Time Vp
6. Data Description UNSUPPORTED_ATTRIBUTE Error occurred that indicates set data being too A 0x0 short The conditions for causing incorrect writing and the possible resultant operations are shown below regulations R SCEN negate timing Operation When SCEN is negated The command fails before completion of Operates normally at the next command and onwards transmission up to the All SET Command data commands When SCEN is negated after For a SET command the data write ends in failure and the ML9636 completion of transmission up asserts SINT After that when a read request is received the ML9636 to the Command data sends the command at the error occurrence and the error contents and negates SINT When SCEN is negated Since the data write fails the internal register is not updated before the SCLK rising edge The ML9636 asserts SINT and notifies the host of the write error at the eighth bit 8 When a read request is received the ML9636 sends the command at the error occurrence and the error contents and negates SINT Commande When SCEN is negated If the data write fails the ML9636 asserts SINT and notifies the host of where the immediately after the SCLK the write ao When a read request is received the ML9636 sends bara rising edge at the eighth bit the command at the error occurrence and the error contents and data bytes to when SCEN is negated negates SINT be setis 1 without
7. RX_QCO clock width 1 Trxacki 122 ns RX_QCO clock width 2 Trxacke2 Load capacitance 122 366 611 ns RX_QCO high pulse width TwackH C 50 pF 50 70 ns RX_QCO low pulse width TWOCKL 50 a ns RX_QDO output delay time Tapop 15 35 ns Notes All timings are measured at 20 and 80 of Vppro The DCLK clock frequency Fpc x is 2400 Hz 4800 Hz 3 MODEM RX ASK Interface Characteristics Vpp3 3 15 V to 3 45 V VppDi6 s 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit RX_ASKCO clock frequency Frxack 1 024 MHz RX_ASKCO high pulse width TwackH Load capacitance 440 540 ns RX_ASKCO high pulse width TwackL C 50 pF 440 540 ns RX_ASKDO output delay time Tapon 15 35 ns Notes All timings are measured at 20 and 80 of Vppro 4 MODEM TX Interface Characteristics Vpp3 3 15 V to 3 45 V VppDi6 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit TX_CI clock frequency FrxcK 4 096 MHz 7 z Load capacitance TX DI input setup time Trxps C 50 pF 15 ns TX DI input hold time ER a 15 ns Notes All timings are measured at 20 and 80 of Vppro Measuring Points 0 8VppI0 ye y 0 AT 0 8Vonio Measuring point 0 2v0010 47 0 2vppio 33 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics Trxack
8. 2 1 3 1 4 and 1 5 show the simplified pin structures that this IC has Table 1 2 Pin Structure 1 of 4 Type Symbol Pin structure RX ASKDO RX ASKCO RX_QDO RX_QCO Cc Z CAR_DET TX_DI TX_CI EE 5 TXW_N MOD_AQ RESET_N l Q Output enable signal 5 LOCK_DET SDIN SDO Q SCLK SINT SCEN a Input signal 5 o Input output pin DTEST1 DTEST2 sd E 2 Output signal a D Output enable signal Sec 2 3 3 Input signal B 2a Input output pin with pull down resistor OSCIN OSCOUT E o o Oscillator circuit T buffer cell 5 n O Oscillator pins The input protection circuits are not shown in the figures above ML9636GDZ45A User s Manual Chapter 1 Overview Table 1 3 Pin Structure 2 of 4 Type Symbol Pin structure LNA P LNA N LNA P Cc 3 cc LNA_N TX_P Cc a Lo TX_P LL aa IF_FIL1 IF_FIL1 Cc 3 D O d E lt IF_FIL2 IF_FIL3 IF_FIL2 O AOMHZ c amplifier ror D 2 z lt IF_FIL3 O generation circuit DET ASK Cc 2 5 demodulation D circuit 2 d Cc lt The input protection circuits are not shown in the figures above ML9636GDZ45A User s Manual Chapter 1 Overview Table 1 4 Pin Structure 3 of 4 Type Symbol Pin structure RSSI C RSSI signal Processing circuit Analog pin O RSSI_C LO1 Charge pump HO LO1 Analog pin lt LO2 z CO a
9. CarrierDet is detected CarrierDet detect rise time after switching from transmssion to 30 US reception Spurious emission level 30 dBm Note and circuits specified by OKT e Reception freguencies downlink D7 5775 MHz D6 5780 MHz D5 5785 MHz D4 5790 MHz D1 5795 MHz D3 5800 MHz D2 5805 MHz 32 The values in the table show characteristics which are calibrated and compensated using external components ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 5 4 2 Digital Characteristics 1 Modulation Demodulation Characteristics Vpp3 3 15 V to 3 45 V Vopi6 s 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Min Typ Max Unit Remarks QPSK demodulation section TRaDLY 2 0 us receive delay time 1 ASK lati i ASK demodulation section 0 pS Samou ation RAON used i TRADLY ASK demodulation section receive delay time 0 3 us skipped QPSK modulation section T 36 transmit delay time ee j E ASK modulation section transmit i TTADLY 3 2 us delay time QPSK demodulation section 95 425 i 5 8 GHz band frequency offset AFC characteristics PP resistance OF Stdemodulaiion section 32 48 Symbol Synchronous pulling in time clock recovery characteristics 2 MODEM RX QPSK Interface Characteristics Vpp3 3 15 V to 3 45 V Vopi6 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit
10. Chapter 7 Temperature correction Temperature correction for reception Temperature correction for transmission e Even during a continuous receiving state repeat the temperature measurement gt re setting the LNA_GAIN_ADJ and CAR_DET_LVL values then writing updating of the value of transmission power level operations taking temperature fluctuations in account e Do not start transmission before making temperature correction e If CAR_DET_LVL is set to an extremely small value CAR DET pin may be indicated as H even when there is no RF reception signal Figure H 4 Example of Procedure for Temperature Correction during Operation of ML9636 71 ML9636GDZ45A User s Manual Revision History Revision History Page Document No Date Previous Current Description Edition Edition PEUL9636 01 Jul 10 2007 Preliminary edition 1 Preliminary edition 2 Modify Chapter 5 PEUL9636 02 Oct 18 2007 74 72 Modify Chapter 7 Delete Appendix D Modify Appendix H Formal edition 1 Chapter 5 5 3 DC Characteristics Modify the DC FEUL9636 01 Jan 10 2008 72 72 characteristics of VIH2 and VIL2 5 4 2 5 SCI Characteristics Delete the characteristics of SCEN output enable time and disable time 72
11. G 2 1 3 Examples of Applicable Crystal ResonatorS see es ee ee ee RR ee ee Ee ee ee Re ee 66 G 2 2 When Configuring an External Clock as the Input to an Oscillation Circuit 66 G 2 2 1 Example of Configuring an External Oscillation CirCUit sesse ese ee ee ee ee Re ee ee 66 G 2 2 2 Notes on Configuring an External Crystal Oscillation Circuit iss ese ee ee ee 67 G 3 On Designing a High Frequency Circuit iese ese ee see ee ee ee ee ER Re ee ee AA rr rr rn 68 G 3 1 General Notes coi doin oa 68 G 3 2 High Frequency Circuit Design esse esse ee ee ee ee ee Re ee nor 68 H Register Setting Procedure est EE Ee gee Ee ee ge e BEE eds 69 H 1 Example of Activation Procedure at Power ON esse se ese ee ee ee Re ee ee AA ee AR Re ee RR ee ee ee ee ee ee Re 69 H 2 Example of Procedure at Power ShutdOWDN ees ee ees ee ee ee ee RR GRA ee ee AR Re ee ERA ee ee ee ee Re 70 H 3 Example of Procedure for Frequency Selection during OperatiON ees ese ese ee ee ee Re 70 H 4 Example of Procedure for Temperature Correction during OperatH ON ese ee ee ee ee 71 Revi SiOn ae ER EE A OR ON EN EE 72 Contents 2 ML9636GDZ45A User s Manual Chapter 1 Overview 1 Overview The ML9636GDZB5A Called ML9636 in following conforms to ARIB STD T75 dedicated short range communications DSRC system standard version 1 3 Itis an IC whose RF and MODEM sections are integrated into a single chip and can be
12. Loz O D ko a c lt LO_CLK S LO PLL o D ko a Cc lt VREF_DAC E DAC gt VREF_DAC QO g g D se The input protection circuits are not shown in the figures above ML9636GDZ45A User s Manual Table 1 5 Pin Structure 4 of 4 Chapter 1 Overview Type Symbol Pin structure VREF_RF E a g RF control circuit E D DO D oc RSSI_A RSSI output amplifier a Ee Circuit O RSSLA O w es lt x RFRX_C a D O RFRX_C 2 w eri hi The input protection circuits are not shown in the figures above ML9636GDZ43A User s Manual Chapter 1 Overview 1 3 4 Handling of Unused Pins Table 1 6 shows how unused pins of this IC should be handled Be sure to connect the other input pins than shown below to appropriate signal lines according to their use Table 1 6 Handling of Unused Pins Pin If unused connect to DTEST1 GND DTEST2 GND ATEST1 Open ATEST3 Open ATEST4 Open Notes e When left open a digital input pin may carry an excessive supply current e Never leave power supply pins or GND pins open The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip 11 ML9636GDZ45A User s Manual Chapter 2 MODEM Function 2 MODEM Function 2 1 DEMOD Interface RX Function 2 1 1 QPSK Demodulation Function The QPSK demodulation section demo
13. ON RX OFF timing value read request Host gt ML9636 OXA5 GET_TX_ON_ASK_ confirm TX ON RX OFF timing value read ML9636 gt HOST OxA6 GET_TX_OFF_ASK_request TX OFF RX ON timing value read request Host gt ML9636 OxA7 GET_TX_OFF_ASK_confirm TX OFF RX ON timing value read ML9636 gt HOST OxA8 GET RAMP RF ON ASK request RAMP RF ON timing value read reguest Host gt ML9636 OXA9 GET RAMP RF ON ASK confirm RAMP RF ON timing value read ML9636 HOST OXAA GET RAMP RF OFF ASK reguest RAMP RF OFF timing value read reguest Host gt ML9636 OxAB GET_RAMP_RF_OFF_ASK_confirm RAMP RF OFF timing value read ML9636 gt HOST OXAG GET RAMP MOD ON ASK reguest RAMP MOD ON timing value read reguest Host gt ML9636 OXAD GET RAMP MOD ON ASK confirm RAMP MOD ON timing value read ML9636 HOST OXAE GET RAMP MOD OFF ASK reguest RAMP MOD OFF timing value read request Host gt ML9636 OxAF GET_RAMP_MOD_OFF_ASK_confirm RAMP MOD OFF timing value read ML9636 gt HOST OxBO GET_TX_ON_QPSK_request TX ON RX OFF timing value read request Host gt ML9636 0xB1 GET_TX_ON_QPSK_confirm TX ON RX OFF timing value read ML9636 gt HOST 0xB2 GET_TX_OFF_QPSK_request TX OFF RX ON timing value read request Host gt ML9636 0xB3 GET_TX_OFF_QPSK_confirm TX OFF RX ON timing value read ML9636 gt HOST 0xB4 GET_RAMP_RF_ON_QPSK_request RAMP RF ON timing value read request Host gt ML9636 OxB5 GET_RAMP_RF_ON_QPSK confirm RAMP RF ON timing value read ML9636 gt HOST OxB6 GET RAMP RF OFF OPSK request RAMP RF OFF timing value read req
14. be set in each of T2_ASK T4 ASK and T6 ASK TO ASK is set on the BB LSI side The external PA control signal and the external ANT SW control signal are controlled from the BB LSI side Figure 2 5 Transmit Timing Diagram in ASK Mode 16 ML9636GDZ45A User s Manual Chapter 2 MODEM Function 2 3 Test Signal Generation Test Function This IC is equipped with a test pattern generating circuit Figure 2 6 shows the configuration of the test pattern generating circuit Data Clock Pattern setting Register setting Figure 2 6 Configuration of the Test Pattern Generating Circuit Table 2 1 lists the patterns that can be generated Each test pattern is transmitted by first writing a value for the test pattern to the register of the test command SET TEST SEND and then setting TXW_N L with a clock being input to TX_CI Table 2 1 Test Patterns That Can Be Generated Pattern Description CWO Transmits an ASK carrier off level equivalent continuous wave If QPSK mode is selected MOD_AQ L the neutral data origin signal of QPSK is transmitted CW1 Transmits an ASK carrier on level equivalent continuous wave If QPSK mode is selected MOD_AQ L the neutral data origin signal of QPSK is transmitted PN15 Transmits a random pattern PN15 continuously The data to be transmitted in ASK mode is the data after split phase coding X15 X14 1 is used as the generating polynomial and an inve
15. command SET_DEMOD_SET In this case no split phase will be decrypted nor will clock ASK_CO be output only data ASK_DO will be output 13 ML9636GDZ43A User s Manual Chapter 2 MODEM Function 2 2 MODEM Interface TX Function This IC performs ASK modulation and 7 4 shift QPSK modulation as transmission TX side functions Switching between ASK and QPSK is made by the MOD_AQ signal sent from the baseband LSI BB LSI The TX_CI clock input has a frequency of 4 096 MHz bon in QPSK mode and in ASK mode Since the TX_CI clock serves as the reference clock of the digital processing section of the IC do not stop clock input even during the period other than during transmission Figure 2 3 shows the relationship between the timing signal generating circuit and the blocks to be controlled during transmission The RF signal transmission is triggered by the TXW_N signal from the BB LSI Note that it must be done from the BB LSI to switch between transmission and reception at the external ANT SW or have on off control of the external PA Transmit receive switching On Off Transmit B enable Register setting External PA control signal External ANT SW control signal Figure 2 3 Block Diagram of Timing Control Function at Transmission The following timing diagrams shows the relationships between the data clock during data transmission the transmit receive circuit enable signal on off signal the Ramp_RF signal and the Ra
16. curve into the nonvolatile memory 50 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics UA AO AA issi External 4 External 1g External Se ies Variable gain Modulation Antenna pin ANT filter ah Sw PA PA driver amplifier circuit y TPC_ASK AMPL_ADJ Measure the transmission TPC_QPSK _AMPL_ADJ output power Q_AMPL_ADJ e g 10 dBm S J Sy Measure the register values that produce the predetermined value 10 dBm for example of the transmission output power at room temperature Determine the TPC and AMPL ADJ registe settings that correspond to the setting No by Setting using a combination of two commands number A 1 e ae ARE ane Standard temperature Ho fee ca anes Pl correction curve nn eee yy7 dotted lines L a aa yy6 A a ET ss EE r yy4 T yy3 1 Sd this curve by translating the ai i standard temperature curve by the h i amount of difference A between the yy2 ee e for setting numbers at room temperature each individual Set lid li i 30 C 15 C Solid line 59c Normal 45 C 75 C 85 C temperature Figure 7 4 Creation of a Temperature Correction Curve for a Set 7 1 5 Correcting Temperatures during the Operation of a Set After power is applied to a Set user applied board and the Set is initialized measure the temperature using a thermistor etc periodically calculate the register setting values appropriate f
17. observing the interface If SINT is not asserted it indicates that the data write has succeeded However whether the set value is correct is not guaranteed When the number of SCLK clock pulses is larger than the number prescribed for the command The data write succeeds and setting in the register is performed normally The excessive clocks and data are ignored 23 ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function ve ek SCEN negate timing Operation When SCEN is negated Since the data write fails the internal register is not updated before the SCLK rising edge The ML9636 asserts SINT and notifies the host of the write error at the first bit in the second When a read request is received the ML9636 sends the command at byte DATA1 the error occurrence and the error contents and negates SINT When although transmission Writing of the data DATAO at the first byte is effected and DATAO is was done normally up to the updated However DATA1 is not updated because writing of the data first bit SCLK rising edge in at the second byte ends in failure the second byte DATA1 The ML9636 asserts SINT and notifies the host of the write error SCEN is negated before the When a read request is received the ML9636 sends the command at Commands _ transmission of the eighth bit the error occurrence and the error contents and negates SINT whe
18. 0 011101 011101 011110 011110 011111 011111 Approx 0 1 dB Center value Approx 0 1 dB Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above Same as above 43 Same as above ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics In the explanations below the TPC register when used in ASK mode denotes the TPC_ASK register and when used in QPSK mode it denotes the TPC_QPSK register Likewise the AMPL_ADJ register means in ASK mode the AMPL_ADJ register and in QPSK mode the I AMPL_ADJ and O AMPL ADJ registers The TPC register has an adjustment resolution of about 1 dB and the AMPL_ADJ register about 0 1 dB By fine adjusting each adjustment step of the TPC register with respect to the AMPL_ADJ register settings a desired adjustment resolution can be achieved Since the AMPL_ADJ register variable width is greater than the adjustment width per step of the TPC register all the AMPL_ADJ settings are not used for normal operation For adjustment a list of combinations of the TPC and AMPL_ADJ settings is used where the transmission power of the ML9636 varies at roughly the same widths monotonously Table 7 2 being the standard table prepared by OKI In Table 7 2 decimal values are used for the TPC and AMPL_AD
19. 636 DET pin RSSI_A pin 1 Depending on the mounting conditions the value of the parallel capacitor needs to be adjusted so that the reception characteristics will be optimized Figure F 1 Example of Slice Level Adjustment Circuit Configuration 63 ML9636GDZ45A User s Manual Appendixes G Notes on Hardware Design G 1 When Designing Power Supplies G 1 1 Power On Sequence When power is turned on apply power to the 1 6 V power supplies and the 3 3 V power supplies either at the same time or the 1 6 V power supplies first In doing so make the time difference between the power suppliy turned on first and those turned on later within 1 ms After power on satisfy the regulations as to the reset time specified for the RESET_N pin If the recommended voltage is exceeded at startup be sure not to release the reset state G 1 2 Bypass Capacitor Insertion G 1 2 1 Example of Bypass Capacitor Insertion It is recommended that bypass capacitors be inserted in each of the VDD GND lines as shown below ML9636 VDD_RFPLL VDD_DPLL VDD_CORE The capacitors should be located adjacent to the IC pins It is preferable to separate the wiring from the board pins Figure G 1 Example of Wiring around the ML9636 Power Supplies 64 ML9636GDZ45A User s Manual Appendixes G 1 2 2 Notes on Inserting Bypass Capacitors Not the following when inserting bypass cpapacitors e For the wiring for VDD and GND use wider wires t
20. 9636 01 A Separate Volume for the ML9636 User s Manual Command Details FEUL9636CMD 01 This user s manual describes the operation of the ML9636 ML9636GDZ45A User s Manual Notation Notation Classification e Numeric value e Address e Unit e Terminology e Register description Read write attribute MSB LSB Notation Oxnn Oxnnnn_nnnn word WORD byte BYTE mega M kilo K kilo k milli m micro u nano n second s lower case H level L level Description Indicates a hexadecimal number Indicates a hexadecimal number represents Oxnnnnnnnn 1 word 32 bits 1 byte 8 bits 10 210 1024 10 1000 10 10 10 second Indicates high voltage signal levels Vy and Vou as specified by the electrical characteristics Indicates low voltage signal levels Vi and Voz as specified by the electrical characteristics R indicates a readable bit and W indicates a writable bit Most significant bit of the 8 bit register memory Least significant bit of the 8 bit register memory Register name 1 EET ii ii TE Ee Bit name I i I 1 i 1 j I 1 i I N I 1 1 I i I 1 N I 1 1 1 i I N 1 1 1 1 i I I N 1 I 1 1 I I 1 1 j 1 1 I 1 I 1 j 1 I i I 1 1 l i 1 j I 1 I N I 1 I i I I N I 1 I 1 I N 1 i 1 1 1 I N I 1 7 6 5 4 3 2 1 0 MCR MMA OW
21. INT The host must confirm that the SINT signal has been asserted and then execute the read request read output enable Figure 3 8 shows the timing diagram for read A simultaneous operation of a read and a write is also possible Figure 3 9 shows the timing diagram when performing a read and a write simultaneously sint Mm scen sek _JU UU UU UWL TUU UL UUUUUUL UUW UU TUUUUUUU UUUUUUUL _ sdin QQ AY WA AAW Request GET_reques Request sdo U ASSY ES MSS Status Status GET_confirm Data0 Data1 Figure 3 8 Timing Diagram for Read sint no scen ad sek TUUUUUUUL TULL UU LL MUTUA TUUUUUUU UUUUUUL UUUUUULUL sdn AQAA SSS SEA W Request GET_request Request SET Data0 Data sdo WAAAY AY Status Status GET_confirm Data0 Data Figure 3 9 Timing Diagram for Read and Write when read and write are simultaneously performed 25 ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function The conditions for causing incorrect reading and the possible resultant operations are shown below
22. J register values and the correspondences with the bits are shown in Tables 7 3 and 7 4 In Table 7 2 the setting No 0 indicates the setting for the lowest transmission power The flowchart below shows the calculation procedure for calculating the setting values for the transmission power adjustment registers above The procedure needs to be taken for ASK mode and QPSK mode separately Each step in the procedure is described in details in Sections 7 1 3 to 7 1 5 Based on the standard temperature correction curve for the ML9636 and with reference to the temperature characteristics of the external lt circuit of the Set user applied board and the transmission output Carry out the process once upon design of power specifications of the Set create a standard temperature each Set user applied board correction curve exclusive to the Set o Jl Measure the register values at room temperature that produces the transmission output power predetermined for the Set when in a transmitting state of the Set _ Carry out the process once upon production of each Set Correct the variation of parts from Set to Set Create temperature correction curve data for the Set and store it into the nonvolatile memory in the Set Il Measure the temperature calculate the register setting values appropriate for the measured value with reference to the temperature od correction curve data then write it to the temp
23. K 9 e BEE O Oo O o 16V power 3 3 3V power 1 5 1 sli ver power 1000p 0 01 1 5k 100p a 16MHz clock 1 6Vpp Input 1 In the figure the bypass capacitor for each power supply and the one for the VREF_RF pin have been omitted 2 Determine the peripheral circuit constants 3 The circuit and constants between pin 42 and pin 40 show examples when used in combination with the filter MKFCC40MOCCOPOOROS or MKFCC40MOCDOPOOROS manufactured by MURATA Manufacturing If another filter is used it is necessary to change the circuit and constants because of the input output impedance of a filter Figure E 1 Example of External Circuit Configuration 62 ML9636GDZ45A User s Manual Appendixes F Example of Improving the demodulation tracking characteristics with respect to a sudden change in the bottom level of a input modulation signal This section gives an example of an improvement in the demodulation tracking characteristics with respect to a sudden change when there is a large difference between the 500 kHz component and 1 MHz component in the bottom level of a input modulation signal during the ASLK receive operation of the ML9636 As shown in the figure below the slice level can be optimized by connecting a resistor and a capacitor between the RSSI_A pin and the DET pin In that case it may be necessary to optimize the external components and comparator slice level SET_RF1 command ASK_SLICE_OFS 2 0 bits ML9
24. MDET time constant SAW External 100 ppm RSSI time constant O O OO O O ML9636 O RESET input OSC O DTEST setting input gt ATEST for testing a be QPSK Q LNA 1st Mix IF Amp vis i ome ES QPSK demodulation output NY fe ASK el ASK demodulation output AM Det E mad J C gt CARRIER detect output scl nar 5 8 GHz Kt Serial interface BPF ANT LO sw O LOCK detect output External ASK QPSK Va D Mod Q QPSK ASK modulation PA VGA Mod LPF DAC O TXW_N input a ey i 0 ASKOPSK mode input O 4M CLK 4 096 MHz 100 ppm Logic section PLL O O Note Use the Baseband LSI to switch between LO PLL transmission and reception for the external ANT time 16 MHz 20 ppm SW and have on off control of the external PA constant Figure 1 1 Block Diagram of ML9636 ML9636GDZ43A User s Manual Chapter 1 Overview Table 1 1 Functional Summary of Each Block LNA Low noise amplifier RX 1st Mix 1st receive mixer IF Amp Intermediate frequency amplifier RX 2nd Mix 2nd receive mixer OSC Oscillator for 2nd mixer 31 808 MHz AM Det RSSI Amplitude detect RSSI carrier detect LO Local oscillator VGA Variable gain amplifier ASK QPSK Mod ASK QPSK modulation LPF Low pass filter VO DAC Digital to analog conversion for VO QPSK Demod QPSK digital demodulation ASK Demod A decoding for split phase of 1024kbps and a clock recovery for ASK D Mod Digital modulation includes split phase coding of 1024kbps for ASK Logic se
25. No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof The products listed in this document are intended for use in general electronics equipment for commercial applications e g office automation communication equipment measurement equipment consumer electronics etc These products are not unless specifically authorized by OKI authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property or death or injury to humans Such applications include but are not limited to traffic and automotive equipment safety devices aerospace equipment nuclear power control medical equipment and life support systems Certain products in this document may need government approval before they can be exported to particular countries The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these No part of the contents contained herein may be reprinted or reproduced without our prior permission Copyright 2008 Oki Electric Industry Co Ltd ML9636GDZ45A User s Manual Preface Preface The ML9636GDZ45A User s Manual consists of the following two documents ML9636GDZ45A User s Manual FEUL
26. OK I Open up your dreams FEUL9636 01 ML9636GDZ45A User s Manual Issue Date January 10 2008 NOTICE 1 The information contained herein can change without notice owing to product and or technical improvements Before using the product please make sure that the information being referred to is up to date The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product When planning to use the product please ensure that the external conditions are reflected in the actual circuit assembly and program designs When designing your product please use our product below the specified maximum ratings and within the specified operating ranges including but not limited to operating voltage power dissipation and operating temperature OKI assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse neglect improper installation repair alteration or accident improper handling or unusual physical or electrical stress including but not limited to exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range Neither indemnity against nor license of a third party s industrial and intellectual property right etc is granted by us in connection with the use of the product and or the information and drawings contained herein
27. Pin Descriptions The pin shown as O in the I O column in the table in Section 1 3 2 Pin Descriptions When 7 dBm is transmitted from the TX_P pin SUELO 30 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 5 4 AC Characteristics 5 4 1 RF Characteristics Vpp3 3 3 V VpDi6 1 6 V Ta 25 C Parameter Condition Min Typ Max Unit LO characteristics LO lock up time 500 us Transmit characteristics TX_P pin A y When the maximum output is set 7 dBm T t PAd tput En AE When the minimum output is set 18 dBm Variation fi f TP Transmit power control slope enel ep E ie 8 aot 0 7 2 5 dB The RF synthesizer reference frequency Center frequency tolerance should have an accuracy specified by 20 20 ppm the recommended operating condition ASK f fc 5 MHz PA driver output 7 to 18 dBm i dee ASK f fc 10 MHz Adjacent channel leakage power ed Oui OTIS dB 7 ai QPSK _ f fc 5 MHz PA driver output 7 to 18 dBm dee QPSK Jf fc 10 MHz PA driver output 7 to 18 dBm 30 des QPSK z EVM PA driver output 7 to 18 dBm _ 6 da ASK time 85 e o PA driver output 7 to 18 dBm j Eye aperture ratio ASK amplitude PA driver output 7 to 18 dBm pe mm So ds A ASK Mogulanon index PA driver output 7 to 18 dBm ee m n mm Leakage power at carrier off 44 dBm Image leakage lo
28. Q 4 EE i p TXW_N a l The Transmission enable and Ramp_RF actually get delayed by 0 5 us inside the IC Ramp_RF The Ramp_Mod signal Ramp_Mod becomes a signal to enable TX_DI Internal TX_P output State of ML9636 _Preheating Afterheat Reception I 1st half of Ramp 2nd half of Ramp l 1st half of Ramp l 2nd half of Ramp Example of ML9636 register settings Setting value TX_ON_ASK T1 0x00 0 ms TX_OFF_ASK T2 0x28 9 76 ms RAMP_RF_ON_ASK T3 0x50 19 53 ms RAMP_RF_OFF_ASK T4 0x10 3 90 ms RAMP_MOD_ON_ASK T5 0x50 19 53 ms RAMP_MOD_OFF_ASK T6 0x00 0 ms Figure B 2 Example of Setting ASK Transmit Timing 59 ML9636GDZ45A User s Manual Appendixes Figure B 2 shows the timing of the BB LSI and the ML9636 during ASK data output and example of settings for the ML9636 registers for timing adjustment The ML9636 requires a preheating time for the PA section of the transmit RF section A preheating time of about 20 us is assumed in th figure above Because of this residual heat time configure timing settings so that the TXW outpu from the BB LSI will be enabled L 20 us ahead of the head of the PR bit of the transmit data TX_DI When the TXW signal is output 20 us ahead of the head of the PR bit from the BB LSI transmit data TX DI can be received at the correct timing by setting T5 to 20 us The preheating time mentioned abo
29. QPSK 14 20 us ASK receive stabilization time TSTABLE ASK gt 3 us 1 Indicates reference data that is in effect when the RSSI_C pin capacitance value is 1000 pF As this capacitance value is made smaller the carrier detect signal rise time and fall time will get shorter However in that case note that the carrier detect signal may go on and off uselessly 2 Note that the carrier detect signal rise time changes depending on the RSSI_C capacitance CAR_DET_LVL setting or power supply voltage 3 Standard condition When a no modulation wave is input with Vppis 1 6 V Vpp3 3 3V and CAR_DET_LVL 256 decimal value RF signal Carrier detection signal Bees AAA EE Receive DATA PS EEN MEN N Ed Valid data TCDET TSTABLE JO Figure C 1 RF Burst Receive Timing 61 ML9636GDZ45A User s Manual Appendixes E Example of External Circuit The following figure shows an example of external circuit configuration for the ML9636 3 3V power 1 6V power ss O 1 0 Unit e Tiss a di output pin Resistor Q O Capacitor iF 1000p 0 01 AA Inductor tH O ak power 4 OS RX_ASKCO 6 5 4 N 21 SAW filter RX ASKDOI ML9636 Digital Interface VDD PADRV RFRX_C LNA_N crystal Matching circuit LNA_P VDD_CORE Rx input pin VDD_DPLL O 1 6V power Ee I E 1 8 n E x ej a 5 2 H g9 5 27 sa x O UI o a a a l 8 1 a E 9 Q 898 9 2 E E H
30. TRQ RCS EIR EIT ERM ARES RW Initial value 0 0 0 0 0 0 0 0 I l i I 1 I N I i 1 I i I N I I l l N I I 1 I 1 1 1 1 1 I N I I 1 I N N I I I N l I I f 1 l I i I I I 1 j I l N I I I l i i i i 1 1 1 i 1 ae A RILLER DAE LE IO AE hte Initial value after reset 11 ML9636GDZ45A User s Manual Table of Contents Table of Contents A AE ME EE AR EE RE ET N N ES i 1 OVERVICW ME ere eR TE N EE ER EE ey a 1 MEN MEE EE EE EE OR EK N EE tteeany ioe 1 PEN ea dele n ER ME RE N EE dt 2 EO RO RE OR EE EE OR ER ean eee 4 1 3 1 bere aile de ele AE EE A A ASA 4 1 32 Pini Descriptions EIER EERS R EES ee RE ee ER ee ii td 5 133 PiN SUTU E a N DE EE etn Ai edd AE EE 7 13 4 Handling ef Unused PINS is EE EER ae edie ice EE Ee Ee a 11 2 MODEM UNC ie RE EE EE EE KA GR EE EE aad 12 2 1 DEMOD Interface RX FunCION esse ese ee ese ee ee Re a AE Ge ee AE Ge ee ee ee Ee ee ee ee ee 12 2 1 1 QPSK Demodulation FUNCION 00 cee cet ee ee ee ee Re ER AA AR ee ER RA RA ee ee AR Re ee ER RA ee ee ee ee Re ee 12 2 12 ASK Demodulation FUNGI ON se EE Eg ee en Ge Oe de EED Ee ES ASe GEED ee Ede ge ee ER GEES se ee Deed 13 2 2 MODEM Interface TX FUunCION ee ees ee ee ee ee ee ee Re Re Re Re Re Re Re e Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re Re ke ee 14 2 3 Test Signal Generation Test FUNCION ee ee ee RR AA ee ER Re RA ee rre 17 3 Synchronous C
31. VCO Power supply pin for RF VCO 1 6 V typ 4 VDD_CP Power supply pin for RF CP 1 6 V typ 36 VDD_IF Power supply pin for IF and MOD 3 3 V typ 44 VDD_PADRV Power supply pin for PA drivers 3 3 V typ 13 VDD_DPLL Power supply pin for digital PLL 1 6 V typ 14 VDD_CORE Power supply pin for digital CORE 1 6 V typ 24 VDD_IO Power supply pin for digital lO 3 3 V typ 18 GND_IO Ground pin for digital IO Ground on the package rear side De GND Ground for the analog section and digital core section on the rear N side 1 VO definition IRF RF input pin la Analog input pin Digital input pin Ip Pulled down digital input pin los Oscillator circuit input pin Orr RF control output pin Oa Analog output pin O Digital output pin Oos Oscillator circuit output pin 2 Do not stop the 16 MHz input while the ML9636 is operating 3 Since TX_CI serves as the reference clock of the digital circuits do not stop it all the time 4 The 3 3 V supply should be used for VDD_IO VDD_IF and VDD PADRV and the 1 6 V supply for VDD_RF VDD_VCO VDD_CP VDD_RFPLL VDD_DPLL and VDD_CORE Never leave the power supply pins or the GND pins open The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip ML9636GDZ43A User s Manual Chapter 1 Overview 1 3 3 Pin Structure Tables 1
32. _ADJ 1 AMPL ADJ and Q_AMPL_ADJ registers write a correction value calculated by the method explained in Sections 7 1 2 to 7 1 5 to each of these registers periodically based on the ambient temperature measurement result 42 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics 7 1 2 Outline of the Method of Setting Transmission Power Adjustment Registers TPC Register AMPL_ADJ Register In ASK mode transmission output is corrected using a combination of the TPC_ASK register and AMPL_ADJ register In QPSK mode transmission output is corrected using a combination of the TPC_QPSK register 1 AMPL_ADJ register and O AMPL_ADJ register Normally set the I AMPL_ADJ register and the Q_AMPL_ ADJ register to the same value Table 7 1 shows the outline of coding for the registers refer to Chapter 4 and the separate volume Table 7 1 Transmission Power Adjustment Registers TPC Register AMPL_ADJ Register ASK mode SET_HDAC_ASK command AMPL_ADJ 5 0 bits QPSK mode SET_HDAC_QPSK1 command command SET_HDAC_QPSK2 command TPC_QPSK 3 0 _ AMPL_ADJ 5 0 bits bits Q_AMPL_ADJ 5 0 bits Coarse adjustment Fine adjustment 111111 SET_TPC command TPC_ASK 3 0 bits SET_TPC Output power Coarse adjustment Fine adjustment 111111 111110 111110 111101 111101 1 00010 1 00010 1 00001 100001 Approx 0 1 dB 0 00000 000000 Center value 0 00001 000001 Approx 0 1 dB 0 00010 0 0001
33. al Appendixes G 2 1 2 Notes on Configuring a Crystal Oscillation Circuit Note the following when configuring a crystal oscillation circuit e The respective values of C1 C2 and R1 need to be set according to the specifications of the crystal resonator Crystall used In determining those values evaluate the oscillation characeristics using the resonator having the target frequency on the mounting board and using the actual IC by such means as making a request to a manufacturer of crystal resonators e Ensure an accuracy of 100 ppm or less for the 31 808 MHz master clock while taking temperature fluctuations power supply voltage fluctuations and aging into account e Do not make any signal line cross over the external wiring pulled out from the OSCIN and OSCOUT pins Also do not wire any signal line that carry a large current near the external wiring pulled out from the OSCIN and OSCOUT pins Surround the periphery of the pins and external components by GND patterns as much as possible so as to make the patterns less subject to noise interference e Make the ground point of the capacitors of the oscillation circuit alway have the same potential as GND and do not connect it to a GND that carries a large current e Do not supply any signal to another oscillation circuit from this oscillation circuit G 2 1 3 Examples of Applicable Crystal Resonators The table below lists the applicable crystal resonators OKI does not provide any guarant
34. al SAW filter Receive RF section CarrierDet circuit CAR_DET_LVL Setting value 30 C 15 C 15 C 45 C 75 C 85 C a Temperature Figure 7 9 Creation of a Temperature Correction Curve for a Set 54 ML9636GDZ43A User s Manual Chapter 7 Temperature Correction for RF Characteristics 7 2 5 Correcting Temperatures during the Operation of a Set After power is applied to a Set and the Set is initialized measure the temperature periodically calculate the register setting values appropriate for the measured value with reference to the temperature correction curve data then write it to the temperature correction registers How often the temperature correction registers are to be set depends on the temperature distribution inside the Set or the rate of temporal temperature change In the ML9636 frequency at about tens of seconds is assumed Do not write to the temperature correction registers during burst signal reception ML9636 CAR_DET_LVL search 350 340 I 1 I 1 I L I I I I I I I I I I A p 330 eo N o CAR_DET_LVL o 280 30 25 20 15 10 5 O 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Temperature degreeC gt TargetRFLevel 61dBm TargetRFLevel 64dBm TargetRFLevel 674Bm Figure 7 10 Standard Values of CAR_DET_LVL When Setting the Carrier Detection Level to 61 64 and 67 dBm Reference Data 55 ML9636GDZ45A User s M
35. anual Appendixes Appendixes A SCI Timing Specifications Reference Values A 1 Internal Register Update Timing at Write Reference Values Figure A 1 shows the internal register update timing for SCLK at the time of writing by SCI If the length of the setting data is one byte the update timing is the same as DATAL1 update timing in the figure The update timing in the table below shows the timing of LSI internal operation and the values shown in the table are for reference only Vpp3 3 15 V to 3 45 V Vopi6 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit Internal register update time TRENEW 190 ns SCEN DATAO update SCLK timing SDIN DATA1 update SDO Wii NN timing Request Status Command Data0 SCEN SCLK SDIN BITS6 1 TRENEW Internal register O Data before update Internal register 1 Data before update X DATA1 Figure A 1 Internal Register Update Timing at Write Setting Data 2 Bytes 56 ML9636GDZ45A User s Manual Appendixes A 2 SINT Assert Timing at Read Reference Values The SINT assert time reference values at read is shown below Figure A 2 shows the timing of SINT assert after SCEN negate at read by the GET_request command Figure A 3 shows the timing of SINT reassert when two read data items are retained Vpp3 3 15 V to 3 45 V VpDi6 1 5 V to 1 65 V Ta 30
36. aximum of 611 ns see the upper diagram of Figure 2 2 and a minimum of 122 ns see the lower diagram of Figure 2 2 ML9636GDZ43A User s Manual Chapter 2 MODEM Function 2 INN Internal data dataq qo ql q2 Trxack fe 122 ns TRXQCK2 611 ns rd d RX_QCO E ll KA RX DO doo Dot oil Dt D20 D21 When timing adjustment occurs and the RX_QCO width reaches its maximum o IAN Internal data data_i 0 11 i2 TRXQCK1 122 ns Trxock2 122 ns 2 048 MHz gt EP gt RX_QCO sd RX_QDO Doo Dot D10 D11 D20 D21 D30 When timing adjustment occurs and the RX_QCO width reaches its minimum Figure 2 2 Timing Adjustment at Synchronous Pulling In 2 1 2 ASK Demodulation Function The ASK demodulation section has a decryption function for split phase of 1024kbps and a clock recovery function and outputs a 1 024 MHz clock In the clock recovery function timing adjustment is performed at synchronous pulling in or at detection of a frequency drift compared with roadside unit therefore the output clock RX_ASKCO may change When no carrier signal is detected CAR DET L data and clock outputs go L This masking function can be disabled using a register setting command SET_DEMOD_SET While the IC is transmitting TX data demodulation data and clock outputs stop and go L In addition the ASK demodulation function can be disabled using a register setting
37. cal harmonic PORE components and RF output harmonic 32 dBm Spurious emission intensity components Others 44 dBm Burst transmit transient response time ae ple S 5 us Note and circuits specified by OKI Spurious emmision at transmissio needs to be attenuated using an external filter e Transmission frequencies uplink U7 5815 MHz U6 5820 MHz US 5825 MHz U4 5830 MHz Ul 5835 MHz U3 5840 MHz U2 5845 MHz 31 The values in the table show characteristics which are calibrated and compensated using external components ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics Vpp3 3 3 V Vopi6 1 6 V Ta 25 C Parameter Condition Min Typ Max Unit Receive characteristics LNA_P and LNA_N pins Receiver sensitivity QPSK BER 1E 5 or less 75 dBm ASK BER 1E 5 or less 68 dBm Maximum input level QPSK BER 1E 5 or less 25 dBm ASK BER 1E 5 or less 33 dBm RSSI_A output voltage 1 RF input 73 dBm 0 8 V RSS _A output voltage 2 RF input 33 dBm 2 2 V Time taken for the RSSI output to reach RSSI detect rise time 1 dB of the final value after switching 30 us from transmssion to reception Upper limit of CarrierDet setting range When the upper limit is set 58 dBm Lower limit of CarrierDet setting range When the lower limit is set 73 dBm Time taken until
38. ch of T2_QPSK T4_QPSK and T6_QPSK TO_QPSK is set on the BB LSI side The external PA control signal and the external ANT SW control signal are controlled from the BB LSI Figure 2 4 Transmit Timing Diagram in QPSK Mode 15 ML9636GDZ45A User s Manual Chapter 2 MODEM Function At ASK TX Cl 4 096 MHz y Vv Vv Vv Vv Y Yy Vv Vv Vv vi PR preamble End of CRC TX_DI ASK mode I MOD AG TO_ASK TXW_N j l E T2_ASK T1 ASK Receive circuit enable oe Transmit circuit enable T3_ASK BB Ramp_RF po E E T6 ASK gt T5_ASK Ramp_Mod o External PA control signal External ANT SW E i control signal Delay in transmit section Delay in transmit section 1 E 3 H E i i Status of Reception Preheat Ramp up Ramp up Transmitting preamble Ramp down Ramo Reception ML9636 1st half 2nd half 1st half 2nd half A value of 0 to 255 cycles approx 62 us at an equivalent clock frequency of 4 096 MHz can be set in each of T1 ASK T3_ASK and T5 ASK A value of 0 to 63 cycles approx 16 us at an equivalent clock frequency of 4 096 MHz can
39. code 0x90 GET_CAR_DET_LVL_request Carrier detection level setting value read request Host ML9636 0x91 GET_CAR_DET_LVL_confirm Carrier detection level setting value read ML9636 gt HOST 0x92 GET CAR _DET_CTL request Carrier detection hysteresis width adjustment Host gt ML9636 value read request 0x93 GET CAR DET CTL confirm Carrier detection hysteresis width adjustment ML9636 gt HOST value read 0x94 GET INIT READ request This command is canceled Host gt ML9636 0x95 GET_INIT_READ_confirm This command is canceled ML9636 gt HOST 0x96 GET RFO request RF section adjustment O value read request Host gt ML9636 0x97 GET_RFO_confirm RF section adjustment 0 value read ML9636 gt HOST 0x98 GET_RF1_request RF section adjustment 1 value read request Host gt ML9636 0x99 GET_RF1_confirm RF section adjustment 1 value read ML9636 gt HOST Ox9A GET_RF2_request RF section adjustment 2 value read request Host gt ML9636 0x9B GET_RF2_confirm RF section adjustment 2 value read ML9636 gt HOST 0x9C GET_RF3_ request RF section adjustment 3 value read request Host gt ML9636 0x9D GET_RF3_confirm RF section adjustment 3 value read ML9636 gt HOST OXAO GET DEMOD request DEMOD section settings read reguest Host gt ML9636 OxA1 GET DEMOD confirm DEMOD section settings read ML9636 HOST OxA2 GET TEST SEND reguest Paad e OSO Host ML9636 patterns for transmission OxA3 GET_TEST_SEND_ confirm Read generalon setings oftest panema To reeds HOST transmission 0xA4 GET_TX_ON_ASK_request TX
40. comes a signal to enable TX_DI Ramp_Mod Hee dus 1 Ps i i l Doa oOo TX_P output i N MDG oe 36us MP 1 4 ys 2 6 us tt State of ML9636 Preheating NEIET 1sthalfof Ramp 2nd half of Ramp sthalfofRamp 2nd halfof Ramp O Ramp bit Example of ML9636 register settings Setting value TX_ON_QPSK T1 0x00 Ops TX_OFF_QPSK T2 0x20 7 81us RAMP_RF_ON_QPSK T3 0x5C 22 45 us RAMP_RF_OFF_QPSK T4 0x14 4 88 us RAMP_MOD_ON_QPSK T5 0x50 19 53 us RAMP_MOD_OFF_QPSK T6 0x00 0 us Figure B 1 Example of Setting QPSK Transmit Timing Figure B 1 shows the timing of the BB LSI and the ML9636 during QPSK data output and example of settings for the ML9636 registers for timing adjustment The ML9636 requires a preheating time for the PA section of the transmit RF section A preheating time of about 20 us is assumed in th figure above Because of this residual heat time configure timing settings so that the TXW outpu from the BB LSI will be enabled L 20 us ahead of the head of the Ramp bit of the transmit data TX DI When the TXW signal is output 20 us ahead of the head of the Ramp bit from the BB LSI transmit data TX_DI can be received at the correct timing by setting T5 to 20 us The preheating time mentioned above refers to the time required to stabilize various fluctuations associated with a change in power supply voltage caused by activation of t
41. ction PLL PLL for the logic section generates the clock based on 4M CLK SCl Serial interface used to configure settings for registers ML9636GDZ45A User s Manual Chapter 1 Overview 1 3 Pins 1 3 1 Pin Configuration O LL lt u o lt q Fy 9 E o 6 3 G amp 4 8 6 z to a ep Yn oa a kE E Q Q O Q gt E oO o v 36 35 34 33 32 31 30 29 28 27 26 25 DET 24 VDD_IO ATESTA 8 23 RX_QCO ATEST3 _b9 22 RX_QDO IF_FIL2 21 RX_ASKCO IF_FIL3 IF FIL TX_P VDD_PADRV l44 RFRX_C Jas 16 OSCOUT LNA_N 15 JOSCIN LNA_P Top View 14 VDD_CORE O VDD_RF o k ine TX_Cl TX DI ATESTI 7 Lo2 J qe Ee Loi ry O e TEW NL m E m VDD_RFPLL LO_CLK VDD_VCO VDD_CP MOD_AQ LOCK_DET 48 Pin WQFN Top View The actual pads are not visible since this pin configuration shows the top view Figure 1 2 Pin Configuration of ML9636 Note The exposed die attach pad must be connected to a solid ground plane as this is the ground connection for the chip ML9636GDZ45A User s Manual Chapter 1 Overview 1 3 2 Pin Descriptions State Active Pin Symbol VO 1 Description at reset level RF related pins 47 LNA_P IRF Receive antenna input pin P 46 LNA_N IRF Receive antenna input pin N 43 TX_P Orr Output pin P to transmit PA 42 IF FIL1 Oa Output pin for the external 40 MH
42. dulates the QPSK signal and regenerates clocks Figure 2 1 shows the data and clock waveform during normal output for the QPSK demodulation function The QPSK demodulation performs modulation in units of symbols and as shown in the figure below produces a 2 bit output at 2 048 MHz for normal output When no carrier signal is detected CAR_DET L data and clock outputs go L This masking function can be disabled using a register setting command SET_DEMOD_SET While the IC is transmitting TX data demodulation data and clock outputs stop and go L wema INN 32 768 MHz Internal data i A AMA 2 Internal dataa EEN N GE a q2 TRXQCK1 122 ns TRXQCK2 366 ns 2 048 MHz 4 RX_QCO RX_QDO Doo Do1 to DI D21 Figure 2 1 QPSK Demodulation Data and Data Clock Timings The QPSK demodulation section of the IC has a function to pull in frequency synchronously At synchronous pulling in or at detection of a frequency drift compared with the roadside unit timing adjustment is performed therefore the output clock RX_QCO may change Figure 2 2 shows the output timing waveforms when a frequency drift is the largest in cases where timing adjustment occurs backwards upper diagram and timing adjustment occurs forwards lower diagram The output width of the 2nd bit of the one symbol that is demodulated is normally 366 ns as shown in Figure 2 1 however if timing adjustment occurs the width is a value between a m
43. e 3 4 ML9636 gt Host Data Read GET command 21 ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 3 3 Setting Write Data Use the SET command to write a setting value from the host to the ML9636 Register setting to the ML9636 can be achieved by setting bit 3 of byte 1 to 1 and writing a setting value to byte 2 onwards using the SET command and sending the data to the ML9636 from the host The internal register update timing varies depending on whether the length of the setting data is two bytes or one byte If the length of setting data is two bytes the update timing for DATAO is hundreds of nanoseconds after the first rising edge of SCLK of the subsequent DATA transmission and the update timing for DATA is hundreds of nanoseconds after the SCLK rising edge at the eighth bit of DATA Meanwhile if the length of the setting data is one byte the update timing is hundreds of nanoseconds after the SCLK rising edge at the eighth bit of DATAO Figures 3 5 and 3 6 shows the outlines of update timing Sinto scen sclk IU UU ULL FU UU UU UUUUUUL TUUHUUUU sdin NN MM M e sdo Wii AN E Request Status Command Data0 A Data1 i DATAO update DATA1 update timing timing Figure 3 5 Data Write Timing Setting Data 2 Bytes Sint see scen sik
44. e ese ee ee ee ee RA Ge AA Ge ER rr rare 59 C RF Burst Receive Timing Reference Values ee ee ee Re ER Re ER AA Ge ee rr 61 E Exampleof Extermal Circuit Ee ee EE dde 62 F Example of Improving the demodulation tracking characteristics with respect to a sudden change in the bottom level of a input modulation signal esse ese ee ee AA Ee AR ee ER Re nr narran nr nr 63 G Notes on Hardware Design esse ee ese ee ee ee Ge ee ee ee ee Ge ee ee ee ee ee AR Ge ee AR Re ee ee ee Re ee ee AR ee 64 G 1 When Designing Power Supplies esse ee ee ER RA ee cn AR Re nr ER Re ee ee ee ER Re ee ER rr ee ee ee ER Re ee 64 en ee Mee ui is 64 G 1 2 Bypass Capacitor nsertiON is se ee ee RA Ee AA Re AR rr 64 G 1 2 1 Example of Bypass Capacitor Insertion iese ee ee ee ee Ge AR ee ER Re ee ee ee Re ee ee 64 G 1 2 2 Notes on Inserting Bypass Capacitors iss ee ee ee ee RA Ge AR ee ER Re ee ee Ee nc Re ee ee 65 G 1 2 3 Notes on Power Supply VoltageS ese ee ee ER Re ee RA Ke Ge AR ee ER Re AA ee ee ee AR Re ee ee 65 G 2 When Configuring Oscillation Circuits iese ee ee ee ee AR ee ER Re RA ee ee ER Re ee ee ee ee ee ee Re ee 65 G 2 1 When Using a Crystal Oscillation Circuit iese ese ee ee RA Ee AA Ee Re ee RR ee ee Re Re ee 65 G 2 1 1 Example of Crystal Oscillation Circuit Configuration esse esse ee ee ee ee ee ER Re ee ee 65 G 2 1 2 Notes on Configuring a Crystal Oscillation Circuit sesse ee ee ee RR ee ee ee Re ee 66
45. ee ee ee ee ee ER RA nn ee ee ER Re ee 50 7 1 4 Creating a Temperature Correction Curve for Each Individual Se esse ee ee ee ee ee 50 7 1 5 Correcting Temperatures during the Operation Of a SeF see ee ER RA ee ee ee ER Re ee 51 4 2 Reception Character St su EES EES EER BEEK SEER ee da de GEE Paas 52 7 2 1 Reception Blocks and Reception Characteristics Adjustment Registers sesse ee ee 52 7 2 2 Method of Setting the Reception Characteristics Adjustment Registers sees ee 52 7 2 3 Creating a Standard Temperature Correction CUFVE ese ese ee ee ee ee ee ER RA ee ee ee ER Re ee 53 7 2 4 Creating a Temperature Correction Curve for Each Individual Se esse ee ee ee ee ee 54 7 2 5 Correcting Temperatures during the Operation Of a SeF iese ee ee ee ER RA ee AR ee ER Re ee 55 E A GE EE ED ee 56 A SCI Timing Specifications Reference Values ee ee ee ER Re RA AG AR ee ER Re ee ee ee AR Re ee 56 A 1 Internal Register Update Timing at Write Reference Values see ee ee ee Re ee AR Re ee 56 A 2 SINT Assert Timing at Read Reference Values ee Re Re AR ee AR Re AA GR ee Re 57 B Example of Setting Transmit TIMING ese esse ee ese ee ee RA ee Ee AR ee ER RA ee AA ee Re ee RA ee ee ee ee ee ee Re 58 B 1 Example of Setting QPSK Transmit TIMING sesse see ee ee ee RR ee ee ee ee ER Re ee ee ee ee Re ee 58 Contents 1 ML9636GDZ45A User s Manual Table of Contents B 2 Example of Setting ASK Transmit TIMING esse e
46. ees as to the operation of them So be sure to check the operation on the customer s board before use Table G 1 Examples of Crystal Resonators Representative Equivalent Load Excitation Overtone Frequency Manufacturer Type name frequency resistance capacitance level order deviation Application Package Frequency range MHz Q Max pF Min W Max ppm Min Daishinku psx8218 30 100 8 300 fremna 10 Automotive SMD 28 50MHz Daishinku DSX32iGA 30 100 8 300 _ runamentall 30 Automotive smD _12 40MHz Kyocera KinseK CX5032GA 25 40MHz G 2 2 When Configuring an External Clock as the Input to an Oscillation Circuit G 2 2 1 Example of Configuring an External Oscillation Circuit The figure below shows an example of configuration where an external clock is intput to the oscillation circuit of this IC Determine the definitive constants after evaluation including the floating capacitance of the custormer s board VOD CORE ML9636 Oscillator TCXO OSCOUT Figure G 3 Example Configuration of ML9636 External Oscillation Circuit 66 ML9636GDZ45A User s Manual Appendixes G 2 2 2 Notes on Configuring an External Crystal Oscillation Circuit Note the following when configuring an external clock as the input to an oscillation circuit e The input level at OSCIN is a 1 5 V CMOS input If the output level of the oscillator used does not satisfy the CMOS input specifications or exceeds a max
47. erature correction p Carry out the process periodically during registers _J operation of the Set Figure 7 2 Procedure for Calculating the Setting Values for the Transmission Power Adjustment Registers TPC Register AMPL_ADJ Register Table 7 2 Standard Table for Transmission Registers Setting No TPC DEC AMPL_ADJ DEC 0 0 22 1 0 21 2 0 20 3 0 19 4 0 18 5 0 17 6 0 16 7 0 15 8 0 14 9 0 13 10 0 12 11 0 11 12 0 10 13 0 9 14 0 8 15 0 7 44 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics TPC DEC AMPL_ADJ DEC 16 0 6 17 0 5 18 0 4 19 0 3 20 0 2 21 0 1 22 0 0 23 0 1 24 0 2 25 0 3 26 0 4 27 0 5 28 0 6 29 1 6 30 1 5 31 1 4 32 1 3 33 1 sg 34 1 35 1 0 36 1 1 a7 1 2 38 1 3 39 1 4 40 1 5 41 1 6 42 2 6 43 2 5 44 2 4 45 2 3 46 2 2 47 2 1 48 2 0 49 2 1 50 2 2 51 2 3 52 2 4 53 2 5 54 2 6 55 3 6 56 3 5 57 3 4 58 3 3 59 3 2 60 3 1 61 3 0 62 3 1 63 3 2 64 3 3 65 3 4 66 3 5 45 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics
48. erature zone to the SET_RFO command LNA_GAIN_ADJ 3 0 bits Since the ML9636 has been trimmed during the production process at OKI use this trimming value to calculate the value appropriate for the temperature zone Use this trimming value to calculate the value appropriate for the corresponding temperature zone and set it ot the register The following figure shows an example flow of setting the LNA GAIN ADJ register Write the values which will be presented from OKI separately to LNA_GAIN_ADJ 3 0 RFO 3 0 register Carry out the process once The value will be retained as the initial value of LNA_GAIN at power on of each Set Write the value obtained through the operation for the appropriate temperature zone below to LNA_GAIN_ADJ 3 0 15 C or lower Initial value of LNA_GAIN 15 C to 15 C Initial value of LNA_GAIN Carry out the process 15 C to 45 C Initial value of LNA_GAIN periodically during operation 45 C to 75 C Initial value of LNA_GAIN of the Set 75 C or higher Initial value of LNA_GAIN OKI s recommended values Figure 7 6 Method of Setting Reception Characteristics Adjustment Registers 1 52 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics 2 Setting the CAR_DET_LVL register Following shows how to calculate the CAR_DET_LVL register setting values correspond to SET_CAR_DET_LVL command CAR DET LVLI8 0 bits 15 7 Based on the standa
49. ernal power amplifier and then determine the standard setting value at each dispersion temperature For example when the dispersion temperature points are set to 30 C 15 C 15 C 27 5 C room temperature 45 C 75 C and 85 C determine the setting No Standard value in Table 2 that produces the required transmission power as a Set at the Set evaluation stage xx1 to xx7 in Figure 7 3 Setting number Xx7 xx1 30 C 15 C 27 5 C 45 C 75 C 85 C Normal na Temperature Figure 7 3 Standard Temperature Correction Curve 7 1 4 Creating a Temperature Correction Curve for Each Individual Set As one of the adjustment items create temperature correction curve data for each individual Set user applied board in the Set production process and store it into the nonvolatile memory in the Set Temperature correction curve data for each Set can be created in the following way using the standard temperature correction curve created in Section 7 1 3 Determine the register values from the value measured at room temperature that produces the transmission output power predetermined for the Set when in a transmitting state Then create a temperature correction curve for the Set by translating that standard temperature correction curve so that the curve passes over this measurement point measured register values at room temperature Store the values at both end of each of the temperature zone for the created temperature correction
50. for reading from the host If a SET command error is detected the ML9636 asserts SINT and if set to output enable for reading from the host returns the SET_confirm command 1st byte 2nd byte 3rd byte 4th byte e Host gt ML9636 sdin Request Command Data0 Data1 SAO Figure 3 2 Transfer Data Format ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 3 2 1 Transaction The request is exchanged with the status between the host and the ML9636 at the first trasnfer byte If host ML9636 or ML9636 gt host or both are feasible data transfer for the second byte onwards is carrired out Use the SET command to write a setting value to the ML9636 and the GET command to read the set value from it 3 2 2 Request Status Byte The host sends a request to the ML9636 and at the same time the ML9636 sends the status to the host For the request and status only bits 3 and 2 out of the eight bits bits 7 0 are used positive logic and the other bits are Don t Care as shown below When the bits at the same bit position in the request and status transmitted from the host and the ML9636 are both in the 1 state a handshaking between the host and the ML9636 is established and data transmission reception for the second bytes onwards starts In the actual ML9636 status output OXOC both bits 3 and 2 are 1 is always returned to the host in order to support read and write to the host at the same
51. ground connection for the chip Figure 6 1 Package Dimensions Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage Therefore before you perform reflow mounting contact Oki s responsible sales person on the product name package name pin number package code and desired mounting conditions reflow method temperature and times 41 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics 7 Temperature Correction for RF Characteristics This capter describes how to adjust RF characteristics transmission and reception and make temperature correction A correction operation is performed by measuring an ambient temperature using an external circuti such as a thermistor and then writing a correction value appropriate for the temperature into a predetermined register from the serial interface of the ML9636 7 1 Transmission Characteristics 7 1 1 Transmission Blocks and Transmission Power Adjustment Registers Figure 7 1 shows the relationship between ML9636 s transmission blocks and the setting registers Transmission i output amplifier 1 PA driver External ANT filter ES OE ye Variable gain Modulation Antenna pin amplifier circuit PADRV_I_ADJ TPC_ASK AMPL_ADJ TPC_QPSK _AMPL_ADJ Q_AMPL_ADJ Figure 7 1 Relationship between ML9636 Transmission Blocks and Setting Registe
52. han other signal lines e Make the wire length between a bypass capacitor and VDD and that between a bypass capacitor and GND as short as possible e Make the wire length between a bypass capacitor and VDD and that between a bypass capacitor and GND as equal as possible G 1 2 3 Notes on Power Supply Voltages The power supply voltage conditions are as follows The recommended operating conditions and all electrical characteristics are specified in this range If any voltage being outside the range is used the electrical characteristics may no longer be satisfied or the device may malfuction VDD_IO VDD_IF VDD PADRV 3 15 to 3 45 V VDD_RF VDD_VCO VDD_CP VDD_RFPLL VDD_DPLL VDD_CORE 1 5 to 1 65 V When adjusting the transmission power or carrier detection level CAR_DET_LVL use a regulator for each power supply because a change in a power supply voltage after correction will accompany a change in the characteristics G 2 When Configuring Oscillation Circuits G 2 1 When Using a Crystal Oscillation Circuit G 2 1 1 Example of Crystal Oscillation Circuit Configuration The following figure shows an example of typical configuration of a crystal oscillation circuit Determine the definitive constants after evaluation including the floating capacitance of the custormer s board ML9636 L Crystal1 AT Ar Figure G 2 Example of ML9636 Crystal Oscillation Circuit Configuration C1 C2 65 ML9636GDZ45A User s Manu
53. hen a SET command is executed without performing a read SINT is once negated and the SET command is executed normally When SCEN is negated after the SET command is executed SINT is asserted again thereby enabling a read When SCEN is negated before all the GET_confirm command data is transmitted SINT will be left asserted If a read is performed again the GET_confirm command is transmitted however the read data at that time is not guaranteed Transmit the GET_request command again 26 ML9636GDZ45A User s Manual Chapter 4 List of Commands 4 List of Commands The following table lists the commands required for normal data transmission reception input from the SCI interface These commands can be ommend Name Description Direction code 0x02 SET_VCV_RAW VCO calibration control setting Host gt ML9636 0x04 SET_FMAP PLL counter setting Host gt ML9636 0x06 SET HDAC OPSK1 OPSK HDAC adjustment 1 Host ML9636 0x08 SET_HDAC_QPSK2 QPSK HDAC adjustment 2 Host gt ML9636 OXOA SET HDAC ASK ASK HDAC adjustment Host gt ML9636 0x0C SET_TPC Gain control for OPSK ASK Host gt ML9636 Ox0E SET_RF_TMP RF section adjustment RF_TEMP Host gt ML9636 0x10 SET_CAR_DET_LVL Carrier detection level setting Host gt ML9636 0x12 SET_CAR_DET_CTL Carrier detection hyste
54. ics Vpp3 3 15 V to 3 45 V VpDi6 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit FOUA Vobio 2 Es High level input Va 6263 20 0 3 y voltage 9 Vin2 4 When inputting signals externally 1 2 a V Low level input Vi 23 0 3 0 8 V voltage Vite 4 When inputting signals externally 0 3 0 4 V liH1 VIH Vppio 2 10 HA Input leakage ln ue 3 w 200 Be current lins VIH 1 65 V 4 1 0 uA hoi VIL 0V 2 3 10 HA li VIL 0V 4 1 0 HA V High level output Vou IOH 100 pA 5 me v voltage IOH 4 mA 5 2 4 V Low level output VoL IOL 100 pA 5 0 2 V voltage IOL 4 mA 5 0 4 V lbo1 When receiving signals 3 3 V supply 50 pF loaded 37 mA Supply current 1 6 V supply Ed 78 mA 1 lbo When transmitting signals 6 3 3 V supply 50 pF loaded 37 mA 1 6 V supply 58 mA 1 The total current supplied to the 3 3 V supply pins Vpp3 VDD_IO VDD IF VDD_PADRV and the 1 6 V supply pins Vppis VDD RF VDD_VCO VDD_CP VDD_RFPLL VDD_DPLL VDD CORE The pin shown as I in the I O column in the table in Section 1 3 2 Pin Descriptions The pin shown as Ip in the I O column in the table in Section 1 3 2 Pin Descriptions The pin shown as Ios in the I O column in the table in Section 1 3 2
55. imum voltage of 1 65 V insert a buffer for level conversion e Leave OSCOUT open e Adjust the values of the resistors R1 and R2 so that the amplitude of the output clock of the oscillator TCXO satisfies the input threshold level of the buffer e The oscillation circuit of this IC has an internal feedback resistor When inputting an external clock turn off the feedback resistor by setting bit 4 of the SET EXT VCO command to 1 from the serial interface SCD If the ML9636 is used without turning off the feedback resistor no normal reception of an external clock may be available 67 ML9636GDZ45A User s Manual Appendixes G 3 On Designing a High Frequency Circuit G 3 1 General Notes 1 Power supplies Use stable ripple free power supplies 2 Patterning Avoid parallel or cross wiring among signal lines as much as possible and guard clock signal lines and other signal lines with GND patterns in order not to interfere with other signal lines 3 Parts layout Keep any parts that emit strong signals such as a clock from the periphery of an antenna having a high sensistivity or the input section of an amplifier G 3 2 High Frequency Circuit Design 1 Loop filter and crystal oscillation circuit section e Parts Select parts whose temperature characteristics are flat and temperature coefficients have been standardized Some parts of high permittivity type or of semiconductor type may have a large margin of error or have
56. ircuits and setting registers are initialized therefore no normal data transmission reception is available In this case all the RF control signals and MODEM control signals for transmission are disabled to prevent erroneous transmission Stable Wait Time after Cancelling RESET_N After RESET_N is released a stabilization wait time of 1 us is required for releasing of the internal reset signal to stabilize When executing an SCI command take care to take an interval of 1 us after RESET_N is released 38 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 7 Oscillation Circuit Characteristics 31 808 MHz OSC Vpp3 3 15 V to 3 45 V VppDi6 s 1 5 V to 1 65 V Ta 30 to 85 C Symbol Oscillation stabilization time tos Note After power is turned on no normal RF reception is available until the oscillation circuit is stabilized after the power supply voltage is stabilized For this reason to start reception processing at the system be sure to do so after the oscillation stabilization time elapses Figure 5 9 Example of Oscillation Circuit 8 Input Section LO Clock 16 MHz Characteristics Vpp3 3 15 V to 3 45 V VppDi6 s 1 5 V to 1 65 V Ta 30 to 85 C Symbol Unit Input amplitude level Visse e A Mo ET Vose Mes Figure 5 10 shows an LO CLK pin connection example For connection to the LO CLK pin insert a coupling capacitor because a DC component is to be cut off As an inpu
57. mmand first there are no restrictions on the setting order as to the other commands However take care not to carry out transmission even if this initialization has been completed until temperature correction described in Section H 4 is made Apply 1 6 V and 3 3 V in this order Apply 1 6 V and 3 3 V to all the corresponding power supply pins TX_Cl Input DPLL operation starts DPLL is locked 31 808 MHz OSC operation starts Oscillation stabilized Figure H 1 Example of Activation Procedure at ML9636 Power On 69 ML9636GDZ45A User s Manual Appendixes H 2 Example of Procedure at Power Shutdown The figure below shows an example of procedure at power shutdown When shutting the power down be sure to make sure that no data is being transmitted then shut the power down Figure H 2 Example of Procedure at ML9636 Power Shutdown H 3 Example of Procedure for Frequency Selection during Operation Figure below shows an example of a procedure for selecting a frequency SET_FMAP command To reception control Yes Time out Figure H 3 Example of Procedure for Frequency Selection during Operation of ML9636 70 ML9636GDZ45A User s Manual Appendixes H4 Example of Procedure for Temperature Correction during Operation Figure below shows an example of a procedure for correcting a temperature For how to calculate the value in accordance with the temparature zone to be written to each registers see
58. mp_Mod signal in the respective cases of ASK mode and QPSK mode As the clock to be input a 4 096 MHz clock is used both in QPSK mode and in ASK mode When in QPSK mode the data to be input is the QPSK mode data at 4 096 Mbps when in ASK mode the data to be input is the data at 1 024 Mbps before split phase coding In ASK mode the boundary of ASK data at 1 024 Mbps is identified by the TXW_N signal falling edge timing Then the Mod circuit performs the split phase coding of 1 024Mbps It is necessary for the BB LSI to enable the TXW_N signal prior to the transmit channel data Itis also necessary for the BB LSI to be provided with a setting function that can change the TXW_N enable timing with respect to transmit channel data It is recommended that the variable values TO_QPSK TO ASK for antecedent output be set to 0 to 255 cycles approx 0 to 62 us at an equivalent clock frequency of 4 096 MHz The TXW_N signal disabling timing is the end of the CRC bit of the TX_DI transmit channel data 14 ML9636GDZ43A User s Manual Chapter 2 MODEM Function This IC generates timing for internal control signals transmit receive enable Ramp_RF and Ramp_Mod based on the TXW_N signal So the user needs to configure the settings for appropriate internal registers Fix the MOD_AQ signal at the same time as or before the assertion of the TXW_N signal The MOD_AQ signal is only fetched at the first cycle during which the TXW_N signal is a
59. non linear temperature characteristics e Parts layout For layout keep parts away from power supply lines as much as possible in order to avoid interference with the power supply circuit and being interfered with high frequency noise from the power supply circuit Also note that an oscillation frequency may drift depending on the floating capacitance of the pattern 2 GND Lower the GND impedance by such means as wiring all around with one GND line and through hole in order to avoid deterioration of characteristics due to a GND impedance 3 Power supply isolation For voltage supply it is recommended to isolate the power supply pins between one pin and the next using a filter circuit that uses a coil and bypass capacitors 4 Capacitors For a power supply bypassing capacitor select one with a value that allows low to high frequency components to be bypassed sufficiently enough Some capacitors with poor temperature characteristics may spoil high frequency characteristics or stability due to capacitor dried up at a low or high temperature 68 ML9636GDZ45A User s Manual Appendixes H Register Setting Procedure H 1 Example of Activation Procedure at Power On The figure below shows the commands that need setting at power on Write the values which will be presented from OKI separately to each command registers except the commands that the adjustment is necessary individually For the order of setting commands set the SET_INITIAL co
60. o 5 to 5 mA Power dissipation Pg 900 mW Storage temperature Tstg 55 to 150 C 3 3 3 V analog pins 4 1 5 V analog pins 5 RF pins 6 Analog output pin RSSI_A 1 3 3 V power supply pins Vdp VDD_IO VDD_IF VDD_PADRV 2 1 6 V power supply pins Vppie VDD_RF VDD_VCO VDD_CP VDD_RFPLL VDD_DPLL VDD CORE LNA_P LNA_N TX_P IF_FIL1 IF_FIL2 IF_FIL3 DET RSSI_C TX_P RSSI_A VREF_DAC RFRX_C LNA_P LNA_N LO1 LO2 LO_CLK OSCIN OSCOUT ATEST1 ATEST3 ATEST4 VREF_RF 5 2 Recommended Operating Conditions Parameter Symbol Condition Min Typ Max Unit Supply voltage 1 0 Vopio VDD_IO pin 3 15 3 3 3 45 V Supply voltage CORE Vppcone VDD CORE pin 1 5 1 6 1 65 V VDD_RF VDD_VCO Supply voltage RF VDDRF VDD CP VDD_RFPLL 1 5 1 6 1 65 V VDD_DPLL VREF RF Supply voltage analog Voorr3 VDD IF VDD_PADRV 3 15 3 3 3 45 V Operating temperature Ta 30 25 85 C RF synthesizer reference frequency Fucka EE ot id MEZ 20 20 ppm deviation E pin RF 2nd LO Input frequency 31 808 MHz crystal oscillator Fuck t 100 100 ppm frequency deviation OSCIN and OSCOUT pins Digital clock frequency Input frequency 4 096 MHz deviation FDCLK TX cl pin 100 100 ppm Digital clock duty ratio Drx ci TX_CI pin 45 50 55 29 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 5 3 DC Characterist
61. ommunication Interface SCI FunNCION ee ee ee ee Ee AR ee RR ee AA ee Re ee 18 BL eo ee oi ME ER EE EE EE EE N 18 3 2 Data oe sa IE RE KA ER EE ete Mend OE 19 321 EG ese N EE N OE RE OR EE N EE N Ea n 20 3 2 2 RBeauest status BYLO ii LE ESE ESE ER as 20 3 2 3 Command Byte and Data ByteS ii iss ei se ee ee ee AE Ee ee ee ee Ee Ee ee EE Ee ee AR Re ee Re ee Ee ee ee ee ee ee 20 EP rooie ele de RR OE EO ME IE ER NE RO ER 21 3 3 Seting dIE IE EE EE OE N N EE EE ER N 22 3 4 Reading Set Data EER EE De SEA ase RE A a 25 4 LICONSA o RA 27 5 Electrical CharacterlSEIES ui 29 5 1 Absolute Maximum RattiindS i e ee ee ee ee ER ee rn 29 5 2 Recommended Operating ConditiONnS i ese ee ee ER Re RA AE rene 29 5 3 DE EharacteristiEs EE d 30 54A el ed de EE OE IE EE EE EE Uie 31 Sal RFE Character STOS to See ead Aneesh 31 5 4 2 Digital Characteristics ites ited eee eee ole ee ee a 33 6 Package DIMENSIONS ic OE RE EE OE OE EE GR EE OE N EK 41 de Temperature Correction for RF Characteristics ie iese se se ee ee ee ER RA nr ee ee ER Re ee GRA ee ee ee ee Re 42 7 1 Transmission Characteristics issie ese ee ee ee AR ee RR AA rr 42 7 1 1 Transmission Blocks and Transmission Power Adjustment RegisterS iss sesse ee ee ee 42 7 1 2 Outline of the Method of Setting Transmission Power Adjustment Registers TPC Register AMPL AD EO IE NE N MEN ER ME NE ON 43 7 1 3 Creating a Standard Temperature Correction CUFVE ees esse
62. or the measured value with reference to the temperature correction curve data then write it to the temperature correction registers For each of the measurement temperatures the setting number can be calculated by linear interpolation by using the setting numbers of both ends of the temperature zone including the temperature Determine the TPC and AMPL_ADJ settings that correspond to the obtained setting numbers from Table 7 2 For example the method of determing the register setting values when the measured temperature is 60 C is as follows Assume that the setting number for 45 C and that for 75 C obtained in Section 7 1 4 are 132 corresponds to TPC_ASK 9 AMPL_ADJ 2 and 172 corresponds to TPC_ASK 13 AMPL_ADJ 3 respectively Here since calculating the setting number for 60 C by linear interpolation procduces 152 the register setting values will be TPC_ASK 11 and AMPL_ADJ 4 How often the temperature correction registers are to be set depends on the temperature distribution inside the Set or the rate of temporal temperature change In the ML9636 frequency at about tens of seconds is assumed In addition it is assumed that the correction data for transmission characteristics will be written at the same frequency as the correction data for reception characteristics Do not write to the temperature correction registers during transmission 51 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteri
63. p3 3 15 V to 3 45 V VppDi6 1 5 V to 1 65 V Ta 30 to 85 C Symbol RESET_N pulse width 1 Atpower on 1 1 ms RESET_N pulse width 2 Other than above 2 1 us 1 At power on reset the IC for 1 ms or more until the logic section PLL is locked with stable TX_CI clock 4 096 MHz clock being input after the power supply voltage is stabilized 2 Resetting during operation will reset the internal circuts even if the reset period is less than 1 us The regulation in the table is to ensure that all the internal circuits and internal registers are reset in which case a reset period of 1 us or more is required RESET_N input timing Sass VDD VDD CF ee GND RESET_N trstw1 oe 7 ya On Figure 5 8 Timing Diagram of RESET_N RESET_N Input Procedure At power on reset the IC for 1 ms or more until the logic section PLL is locked with stable TX_CI clock 4 096 MHz clock being input after the power supply voltage is stabilized A reset is made asynchronously with the internal registers and a reset is not released unless TX_CT is input at the time of reset release When making a reset during operation do so for 1 us or more to ensure that the internal circuits and the internal registers are initialized In this case also the reset is not released unless the TX_CI clock is input at the time of reset release When a reset is made during operation all the internal digital c
64. plies first e If power is turned on or shut down without following the above sequences it is possible that pins that are originally for input will be configured as output because every digital IO circuit of this IC uses bi directional buffer and as a result a signal conflict may be caused with output pins of the opposing BB LSI At Power On At Power Shutdown EE 1 6 V 1 6 V power supply 1 4V 14V RT Vpp16 OV BE 3 3 V 3 15 V A 3 3 V power supply Voos I 0 1V 2 ov LO J e tvccs 0 ms min tvccH 0 ms min Recommended power on shutdown sequences When turning power on apply power to the 1 6 V for RF and Logic core power supplies and 3 3 V for IO and DAC power supplies at the same time tvccs 0 ms or the 1 6 V power supplies first When shutting power down shut down the 1 6 V for RF and Logic core power supplies and 3 3 V for IO and DAC power supplies at the same time tvcch 0 ms or the 3 3 V power supplies first Figure 5 11 Power On Shutdown Sequences 40 ML9636GDZ45A User s Manual Chapter 6 Package Dimensions 6 Package Dimensions Unit mm P WQFN48 0707 0 50 63 Package material Lead frame material Lead finish Oki Electric Industry Co Ltd Pin treatment um Au 0 01 max Pd 0 15 max Package weight q 0 120 TYP Rev No Last Revised 2 Apr 16 2007 Note The exposed die attach pad must be connected to a solid ground plane as this is the
65. ransmitter circuits including the external AP circuit The preheating time is affected by external components and board patterns If there are no power supply voltage fluctuations associated with activation of transmitter circuits including the external PA circuit the ML9636 s transmitter circuits are activated within 5 us worst value 58 ML9636GDZ45A User s Manual Appendixes When in QPSK mode be careful of the handling of the Ramp In the figure above the timing of outputting the TXW signal from the BB LSI is indicated by reference to the head of the Ramp The register settings shown in the figure above are those which were considered as optimized values at the design stage of the ML9636 and are not guaranteed values Determine the definitive settings after verification after system evaluation on the customer side B 2 Example of Setting ASK Transmit Timing Shows air timing Shows MDC boundary BB LSI Delay in ML9636 SLOT boundary of air timing 3 2 us gt Po BB LSI transmit data Em ii I PA BB LSIMOD_AQ A TE E signal Switching by the MOD_AQ signal must be done either atthe same time as or before the TXW enable timing h 3 us I ee a Transmitted when L ANT_SW control signal T HS 3 TXW IDLY 0 ps t 1 The setting values for the ANT SW and PA Control signals are for reference only ML9636 Adjust those values in accordance with the TX DI AAA AA o MOD_A
66. rd temperature correction curve for the ML9636 and with reference to the temperature characteristics of the external circuit of the Set system and the carrier detect level specifications of the Set Carry out the process once create a standard temperature correction curve exclusive to the Set upon design of each Set Measure the CAR_DET_LVL value at room temperature that produces the carrier detection level predetermined for the Set when in a receiving state of the Set C arry out the process once upon Create temperature correction curve data for the Set and store it production of each Set into the nonvolatile memory in the Set eks the variation of parts from Set to Set Measure the temperature calculate the register setting values appropriate for the measured value with reference to the temperature correction curve data then write it to the temperature correction registers Carry out the process periodically during operation of the Set Figure 7 7 Method of Setting Reception Characteristics Adjustment Registers 2 7 2 3 Creating a Standard Temperature Correction Curve Create a standard temperature correction curve as a Set based on the ML9636 satandard temperature correction curve provided by OKI with reference to the temperature characteristics of external components ANT filter ANT SW and SAW filter that are used in the actual Set and according to the carrier detection level specifications as a Set The fig
67. re the SCLK rising edge in the number of second byte data bytes to When SCEN is negated If the data write fails the ML9636 asserts SINT and notifies the host of be set is 2 immediately after the SCLK the write error In this case the data DATAO at the first byte is rising edge at the eighth bit 8 updated but the data DATA1 at the second byte is not When a read when SCEN is negated request is received the ML9636 sends the command at the error without observing the interface occurrence and the error contents and negates SINT regulations If SINT is not asserted it indicates that the data write has succeeded However whether the DATA1 set value is correct is not guaranteed When the number of SCLK The data write succeeds and the register is set normally clocks is larger than the The excessive clocks and data are ignored number prescribed for the command The command at an error occurrence is output as a value command of the target SET command incremented by 1 24 ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 34 Reading Set Data For the host to read set values in the ML9636 use a GET command By setting bit 3 of the first byte to 1 and transmitting a GET_request command at the second byte the ML9636 prepares for a read When the ML9636 completes the preparation it asserts the SINT signal It takes several microseconds after the negation of SCEN to assert S
68. resis width adjustment Host gt ML9636 0x16 SET_RFO RF section adjustment O Host gt ML9636 0x18 SET_RF1 RF section adjustment 1 Host gt ML9636 Ox1A SET_RF2 RF section adjustment 2 Host gt ML9636 0x1C SET_RF3 RF section adjustment 3 Host gt ML9636 0x20 SET_DEMOD_SET DEMOD section configuration Host gt ML9636 0x22 SET_TEST_SEND Generation of test patterns for transmission Host gt ML9636 0x24 SET_TX_ON_ASK TX ON RX OFF timing adjustment T1 ASK Host gt ML9636 0x26 SET_TX_OFF_ASK TX OFF RX ON timing adjustment T2_ASK Host gt ML9636 0x28 SET_RAMP_RF_ON_ASK RAMP RF ON timing adjustment T3_ASK Host gt ML9636 0x2A SET_RAMP_RF_OFF_ASK RAMP RF OFF timing adjustment T4 ASK Host ML9636 0x2C SET_RAMP_MOD_ON_ASK RAMP MOD ON timing adjustment T5_ASK Host gt ML9636 0x2E SET_RAMP_MOD_OFF_ASK RAMP MOD OFF timing adjustment T6_ASK Host gt ML9636 0x30 SET_TX_ON_QPSK TX ON RX OFF timing adjustment T1 OPSK Host ML9636 0x32 SET_TX_OFF_QPSK TX OFF RX ON timing adjustment T2 OPSK Host ML9636 0x34 SET_RAMP_RF_ON_QPSK RAMP RF ON timing adjustment T3_QPSK Host gt ML9636 0x36 SET_RAMP_RF_OFF_QPSK RAMP RF OFF timing adjustment T4 OPSK Host gt ML9636 0x38 SET_RAMP_MOD_ON_QPSK RAMP MOD ON timing adjustment T5_QPSK Host gt ML9636 0x3A SET_RAMP_MOD_OFF_QPSK RAMP MOD OFF timing adjustment T6_QPSK Host gt ML9636 0x3C SET_TEST_MODE Test monitor mode setting Host gt ML9636 Ox3E SET_INITIAL Initial setting Host gt ML9636 0x82 GET_VCV_RAW_ request VCO calibra
69. rs In the explanations below it is assumed that the transmission power of the entire system including the external components such as the power amplifier will be adjusted using the functions of the ML9636 Transmission power is adjusted by configuring the following three types of registers e PADRV_I_ADJ register This register sets the transmission output amplifier PA driver block gain adjustment value e TPC_ASK and TPC_QPSK registers These registers correct the gain fluctuation by adjusting the variable gain amplifier to make the transmission output power from the antenna pin constant Gain fluctuation elements include interdevice variation in ML9636 temperature fluctuation in ML9636 interdevice variation in external components ANT filter ANT SW and SAW filter from device to device and temperature fluctuation in external components Adjustments are necessary for ASK mode and QPSK mode separately e AMPL_ADJ IAMPL_ADJ and Q_AMPL_ADJ registers Gain fluctuation is corrected in combination with the TPC_ASK and TPC_QPSK registers above Adjustments are necessary for ASK mode and QPSK mode separately The TPC_ASK and TPC_QPSK registers have an adjustment resolution of about 1 dB and the AMPL_ADJ I_AMPL_ADJ and O AMPL ADJ registers about 0 1 dB For the PADRV_I_ADJ register write the values RF1 15 12 which is presented by OKI separately This is the fixed values regardless of the ambient temperature For the TPC_ASK TPC_QPSK AMPL
70. rted value is output ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 3 Synchronous Communication Interface SCI Function The ML9636 is equipped with a synchronous communication interface SCI as an interface with the host 3 1 Clock Timing The SCI that the ML9636 has is for slave use only and input clocks from the host are applied to rising edges only Only MSB first is supported for transmit receive data SCEN EE SCLK Positive clock o ir N ar EEN SCLK Negative clock ENT os LI USE frst a USB frst 7 Figure 3 1 SCI Clocks and Data Transmit Receive Waveforms ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 3 2 Data Format Figure 3 2 shows the transfer data format Transfer data consists of request or status byte command byte and data byte s The number of data bytes is either one or two depending on the command The types of commands are SET commands to set registers GET_request and GET_confirm commands to read registers and SET_confirm command that is returned from the ML9636 if a SET command error occurs To configure settings from the host to the ML9636 write setting values using the SET command To read from the host into the ML9636 send the GET_request command from the host and the ML9636 will assert SINT and returns the corresponding GET_confirm command and the read value if set to output enable
71. sserted and no decision between ASK and QPSK is made in any other timing Because the R bit in QPSK mode is added before the input data from TX_DI fix TX_DI to L during the R bit addition timing Hold the TX_DI input L also after CRC is finished At QPSK TX Cl 4 096 MHz Yy f PR preamble End of CRC TX_DI QPSK mode R bit I I I MOD AG TEW N TO OPSK T2 OPSK T4_QPSK_ T6_QPSK tT OPSK Reception circuit enable Transmission circuit enable pu T3 QPSK Ramp_RF Ramp_Mod External PA control signal External ANT SW control signal Delay in transmit section Delay in transmit section Delay in transmit section E 1 EP MEAR Status of Reception Preheat Ramp up 1st half Ramp up 2nd half R bit Transmitting preamble Ramp Ramp down Reception ML9636 I ist half 2nd half A value of 0 to 255 cycles approx 62 us at an equivalent clock frequency of 4 096 MHz can be set in each of T1_QPSK T3_QPSK and T5_QPSK A value of 0 to 63 cycles approx 16 us at an equivalent clock frequency of 4 096 MHz can be set in ea
72. stics 7 2 Reception Characteristics 7 2 1 Reception Blocks and Reception Characteristics Adjustment Registers Figure 7 5 shows the receive blocks of the ML9636 LNA_GAIN_ADJ CAR_DET_LVL ER EO MO Moe 1 1 External 1 External 1 1 Receive External Receive O A ANT filter EP an P RF section SAW filter IF section Antennapin re he Se a Ep ANS crs i CarrierDet circuit ls Figure 7 5 Relationship between Reception Blocks and Setting Registers The setting registers are the following two For the relevant commands and registers refer to Chapter 4 and the separate volume for this manual e LNA_GAIN_ADJ Corrects the temperature characteristics of the gains of the receive RF section amplifier circuit and keeps good receiver sensitivity characteristics maximum and minimum reception levels e CAR_DET_LVL Corrects the fluctuations in gain from the antenna pin to the carrier detect circuit The gain fluctuation factors include variations in ML9636 devices temperature fluctuation in an ML9636 device variations in external components ANT filter ANT SW and SAW filter and temperature fluctuation in external component 7 2 2 Method of Setting the Reception Characteristics Adjustment Registers 1 Setting the LNA_GAIN_ADJ register Divide the temperature range into five temperature zones and based on the measured temperature information write the value appropriate for the corresponding temp
73. t Trxack2 RX_QCO RX_QDO Figure 5 1 Timing Diagram of MODEM RX QPSK Interface Frxack RX_ASKCO ed TWACKL RX ASKDO Figure 5 2 Timing Diagram of MODEM RX ASK Interface 34 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics Frxck TX_Cl Trxps TTXDH A gt Trxps TXW_N Trxps TTXDH mM N Note Signals are fetched on the falling edge of the TX Cl signal at 4 096 MHz irrespective of QPSK or ASK mode The MOD AO signal is fetched only in the first cycle after the TXW_N signal goes L Therefore fix the MOD AO signal either at the same time as the fixation of the TXW_N signal or before that A change in the MOD_AQ signal level during transmission does not affect the transmission signal Figure 5 3 Timing Diagram of MODEM TX Interface 35 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 5 Synchronous Communication Interface SCI Characteristics Vpp3 3 15 V to 3 45 V VppDi6 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit Other than ina SCLK clock frequency Fscik suspended state 0 1 2 4 MHz SCEN input setup time TCESU 125 ns SCEN input hold time Teen 125 ns SCLK high pulse width TwckH 50 ns SCLK high pulse width TwckL 50 ns a Load SDIN input setup time TDISU 3 20 ns P F capacitance SDIN input hold time TDIH C
74. t waveform inputting a square wave whose amplitude level is Vppis Vp p is recommended from the viewpoint of the optimization of RF characteristics Do not stop the 16 MHz input while the ML9636 is operating ML9636 Figure 5 10 LO CLK Pin Connection Example 39 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 9 Logic Section PLL Characteristics Vpp3 3 15 V to El 45 V VbDpi6 L 5 V to 1 65 V Ta 30 to 8520 Symbol AAA The reference clock for the digital processing section receive section transmit section and SCI section is generated based on the 4 096 MHz input clock from the TX_CI pin Note that if the input clock from the TX_CI pin is stopped or the frequency is changed the digital processing section may lose normal functioning 10 Power On Shutdown Time Vpp3 3 15 V to 3 45 V Vppi6 r 5 V to 1 65 V Ta 30 to EE Condition min Typ max Unit Poweron me iferenos tes Arpoweron o 10 m Power shutdown time difference At power shutdown o 10 ms Note e When turning power on apply power to the 1 6 V for RF and Logic core power supplies and 3 3 V for IO and DAC power supplies at the same time tvccs 0 ms or the 1 6 V power supplies first e When shutting power down shut down the 1 6 V for RF and Logic core power supplies and 3 3 V for IO and DAC power supplies at the same time tvcch 0 ms or the 3 3 V power sup
75. time Bit Request Host gt ML9636 Status ML9636 Host 3 Setup data write request Setup data write enable Setup data read request Setup data read enable 2 Confirm enable Confirm request 3 2 3 Command Byte and Data Bytes There exist commands and data that accompanies them For the details of each command refer to A Separate Volume for the ML9636 User s Manual Command Details 20 ML9636GDZ45A User s Manual Chapter 3 Synchronous Communication Interface SCI Function 3 2 4 Timing Diagram sint scene sclk WU UU UU UL UU sdn ANN AMM E so ANNAN AQ Request Status Command Data0 Data1 MSB first 4 byte transfer Command 0x02 Data 0x0a 0x07 Figure 3 3 Host ML9636 Data Write SET command sint po scen sclk UUUUUUULUUUUUUULUUUUULNI IUU l sdin WAN AY A so ANN AT PS Request Status Command Data0 Data1 MSB first 4 byte transfer Command 0x02 Data Ox0a 0x07 Do not negate scen H scen during transfer If it is negated the transfer data is invalid The interrupt sint changes only when scen is H When only a write operation is performed after interrupt occurrence the ML9636 first negates sint and then asserts sint again Figur
76. tion results register read request Host gt ML9636 0x83 GET VCV RAW confirm VCO calibration results register read ML9636 gt HOST 0x84 GET FMAP _ request PLL counter settings read request Host gt ML9636 0x85 GET_FMAP_confirm PLL counter settings read ML9636 gt HOST 0x86 GET HDAC GPSK1 request ch DC offset and amplitude adjustment value Host gt ML9636 read request 0x87 GET_HDAC_QPSK1_confirm Hi Fi offset and amplitude adjustment value L9636 HOST 0x88 GET_HDAC_QPSK2_request QchDC offset amplitude and phase adjustment Host gt ML9636 value read request 0x89 GET _HDAC_QPSK2_ confirm QchDCoffset amplitude and phase adjustment ML9636 gt HOST value read Ox8A GET HDAC ASK request ASK DC offset and amplitude adjustment value Host gt ML9636 read request 0x8B GET HDAC_ASK confirm ae DC offset and amplitude adjustment value ML9636 gt HOST 0x8C GET TPC request OPSK ASK gain control value read reguest Host gt ML9636 0x8D GET_TPC_confirm QPSK ASK gain control value read ML9636 gt HOST OXBE GET RF TMP redguest RF section adjustment value read reguest Host gt ML9636 0x8F GET_RF_TMP_confirm RF section adjustment value read ML9636 gt HOST 27 ML9636GDZ45A User s Manual Chapter 4 List of Commands nee Name Description Direction
77. to 85 C Parameter Symbol Condition Min Typ Max Unit SINT assert time at read Tsiast Load capacitance 2 4 us SINT reassert time TSIREAST C 50pF 2 0 US SINT Tsiast SCEN Figure A 2 SINT Assert Timing at Read SINT EEN TSIREAST SCEN eee TEG Figure A 3 SINT Reassert Timing 57 ML9636GDZ45A User s Manual Appendixes B Example of Setting Transmit Timing B 1 Example of Setting QPSK Transmit Timing i Shows air timing Shows MDC boundary BB LSI a lg l I BB LSI transmit data E O E Switching by the y MOD_AQ signal must be done at the same time as or before the TXW enable timing f signal BB LSI TXW signal es P OED ANT_SW control signal l us I je us Transmitted when L lt gt gt t PA control signal l Fs us I je HS PRON wheats 4 x v M m N o E G gr d ma ME ee ey o E lt o D I I I The setting values for the ANT_SW and PA control signals are for reference only ML9636 Adjust those values in accordance with the characteristics of the SW and PA used TDI NW 2 2 ii l i 1 i MOD_AQ i I l H l i l eran The Transmission TXW_N I l enable and Ramp_RF l I l actually get delayed by L 0 ps l T2 8 us 0 5 us inside the IC re 1 l Transmission enable I pol 1 sa gt 474 5 us T3 23 Ramp_RF HS l l 1 l T6 048 pe The Ramp_Mod signal I be
78. tput switching H ASK L QPSK Synchronous communication interface SCI related pins 28 SDIN Synchronous communication interface E Data input pin 25 SDO o Synchronous communication interface L Kai Data output pin 27 SCLK Synchronous communication interface ME Clock input pin 26 SINT O Synchronous communication interface 4 L Interrupt output pin 29 SCEN Synchronous communication interface E L Chip enable pin System control pins 17 RESET_N I Hardware reset pin L 31 808 MHz crystal connection pin 1 eer los External clock input pin oe 31 808 MHz crystal connection pin 2 16 OSCOUT Oos Leave this pin open when OSCIN is used as an external clock input pin 12 LOCK_DET O PLL LOCK detecting output pin H Lock L Unlock H ML9636GDZ43A User s Manual Chapter 1 Overview F A TEP State Active Pin Symbol VO 1 Description arresanieval Control pins for testing 31 DTEST1 ID Test mode setting pin 1 Fix to L 30 DTEST2 ID Test mode setting pin 2 Fix to L 1 ATEST1 In F Orr RF circuit test pin Hi Z 33 ATEST IWOA IF and analog circuits test pin al 38 ATEST4 la Oa Hi Z Power supply pins 4 48 VDD_RF Power supply pin for LNA and DET 1 6 V typ 6 VDD_RFPLL Power supply pin for RF PLL 1 6 V typ 3 VDD_
79. uest Host gt ML9636 0xB7 GET RAMP RF OFF OPSK confrm RAMP RF OFF timing value read ML9636 HOST 0xB8 GET_RAMP_MOD_ON_QPSK_request RAMP MOD ON timing value read request Host gt ML9636 OxB9 GET_RAMP_MOD_ON_QPSK_confirm RAMP MOD ON timing value read ML9636 gt HOST OXBA GET RAMP MOD OFF OPSK reguest RAMP MOD OFF timing value read request Host gt ML9636 OxBB GET_RAMP_MOD_OFF_QPSK_confirm RAMP MOD OFF timing value read ML9636 gt HOST 0xBC GET_TEST_MODE_request Test monitor mode settings read request Host gt ML9636 OXBD GET TEST MODE confirm Test monitor mode settings read Host gt ML9636 OxBE GET INITIAL request Initial settings read reguest Host gt ML9636 OxBF GET_INITIAL_confirm Initial settings read Host gt ML9636 Do not access any unimplemented command command If any unimplemented command is issued the ML9636 neglects such a 28 ML9636GDZ45A User s Manual Chapter 5 Electrical Characteristics 5 Electrical Characteristics 5 1 Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Supply voltage 3 3 V 1 Vops 0 3 to 4 6 V Supply voltage 1 6 V 2 VpDi6 0 3 to 12 0 V Digital pin voltage Vo 0 3 to Vpp3 0 3 V 3 3 V analog pin voltage 43 Vas 0 3 to Vpp3 0 3 V 1 6 V analog pin voltage 4 Varo 0 3 to Vppie 0 3 V RF pin RF signal level 45 PrF Ta 25 C 7 dBm Digital output current Ibo 16 to 16 mA Analog output current 6 la
80. ure below shows the standard value carrier detect level 64 dBm For details see Figure 7 10 CAR_DET_LVL setting value 315 306 310 311 317 298 30 C 15 C 15 C 45 C 75 C 85 C gt Temperature Figure 7 8 Creation of a Receive Standard Temperature Correction Curve 53 ML9636GDZ45A User s Manual Chapter 7 Temperature Correction for RF Characteristics 7 2 4 Creating a Temperature Correction Curve for Each Individual Set As one of the adjustment items create temperature correction curve data for each individual Set in the Set production process and store it into the nonvolatile memory in the Set Measure the CAR_DET_LVL value at room temperature that produces the carrier detection level predetermined for the Set when in a receiving state Then create a temperature correction curve for the Set by translating that standard temperature correction curve so that the curve passes over this measurement point measured CAR_DET_LVL value at room temperature Store the values at both end of each of the temperature zone for the created temperature correction curve into the nonvolatile memory Input the RF signal at the arrier detect level r LNA_GAIN_ADJ setting value CAR_DET LVL higher e g 64 dBm at room temperature Measure the detection threshold level at room temperature E r Eternal 1 Exte 1 External l 1 rnal 1 1 gt ANT filter gt ANT gt l Antenna pin Extern
81. used for 5 8 GHz ASK QPSK DSRC communication The IC can be applied to DSRC systems in combination with a baseband LSI for DSRC 1 1 Features e Conforms to ARIB STD T75 dedicated short range communications DSRC system standard version 1 3 Includes receive and transmit circuits a synthesizer and a digital modulation and demodulation circuit The digital circuit also includes a split phase coding and decoding circuit in ASK mode However this is only for the split phase code of 1024kbps Manchester code The interface with a base band is for digital signals and low speed analog signals RSSI only Radio frequency range Downlink D7 5775 MHz D6 5780 MHz D5 5785 MHz D4 5790 MHz D1 5795 MHz D3 5800 MHz D2 5805 MHz Uplink U7 5815 MHz U6 5820 MHz US 5825 MHz U4 5830 MHz U1 5835 MHz U3 5840 MHz U2 5845 MHz Data transfer speed In ASK mode 1024 kbps In QPSK mode 4096 kbps Supply voltage T O section VDDIO 3 3 V Typ 3 15 V Min 3 45 V Max CORE and RF sections VDDCORE 1 6 V Typ 1 5 V Min 1 65 V Max Supply current During reception 115 mA Max During transmission 95 mA Max When 7 dBm is transmitted from the TX_P pin e Package 48 pin WQFN P WQFN48 0707 0 50 63 ML9636GD7Z45A User s Manual Chapter 1 Overview 1 2 Block Diagram Figure 1 1 shows a block diagram of this IC Table 1 1 shows a functional summary of each block 40 MHz 31 808 MHz A
82. ve refers to the time required to stabilize various fluctuations associated with a change in power supply voltage caused by activation of transmitter circuits including the external AP circuit The preheating time is affected by external components and board patterns If there are no power supply voltage fluctuations associated with activation of transmitter circuits including the external PA circuit the ML9636 s transmitter circuits are activated within 5 us worst value When in QPSK mode be careful of the handling of the Ramp In the figure above the timing of outputting the TXW signal from the BB LSI is indicated by reference to the head of the Ramp The register settings shown in the figure above are those which were considered as optimized values at the design stage of the ML9636 and are not guaranteed values Determine the definitive settings after verification after system evaluation on the customer side 60 ML9636GDZ45A User s Manual Appendixes C RF Burst Receive Timing Reference Values Shown below are the carrier detect signal rise time and the time for receive data to stabilize at RF signal input reference values Figure C 1 shows the timing Vpp3 3 15 V to 3 45 V Vopi6 s 1 5 V to 1 65 V Ta 30 to 85 C Parameter Symbol Condition Min Typ Max Unit Carrier detect signal rise time At no modulation wave T E 14 1 2 CDET input 3 3 US OPSK receive stabilization time TsTABLE_
83. z filter 40 IF_FIL2 la Input pin for the external 40 MHz filter 41 IF FIL3 la Connection pin for the external 40 MHz filter 45 RFRX_C Connection pin for the external capacitor for RF 37 DET Connection pin for the external capacitor for ASK demodulation 35 RSSI_C Connection pin for the external capacitor for RSSI integration 5 LOT Connection pin for the external capacitor and resistor for PLL 2 LO2 Connection pin for the external capacitor and resistor for PLL 7 LO_CLK la 16 MHz input pin for LO 2 Reference pin for DAC 2 VREF_DA 4 E Es 3 PAG connected to GND via a 0 01 uF capacitor 33 VREF_RF Reference pin for RF connected to the 1 6 V supply MODEM interface RX related pins 20 RX_ASKDO O RX ASK split phase demodulation data output pin L 21 RX_ASKCO O Clock output pin for RX ASK 1 024 MHz E 22 RX_QDO O RX QPSK data output pin L 23 RX_QCO O Clock output pin for RX QPSK equivalent to 4 096 MHz L 19 CAR_DET O Carrier detect output pin H Detect H 34 RSSI_A Oa RSSI analog output pin MODEM interface TX related pins 11 TX_DI I TX data input pin TX clock input pin 4 096 MHz 19 Xl Digital reference clock 3 9 TXW_N l Input pin for output timing control L Transmission H Reception 8 MOD_AQ I Input pin for ASK QPSK ou

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