the user manual for the OPTO16x16
Contents
1. Board Offset 0x04 16 bits Debounced Receive data bits 0 16 Read ONLY The Input Data Bits After they have been Debounced Table 3 7 Received Data Register Debounced Receive Data bits 0 16 Read ONLY The Debounced Input Data Bits 31 16 Reserved Undefined User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 20 3 2 4 Change of State Register Board Offset 0x08 16 bits Change of State Detected Polarity programmed thru COS Polarity register 0x014 If a COS bit is set then it will stay set until cleared by the host A COS bit can be cleared by writing a 1 to a COS bit that is set Writing zero will have no effect Writing Ito a bit that is 0 will do nothing COS bits may also be cleared by using the board control register Byte clears or using the board control master clear Table 3 8 Change of State register Change of State Data bits 0 16 Writing a 1 will clear a bit that 1s set 31 16 Reserved Undefined 3 2 5 Receive Event Counter Board Offset 0x0c 16 bits Read Write Reset to Zero This counter may be read at any time by the host Counter will increment once for every Debounced Rising edge detected on input data bit 15 When the counter 1 OxOffff and increments the Rx event overflow status bit will be set and can be used to generate an interrupt Table 3 9 Receive Event Cou2. PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 16 16 Documentation History 1 Alterations for PCIe OPTO16x16 Board Assembly 2 2010 09 15 Added PCI Sub System Identifier Section 3 2 1 Added Firmware Revision Identifiers Finished adding Mailbox Information 3 2011 02 07 Rev Re Wrote PLX EEPROM section Added Full PLX EEPROM as an Appendix Manually added the Appendix s into the Table of Contents Added Explained how the PEX8311AA works Updated Layout Picture to Rev A Added Test Register 1 and 2 Changed Register bit level descriptions Tried to Clarify descriptions Added Register Contents tables for all registers Added Note Schmidt Trigger Input has been removed Fix descriptions for COS Byte Clears Fixed Differences from OPTO32 Introduction Input s and Outputs were mixed up 4 2011 02 08 Rev Changes Per Don Revision History is on this page Period missing on page 11 Period missing on page 13 Fixed COS Polarity Type Fixed Initialization Punctuation Fixed Class code description Fixed Typo in Interrupt Appendix test for if this board generated Interrupt Made Page Numbers Consistent User Manual for the PCIe OPTO16x16 Ca
3. Board Register Descriptions Table 3 4 Register Address Map 3 2 1 Board Status Register Board Offset 0x00 32 Bits read only With Firmware Rev B this Register expanded to 32 Bits with Fields to Identify the Firmware Revision Level and the Board ID Table 3 5 Board Status Register Prior to Firmware Rev B Bits 8 31 were not used and Undefined When the FW Rev field was added it was set to 0x0l1because it was the first time the Field was Present If there is a future revision it will be adjusted to be consistent with the Actual Firmware Revision Level User Manual for the PCle OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 19 3 2 2 Board Control Register Board Offset 0x00 8 Bits write only Table 3 6 Board Control Register NOTE Bits 0 4 are self clearing pulses that are written as a 1 to clear the interrupt source The bits will then self clear so that another host operation is not required NOTE The Clear COS Bytes or the Master Clear bit 4 will clear ANY COS register bit that is set regardless of the bits Interrupt Enable Status For Individual COS bit clearing Write a 1 to the COS bit you wish to clear Event Overflow status will only be cleared by Clear Event Overflow or by Master Clear Bit 4 Loading the Event Counter WILL NOT clear out the event overflow status 3 2 3 Received Data Register
4. replaceable bias resistors labeled RIN using standard 8 pin SIP isolation resistors These bias resistor packages are socketed for easy replacement One bias resistor package will affect the input channels on nibble boundaries as follows Table 2 2 Input Channels Bias Resistors Locations Input Channels IN thru IN IN CH04 thru IN CH07 IN CHO8 thru IN IN CH12 thru IN 5 Current Limiting Resistor Values should be chosen to provide a Minimum input current of 2 3 mA Typical resistor values for input voltage levels are as follows Table 2 3 Input Channels Bias Resistor Values Input Voltage Range Bias Resistor Values 2200 ohms 5100 ohms 12000 ohms 20000 ohms User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 15 2 3 1 1 Input Channels 0 15 Isolation Voltage 5000 Current Transfer Ratio 80 600 Min Input Current 2 3 mA Max Input Current 80 mA Typical Ton Toff 3 5 uSec Figure 2 Input Channels 0 15 Typical IN CH12 HI gt lt _ JIN DTA 12 RIN SOCKETED 2 2K SMT 144148 INCH12LO gt 52501 4 GND User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 16 2 3 2 Opto Isolated Outputs 2 3 2 1 Normal Outputs
5. 1 1 Device ID Vendor ID Device ID and Vendor ID are used to identify the PLX Device during configuration cycles Table 4 17 Device ID Vendor ID Register Description Value After Reset 15 0 Vendor ID Identifies the manufacturer of the device Defaults to the PCI 0x10B5 SIG issued vendor ID of PLX 31 16 Device ID Identifies the particular device Defaults to the PLX part number 0x9056 for PCI interface chip User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 24 4 1 2 Sub System ID Vendor ID Sub System ID and Vendor ID are used to identify the PCle OPTO16x16 during configuration cycles Table 4 18 Sub System ID and Vendor ID Register Description Value After Reset 15 0 Vendor ID Identifies the manufacturer of the device Defaults to the PCI Ox10B5 SIG issued vendor ID of PLX 31 16 Sub System ID Identifies the particular device Sub System ID Assigned to 0x3460 the OPTO16x16 by PLX 4 1 3 Class Code Revision When loaded from the EE Prom this register will identify the device Base Class Code Sub Class Code and Revision of the PLX Device PLX Revision is hard coded in the device Table 4 19 Class Code Revision Register 4 1 4 Mailbox 0 When loaded from the EE Prom this mailbox is used to contain values to identify the PLD revision and EE Prom Revision levels of this board Ta
6. Bits 0 3 8 15 Output Bits 0 3 contain an Optional Pullup resistor to VCC that is not normally installed Output Bits 8 15 are the same as bits 0 3 except the optional resistor does not exist Isolation Voltage 5000 V 60 Maximum Current 100 ma Typical Ton Toff 3 5 uSec Figure 3 Normal Outputs Bits 0 3 WEC VEC SIP 100K ISOL OPTIONAL SIP 470 lt 06 OUT LO 100 K isolation Resistor is Optional and is not normally installed Figure 4 Normal Outputs Bits 8 15 VEC SIP 470 lt LOG OUT CH8 HI MPSADS pTaAouTs gt lt 06 OUT CH8 LO User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 17 2 3 2 2 Diode Clamped Outputs Bits 4 7 Isolation Voltage 5000 V VCEO 60 Maximum Current 100 ma Typical Ton Toff 3 5 uSec Figure 5 Diode Clamped Outputs Bits 4 7 WEC SIP 470 PS2501 4 User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 OUT CLAMP 6 MUR120 SA28A lt PWR OUT HI 5 lt PWR OUT CHG LO 18 SECTION 3 3 CONTROL SOFTWARE 3 1 Introduction 3 2
7. M 19 3 2 Board Register Descriptions ccsccsscssscsscsssssccsccsscscecsccsssssccsssscsssssccsesescsessscccsesseesssscesssssees 19 3 2 1 Board Status Register Board Offset 0 00 sese 19 3 2 2 Board Control Register Board Offset 0x00 20 3 2 3 Received Data Register Board Offset OX04 20 3 2 4 Change of State Register Board Offset 0x08 sse eene nene 21 3 2 5 Receive Event Counter Board Offset 0 nennen nennen 21 3 2 6 COS Interrupt Enable Register Board Offset 0 10 sse nennen 21 3 2 7 COS Polarity Register Board Offset 0 014 enne eene nnn 22 3 2 8 Clock Division Register Board Offset 0 018 sse enne nnne nennen 22 3 2 9 Output Data Register Board Offset 0 01 eene 23 3 2 MO Test R gister 175 EE EAR ARE 23 3 2 1 1 Test Register 2 a eee ew ue ettet qe iie e oe tarte 23 PEX BS LIN OS auno citet ats 24 24 Device Vendor eod 24 4 12 Sub System ID Vendor ID s t eee 25 1 3 1 55 Revision i n e T ERREUR Sig FERE ERU 25 p RR EE E 25 T LI ER 25 4 1 6 Address Space 0 Range PCI to Local cesses e
8. PCle OPTO16x16 User s Manual 16 Input Bits 16 Output Bits Opto Isolator Board General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail support generalstandards com User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 General Standards Corporation Copyright C 2011 General Standards Corp Additional copies of this manual or other literature may be obtained from General Standards Corporation 8302A Whitesburg Dr Huntsville Alabama 35802 Tele 256 880 8787 FAX 256 880 8788 E mail support generalstandards com The information in this document is subject to change without notice General Standards Corp makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corp assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep current the information cont
9. Table 3 6 Board Control Register esee PEE AGES 20 Table 3 7 Received Data eaten obra u eaae SUE la 20 Table 3 8 Change of State YEplster VE e NN paw PUES 21 Table 3 9 Receive Event PRUNUS 21 Table 3 10 COS Interrupt Enable RegiStet sssssssssesssesssoosssosssoossoesssoessoesssoessocssoesssosssocsssosssoesse 21 Table 3 11 COS Polarity ReGtsterecvisessccscssussusstaiausesteneistoncssssestvouststcnsusesusasssivuseasousweserytoeceusasnee 22 Table 3 12 Clock Division a ee Erb YR E EUR 22 Table 3 13 Output Data vest peti do eis e DRTSE bdo peas do eU RR Ud 23 Table 3 14 Test Register 23 Table 3 15 Test Register 23 Table 4 16 EEPROM Register Initialization s sssssssssssssssossosssoesossoossoesosseossoesosesossoesosesosesooseseoses 24 Table 4 17 Device ID Vendor ID Register 24 Table 4 18 Sub System ID and Vendor ID Register Description eee eee eerte ene 25 Table 4 19 Class Code Revision Register eee eee eee eee eee eee eren eene eee tn sesta see ena se 25 Table 4 20 Mailbox Oi zs date 25 Table 4 21 Mailbox Ga taxed Ie Ope Hoc i oderat UP es Pid Se REDE UK ERN CLAVE VES SUR 25 Table 4 22 Space 0 Range PCI to 26 Table 4 23 Addres
10. a 11 ee 59 024 iL re 2 ve a m eeeeeeer 00000000 6 Ea fafa Ege RPIS PPI RP20 21 22 fje Taer 15 00000008 es e in TOP SILKSCREEN THIS SIDE UP cema ma mm ma 2 2 Installation 2 2 1 Physical Installation Selectable input voltage range thru use of field replaceable bias resistors using standard 8 pin SIP isolation resistors These bias resistor packages are socketed for easy replacement One bias resistor package will affect the input channels on nibble boundaries User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 13 2 2 2 Input Output Cable Connectors Table 2 1 Input Output Cable Pin Assignments INCHI2LO 60 PWROUTCHSHI INCHISLO 7 34 LOG OUTCH8LO 8 PWROUTCH7LO O gt Un 5 4 8 9 4 5 User Manual for the PCle OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 14 2 3 System Configuration 2 3 1 Opto Isolated Inputs Selectable input voltage range thru use of field
11. ained in this document General Standards Corp does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corp assumes no responsibility for any consequences resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corp reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corp This user s manual provides information on the specifications theory of operation register level programming installation of the board and information required for customized hardware software development User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 RELATED PUBLICATIONS The following manuals and specifications provide the necessary information for in depth understanding of the specialized parts used on this board EIA Standard for the RS 422A Interface EIA order number EIA RS 422A PCI Local Bus Specification Revision 2 1 June 1 1995 Questions regarding the PCI specification be forwarded to
12. ble 4 20 Mailbox 0 Value After Reset PLD Revision Level Revision Level of the FPGA on the OPTO16x16 Currently 0x02 Rev EE Prom Revision Level Revision Level of the PLX EEPROM contents Currently 0x02 Rev 4 1 5 Mailbox 1 When loaded from the EE Prom this mailbox register is used to identify the overall Board assembly level and to Identify this Assembly Table 4 21 Mailbox 1 Value After Reset 15 0 Assembly Identifier 0x0100 0x0100 Identifies the 16 16 31 16 Board Assembly Revision Level 0x0002 Currently 0x02 Rev User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 25 4 1 6 Address Space 0 Range PCI to Local Size of the Address Space required for the OPTO16x16 The OPTO16x16 uses 128 Bytes of Memory Space Table 4 22 Space 0 Range PCI to Local Value After Reset Address Space 0 Range Zero s indicate the size in Bytes of the Address Oxffffff80 Space to be reserved for the Board Bit 0 Indicates the Board is mapped into Memory Space The OPTO16x16 uses 128 Bytes of Memory Space 4 1 7 Address Space 0 Base Address Remap There is no address space Remap for the Board Bit Zero indicates that Address Space 0 is Active for writing to Local Registers on the Board Table 4 23 Address Space 0 Base Address Remap Value After Reset 31 00 Address S
13. er Output Data Register Controls the Opto Isolated Outputs 31 16 Reserved Undefined 3 2 10 Test Register 1 32 Bits Read Write Reset to Zero 32 bit Register does not do anything It was added to test 8 16 and 32 Bit Reads and Writes Table 3 14 Test Register 1 Test Register 1 Can be used for anything 3 2 11 Test Register 2 32 Bits Read Write Reset to Zero 32 bit Register does not do anything It was added to test 8 16 and 32 Bit Reads and Writes Table 3 15 Test Register 2 Test Register 2 Can be used for anything User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 23 4 PEX 8311 Notes The PCIe OPTO16x16 uses the PLX Technologies PEX8311AA Interface chip In the System Devices list this chip will show up as 2 devices 8311 PCIe to PCI bridge and a 9056 PCI to local bus adapter 4 1 Initialization When the PEX8311 15 reset the 9056 part of the chip will initialize itself from an on board serial EEPROM that is programmed at General Standards A brief description of some of the Registers follows Table 4 16 EEPROM Register Initialization Eeprom Addr Addr Description Value After Reset 0 4 Space 0 range PCI to Local 0x18 Space 0 Base Address remap 0x00000001 A list of the full EEPROM contents is located in Appendix B 4
14. he Event Counter overflow NOTE NOTE NOTE NOTE The Master Clear will Clear ALL COS Bits The Byte Clear s will ALSO Clear ALL COS Bits in that Byte To Only Clear the Bit generating the Interrupt you must use the individual Clear s as Described below Or Individual Clears for the COS and Event Overflow Outportl Opto register base address 0x08 0x08421 Long word write Offset 0x08 COS register Clear COS Bit s 0 5 10 and 15 If they are set Outportb Opto register base address 0x00 Oxc8 Byte write Turn LED off Enable Event Overflow Interrupt Clear Event Overflow The final step is the write to the PLX interface that will enable it to generate Interrupts onto the PCI bus Outportl PLX base address 0x068 0x00900 Long word write PLX interrupt control register Bit s 8 and 11 Enable Local input to generate PCI interrupts User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 27 In the Interrupt Handler there is NO action required to with the PLX Interface chip The only requirement to remove the Asserted interrupt is to remove the Local source of the interrupt Which would be the COS bit or the event overflow temp inportb Opto register base address 0x00 Read the OPTO Board Status register if temp amp 0x010 0x010 Master Inter
15. nputs e Selectable input voltage range thru use of field replaceable bias resistors e Industry Standard 8 Pin Sip Resistors 770 83 Rxx Series e 16 optically isolated outputs 12 normal 4 Diode Clamped e Software Programmable clock debounce rate e Software Programmable Change of State detection Rising edge or falling edge per input channel e Software Programmable Interrupts on any or all Change of State bit s e Software Pre loadable Event counter on Input Bit 15 e Programmable Interrupt on Event Counter Overflow e Built in Self Test Features e Registers are Read Write e Ability to monitor the Debounce Clock The board uses the PEX 8311 PCIe single lane interface chip to provide the advanced features of the PCIe interface environment These features include e Programmable Little Endian Big Endian swapping e PCIe cycles Asynchronous to local bus cycles e Software Programmable board base address User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 12 SECTION 2 2 INSTALLATION AND MAINTENANCE 2 1 Card Configuration Figure 1 Board Layout RPS RP RPIO fa RPI2 een eJ Ye re l ees Ney 00000000 essseess GS ee eto eto 000200000 e wo Yi 00000000 9 ee 0n 3
16. nter 31 16 Reserved Undefined 3 2 6 COS Interrupt Enable Register Board Offset 0x010 16 bits Read Write Reset to Zero Each bit will be bitwise ANDED with the COS register and all of the results OR ed together to generate an Interrupt A 1 will enable the corresponding interrupt A 0 will disable that bit from generating an interrupt Table 3 10 COS Interrupt Enable Register COS Interrupt Enable Register 1 Enable Interrupt for that corresponding COS bit 31 16 Reserved Undefined User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 21 3 2 7 COS Polarity Register Board Offset 0x014 16 bits Read Write Reset to Zero When the corresponding bit is zero the COS detection for that bit will be set by a detected High to Low transition When Set to a the COS detection for that bit will look for Low to High transitions Reset to all zeros Table 3 11 COS Polarity Register COS Polarity Register 1 Low to Hi will set COS Bit 0 to Low will set COS Per Bit 31 16 Reserved Undefined 3 2 8 Clock Division Register Board Offset 0x018 24 bits Read Write Reset to Zero Table 3 12 Clock Division Register Clock Division Register Sets the Clock Division Rate 31 24 Reserved Undefined NOTE gt gt gt gt when altering this register disable all interrupts and expect
17. pace 0 Base Address Remap 0x01 0x00000001 Bit 0 Indicates that Address Space 0 is Active User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 26 Appendix INTERRUPTS For Interrupt Operation the Desired Interrupts are Enabled on the Opto isolator board AND Interrupts MUST be enabled At Thru the PLX Interface chip To enable Event Counter Overflow Interrupts Bit 6 of the Board Control Register must be set to 1 outportb Opto register base address 0x00 Oxc0 Byte write Turn LED off Enable Event Overflow Interrupt outportl Opto_register_base_address OxOc OxOfffe Long word write Event Counter 2 The Second Rising Edge detected will generate the Interrupt To Enable COS Interrupts Any All Desired COS Interrupt bit s are enabled thru the COS Interrupt Enable Register outportl Opto register base address 0x010 0x08421 Long word write Offset 0x010 Enable Interrupts on COS Bit s 0 5 10 and 15 other Machine dependent actions should be taken before the final steps in the process Make ABSOLUTELY sure that there is NO Pending status laying around that is already setting an interrupt action Either use the master clear s outportb Opto register base address 0x00 Oxdf Byte write Turn LED off Enable Event Overflow Interrupt Master Clear All COS and Clear t
18. rd Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Contents ER RUTTO 11 pem 11 1 1 Differences From OPTO32 Family 4 crees eese eese eene seen netta netta setas etta setas etos setas etas etas ens 11 1 2 Card Features 12 2 INSTALLATION AND MAINTENANCE ssccsssrssssssssccsssssseccssscsescsscessccsssssssscssssssssssccscesssees 13 2 1 Card or Ieri te tne tirer en rna epe a E ao Rev ee eL VP Tes ee PUR e SEO Ee e een re eine 13 2 2 1015 ossos ssov ssis 13 2 2 Physical Installation uio eee e estre te OR qi m ie aep ee e TEES 13 2 22 Input Output Cable Connectors eeki err ertet etre edes 14 2 3 System Configuration ccsccccccsccsscssssscscsscsscscccessscssessscccessscssesscssesssccssssscssssscesseeesssssssoscoeees 15 2 3 T OptosIsolated Inputs 2c i etd tu n D RR s 15 2 3 2 Opto Isolated Outputs osea tee ta S Gy e esee HEART e ere CERTE HE PR E 17 SSCON TROL SOP LW ARE ss 19 3 1 IMtrOdu Ct O
19. rupt bit will be set in the Board Status Register if this board generated the Interrupt Status Bits 0 thru 3 could also be examined to Determine Which Byte generated the Interrupt Or if the Event Counter Overflow generated The Interrupt Finished processing Now It s time to clear the Pending Interrupt Outportl Opto register base address 0x08 0x08421 Long word write Offset 0x08 COS register Clear COS Bit s 0 5 10 and 15 If they are set Outportb Opto register base address 0x00 Oxc8 Byte write Turn LED off Enable Event Overflow Interrupt Clear Event Overflow To Disable Interrupt s From board write to the PLX interface Chip Outportl PLX_io_base_address 0x068 0x0000 Long word write PLX interrupt control register Clear Bit s 8 and 11 disable All PCI interrupts User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 28 Appendix PLX EEPROM Contents The Full contents of the OPTO16x16 EEPROM for the 9056 portion of the interface chip are as follows Table B 24 PLX EEPROM Contents Addr User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 29
20. s Space 0 Base Address 26 Table B 24 PLX EEPROM 29 User Manual for the PCle OPTO16x16 Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 User Manual for PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 10 1 SECTION 1 Introduction The PCIe OPTO16x16 board is a high performance Single Lane PCI Express card offering 16 Opto Isolated inputs and 16 Opto Isolated outputs 1 1 Differences From OPTO32 Family The PCIe OPTO16x16 is based on the OPTO32 family It was designed to provide a migration path from the OPTO32 family to the OPTO16 on the PCIe Bus The following differences exist between the OPTO32 and the PCIe OPTO16x16 Output Bits 0 7 are the same as the OPTO32 Family Input Bits 0 15 are the same as the OPTO32 Family Input Bits 16 23 have been removed e Output Bits 8 15 were placed where OPTO32 Input 16 23 were at Special Schmidt Trigger Input has been removed Inputs are the same True PCIe Form factor User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 11 1 2 Features e 16 optically isolated i
21. te HERO e Reg Rede 26 4 1 7 Address Space 0 Base Address Remap 26 Appendix odii 27 Appendix B PLX EEPROM Contents eerie esee eee essa seen seins essen seen seta seen senses stas 29 User Manual for the PCIe OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Figures Figure T Board 13 Figure 2 Input Channels 0 15 Typicdll sccccccccscsscsscsscsccsccssscccscssccsscccsscccccsccsesscsccsesssssccssseeeees 16 Figure 3 Normal Outputs 17 Figure4 Normal Outputs Bits 17 Figure 5 Diode Clamped Outputs Bits 4 7 18 User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B 8 General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Tables Table 2 1 Input Output Cable Pin ASsigniments cscccccsccseorcsscsscsscsccssssccscssccssssssssssesscssesscsoes 14 Table 2 2 Input Channels Bias Resistors Locations eere eee eee eene eee eene nnne etna annee 15 Table 2 3 Input Channels Bias Resistor 15 Table Register voiebustbudontactessciacdecused sipasteasicdeuassousanoskanns 19 Table 3 5 Board Reglstera 19
22. unusual results in the COS Detection register A 24 Bit clock divider is provided for programmable Debounce delays The debounce circuit registers the incoming data 3 times in a daisy chain When ALL 3 registers are high the incoming data is a high When the debounced data register contains a 1 then ALL three registers must contain zero for the debounced data to transition back to a zero The clock for these holding registers is programmable thru the clock divider The Basic clock of the board is 20 MHz 50 Ns The Basic Clock Counter will always divide by 4 200 Ns Values of 0x0000 or 0x0001 will not alter this When the clock divider is loaded with a larger value then the clock division will be count 2 2 The Total debounce time will be 3 X clock division time For Example for a 15ms debounce time Clock period should be Sms 5ms 50 Ns 100000 2 99998 99998 2 49999 0x0c34f Hex User Manual for the PCle OPTO16x16 Card Revision A Manual Revision B General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 22 3 2 9 Output Data Register Board Offset 0 01 16 bits Read Write Reset to Zero The 16 bit output data register Reset to All Zero s Writing a 1 to a bit will make that opto output conductive and current will flow from to LO Writing a 0 will turn the opto off and the output will be Non Conductive from HI to Table 3 13 Output Data Regist
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