the user manual for the OPTO32B
Contents
1. 17 3 2 1 Board Status Register Board Offset 0x00 eren nnne 17 3 2 2 Board Control Register Board Offset 0x00 nennen enne 18 3 2 3 Received data register Board Offset 0x04 enne 18 3 2 4 Change of state register Board Offset 0 08 sse eene nennen nennen enne 18 3 2 5 Receive Event Counter Board Offset eene 18 3 2 6 COS Interrupt enable register Board Offset 0 010 ener 18 3 2 7 COS Polarity register Board Offset 0 014 19 3 2 8 Clock Division Register Board Offset 0 018 19 3 2 9 Output data register Board 1 19 4 PEX 9080 3 esaet isa OE tont caddie 20 4 1 BI UClivecot 20 4T Device ID CO Emi diste eot 20 4 1 2 lass Code Revisiom ID eir tte E C EE UE UE Ie TRU ER GE E 21 4 1 3 Max Latency Min Grant Int Pin Int Line Routing 21 4 1 4 Mailbox 0 User 4 22 4 1 5 Mailbox V User defined iie heehee na ee ae AS 22 4 1 6 Range PCI to Local HR RI THU 23 4 1 7 Local Base Address TOH sse eene enne ennt erre nennen een 23 44 8 Big Little Endi2. gt PS2501 4 lt OUT CHO 100 K isolation Resistor is Optional and is not normally installed User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 15 2 3 2 2 Diode Clamped Outputs Isolation Voltage 5000 V Max 60 V Maximum Current 100 ma Typical Ton Toff 3 5 uSec Figure 5 Diode Clamped Outputs Bits 4 7 vec SIP 470 gt 52501 4 User Manual for the PCI OPTO32B Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 c PWR OUT CLAMP 6 MUR120 SA28A lt PWR OUT CHG HI 05 lt PWR OUT CH6 LO 16 SECTION 3 3 CONTROL SOFTWARE 3 1 Introduction 3 2 Board Register Descriptions Table 3 6 Register Address Map 8 bits Read Write 3 2 1 Board Status Register Board Offset 0x00 8 Bits read only Table 3 7 Board Status Register Bit 0 Int Byte LO Out bits 7 0 COS interrupt status Bit 1 Int Byte MD Out bits 15 8 COS interrupt status Bi 2 Int Byte HI Out H Bits 23 16 COS interrupt status Bit 3 Rx Event Overflow H event overflow status User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Hun
3. 2 User s Manual 24 Input Bits 8 Output Bits Opto Isolator Board General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Fax 256 880 8788 URL www generalstandards com E mail support generalstandards com User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 PREFACE General Standards Corporation Preliminary Revised July 20 2000 Copyright C 2000 General Standards Corp Additional copies of this manual or other literature may be obtained from General Standards Corporation 8302A Whitesburg Dr Huntsville Alabama 35802 Tele 256 880 8787 FAX 256 880 8788 E mail support generalstandards com The information in this document is subject to change without notice General Standards Corp makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Although extensive editing and reviews are performed before release to ECO control General Standards Corp assumes no responsibility for any errors that may exist in this document No commitment is made to update or keep cu
4. Interrupt s From the board write to the PLX interface Chip Outportl PLX 1o base address 0x068 0x0000 Long word write PLX interrupt control register Clear Bit s 8 and 11 disable PCI interrupts User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 43
5. 23 Table 4 16 Local Base Address remap eee eee e eene eese eee netta aset 23 Table 4 17 Big Little Endian Register Description e eee eee eee 24 Table 4 18 Bus region descriptors for PCI to Local e eee eee cette eren eene etna nnn 25 Table 4 19 PCI CONFIGURATION REGISTERS ceres sees eee eene etna 27 Table 4 20 PCI Configuration ID Register Description 28 Table 4 21 PCI Command Register Description e ecce eren sees eerte e eene enne ttn 29 Table 4 22 PCI Status Register Description eese eee ee eene nete neenon nane ee 30 Table 4 23 PCI Revision ID Register Description eere eee eee esee eene eene ee enne eee anna enn 31 Table 4 24 PCI Class Code Register Description eee e eee eere eee eee eren nenne eene 31 Table 4 25 PCI Base Address Register Description ee 32 Table 4 26 PCI Base Address Register Description eee eese eese eene seen netten etna neenon 33 Table 4 27 PCI Base Address Register Description eere ee eese eene seen netten etn neenon 33 Table 4 28 PCI Interrupt Line Register Description ee
6. Field Description Read Write Value After e output to go high A value of 0 will cause the output to go low General Purpose Input A valve of 1 indicates that USERI input pin 7 15 high A value of 0 indicates that USERI is low EEPROM clock for Local or PCI bus reads or writes to EEPROM Toggling this bit generates an EEPROM clock Refer to the manufacturer s data sheet for the particular EEPROM being used EEPROM chip select For Local or PCI bus reads or writes to Yes EEPROM setting this bit to a 1 provides the EEPROM chip select Write bit to EEPROM For writes this output bit is the input to Yes EEPROM The EEPROM clock clocks it into the EEPROM Read EEPROM data bit For reads this input bit is the output of the EEPROM The EEPROM clock clocks it out of the EEPROM EEPROM present A 1 in this bit indicates that an EEPROM is present Reload Configuration Registers When this bit is 0 writing a 1 causes the PLX9080 3 to reload the PCI configuration registers from EEPROM PCI Adapter Software Reset A value of 1 written to this bit will hold the local bus logic in the PLX9080 3 reset and LRESETO asserted The contents of the PCI configuration registers and Shared Run Time registers will not be reset Software Reset can only be cleared from the PCI bus Local Init Status 1 local init done Responses to PCI accesses will be RETRYs until this bit is set While Input NB is asserted low this
7. Image Scaling Added Checked Current Limit notes on Output Circuit Added Checked Extra Output Resistor is marked Optional User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Contents 9 1 1 Differences From 2 10103110 9 1 2 10 2 INSTALLATION 11 VES YIEeD nini 11 2 2 H 12 2 2 1 Physical Installation eee ee rH ite e c E e e CH Pe dne qi 12 2 2 2 Input Output Cable 12 2 3 D M 13 2 31 Optorisolated Inputs oin e terere m e 13 2 32 Opto solated Outputs tert RYE p I HT UE a E 15 3 CONTROL SOF TVARE disini tte 17 3 1 Introduction 17 3 2 Board Register Descriptions ceres ecce eese ee eene
8. n descriptor utt tester Ue nto heben tuer Peres 24 4 1 9 Bus region descriptors for PCI to nennen enne E E 25 4 2 PCI Configuration Registers eere 27 4 2 1 PCI Configuration ID Register Offset 006 28 4 2 2 PCI Command Register Offset 04 4 4 4 00000000000000000000000000000000000000000000000000 ener 29 4 2 3 PCT Stat s Register Offset eter m ate e edet tette Reed re 30 4 2 4 PCI Revision ID Register Offset 086 eren 31 4 2 5 PCI Class Code Register Offset 09 Oh eene neret nnne nennen 31 4 2 6 PCI Base Address Register for Memory Access to Runtime Registers Offset 0 32 4 2 7 PCI Base Address Register for Access to Runtime Registers Offset 14h esses 33 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 4 2 8 PCI Base Address Register for Access to Local Address Space 0 Offset 18h sss 33 4 2 9 PCI Interrupt Line Register Offset 34 4 2 10 PCI Interrupt Pin Register Offset ennemi 34 4 3 Shared Run Time Registers 1 4220 ene eene ene etna netten asset tss etes esee sese teens esee ens seen 35 4 3 1 Big Little Endian Descriptor Register PCI OCh esse
9. 1 7 Local Base Address remap Not used This register should always be set to 0x001 to enable address decode Table 4 16 Local Base Address remap Field Description Read Write Value After Rosoi Space 0 Enable A 1 value enables Decode of PCI addresses for EER Slave access to local space 0 A value of 0 disables Decode 311 NotUsed 000 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 23 4 1 8 Big Little Endian descriptor Upon reset the board is configured for Little Endian operation Bit 2 can be used to program the board for Big Endian operation If Endian mode is changed Bit 4 should always be 0 Bits 0 and 1 apply to Direct Bus Master devices and do not apply to the PCI OPTO32 The PCI OPTO32B is not a direct bus master Table 4 17 Big Little Endian Register Description Field Description Read Write Value After 0 Configuration Register Big Endian mode Does Not Apply IM Direct Master Big Endian mode Does Not Apply S ps Direct Slave Address Space 0 Big Endian mode A 1 value specifies that Big Endian data ordering is used for Direct Slave accesses to local Address Space 0 A value of 0 specifies Little Endian ordering ee Used 4 Big Endian byte lane mode Must be 0 31 5 User Manual for the PCI OPTO32B Card Revision A Manu
10. 3 259 s a FE AE au agp pap C4 Ube BE rz RP4 see ee exe macs es gem C9 RP6 RPI RR LE a U10 208 R14 585 R6 ed lec lee D 2 e 8 gt RP19 R4 MEM 5 i 15 gt Pa RP ERR X ose re eI eL Lee le Lee e C21 RP16 RP15 RP RPIS BERE matzo RP21 RP23 RP27 RP10 s c C24 sed e e e ed re amp 012 eT OLEE P User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 11 2 2 Installation 2 2 4 Physical Installation Selectable input voltage range thru use of field replaceable bias resistors using standard 8 pin SIP isolation resistors These bias resistor packages are socketed for easy replacement One bias resistor package will affect the input channels on nibble boundaries 2 2 2 Input Output Cable Connectors Table 2 3 Input Output Cable Pin Assignments PIN NUMBER SIGNAL IN CH00 HI IN CH00 LO IN CHO HI IN CH01 LO IN 02 HI IN C
11. A 1 value enables bursting Yes es 24 Memory Space 0 Burst Enable A 1 value enables bursting A value Yes of 0 disables bursting Yes Yes A value of 0 disables bursting 27 Direct Slave PCI write mode A 0 indicates that the PLX9080 3 should disconnect when the Direct Slave write FIFO is full A 1 indicates that the PLX9080 3 should de assert TRDY when the write FIFO is full PCI Target Retry Delay Clocks Contains the value multiplied by 8 of the of PCI bus clocks after receiving a PCI Local read or write access and not successfully completing a transfer Only pertains to Direct Slave write when bit 27 is set to 1 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 26 4 2 PCI Configuration Registers After power up the PLX interface needs to be initialized for PCI bus operation The PCI interface is initialized thru PCI configuration cycles The primary purposes of PCI configuration cycles are to l Identify any boards found thru the Device ID and Vendor ID 2 Assign addresses for memory mapped and access The base address registers at offsets 0x010 and 0x014 assign addresses for access to PLX registers The register at offset 0x018 assigns the address for access to the PCI OPTO32B board registers described in section 3 2 Identify Interrupt routing 4 Enable the board for PCI bus accesses In t
12. access to runtime registers Default 256 bytes I O Base Address Base Address for I O access to runtime registers Default 256 bytes 4 2 8 PCI Base Address Register for Access to Local Address Space 0 Offset 18h This register is used to set the base address to access the PCI OPTO32B registers contained on the PCI DPTO32B board The PCI OPTO32B registers are described in section 3 2 The default configuration is to place PCI OPTO32B registers into PCI I O space using 64 bytes of I O Space Table 4 27 PCI Base Address Register Description Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Location of register 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 MByte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved DEE ege reads address space User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 33 4 2 9 PCI Interrupt Line Register Offset 3Ch The Interrupt Line Routing Register should be filled in during initialization of the PCI OPTO32B board by the host processor The PCI OPTO32B will generate interrupts using the INTA connection of the PCI location it is plugged into The host processor should fill in the host interrupt level that INTA is connected to Ta
13. bridge device Yes Local 80h a 41 3 Max Latency Min Grant Int Pin Int Line Routing Value Latency and Grant are for DMA Applications The PCI OPTO32 does not use DMA and these are not used Interrupt Pin identifies which interrupt on the PCI PCI connector this device is connected to The PCI OPTO32B is connected to INTA The other interrupt pins are not connected Interrupt line routing is host dependent and should be filled in by the host processor during PCI configuration Table 4 12 PCI Interrupt Line Register Description p interrupt controller s the devices interrupt line is connected to Interrupt Pin register Indicates which interrupt pin the device uses Yes Local The following values are decoded Only Interrupt Pin INTA INTB INTC INTD Min Gnt Used to specify how long a burst period the device needs Yes Local assuming a clock rate of 33 MHz Value is multiple of 1 4 usec Only increments 31 24 Max Lat Used to specify how often the device needs to gain Yes Local access to the PCI bus Value is multiple of 1 4 usec increments Only User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 21 4 1 4 Mailbox 0 User defined When loaded from the EE Prom this mailbox is used to contain values to identify the PLD revision and EE Prom Revision levels of t
14. for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 1 2 Features e 24 optically isolated inputs Selectable input voltage range thru use of field replaceable bias resistors 8 optically isolated outputs 4 normal 4 Diode Clamped e Software Programmable clock debounce rate e Software Programmable Change of State detection Rising edge or falling edge per input channel e Software Programmable Interrupts on any or all Change of State bit s e Software Pre loadable Event counter on Input Bit 23 e Programmable Interrupt on event counter overflow e Built in Self Test Features Registers are Read Write e Ability to monitor the Debounce Clock The board uses the PLX 9080 3 PCI interface chip to provide the advanced features of the PCI interface environment These features include e Programmable Little Endian Big Endian swapping PCI cycles Asynchronous to local bus cycles e Software Programmable board base address User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 10 SECTION 2 2 INSTALLATION AND MAINTENANCE 2 1 Card Configuration m ala Figure 1 Board Layout gt c U4 mm C2 fal x 9 e edI evedI e
15. resistor values for input voltage levels are as follows Table 2 5 Input Channels Bias Resistor Values Input Voltage Range Bias Resistor Values 2200 ohms 5100 ohms 12000 ohms 20000 ohms User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 13 2 3 1 1 Channels 0 22 Isolation Voltage 5000 V Current Transfer Ratio 80 600 Min Input Current 2 3 mA Max Input Current 80 mA Typical Ton Toff 3 5 uSec Figure 2 Input Channels 0 22 Typical IN CH22 HI gt lt ___JIN DTA 22 RIN SOCKETED 2 2K SMT IN CH22LO gt 52501 4 GND 2 3 1 2 Channel 23 Isolation Voltage 7500 V Min Input Current 2 3 mA Max Input Current 60 mA Max Ton Toff 4 4 uSec Figure 3 Input Channel 23 VEC VEC INCH23 HI gt RIN SOCKETED 2 2K SMT 1N4448 23 INCH23LO gt H11L1 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 14 2 3 2 Opto isolated Outputs 2 3 2 1 Normal Outputs Isolation Voltage 5000 V Max 60 V Maximum Current 100 ma Typical Ton Toff 3 5 uSec Figure 4 Normal Outputs Bits 0 3 vcc WEC SIP 100K ISOL OPTIONAL SIP 470 LOG OUT CHO HI 5
16. 2 3 Input Output Cable Pin Assignments ee eere eerte e eee eene enne nne tn esee 12 Table 2 4 Input Channels Bias Resistors Locations e eere e eese e eene entente 13 Table 2 5 Input Channels Bias Resistor Values eee ee cease eee ee eene seen tenen 13 Table 3 6 Register Address MAD csciicssessivisesssievssstoncssasesssvonststwasusessesoeubicesiedscsunsvabadeiaeeadevarovassonse 17 Table 3 7 Board Status ROGiSt TENE PE 17 Table 3 8 Board Control Ce sie e eve 18 Table 4 9 EEPROM Register Initialization eere ee eee eee eee eee eene tentata anat 20 Table 4 10 PCI Configuration ID Register Description eee ecce eee eee eren eene nnt tnn 20 Table 4 11 PCI Revision ID Register Description e eere eee eee ee eee ee eene nete enne 21 Table 4 12 PCI Interrupt Line Register Description eee eee esee e e eene eene eee 21 Table 4 13 Mailbox qiu eau aliut 22 4 14 Mailbox 22 Table 4 15 Range PCI to Local Register Description eee eee ee eese eene eene eene etta
17. AL 35802 Phone 256 880 8787 28 4 2 2 PCI Command Register Offset 04h Must be initialized by the Host CPU Should be the last register initialized during configuration Bits 0 and 1 should be set to a 1 Bit 6 can also be set as desired 16 bit register If written as a 32 bit register the upper 16 bits should be 0x0280 Typical value would be 0x02800003 Table 4 21 PCI Command Register Description Field Description Read Write Value After Reset I O Space A value of 1 allows the device to respond to I O space accesses A value of 0 disables the device from responding to I O Space accesses Memory Space A value of 1 allows the device to respond to memory space accesses A value of 0 disables the device from responding to memory space accesses Master Enable A value of 1 allows the device to behave as a bus master A value of 0 disables the device from generating bus master accesses Memory Write invalidate Enable Direct Master does not apply Yes 0 7 E Parity Error Response A value of 0 indicates that parity error 15 Yes Yes ignored and operation continues value of 1 indicates that parity MEN checking is enabled Wait Cycle Control Controls whether or not the device does Yes Yes address data stepping A 0 value indicates the device never does stepping A value of 1 indicates that the device always does stepping This value 1 hardwired to 0 Fast Back to Back Enable Indicates what type of
18. Field Description Read Write Value After 3 0 32bitmallboxregiter Yes 4 3 5 Mailbox Register 3 PCI 4Ch Not Used Table 4 35 Mailbox Register 3 Description Field Description Read Write Value After URS 3 0 32bitmallboxregiter Yes User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 37 4 3 6 Interrupt Control Status PCI 68h Bits 8 and 11 MUST be set for the Local PCI OPTO32B interrupt to generate a PCI interrupt to the host Doorbell interrupts are not used Bit 16 concerns the PCI bus generating an interrupt of a local processor There is no local processor on the PCI OPTO32B so Bit 16 will have no affect Table 4 36 Interrupt Control Status Field Description Read Write Value After Reset Enable Local bus LSERR A value of 1 will enable the PLX9080 Yes Yes 3 to assert LSERR interrupt output when the PCI bus Target Abort or Master Abort status bit is set in the PCI Status Configuration Register PLX9080 3 Master Transfer a PLX9080 3 Slave access a PCI bus SERR LT3 Not Used Se 8 PCI interrupt enable A value of 1 will enable PCI interrupts Yes Yes 1i PCI doorbell interrupt enable A value of 1 will enable doorbell interrupts Used in conjunction with PCI interrupt enable Clearing the d
19. H02 LO IN CH03 HI IN CH03 LO IN CH04 HI IN CH04 LO IN CH05 HI IN CH05 LO IN CH06 HI IN CH06 LO IN CH07 HI IN CH07 LO IN CH08 LO IN CH09 HI IN CH09 LO IN CH10 LO IN CH11 HI IN CH11 LO IN CH12 HI IN CH12 LO IN CH13 LO IN HI IN CH14 LO IN CH15 HI IN CH15 LO IN CH16 LO User Manual for the PCI OPTO32B Card Revision A Manual Revision E IN CH08 HI IN CH10 HI IN CH13 HI IN CH16 HI LOG OUT HI LOG OUT CH0 LO LOG OUT CH1 HI LOG OUT CH1 LO LOG OUT CH2 HI LOG OUT CH2 LO LOG OUT CH3 HI LOG OUT CH3 LO PWR OUT CH4 HI PWR OUT CH4 LO PWR OUT CLAMP 4 07 PWR OUT 5 HI PWR OUT 5 LO PWR OUT CLAMP 5 PWR OUT CLAMP 6 PWR OUT CH6 HI PWR OUT CH6 LO 66 1 PWROUTCLAMP 7 PWR OUT CH7 HI 68 PWROUTCH7LO General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 12 2 3 System Configuration 2 3 1 Opto isolated Inputs Selectable input voltage range thru use of field replaceable bias resistors labeled RIN using standard 8 pin SIP isolation resistors These bias resistor packages are socketed for easy replacement One bias resistor package will affect the input channels on nibble boundaries as follows Table 2 4 Input Channels Bias Resistors Locations Input Channels IN thru IN CHO3 IN 4 thru IN CH07 Current Limiting Resistor Values should be chosen to provide a Minimum input current of 2 3 mA Typical
20. L assertion A Yes No Olh value of 01 is medium Target Abort When this bit is set to a 1 this bit indicates the PLX9080 3 has signaled a target abort Written a 1 to this bit clears the bit 0 Received Target Abort When set to a 1 this bit indicates the PLX9080 3 has received a target abort signal Written 1 to this bit clears the bit 0 Received Master Abort When set to a 1 this bit indicates the PLX9080 3 has received a master abort signal Writing a to this bit clears the bit 0 Signaled System Error When set to a 1 this bit indicates the PLX9080 3 has reported a system error on the SERR signal Writing a to this bit clears the bit 0 Detected Parity Error When set to a 1 this bit indicates the PLX9080 3 has detected a PCI bus parity error even if parity error handling is disabled the Parity Error Response bit in the Command Register is clear One of three conditions can cause this bit to be set 1 The PLX9080 3 detected a parity error during a PCI address phase 2 the PLX9080 3 detected a data parity error when it was the target of a write 3 the PLX9080 3 detected a data parity error when performing a master read operation Writing a 1 to this bit clears the bit 0 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 30 4 2 4 PCI Revision ID Register Offset 08h Identifies the sil
21. Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 1 SECTION 1 Introduction The PCI OPTO32B board is a high performance PCI card offering 24 optoisolated inputs and 8 optoisolated outputs 1 1 Differences From PMC OPTO32 The PCI OPTO32B is an update to the PCI OPTO32 It was redesigned to reduce power consumption and simplify board assembly Every effort was made to ensure that the PCI OPTO32B and the PMC OPTO32 are as close to hardware and software interchangeable as possible The following differences exist between the PMC OPTO32 and the PCI OPTO32B The PCI9060ES was replaced with a PCI9080 3 The PCI9080 will request 256 bytes of I O space for it s register mapping the PCI9060 only requested 128 bytes of I O space The PCI9080 will request 256 bytes of memory space for it s register mapping the PCI9060 only requested 128 bytes of memory space Optional assembly with PCI9060ES is available Order Code 9060ES 1 Xilinx FPGA replaces the 3 Mach 5 devices used on the PCI OPTO32 The Xilinx runs at 3 3V to reduce power consumption An on board 3 3V Voltage Regulator removes the need for 3 3Volt power from the PCI connector Input Bias resistor reference designators have changed as follows Table 1 1 Bias resistor was is list Description Value Table 1 2 Other Resistor Was Is Changes Output Bias For Testing 100K Optional User Manual
22. active 22 21 23 24 7 A value of 1 indicates that the BIST interrupt is active The BIST built in self test interrupt is generated by writing a 1 to bit 6 of the PCI Configuration BIST register Clearing bit 6 clears the interrupt Refer to the BIST register for a description of self test A value of 0 indicates that a Direct Master was the bus master during a Master or Target abort 26 25 2 A value of 0 indicates that a Target Abort was generated by the PLX9080 3 after 256 consecutive Master retries to a Target User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 39 4 3 7 EEPROM Control Command Codes User I O Control PCI 6 This register 1 not used in normal operation It does contain special bits that could be used in special circumstances Bits 15 thru 8 will have no affect the PCI OPTO32B does not generate direct bus master cycles Bits 16 and 17 User Output and Input are connected on the board but at this time do not perform any function they are reserved for future use Bits 24 thru 28 can be used to read or re program the PLX configuration EEPROM they should never be used without consulting the factory Bit 30 will perform a software reset of the local side of the PCI OPTO32 everything on the board except the PLX9060ES Table 4 37 EEPROM Control PCI Command Codes User I O Control
23. al Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 24 4 1 9 Bus region descriptors for PCI to Local The following values should never be altered Bits 1 0 0x00 Local bus is 8 bits Bit 6 0 Ready Input is not used Bit 7 0 Bterm Input is not used Table 4 18 Bus region descriptors for PCI to Local Field Description Read Write Value After Reset Memory Space 0 Local Bus Width Programmable for the Cx and 0x00 Jx modes only A value 00 indicates a bus width of 8 bits A value 8 bit local bus of 01 indicates a bus width of 16 bit a value of 10 or 11 indicates a width bus width of 32 bits 53 Memory Space 0 Internal Wait States data to data Yes 0 D Ready input Bterm input Memory Space 0 Prefetch Disable If mapped into memory space a 0 enables read pre fetching a value of 1 disables pre fetching If pre fetching is disabled the PLX9080 3 will disconnect after each memory read Expansion ROM Space Prefetch Disable A 0 enables read pre fetching a value of 1 disables pre fetching If pre fetching is disabled the PLX9080 3 will disconnect after each memory read Read Prefetch Count Enable When set to a 1 and memory pre fetching 15 enabled the PLX9080 3 will pre fetch up to the number of Lwords specified in the Prefetch count 14 11 Read Prefetch Count When the Read Pre fetch Count Enable is set to a 1 and memory pre fetch
24. bit will be forced to 1 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 40 4 3 8 PCI Configuration ID Register PCI 70h The Device ID and Vendor ID can be read at this offset using normal PCI bus reads configuration cycles are not required It is useful for device driver troubleshooting Table 4 38 PCI Configuration ID Register Description Field Description Read Write Value After Reset Vendor ID Identifies the manufacturer of the device Defaults to 10B5h the PCI SIG issued vendor ID of PLX If no EEPROM is present and pin NB no local bus initialization is asserted low Device ID Identifies the particular device Defaults to the PLX 906Eh part number for PCI interface chip if no EEPROM is present and pin NB no local bus initialization is asserted low User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 41 Appendix INTERRUPTS For Interrupt Operation the Desired Interrupts are Enabled on the Opto isolator board AND Interrupts MUST be enabled At Thru the PLX Interface chip To enable Event Counter Overflow Interrupts Bit 6 of the Board Control Register must be set to a 1 outportb Opto register base address 0x00 Oxc0 Byte write Turn LED off Enable Event Ov
25. ble 4 28 PCI Interrupt Line Register Description Field Description Read Write Value After Reset Interrupt Line Routing Value indicates which input of the system interrupt controller s the devices interrupt line is connected to 4 2 10 PCI Interrupt Pin Register Offset 3Dh The PCI OPTO32B board will generate all interrupts the INTA line of the PCI Connector The host should fill in which host interrupt the INTA line is connected to in the Interrupt Line Routing Register Table 4 29 PCI Interrupt Pin Register Description Field Description Read Write Value After Rosoi Interrupt Pin register Indicates which interrupt pin the device uses Yes Local The following values are decoded Only 0 Nolnterrupt Pin 1 INTA 2 INTB 3 INTC 4 INTD User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 34 4 3 Shared Run Time Registers After the board has been configured for PCI Bus operation the run time registers within the PLX9080 3 are available to the host processor The most important of these are the Big Little Endian Descriptor register and the Interrupt Control Status register Other registers listed provide information and can be used for special functions Table 4 30 SHARED RUN TIME REGISTERS PCI To ensure software compatibility with other versions of PLX9080 3 Value After Reset offset fro
26. dress bits 7 thru 31 are decoded Address bits 0 thru 6 are ignored The PLX9080 3 registers will take up 256 bytes in memory space The Host CPU will then assign an address for Memory Access to PLX9080 3 internal registers and write the assigned address into the base address register Table 4 25 PCI Base Address Register Description Field Description Read Write Value After Reset Memory space indicator A value of 0 indicates register maps into Memory space value of 1 indicates the register maps into I O space Location of register 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 Mbytes memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved pole eu reads IT qu registers Default 256 bytes mE EN registers User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 32 4 2 7 PCI Base Address Register for I O Access to Runtime Registers Offset 14h This register 1s used to set the base address to access the PLX internal registers using PCI I O access cycles Table 4 26 PCI Base Address Register Description Field Description Read Write Value After Rosoi Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Reserved Base Address Base Address for I O
27. e eee eee e eee eene eene eee tenant 34 Table 4 29 PCI Interrupt Pin Register Description eee e eee eene ee eee e eerte netten netta 34 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table 4 30 SHARED RUN REGISTERS wssssccseussendsessscsssusssvsssageastesssuetovscvssensaveuseesseesden 35 Table 4 31 Big Little Endian Register Description eee 36 Table 4 32 Mailbox Register 0 Description eere eee eene eese eee nente einst tn setas etta 37 Table 4 33 Mailbox Register 1 Description e eeee eee eese eese eee 37 Table 4 34 Mailbox Register 2 Description eee eee eee eee ee eene eren netten etas eines enn 37 Table 4 35 Mailbox Register 3 Description eese eren eene netten etta ase esten 37 Table 4 36 Interrupt Control Status eere eee eee ee eene see 38 Table 4 37 EEPROM Control PCI Command Codes User 1 40 Table 4 38 PCI Configuration ID Register Description eee eee netten ente eeen nnno 41 User Manual for the PCI OPTO32B Card Revision A Manual
28. erflow Interrupt outportl Opto register base address 0 0 OxOfffe Long word write Event Counter 2 The Second Rising Edge detected will generate the Interrupt To Enable COS Interrupts Any All Desired COS Interrupt bit s are enabled thru the COS Interrupt Enable Register outportl Opto register base address 0x010 0x08421 Long word write Offset 0x010 Enable Interrupts on COS Bit s 0 5 10 and 15 other Machine dependent actions should be taken before the final steps in the process Make ABSOLUTELY sure that there is NO Pending status laying around that 1s already setting an interrupt action Either use the master clear s outportb Opto register base address 0x00 Oxdf Byte write Turn LED off Enable Event Overflow Interrupt Master Clear All COS and Clear the Event Counter overflow NOTE NOTE NOTE NOTE The Master Clear will Clear ALL COS Bits The Byte Clear s will ALSO Clear ALL COS Bits in that Byte To Only Clear the Bit generating the Interrupt you must use the individual Clear s as Described below Or Individual Clears for the COS and Event Overflow Outportl Opto register base address 0x08 0x08421 Long word write Offset 0x08 COS register Clear COS Bit s 0 5 10 and 15 If they are set Outportb Opto register base address 0x00 Oxc8 Byte write Turn LED off Enable Event Overflow Interrupt Clear Event Overflow The final step 1
29. fast back to back transfers a Master can perform on bus value of 1 indicates that fast back to back transfers can occur to any agent on the bus A value of 0 indicates that fast back to back transfers can only occur to the same agent as the previous cycle Reserved 0 SERR Enable A value of 1 enables the SERR driver A value of 0 disables driver User Manual for the PCI OPTO32B Card Revision A Manual Revision General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 29 4 2 3 PCI Status Register Offset 06h The PCI Status Register affects how the PLX9080 3 will interact with the host PCI bus This register should be left with its default value 16 bit register Table 4 22 PCI Status Register Description Field Description Read Write Value After Lo Reseved Fast Back to Back Capable When this bit is set to a 1 it indicates Yes a the adapter can accept fast back to back transactions A 0 indicates the adapter cannot Master Data Parity Error Detected This bit is set to a 1 when three Yes Yes conditions are met 1 the PLX9080 3 asserted PERR itself or observed PERR asserted 2 the PLX9080 3 was the bus master for the operation in which the error occurred 3 the Parity Error Response bit in the Command Register is set Writing a to this bit clears the bit 0 10 9 DEVSEL Timing Indicates timing for DEVSE
30. he PCI Status Command register at offset 0x04 bits 0 and 1 must be set to enable the PLX9080 3 to respond to PCI bus cycles UJ All registers may be written to or read from in byte word or long word accesses Table 4 19 PCI CONFIGURATION REGISTERS PCI To ensure software compatibility with other versions of PLX9080 3 Value After Reset CFG family and to ensure compatibility with future enhancement All Register unused bits should be written to 0 Address 31 23 15 7 0 PCI Base Address to local Expansion ROM Not Used User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 27 4 2 1 PCI Configuration ID Register Offset 00h Read to identify the board during configuration cycles Table 4 20 PCI Configuration ID Register Description Field Description Read Write Value After Reset Vendor ID Identifies the manufacturer of the device Defaults to Local 10B5h the PCI SIG issued vendor ID of PLX if no EEPROM is present only and pin NB no local bus initialization is asserted low Device ID Identifies the particular device Defaults to the PLX Local 906Eh part number for PCI interface chip if no EEPROM is present and only pin NB no local bus initialization is asserted low User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville
31. his board Table 4 13 Mailbox 0 Field Description Read Write Value After Reset PLD Revision Level 0x0003 31 16 EE Prom Revision Level 0x0003 4 1 5 Mailbox 1 User defined When loaded from the EE Prom this mailbox register is used to identify the overall PCI OPTO32B board assembly revision level Bits 0 7 will be used to identify the 3 different PCI OPTO32B Variations Table 4 14 Mailbox 1 Field Description Read Write Value After Reset Device ID 0x0000 0x00 PCI OPTO32B 0 01 PCI OPTO32B 12V CONTACT 0x02 PCI OPTO32B 12V CONTACT 8x28v 0x0000 31 16 Board Assembly Revision Level 0x0003 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 22 4 1 6 Range PCI to Local The PCI OPTO32B registers map into PCI I O Space using 64 bytes of I O Space PCI OPTO32B registers should not be prefetched because they act as ports Table 4 15 Range PCI to Local Register Description Field Description Read Write Value After Rosai Memory space indicator A value of 0 indicates register maps into Memory space A value of 1 indicates the register maps into I O space Location of register 00 Locate anywhere in 32 bit memory address space 01 Locate below 1 MByte memory address space 10 Locate anywhere in 64 bit memory address space 11 Reserved Wee Wee reads address space 4
32. icon revision of the PLX9060ES Table 4 23 PCI Revision ID Register Description Field Description Read Write Value After Reset Revision ID The silicon revision of the PLX9060ES Only 4 2 5 PCI Class Code Register Offset 09 Oh Used in Plug and Play PCI applications Table 4 24 PCI Class Code Register Description Reset defined Only Sub class Encoding 80h Other bridge device Local Only 23 16 Base Class Encoding other Bridge Device Only User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 31 4 2 6 PCI Base Address Register for Memory Access to Runtime Registers Offset 10h This register is used to set the base address to access the PLX internal registers using PCI Memory access cycles The defined sequence for initializing Base Addresses is as follows PCI reset software determines how much address space is required by writing a value of all ones 1 to a PCI Base Address register and then reading the value back The PLX9080 3 returns 0 s in don t care address bits effectively specifying the address space required The PCI software then maps the Local Address space into the PCI Address space by programming the PCI Base Address register For Example The Host CPU will write OXFFFFFFFF to register 0x010 The host will read back register 0x010 and get a value of OXFFFFFF80 Ad
33. ing is enabled the PLX9080 3 will pre fetch up to the number of Lwords specified in the pre fetch count for memory access to the Memory Space 0 or to the Expansion ROM Single Read Access Mode Enable Used in conjunction with Memory Space 0 and Expansion ROM Pre fetch Disable If a PCI read access is made to address space 0 and space 0 Pre fetch Disable is set to a 1 or a PCI read access is made to Expansion ROM space and Expansion ROM pre fetch Disable is set to a 1 the PLX9080 3 will perform a single read access independent of the PCI bus byte enables The single access is made as follows 32 bit local bus bytes 0 1 2 3 16 bit local bus bytes 0 1 8 bit local bus For a 16 bit local bus bytes 2 3 of the PCI Lword will contain invalid data For an 8 bit local bus bytes 1 2 3 of the PCI Lword will contain invalid data User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 25 17 16 Expansion ROM Space Local Bus Width Programmable for the Yes Cx and Jx modes only A value of 00 indicates a bus width of 8 bits a value of 01 indicates bus width of 16 bits A value of 10 or 11 indicates a bus width of 32 bits Expansion ROM Space Ready Input Enable 1 value enables 1 Bterm input A value of 0 disables the Bterm input es ing Yes Yes Yes Expansion ROM Space Burst Enable
34. ion be forwarded to PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 II PCI OPTO32B Documentation History qo DT Alterations for PMCI OPTO32A Board Assembly March 8 2001 Rev A Added Company name and Related Materials Pages Added Footers 23 2001 Rev B Updated Board Layout to include Voltage Regulator July 27 2005 Rev D Update to PCI OPTO32B Spin for PCI Board Corrected High Current Diode Clamped error October 06 2009 Rev E Corrected an error in the drawings of the Output Circuit Fig 4 and Fig 5 Pullup is 470 Ohms Error made it look like 4700 Ohms Deleted Section 1 3 Empty Section Sec 2 3 1 Changed Bias Resistors to Current Limiting Resistors added text that Minimum Input Current should be 2 3 mA Sec 2 3 1 1 Removed VCEO Not Applicable Added Min Input Current 2 3mA Added Max Input Current 80 mA Sec 2 3 1 2 Added Characteristics Isolation 7500 V Min Input Current 2 3 mA Max Input Current 60 mA Ton Toff 4 4 uSec Sec 2 3 2 1 Changed Max Output Voltage to 60V Sec 2 3 2 2 Changed Max Output Voltage to 60V Fixed and Added Footers Fixed Revision note in Footers Fixed Margins Fixed Picture
35. l base address direct Master to PCI IO CFG 0x0000 Not U PCI base address Remap for direct Master to PCI 0x0000 Not U PCI Configuration Address register for direct Master to PCI 0x0000 Not Used IO CFG A brief description of the PLX9080 3 Registers initialized 1s as follows 4 1 1 Device ID Vendor ID Device ID and Vendor ID are used to identify the PCI OPTO32B during configuration cycles Table 4 10 PCI Configuration ID Register Description Field Description Read Write Value After Reset Vendor ID Identifies the manufacturer of the device Defaults to Local 10B5h the PCI SIG issued vendor ID of PLX if no EEPROM is present only and pin NB no local bus initialization is asserted low Device ID Identifies the particular device Defaults to the PLX Local 906Eh part number for PCI interface chip if no EEPROM is present and only pin NB no local bus initialization is asserted low User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 20 4 1 3 Class Code Revision ID PCI Specification defined encoding to identify the type of device this is Used primarily for Plug and Play applications Table 4 11 PCI Revision ID Register Description Field Description Read Write Value After Reset Revision ID The silicon revision of the PLX9060ES Only defined Only 23 16 Sub class Encoding 80h Other
36. m family and to ensure compatibility with future enhancement All Runtime Base unused bits should be written to 0 Addr User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 35 4 3 1 Big Little Endian Descriptor Register PCI 0Ch The PCI bus is a Little Endian bus Data is longword aligned to the lowermost byte lane Byte O address 0 appears in AD 07 00 byte 1 appears in AD 15 8 byte 2 appears in AD 23 16 byte 3 appears in AD 31 24 The PLX9080 3 defaults to Little Endian operation for access to the PLX device and for access to the Local PCI OPTO32B registers The Local PCI OPTO32B registers are designed for Little Endian operation The PLX9080 3 can be programmed to operate in Big Endian mode thru the use of this register Bit 0 controls Big Endian access to the PLX9080 3 internal registers Bit 2 controls Big Endian access to the Local PCI DPTO32B registers In Big Endian Transfers the data is longword aligned to the uppermost byte lane Byte O address 0 appears in AD 31 24 byte 1 appears in AD 23 16 byte 2 appears in AD 15 8 byte 3 appears in AD 07 00 Bit 4 MUST ALWAYS be 0 Bits 1 and 3 are not used Table 4 31 Big Little Endian Register Description Field Description Read Write Value After Reset 0 Configuration Register Big Endian mode IM Direct Master Big Endian mode Not Used ys Direct Sla
37. ontain zero for the debounced data to transition back to a zero The clock for these holding registers is programmable thru the clock divider The Basic clock of the board is 20 MHz 50 Ns The Basic Clock Counter will always divide by 4 200 Ns Values of 0x0000 or 0x0001 will not alter this When the clock divider is loaded with a larger value then the clock division will be count 2 2 The Total debounce time will be 3 X clock division time For Example for a 15ms debounce time Clock period should be 5ms 5ms 50 100000 2 99998 99998 2 49999 0x0c34f Hex 3 2 9 Output data register Board Offset 0 01 8 bits Read Write The 8 bit output data register Reset to All Zero s Writing a 1 to a bit will make that opto output conductive and give a 0 to the other end Writing a 0 will turn the opto off and allow the output to float to 1 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 19 4 PLX9080 3 Programming 4 1 Initialization When the PLX9080 3 is reset it will initialize itself from an on board serial EEPROM that is programmed at General Standards The registers loaded at initialization are Table 4 9 EEPROM Register Initialization PCI Configuration Bits Description Value After Reset Reg PCI Register Offset Description Value After Reset Loca
38. oorbell interrupt bits causing the interrupt will clear the PCI interrupt PCI Abort interrupt enable A value of 1 will enable a master abort or master detect of a target abort to generate a PCI interrupt Used in conjunction with PCI interrupt enable Clearing the abort status bits will clear the PCI interrupt PCI local interrupt enable A value of 1 will enable a local interrupt input to generate a PCI interrupt Use in conjunction with PCI interrupt enable Clearing the local bus cause of the interrupt will clear the interrupt Retry Abort Enable A value of 1 will enable the PLX9080 3 to treat 256 Master consecutive retries to a Target as a Target Abort A value of 0 will enable the PLX9080 3 to attempt Master Retries indefinitely A value of 1 indicates that the PCI doorbell interrupt is active N A value of 1 indicates that the PCI abort interrupt is active N A value of 1 indicates that the local interrupt input 1 active N interrupt output Local doorbell interrupts enable A value of 1 will enable doorbell interrupts Used in conjunction with Local interrupt enable Clearing the Local doorbell interrupt bits causing the interrupt will clear the interrupt User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 38 19 18 Not Used A value of 1 indicates that the Local doorbell interrupt is
39. rement once for every Debounced Rising edge detected on input data bit 23 When the counter 1 OxOffff and increments the Rx event overflow status bit will be set and can be used to generate an interrupt 3 2 6 COS Interrupt enable register Board Offset 0x010 24 bits Read Write Each bit will be bitwise ANDED with the COS register and all of the results OR ed together to generate an Interrupt A 1 will enable the corresponding interrupt A 0 will disable that bit from generating an interrupt User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 18 3 2 7 COS Polarity register Board Offset 0x014 24 bits Read Write When the corresponding bit is zero the COS detection for that bit will be set by a detected High to Low transition When Set to a 1 the COS detection for that bit will look for Low to High transitions Reset to all zeros 3 2 8 Clock Division Register Board Offset 0x018 24 bits Read Write NOTE gt gt gt gt when altering this register disable all interrupts and expect unusual results in the COS Detection register 24 Bit clock divider is provided for programmable Debounce delays The debounce circuit registers the incoming data 3 times in a daisy chain When ALL 3 registers are high the incoming data is a high When the debounced data register contains a 1 then ALL three registers must c
40. rrent the information contained in this document General Standards Corp does not assume any liability arising out of the application or use of any product or circuit described herein nor is any license conveyed under any patent rights or any rights of others General Standards Corp assumes no responsibility for any consequences resulting from omissions or errors in this manual or from the use of information contained herein General Standards Corp reserves the right to make any changes without notice to this product to improve reliability performance function or design All rights reserved No part of this document may be copied or reproduced in any form or by any means without prior written consent of General Standards Corp This user s manual provides information on the specifications theory of operation register level programming installation of the board and information required for customized hardware software development User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 RELATED PUBLICATIONS The following manuals and specifications provide the necessary information for in depth understanding of the specialized parts used on this board EIA Standard for the RS 422A Interface EIA order number EIA RS 422A PCI Local Bus Specification Revision 2 1 June 1 1995 Questions regarding the PCI specificat
41. s enne enne 36 43 2 Mailbox Register 0AXPCTAOR e tec e etre dng ee este ade 37 4 33 Mailbox Register 1 PCTAAh 37 4 3 4 Mailbox Register 2 PCI 48 erinnere nnne enn 37 435 Mailbox Register 3 PCI ACH ote eno e te ee ve ose te 37 4 3 6 Interrupt Control Status PCI 68h 38 4 3 7 EEPROM Control PCI Command Codes User I O Control 40 4 3 8 PCI Configuration ID Register PCI 70h eese nennen nennen 41 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Figures Fieure 1 Board eR T 11 Figure 2 Input Channels 0 22 senos sesso 14 Figures Input Channel 14 Figure 4 Normal Outputs Bits 15 Figure 5 Diode Clamped Outputs Bits 4 7 e eee sees eee ee esee en setenta assesses een 16 User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 Table Of Tables Table 1 1 Bids resistor Was 7 Is REFERS RR 9 Table 1 2 Other Resistor Was Is Changes cerae eee eee ee eene eene nettes 9 Table
42. s the write to the PLX interface that will enable it to generate Interrupts onto the PCI bus Outportl PLX 1o base address 0x068 0x00900 Long word write PLX interrupt control register Bit s 8 and 11 Enable Local input to generate PCI interrupts User Manual for the PCI OPTO32B Card Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 42 In the Interrupt there is NO action required to with the PLX Interface chip The only requirement to remove the Asserted interrupt 1 to remove the Local source of the interrupt Which would be the COS bit or the event overflow temp inportb Opto register base address 0x00 Read the OPTO Board Status register if temp amp 0x010 1 1 Master Interrupt bit will be set in the Board Status Register if this board generated the Interrupt Status Bits 0 thru 3 could also be examined to Determine Which Byte generated the Interrupt Or if the Event Counter Overflow generated The Interrupt Finished processing Now It s time to clear the Pending Interrupt Outportl Opto register base address 0x08 0x08421 Long word write Offset 0x08 COS register Clear COS Bit s 0 5 10 and 15 If they are set Outportb Opto register base address 0x00 Oxc8 Byte write Turn LED off Enable Event Overflow Interrupt Clear Event Overflow To Disable
43. tsville AL 35802 Phone 256 880 8787 17 3 2 2 Board Control Register Board Offset 0x00 8 Bits write only Table 3 8 Board Control Register NOTE Bits 0 4 are self clearing pulses that are written as a 1 to clear the interrupt source The bits will then self clear so that another host operation is not required NOTE The Clear Interrupt Bytes or the Master Clear bit 4 will clear ANY COS register bit that is set regardless of the bits Interrupt Enable Status For Individual COS bit clearing Write a 1 to the COS bit you wish to clear Event Overflow status will only be cleared by Clear Event Overflow or by Master Clear Bit 4 Loading the Event Counter WILL NOT clear out the event overflow status 3 2 3 Received data register Board Offset 0x04 24 bits Debounced receive data bits 0 23 Read ONLY 3 2 4 Change of state register Board Offset 0x08 24 bits Change of state detection Polarity programmed thru COS Polarity register 0x014 Read COS data bits 0 23 Read ONLY If a COS bit is set then it will stay set until cleared by the host A COS bit is cleared by writing a 1 to a COS bit that is set Writing a zero will have no effect COS bits may also be cleared by using the board control register Byte clears or using the board control master clear 3 2 5 Receive Event Counter Board Offset 0x0c 16 bits Read Write Written by the host This counter may be read at any time by the host Counter will inc
44. ve Address Space 0 Big Endian mode A 1 value specifies that Big Endian data ordering is used for Direct Slave accesses to local Address Space 0 A value of 0 specifies Little Endian ordering ee Used 4 Big Endian byte lane mode Must be 0 E UE _ 0 0000 User Manual for the PCI OPTO32B Revision A Manual Revision E General Standards Corporation 8302A Whitesburg Drive Huntsville AL 35802 Phone 256 880 8787 36 4 3 2 Mailbox Register 0 PCI 40h When loaded from the EE Prom this mailbox is used to contain values to identify the PLD revision and EE Prom Revision levels of this board This is provided as information for the host processor Table 4 32 Mailbox Register 0 Description Field Description Read Write Value After Reset PLD Revision Level 0x0003 31 16 EE Prom Revision Level 0x0003 4 3 3 Mailbox Register 1 PCI 44h When loaded from the EE Prom this mailbox register is used to identify the overall PCI OPTO32B board assembly revision level Bits 0 7 will be used to identify the 3 different PCI OPTO32B Variations Table 4 33 Mailbox Register 1 Description Field Description Read Write Value After Reset Device ID 0x0000 0x00 PCI OPTO32B 0 01 PCI OPTO32B 12V CONTACT 0x02 PCI OPTO32B 12V CONTACT 8x28v 15 8 Reserved 0x0000 31 16 Board Assembly Revision Level 0x0003 4 3 4 Mailbox Register 2 PCI 48h Not Used Table 4 34 Mailbox Register 2 Description
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