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12.2.5 Class or Vendor read command with 1 byte data

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1. 5 8 5 MDI6 RD6 1 60 XTO MDI7 RD7 XTIB vss CLK1 CUVDD DATA 5 CVDD IVDD 55 RES6K2 vss VSSA GPP1 VDDA33 CVDD CE6231 VSSD vss 10 VDDL18 CVDD 50 VDDD33 vss LQFP 80 VSSA CVDD USBM vss USBP CUVDD 15 RES1K5 GPP2 45 VDDA33 GPP3 DVDD GPP4 DGND GPP5 RFLEV GPP6 20 41 AVDD33 R lt 2 2 27 9958 5555756 lt D73701 003 CE6231 User Manual 5 Pin list Table 5 1 Package Pin List FUNCTION __ FUNCTION FUNCTION PIN FUNCTION MDZIRD 22 vss 42 _ 62 SRD 64 26 46 RESK5 66 TEST 8 28 48 06 68 MVAUSD 9 CVDD 29 49 69 RESETB GPP2 AVDD AGND 20 40 60 80 20 CE6231 User Manual D73701 003 Application schemati Figure 5 Typical application schematic auan ana EST I jugar _ jung me 122 li 1 Jugal aii Jupp SiS Jung gie Jugni sie jupo S jung sie uggi avuga nui I li 1 Esa 152 1 Bt2 i 22 I 55 T gia 1 27
2. XL jul y 1 1501 OUAS Jd 2 1 _ 305 asn 0 LdNYYALNI dnjes Oda euop 0 YO 5 044 14 guess AN T MO 1 ldg 9 YSD JSN _ _ 19591 sng gs b JSN asn dd9 _ 29 OHIO LNI GNP LNI Joejep INI L 3IX3 9 JIX3 NO2L L NOOL 3la c 3l3 b oam 0 3 609 puedsns Ldd9 3 1X3 aid euw z asn dsns GLINI u SLNI u LLNI u OLNI 0X3 47 6231 User Manual Ref D73701 003 9 11 4 Interrupt Sampling The internal timers and serial ports generate interrupts by setting their respective SFR int
3. Access TIMER_RD_1 T PUMA Counter timer instantaneous value TIMER RD 0 272bEh Reseved VIT ERR CNT 2 VIT ERR 1 Viterbi error counter 24 bit VIT ERR 0 8249 4Ah HAN FREQ 1 Channel frequency after search 15 bits 4Bh CHAN FREQ 0 4Bh 1 Clock control dci 31h RW target setting 6h RW 589h Reseved 1010004 5Ah OP CTRLO Oufptconrolbis __ 48h RW 58Bh Reseved 5Ch MCLKCTL ClockratioforMPEG TSouput 7Dh RW S8Dh Reseved RS ERRPER 0 blocks R W 6263h Reseved y y o o 1 68h R W OFDM channel bandwidth normalised to sampling rate TRL 078 R W NominalRate 0 67 6Bh o 6Ch FREQ 1 Lm Input signal frequency normalised to sampling rate INPUT FREQ 0 RW Specified TPS parameters of the OFDM signal E ME M 80h RW __7 Reevwed 0o RW Control the interrupt bits connected to INT3 N R W RIW 75h Reseved D73701 003 CE6231 User Manual 97 Address Description Detault Access Control the status bits connected to the STATUS pin 78h Programmable timer period 7 TIMER PERO 0h RW TBh CUE 7 E RR NNNM 7D7Eh Reserved Fh CHIP ID Chipidenific
4. desti sud latc danse 108 11 2 11 109 meee DE 109 1 2 1 MAX 110 TEZAA a 110 1452 19 d 111 111 TE AGC COPING O eS Sects ELE 112 11219 aden 113 11 3 Baseband 114 11 9 1 INPUT FREQ 509 Teron eno 114 1453 27 MEV 115 11 4 Interpolation and Clock Synchronisation 116 11 21 TRL Nominal Rate deor ae curta 116 11 5 Carrier Frequency Synchronisation 117 RANGE n anced alec 117 WAZ MEE A 118 TES39 2 512 0 A a S 119 11 6 Transmission Parameter Signalling 2 4 120 SCODE Ol TE S 120 11 6 2 TPStransmisslioh beans esed aao edge aerea 121 11 7 TIS eR RID ATP 122 Wray PPS T
5. TR 44 Cua 45 9211 2 Interrupr MaskIDG bete Sena He deoa xe Madea 45 93ET149 ImMerupt POLIS uses t ta nos eode ceo repeti mctu e Lp oat 46 erupt Sampi ce 48 MALCTRUPT ve Add Ro bL RU Tu DEA bota iU edad Udo te ud 48 9 11 6 Extended Interrupt 5 49 9 11 7 Extended Interrupt 50 9 11 8 EIP Extended Interrupt PEIOFE 51 SEEKS ME gt ER OE ee Re 52 ad 53 9 11 11 had 54 LIEIS INTEN 55 SEINE MEMMIUS 56 SEC NT ENTA D 57 PE 58 IRIG INT ENIB 59 Cc Soe 60 9 11 18 1 05 interrupt a 61 9 12 USB Control and Status
6. 162 Table 11 14 Available clock 167 Table 11 15 Register settings for clock 167 Table 13 1 Recommended operating 201 Table 13 2 Absolute maximum 201 Table 13 3 DC electrical characterisliCS ocio iuo Ue boue odio cop 202 Table 13 4 Digital Dus MING 2 oto nn oe dan GE tr Sa n ico et aano aun sedan 203 10 CE6231 User Manual D73701 003 Abbreviations and symbols ACRONYM ACI ACQ ADC AGC BA BCH BDI BER CAS CCI CHC COFDM CP CPE CRL CSI CSR DMP DVB ETSI FEC FFT FSM 25 ISR ITB ITP PID PPM REC656 SCR SDI SFR SOF SP SYR TPS TRL TS TWB UPIF USB Ref D73701 003 Description Adjacent Channel Interferer Acquisition Analog to Digital Converter Automatic Gain Control Byte Align er Bose Chaudhuri amp Hocquenghem coding scheme applied to TPS data Bit Deinterleave Bit Error Ratio Co and Adjacent channel interference suppression Co Channel Interferer Channel Corrector Coded Orthogonal Frequency Division Multiplexing Continuous Pilot Common Phase Error Carrier recovery loop Channel State Information Control and Status Registers Symbol Demapper Digital Video Broadcasting European Telecommunications Standa
7. 13 codi sie ante 20 Table 9 1 Register bank 29 ee ee ae 38 Table 9 3 CE6231 internal event interrupts 44 Table 9 4 Interrupt Natural Vectors and 45 Table 9 5 Summary of interrupt sources flags enables and priority control 45 Table 11 1 AGC voltage limit nnne nnns 101 Table 11 2 AGC 102 Tane TS RE 6 114 Table 11 4 Elliptic filter options 115 Tabe RN ER 117 Table 11 6 TPS signaling nnns 121 Table 11 7 TPS_RECEIEVED data format not including ETSI 300 744 Annex F DVB H modes 121 Table 11 8 TPS GIVEN data format not including ETSI 300 744 Annex DVB H 5 125 Table 11 9 TPS GIVEN data format not including ETSI 300 744 Annex DVB H modes 126 Table 11 10 Mapping of the cell id on the TPS 128 een ERE 137 Table 11 12 Table of SNR 141 Table 11 13 Elliptic filter
8. USBC_SET_INTERFACE Bit 5 is set after Set Interface command and reset after the 8051 sets APP DONE CSRS 5 is set Bit 5 is set after Set Interface command and reset after the 8051 sets APP DONE CSRS a Set Interface command and reset after the 8051 sets APP DONE CSRS USBC SET CONFIG Bit 4 is set after a Set Configuration command and reset after the 8051 sets APP DONE CSRS This contains the USB configuration selected by the last Set Configuration command See USBC CFG also USBC SET CSRs This contains the USB configuration selected by the last Set Configuration command See also USBC SET CSRs Ref D73701 003 CE6231 User Manual 63 9 12 3 USB STATUS1 Register USB STATUS1 Access Read only Address 9Fh x o x USBC_ALTINTF 5 4 Bits 3 0 contain the USB interface selected and bits 7 4 the alternate setting for that interface These are set by the Set Interface command See also USBC SET CSRs in USB_STATUS2 2 USBC INTF 0 This contains the USB interface selected by the last Set Interface command 64 CE6231 User Manual D73701 003 9 124 USB_STATUS2 USB_STATUS2 Read only AOh 1 1 USBC Bit 6 set while bus speed enumeration takes place during a bus reset When this bit goes low bits 4 3 are valid
9. rat ERE K SS Setting each bit in INT to 1 enables corresponding bit in INT4B to generate an interrupt on 8051 interrupt 4 Ref D73701 003 CE6231 User Manual 59 9 11 17 INT CTRL Read Write __ o 1 1 ___ EXT EXT_INT_EDGESEN When bit 3 is set to 1 interrupt 5 is edge sensitive when 0 interrupt 5 is level sensitive When bit 2 is 0 8051 interrupt 5 is connected to GPP 7 when 1 interrupt 5 is connected to the EXT_INT_INV inverse of GPP 7 INT INT 353 EDGESEN EDGESEN When bit 1 is set to 1 interrupt 3 is edge sensitive when 0 interrupt 3 is level sensitive When bit O is set to 1 the internal demodulator interrupt output is connected to 8051 interrupt 3 INT 353 EN See Note Interrupt control e Note The required demodulator interrupts and the 8051 internal interrupt 3 enable register must be selected as well 60 CE6231 User Manual D73701 003 USB 9 11 18 EICON USB suspend interrupt Read Write D8h uim ___ SS T This register is the USB suspend interrupt Caution If SFR DF bit 2 1s 0 the CE6231 could be suspended before the suspend interrupt service routine 1 called If SFR DF bit 2 15 1 the CE6231 15 not automatically suspended
10. AN AD negative input ADC power pins 36 AVDD ADCanalogsupply ds ADC analog supply ADC digital supply ADC digital ground USB power pins USB PHY Logic supply 4553 VDDA3 USBPHYAmlogsupy _ ls 3 us 49 54 USBPHYAnaoggroud S _ ______65 66 TEST I ground Jo ______30 31 TEST Testpins 12 ComectoVDD33 33 3 1 1 Pull Up Pull Down Resistors Pin 5 5 must be connected to a 1 5 kohm 5 resistor tied to 3 3V This 15 used for the USB bus pull up Pin RES6K2 must be connected to a 6 2 kohm 1 0 resistor tied to ground This is used to bias the USB band gap reference A 0 1 uF capacitor should be connected in parallel with this 3 1 2 Hardware Reset At system power up the hardware reset pin RESETB must be held low for at least 40 ms and no more than 90 ms 18 CE6231 User Manual D73701 003 4 Pin diagram Figure 4 80 Pin QFP Package Diagram
11. STU 22 8 Special Function Registers 2 4 11112 24 ok a a iak 24 9 2 tu 28 Re d mmm 28 92 PSW Program Status 29 2 224 niue 30 Sic __________ 31 9 nes 32 g6 33 CKROON CIOCK 34 9 0 SPC FNG 9peclal TUR CUOM _ _____ __ 35 9 cro rl ENNIO ROI 36 9 9 1 DPS Data Pointer Sele6l a qus c aai 36 9 9 2 BO gt o RR MM 37 222 ru ONG EET Tm 37 9 10 Timers 38 38 9 10 2 TCON Timer Counter 39 TIME E 40 SRI ETT 40 9 10 5 T2CON 2 COMMON torneo n dran iot men inen macte adm mud nado susti 41 9 10 6 RCAP2 Timer 2 Reload Capture 42 Ref D73701 003 CE6231 User Manual 3 ONO COUM Gua 43 9 11
12. OFDM BW where OFDM BW is the signal bandwidth in MHz 1 6 7 or 8 MHz and fADC is ADC clock frequency in MHz If SR 1 bit 2 in CLOCK 0 then subtract 200 from this because if SR 1 the CRL adds 200 to this This approach has been taken to keep this parameter within the 8 bit number range if SR 0 then CRL AFC CTL S OFDM BW else CRL 509 OFDM BW end Ref D73701 003 CE6231 User Manual 163 11 18 2 6MHZ BW 1 Read Write DCh at se ttt sts ts 7 6 ___ ____ Reserved 1 5 0 6MHZ BW 1 Set this to 06 for 6 MHz bandwidth 11 18 3 6MHZ BW 2 Read Write o o o 1 j 1 Symbo 5 Reserved 4 0 6MHZ BW 2 Set this to 07 for 6 MHz bandwidth 164 CE6231 User Manual D73701 003 11 19 Registers that are not software reset The registers in all the above sections are reset to their default values by demodulator RESET register 55h full software reset In addition to these registers there are five special registers that are not reset by demodulator full software reset These are reset to default values only by a hardware reset or SFR DF bit 4 and are used to Power up down the 6231 Set up the CE6231 clocks All these registers are in the crystal clock domain and hence do not re
13. 125 TRS CURRENT sed 126 Tew TPSZREGEIVED Q 15 127 11 8 ES 128 EST RPS IDOT crm 128 14 92 TPS MISC 129 11 9 130 TL91 Programmable Timer utc Ra e rele Rt e 130 11 92 Programmable Timer 131 132 11 10 1 EC M E 132 ACO TE aate ta oe iode tof 133 1121029 CMR ND acm Lu ba phe duet ea sea phu tius 134 TAGA 135 EXPECTED eaten 136 TEIG MCEK TES as deena 137 ue SR eee 138 CE6231 User Manual Ref D73701 003 a a a 139 TAT 140 ONR er C X CEN 140 TEIZ Enor Rate Montong c 142 11 12 1 minio RER O Prenna a TERES 143 1 12 2 ORS E
14. 2 p E JH ICA zal PER E zm en 1001 mM 7 JHTNASTATA 29v20 p aue 23 A 5745524 qasnNn 29 A I5 7YNW Vivd gt lt a 45 T 662 mA HOC SM LHLSIN zp AAS 43375 dcum MIL 7 Lasa ves on s po a 8 940394 SEJ ma uueggs 9194 1 lt lt 8d 0 9 lt 5 4 9 wei nsa us m gi 5 gt ener 8595 15 2 dB 2 uus ES NIA mz T 4 X A gt 394 a989 eza 6 wp e sp el 2e mus 2 5449 m m p J A 2 oUt a UU 855 a 5585 S S S NIA p HUBS Hugg gt Ss 13 gt gt 1 51 581 gt gt gt gt lt 22
15. 62 IDWS TA EUS bii nube mE ecco 62 9 122 USB STATUSO 63 IAS YB STATO een 64 JIZZA sob STATUS Z MUI 65 STATUS 0 66 2120 SUSP CTR ace oam 67 2 DISCON CTR iano 68 9128 9051 End pointeomtarid kee ee 69 9129 ERO End COMMU Oli ese ee ieee e Cen ut 70 STO E ILE 71 9 12 11 HOMI Pr 72 9 12 12 COR 72 91213 CSR ADDR 73 c tra eee 73 9 13 NEUTER 74 9 13 1 PF Data stream PID filter 74 He NLIS RD tat cp per EO aes oe 75 PID 2 4 E S DU MIL 76 SERRE mc ER 77 18 92 mE 78 9 13 6 PF HEADER LEN PF header length 79 SS 80 9 14 GS n 81 CE6231 User Manual Ref D73701 003 9
16. NM CE6231 The two outputs pin 24 and AGC2 pin 25 each produce a pulse density modulated bit stream through open drain output ports The bit stream which varies in density from 0 to 100 is then low pass filtered to produce the gain control voltages The frequency of the bit stream 1s variable and dependent on the ADC clock Although typical values for the ADC clock vary with the system clock the time constant TAGC of the low pass filters can be set to about 500us which will be appropriate for most applications In the default mode the RF AGC is turned off and the CE6231controls only the IF AGC To use the RF AGC in conjunction with the IF AGC the OP CTRL 0 register 0x5A bit AGC2 B6 has to be cleared from its default 1 to 0 Prior to use the two bits that set the AGC output sense positive or negative also need to be set as appropriate to the hardware configuration For the IF AGC section this bit is B7 in the Target register 0x56 and for the RF AGC bit B5 in the AGC 5 register Ox8E The internal total gain control range is 0 to 24 1 and this range can be arbitrarily split between the two AGC sections IF and RF or can be used for just one section normally IF only The following sections describe how the various registers be used to set up the 623 for use with a specific tuner These registers would normally only be changed from their defaults after a hard or soft reset and do not
17. Program CE6231_EN and clock control registers 51 to 54 Wait 200us Software reset All registers except 50 to 54 will take default value Recalibrate ADC Change AGC defaults if necessary Program hardware specific registers and IF frequency If this is a channel search then program OFDM parameters for search mode channel acquisition flow diagram CE6231 User Manual 187 12 38 Acquire channel sequence This has to be done for every channel change or for every channel in a scan 1 Program tuner using master 2 wire bus controller 2 While the tuner and the AGC are locking program channel specific OFDM parameters e Change registers that control OFDM bandwidth default to 8 MHz e Change TPS parameters These may be acquired from the signal but such a search takes longer hence it is always best to program TPS parameters if known If these are incorrect then the CE6231 will search and find the correct ones e Change the IF frequency for single or triple offsets 3 During 2 above the tuner and AGC are very likely to lock However wait for tuner lock and start an acquisition by writing 1 to FSM GO This will reset AGC lock flag but since the signal levels have settled a new lock flag will usually be generated straight away 4 The CE6231 will usually lock even with a relatively large fre
18. 1 to generate an extended interrupt in turn setting flag bit 5 in EXIF register provided that bit 0 of the SFR INT CTRL has been set Ref D73701 003 CE6231 User Manual 159 11 16 3 EN 2 INTERRUPT EN 2 74h adi ICE se tse ts ts Symbo Enable bits 7 0 of INTERRUPT 2 to generate an extended interrupt in turn setting flag bit 5 in EXIF register provided that bit 0 of the SFR INT CTRL has been set 160 CE6231 User Manual Ref D73701 003 11 16 4 4 INTERRUPT_EN 4 76h adi at se ICE sts ts ts ep eena _ _ Enable bits 7 0 of INTERRUPT EN 4 to generate an extended interrupt in turn setting flag bit 5 in EXIF register provided that bit 0 of the SFR INT CTRL has been set Ref D73701 003 CE6231 User Manual 161 11 17 Elliptic filter The default filter parameters for the elliptic filter depend on OFDM bandwidth 6 7 or 8 MHz defined by OFDM BW 1 0 sampling rate Low or High defined using SR This will usually be 19 5 or 20 40 MHz for the low sample rate mode and 17 25 or 22 5 MHz for the high sample rate mode Note that although the high sample rate mode will be sampling at 34 5 and 45 MHz for 36 17 and 43 5 MH
19. we m RwN FS ee A e 174 SETUP packet received USB controller returns ACK USB controller writes 8 bytes to EPO SETUP ADDR USB controller sets EPO SETUP status and interrupt PING returns NAK 0 to n occurrences DATA write returns NAK 0 to n occurrences 8051 sets EPO LENGTH to 10 8051 sets EPO 8051 DATAEND DATA write returns ACK USB controller writes 10 bytes to EPO ADDR USB controller sets EPO DONE status and interrupt STATUS stage read returns NAK 0 to n occurrences 8051 sets 8051 STATUS STATUS stage read returns zero length packet SETUP packet received USB controller returns ACK USB controller writes 8 bytes to EPO SETUP ADDR USB controller sets EPO SETUP status and interrupt PING returns NAK 0 to n occurrences DATA write returns NAK 0 to n occurrences 8051 sets 8051 STALL DATA write returns STALL STATUS stage read returns STALL CE6231 User Manual Class or Vendor write command with 10 bytes data Ref D73701 003 12 2 3 9e de 2 NO m S A ipeo dq Ref D73701 003 SETUP packet received USB controller returns ACK USB controller writes 8 bytes to EPO SETUP ADDR USB controller sets EPO SETUP status and interrupt PING returns NAK 0 to n occurrences DATA write returns NAK 0 to n occurrences 8051 sets EPO LENGTH to 64 8051 sets EPO 8051 DATAMID DAT
20. Register PID INT PID INT BASE ADDR 15 10 PID INT MAX Defines the internal MPEG data PID look up table size 90 PID INT BASE ADDR Defines the base address in 32 bit words of the internal MPEG data PID look up table This register pair defines the base address in 32 bit words of the internal MPEG data PID look up table and the internal MPEG data PID look up table size HF Note PID INT MAX This should be set to the number of PIDs minus 1 D73701 003 CE6231 User Manual 75 9 13 3 EXT Read Write Symbol PID EXT MAX PID EXT BASE ADDR order Register 0 EXT MAX EXT BASE ADDR 15 10 PID EXT MAX Defines the external MPEG data PID look up table size 90 PID EXT BASE ADDR Defines the base address in 32 bit words of the external MPEG data PID look up table This register pair defines the base address in 32 bit words of the external MPEG data PID look up table and the external MPEG data PID look up table size HF Note PID EXT MAX This should be set to the number of PIDs minus 1 76 CE6231 User Manual Ref D73701 003 9 13 4 PID SETUP LOCO PEEXLMAXIEN PEINLMAXAEN __ PF 125 MAX LENGTH defines the maximum length in 32 bit words that may be sent in one 1 24 em as oa external audio transfer For bulk mode this must be set to 128 high speed or 16 full speed PF EXT MAX L
21. Symbo This register contains Timer Zero current count and is available in two bytes TOL Low byte and High byte 9 10 4 Timer Access Read Write Symbol Default Jo 7 0 Address Symbol This register contains the Timer One current count and is available in two bytes TIL Low byte and High byte 40 CE6231 User Manual D73701 003 9 10 5 2 Timer 2 control Read Write at se te tt st ets ts symbol 00000 This register controls timer 2 Ref D73701 003 CE6231 User Manual 41 9 10 6 2 Timer 2 Reload Capture value Read Write Symbol RCAP2H RCAP2L Address Defaut eT eo 7 Bi Symbol RCAP2 Timer 2 Reload Capture RCAP2L SFR CAh Used to capture TL2 value when Timer 2 15 configured for capture mode or as the LSB of the 16 bit reload value when Timer 2 is configured for auto reload mode RCAP2H SFR CBh Used to capture the TH2 value when Timer 2 1 configured for capture mode or as the MSB of the 16 bit reload value when Timer 2 15 configured for auto reload mode 42 CE6231 User Manual D73701 003 9 10 7 T2 Timer two count Read Write Symbol T2H CDh Defaut pe 6 9 ee 7 15 8 _ Symbol
22. status and interrupt CE6231 User Manual D73701 003 12 2 5 Class Vendor read command with 1 byte data xc X cd WwW N e x9 SETUP packet received USB controller returns ACK USB controller writes 8 bytes to EPO SETUP ADDR USB controller sets EPO SETUP status and interrupt DATA read returns NAK 0 to n occurrences 8051 writes 1 byte to EPO ADDR 8051 sets EPO LENGTH to 1 8051 sets EPO 8051 DATAEND DATA read returns byte and ACK USB controller sets DONE status STATUS packet received USB controller returns ACK handshake USB controller sets STATUS status and interrupt SETUP packet received USB controller returns ACK USB controller writes 8 bytes to SETUP ADDR USB controller sets EPO SETUP status and interrupt DATA read returns NAK 0 to n occurrences 8051 sets 8051 STALL DATA read returns STALL STATUS stage write returns STALL Ref D73701 003 CE6231 User Manual 177 12 2 6 Software endpoint 1 processing Endpoint 1 is an Interrupt IN endpoint The format of the data is completely user defined When the 8051 has data to send to the PC the 8051 writes the data to the address pointed to by ADDR and writes the length to LENGTH Then 8051 DATA should be set to 1 After the data has been read the PC the STATUS status and interrupt bits will be set If
23. at se te tt Symbo Bit 7 global interrupt enable All interrupts except the Suspend Interrupt are disabled when bit 7 is 0 When 1 the individual interrupt enable bits control ISR calling 7 5 2 When bit 1 1 this enables the Timer 2 interrupt The ISR is called when TF2 is set When bit 5 1 0 the ISR is disabled 3 ET1 When bit 3 is 1 this enables the Timer 1 interrupt The ISR is called when the TF1 flag is set When bit 3 is 0 the ISR is disabled 2 EX1 When bit 2 is 1 this enables the INT1_N interrupt The ISR is called when the IE1 flag is set When bit 2 is 0 the ISR is disabled 1 ETO When bit 1 is 1 this enables the Timer O interrupt The ISR is called when the TFO flag is set When bit 1 is 0 the ISR is disabled EXO When bit O is 1 this enables the INTO N interrupt The interrupt service routine is called on the falling edge of IRDI When 0 the ISR is disabled This register enables or disables the interrupts in the 8051 core 52 CE6231 User Manual D73701 003 9 11 10 IP Interrupt Priority Register Read Write t st ett sists ts sm s lem When bit 5 is 1 Timer 2 interrupt is high priority when O Timer 2 interrupt is low priority oo When bit 3 is 1 Timer 1 interrupt is high priority when 0 Timer 1 interrupt is low priority When bit 2 is 1 INT1_N is a high priority
24. cd 3297 5 4 mares Ela 3922 J300 g T aei 212 3 a 5 F 3 3 au 7 820A 8 545 a STON ERE 5 i I 888 AS U EAE an T 4 4 I dig qus dis GIES azz m IE NEC 4 4 H 5 HL 297 IEJ 97 3u02 JBUE wis 2001 D mM 0001 etie D 999 E st asn aaa 2 5 ag 5 auo AN W yogi 21 CE6231 User Manual Ref D73701 003 7 8051 Microprocessor The CE6231 is controlled by an internal 8051 compatible microprocessor This is connected to 3 internal memories The Internal RAM is 256 bytes The Program RAM is 12 Kbytes The Data RAM or
25. External RAM is 4Kbytes There is no ROM inside CE6231 The Program RAM can be written to by the 8051 and by the 2 wire bus controller The Data RAM can be written to and read from by the USB controller The Data RAM can be read by PID Filter The 8051 is clocked at 30 MHz and the basic instruction cycle is four 30 MHz cycles There are 3 timers in the 8051 There are no serial ports There are 7 interrupts used in the CE6231 mme OO INTO Infra red falling edge detection INT1 N USB interrupts INT2 Infra red rising edge detection Suspend interrupt 7 1 Internal data memory Internal Data Memory is mapped in Figure 6 The memory space is shown divided into three blocks which are generally referred to as the Lower 128 the Upper 128 and SFR space Internal Data Memory addresses are always one byte wide which implies an address space of only 256 bytes However the addressing modes for internal RAM can fact accommodate 384 bytes using a simple trick Direct addresses higher than 7FH are one memory space and indirect addresses higher than 7FH access a different memory space Thus Figure 6 shows the Upper 128 and SFR Special function register space occupying the same block of addresses 80H through FFH although they are physically separate entities The lower 128 bytes of RAM are as mapped in Figure 6 The lowest 32 bytes are grouped into 4 banks of 8 registers RO R7 Two bits in the P
26. IF gt RF in AGC gt Tuner 2 wire et pe bus USB CE6231 ITU IF 656 RF in AGC Analog 2 gt Tuner o Demod 2 wire 1 lt 2 wire bus n detector XTAL Y EEPROM D73701 003 CE6231 User Manual 15 Figure 3 Block diagram AGC1 AGC2 lt IF input RF level input 2 TS ITU656 125 CLK1 DATA1 gt CLK2 DATA2 GPP 7 0 16 OFDM CE6231 User Manual 10 bit System clocks 7 bit Demod Demod PLL ADC UPIF PID filter USB USB PAY USB 1 controller PLL PID filter E 2 Buffer i 30MHz clock intreface gt Crystal Demod Data RAM PLL ADC power down Y lg Suspend control gt _ SLEEP 2 wire bus 8051 controller IRDI RAM Ref D73701 003 3 Pin definitions Pin f Name Pindescription 10 V mA DUI 76 77 80 data input Tristate cw Tristate ee I2S data input Tristate Lo E 125 word select input Tristate 68 S clock CMOS Bs Il mL Fall time
27. PC reads endpoint 1 when 8051 DATA is not set a NAK handshake is returned to the PC A pending interrupt transfer can be cancelled by clearing 8051 DATA prior to the PC requesting interrupt data 12 2 7 control and status registers CSRs The 8051 software must set these registers to define the endpoints after each SET CONFIGURATION and SET INTERFACE command The interrupt USBC SET CSRS will be set after either of these commands The software must read the new configuration and interface values and set these registers appropriately There are 6 32 bit CSRs these are shown in table below Ree int eote 999000 Endpoint 2 config 0000 0000 Endpoint 3 config 0000 0000 Endpoint 4 config 0000 0000 Caution SCA should not be changed from the default of 4000 hex The format of the data for the endpoint configuration CSRs 15 given below Bits Purpose 3 0 Endpoint number 4 Endpoint direction 0 OUT 1 IN 6 5 Endpoint type 00 Control 01 Isochronous 10 Bulk 11 Interrupt 10 7 Configuration number for this endpoint 14 11 Interface number for this endpoint 18 15 Alternate setting number for this endpoint 29 19 Maximum packet size 31 30 Isochronous mode control 178 CE6231 User Manual Ref D73701 003 The maximum packet size of endpoint 0 must set to 64 and direction set to OUT Bits 31 30 should be set to 00 for non isochronous endpoints and 01 for isochronous en
28. correspond to one OFDM super frame The reference sequence corresponding to the TPS carriers of the first symbol of each OFDM frame are used to initialize the TPS modulation on each TPS carrier see clause 4 6 3 Each OFDM symbol conveys one TPS bit Each TPS block corresponding to one OFDM frame contains 68 bits defined as follows e initialization bit e l6synchronization bits 37 information bits 14 redundancy bits for error protection Of the 37 information bits 31 are used The remaining 6 bits shall be set to zero 120 CE6231 User Manual Ref D73701 003 11 6 2 TPS transmission format The transmission parameter information shall be transmitted as shown in Table 11 6 The mapping of each of the transmission parameters constellation characteristics value code rate s super frame indicator and guard interval onto the bit combinations 1 performed according to clauses 4 6 2 1 to 4 6 2 8 The left most bit is sent first Table 11 6 TPS signaling information The TPS information transmitted in super frame m bits s25 39 always apply to super frame m 1 whereas all other bits refer to super frame m Table 11 7 TPS RECEIEVED data format not including ETSI 300 744 Annex F DVB H modes Channel TPS signalling bit number 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Received TPS signalling bit number TPS RECEIVED 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Val Constellation Hierarchy HP code ra
29. internal PIDs 0x1234 and 0x1235 external PIDs 0x76D and 0 89 generating packet aligned isochronous data with 2 byte headers CSRs 000C 600080B2 0010 60008083 This sets both endpoints 2 and 3 as isochronous IN with maximum packet size of 1024 bytes transfer per microframe in configuration 1 interface 0 alternate setting 1 Note that the actual maximum transfer size will be 5 188 2 942 bytes but setting 1024 bytes here does no harm Data RAM 0048 34 0049 12 004A 35 004B 12 0300 6D 0301 07 0302 9 0303 08 SFR settings 00 EP USE BULK 0 4 04 PID INT 2 1 B6 04 PID EXT MAX 2 1 B7 00 B9 04 PF INT MAX LENGTH 1024 bytes BA 20 PF EXT MAX LENGTH 1024 bytes BC 02 Header byte 0 BD 80 Header byte 1 C2 22 PF HEADER LEN 2 DE 40 1 BUFFER 0 2 03 INT353 1 PF EXT353 1 PF INT FILT DIS 0 PF EXT DIS 0 198 CE6231 User Manual Ref D73701 003 Example 4 CE6231 with external analog demodulator using bulk transfers PIDs 0xC56 0 40 OXFFE packet aligned data CSRs 000 0010 0014 Data 0048 56 0049 OC 004 40 004 004 FE 0040 OF SFR settings 20 4 08 7 00 9 04 10 30 2 20 50 2 20 600080B2 Isochronous IN maximum packet size 1024 bytes 100080D3 Bulk IN maximum packet size 512 bytes 460080B4 Isochronous IN maximum packet size 192 bytes EP USE BULK 2 PID INT MAX 23 1 PF
30. the demodulator logic 1 powered down and the power down pins on the ADCs are set to power down mode This 15 necessary to meet the 100 mA pre configuration USB current limit 12 11 Calibration The ADC will not self calibrate at power up since it has no clock It 15 therefore essential to calibrate the ADC by changing 0 0 from 0 to 1 to 0 whenever the ADC is taken out of the power down state 200 CE6231 User Manual Ref D73701 003 13 Electrical characteristics Test conditions unless otherwise stated Tamb 0 70 C Vdd 3 3V 5 and 1 8V 5 13 1 Recommended Operating Conditions Table 13 1 Recommended operating conditions ______ Max Unite Power supply voltage periphery core 120 Power supply current periphery 50 ___ ___ coe 185 ___ XI Crystal frequency 240 100 MHZ Toe ____ Operating ambionttemperatue o 0 fe Taser _ Reset Time after Valid Power 40 90 fms Theta JA Still Air _______ 44 1 Current from the 3 3 supply will be dependent the external loads 2 Decoding 8k 64QAM guard interval 1 4 code rate 2 3 3 Theta JA 0JA is the junction to ambient thermal resistance when the package is mounted on a four layer JEDEC standard test board with no airflow and dissipating maximum power Neither performance nor reliability is guaranteed outside th
31. 12 29 Example CSR medido vnd oe ato 179 12210 325WITO DUS AMS a aaa ___6_ aad 181 12 3 Demodulator register access 182 12 3 1 Enable the demodulator clock and ADC and reset the demodulator 182 12 3 2 Read the Reed Solomon error counters 183 12 9 9 2 Wire bus controller DY PASS usce dna cda iom doo Ne vade p a 184 12 34 EEPROM REQUINGIMNGING masa ie atu 184 12 3 4 1 Single address byte 184 12 3 4 2 Dual Address Byte 185 1255 EEPROM GAA OMA suut _____ 185 12 36 Star 8 Lec eset eee 186 12 3 7 Demodulator start up 186 12 3 8 Acquire channel 188 12 4 PID Tier programming 190 12 5 Suspend IMO 190 12 51 Automatic SUSPENSION vc 191 12 5 2 Software controlled 191 122522 TRESUMPUIOM 192 12 5 4 Demodulator power nennen nnne nnne nnne rasan asas na ns 192 12 6 Hira Red GeteClOl der P 192 12 7 GE6291 external uit d dim a mu edi dudes 193 12 7 1 Ex
32. 12 6 SUSP CTRL Register SUSP_CTRL Access Read Write Address DFh __ o j d 1 Symbol m o o eea IR SUSP DIS When bit 5 is set to 1 remote wake up is disabled even if the host has enabled this via the Set 5 Feature command SW DEMOD RST While bit 4 is set to 1 the internal demodulator is held in reset Since the power supply can be 4 7 E removed from the demodulator during suspend it is necessary for the software to control length of the reset 3 IR SUSP INV When bit 3 IS set to 1 a low level on IRDI will wake up the CE6231 during a suspend when 0 a high level will cause wake up When bit 2 is set to 0 the CE6231 will automatically enter suspend mode after 3 ms of USB bus 2 UP_SUSP_CTRL inactivity When bit 2 is set to 1 the suspend sequence will be controlled by 8051 software In either case a suspend interrupt SUSPI will indicate 3 ms of USB bus inactivity 4 SUSP INT CLR Bit 1 must be set to 1 then to 0 to clear the SUSPI within the SUSPI service routine else the interrupt will immediately re occur UP DO SUSP Set UP DO SUSP to 1 to finish the power down sequence turn off all clocks Suspend mode control X When bit 2 1s set the software must set UP DO SUSP to 1 to finish the power down sequence turn off all clocks The software should write a 0 to UP DO SUSP immediately afterwards D73701 003 CE6231 User Manual 67 9 127 DISCON CTRL DISCON_
33. 164 11 19 Registers that are not software 165 A 166 dutem etel Cip UE 167 119 95 CROCK CU r a a a E A E 168 PEISA eE E 169 12 USB software 170 12 1 DD Td 170 12 1 1 Software endpoint 0 command 171 12 1 2 PC Wile COMMandS 171 12 15 TOT6ead comdlids 172 D73701 003 CE6231 User Manual 7 12 2 Endpoint 0 example transfer 173 12 2 1 Class or Vendor command with no data 173 12 2 2 Class or Vendor write command with 10 bytes 174 12 2 3 Class or Vendor write command with 100 bytes 175 12 2 4 Class or Vendor read command with 80 bytes data 176 12 2 5 Class or Vendor read command with 1 byte 177 12 2 6 Software endpoint 1 178 12 2 7 USB control and status registers 178 12 2 8 High bandwidth isochronous transfers 179
34. CTL_5 Access Read Write Address Symbo The bit controls the output the RF AGC pin MUX The value of 0 outputs the calculated RF AGC value Leaving this bit at 1 forces the output to 64 AGC_RF_Min for test purposes The default value of 0 outputs generates an increasing output level on the RF AGC output as the 5 SENSE l a ee ud signal level increases Setting this to 1 inverts this if the external circuitry requires it 4 Reserved The RF AGC control via CE6231 will usually not be used and setting this bit to 1 default allows the 64 AGC RF MIN value go to the second AGC pin See also the AGC2 DIS bit in 0 register 5A 106 CE6231 User Manual D73701 003 11 2 8 Man 8Fh AGCManual Allows manual setting of the AGC output This value can be used to force the AGC output to a known value for hardware testing Its use is enabled by setting it to a non zero value whereupon the value 64 AGCManual 7 0 is used as the 14 bit AGC gain instead of the gain computed by the AGC circuit Please refer to the multiplexer in Figure 10 Ref D73701 003 CE6231 User Manual 107 11 29 IF LoLim AGC_IF_LOLIM 90h adi sat es ts S 11 2 1
35. CTRL Eth __ 1 1 j symbol 00000 2 When bit 5 is set to 1 soft disconnect of the USB bus occurs 68 CE6231 User Manual Ref D73701 003 9 128 8051 End point command EP 8051 CMD adi at ste tt Symbol i ee section and the command is invalid A STALL handshake will be returned to the PC Bit 2 should be set to 1 when the 8051 has read the DATA for a write command and the data is valid This should also be generated instead of 8051 DATAMID END after the SETUP section of a command with no DATA section This register is not used for a read command since the status packet is from the host instead Bit 1 should be set to 1 when the 8051 has processed a SETUP command for a transfer of 64 bytes or less and ADDR LENGTH and the data buffer for reads are valid This indicates that the SETUP command has been understood EPO 8051 DATAEND should also be set after EPO DONE has been received and the 8051 has prepared for the final data packet This register is only used for the last data packet in a transfer For earlier packets in a transfer EPO 8051 DATAMID is used instead EPO 8051 DATAMID Bit 0 should be set to 1 when the 8051 has processed a SETUP command for a transfer of more than 64 bytes and LENGTH and the data buffer for reads are valid
36. FAILED INT 3 is set when an endpoint 0 command fails due to an incorrect packet length 69 Note Bit 0 SETUP INT Note that a new SETUP command can occur at any time so the software should check this interrupt even if in the middle of another command 54 CE6231 User Manual D73701 003 9 11 12 INT EN1 Read Write adi 7 USCEMMIN EN usec OOOO s eo cmo raeme 2 ero OKINTEN SSS 1 EPO SETUP INT EN Setting each bit to 1 enables the corresponding bit in INT1 to generate an interrupt on 8051 interrupt 1 D73701 003 CE6231 User Manual 55 9 11 13 INT4A Read only S Toc _ Hs 6 SOF_INT Bit 6 is set after a USB Start of Micro Frame packet is received PF_LOST_SYNC2_INT Bits 5 4 are set when the first byte of a demodulator USB packet is not a sync byte This implies a loss of buffer pointer alignment due to loss of lock in the PID Filter unless PF LOST SYNC1 INT continuous data mode is in use when bits 5 4 should be ignored PF OVERFLOW3 INT PF OVERFLOW2 INT set when a buffer overflow occurs in the PID Filter on the corresponding data PF_OVERFLOW1_INT TWB_INT Bit 0 set after the 2 wire bus transaction completes or fails a 2 wire bus operation The 8051 INT4 interrupt pin is connected to 10
37. INT MAX LENGTH 1024 bytes PF EXT MAX LENGTH 512 bytes DS MAX LENGTH 192 bytes PF HEADER LEN 0 PF 1 BUFFER 0 PF 656 HBLANK DEL 0 PF PKT 015 1 PF INT353 EN 1 PF 656 I PF 12 1 PF INT FILT DIS 0 Example 5 CE6231 with external analog demodulator using isochronous transfers no PID filtering generating packetized DVB data with no headers CSRs 000C 60008082 Isochronous IN maximum packet size 1024 bytes 0014 48008084 Isochronous IN maximum packet size 256 bytes 0010 00080 3 Isochronous IN maximum packet size 1024 bytes 3 transfers microframe must be set last SFR settings A6 00 EP USE BULK 0 B7 00 B9 4 PF INT MAX LENGTH 1024 bytes BA ID PF EXT MAX LENGTH 948 bytes BB 40 I28 MAX LENGTH 256 bytes C2 38 EP3 HB CTRL 3 PF HEADER LEN 0 Ref D73701 003 CE6231 User Manual 199 60 1 BUFFER 0 PF 656 HBLANK DEL 1 2 3D INT353 1 PF 656 EN 1 PF 125 EN 1 The ITU 656 data rate after horizontal blanking 15 removed 1448 1728 27 22 625 MB s 2828 1 bytes microframe Hence the transfer size has been set to 948 bytes just a bit higher than 2828 1 3 12 9 RF level ADC The CE6231 features a 7 bit RF signal level monitor ADC in addition to the main 10 bit ADC 12 10 Power down The 2 ADCs have power down controls The main ADC is powered down using register 50 bit 1 the RF level ADC 1s powered down using register 5A bit 7 At CE6231 switch on
38. RS UBC Reed Solomon uncorrectable block counter This register pair is reset when RS 0 is read Hence this register contains the number of uncorrectable blocks in the time between two successive read operations D73701 003 CE6231 User Manual 145 11 124 Viterbi error period ERR PER VIT_ERR PER D6h VIT_ERR_PER Viterbi error period This counter determines a multiple of the number of data bits entering the Viterbi decoder which are counted and compared to the error count available in VIT ERR CNT 2 1 0 The actual counter value 15 Viterbi input bits 4 VIT ERR PER 65536 65535 So for the default register setting of FFh 4 255 65536 65535 67 108 860 bits 146 CE6231 User Manual Ref D73701 003 11 12 55 ERR CNT 2 1 0 VIT_ERR_CNT Read only Symbol VIT ERR CNT 2 ERR 1 VIT ERR CNT 0 MER Default EET _ 5 177 ______ Bit order 23 16 15 8 Cnt The pre Viterbi OFDM output bit error count This register contains the number of Viterbi input bit errors during the period defined by VIT ERR PER The Viterbi bit error measuring period see VIT ERR PER defaults to 67 108 860 bits so the Viterbi input BER is then given by VIT Err Cnt VIT Viterbi input BER Err Per 67 108 860 HF Note
39. Read only Symbol TPS CELL ID 1 TPS CELL ID 0 21h 22h ECCL order ai CELL 10 1 Sy to S47 frame 1 or 3 CELL ID 0 S45 to S47 frame 2 or 4 The 16 bit cell identifier is collected from two successive frames Before reading this register it 15 necessary to ensure that the contents of this are valid by reading bit 3 of the register STATUS 3 Caution Before reading this register it 15 necessary to ensure that the contents of this are valid by reading bit 3 of the register STATUS 3 128 CE6231 User Manual D73701 003 11 8 2 TPS MISC DATA 2 1 0 25h Default peat Eee Bit order 23 16 15 8 Symbol rae cary TPS length information tats bis 517 S22 of ETS 300 744 Table V _____ Paras Bits 1716 contain te number tat bis 523 amp 624 of ETS 300 744 Table 10 bis 40 553 of ETS 300744 Tabe 10 Ref D73701 003 CE6231 User Manual 129 11 9 On chip timer 11 9 1 Programmable Timer Period Register PROG_TIMER_PER Access Read Write Symbol TIMER PD 1 TIMER PD 0 Address Defaut ________ Bit order 15 Bit Symbol Description TIMER PD Refer to equation below These registers define the period for the timer interrupt in appro
40. The register is frozen when VIT ERR CNT 2 is read and unfrozen when VIT ERR CNT 0 is read Ref D73701 003 CE6231 User Manual 147 11 13 Status registers The status registers show the current status of CE6231 while the interrupt registers show the history of events that have occurred within the device Status register bits are not cleared when the corresponding register 15 read 11 131 STATUS 0 Register STATUS _0 Access Read only Address O6h ee ee Spectral_ Inv After a spectral inversion search this bit will indicate the spectral inversion status 6 Full Lock All stages are locked and therefore data should be available to the USB Set by the control FSM when Byte Align lock has occurred FEC Lock indicates that the FEC byte 5 FEC Lock aligner has locked at least once There is a difference between this and byte lock signal in the FEC status register which indicates the current lock status of the byte aligner Lock is with first byte lock and remains set until there is a re acquisition or an auto re acquisition 3 TPS Lock A valid TPS word has been found This will usually happen within two frames from FSM OFDM FOUND FEC lock may occur before TPS lock Set by the control FSM when all OFDM pilots are found Used to test for the presence of a DVB T 2 OFDM_Found channel At this point the device has compensated for any frequency timing offsets and spectral inversions Sym_Lock Set
41. Wire Bus 9 14 1 TWB_STATUS Two wire bus status TWB STATUS d _ ret Symbol Bits 3 1 indicate failure due to acknowledge or stuck pins twa Done Bt Oindcatos These bits indicate the status of the previous 2 wire bus command One of these bits will be set at the same time TWB INT occurs The register 15 reset when the software writes a non zero value to TWB CMD Ref D73701 003 CE6231 User Manual 81 9 14 2 RD Two wire bus status TWB GPP CTRL RD S _ _ LL 2222222 This contains the status of the 2 wire bus pins 82 CE6231 User Manual Ref D73701 003 9 14 3 TWB_CMD 2 wire bus commands Read Write Dh adi tet tt sts ts i eea mesme The 8051 can generate 2 wire bus command by writing 1 to one of these bits The register bit will reset automatically after the command completes INT TWB STATUS will be set at the same time Bit 4 should be used for the last read in a 2 wire bus command sequence Bit 3 should be used for all previous reads Ref D73701 003 CE6231 User Manual 83 9 14 4 TWB_DATA D2h adi at es TWB DATA 2 wire bus data This register 15 should be wr
42. contains several mechanisms to reduce the impact of impulse noise on system performance 10 12 Transmission Parameter Signalling TPS An OFDM frame consists of 68 symbols and a superframe is made up of four such frames There is a set of TPS carriers in every symbol and all these carry one bit of TPS These bits when combined include information about the transmission mode guard ratio constellation hierarchy and code rate as defined in ETS 300 744 In addition the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are in odd frames The TPS module extracts all the TPS data and presents these to the processor in a structured manner 10 13 This module generates soft decisions for demodulated bits using the channel equalized in phase and quadrature components of the data carriers as well as per carrier channel state information CSI The de mapping algorithm depends on the constellation QPSK 16 QAM or 64 QAM and the hierarchy a 0 1 2 or 4 Soft decisions for both low and high priority data streams are generated 10 14 Symbol and Bit De Interleaving The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol The de interleaver modules consist largely of memory to invert these interleaving functions and present the soft decisions to the FEC in the original order 10 15 Viterbi Decoder The Viterbi dec
43. from the EPROM without the device suspending When the firmware has loaded the suspend interrupt will be set and the firmware should initiate the suspend procedure D73701 003 CE6231 User Manual 191 12 5 3 Resumption The CE6231 will exit the suspend state after resume signalling 15 detected on the USB The crystal oscillator will be powered up the SLEEP output will be driven low and USB 8051 PLL will be powered up The USB 8051 clock will be held until the PLL has settled hence the software should resume cleanly at the address where the clock was stopped The CE6231 will also exit suspend via infra red wakeup If remote wakeup is enabled bit 1 of SFR AO 15 set then IRDI pin enables wakeup When IR SUSP INV is wakeup occurs when IRDI goes low When IR SUSP INV is 0 wakeup occurs when IDRI goes high The INTO N and INT2 interrupts can be used to find out whether the resumption was caused by the infra red detector The 8051 may need to carry out some operations on resumption After pulsing UP DO SUSP to 1 the software should wait for SFR bit 2 to go low before carrying out resume operations After resumption the demodulator always receives a full reset 12 5 4 Demodulator power down In the description above the demodulator supply current was kept to a minimum by stopping the clocks This will eliminate the dynamic power consumption However there will still be a small leakage current remaining The demodulator leak
44. has time to read this register Bit 1 is set to 1 after a data packet has been successfully written to read from the memory pointed to ADDR If the previous packet was an 8051 DATAMID the software must prepare for the next DATA packet Otherwise for EPO 8051 DATAEND the behaviour is different depending on the direction of the DATA For DATA writes to 8051 RAM the STATUS response EPO DONE must be generated by the 8051 by setting EPO 8051 STATUS or EPO 8051 STALL to 1 Hence EPO DONE and EPO DONE INT are sent to the 8051 For DATA reads the STATUS response is to the 8051 so the 8051 does not need to take any action at this stage For this reason EPO DONE is not set but DONE still is Bit 1 is reset to 0 after the software sets EPO 8051 DATAMID EPO 8051 DATAEND EPO 8051 STATUS or EPO 8051 STALL is set to 1 after each new SETUP packet is received on endpoint 0 It indicates that the data in the memory pointed to by EPO SETUP ADDR is valid This bit is reset to O after the software sets EPO SETUP EPO 8051 DATAMID EPO 8051 DATAEND EPO 8051 STATUS or EPO 8051 STALL Note that a new SETUP command can occur at any time so the EPO SETUP interrupt should be checked as well This register indicates the status of endpoint 0 and endpoint 1 transfers 62 CE6231 User Manual D73701 003 9 12 2 USB STATUSO USB STATUSO Read only 9Eh S _ at
45. hasten eae 93 1014 Symbol and Bit DesInterleavihig sonus 93 105159 Vero Mast 93 10 16 MPEG Frane pede itu 94 1072 DesnterledVbl eon imum ur Wei cis ades Nas sence oa Sea 94 10 18 94 NM eR ER UA 94 10 20 Differences 95 11 Demodulator Registers 96 11 1 Demodulator Register Summary 96 11 2 Automatic Gain Cohlrel 3 ee pads wand dicen euet 99 System descHplolLll 99 11 22 IRE GIP AGC 100 11 2 3 Configuring the output voltage limits 101 11 2 4 Setting the IF RF crossover 102 AGC TARGET E 104 Ref D73701 003 CE6231 User Manual 5 105 106 TED 107 11248 WE SEODIITIG S 108 112 10 RFE AILI
46. interrupt when 0 INT1_N is low priority When bit 1 is 1 Timer O interrupt is high priority when O Timer O interrupt is low priority 0 PXO _____ When bit 1 INTO Nis a high priority interrupt when 0 INTO is low priority This register sets the timer interrupt priority level in the 8051 core D73701 003 CE6231 User Manual 53 9 11 11 INT1 Interrupt 1 Read only S oe dbo _ klal c 7 SBC_ENUM_INT Bit 7 is set after a USB bus reset is detected U USBC SET CSRS INT Bit 6 is set when the USB CSR Registers need to be reprogrammed after Set Interface or Set Configuration command E E P1 STATUS OK INT Bit 4 is set when an endpoint 1 transfer completes successfully 2 EPO STATUS OK INT Bit 2 is set when the status packet is successfully received from the host during a read command Bit 1 is set after a data packet has been successfully written to read from the memory pointed EPO DONE INT to by EPO ADDR except for the last data packet in a read command In the latter case bit 2 will be set instead after the status section completes EPO SETUP INT Bit 0 is set after each new SETUP packet is received on endpoint 0 It indicates that the data in the memory pointed to by EPO SETUP ADDR is valid This 1s the USB event interrupt register When individually enabled these bits are NOR ed together to generate the 8051 INT N input This register is self reset after reading PO
47. loaded the 2 wire bus master is controlled by the 8051 TWB SRC selects 2 wire bus destination either external interface 1 or 2 or the internal demodulator After the destination has been selected a 2 wire bus command can be sent by writing to TWB DATA and TWB CMD The demodulator 2 wire bus address 15 fixed at 0001111 D73701 003 CE6231 User Manual 181 12 3 Demodulator register access examples 12 3 1 Enable the demodulator clock and ADC and reset je OX y 22 Ww Ww N N N N NNN N WN gt NV 182 the demodulator Write 04 to TWB_SRC Select demodulator and 330 kHz speed Write 01 to TWB CMD Send START Wait for TWB INT Check for successful status in TWB STATUS Write IE to TWB DATA Address OF write mode Write 04 to CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 50 to TWB DATA CE6231 EN Write 04 to TWB CMD Do write Wait for TWB_INT Check for successful status in TWB STATUS Write 03 to TWB DATA Enable demodulator and ADC Write 04 to TWB CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 02 to Send STOP Wait for TWB INT Check for successful status in TWB STATUS Write 01 to TWB CMD Send START Wait for TWB INT Check for successful status in TWB STATUS Write IE to TWB DATA Address OF write mode Write 04
48. normalized to the ADC sampling rate The default value of this has been set for 8 MHz OFDM and 45 MHz sampling Hence if the OFDM channel bandwidth is different and or if the ADC sampling rate 15 changed then this register has to be modified Since there 15 decimation by 2 in the ITB the effective sampling rate seen by the TRL 1 22 5 MHz TRL Nominal Rate is the ratio between channel bandwidth ChanBW and ADC sampling rate expressed as an unsigned 16 bit integer 1 TRL_NominalRate ChanBW 8 where f4nc is ADC sampling rate in MHz Channel BW High sampling rate TRL Nom Rate Low sampling rate TRL Nom Rate 8 MHz 45 45 0 26631 6807h 20 40 29372 72BCh 7 MHz 45 45 0 23302 5806 20 40 25700 6464 6 MHz 35 34 5 26052 65C4h 19 5 23046 5A06h 116 CE6231 User Manual Ref D73701 003 11 5 Carrier Frequency Synchronisation CE6231 can lock onto an OFDM signal with a relatively large frequency offset at input This section contains description of the register which is used to set the capture range and the read register triplet which has this frequency offset information after the OFDM has locked 11 5 1 RANGE The effective IF frequency specified by INPUT FREQ 1 0 register may not be precise for two reasons Firstly there could be deliberate frequency shifts introduced to the channel by the transmitter Secondly the tuner may be unable to set the exact frequency owing to its f
49. number and that the frequency offset computed from the above equation is a signed quantity In normal operation an AFC loop ensures that this frequency offset is kept down to a small value by continuously transferring this to the baseband down converter of the CE6231 Hence in order to obtain a stable value for the frequency offset during a channel scan the AFC loop must be temporarily disabled see CTL Ref D73701 003 CE6231 User Manual 119 11 66 Transmission Parameter Signalling TPS The TPS carriers are used for the purpose of signalling parameters related to the transmission scheme 1 to channel coding and modulation The TPS is transmitted in parallel on 17 TPS carriers for the 2K mode and on 68 carriers for the 8K mode Every TPS carrier in the same symbol conveys the same differentially encoded information bit The TPS carriers convey information on modulation including the value of the QAM constellation pattern see note e hierarchy information e guard interval e inner code rates e transmission mode e frame number in a super frame cell identification NOTE The a value defines the modulation based on the cloud spacing of a generalized QAM constellation It allows specification of uniform and non uniform modulation schemes covering QPSK 16 and 64 11 6 1 Scope of the TPS The TPS is defined over 68 consecutive OFDM symbols referred to as one OFDM frame Four consecutive frames
50. red port for remote control signal decode in software Self or bus powered modes e 8 general purpose ports Full chip control over USB bus 3 3 1 8V operation e 80 pin LQFP e Low external component count Evaluation board and comprehensive software e Full front end NIM reference design available Applications Hybrid analog digital or twin digital tuner application e Terrestrial PC applications e Digital terrestrial TV set top boxes e Digital terrestrial integrated televisions 14 CE6231 User Manual D73701 003 2 2 Applications The 6231 is intended for use in a dual tuner system Figure 1 shows watch and record DVB T system for use in a recordable media box This uses an external CE6353as a second DVB T demodulator Figure 1 Watch and record DVB T system IF gt RF in AGC gt Tuner lt 2 wire gt USB CE6231 IF RFin tuner 4 496 MPEG2 2 wire bus A p i 2 wire bus ZANEZ detector XTAL y EEPROM Figure 2 shows an analog and digital PC TV application The analog demodulator will generate ITU 656 video data and 125 audio data for the CE6231 to transfer over the USB Figure 2 Analog and digital TV system
51. require changes during normal operation Monitoring of the AGC status locked or not and input levels is through interrupt registers status registers and the AGC gain and level registers 100 CE6231 User Manual D73701 003 Figure 12 below shows how gain control range is assigned to the two AGC sections Figure 12 AGC control range 14 27 1 U IF_Max eel Unr diues 0 t E Gnr Max Or win O 8 5 S 5 D B 5 gt B 5 LL 84 UF win Limit points can be set individually as required 11 2 3 Configuring the output voltage limits To control both the RF and IF sections of a tuner four registers IF Max IF Min RF Max and RF Min need to be set up to determine the limiting voltages of the AGC outputs Table 11 1 AGC voltage limit setting IF Max 92h Sets the highest voltage U hereU IF 7 01 64 of the IF AGC range Vir wes Vere x 16383 IF Min 93h Sets the lowest voltage U whereU IF MIN 7 0 64 of the IF AGC range ye IF Min _ Min 16383 94h Sets the highest voltage U whereU po RF 0 64 of the RF AGC range Vus _ 16383 58h Sets the lowest voltage U where ZRF MINV 0l 64 This example illustrates the above A typical two stage tuner requires the IF
52. when the initial symbol timing lock has been established 0 AGC Lock Set when the AGC is in lock 148 CE6231 User Manual D73701 003 11 13 2 STATUS_1 S oe dko leol asila ___ DSCR_Lock Set when the Descrambler is in lock Set when the Byte Aligner is in lock This is a different signal to bit B5 of STATUS_0 and will BA Lock immediately show loss of byte align lock in the event of severe errors ONE NN The CE6231 has STATUS 2 register Ref D73701 003 CE6231 User Manual 149 11 13 3 STATUS 3 Register STATUS 3 Access Read only Address 09h S Toc _ Pr Reed E s 5 This bit is set to 1 if valid TPS data were received during the previous TPS frame TPS_LOCK is 4 TPS_ Valid when TPS_VALID goes high for the first time during an acquisition After that the TPS_ VALID may go low if the BCH checksum of an OFDM frame is incorrect This has no effect on TPS_LOCK Cell ID Valid Indicates the presence of a valid cell identifier in the TPS CELL ID 1 0 registers es To 150 CE6231 User Manual Ref D73701 003 11 14 Status enables Setting one or more bits of these registers enables the corresponding demodulator status bits from the STATUS registers to be output on GPP6 pin 2
53. 0 provided that STATUS OP EN in Demod Status register and GPPDIR 6 have been set The logical OR combination of all enabled status bits will be output Only one bit should be set at a time for the output to be meaningful 11 14 1 STATUS EN 0 STATUS EN 0 Symbo 6 Valid En Enables the TPS Valid bit value see STATUS register bit 4 to be output on GPP6 pin 20 Enables the Spectral Invert bit value see STATUS_0 register bit 7 to be output on GPP6 20 Enables the OFDM Lock bit value see STATUS 0 register bit 6 to be output on GPP6 pin 20 Enables the Lock bit value see STATUS 0 register bit 3 to be output on GPP6 pin 20 Enables the OFDM Found bit value see STATUS 0 register bit 2 to be output on GPP6 pin 20 Enables the SYM Lock bit value see STATUS 0 register bit 1 to be output on GPP6 pin 20 0 Lock En Enables the Lock bit value see STATUS 0 register bit 0 to be output on 6 pin 20 Status enable 0 register default setting set to select OFDM Locked enabled See also SFR DEMOD STATUS Caution It is important to note that these enable bits do NOT have a 1 1 map with the corresponding bits of STATUS 0 D73701 003 CE6231 User Manual 151 11 14 2 STATUS EN 1 STATUS EN 1 adi at se IE _ T DSCR_Lock the DSCR
54. 0 RF HiLim AGC IF LIMITS uim If gain 1s equally distributed between the RF and IF amplifiers the AGC IF LOLIM and AGC RF HILIM will both be close to mid range 128 However the LO will be made a bit smaller than 128 and the HI LIM a bit larger than 128 to introduce some overlap between the AGC loops In the default mode the RF amplifier 15 not used Hence IF amplifier is made to take the full range by setting its low limit to zero 108 CE6231 User Manual D73701 003 11 2 11 IF Read Write 11 2 12 IF_Min Read Write 93h uim Ref 073701 003 CE6231 User Manual 109 11 2 13 Read Write st es ts Symbo 11 214 Min Read Write 58h uim olem o o 110 CE6231 User Manual Ref D73701 003 11 2 15 Read Write Fh __ o 1 j 1 10 1 1 7 _ Symbol The default corresponds to unity gain Do not modify this register setting if the RF AGC loop is not being used 11 2 16 Read Write The gain coefficient is to zero because the RF AGC loop is us
55. 03 11 19 2 CLOCK CTL 0 CLOCK 0 Default n 1 o 1 Bit Symbol Description ADC sample rate A 0 in this bit sets a lower sampling rate Normally the default of 1 will be used The PLL 1 0 bits define the PLL range The PLL in CE6231 allows a wide range of frequencies to be specified however only certain modes are characterised for use with either a 24 0 MHz crystal For all these modes the bits SR see above and ADCS see register CLOCK 1 are left in their default states Table 11 14 Available clock modes PLL 15 0 20 40 40 80 68 00 39 0 2 00 T Channel BW MHz 45 0 45 0 60 00 OFDM DIV FEC DIV ADC clock MHz OFDM clock e FEC clock MHz 34 5 55 20 Bytes 51 to 54 CLOCK_CTL_0 1 PLL C5DBh Ref D73701 003 CE6231 User Manual 167 11 19 3 CLOCK 1 0 1 1 1 OFDM OFDM_DIV 3 0 sets the division ratio for the OFDM logic clock DIV FEC DIV 2 0 sets the division ratio for the FEC logic clock ADCS The ADCS bit sets the clock source for the ADC The default setting of 0 uses the PLL If set to 1 the ADC is clocked directly from the crystal clock not recommended These control the clock division ratios for OFDM and FEC clocks see section 10 1 When ADCS 1 set to 1 the ADC is clocked directly from the crystal rather than from
56. 1 Figure 6 Internal RAM organisation 23 Figure 7 Interrupts used by the 6231 47 Figure 8 OFDM demodulator 90 Figure Block diagr al 91 Figure 10 6231 AGC internal system 99 Figure TT CE6231 System OU UNG 100 Figure 12 control range SRM TERT 101 Figure 13 System gain v RF 102 dizi DUNO M mm 113 Figure 15 123 Figure 16 Acquisition Re acquisition flow 124 Figure 17 Single address byte nn nnn nnne 184 Figure 18 Dual address byte 185 Figure 19 Start up 187 Figure 20 Channel ACQUISINOM iz ana iudi cous aita oa Ea St mue save Ada pa naa 189 Figure 21 2 iro ePi 193 Fig re 22 Serial ala ER 194 Figure 23 125 data re alignment 195 196 Ref D73701 003 CE6231 User Manual 9 List of Tables Table 1 1 Document
57. 10 2 Automatic Gain Control An AGC module compares the absolute value of the digitized signal with a programmable reference The error signal is filtered and 1 used to control the gain of the amplifier A sigma delta modulated output 15 provided which has to be RC low pass filtered to obtain the voltage to control the amplifier The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking The AGC 1s free running during OFDM channel changes and locks to the new channel while the tuner lock is being established This is one of the features of CE6231 used to minimize acquisition time A robust AGC lock mechanism is provided and the other parts of the CE6231 begin to acquire only after the AGC has locked Ref D73701 003 CE6231 User Manual 91 10 3 IF to Baseband Conversion Sampling a 36 17 MHz IF signal at 45 MHz results a spectrally inverted OFDM signal centred at approximately 8 9 MHz The first step of the demodulation process is to convert this signal to a complex in phase and quadrature signal in baseband A correction for spectral inversion 15 implemented during this conversion process Note also that the CE6231 has control mechanisms to search automatically for an unknown spectral inversion status 10 4 Adjacent Channel Filtering Adjacent channels in particular the Nicam digital sound signal associated with analogue channels are filtered prior to the FFT 10 5 Interpolation
58. 141 TWB STATUS Two wire bus 81 9 14 2 TWB_GPP_CTRL_RD Two wire bus 82 9 14 3 TWB_CMD 2 WIre bus e See ais Sosa Ee ioi sem dene neice 83 9dd4 TNB DATA Ine eo a eA T 84 SM MESI P M ange 85 9 146 TWB GPP CURL muita det 86 9 15 General PUMOSS POMS tete 87 151 CGRP 2 DUR cmm 87 2 ATE 88 9 16 89 10 Demodulator Functional 90 10 1 Analogue to Digital 91 10 2 T ET 91 10 3 IF to Baseband COMVGISIOMN E 92 10 4 Adjacent Channel Filtering leute Iram t ed ned os 92 10 5 Interpolation and Clock Synchronisation 92 10 6 Carrier Frequency Synchronisation 92 10 7 Symbol Timing SVACHVOMISAUOM EAA 92 10 8 92 10 9 Common Phase Error 93 1010 93 VOR Impulse 93 10 12 Transmission Parameter Signalling 93 10 123
59. 1500 and the external filter with the PIDs 0708 and 094F starting at address 0x0048 Set PID INT BASE ADDR to 0x012 Set PID EXT BASE ADDR to 0x014 Set PID INT MAX to3 Set PID EXT MAX to e Write 02 to 0048 e Write 03 to 0049 e Write D8to 004A e Write 06 to 0048 e Write 2C to 004C e Write 10 to 004D e Write 00 to 004E e Write 15 to 004 e Write 08 to 0050 e Write 07 to 0051 e Write 4F to 0052 e Write 09 to 0053 The PID filters can be disabled by setting EN 5 4 12 5 Suspend mode USB devices must support a suspend mode in which the current drawn from the bus must be less than 500 uA For remote wakeup enabled devices this limit 1s raised to 2 5 mA but only when the remote wakeup feature has been enabled by the PC The PC requests device suspend mode by stopping USB activity for more than 3 ms There are 2 ways for the CE6231 to respond to a suspend request 190 CE6231 User Manual D73701 003 12 5 1 Automatic suspension This mode is enabled by resetting bit 2 of SUSP_ CTRL After the suspend condition is detected on the USB the following steps occur sequence A suspend interrupt is generated to the 8051 The AGC pins are pulled high The demodulator ADCs are powered down The demodulator PLL is powered down The SLEEP output is driven high The USB and 8051 PLL 1 powered down The crystal oscillator 1 powered down Oo The SLEEP output be used to power down t
60. 17571 BB5Dh 43 75 4 1500 15964 C1A4h 114 CE6231 User Manual Ref D73701 003 11 3 2 BW Register BW_CTL Access Read Write Address 64h __ 1 1 1 _ Symbo eea OFDM BW 1 0 value sets the bandwidth for the OFDM sections of the CE6231 In addition to 1 0 OFDM_BW 1 0 programming this register it is necessary to program the TRL_NOMINAL_RATE registers for different OFDM bandwidths and sampling rates Table 11 4 Elliptic filter options OFDM BW Bandwidth o0 ee 490 18 Default ptt _________ Ref D73701 003 CE6231 User Manual 115 11 4 Interpolation and Clock Synchronisation The CE6231 samples the input signal at a fixed sample rate An interpolator controlled by a clock recovery loop is used to re sample this signal at the OFDM sample rate This section contains the description of the register used to set the ratio between the ADC sample rate and the OFDM sample rate The default setting is for 45 0 MHz sampling and 8 MHz OFDM This register has to be modified for other sampling rates and channel bandwidths 1141 TRL Nominal Rate 0 1 TRL_Nominal_Rate Read Write Symbol TRL Nominal Rate 1 TRL Nomianl Rate 0 66h TRL_Nominal_Rate Sets the ratio between OFDM and ADC sample rates TRL NOMINAL RATE register defines the OFDM sampling rate
61. 2 CE6231 User Manual D73701 003 12 7 CE6231 external inputs 12 7 1 External DVB Demodulator Input The CE6231 provides inputs for an external DVB satellite terrestrial or cable demodulator MPEG2 transport stream The data input can be either parallel data at up to 12 MHz or serial data on MDI 0 at up to 100 MHz The waveforms for the data are shown in Figure 21 and Figure 22 If PF MISC bit 1 15 set the falling edge of MCLK 15 used to sample the data otherwise the rising edge of MCLK 1s used Figure 21 Parallel data format MISTART MIVAL The external DVB data will be transferred using USB endpoint 3 Bit 7 of PF MISC must be set to 0 to enable external data transfer Ref D73701 003 CE6231 User Manual 193 Figure 22 Serial data format MCLK MDIO MISTART MIVAL Byte 0 Byte 1 MCLK MISTART MIVAL Byte 187 194 CE6231 User Manual Ref D73701 003 12 7 2 External Analog Video and Audio Input The CE6231 provides inputs for an external analog TV demodulator that generates ITU 656 video data and 125 audio data The DVB input pins are re used for this The video data input will be 8 bit samples at 27 MHz on pins RD 7 0 If PF MISC bit 1 is set the falling edge of RCK is used to sample the data otherwise the rising edge of 1s used The audio data is serial data at up to 7 MHz The format of 125 data is shown in Figure 24 If PF MISC bit 2 is set the f
62. 2 Timer 2 Reload Capture This register contains the Timer Two current count and 15 available two bytes T2L Low byte and T2H High byte Ref D73701 003 CE6231 User Manual 43 9 11 Interrupts The following SFRs are associated with interrupt control JE SFR A8h SFR EXIF SFR 9 EICON SFR D8h EIE SFR E8h EIP SFR F8h The IE and IP SFRs provide interrupt enable and priority control for the standard interrupt unit The EXIF EICON EIE and EIP registers provide flags enable control and priority control for the extended interrupt unit There are 7 interrupts used in the CE6231 as listed in Table 9 3 Table 9 3 CE6231 internal event interrupts Name Sensitive Suspend interrupt In order to use any of the interrupts the following three steps must be taken 1 Set the EA enable all bit in the IE register to 1 2 Setthe corresponding individual interrupt enable bit in the IE register to 1 3 Begin the interrupt service routine at the corresponding Vector Address of that interrupt See Table 9 4 In addition to use the demodulator interrupts the following steps must also be taken 1 Set appropriate interrupt enable in the demodulator 0 1 2 4 2 Set demodulator interrupt enable INT CTRL O 3 Set the external interrupt enable EIE 1 44 CE6231 User Manual Ref D73701 003 9 11 1 Interrupt Processing When an enabled interrupt occurs the CP
63. 2K 001 16 QAM a 1 2 3 2 3 1 16 8K 010 64 QAM 2 3 4 3 4 1 8 Reserved 011 Reserved a 4 5 6 5 6 1 4 Reserved 100 n a n a 7 8 7 8 n a n a 101 n a n a 110 111 Ref D73701 003 CE6231 User Manual 125 11 7 2 0 1 GNE _ _ _ _ Bit order 15 8 ___ This is a copy the corresponding bit the TPS GIVEN current See table below This defines the current OFDM and FEC parameters used by the demodulator FEC in the ETS 300 744 format The LP bit is a copy of the corresponding bit in the TPS GIVEN 1 0 register and indicates whether it is the low or high priority bit stream that is being FEC decoded Table 11 9 TPS GIVEN data format not including ETSI 300 744 Annex DVB H modes Channel TPS signalling bit number 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Received TPS signalling bit number TPS RECEIVED 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sel Constellation Hierarchy HP code rate LP code rate Guard Mode Signalling function Constellation Hierarchy HP code rate LP code rate Guard Mode 000 QPSK Non hierarchical 1 2 1 2 1 32 2K 001 16 QAM 1 2 3 2 3 1 16 8K 010 64 QAM a 2 3 4 3 4 1 8 Reserved 011 Reserved a 4 5 6 5 6 1 4 Reserved 100 7 8 7 8 111 126 CE6231 User Manual Ref D73701 003 11 73 TPS RECEIVED 0 1 Bit order 15 8 Symb
64. 5 is a bit addressable general purpose flag for software control RS 0 Register bank select Bits 4 3 select the current register bank to use as given in table below Overflow flag Bits 2 is set to 1 when last arithmetic operation resulted in a carry addition borrow subtraction or overflow multiply or divide otherwise cleared to 0 by all arithmetic operations 2 User flag 1 Bit 1 is a bit addressable general purpose flag for software control Parity flag Bit 1 set to 1 when modulo 2 sum of 8 bits in accumulator is 1 odd parity cleared to 0 on even parity The Program Status Word PSW contains several status bits that reflect the current state of the CPU The PSW shown in below resides in SFR space It contains the Carry bit the Auxiliary Carry for BCD operations the two register bank select bits the Overflow flag a Parity bit and two user definable status flags The Carry bit other than serving the functions of a Carry bit in arithmetic operations also serves as the Accumulator for a number of Boolean operations The bits RSO and RSI are used to select one of the four register banks shown in Table 9 1 A number of instructions refer to these RAM locations as RO through R7 The selection of which of the four banks is being referred to is made on the basis of the bits RSO and RS1 at execution time The Parity bit reflects the number of 1s in the Accumulator P 1 if the Accumulator contains an od
65. 852 BI3 sa 1479 m MS 3203A sn a m ano EAE 7HABDI A cui L 8 HZUZWIH idee see p sa 95 5 T M878402A ai 3 1 N PHY zim aa s RE RE lt lt lt lt lt lt lt lt lt X 4 E sci lWadwv m m n o o 0 m Ze 2 6 6 n l yas 75 5 Ug Scu ans 571 Jugg dn B2 aug 10H gay e lt Tee ang AZZ AA I UTI ar A JH sum Hes SASIH et a 5 Em Ed oF d af a TT ss S27PS585 8 e uuoggl 82 aus AA meet FT 1 gt ana gt D E u E Sugai fay 5 LEJ BEJ L pu amp y DK 1 gt vas AAT i x sv ana mS V EAE ppay _ MS EnE En d3 II V LLVBA DEzS323 is cau ziaw In as Hea
66. A write returns NYET or ACK for full speed mode USB controller writes 64 bytes to ADDR USB controller sets EPO DONE status and interrupt PING returns NAK 0 to n occurrences DATA write returns NAK 0 to n occurrences 8051 sets EPO LENGTH to 36 8051 sets 8051 DATAEND DATA write returns USB controller writes 36 bytes to EPO ADDR USB controller sets EPO DONE status and interrupt STATUS stage read returns NAK 0 to n occurrences 8051 sets EPO 8051 STATUS STATUS stage read returns zero length packet CE6231 User Manual Class or Vendor write command with 100 bytes data 175 12 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 176 2 4 Class or Vendor read command with 80 bytes data SETUP packet received USB controller returns ACK USB controller writes 8 bytes to SETUP ADDR USB controller sets SETUP status and interrupt DATA read returns 0 to n occurrences 8051 writes 64 bytes to EPO ADDR 8051 sets EPO LENGTH to 64 8051 sets EPO 8051 DATAMID DATA read returns 64 bytes and ACK USB controller sets EPO DONE status and interrupt DATA read returns 0 to n occurrences 8051 writes 16 bytes to EPO ADDR 8051 sets EPO LENGTH to 16 8051 sets EPO 8051 DATAEND DATA read returns 16 bytes and USB controller sets EPO DONE status STATUS packet received USB controller returns ACK handshake USB controller sets EPO STATUS
67. Bit 5 is set when the USB PHY is in an error state USBC ENUM SPEED usec 5 Bis 43 indicate the speed of the USB host 00 indicates high speed 01 or 11 indicates full Bit 2 is set to 1 after 3 ms of inactivity of the USB the suspend interrupt will occur at the same USBC SUSPEND time It is reset after the device resumes from the suspend state It is recommended to use the suspend interrupt instead to detect the start of suspend to ensure that the suspend timing requirements are met Bit 1 is set to 1 when the remote wake up feature has been selected by a Set Feature 1 RMT WKUP FEAT command The software should check this bit during a suspend request to decide whether the infra red detector should be powered down USBC SET CSRS is set to 1 when the USB CSR Registers need to be reprogrammed after a Set Interface or Set Configuration command This bit is reset after the software sets APP_DONE_CSRs Ref D73701 003 CE6231 User Manual 65 9 125 USBC_STATUS3 4 DCh d o do dz bz eee _ Bit order 0 R 10 eem CRT NUM 13 11 USBC UFRAME NUM USBC UFRAME NUM is set to the Microframe Number of the last SOF packet USBC TIMESTAMP USBC TIMESTAMP is set to the Frame Number of the last SOF packet USBC TIMESTAMP is set to the Frame Number of the last SOF packet USBC UFRAME NUM is set to the Microframe Number of the last SOF packet 66 CE6231 User Manual D73701 003 9
68. CE6231 COFDM demodulator with USB interface for PC TV User Manual March 29 2007 Revision 1 2 Reference Number D73701 003 Legal Statements INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS NO LICENSE EXPRESS OR IMPLIED BY ESTOPPEL OR OTHERWISE TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT EXCEPT AS PROVIDED IN INTEL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS INTEL ASSUMES NO LIABILITY WHATSOEVER AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO SALE AND OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT Intel products are not intended for use in medical life saving life sustaining applications Intel may make changes to specifications and product descriptions at any time without notice Designers must not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them This manual may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characterized errata are available on request This manual as well as the software described in it i
69. CSR DATAO AFh Address 008 12 0000 0 Oh BOh Default 00h 31 24 23 16 15 8 7 31 0 CSR_DATA Contains the data to be written the data read from the selected CSR as set by CSR_ADDR Ref D73701 003 CE6231 User Manual 73 9 13 PID Filters 9 13 1 PF_EN Data stream PID filter enable Read Write __ 1 o ___ 5 PF EXT FILT DIS Bit 5 disables the PID filter for external demodulator data 1 disabled 0 enabled When disabled the entire transport stream will be sent over the USB 4 PF INT FILT DIS Bit 4 disables the PID filter for internal demodulator data 1 disabled 0 enabled When disabled the entire transport stream will be sent over the USB EN __ DVB T Bits 0 to 3 select which data streams are selected for output USB When bit is set to 1 the stream is enabled for output when 0 data from the stream is discarded at the input to the PID Filter block amp Tip Bits 3 0 can also be used as reset signals to clear error conditions on the relevant stream e g OVERFLOW1 INT 74 CE6231 User Manual Ref D73701 003 9 13 2 INT PID_INT Read Write Symbol PID INT MAX PID INT BASE ADDR 1 Default Bit order 0 15
70. EFACE SET INTERFACE For these commands the registers are not used After a SET CONFIGURATION or SET INTERFACE command is sent the new configuration or interface setting is written to USBC STATUSO or USBC STATUSI then the USBC SET CSRS interrupt is set Either bit 4 or bit 5 of USBC STATUSO will be set to indicate which command was sent The 8051 software must re program the USB Control and Status Registers then set APP DONE CSRS to 1 The USB controller returns to the STATUS stage until APP DONE CSRS is set Bits 4 and 5 of USBC STATUSO are cleared when APP DONE CSRS is set The GET DESCRIPTOR command must be decoded in software The SYNCH FRAME command is not supported this gives a STALL response The SET DESCRIPTOR command is not supported by default gives a STALL response but can be enabled and must then be decoded in software 12 1 1 Software endpoint 0 command processing This process is required for the GET DESCRIPTOR command and any class or vendor commands When a SETUP packet 1 received without error it 15 checked to see if it should be handled in hardware If not the data is written to the Data RAM at the address pointed to by EPO SETUP ADDR Then EPO SETUP is set to 1 and EPO SETUP INT is set The software must respond by setting a bit in 8051 CMD to 1 If the command is invalid EPO 8051 STALL should be set to 1 This will send a STALL handshake response in the data and status stages of the command 12 1 2
71. ENGTH defines the maximum length in bytes that be sent one external 21 11 PF EXT MAX LEN video MPEG TS or ITU 656 USB transfer For bulk mode this must be set to 512 high speed or 64 full speed This register defines the maximum length in bytes that may be sent in one internal demodulator 10 0 PEAN MRA USB transfer For bulk mode this must be set to 512 high speed or 64 full speed These registers define the maximum length for USB transfers of audio video and demodulator data N Caution INT MAX LEN has a gap in register addressing from B7h to B9h B8h is part of PF INT MAX LEN The following restrictions apply to bulk transfers The maximum length register PF INT MAX LEN PF EXT MAX LEN must be set to the bulk maximum packet size 512 bytes in high speed or 64 bytes in full speed mode e All transfers must be an exact multiple of the maximum packet size e Only continuous data without headers be used PF HEADER LEN 0 PF PKT DIS 1 No sync byte alignment should be assumed for bulk data D73701 003 CE6231 User Manual 77 9 13 5 Header 31 24 23 16 31 0 Header PF HEADER defines the header bytes 0 to 4 added to the start of each USB payload is transmitted first These only used for 2 Transport Stream data 78 CE6231 User Manual Ref D73701 003 9 13 6 HEADER LEN P
72. F header length Register PF HEADER LEN Access Read Write Address C2h BEGUN __ 1 o o _ ___ i ee When EP3_HB_CTRL is 0 automatic CSR reprogramming for endpoint 3 is enabled This is used for high bandwidth isochronous transfers only While enabled CSR_ADDR must always be set to 0x10 DATAO 3 must always contain endpoint 3 CSR data Set EP3 CTRL to 4 3 EP3 HB CTRL 2 for high speed isochronous MPEC2 TS data gt 8MB s Set EP3 HB CTRL to isochronous analog video data When EP3 HB CTRL is enabled the hardware will automatically reprogram bits 31 30 of the endpoint 3 CSR at the start of each microframe to the number of transfers within that microframe defines the length of the MPEG TS USB Payload Header Set this to 2 to 2 0 PF HEADER LEN id with the USB Video Device Class for MPEG2 TS payloads The value can be in the range Setting this to O disables header generation PF HEADER LEN defines the length of the MPEG TS USB Payload Header 5 Note Note that header generation 15 only supported for isochronous transfer mode so if bulk mode 15 used PF HEADER LEN must be 0 D73701 003 CE6231 User Manual 79 9 13 7 PF MISC Register PF MISC Access Read Write Address DEh ___ Syma When bit 7 is 1 entire USB buffer space is used for internal de
73. Intel XScale IPLink Itanium Itanium Inside MCS MMX MMX logo Optimizer logo OverDrive Paragon PDCharm Pentium Pentium Xeon Pentium Xeon Performance at Your Command Pentium Inside skoool Sound Mark The Computer Inside The Journey Inside VTune Xeon Xeon Inside and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries MPEG is an international standard for video compression decompression promoted by ISO Implementations of MPEG CODEOCs or MPEG enabled platforms may require licenses from various entities including Intel Corporation Other names and brands be claimed as the property of others Copyright 2006 Intel Corporation 2 CE6231 User Manual D73701 003 Contents T 13 1 1 Related 13 X 14 001 0 RETI 14 2 1 15 3 21 0 crt 17 3 1 1 PUD OW TONS 18 3 1 2 Hardware TSS OU 18 19 ME unc E 20 6 Apbucaubnn 21 7 9051 PE URNA 22 7 1 merma gata MEMO
74. K hold time 55 Ref D73701 003 CE6231 User Manual 203 14 Package Information 204 DIMENSION LIST FOOTPRINT 2 00 DIMENSIONS REMARK A 1 600 OVERALL HEIGHT Al G7 000 050 STANDOFF 2 1 4000 050 PEG THICKNESS 1 1 T 11 OQ BOUT 150 FOOT LENGTH L L b m 0 200 PROFILE OF MOLD SURFACE coe 0 080 FOOT CGOPLAMARITT 0 080 FOOT POSITION NOTES DESCRIPTION SPECIFICATION 1 GENERAL TOLERANCE _ DISTANCE 0 100 ANGLE 2 MATTE FINISH ON PACKAGE BODY SURFACE um EXPECT EJECTION AND PIN 1 MARKING uy 5 ALL BODY SHARP CORNER RADII 200 UNLESS OTHERWISE SPECIFIED PACKAGE LEADFRAME MISALIGNMENT Y 9 12 PACKAGE MISALIGNMENT X T X 1 127 DRAWING GOES INCLUDE PLASTIC OR METAL PROTRUSION DR CUTTING BURR COMPLIANT TO JEDES STANDARD Mo O2b CE6231 User Manual Ref D73701 003 4x 9 90 10 17 ALL AROUND ALL AROUND 01 10 0040 10 Orc 205 CE6231 User Manual Ref D73701 003 CD Sd xe 4X 206 ALL AROUND 0 20 Min Min qe qu nm A G20 BASE GAGE PLANE 49400 2 DETAIL CE6231 User Manual Ref D73701 003
75. Lock bit value see STATUS 1 register bit 5 to be output on the Status output ap i eee Ce 152 CE6231 User Manual Ref D73701 003 11 15 Interrupts All the interrupt bits in a register are reset when that register is read by the 8051 The interrupt registers are also reset when a new acquisition 15 initiated by writing to a GO register The interrupt bits are not reset during automatic re acquisitions that can occur for example due to loss of byte lock for a relatively long period Interrupt registers do not indicate the current state of the device These reflect the history of events that have occurred since the last read operation of these registers For example it 15 possible for the AGC_ Lock to be high and for the AGC Lock status flag to remain low This indicates the fact that the AGC has locked and subsequently lost lock 11 15 1 0 Register INTERRUPT_0 Access Read only Address m 5 5 OFDM Fail Set when OFDM pilot detection fails during acquisition 6 OFDM Found Set when the OFDM demodulator finds a valid OFDM signal by detecting pilots MG Fail Set if the mode and guard interval parameters search fails MG Search Set when the mode and guard interval parameters search is started after Sym fail occurs Set if symbol timing lock fails during acquisition This indic
76. N maximum packet size 1024 bytes max 3 transfers microframe Endpoint 4 isochronous IN maximum packet size 256 bytes Address Data 0004 02008080 00 00001000000 0001 0000 0001 00 0 0000 0008 04008021 00 00010000000 0001 0000 0001 1110001 000C 600080B2 01 10000000000 0001 0000 0001 0110010 0014 48008084 0100100000000 0001 0000 0001 0110100 0010 600080 3 01 10000000000 0001 0000 0001 0110011 program CSR data must be written to DATAO 3 and register address to ADDR 4 0 Then a 1 should be written to CSR WR SFR AC bit 0 To read a CSR the register address must be written to CSR ADDR 4 0 then 1 written to CSR RD The data can then be read in DATAO 3 After all of the CSRs have been set appropriately APP DONE CSRS should be set to 1 This will clear USBC SET CSRS 180 CE6231 User Manual Ref D73701 003 12 2 10 2 wire bus interface The 6231 has two external 2 wire bus master interfaces CLK1 DATA1 must be connected to the boot EEPROM CLK2 and DATA2 can be connected to the tuner For the two digital channels mode the external demodulator can be connected to and to avoid interfering with the tuner for the internal demodulator There 15 a master 2 wire bus controller inside the CE6231 After RESETB has been released this transfers the 8051 software from the EEPROM to the 8051 Program during this process the 8051 1 held in reset After the software is
77. O LENGTH LENGTH Read Write ATH at ste tt _ The software should write to this register the length in bytes of the current data packet written to ADDR For read commands LENGTH bytes will have been written by the 8051 For write commands EPO LENGTH is the expected length of data to be written by the PC If the PC writes LENGTH incorrect length EPO_CMD_FAILED is set The USB standard guarantees that the exact length of a write command is specified SETUP packet If there is no data section in the command SETUP bytes 7 and 8 are zero then the 8051 does not have to write to this register EPO LENGTH will always be 64 bytes for EPO 8051 DATAMID packets The software should write to this register the length in bytes of the current data packet written to ADDR For read commands EPO LENGTH bytes will have been written by the 8051 For write commands EPO LENGTH is the expected length of data to be written by the PC If the PC sends a different length EPO CMD FAILED is set The USB standard guarantees that the exact length of a write command 15 specified in a SETUP packet If there 15 no data section in the command SETUP bytes 7 and 8 are zero then the 8051 does not have to write to this register EPO LENGTH will always be 64 bytes for EPO 8051 DATAMID packets Caution Note that all transfers to the 8051 RAM are 32 bits eve
78. OFDM _ Bandwidth 61 44 where refers to truncation i e 150 9 is set to 150 It 15 important to note that CTL 15 a one off setting at power up since the clock configuration 15 fixed by hardware and the OFDM bandwidth is usually fixed by national boundaries MCLK CTL does not depend any of the other OFDM parameters For example if the TPS parameters during channel hop changes QAM64 code rate 2 3 to QAM 16 code rate 3 4 then bit rate goes down by a factor of 3 2 3 4 4 6 3 4 Then the MCLK frequency will go down by a factor of 3 4 transparent to the user without any change in MCLK CTL Table 11 11 MCLK control Clock source MHz SR clock MHz FEC clock MHz ____ 0 204 CT 24 19 50 52 00 24 45 00 60 00 24 34 50 55 20 D73701 003 CE6231 User Manual 137 11 10 7 ADC CTL te tt st yt _ ADC calibrate A calibration of the ADC can be requested by writing ADC_CTL 0 from 0 to 1 and back to 0 5 Note It is essential that the ADC is recalibrated whenever the ADC is taken out of the power down state 138 CE6231 User Manual D73701 003 11 10 8 DIS Eth __ o 1d j 1 symbol eea Setting bit 1 will disable RS erro
79. PC write commands If there 1s no data section the software should set EPO 8051 STATUS to 1 This will send a zero length packet during the status stage to indicate that the command was interpreted correctly If there 15 a data section of more than 64 bytes 64 must be written to EPO LENGTH then EPO 8051 DATAMID should be set to 1 This indicates that the following data packet 1 not the final one On receipt of the DATA packet the data will be copied to the Data RAM at the address pointed to by EPO ADDR then the DONE status interrupt bits will be set The 8051 requests the next data packet by setting either EPO 8051 DATAMID or EPO 8051 DATAEND to 1 Alternatively if the data 15 invalid EPO 8051 STALL can be set instead to return a STALL handshake If the data section 15 64 bytes or less the length 15 written to EPO LENGTH then EPO 8051 DATAEND should be set to 1 This indicates that the STATUS stage should follow this packet On receipt of the DATA packet the data will be copied to the Data RAM at the address pointed to by ADDR then the EPO DONE status and interrupt bits will be set The 8051 then sets EPO 8051 STATUS to 1 This will send a zero length packet during the status stage to indicate that the command was interpreted correctly Alternatively if the data 1s invalid EPO 8051 STALL can be set instead to return a STALL handshake in the status stage D73701 003 CE6231 User Manual 171 12 1 3 read comm
80. RF gain control For this tuner therefore a 50 handover point 15 appropriate and both IF LoLim and RF HiLim would be set to about 127 0 7 usually with a small amount of overlap to ensure that there 1 no region of instability The degree of overlap is probably best determined empirically For the purposes of demonstrating the example calculations IF LoLim will be 125 and HiLim will be 129 These values are not neccesarily suitable for use with a real tuner The coefficients KIF and KRF are calculated from the other register settings once these have been determined The crossover point is set as shown Table 11 2 AGC gain setting IF LoLim 90h Sets gain handover point of the IF vn 64 IF LoLim 7 0 AGC range RF_HiLim 91h Sets gain handover point of the RF G 64 RF HiLim 7 0 6h 95h Sets the gain range of the IF AGC U U T TP des 2 EN NA 9 Sets the gain range of the RF AGC U mdi a are 102 CE6231 User Manual Ref D73701 003 Thus using values from previous examples and would be as follows for the IF LoLim and RF HiLim values given above From the first equation in Table 11 2 KIF 64 64 155 38 16383 64 125 57 0x39 and the fourth equation 64 64 204 12 64 129 95 Ox5F Note that internally computed gain value is a 14 bit positive number This may be read from t
81. RR CONI 22 21 0 A a 144 121259 RS UBC D aa 145 11 124 Viterbi error period VIT ERR 146 T4 12 9 EIR 147 clTe EX 148 STATUS 148 TETSZ TATUS akon osea a ay 149 ge E 150 I STATUS enables ied eire Malis Maru nta 151 Tel STATUS EE 151 STATUS INA sect aa deae 152 M ME I II 153 11 15 1 UNO 153 WAZ NINETIES hale hae cece ee ale eo 154 T11 15 9 INTERRUPT bes ud 155 156 11271525 INTERRUPT 157 11 16 INTERRUPT ENABLES uua ot 158 11 16 1 INTERRUPT IENS 158 110 2 INTERRUPT EN oiim ben 159 INTERRUPT 2 rU M 160 11162 INTERRUPT um usu MM A R 161 CHI IDE DISTULIT 162 11 18 Carrier Recovery Loop 163 AFC Ea 163 145102 GMA BW T _ _ __ 164 TEISS
82. This indicates that the SETUP command has been understood It should also be set after the EPO DONE has been received and the 8051 has prepared for the next data packet EPO 8051 DATAMID should be used for all data packets except for the last packet For the last data packet in a transfer EPO 8051 DATAEND should be used instead The 8051 writes one of these bits in response to receiving a UDM STATUS bit to indicate that the software has processed the next stage of the USB command these register bits are reset automatically EPO 8051 STATUS EPO 8051 DATAEND Ref D73701 003 CE6231 User Manual 69 9 12 9 End point 0 control Register Address AGH Ge oe ee Se EE Default 5 9 tt 7 Bit Bitorder Register EP EPO ADDR EPO SETUP ADDR USE BULK Bits 22 20 select the transfer mode for endpoints 2 to 4 Bit 20 is for endpoint 2 bit 21 for 22 2 endpoint 3 and bit 22 for endpoint 4 Set to 1 for bulk mode 0 for isochronous mode 1910 EPO ADDR ADDR contains the base address in 32 bit words where the command DATA will be read from written to EPO SETUP ADDR contains the base address in 32 bit words where the SETUP data 2 words EPO SEIT will be written to It is recommended to leave this address fixed at 0000 70 CE6231 User Manual Ref D73701 003 9 12 10 EP
83. U vectors to the address of the interrupt service routine ISR associated with that interrupt as listed in Table 9 4 The CPU executes the ISR to completion unless another interrupt of higher priority occurs Each ISR ends with an RETI return from interrupt instruction After executing the RETI the CPU returns to the next instruction that would have been executed if the interrupt had not occurred Table 9 4 Interrupt Natural Vectors and Priorities interrupt Description Natural Priority Interrupt Vector Sep USBuspendinterupt 0 an _ mon mo ____ 2 o mts e Timer tinerupt 4 Tez or EXF2 6 32h _ mg 4 mss 9 4 An ISR can only be interrupted by a higher priority interrupt That is an ISR for a low level interrupt can be interrupted only by a high level interrupt An ISR for a high level interrupt can be interrupted only by a USB suspend interrupt The 8051 always completes the instruction in progress before servicing an interrupt If the instruction in progress 15 RETI or a write access to any of the IP IE EIP or EIE SFRs the 8051 completes one additional instruction before servicing the interrupt 9 11 2 Interrupt Masking The EA bit in the IE SFR IE 7 is a global enable for all interrupts except the USB suspend interrupt When EA 1 each interrupt is enabled maske
84. age current can be eliminated by disconnecting the 1 8V supplies to the demodulator CVDD PLL PLLVDD and ADC AVDD and DVDD and the 3 3 V ADC supply AVD33 The demodulator and USB 8051 logic VDD supplies have been kept separate for this purpose The SLEEP pin output or a general purpose port can be used to disconnect these supplies during a suspend If this feature is used the 8051 should hold the demodulator in reset while the supplies settle by writing 1 to 5 5 CTRL bit 5 Separate from the suspend mode the demodulator contains 3 registers to save power when the demodulator is not in use When CE6231 EN bit 0 1 low the demodulator PLL is powered down and the demodulator clocks are disabled When 6231 EN bit 1 is low the 10 bit ADC is powered down When 0 bit 7 is low the 7 bit ADC 15 powered down It is recommended to power down 2 ADCs first before powering down the demodulator PLL 12 6 Infra Red detector The infra red detector should be connected to pin IRDI A rising edge on IRDI will set interrupt INT2 a falling edge will set INTO N These interrupts together with the 8051 timers can be used to measure the pulse widths on the infra red symbols The 8051 can decode the pulse sequence into a keypad code which can be sent over interrupt endpoint 1 to the PC If the device is configured as remote wakeup capable remote wakeup using pin IRDI should work automatically without requiring software intervention 19
85. aion number R 8t88h Reseved 4242 88 amp 8Dh Reseved 90 AGCIFLOIM 91h AGCRFHLM 1 RW 92h AGCIF RW Bh AGCIFMN _ O 00 RW 94h AGCREMAX 95 RW __ AGCKRF 081 RW 97 CBh Reseved CD DBh Reserved DZDBh DEEOh Reserved 042 EZE9h Reseved EBFFh Reserved 1 11014 2 1 These registers are not reset by demodulator full software reset These are reset to default values only by a hardware reset or SFR DF bit 4 Refer to 11 19 98 CE6231 User Manual Ref D73701 003 11 2 Automatic Gain Control 11 2 1 System description Figure 10 CE6231 AGC internal system outline Koy Register values Interrupt Status amp Acquisition Lock detect EFFE Mo ock Panat amp interrupt ce a Interrupts IF in timing Lock 1 ADC 9 _ Status bit Difference Non Linearity ADC cicpk IF Max 7 0 _IF_Min 0 c L KIF 7 0 IF AGC outT Sigma Gain 13 0 l BW gain 3 0 Accumulate RF HiLIm 7 0 BW _lock_red 2 0 7 0 KRF 7 0 x64 The output of the ADC is range 512 to 511 Thi
86. al Ref D73701 003 12 3 4 2 Dual Address Byte Format This format is used when ADFMT is tied high An example device is the 2464 8K x 8 EEPROM The command sequence for reading data starting at address 0 is shown in Figure 18 Figure 18 Dual address byte format 12 3 5 EEPROM data format The first 2 bytes in the EEPROM contain configuration settings The 8051 code begins at EEPROM address 0002 EPROM address 0000 B7 SELF PWR B6 TWB SPEED B5 WKUP CAP B4 B0 PROG LEN 13 9 EPROM address 0001 7 PROG LEN 8 1 The SELF PWR should be set to if system is self powered 0 if system is USB powered TWB SPEED should be set to 1 for 330 kHz 2 wire bus speed 0 for 60 kHz speed WKUP CAP should be set to 1 if the device is remote wakeup capable PROG LEN defines the length of the code in the EPROM PROG LEN 0 is always 0 Hence for a code size of 1250h bytes USB powered 330 kHz 2 wire bus speed and remote wakeup capable EEPROM address 0000 would be 69h and address 0001 would be 28h The program would be stored in addresses 0002h to 1251h which would be transferred to Program RAM addresses 0000h to 124Fh AS Caution PROG 0 is in the CE6231 is always 0 The CE6231 will always load an even number of bytes Ref D73701 003 CE6231 User Manual 185 12 3 6 Start up sequence e Pu SA ucc Apply a hardware reset After this the 8051 will be held in reset and the demodulator will be powe
87. alling edge of SCK 15 used to sample data otherwise the rising edge of SCK 15 used 12 7 3 125 application note The 125 interface on the CE6231 will work without modification with an 125 data width of 16 bits or less adjustment to the data alignment is necessary if the data width 15 more than 16 bits The 16 most significant bits of the data must be generated in the position expected for the 16 least significant data bits The figure shows the modification required for an I2S data width of 24 bits per channel assuming no extra padding bits The signal SD DEL is the normal SD signal delayed by 8 cycles This should be used for the CE6231 SD input pin An alternative would be to delay WS by 16 cycles the left and right channels would be swapped over in this case Figure 23 125 data re alignment SCK Right Channel Left Channel TE Right Channel Left Channel Ref D73701 003 CE6231 User Manual 195 Figure 24 125 data format Right Channel Left Channel Right Channel i M 4 M The ITU 656 data will be transferred using USB endpoint 3 Bit 7 of PF MISC must be set to 0 to enable external data transfer The data can be transferred using either isochronous or bulk transfers Isochronous transfers provide pre allocated USB bandwidth hence should prevent CE6231 buffer overflows due to bus starvation Unfortunat
88. and Clock Synchronisation CE6231 uses digital timing recovery and this eliminates the need for an external VCXO The ADC samples the signal at a fixed rate for example 45 0 MHz Conversion of the 45 0 MHz signal to the OFDM sample rate is achieved using the time varying interpolator The OFDM sample rate is 64 7 MHz for 8 MHz and this is scaled by factors 6 8 and 7 8 for 6 and 7 MHz channel bandwidths The nominal ratio of the ADC to OFDM sample rate is programmed in CE6231 register defaults are for 45 MHz sampling and 8 MHz OFDM The clock recovery phase locked loop the CE6231 compensates for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock 10 6 Carrier Frequency Synchronisation There can be frequency offsets in the signal at the input to OFDM partly due to tuner step size and partly due to broadcast frequency shifts typically 1 6 MHz These are tracked out digitally up to 1 MHz in 2 K and 8 K modes without the need for an analogue frequency control AFC loop The default frequency capture range has been set to 286 kHz in the 2 K and 8 K mode However these values can be increased 1f necessary by programming an on chip register RANGE It is recommended that a larger capture range be used for channel scan in order to find channels with broadcast frequency shifts without having to adjust the tuner After the OFDM module has locked the AFC will have been previously disabled the freque
89. ands If there is a data section of more than 64 bytes the 8051 must write the first data packet to the Data RAM at the address pointed to by ADDR and 64 must be written to LENGTH then EPO 8051 DATAMID should be set to 1 This indicates that there 1s another data packet to follow After transfer of the data the DONE status and interrupt bits will be set The 8051 writes the next data packet to the address pointed to by EPO ADDR sets EPO LENGTH then sets either EPO 8051 DATAMID or EPO 8051 DATAEND to 1 If the data section is 64 bytes or less the 8051 must write the data to the Data RAM at the address pointed to by EPO ADDR and set LENGTH then EPO 8051 DATAEND should be set to 1 This indicates this is the final data packet After transfer of the data the DONE status bit will be set but not DONE interrupt bit because there is nothing for the 8051 to do After the STATUS stage is received the EPO STATUS status and interrupt bits are set to indicate that the PC received the data successfully Note The 8051 may have less data than requested by the PC This is indicated by a short packet or for a multiple of 64 bytes a zero length data packet In this latter case the software should set 8051 DATAEND for the final 64 byte packet The hardware will automatically send a zero length packet in response to a further data request from the PC The register bits in 8051 CMD are all autom
90. anual Ref D73701 003 11 121 RS ERR PER 0 1 Read Write Symbol RS ERR PER 1 RS ERR PER 0 Address ba papa 7 RS Per See equation below This period is defined in terms of 1024 RS blocks that is a value of 1 this 16 bit register corresponds to 1024 RS blocks Reed Solomon decoder measures the bit errors at the Viterbi decoder output Hence this period has to be chosen such that the number of bit errors during this time is fairly large when the Viterbi output BER correspond to the QEF point that is 2 0e 4 The default setting of 0x4D corresponds to 78 848 RS blocks or 128 679 936 input bits If the BER is 2 0e 4 then the expected number of bit errors is 25 735 bits If the OFDM parameters are 8 MHz 2 K Guard 1 32 non hierarchical QAM64 code rate 2 3 there will be 1 008 RS packets an OFDM superframe 62 832 ms The time to collect this number of RS blocks is hence about 5 seconds The procedure recommended for Viterbi output BER computation 1s as follows Wait for CE6231 FEC to lock bit 5 of STATUS_0 register Keep polling the RS Err Per Int interrupt flag bit 7 of INTERRUPT 1 until it is 1 Repeat above several times to discard first few RS BER counts Then read the Reed Solomon bit error count RS ERR 2 1 0 Read the uncorrectable block count RS UBC 1 0 as well If RS UBC 1 0 is non zero the
91. ates the absence of a OFDM signal with 3 Sym Fail given mode and guard The CE6231 will then begin searching for mode and guard this can be disabled The fact that this search has started is shown by the interrupt bit SEARCH Sym Fail signal will only be generated if mode and guard are forced Set when symbol timing lock is initially established during acquisition though the pilots have not 2 Sym Lock been detected at this stage The mode and guard that have been detected can now be read from the TPS CURRENT register 1 AGC Fail Set if the AGC fails to lock after the interval The No Lock period be programmed in steps of 50 ms from 50 ms up to 800 ms The default has been set to 200 ms Lock Set when AGC lock occurs Note This register 1 reset when read Tip If the mode and or guard search is unsuccessful the MG SEARCH FAILED interrupt will be set This indicates the absence of an OFDM signal The device will continue to search for a mode and guard but the software can abort this search and go to the next channel Ref D73701 003 CE6231 User Manual 153 11 15 2 INTERRUPT 1 Register INTERRUPT_1 Access Read only Address 01h _ loa _ Symbol Full Lock Set when all the stages of the device are locked see also bit 6 of STATUS 0 If Retry Start occurs then this bit will be set if the alternative algorithm does not improve the sig
92. atically reset to 0 by the hardware after they have been processed After the 8051 sets 8051 STALL a STALL response will be sent to the PC for each subsequent data stage and the status stage automatically without interrupting the 8051 If a data packet 1 corrupted the hardware will wait for re transmission without indicating to the 8051 1 the 8051 does not need to know about corrupted data packets If the length of the data sent by the PC is different to that set in EPO LENGTH the CMD FAILED status and interrupt bits will be set instead of DONE The hardware will automatically send a STALL response for the remaining stages of the command 172 CE6231 User Manual Ref D73701 003 12 2 Endpoint 0 example transfer sequences 12 2 1 Class or Vendor command with no data section 22255250042 2 SETUP packet received USB controller returns ACK USB controller writes 8 bytes to EPO SETUP ADDR USB controller sets EPO SETUP status and interrupt STATUS stage read returns NAK 0 to n occurrences 8051 sets 8051 STATUS STATUS stage read returns zero length packet Or SETUP packet received USB controller returns ACK USB controller writes 8 bytes to EPO SETUP ADDR USB controller sets SETUP status and interrupt STATUS stage read returns NAK 0 to n occurrences 8051 sets 8051 STALL STATUS stage read returns STALL Ref D73701 003 CE6231 User Manual 173 12 2 2 Xs
93. ation is hierarchical the OFDM outputs both high and low priority data streams Only one of these streams 1s FEC decoded but the FEC can be switched from one stream to another with minimal interruption to the transport stream Figure 8 OFDM demodulator diagram 2A gt m Channel filter __Interpolate FFT conversion 2 AGC out CPE correction Clock carrier amp symbol Chanel equaliser timing recovery loops IF in ADC T De mapper TPS SNR p De interleaver PLL Demod HP LP A control stream y 050 FSMs Tuner gt Channel scan Acquisition amp tracking RF level Host I ADC 2 lt The FEC module shown in Figure 9 consists of a concatenated convolutional Viterbi and Reed Solomon decoder separated by a depth 12 convolutional de interleaver The Viterbi decoder operates on 5 bit soft decisions to provide the best performance over a wide range of channel conditions The trace back depth of 128 ensures minimum loss of performance due to inevitable survivor truncation especially at high code rates Both the Viterbi and Reed Solomon decoders are equipped with bit error monitors The former provides the bit error rate BER at the OFDM output The latter 1s the more useful measure as it gives the Viterbi ou
94. ault Access EN STATUS E6 E7h Reseed EU EG Extended interrupt enable ta Eh _E9 EFh Fm B On RW Reserved _F9 FFh Reserved EEUU Ref D73701 003 CE6231 User Manual 27 9 SFR descriptions This section presents the special function registers information 9 1 SP Stack Pointer Stack Pointer Read Write nun __ j o o o 1 1 1 Symbo Points to next available stack location This is the 8051 Stack Pointer The internal RAM used for stack storage is 256 bytes The Stack Pointer Register is 8 bits wide It is incremented before data is stored during PUSH and CALL executions While the stack may reside anywhere in on chip RAM the Stack Pointer is initialized to 07h after a reset This causes the stack to begin at location O8h 28 CE6231 User Manual Ref D73701 003 9 2 PSW Program Status Word Read Write 7 Carry flag Bit 7 is set to 1 when last arithmetic operation resulted in a carry during addition or borrow during subtraction otherwise cleared to 0 by all arithmetic operations Auxiliary carry flag Bit 6 is set to 1 when last arithmetic operation resulted in a carry into during addition or borrow from during subtraction the high order nibble otherwise cleared to 0 by arithmetic operations ENL _ User flag 0 Bit
95. control p 1 Fall time control xe qe eee Fall time control pee umm Fall time control EEPROM address format CMOS Crystal SS Low phase noise oscillator cell 24 CMOS S Lus ome ____ pens EUM 8 16 17 18 7 0 eo Purpose Ports mau Tristate 1 20 23 pull ia AGC Omedun ____5 16 25 2 RF should be tied to ground Open drain when not used RFLEV RF AGC level indicator input Analog Conr 29 SLEEP Suspend mode power down for rest of CMOS 9 5 1 PCB High suspend low powered 69 RESETB Active low reset pin low reset pin XL Infrared Fg 180 ______ Infrared input input ao _________ 47 USBP USBpostivedaa VO Differential Analog J 48 USBM X USBnegaivedaaa O Differential Analog 46 RESIKS X USBpuluprsstr 33 USB bias resistor o do emi pins PLL and supply LH PLLGND PLL PLL ground supply supply l amp gue o 26 56 79 15 5764 CUVDD_ USB core logic power supply O s 18 e 7 10 12 14 vss LogcCoreand Ogound s D73701 003 CE6231 User Manual 17 61 72 78 Pin Name Pindescrpion 1 0 V
96. d by its individual enable bit When EA 0 all interrupts are masked The only exception 15 the USB suspend interrupt which 15 not affected by the EA bit When ESUSPI 1 the USB suspend interrupt 15 enabled regardless of the state of the EA bit Table 9 5 Summary of interrupt sources flags enables and priority control Description Priority Control mon Exemalinterypt0 _1 Po Ref D73701 003 CE6231 User Manual 45 9 11 3 Interrupt Priorities There are two stages of interrupt priority assignment interrupt level and natural priority The interrupt level highest high or low takes precedence over natural priority The USB suspend interrupt if enabled always has highest priority and 1 the only interrupt that can have highest priority All other interrupts can be assigned either high or low priority In addition to an assigned priority level high or low each interrupt has a natural priority as listed in Table 9 4 Simultaneous interrupts with the same priority level for example both high are resolved according to their natural priority For example if int n and int2 both programmed as high priority n takes precedence Once an interrupt is being serviced only an interrupt of higher priority level can interrupt the service routine of the interrupt currently being serviced 46 CE6231 User Manual D73701 003 Figure 7 Interrupts used by the 6231
97. d number of 15 and P O if the Accumulator contains an even number of 1s Thus the number of 1s in the Accumulator plus P 15 always even Two bits in the PSW are uncommitted and maybe used as general purpose status flags Table 9 1 Register bank selection Bits 4 3 RS1 RSO Bank selected 0 Register bank 0 addresses OOh 07h 5 01 Register bank 1 RAM addresses 08h OFh Register bank 2 RAM addresses 10h 17h Register bank 3 RAM addresses 18h 1Fh Ref D73701 003 CE6231 User Manual 29 9 3 Accumulator Read Write I s _ Symbo This is accumulator register 30 CE6231 User Manual Ref D73701 003 9 4 register Reiter Read Write FOh Symbo The register is used during multiply and divide operations For other instructions it can be treated as another scratch pad register Ref D73701 003 CE6231 User Manual 31 9 5 Register Read Write 92h Symbo This register contains upper address byte used during MOVX A and MOVX A 7 0 MPAGE opcodes 32 CE6231 User Manual Ref D73701 003 9 6 PCON Power Control Read Write __ 1 1 Rem LL 75 me ______ when serto 1 the 8051 meme 2 Th
98. dpoints f Note Note that the LENGTH PF INT MAX LENGTH PF EXT MAX LENGTH and I28 MAX LENGTH registers define the actual transfer sizes for endpoints 1 to 4 hence the maximum packet sizes here do not matter much provided that they are at least as large as those values For example if PF INT MAX LENGTH is 188 and endpoint 2 config 1 set to 1024 bytes maximum the maximum transfer size for endpoint 2 will be 188 bytes 12 2 8 High bandwidth isochronous transfers Endpoint 3 can utilise high bandwidth isochronous transfers to achieve data rates greater than 1024 bytes per microframe The procedure described in this section must be used to enable high bandwidth isochronous transfers on endpoint 3 1 EP HB CTRL must be set to 0 2 The CSRs must be programmed as shown above Endpoint 3 should be programmed last 3 HB CTRL should be set to the maximum number of isochronous transfers per microframe see below 4 While HB CTRL 15 non zero ADDR must contain 0x10 CSR DATAO to CSR DATA3 must hold the appropriate data for endpoint 3 which should be the case since endpoint 3 was programmed last If any subsequent changes to the CSRs are necessary EP3 HB CTRL must be set to 0 first EP3 HB CTRL Purpose 0 High bandwidth isochronous transfers are disabled 2 Maximum of 2 transfers microframe Use this for external DVB data of greater than 8 MB s e g 45MBaud DVB S 3 Maximum of 3 trans
99. e CE6231 provides two power saving modes idle mode and stop mode Idle mode Exit idle mode by interrupt or reset Stop mode Exit stop mode by power on reset only Ref D73701 003 CE6231 User Manual 33 9 7 Clock Control Read Write ret Symbol me i eea This register sets division ratio of the 30MHz clock and thus determines clock to be used for timers 1 and 2 ej Note Bits 2 0 should be set 0 This should be done as the first operation of the user software 34 CE6231 User Manual D73701 003 9 8 SPC Special function 8Fh _ Symbo Ree When bit O is 1 instructions that normally write to Data RAM write to Program RAM instead When bit O is O these opcodes access the Data RAM This affects MOVX DTPR and MOVX Ri opcodes This feature can be used to provide software modifications via the USB Care must be taken if MOV X opcodes are used in interrupt service routines D73701 003 CE6231 User Manual 35 9 9 Dual Data Pointers The CE6231 employs dual data pointers to accelerate data memory block moves The standard 8051 data pointer DPTR 15 a 16 bit value used to address external data RAM or peripherals The CE6231 maintains the standard data pointer as DPTRO at SFR locations 82h and 83h It is not necessary t
100. e frame using a truncated version of a systematic 255 239 Reed Solomon code The corresponding 204 188 Reed Solomon decoder is capable of correcting up to eight byte errors in a 204 byte frame It may also detect frames with more than eight byte errors In addition to efficiently performing this decoding function the Reed Solomon decoder in CE6231 keeps a count of the number of bit errors corrected over a programmable period and the number of uncorrectable blocks This information can be used to compute the post Viterbi BER 10 19 De scrambler The de scrambler de randomizes the Reed Solomon decoded data by generating the exclusive OR of this with a pseudo random bit sequence PRBS This outputs 188 byte MPEG transport packets The TEI bit of the packet header will be set if required to indicate uncorrectable packets 94 CE6231 User Manual Ref D73701 003 10 20 Differences from CE6353 The CE6231 has register The CE6231 has no INTERRUPT 3 register The CE6231 has no INTERRUPT ENABLE 3 register The CE6231 has no STATUS 2 register In the register STATUS 1 bits 3 0 are reserved In the register STATUS ENABLE 41 bits 3 0 are reserved The register INPUT FREQ 0 has a different default value In CE6231 bits 4 2 0 are reserved in OP CTL 0 The CE6231 has no OP CTL 1 register The register PLL 0 has a different default value D73701 003 CE6231 User Manual 95 11 Demodulator Registers 111 D
101. e oO Reserved set only to default Capt_Range The Capt_Range 2 0 value defines the frequency capture range given in kHz in Table 11 5 Ref D73701 003 CE6231 User Manual 117 11 5 2 AFC CTL Register AFC_CTL Access Read Write Address __ o j 1 _ Symbo E This bit should be set to 0 to disable the AFC before searching for channels to ensure that when AFC En reading frequency offset details the AFC does not affect the offset readings After tuning to a channel using the optimum frequency setting the AFC should be re enabled 118 CE6231 User Manual D73701 003 11 5 3 FREQ OFF 2 1 0 Ppp Default T T 1 ET EE 15 o 23 16 15 8 FREQ OFFSET Provides information on the frequency offset at the input to CE6231 The sources of frequency offset of the input signal have been described in the section describing the register CAPT RANGE After the OFDM signal has been captured that 1s after the OFDM found bit B2 in STATUS 0 register has gone high the FREQ OFFSET 2 1 0 read register triplet contains this frequency offset as given by FREQ OFF 64000 ChanBW Carrier offset kHz 2048 3 2048 mode 8192 7 2048 3 2048 mode 8 where mode is 0 for 2K and 1 for 8K The ChanBW is 6 7 or 8 MHz Note Note that FREQ OFFSET 15 a 24 bit two s complement
102. eading and writing of the USB Controller Control and Status Registers CSRs To write to a CSR the software should write to CSR ADDR and 5 DATAO to CSR DATA3 then set CSR WR To read from a CSR the software should write to CSR ADDR then set RD data can then be read from DATAO to CSR DATA3 After receiving a USBC SET CSRS interrupt the 8051 should write the new CSR data then set APP DONE CSRS Note 3 bits are self resetting 72 CE6231 User Manual Ref D73701 003 9 12 13 CSR_ADDR Register CSR_ADDR Access Read Write Address ADh at ste tt sty ts _ Symbo APP SETDESC SUP When APP SETDESC SUP is set to 1 this enables Set Descriptor USB commands to 5 passed through to the 8051 for processing When set to 0 a STALL response is sent when a Set Descriptor command is received CSR ADDR CSR_ADDR selects the CSR for writing or reading by the 8051 CSR ADDR selects the CSR for writing or reading by 8051 Address CSR to be written to 00 SCA 04 Endpoint 0 Configuration Register 08 Endpoint 1 Configuration Register OC Endpoint 2 Configuration Register 10 Endpoint 3 Configuration Register 14 Endpoint 4 Configuration Register When APP SETDESC SUP is set to 1 this enables Set Descriptor USB commands to be passed through to the 8051 for processing When set to 0 a STALL response 15 sent when a Set Descriptor command is received 9 12 14 CSR DATA
103. ed by default Ref D73701 003 CE6231 User Manual 111 11 2 17 1 0 1 Address PCE E db Bitoder Symbo Reemi These two read only registers form a 14 bit register which gives the IF gain fed back to the analogue IF Gain front end by the CE6231 This gain value gives an indication of the signal level in the analogue front end 112 6231 User Manual Ref D73701 003 11 2 18 RF LEVEL 1 mod RF LEVEL RF signal level Provides measurement of the RF level hence the signal strength if the RF level pin is connected to the RF AGC this is usually controlled exclusively by the RF tuner Although this is not a part of the AGC circuitry it 1s included here because the reading will usually be associated with the AGC if RF level pin is connected to the RF AGC Some low cost can tuners require very high load impedances on their RFAGC voltage output pin gt 5 This necessitates the use of a simple transistor buffer circuit as detailed in Figure 14 If the tuner can directly drive a 1 impedance direct connection can be made instead Figure 14 RF level input buffer D73701 003 CE6231 User Manual 113 11 3 IF to Baseband Conversion The first operation in the OFDM demodulator 1 to convert the real valued IF signal into a com
104. eft channel LS Byte Byte 5 Left channel MS Byte Byte 6 Right channel LS Byte Byte 7 Right channel MS Byte Byte 8 Left channel LS Byte Byte 1 Right channel LS Byte Byten Right channel MS Byte 196 CE6231 User Manual Ref D73701 003 12 8 Example USB register settings Example 1 CE6231 with 2 PIDs 0x0560 and 0x06C1 generating isochronous data that is not packet aligned CSRs 000C 600080B2 This sets endpoint 2 as isochronous IN with maximum packet size of 1024 bytes transfer per microframe in configuration 1 interface 0 alternate setting 1 Data RAM 0048 60 0049 05 004A Cl 004B 06 SFR settings 00 EP USE BULK 0 B4 04 PID INT MAX 2 1 7 00 9 04 INT LENGTH 1024 bytes 2 20 HEADER LEN 0 no header DE PKT DIS 1 B2 2d PF INT353 1 INT FILT DIS 0 Example 2 CE6231 with 4 PIDs 0x101 0x102 0x103 0x104 generating bulk data CSRs 000C 10008002 This sets endpoint 2 as bulk IN with maximum packet size of 512 bytes in configuration 1 interface 0 alternate setting 1 Data RAM 0048 01 0049 01 004A 02 004B 01 0048 03 0049 01 004A 04 004B 01 D73701 003 CE6231 User Manual 197 SFR settings 10 EP USE BULK 1 B4 0C PID INT 4 1 B7 00 B9 02 INT MAX LENGTH 512 bytes C2 20 PF HEADER LEN 0 no header DE DO PKT DIS 1 B2 21 PF INT353 EN 1 PF INT FILT DIS 0 Example 3 CE6231 with external DVB demodulator
105. ely the ITU 656 data rate 27 5 15 higher than the maximum rate for an isochronous endpoint 24 MB s To reduce the data rate to less than the isochronous maximum the horizontal blanking interval samples are discarded when bit 5 of PF MISC is set If isochronous transfers are used the instructions given in section 12 2 8 must be followed There may be teletext data within the horizontal blanking interval If the user wants all of the ITU 656 samples bulk USB transfers must be used for endpoint 3 and bit 5 of PF MISC must be reset The ITU 656 data in a 625 line system has 1728 bytes per line These consist of 1440 active video bytes and 280 bytes of horizontal blanking data separated by 4 byte timing codes When PF 656 HBLANK DEL is set the 280 blanking bytes per line are skipped so that each line gives 1448 bytes active video and timing codes When PF 656 HBLANK DEL is 0 all 1728 bytes are transferred The data 1 not aligned to the USB transfers so the PC software must scan for the timing codes to recover the synchronization The 125 data will be transferred using USB endpoint 4 The 125 data is truncated or zero extended to 16 bits per channel if necessary The data is then transferred as groups of 4 bytes per audio sample The transfer length will always be a multiple of 4 bytes The data format 15 shown below Byte 0 Left channel LS Byte Byte 1 Left channel MS Byte Byte 2 Right channel LS Byte Byte 3 Right channel MS Byte Byte 4 L
106. emodulator Register Summary Table Table 11 1 Demodulator Registers Address Map Address Symo Default Access 00h INTERRUPTO OFDM interrupts R Oth INTERRUPT 1 Controller interrupts 02h INTERRUPT2 FECintempts 03h Reseved __ ___ 04h INTERRUPT 4 Othercontroller interrupts 05h INTERRUPT 5 TPS interrupts 06h STATUSO OFDM and FEC status 1 1 R Oi p statusi FG tuner conte status Reserved 08h _ RR EI OA o GAIN 1 AGC IF total gain 14 bit GAIN 0 0 001 Reseved RF LEVEL RF level indicator 7 bit Selectable signal noise ratio monitor RS ERR CNT 2 RS ERR CNT 1 Reed Solomon error counter 24 bit RS ERR CNT 0 RS UBO ee Reed Solomon uncorrected block count 16 bit RS UBC 0 Reseved 0 FREQ OFFSET 2 FREQ OFFSET 1 Frequency offset 24 bits FREQ OFFSET 0 1B 1Ch Reseved 0 1 Received TPS bits 16 bits TPS RECEIVED_0 TPS CURRENT 1 TPS bits used by CE6231 16 bits 20h TPS CURRENT_0 WOODEN TPS cell identifier 16 bits TPSCELL TPS MISC DATA 2 TPS MISC DATA 1 TPS length frame number and reserved bits 24 bits TPS MISC _0 96 CE6231 User Manual Ref D73701 003
107. enabled bit in INT4A or INT4B is set When 0 the ISR is disabled 4 EX3 When bit 1 is 1 this enables the INT3 N interrupt The interrupt service routine is called when the demodulator interrupt occurs When 0 the ISR is disabled EX2 When bit O is 1 this enables the INT2 interrupt The interrupt service routine is called on rising edge of IRDI When 0 the ISR is disabled This register enables or disables the interrupts in the 8051 core 7 Note This register is not part of standard 8051 architecture Refer to Table 9 3 CE6231 internal event interrupts 50 CE6231 User Manual Ref D73701 003 9 11 8 EIP Extended Interrupt Priority Register Read Write ___ 1 o o _ 000002 When bit 3 is 1 INT5 N is a high priority interrupt when 0 INT5 N is low priority When bit 2 is 1 INT4 is a high priority interrupt when 0 INT4 is low priority When bit 1 is 1 INT3_N is a high priority interrupt when 0 INT3_N is low priority P2 When bit 0 is 1 INT2 is a high priority interrupt when 0 INT2 is low priority This register sets the interrupt priority level in the 8051 core 5 Note This register is not part of standard 8051 architecture Refer to Table 9 3 CE6231 internal event interrupts D73701 003 CE6231 User Manual 51 9 11 9 IE Interrupt Enable Reiter Read Write
108. errupt flag bits The 8051 samples external interrupts once per instruction cycle at the rising edge of clk at the end of cycle C4 The intO n and intl n signals are both active low and can be programmed through the ITO and IT1 bits in the TCON SFR to be either edge sensitive or level sensitive For example when ITO 0 intO n 15 level sensitive and 8051 sets the flag when pin is sampled low When ITO 1 110 is edge sensitive and the 8051 sets the flag when int0_n pin is sampled high then low on consecutive samples The USB suspend Susup int interrupt 15 active high and sampled once per instruction cycle The USB suspend interrupt is level sensitive 9 11 5 Interrupt Latency Interrupt response time depends on the current state of the 8051 The fastest response time is five instruction cycles one to detect the interrupt and four to perform the LCALL to the ISR The maximum latency thirteen instruction cycles occurs when the 8051 is currently executing an RETI instruction followed by a MUL or DIV instruction The thirteen instruction cycles in this case are one to detect the interrupt three to complete the RETI five to execute the DIV or MUL and four to execute the LCALL to the ISR For the maximum latency case the response time 15 13 x 4 52 clock cycles 48 CE6231 User Manual Ref D73701 003 9 11 6 EXIF Extended Interrupt Flags Read Write 91h adi ats ICE sts ts ts
109. ese limits Extended operation outside these limits might adversely affect device reliability 13 2 Absolute Maximum Ratings Table 13 2 Absolute maximum ratings Symbol Parameter Min Max Units Power supply voltage periphery Vo Voltage on input pins 3 3 V rated umeontmpraue s o Note Stresses exceeding these listed under absolute maximum ratings may induce failure Exposure to absolute maximum ratings for extended periods may reduce reliability Functionality at or above these conditions is not implied D73701 003 CE6231 User Manual 201 13 3 DC Electrical Characteristics Table 13 3 DC electrical characteristics Symb Parameter Conditons Pins Min Typ Max Units VDD VDD Operating voltage periphery 3 44 347 core 2 171 18 189 1002 Supply current 171 CVDD 189 1885 a IsusP Suspend supply current Host computer 95 UA CE6230 disconnected IsusP Suspend supply current Host computer 295 SYSTEM connected Outputs sumaa _ 3 14 lt VDD lt 3 47 3 14 lt VDD lt 3 47 eae 3 14 lt VDD lt 3 47 IOL 6mA GPP 7 0 CLK1 04 3 14 lt VDD lt 3 47 CLK2 DATA DATA2 AGC1 AGC2 Output capacitance F GPP 7 0 CLK1 3 6 pF Not including track CLK2 DATA1 DATA2 AGC1 AGC2 Output leakage current tri state 1 Sj I
110. fers per microframe Use this for external analog data at 22 625 MB s 12 2 9 Example CSR settings a Configuration 1 Interface 0 alternate setting 1 Endpoint 1 interrupt IN maximum packet size 256 bytes Endpoint 2 bulk IN maximum packet size 512 bytes Endpoint 3 bulk IN maximum packet size 512 bytes Endpoint 4 bulk IN maximum packet size 512 bytes Address Data 0004 02008080 00 00001000000 0001 0000 0001 00 0 0000 0008 080080F1 00 00100000000 0001 0000 0001 11 1 0001 D73701 003 CE6231 User Manual 179 000C 10008002 00 01000000000 0001 0000 0001 10 1 0010 0010 10008003 00 01000000000 0001 0000 0001 10 1 0011 0014 10008004 00 01000000000 0001 0000 0001 10 1 0100 5 Configuration 2 Interface 0 alternate setting 1 Endpoint interrupt IN maximum packet size 80 bytes Endpoint 2 isochronous IN maximum packet size 940 bytes Endpoint 3 bulk IN maximum packet size 512 bytes Endpoint 4 isochronous IN maximum packet size 192 bytes Address Data 0004 02008100 00 00001000000 0001 0000 0010 00 0 0000 0008 02808171 00 00001010000 0001 0000 0010 11 1 0001 000C 50608132 0101110101100 0001 0000 0010 0110010 0010 10008153 00 01000000000 0001 0000 0010 10 10011 0014 46008134 01 00011000000 0001 0000 0010 0110100 Configuration 1 Interface 0 alternate setting 1 Endpoint 1 interrupt IN maximum packet size 128 bytes Endpoint 2 isochronous IN maximum packet size 1024 bytes Endpoint 3 isochronous I
111. gain to be controlled with a voltage in the range 0 5 to 2 0 V and the RF gain with a voltage in the range 0 25 to 4 0 V It 15 likely that a stable 5 0 V supply will be available so this would be a good choice for the VREFRF supply and if a stable 3 3 V supply 15 available this would be a good choice for the VMAXIF supply Rearranging the first equation in Table 11 1 VREFIF 3 3 V IF Max 2 0 3 3 16383 64 155 Ox9B and the second equation IF Min 0 5 3 3 16383 64 38 0x26 D73701 003 CE6231 User Manual 101 From third equation in Table 11 1 VREFRF 5 0 V 4 0 5 0 16383 64 204 and the fourth equation RF_Min 0 25 5 0 16383 64 12 11 2 4 Setting the IF RF crossover point Four registers need to be set IF LOLIM KIF and KRF IF LoLim and HiLim are used to set GIF Min and GRF Max of Figure 12 and are coefficients that are dependent on gain and voltage limits of Figure 12 These are used to linearly scale the RF and IF gain ranges into corresponding voltage ranges Figure 13 System gain v RF signal level A Gain Overlap range Increasing RF signal level IF LoLim and HiLim are determined from the tuner s characteristics and possibly test results For instance typical tuner may cover the input level range from 80 dB to 45 dB using the IF gain control and the range from 45 dB to 10 dB using the
112. he Force Mode and Force Guard bits of this register are used to control the blind acquisition of transmission mode and guard ratio respectively By default the mode and guard are forced to the values specified in the TPS GIVEN 1 O register If one or both the above mentioned bits are set to 0 then mode and or guard search is initiated starting with the mode and guard values in TPS GIVEN 1 0 ule Y Tip When carrying out a channel search it is recommended that the initial mode and guard be set to zero Ref D73701 003 CE6231 User Manual 133 11 10 3 CHIP ID __ o 1 1 o j 1 _ CHIP ID This register has a unique number which defines the CE6231 134 CE6231 User Manual D73701 003 11 10 4 RESET Read Write ats te tt Symbo 7 Full Resets all the circuits and registers in the demodulator section except as noted in the register map to their default values 6 Pat Resets all the circuits in the demodulator section except read write registers 50 Reseved 0000 9 Note A full reset includes a partial reset but not vice versa bits are self resetting The only reset that is needed for normal operation 1 the full reset bit 7 Ref D73701 003 CE6231 User Manual 135 11 10 5 0 0 1 1 Symb
113. he other components on the PCB Note 8051 clock may be stopped before the 8051 has time to process the suspend interrupt Hence this interrupt may be more useful as an indication that suspend resume cycle has occurred The interrupt must be cleared by setting bit 1 of SUSP_ CTRL 12 5 2 Software controlled suspension This mode is selected when bit 2 SUSP_ CTRL 15 set the default After the suspend condition is detected on the USB a suspend interrupt 15 generated to the 8051 The 8051 should first clear the interrupt by setting bit 1 of SUSP CTRL The software can then take any other actions that are necessary as part of the power down sequence For example the infra red detector may need to be powered down if remote wakeup 1s not enabled Whereas if remote wakeup 15 enabled the detector must be operational general purpose port can be used to control the supply to the IR detector then the software has the option to power it down After the software has taken all necessary actions bit 0 of SUSP_ CTRL must be pulsed to 1 This will cause the following steps to occur in sequence The AGC pins are pulled high The demodulator ADCs are powered down The demodulator PLL is powered down The SLEEP output is driven high The USB and 8051 PLL is powered down The crystal oscillator is powered down AM LL If a self powered CE6231 1 powered up when unplugged the default setting for UP SUSP CTRL ensures that the firmware can load
114. he register Gain _1 _0 Assuming that the RF and IF amplifier have a positive voltage vs gain slope then the range of gain from 0 to 64 RF HiLim is linearly transformed to the voltage range Min to VRF Max The range of gain 64 IF LoLim to 2 1 is linearly transformed to the voltage range VIF Min to VIF Max Hence it is seen that by making RF HiLim IF LoLim an overlap is created between the two gain curves This overlap should be minimized or made zero If the RF or IF amplifier has a negative gain then the corresponding mapping 15 inverted For example if the IF amplifier has a negative voltage vs gain slope then the range of gain 64 LoLim to 2 1 is linearly transformed into the range VIF Max to VIF Min The IF and RF amplifier slope or sense is set using bits in registers Target and AGC 5 Ref D73701 003 CE6231 User Manual 103 11 2 5 TARGETS Register AGC TARGETS Access Read Write Symbol IF Target Dig Target 0 The IF_Sense bit allows the IF AGC output logic to be changed to opposite polarity if the external T IF Sense circuitry requires it The default setting of 0 generates an increasing output level as the signal level increases IF Taraet The IF automatic gain control loop aims to make the average absolute value of the ADC output equal 879
115. interrupt events therefore these are split across 2 registers INT4A and INT4B When individually enabled these bits are OR ed together to give a level sensitive INT4 input This register 1s self reset after reading Note that data channels 1 to 3 are assigned to endpoints 2 to 4 respectively 1 OVERFLOW1 implies an overflow of ENDPOINT2 data 56 CE6231 User Manual Ref D73701 003 9 11 14 INT_EN4A D6h adi ICE st yt s OOS SSS 2 PF_OVERFLOW2 INTEN PF OVERFLOW INLEN Setting each bit in INT to 1 enables corresponding bit in INT4A to generate an interrupt 8051 interrupt 4 Ref D73701 003 CE6231 User Manual 57 9 11 15 INT4B Read only S oe dbo kael alkao DATA INT These bits are set after a PID Filter transfer is aborted before end of the packet This should only occur if the USB PID Filter registers are incorrectly programmed 0 PF_DATA_ABORT1_INT The 8051 INT4 interrupt pin is connected to 10 interrupt events therefore these are split across 2 registers INT4A and INT4B When individually enabled these bits are OR ed together to give a level sensitive INT4 input This register 1s self reset after reading 58 CE6231 User Manual Ref D73701 003 9 11 16 INT ENAB D7h adi at se IE
116. itten by the 8051 for each address byte and write data byte For read operations this register location will be written by the 2 wire bus controller after each byte has been read over the 2 wire bus 84 CE6231 User Manual D73701 003 9 145 SRC D3h 01 sma _ Bits 1 0 select the 2 wire bus interface for access by 2 wire bus controller 00 Internal demodulator 2 wire bus interface 01 External interface 1 DATA 10 External interface 2 CLK2 DATA2 Bit 2 selects the 2 wire bus clock speed 0 60 kHz 1 330 kHz Ref D73701 003 CE6231 User Manual 85 9 14 6 WR TWB CTRL WR D4h __ 1 1 j 1 10 yo _ __ internal demodulator ockeontol This register together with TWB GPP CTRL provides manual bit banging control of 2 wire bus interfaces The bit is set to 1 for high impedance 0 to pull the bus low Bit 0 controls the internal demodulator clock bit 1 controls the internal demodulator data bit 2 controls CLK1 bit 3 controls bit 4 controls CLK2 and bit 5 controls DATA2 86 CE6231 User Manual Ref D73701 003 9 15 General Purpose Ports 9 15 1 GPP_DIR Read Write DAh d Symbo 6 6 Setting a bit to 1 config
117. l count if TRO 1 SFR 88h TCON Timers 0 and 1 each operate in four modes as controlled through the TMOD SFR and the TCON SFR Table 9 2 Timer 0 1 mode Bits 1 0 or 5 4 Timer 0 1 Mode 00 13 btcomter 16 bit counter 8 bit counter with auto reload 2 8 bit counters 38 CE6231 User Manual D73701 003 9 10 2 Timer Counter Control Read Write ICE sty ts ts _ 7 is set when Timer 1 overflows and cleared when the Interrupt service routine is called 6 TR When bit 6 is set counting on Timer 1 is enabled Bit 5 is set when Timer 0 overflows and cleared when the interrupt service routine is called When bit 4 is set counting on Timer 0 is enabled 3 IE1 Bit 3 is the INT1 N interrupt flag This is set when an enabled bit in INT1 SFR 9Ah is set and cleared when INT1 is reset by reading SFR 9Ah 2 1 When bit 2 is 1 INT1_N is an edge sensitive interrupt When 0 INT1_N is level sensitive This bit should be set to 0 1 1 the INTO interrupt flag This is set by a falling edge and reset when the interrupt service routine is called ITO When bit 0 is 1 INTO_N is an edge sensitive interrupt When 0 INTO_N is level sensitive This bit should be set to 1 Ref D73701 003 CE6231 User Manual 39 9 10 3 0 Read Write Symbol BCh E 9 3 9 eG 7 Bit order 15 8 _
118. ly on PLL generated clocks for their operation The hardware reset or SFR DF bit 4 will put these registers to default values Since a clock is present when the hardware reset is applied the reset signal will first be synchronised to the clock signal to prevent the registers going to unknown states when this reset is removed The first of these registers 15 CE6231 EN The CE6231 15 powered up the low power standby mode and hence it is essential to write to CE6231 EN after a hardware reset The other three registers default to the values required for normal operation 1 45 MHz sampling using a 24 MHz crystal and hence do not have to be programmed for the normal operating mode Ref D73701 003 CE6231 User Manual 165 11 19 1 231_ 50h __ o j 1 symbol pra Reed orsast en 7 After a hardware reset CE6231 has to be activated using this register A hardware reset is applied by taking the RESET pin low briefly This resets the all the registers to their default values The default settings for bits 0 and 1 0 hence after the hardware reset the CE6231 is in a low power state activate and enable output from CE6231 it 1 necessary to write a 1 to bits 1 amp 0 The other six bits of this register should be written with their default value ADC should be set to 0 to power down the ADC 166 CE6231 User Manual Ref D73701 0
119. modulator data When 0 the 7 PF 1 BUFFER internal demodulator buffer space is reduced so that external digital or analog data can be im used A separate enable bit is used for this to allow an external demodulator to be switched on and off without interfering with internal demodulator data When bit 5 is set to 1 the horizontal blanking data is removed from ITU 656 samples prior to PF 656 HBLANK DEL transfer over the USB This enables isochronous transfers to be used When O all ITU 656 data samples are transferred over the USB When bit 4 1 0 the MPEG TS data is transferred as a whole number of TS packets When 1 4 PF PKT DIS the data is not packet aligned i e each data payload can start and end anywhere within a TS packet See note 3 2 PF SCK INV When bit 2 is set to 1 the falling edge of SCK is used to sample audio data When bit 2 is set 100 the rising edge of SCK is used to sample audio data When bit 1 is set to 1 the falling edge of MCLK is used to sample the external TS data When 1 bit 1 is set to 0 the rising edge of MCLK is used to sample the external TS data SER serial or parallel external transport stream data 1 for serial data 0 for parallel Miscellaneous PID filter control F Note Packet aligned data is only supported for isochronous transfer mode so if bulk mode is used this bit must be 1 80 CE6231 User Manual Ref D73701 003 9 14 Two
120. n Registers Address Map Address Symbol Defaut Access 80 81h 85h 87h 30h R W 88h 00h R W 89h 00h R W n 00h RW 8Ch Timer One Count Low R W 8Bh Timer Timer Zero Count High R W 8Dh 00h __ 91h 93 99h Unused 9M USBevenintemptregster INT4A INT4 interrupt pin is connected to 10 interrupt events therefore these are split INT4B across 2 registers INT4A and INT4B UDM STATUS Indicates the status of endpoint 0 and endpoint 1 transfers uM USBC STATUSO 9Fh oe Contains the USB configuration selected by the last Set Configuration command STATUS1 USBC Ath TE Indicates the status of the previous 2 wire bus command STATUS TWB GPP CTRL RD Contains the status of the 2 wire bus pins EP 8051 End point command 24 CE6231 User Manual Ref D73701 003 Mes Symbol Descipon Default Access EPO SETUP ADDR EPO Ash 08h R W ADDRO End point zero control 00h R W EPO ADDR1 d EPO ATh LENGTH 00h RAW Enables or disables the interrupts in the 8051 core EP A9h ADDR 32h R W AAh ae End point one control R W LENGTHO EP1 ABh LENGTHY 00h RAW CSR CMD CMD 00h R W CSR CSR DATAO d AFh CSR USB control and status RAY CSR 00h R W CSR PF EN Data stream PID filter enable PID INT BASE 12h R W ADDR This register pair defines the base address in 32 bit words
121. n discard this RS ERR reading Continue reading RS ERR CNT 2 1 O until the corresponding RS UBC 1 0 1s zero If this is not possible then the bit error rate 1 very poor Fromthis RS ERR 2 1 0 work out the bit error rate RS Err Per BS 77 or 4Dh 1024 221024 RS Viterbi output BER i RS _ 1024 1632 RS Cnt For default setting Viterbi output B 7 128 679 936 It is best to perform this several times and compute the average BER Ref D73701 003 CE6231 User Manual 143 11 12 2 RS ERR CNT 2 1 0 Read only Symbol RS ERR CNT 2 RS _ 1 RS ERR 0 12h Addess tt Default 23 0 RS Reed Solomon bit error counter This register contains the number of bit errors corrected by the RS decoder during the period defined by the register pair RS ERR PER _1 0 For details refer to the description of the RS ERR PER 1 0 registers 69 Note The register is frozen when RS ERR CNT 2 is read and unfrozen when RS ERR CNT 0 is read N Caution The value in this register will be too low to give an accurate reading if is non zero 144 CE6231 User Manual Ref D73701 003 11423 RS UBC 0 1 Read only Symbol RS UBC 1 RS UBC 0 Address Defaut ____ j _ _ _ _
122. n if EPO LENGTH is not a multiple of 4 bytes Hence for write commands extra bytes will be written during the last 32 bit write of the transfer These extra bytes will be random and must be ignored However space must be allocated in the buffer to allow for these extra writes For example if EPO LENGTH 15 18 the buffer space must be at least 20 bytes and the last 2 bytes in the buffer should be ignored D73701 003 CE6231 User Manual T1 9 12 11 EP1 End point 1 control Read Write Address Ah A oe ee eo eT eo Default own 2199119 01015 Bitorder ie LENGTH ADDR Bit 21 should be to 1 when the 8051 has prepared an endpoint 1 interrupt packet and 24 8051 DATA EP1 ADDR EP1 LENGTH and the data buffer are valid This bit will be reset after the interrupt ES transfer has completed If the software resets this before the transfer starts the transfer will be cancelled 20 10 EP1 LENGTH EP1 LENGTH contains the length in bytes of the data written by the 8051 to EP1 ADDR 90 EP1 ADDR EP1 ADDR contains the base address in 32 bit words where the interrupt data will be read from 9 12 12 CSR CMD Register CSR CMD Write only ACh eon Ree E csmwm Setemecroandsu smgserwte These bits control the r
123. nal Retry_ Fail sufficiently This indicates that the signal is too weak for QEF reception Note that the alternative algorithm may not be attempted even with poor BER In certain mode guard combinations is possible to improve the BER by using a different algorithm 4 Retry_ Start from the default If the CE6231 detects poor BER the alternative algorithm may be initiated Retry_Start will be set if this occurs FEC Fail Set if the FEC byte aligner fails to lock Lock Set when the FEC byte aligner goes into lock 1 TPS Fail Set if the a valid TPS word is not received during acquisition After setting this bit the state machine re acquires the signal Lock Set when the first valid TPS word is received during acquisition Note This register is reset when read 154 CE6231 User Manual Ref D73701 003 11 15 3 INTERRUPT 2 INTERRUPT 2 S oe dbo laol asla Symbo Lr Rem E eao SetwentyeAknerbckomus o o 5 Note 1 This register is reset when read 2 The CE6231 has INTERRUPT 3 register D73701 003 CE6231 User Manual 155 11 15 4 INTERRUPT 4 INTERRUPT 4 S ee Hs Ca Set when a new set of TPS parameters are stored in the TPS RECEIVED 1 0 registers This 2 TPS changed will cause a re acquire et Note 1 This register is reset when
124. ncy offset can be read from an on chip register 10 7 Symbol Timing Synchronisation This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter symbol interference in the presence of multi path distortion Furthermore this trigger point is continuously updated to dynamically adapt to time variations in the transmission channel 10 8 Fast Fourier Transform The FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT It then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain An extremely hardware efficient and highly accurate algorithm has been used for this purpose 92 CE6231 User Manual D73701 003 10 9 Common Phase Error Correction This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the tuner phase noise on system performance 10 10 Channel Equalisation This consists of two parts The first part involves estimating the channel frequency response from pilot information Efficient algorithms have been used to track time varying channels with a minimum of hardware The second part involves applying a correction to the data carriers based on the estimated frequency response of the channel This module also generates dynamic channel state information CSI for every carrier every symbol 10 11 Impulse Filtering CE6231
125. nputs Input levels 3 14 lt VDD lt 3 47 GPP 7 0 0 5 2 Vin gt ADFMT IRDI MCLK MDI 7 0 MISTART MIVAL SCK Input levels 3 14 lt VDD lt 3 47 DATA1 DATA2 0 5 gt Vin gt 5 5V CLK2 inpilevlis _____________ 3 14 lt 00 lt 3 47 Input leakage current IRDI ADFMT Input capacitance Capacitances do RESETB Input capacitance not include track CLK1 2 1 2 7 0 202 CE6231 User Manual Ref D73701 003 13 4 Crystal specification Parallel resonant fundamental frequency preferred 24 00 MHz Tolerance overall including frequency accuracy and over temperature 100ppm Equivalent series resistance ESR 30 Ohms ideal 50 Ohms maximum Typical load capacitance CL 20 pF Drive level mW Value of C1 C2 parallel capacitors in the application for an ESR of 30 Ohms 13 5 Dynamic characteristics Table 13 4 Digital input bus timing Parameter Mm Parallel mode TS MCLK frequency 12 MHz Serial mode TS MCLK frequency 100 MHz ITU 656 frequency 28 MHz Parallel mode MDI MIVAL MISTART to MCLK setup time Parallel mode MDI MIVAL MISTART to hold time 8ns Serial mode MDI 0 MIVAL MISTART to MCLK setup time dns Serial mode MDI 0 MIVAL MISTART to MCLK hold time ns ITU 656 RD to RCK setup time ITU 656 RD to RCK hold time 8ns WS SD to SCK setup time f WS SD to SC
126. nual April 2006 D56169 002 Intel CE 6353 DVB T Demodulator Overview http www nordig org Universal Serial Bus Device Class Definition for Video Devices MPEG2 TS http www usb org developer evclass docs Ref D73701 003 CE6231 User Manual 13 2 System 2 1 Features Nordig Unified and ETSI 300 744 compliant e Superior Single Frequency Network performance e Unique active impulse noise filtering e Single SAW operation on 6 7 amp 8 MHz OFDM e Excellent performance with any echo profile pre post inside or outside the guard interval e Automatic co channel and adjacent channel interference suppression e Fast AGC and good Doppler performance for portable applications e Large frequency capture range to enable channel acquisition with triple offsets e Clock generation from single low cost 24 0 MHz crystal sampling at 36 17 43 5 or 5 10 MHz from a single crystal frequency e Channel bandwidth of 6 7 amp 8 MHz e Blind acquisition capability including 2K 8K mode detect e Automatic spectral inversion detection e Fast auto acquisition technology e Very low software overhead e Access to channel SNR pre and post Viterbi bit error rates 7 bit ADC for RF signal level measurement e USB 2 0 compliant interface 1 1 compatible e 2 digital input for DVB TS or REC656 125 e On chip 8051 microcontroller with 12K program and 4K data RAM Hardware MPEG PID filters enables USB1 1 operation Infra
127. o When high enables RF level detect ADC By default it is off for lowest power Em AGC2 DIS AGC2 disable When low the AGC2 circuits are enabled By default it is off bit is high for lowest power High enable automatic setting of transport error indicator bit in MPEG packet header byte 2 when the block contains an uncorrected error Low the TEI bit is not used Reseed SSCS Caution The TEI bit should always be set to 1 as otherwise there will be no indication of block errors to the PC 136 CE6231 User Manual D73701 003 11 10 6 CTL CE6231 is designed to select most appropriate output clock frequency for the TPS parameters extracted from received bit stream including constellation hierarchy and code rate The default register setting has been chosen to provide the optimum MPEG data rate for 8 MHz OFDM and 45 MHz sampling with 24MHz crystal The system will work for 6 and 7 MHz OFDM and other clocking configurations but the gap between successive MPEG packets may be larger than optimum The register MCLK CTL allows the user to optimise the MPEG clock for e OFDM bandwidths other than 8 MHz e Clock configurations other than 45 MHz with 24 crystal Read Write 5Ch __ 1 1 The general equation for working out MCLK CTL is MCLK ES Pret
128. o modify code to use DPTRO The CE6231 adds a second data pointer DPTR1 at SFR locations 84h and 85h The SEL bit in the DPTR Select register DPS SFR 86h selects the active pointer When SEL 0 instructions that use the DPTR will use DPLO and When SEL 1 instructions that use the DPTR will use DPL1 and DPHI SEL 15 the bit 0 of SFR location 86h No other bits of SFR location 86h are used All DPTR related instructions use the currently selected data pointer To switch the active pointer toggle the SEL bit The fastest way to do so 1s to use the increment instruction INC DPS This requires only one instruction to switch from a source address to a destination address saving application code from having to save source and destination addresses when doing a block move When bit 0 15 1 and are the data pointers When 0 and DPLO are the data pointers Using dual data pointers provides significantly increased efficiency when moving large blocks of data The SFR locations related to the dual data pointers are e 82h DPOL Data Pointer zero low byte e 83h DPOH Data Pointer zero high byte e 84h DPIL Data Pointer low byte e 85h Data Pointer one high byte e 86h DPS Data Pointer Select LSB 9 9 1 DPS Data Pointer Select me BR _ Read Write 86h ww l1 9 0 DPS Selects between data p
129. ode Endpoint 3 is either Isochronous IN endpoint or a Bulk IN endpoint This is used to transfer ITU Recommendation 656 video data to the PC This 1s a hardware interface once set up the transfers will occur independently of the 8051 Endpoint 4 is either an Isochronous IN endpoint or a Bulk IN endpoint This is used to transfer 125 audio data to the PC This is a hardware interface once set up the transfers will occur independently of the 8051 In isochronous transfer mode the CE6231 has the ability to insert a header before each MPEG transport stream transfer The length of the header can be from 1 to 4 bytes but will usually be set to 2 for compliance with the Device Class Definition for Video Devices with MPEG2 TS Payload The CE6231 can support up to 3 USB configurations 1 to 3 each of which can have up to 3 interfaces 0 to 2 There can be up to 15 alternate settings 0 to 14 for each interface All control operations use endpoint 0 The standard USB commands are given below GETSTATUS ___ DESCRPTOR 6 Software CONFIGURATION 1 SET CONFIGURATION 9 SYNCH_FRAME Unsupported 170 CE6231 User Manual Ref D73701 003 Some standard commands are handled automatically in hardware and do not need to be decoded by software These GET STATUS CLEAR FEATURE SET FEATURE SET ADDRESS GET CONFIGURATION SET CONFIGURATION INT
130. oder accepts the soft decision data from the OFDM demodulator and outputs a decoded bit stream The decoder does the de puncturing of the input data for all code rates other than 1 2 It then evaluates the branch metrics and passes these to a 64 state path metric updating unit which in turn outputs a 64 bit word to the survivor Ref D73701 003 CE6231 User Manual 93 memory The Viterbi decoded bits are obtained by tracing back survivor paths in this memory trace back depth of 128 is used to minimize any loss performance especially at high code rates The decoder re encodes the decoded bits and compares these with received data delayed to compute bit errors at its input on the assumption that the Viterbi output BER 1s significantly lower than its input BER 10 16 MPEG Frame Aligner The Viterbi decoded bit stream is aligned into 204 byte frames A robust synchronization algorithm is used to ensure correct lock and to prevent loss of lock due to noise impulses 10 17 De interleaver Errors at the Viterbi output occur in bursts and the function of the de interleaver is to spread these errors over number of 204 byte frames to give the Reed Solomon decoder a better chance of correcting these The de interleaver is amemory unit which implements the inverse of the convolutional interleaving function introduced by the transmitter 10 18 Reed Solomon Decoder Every 188 byte transport packet 15 encoded by the transmitter into a 204 byt
131. of the internal MPEG data PID look up table and the internal MPEG data PID look up table size PID INT MAX 00h R W PID EXT BASE COh R W This register pair defines the base address in 32 bit words of the external MPEG ADDR data PID look up table and the external MPEG data PID look up table size PID EXT MAX PF INT priority USB payload setting LENO PF EXT MAX USB payload setting 20h R W LEN1 125 Ref D73701 003 CE6231 User Manual 25 HEADER These registers define the header bytes 0 to 4 added to start of each USB BEh E 00h R W HEADER2 PF R W Reseved PF HEADER PF Header Length LEN Reseved Ch Reserved ea Timer 2 Reload Capture value iid RCAP2H 4 Timer 2 current count CE CFh Reserved Progam status word RW TWB TWB TWB SRC Select the 2 wire bus interface for access by the 2 wire bus controller TWB GPP CTRL WR 2 wire bus bit control through GPP ports R W INT Enable interrupt one INT EN4A Enable interrupt 4 INT EN4B R W EICON USB suspend interrupt INT CTRL Interrupt control GPP DIR GPP direction control GPP DATA Defines the data on each GPP pin R W USBC oon gratis Em USB status PF MISC Miscellaneous control bits R W ACC 2 USB disconnect control R W 2 Reserved 26 CE6231 User Manual Ref D73701 003 Mes Def
132. ointer zero and one 36 CE6231 User Manual D73701 003 9 9 2 DPO Data Pointer Zero Read Write Symbol 9 3 eG 7 Bit order 15 8 ___ 9 9 3 Data Pointer One Register Read Write Symbol TG TT Bit order Symb These dual data pointers can be used to accelerate data memory block moves The DPS bit in the DPTR Select register DPS SFR 86h selects the active pointer When DPS 0 instructions that use the DPTR will use DPLO and When DPS 1 instructions that use the DPTR will use DPL1 and DPHI DPS 1 the bit 0 of SFR location 86h No other bits of SFR location 86h are used Using dual data pointers provides significantly increased efficiency when moving large blocks of data HF Note Bit 0 of DPS special function register 86h is used to select between DP0 1 D73701 003 CE6231 User Manual 37 9 10 Timers Counters 9 10 1 TMOD Register TMOD Access Read Write Address 89h 1 o ___ 1 When bit 7 is 1 Timer 1 will only count when INT1_N 1 and TR1 1 When 7 is 0 Timer 1 will T count when TR1 1 SFR 88h TCON Ls TGr OOO O O OOOO When bit 3 is 0 Timer 0 wil
133. ol TPS Received TPS data The 15 LSBs of this register contains the latest TPS parameters received from the input bit stream The contents of these register bits are invalid before the first TPS word has been captured hence the MSB is used to signify the validity of the 15 LSBs Initially this bit will be 0 It is set to 1 when the first error free TPS frame 15 received After this it will remain at 1 It is important to note that the TPS RECEIVED registers are not loaded by received TPS data if this data 15 not valid the TPS Valid bit in STATUS 3 bit 4 indicates the success of the BCH checksum for previous TPS frame TPS word 15 taken as valid only if the 16 bit synchronization word is perfect and the checksum is correct D73701 003 CE6231 User Manual 127 11 8 TPS identifier The eight bits s40 to s47 are used to identify the cell from which the signal comes from The most significant byte of the cell_id 1 b15 b8 shall be transmitted super frames with the frame number and 3 The least significant byte of cell id 67 60 shall be transmitted in super frames with the frame number 2 4 The mapping of bits 1s according to the table below If the provision of the cell_id is not foreseen the eight bits shall be set to zero Table 11 10 Mapping of the cell_id on the TPS bits cell id 610 cell id bo cell id cell id b4 540 941 942 S43 S44 S45 S46 47 11 8 1 TPS CELL ID 0 1
134. om TWB DATA Write 08 to TWB_ CMD Do read and acknowledge Wait for TWB_INT Check for successful status in TWB STATUS Read RSBERCNT 1 from TWB DATA Write 08 to Do read and acknowledge Wait for TWB INT Ref D73701 003 CE6231 User Manual 183 30 Check for successful status in TWB STATUS 31 Read RSBERCNT 0 from TWB DATA 32 Write 08 to Do read and acknowledge 33 Wait for TWB_INT 34 Check for successful status in TWB STATUS 35 Read RS 1 from TWB DATA 36 Write 10 to CMD Do read but do not acknowledge 37 Wait TWB INT 38 Check for successful status in TWB STATUS 39 Read RS UBC 0 from TWB DATA 40 Write 02 to TWB_CMD Send STOP 4 Wait for TWB INT 42 Check for successful status in TWB STATUS 12 3 3 2 Wire bus controller bypass The 8051 can directly control the 2 wire bus signals using the registers TWB GPP WR and TWB GPP CTRL RD This enables bit banging control of the buses if required 12 3 4 EEPROM Requirements The EEPROM must be configured to have 1010000 as the 2 wire bus address There are 2 EEPROM instruction formats supported by the CE6231 These are selected by the pin ADFMT 12 3 4 1 Single address byte format This format is used when ADFMT is tied low An example device 15 the 2416 2K x 8 EEPROM The command sequence for reading data starting at address 0 is shown in Figure 17 Figure 17 Single address byte format 184 CE6231 User Manu
135. ord valid Y gt lt A TPS RECEIVED gt TPS_CURRENT Tracking state gt Y lt change followed by dae No lock lost for loss of FEC gt 18 lock Re acquire OFDM using TPS RECEIVED _ TPS CURRENT Re acquire relevant parts of OFDM and FEC Note that the above figure does not show the complete acquisition algorithm It 1s intended to provide an indication of the acquisition and re acquisition operations showing how the TPS CURRENT _1 0 register is modified 124 CE6231 User Manual Ref D73701 003 1174 TPS GIVEN 1 0 Read Write Symbol TPS GIVEN 1 TPS GIVEN 0 Fh Bit order 15 8 0 Bit Symbol Description Selects between high priority HP and low priority LP bit streams By default this bit is 0 to select 15 LP the HP bit stream TPS given Contains the constellation hierarchy code rates guard ratio mode as in the TPS This register is used to specify the TPS parameters of the OFDM signal to be acquired If some parameters are not known then an automatic search for those parameters can be activated using the register ACQ CTL In the event of a search this register specifies initial search setting For example if the guard 15 specified as 1 32 this register and if guard ratio search 15 enabled by setting bit 1 register ACQ CTL to 0 then a guard search 15 activated wi
136. plex valued signal in baseband This section describes the register which contains the IF frequency setting 11 3 1 INPUT FREQ 0 1 Read Write Symbol INPUT_FREQ_1 INPUT_FREQ_0 6C COMAN Bit order Sets the effective input IF frequency The 16 bit two s complement number ITBFREQ 1s given by the equation Input _ Freq i 65536 The default operating mode is 45 MHz sampling using 24 MHz crystal The effective IF frequency is then 45 0 36 1667 MHz and the corresponding ITBFREQ turns out to be 12864 Note that in some applications the IF frequency is set to be 36 MHz possibly to cut out the Nicam signal Note that at 45 MHz sampling the accuracy with which ITBFREQ can be specified 1s 343 Hz This frequency setting 1 independent of channel bandwidth 6 7 or 8 MHz However the IF frequency may be different for 6 MHz channels and this will have an impact on ITBFREQ Note that ITBFREQ is always a negative number irrespective of the spectral inversion status at the input Note that there are two sets of sampling rates defined using a parameter called SR ADC clock FEC clock 24 xtal 52 00 24 1 60 00 24 xtal 55 20 Table 11 3 meme 24 ___ 68 00 26 1667 20 40 4 6333 14885 CSDBh 36 1667 8 8333 12864 CDCOh 43 75 9 2500
137. quency offset However the BER will then be poor So if the BER is poor or if there are too many UBCs the software ought to read the frequency offset from the CE6231 and re program the tuner to remove this frequency offset 188 CE6231 User Manual Ref D73701 003 Figure 20 Channel acquisition From Start up sequence flow diagram Program tuner using 2 wire bus controller Program OFDM parameters a TPS parameters b OFDM bandwidth d Capture range e Acquisition control Wait for tuner to lock Write 1 to FSM_GO to acquire channel Monitor performance Yes Freq offset too gt Re program offset to tuner large amp BER poor No Yes Ref D73701 003 Hop channel gt CE6231 User Manual 189 12 4 PID filter programming The CE6231 has two MPEG2 transport stream packet identifier PID filters one for the internal TS and one for the external TS The PID filters check the MPEG2 PID against a table of wanted PIDs Any transport stream packets that have PIDs that do not match are discarded Each PID filter can be programmed with up to 64 wanted PIDs The size of the PID tables are written to PID INT MAX and PID EXT MAX and the start addresses of the PID table in Data RAM are written to PID INT BASE ADDR and PID EXT BASE ADDR Example To program the internal filter with the PIDs 0302 0608 102C
138. r correction which enables external test equipment to measure post Viterbi Ref D73701 003 CE6231 User Manual 139 11 11 Signal to Noise ratio 11 11 1 SNR Read only a Sc Symbol The value in this register 15 the estimated mean signal to noise ratio in 1 8dB steps 1 0 to 31 875 dB Note that this value is as seen by the CE6231 at its input and will therefore include the noise contributed by the tuner if the RF level is small SN 140 CE6231 User Manual Ref D73701 003 Table 11 12 Table of SNR values SNR 0 1 2 3 4 5 6 7 8 9 D73701 003 CE6231 User Manual 141 11 12 Error Rate Monitoring CE6231 has two bit error rate monitors and one block error monitor e The Reed Solomon decoder keeps a count of the number of bit errors corrected in a 3 byte register called RS ERR CNT 2 1 0 during a period defined by the register pair RS ERR PER 1 0 This be used to work out the bit error rate at the Viterbi decoder output e The Reed Solomon decoder keeps a count of the number of uncorrectable blocks in a 2 byte register called RS UBC 1 0 This is reset when it is read Hence this gives a count of the number of block errors between two successive read operations Viterbi decoder re encodes the decoded bits and compares these with Viterbi input bits This gives a measure of the OFDM output bit error rate 142 CE6231 User M
139. rds Institute Forward Error Correction Fast Fourier Transform Finite State Machine An audio bus standard Interrupt Service Routine IF to Baseband Conversion Digital interpolator Packet Identifier Pilot Processing Module A digital video standard Slope corrector Symbol Deinterleave Special Function Register Start of frame Scattered pilot Symbol timing recovery Transmission Parameter Signalling Timing Recovery Loop Transport Stream 2 Wire Bus Micro Processor interface Universal Serial Bus CE6231 User Manual 11 Revision History Dat Revision Reference _ 11 September 2006 Initial release 23November2006 1 1 Added 5 interface note 29 March 2007 12 Added Theta JA data 12 CE6231 User Manual D73701 003 1 Introduction 1 1 Related Documents Table 1 1 Document References http www usb org home http www usb org developer s devclass docs Universal Serial Bus Specification Revision 2 0 27th April 2000 Universal Serial Bus Device Class Definition for Video Devices Revision 1 1 151 June 2005 s devclass docs http www itu int Payload Revision 1 1 1st June 2005 Recommendation ITU R BT 656 4 1998 NorDig Unified Requirements for profiles Basic TV Enhanced Interactive and Internet for Digital Integrated Receiver Decoders for use in cable satellite terrestrial and IP based networks version 1 0 2 CE6353 DVB T Demodulator Design Ma
140. read Writing to a Timer register also clears PROG TIMER INT interrupt 156 CE6231 User Manual D73701 003 11 15 5 5 INTERRUPT_5 S oe dbo laol asila ___ 7 ____ Remed F3 TPS Frame Sync Set when a valid TPS word is received e Set when TPS lock is lost Reeme 078 op ee et Note This register 15 reset when read This register does not generate an interrupt D73701 003 CE6231 User Manual 157 11 16 INTERRUPT ENABLES Set a bit to 1 to enable the corresponding interrupt The demodulator interrupt occurs when an enabled interrupt condition in INTERRUPT 0 to INTERRUPT 4 occurs Note that the interrupt registers always show the interrupt status whether enabled or not There is no interrupt enable for the INTERRUPT_5 register 11 16 1 INTERRUPT 0 INTERRUPT EN 0 m Symbo s o Enable bits 7 0 of INTERRUPT 0 to generate an extended interrupt in turn setting flag bit 5 in EXIF register provided that bit 0 of the SFR INT CTRL has been set 158 CE6231 User Manual Ref D73701 003 11 16 2 1 INTERRUPT EN 1 73h at se te tt sts ts ts Symbo o Enable bits 7 0 of INTERRUPT
141. red down The 8051 software 15 loaded from the EEPROM During this time some USB operations can be handled by the USB controller such as SET ADDRESS Other operations will until the 8051 1 operational The 8051 reset 15 released The 8051 begins execution from Program RAM address 0000 The PC sends GET DESCRIPTOR commands to identify the device The PC sends SET CONFIGURATION and SET INTERFACE commands to configure the device After configuration the 8051 can write to the demodulator to power it up The demodulator should not be powered up before configuration to limit the bus current to less than 100 mA 12 3 7 Demodulator start up sequence er 186 Program CE6231 EN 50h to power up device and program clock control registers 51h to 54h Wait about 200 micro seconds for the clock PLLs to settle Apply a software reset to bring all the registers except registers 50h to 54h to their default values Recalibrate the ADC by writing 01 then 00 to register EA Change AGC defaults if necessary The AGC settings are programmed first to allow the AGC to settle while the other registers are being programmed Program the registers required for channel scan Increase the capture range to lock onto channels with triple offsets in both 2K and 8K modes Set the acquisition controls to search mode CE6231 User Manual Ref D73701 003 Figure 19 Start up sequence Ref D73701 003 Hardware Reset
142. requency step size The CE6231 can digitally track out any errors in the input IF frequency specification and then report this error or offset back to the user The Capt Range 2 0 value defines the frequency capture range given in kHz by the following table Table 11 5 Capture range Capt Rng 2 0 0 1 2 3 4 5 6 7 8 MHz 143 286 429 571 714 857 1000 1143 8K 7 MHz 125 250 375 500 625 750 875 1000 6 MHz 107 212 322 428 535 643 750 857 8 MHz 143 286 571 1143 2 7 MHz 125 250 500 1000 6 MHz 107 212 428 857 In the normal acquisition mode it 15 usually assumed that the frequency offsets introduced by the transmitter are known by the user Hence the default setting of Capt Range 2 0 allows only for frequency errors introduced by the tuner step size The default Capt Range 2 0 setting of 1 ensures channel capture with a synthesizer step size of 166 kHz in all operating modes However the user always has the option of increasing the capture range in any mode of operation to any value given by the above table In the channel scan mode the frequency offsets introduced by the transmitter to individual channels may not be known Hence it is recommended that Capt Range 2 0 be set to its maximum value of 7 when scanning for channels with possible offsets The default setting of 1 ensures channel capture with a synthesiser step size of 166 kHz CAPT RANGE Read Write Default al
143. ret symbol s ies Bk Rsetwhen an interrupt eventin TAA orINTAB occurs This register contains interrupt flags for interrupts 2 to 5 5 Note Bit 7 GPP7 can be found in register GPP DATA DBh Bit 6 refer to registers Doh INT EN4A and D7h INT ENAB Bit 5 Bit 5 is set when a demodulator interrupt occurs provided that bit 0 of SFR D9h INT CTRL and the demodulator interrupt enable registers 72h 76h are set as well Bit 4 IRDI is pin 62 of the device and 1 the infra red input Interrupts on this pin are used by the software to decode remote control commands Caution When bit becomes set and the interrupt is enabled in SFR E8 EIE the corresponding interrupt service routine is called The interrupt service routine must clear the bit manually If you enable interrupt 5 when GPP7 15 an output then changes to the GPP7 output by the 8051 will cause an interrupt This interrupt should therefore be disabled when is set to be an output Ref D73701 003 CE6231 User Manual 49 9 117 Extended Interrupt Enable Read Write ___ 1 J o o ___ _______ 7 3 EX5 When bit 3 is 1 this enables the INT5_N interrupt The interrupt service routine is called when the active event on GPP7 occurs 2 EXA When bit 2 is 1 this enables INT4 interrupt The interrupt service routine is called when
144. rogram Status Word PSW select which register bank is in use This allows more efficient use of code space since register instructions are shorter than instructions that use direct addressing The next 16 bytes above the register bank form a block of bit addressable memory apace The 8051 instruction set includes a selection of single bit instructions and the 128 bits this area can be directly addressed by these instructions The bit addresses this area are OOH through 7FH All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing The Upper 128 can only be accessed by indirect addressing 22 CE6231 User Manual Ref D73701 003 Figure 6 Internal RAM organisation Upper 128 bytes Lower 128 bytes 11 10 01 00 Bank select bits PSW 4 3 Ref D73701 003 FFh FFh Accessible by indirect Accessible by direct addressing only addressing only 80h 80h 7FA 78h Accessible by direct and SFR s indirect addressing Special Function Registers 20h 078 Lower 128 bytes 7Fh Direct RAM 30h 2Fh 78h Bit addressable space Bit addressable registers gt bit addresses 00 7 07h 20h E 1Fh Bank 3 18h 17h Bank 2 10h OFh Bank 1 08h Reset value of 07h Bank 0 Stack Pointer CE6231 User Manual 23 8 Special Function Registers 8 1 SFR Summary Table Table 8 1 Special Functio
145. s 15 first converted to an absolute value and then averaged over a pre defined period The difference between this average and twice the Target value is computed and then sent through a non linearity to generate an error value This error 15 used for AGC lock detection The error is also multiplied by a 3 bit gain value to control bandwidth of the AGC loop It 15 then further multiplied by a gain value that is reduced when the error goes below a threshold and when the AGC goes into lock The result is fed into an accumulator which outputs a 14 bit unsigned gain value that can be read out by the software There is an option for inserting an external AGC gain value to test or calibrate the AGC loop If the value of the 8 bit register Manual 15 non zero then this value multiplied by 64 is used instead of the 14 bit value from the AGC accumulator This gain is split between RF and IF AGC loops as described the next section Ref D73701 003 CE6231 User Manual 99 11 2 2 8 IF AGC loops There are two AGC loops one to control amplifier and other to control IF amplifier The dual loop configuration 1 outlined in Figure 11 below Figure 11 CE6231 system outline e MDC RF in RF amp IF amp ADC or VnegrlF AGC1 228 Keo pass pass
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147. sion but this is not a part of TPS If the given constellation hierarchy and code rates are correct CE6231 will acquire the OFDM signal well before a TPS word is received the input bit stream However if a valid TPS word is received before the FEC locks CE6231 will copy the TPS parameters in this to TPS CURRENT _1 0 and use these for locking the FEC If the TPS parameters change during the tracking phase CE6231 responds to these as described in the section on ACQ CTL If the FEC loses lock for about 1 s without a change in TPS parameters CE6231 re acquires lock using the TPS CURRENT _1 0 parameters These operations are depicted in Figure 15 and 122 CE6231 User Manual Ref D73701 003 Figure 16 Figure 15 TPS parameter usage TPS _GIVEN R W Y User gt TPS CURRENT ACQ CTL Y MO GO M G TPS RECEIVED Mode Guard search TPS FSM control D73701 003 CE6231 User Manual OFDM FEC 123 Figure 16 Acquisition Re acquisition flow diagram 5 gt 5 CURRENT mode guard search is enabled find mode and or guard and modify mode and guard bits TPS_ CURRENT Spectral inversion search gt lt FEC locked TPS w
148. te LP code rate Guard Mode Signalling function Constellation Hierarchy HP code rate LP code rate Guard Mode 000 QPSK Non hierarchical 1 2 1 2 1 32 2K 001 16 QAM a 1 2 3 2 3 1 16 8K 010 64 QAM a 2 3 4 3 4 1 8 Reserved 011 Reserved a 4 5 6 5 6 1 4 Reserved 100 7 8 7 8 101 110 111 Ref D73701 003 CE6231 User Manual 121 11 7 TPS Registers There are three registers that contain TPS parameters TPS GIVEN 1 0 RW TPS CURRENT 1 TPS RECEIVED 1 OR TPS GIVEN 1 0 contains user specified TPS parameters TPS CURRENT 1 0 contains the TPS parameters currently used by the CE6231 TPS RECEIVED 1 0 contains the latest TPS parameters in the input bit stream TPS GIVEN _1 0 refers to TPS parameters provided by the user TPS CURRENT _1 0 refers to the current TPS parameters used by the device The user cannot write to TPS CURRENT _1 0 At the beginning of acquisition the CE6231 control unit copies the contents of TPS GIVEN 1 0 TPS CURRENT 1 0 If mode and or guard search is enabled using ACQ CTL then this search happens next When this search is successfully completed the new mode and guard values found replace the given mode and guard values in the register TPS CURRENT _1 0 Note that CE6231 never modifies the contents of TPS GIVEN _1 0 Then CE6231 tries to acquire the OFDM signal using the other parameters in the TPS CURRENT 1 0 in the meantime CE6231 may also acquire spectral inver
149. ternal DVB Demodulator 193 12 7 2 External Analog Video and Audio 195 127 9 eate ti sas uec ut cones 195 12 8 Example USB register settings 197 12 9 PRE OVEN LI 200 OWE COW SE stare tri ti AM 200 AZ TC Lo PATON TEUER 200 19 Electrical Ccnaracterisli6S eise teu 201 13 1 Recommended Operating 201 13 2 Absolute Maximum Ratings 201 13 3 DG Electrical Character iSt CS once eta tosta 202 CE6231 User Manual D73701 003 13 4 Crystal Spec 203 13 5 5 203 14 Package 4 4 4 4 00001 204 List of Figures Figure 1 Watch and record DVB T system 15 Figure 2 Analog and digital TV 15 lt NEE 16 Figure 4 60 Pit QFP Package DIag l BET fati tua DUE 19 I Idure 5 Typical application SCNEMIAUG 2
150. th an initial guard setting of 1 32 The most significant bit MSB of this register LP is used to select between high priority HP and low priority LP bit streams By default this bit 15 0 to select the HP bit stream If at any time the user toggles this bit the LP stream will immediately be decoded without an OFDM re acquisition if the modulation scheme 1 hierarchical However note that the demodulator does not respond automatically for other changes in the TPS GIVEN register To respond to these changes host must write a one to the FSM_GO register bit The 15 least significant bits of this register should contain constellation hierarchy code rates guard ratio mode as in the TPS signalling format defined in ETS 300 744 In fact the format of these 15 bits correspond exactly to that of the bits S25 S39 in Table 10 of section 4 6 2 of ETS 300 744 This 15 further defined by the table below Table 11 8 TPS GIVEN data format not including ETSI 300 744 Annex DVB H modes Channel TPS signalling bit number 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Received TPS signalling bit number TPS RECEIVED 0 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default setting 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 HP 64 QAM Non hierarchical 2 3 1 2 1 32 2K Sel Constellation Hierarchy HP code rate LP code rate Guard Mode Signalling function Constellation Hierarchy HP code rate LP code rate Guard Mode 000 QPSK Non hierarchical 1 2 1 2 1 32
151. the PLL 168 CE6231 User Manual Ref D73701 003 11 19 4 PLL ee Bit order 15 8 0 po fgg ret Symbol pis T Ref D73701 003 CE6231 User Manual 169 12 USB software description This section describes the requirements for the 8051 software for USB communication 12 1 USB implementation The CE6231 provides 3 standard USB endpoints e Endpoint 0 is the default control endpoint This is used for all control operations of the CE6231 The format of the data is completely user defined except for standard USB commands e Endpoint is an Interrupt IN endpoint This can be used by the 8051 to report events such as infra red key presses to the host PC The format of the data is completely user defined Endpoint 2 is either Isochronous IN endpoint or a Bulk IN endpoint This is used to transfer MPEG transport stream data to the PC This 1s a hardware interface once set up the transfers will occur independently of the 8051 The CE6231 has 2 endpoints in addition to the above which depend on the mode of operation Dual DVB demodulator mode e Endpoint 3 is either Isochronous IN endpoint or a Bulk IN endpoint This is used to transfer external MPEG transport stream data to the PC This 15 a hardware interface once set up the transfers will occur independently of the 8051 Analog external demodulator m
152. the suspend ISR must start the power down by setting SFR DF bit 0 The software must clear SUSPI inside the ISR otherwise the suspend interrupt will re occur Ref D73701 003 CE6231 User Manual 61 9 12 USB Control and Status Registers 9 12 1 UDM STATUS Register UDM STATUS Access Read only Address 9Dh eee ___ Em E Bit 4 is set to 1 when an endpoint 1 read completes successfully This is reset to 0 after the EP1 STATUS OK 8051 sets 8051 DATA again Bit 3 is set to 1 when a command fails due to an incorrect packet length This bit is reset to 0 after the 8051 sets EPO 8051 DATAMID EPO 8051 DATAEND EPO 8051 STATUS or EPO CMD FAILED EPO 8051 STALL for the next command This ensures that the 8051 has had time to read this status register since a new SETUP command could occur before the 8051 has time to read this register Bit 2 is set to 1 when an endpoint 0 read or write command completes successfully with no errors For read commands EPO STATUS INT will be set as well since the status direction is PC to 8051 For writes the 8051 will have already sent a status response to the PC This bit is reset to O 2 EPO STATUS OK after the 8051 sets EPO 8051 DATAMID EPO 8051 DATAEND EPO 8051 STATUS or EPO 8051 STALL for the next command This ensures that the software has had time to read this status register since a new SETUP command could occur before the software
153. to TWB CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 55 to TWB DATA RESET Write 04 to TWB CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 80 to DATA Full reset CE6231 User Manual D73701 003 32 33 34 35 36 37 Write 04 to TWB_ CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 02 to TWB_CMD Send STOP Wait for TWB INT Check for successful status in TWB STATUS 12 3 2 Read the Reed Solomon error counters De oy ee NA NO N WN HN N KN HH FY NY FSF FY 29 Write 04 to SRC Select demodulator and 330 kHz speed Write 01 to CMD Send START Wait for TWB INT Check for successful status in TWB STATUS Write IE to TWB DATA Address OF write mode Write 04 to TWB CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 11 to TWB DATA RSBERCNT 2 Write 04 to TWB CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 01 to TWB CMD Send START Wait for TWB INT Check for successful status in TWB STATUS Write to TWB DATA Address OF read mode Write 04 to TWB CMD Do write Wait for TWB INT Check for successful status in TWB STATUS Write 08 to TWB_ CMD Do read and acknowledge Wait for TWB INT Check for successful status in TWB STATUS Read RSBERCNT 2 fr
154. to twice the setting the IF AGC target register Dig AGC Target The digital AGC target should not be altered The automatic gain control loop works to make the average absolute value of the ADC output equal to twice the setting of this register The default setting of this register 1 49 decimal 104 CE6231 User Manual Ref D73701 003 11 26 1 0 Read only or Read Write AGC Cil 0 89h PP eT Bit order 15 8 0 13 11 BW lock red This is the bandwidth reduction applied when the AGC goes into lock default 2 10 7 BW aain red This is the gain reduction applied when the error in dB goes below 3 dB A proportionately reducing gam part of this reduction is applied when the error is over 3 dB but less than 6 dB default 4 A fixed gain applied all the time default 4 Defines the period between AGC_NoLock interrupts register Interrupt 0 address 0 00 bit BO 3 0 NoLock Per which are generated whenever the AGC is out of lock The period is 50 1 NoLock Per 3 0 milliseconds This can be used speed up channel scan The bandwidth of the AGC loop may have to be changed if tuner parameters require it Normally only the BW gain 2 0 parameter would be changed typically from a value of four to two if the RC time constant of the AGC loop is large Ref D73701 003 CE6231 User Manual 105 11 27 AGC CTL 5 Register AGC
155. tput BER The error collecting intervals of these are programmable over a very wide range 90 CE6231 User Manual Ref D73701 003 Figure 9 FEC block diagram HP LP stream from OFDM Viterbi MPEG frame De gt o decoder aligner interleaver Pre Vierbi a BER BER monitor INO Descrambler gt USB decoder Uncorrected block count a UBC monitor BER monitor Post Vierbi BER The FSM controller shown in Figure 8 controls both the demodulator and the FEC The controller facilitates the automated search of all parameters or any sub set of parameters of the received signal This mechanism provides the fast channel scan and acquisition performance whilst requiring minimal software overhead in the driver The algorithms and architectures used in the CE6231 have been optimized to minimize power consumption 10 1 Analogue to Digital Converter The CE6231 has a high performance 10 bit analogue to digital converter ADC which can sample a 6 7 or 8 MHz bandwidth OFDM signal with its spectrum centred at 36 17 MHz 43 75 MHz 5 JOMHz near zero IF An on chip programmable phase locked loop PLL is used to generate the ADC sampling clock PLL is highly programmable allowing a wide choice of sampling frequencies to suit any IF frequency and all signal bandwidths
156. ures the as an output 0 configures the as an input 0 GPPDIRO This register defines the direction of the General Purpose Ports D73701 003 CE6231 User Manual 87 9 15 2 DATA at se st tse When the pin direction is input the corresponding bit is read only When configured an output the register bit defines the output level of the pin oaro __ This defines data on each GPP pin 88 CE6231 User Manual Ref D73701 003 9 16 DEMOD STATUS STATUS ESh __ 1 1 LE When bit 0 is to 1 the internal demodulator STATUS output will be generated on GPP 6 GPP_DIR 6 must be set to 1 as well Ref D73701 003 CE6231 User Manual 89 10 Demodulator Functional Description A functional block diagram of the CE6231 OFDM demodulator is shown Figure 8 This accepts an IF analogue signal and delivers a stream of demodulated soft decision data to the on chip Viterbi decoder Clock timing and frequency synchronization operations are all digital and there are no analogue control loops except the AGC The frequency capture range 1 large enough for all practical applications This demodulator has novel algorithms to combat impulse noise as well as co channel and adjacent channel interference If the modul
157. ximately 1ms steps The actual period depends on the OFDM clock frequency see BW OFDM_DIV FEC DIV ADC clock OFDM clock FEC clock Channel ee 111 he 40 96 Period ms TIMER E OFDMclockfrequency MHz So for the default 45 MHz OFDM clock these are 0 910 ms steps 1 e Period ms 0 9102 5 130 CE6231 User Manual Ref D73701 003 11 9 2 Programmable Timer Value Read only Symbol TIMER 1 TIMER RD 0 Address do dz b _ _ 7 0 See equation for Programmable Timer period This register gives the elapsed time of the programmable timer using the same units as PROG TIMER PER Also refer to the PROG TIMER INT interrupt Elapsedtim e ms TIMER _PD TIMER RD If TIMER RD 044Ah 1098 decimal Then Elapsedtim e 0 9102 1098 999 ms D73701 003 CE6231 User Manual 131 11 10 Miscellaneous 11 10 1 FSM GO Write only d _ Rene E Writing a 1 to ACQ GO will initiate a re acquisition This bit is self resetting so it does not need to be written back to 0 after being written with a 1 132 CE6231 User Manual D73701 003 11 10 2 CTL __ 1 1 symbol Lr o Rem E T
158. z IF by the time the data reaches the elliptic filter the data will be decimated in rate by a factor of 2 Although there are many possible combinations only six sets of coefficients are held within the device This assumes that the IF frequency of 36 17 MHz will be used with 7 and 8 MHz OFDM and the IF frequency of 43 5 MHz will be used with 6 MHz OFDM So we have Set 1 8 MHz OFDM and 20 4 MHz sampling Set 2 7 MHz OFDM and 20 4 MHz sampling Set 3 6 MHz OFDM and 19 5 MHz sampling Set 4 8 MHz OFDM and 22 5 MHz sampling Set 5 7 MHz OFDM and 22 5 MHz sampling Set 6 6 MHz OFDM and 17 25 MHz sampling Each coefficient set has Twelve 12 bit coefficients One 3 bit IPSHIFTS One 3 bit OPSHIFTS One 7 bit GAIN 16XDB Sets 1 2 and 3 are for the low sampling rate mode and sets 4 5 and 6 are for the high sampling rate mode Table 11 13 Elliptic filter options OFDM BW OFDM bandwidth SR Coeff set 162 CE6231 User Manual D73701 003 11 18 Carrier Recovery Loop CRL 11 18 1 AFC Step Register AFC_Step Read Write CCh ecc _ 1 Jj 11 This register sets the parameters for the AFC loop Register CLOCK 0 address 0x51 has a 7 0 AFC Step bit SR bit B2 the setting of which determines the value that should be written to this register This register needs to be reprogrammed when the bandwidth or the ADC sample rate is changed 56 Step

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