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ERC32 System Overview, Saab Ericsson, 04/1997

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2. The copuright ounership of this document is and will remain ours The document must not be used without our authorization or brought to the knowledge of a third party Contravention will be prosecuted R64 8 oo SD 10318 RES RM1005 KI 1620 ws poc SENI SENI 5 E O 3EN2 O 3EN2 RM1005 i d l des 3 p pco 0 2 8 9 0 2 8 0 c iv iv peg ATOS V2 V2 13 cuf t 3 z A 2 4 6 2 2 4 6 2 3 5 5 3 3 5 5 3 4 6 4 4 4 6 4 4 5 7 3 5 5 7 3 5 6 8 SAM 6 8 oe iG 1 9 17 1 9 bri 4KC245 4KC245 IC21 1 i SENT O 3EN2 S 63 gt 2 TTV 8 8 V2 9 3 71 9 lo 4 6 10 is 5 1 2 6 4 12 127 3 13 i4 8 2 14 ip 9 115 4KC245 4KC245 844 IQ 25 S0421 0 IC18 1622 1 SENT 1 SENT 100 31 0 d SEN C 3EN2 19 do 19 deg SAA 20 2 16 2 8 16 16 2 8 16 SAA 102012 Ici IG12 dV dV en I R35 KI 11 E 11 v2 v2 1 5 Se 2c t i act 7 3 10 7 3 7 17 R36 BHT O05 62 be 18 4 6 18 18 4 6 18 3 t TOME 2 3 np 2 2 3 np 2 19 5 5 19 19 5 5 19 c 3 4 3 3 4 3 20 6 4 20 20 6 4 20 pag mms 4 7 4 4 4 20 7 3 21 20 7 MN co m po 5 8 5 5 8 5 2 8 2 22 2 8 2 22 Z co 6 13 2 6 6 1
3. Icio D i Jee MEC RESET D gt RESET FNIT FNITS CPUHALT gt CPUHALT 285 os 2s gs SYSCLK 1 0 J 3 0 2 SYSCLK 1 235 9 1 C26 rea Wee a NN RN1 12 CSO nes 12 13 ALE oS i gt ALE UPS mes ur 9 39 gt DDIR CONN EUROS 5 i DDIR bse Dangle x 9213 SYSHALT C 39o SYSHALT OE MITE CLK2ES 233 ike 9 Kii 238 WDCLKTST 38 WDCLK 1 SYSRESET S o SYSRESET NAN TERRES J301 PROMS 148 ROMCS gt ROMCS 9 NOPAR 147 a 9 IE RE sr NE 1 i NEI 1 ROMWRT 2316 ROMURT 1 2 J301 17 BUSERR 4 gt __ _189 BUSERR 3 PCT TUCMPERR 1 TUCMPERR 24710 TUCMPERR HERGS 4 TEIS IUHMERRI TUHMERR 2460 TUHWERR 5 TA TUERR I TUERR 5 OTS T NEI 8 Liens 9 TEIE 245 2456 TUERR RARES C MEMWRI gt m FPUCMPERR o FPUOMPERR Dangle JE FPUCMPERR 1 3 7 9 gt MEMWR2 ET FPUHHE RP EPUHMERRs 2432 EPUHUERR MEMWRe Danale A MEMBE E gt MEMBEN MECHWERR CONN IDC20 J303 I gt IOSELO 228 DMAREQ D gt Sc DMAREG DMAAS 232 DMAAS IOSEL 2 EXTCCVI 226 gxrccv 3 TOSEL 3 1 EKTHOLD AD EXTHOLD IOWR as Subh LOBE gt gt IOBEN es INULL 224 NULL EXMCS EXMCS L gt EXMCS Dangle 3513 3 IMPAR EST IMPAR M ds Dangle CONN IDC20 LDSTO 203 T
4. 2 4 5 WED 2 ASIG OD 7 alu Emp A 31 0 2d E a D 31 0 B 05 o O po l Ll CTL 24 0 AILL 77 e 4 LLL LL LLL DMACTL lt 6 0 ee ee j 1 s D gt DRDY C gt DMAGNT IMPARI n e DPARIO RXBI TAP lt 2 0 D at gt TCKF Dangle ME RNJIG PNUI6 e Wd R10 E x IC6 1 c LAEN RMTOOS 1206 ER C3 Tee ET 1 gy 9 TMSI l 2 m e S 1 C WDCLK ACT 244 A Drug Na Saab Ericsson Space 9241903 503 The copuright ownership of this document aii o CIRCUIT DIAGRAM is and will remain ours The document fr must not be used without our authorization DEMS2 or brought to the knowledge of a third PC 3 a partu Contravention will be prosecuted ORGINALFORMAT A1 J102 ver 02 31 CONN_EUROSS ce 07 92 RNUIG CONN_EUROSS Jois RN2 1 FLOW CONN_IDC20 IC7 IId FLOW CMODEs CMODE 224 CMODE HCERR BE tenate 601MODE IU id HALT Q HA
5. 44 4 3 3 4 Data Hold Time to ATAC During Store 44 APPENDIX 1 4 PEDIEOUATIONS e tedesca pe seed de e e Son Daan ae eet peru aa 47 APPENDIX 2 DEMS2Z SCHEMA TICS sn ei rie t uibs a emissa 49 Date 10 Apr 1997 Issue 3 Page Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 544 LIST OF FIGURES 11 Basic Configuration with 40 bit Boot PROM Basie Configuration with 40 bit Boot PROM stt 11H 22 Basic Configuration with 8 bit Boot PROMP Basic Conf With 8 bit Boot PROM se 1242 55 System with I O and ATAG System with O and ATAC 1616 66 System with I O and Exchange Memor i Exchange Memory 88 DEM32 Block Diagranh DEMB3Z2Blecek Diagram 2151 99 ERC32 cor e ERC32 eere 2222 1010 DEM32 ATAC Block10 DEM32 ATAC Ble kK 2626 1111 DEM32 MemoryH PEM32 Memaestsjy 2727 1212 DEM32 Memory Mapt2 DEM32 Memeorvy Map t 2628 1313 DEM32 front panell3 DEM32frontpanegl 3131 1414 DEM32 RAM Load at 0Ws and Store at 1 Ws Sequenct4 DEM32 RAM Loadat0Wsand Store att Ws Sequene 40 1515 DEM32 PROM Load at 1 WSIS
6. lt gt I0D 31 0 EXTINT 119 gt BUSRDY IC42 CSW pi Dangle TICK Dangle EF ATAC CEXT Para angle WRHI D 9 Dangle WRLO D Dangle Dangle F12 1 ARE Dangle 2 GIP Dangle 5 Dangle GIS 4 Dangle HIS 5 Dangle HA 6 Dangle 1 HIS i T_ADDR Hig E Dangle HS g Dangle 10 L Dangle 1 sia Dangl D I angle WDCLKI KIS Dangle 13 zi Dangle 14 S Dangle JIS 15 Dangle CLKI c FAS CLK 9 Dangle RM1005 D18 PTC B12 Dangle E EXTCLK CE RESET I 0 RST GIE NM 4 Dangle NC 5 AIS mem 6 i nu H4 A 4 angle Dangle G AIS 8 Dangle G2 15 e 2 9 Dangle d F D14 3 9 Dangle GS DIS 4 11 Dangle G4 E12 amp 2 Dangle r EIS B 3 E14 Dangle e 1 7 4 Dangle H2 E15 s e 5 FE Danale e _ J 6 F4 T_DATAG mm amp 10 7 Dangle ES LIS D 8 E Dangle 2 2 S mI 3 Dangle t D 3 20 2 Dangle d 21 Dangle 84 5 5 22 Dangle 6 23 d Danale C2 T_DATAT 5 i F 24 Dangle B 015 e a E 25 ji Dangle IC4 19 26 Dangle B2 3 RNJJ16 20 27 zi Danale PLD l C 5 UNPROGI Oana ee 28 os Dale CLOCK CLK 8 22 29 2 Dangle pev A3 23 30 012 Dangle 2 amp 21 31 Dangle MHOLD 1 B4 L11 IOWR 2 o 23 QE 25 32 I Dangle IOSELO 3 1 RD 5 33 _ Dangle ia 1 2 ae C5 RELEASE RELEASE 5 IN a 29 pusenve ss 2 g LA 9 BUSERR e gt 29 9n E Iw 8 AS ag Vs BXMCS 7 5 Dangle C
7. CBWR BWR 2 SAB 20 2 I uas MEMCS 8 1 0 D gt 0 1 8 IC3 IC36 IC4 etig RAM 2 1f RAM 2 o RAM 3 2 si2kx8 3 2 Stakxs 3 2 si2kx8 4 3 5 d 715 mu 5 4 s 4 5 4 6 5 6 5 Bar be T 14 g 1 14 g T 14 s 8 15 c 8 15 g 8 15 g s 16 s 16 9 16 gu Im ER e hil 2 20 A Let 2 20 A Sipe 2 20 5 g 3 21 s 21 3 21 4 22 i 4 22 i5 4 22 i 58 5 23 5 23 lia 6 24 6 24 6 24 7 32 lis 7 32 lis 7 32 lis 8 33 I 8 33 9 33 amp 9 3 1 9 3 1 9 3 1 20 35 lig 20 35 lig 20 35 lig 3 3 316 9 5 n 9 8 m Len 131 ac 2C Sloe er G2 cz AV 7 9 7 9 AV 7 9 AID Al 8 1 8 1 8 1 1 2 1 2 1 2 12 3 12 3 12 3 25 4 25 4 25 4 26 5 26 5 26 5 29 5 29 5 29 6 30 T 30 T 30 T M694002L 17 M694002L 17 M684002L 17 SCB T 0 OE e Drug No Saab Ericsson Space 9241903 503 The copuright ownership of this document E iat ion CIRCUIT DIAGRAM must not be used without our authorization DEM32 or brought to the knowledge of a third partu Contravention will be prosecuted CB Ram ORGINALFORMAT Al
8. SAAC 20 2 SRAM SAB 20 2 MEMWR SD 31 0 MEMCS 8 1 0 OE 1 0 CBUR TE SAB 20 2 CBRAM MEMCS 8 1 0 OE CBWR SCB 7 0 Dangle IC25 12 o ROM il 512kx8 2 19 3 8 4 8 5 Ls 6 6 1 5 8 27 lo 9 26 9 23 a ASE 1 25 2 4 jo 3 28 3 4 23 9 la a 4 14 1 gt 3 5 15 2 216 i 17 3 3 T 30 7 AV m 8 i 4 9 5 19 5 CS 229 ME 6 OE 24 je 7121 7 PROG IFLASHI 8 MER Hotel lt N Am29r 040 Drug No saab Ericsson Space Designation The copuright ownership of this document is end will remain ours The document must not be used without our authorization DEMS2 or brought to the knowledge of a third partu Contravention will be prosecuted Memor A E CIRCUIT DIAGRAM ORGINALFOR 4AC244 BMEMWR C2 0 CBUR gt CBWR MEMCS 8 1 0 ET i i
9. The following parameters are changed in the MEC register reset values PROM size is set to 512 Kbyte PROM wait state value is set to 2 RAM size is set to 2 Mbyte RAM wait state value 1s set to 0 RAM EDAC and parity protection 1s enabled Number of nominal RAM blocks are set to 1 Watchdog counter is disabled The UART baud rate 1s set to 19200 The GCC rdbmon has been adapted by ESTEC for the DEM32 board Refer to GMON1 for a detailed description and users manual of rdbmon Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 3144 4 2 8 Front Panel Functions Figure 1747 shows the front panel of the DEM32 board at Figure 1313 DEM32 front panel RESET O HALT e tc Z ET amp 22 oO gt a o 5 S 2 O SERIAL B O ail 9 SERIAL A Two RS232 type serial interface connectors used for host computer communication are provided on the front panel of the DEM32 One halt switch 1s provided The halt switch shall be set to off left position for normal operation A reset push button used for hardware reset of the DEM32 Three LED indicators show the status of the DEM32 After power up the SYSAV LED should be lit and the SYSERR and CPUHALT indicators should be unlit 4 2 8 1 Serial Interface The electrical characteristics for the serial interface pins comply with the RS 232 standard RD9 The Serial A connector c
10. and double precision floating point calculations for ERC32 systems and is designed to operate concurrently with the IU All address and control signals for memory accesses by the FPU are supplied by the IU Floating point instructions are addressed by the IU and are simultaneously latched from the data bus by both the IU and FPU Floating point instructions are concurrently decoded by the IU and the FPU but do not begin execution in the FPU until after the instruction is enabled by a signal from the IU Pending and currently executing FP instructions are placed in an on chip queue while the IU continues to execute non floating point instructions The FPU has a 32 x 32 bit data register file for floating point operations The contents of these registers are transferred to and from external memory under control of the floating point load store instructions Addresses and control signals for data accesses during a floating point load or store are supplied by the TU while the FPU supplies or receives data Although the FPU operates concurrently with the IU a program containing floating point computations generates results as if the instructions were being executed sequentially The FPU supports concurrent error detection by including parity generation and checking and possibility to work in a master slave configuration For more details on the FPU refer to the FPU device specification FPUSPC and the FPU User s Manual FPUUM Document No
11. 35 ns mec t16 OE Output Delay 35 ns mT LI lur _ mec t19 Data setup time to SYSCLK during store 20 ns mec t20 Data hold time during store 1 ns mec t21 MEC Data Output Delay 20 ns mec t22 MEC Data Valid 2 ns mec t23 CB Output Delay 35 ns mec t24 CB output valid to high Z Delay 2 ns mec t69 SYSCLK Output Delay 20 ns mec t7 1 Data Setup Time MEC during Load 3 ns mec t78 Data Hold Time MEC during Load 1 ns iu tDIS Data Input Setup TSC691E 14 7 ns 1u tDIH Data Input Hold TSC691E 14 9 ns iu tDOD 10 tpDCIkB Data Output Delay TSC691E 14 35 ns iu tDOH ju tpDCkBI Data Output Valid TSC691E 14 4 ns 4 3 1 RAM Access The RAM access timing is determined by the IU MEC buffer and memory timing In Figure 14 the timing is shown for a loadand stere operation at 0 waitstates and store operation at 1 waitstates 10 MHz system clock For instance the address setup time for the address latches AC377 is calculated in the diagram to 2 5 ns compared to t4 15 ns which 15 the minimun setup time reguired by the MEC 4 3 1 1 Data Setup Time to IU and MEC During Load Data shall be available at yscr KT with a setup time of mec t71 3 ns Data shall be available at gysc KT with a setup time of iu tDIS 7 ns Timing chain 1 MEMBEN asserted to data available Time from bei kol to tosyscrk 75 ns t69 75ns worst case when t69 0 Margin 1 MEC tosvsc KT tocLk2J1
12. ATA CLK RTC CLK SA 7 2 IOD 31 0 MEC interrupt inputs SA 7 2 IOD 31 0 PLD 22V10 CTL Figure 1010 DEM32 ATAC Block The ATAC is addressed as I O unit 0 in the DEM32 i e command address 0 of the ATAC is accessed at the first memory address of I O unit 0 The chip is operated at 10 MHz which is the system clock frequency The RTC input of the ATAC is connected to the WDCLK signal ATAC external memory is not supported on the DEM32 The EXTCLK input of the ATAC is not used nor are the external interrupt inputs of the ATAC For details about the ATAC see ATACI 3 The ATTN and FAULT interrupts from the ATAC are connected to MEC external interrupt inputs and INTACK is connected to the EXTINTACK output of the MEC Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2744 4 2 5 Memory In Figure 114 below the block schematics of the DEM32 memory is shown SRAM SA 18 2 SA 18 2 MEMCS 9 8 1 0 SD Hum SD 31 0 SCB 6 0 DPARIO S DESI CTL CTL 1 Memory Bank BA 1 0 of 512 kwords 2 Mbyte data and 512 kbytes check bits ROMCS One bank of 512 kbyte data and no check bits Figure 11H DEM32 Memory 4 2 5 1 Nominal RAM The board is equipped with 2 Mbytes of nominal RAM excluding checkbits The RAM is implemented as one bank with four 512k x 8 utilising MEMCS 0 signal of the MEC Once the Memory Configuration Register of the MEC has been initialised it is seen as a continuous 2 MBy
13. ATACIF ABL Type Text RDx N A N A N A N A N A N A N A N A N A No Dependencies No Dependencies Revision history all revisions included Version No Author Modification Date Changes made v1 0 J rgen Jost auf der Stroth 940428 New issue v1 1 J rgen Jost auf der Stroth 940915 Added signal BUSERR N v J rgen Jost auf der Stroth 940920 Removed signal ALE N m Logical behavior and START replaced by IOBEN N 950119 PIN Placement v2 0 Ola Persson 951114 Statemachine rewritten for DEM32 board SAAB ERICSSON SPACE AB Delsjomotet Phone Int 46 31 35 00 00 405 15 GOTHENBURG Swede n CF as Fax In 46 31 35 95 20 Telex 27950 saabsp s This is an module that interfaces a system with ready controlled accesses to the Ada Tasking Accellerator Coprocessor ATAC device typ ic43 device p22v10 CLK pin 1 IOWR N Dun 3 SEL N pin 4 RELEASE pin 6 CE N pin 23 RD pin 22 WR N pin 21 BUSRDY N pin 20 BUSERR N pin 19 Q1 pin 18 Q2 pin 17 States 01 02 CE N IDLE 0 0 1 READ1 1 1 0 READ2 0 1 0 READ3 1 0 0 WRITE1 0 0 0 WRITE2 1 0 1 WRITE3 AP E O WAIT 0 1 1 equations Input Signals Output Signals ist
14. DEM32 PROM Load at 1 W5 4343 1616 DEM32 IO Load ATACI6 DEM32 IO Load ATAC 4545 1717 DEM32 IO Store ATACH7 DEMJ32JIO Store AT AC 4646 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 614 1 SCOPE This document is intended as an introduction to system design using the ERC32 processor core chip set revision CBA The reader is assumed to be familiar with the ERC32 development programme and its objectives Also some knowledge about the ERC32 core components TU FPU and MEC is assumed This document provides an overview of several different architectures built around the ERC32 core as well as a detailed description of a running demonstration board built around revision CBA of the ERC32 components IU FPU and MEC It does not provide in depth analyses of the internal functionality of the ERC32 components rather the principles on how to design a complete system are addressed A list of available documents describing ERC32 is provided in paragraph 2 In particular the ERC32 System Design Documenprovides a detailed description of one computer implementation using the ERC32 core however this document is a paper design based on an early estimation of the ERC32 performance ThazRC32 Functional Description document is more focused on the functions provided by the ERC32 core and serves as overview of the detailed descriptions of the ERC32 components and is fully
15. The document must not be used without our authorization DEMS2 or brought tothe knowledge of a third party Contravention w be prosecuted Io ORGINALFORMAT Al DEST O HOT a 02 13 Jr8e 14 SOAS 02 16 JO TT 02 18 ko oo km Jen Le few ro co Joo no Jen LL jw no 02 19 02 20 TUT 10 22 02 23 JIU2 24 Jige 25 02 26 02 27 Jige 28 Jige 28 02 30 02 31 02 32 CLKI DMAGNT REIS 02 66 02 67 DPARIO DRDY Jige 68 MDS 02 69 102 70 HOT MEXC BUSRDY TEIS CONN_EUROSS AST 07 33 SST J102 35 J102 36 Jlgo ar JT02 38 JT02 33 JT02 40 10 41 1097 4272 02 43 TUT 102 45 JT02 46 JTE AT JT02 48 JT02 43 Jlgo sg OST Jige 52 H S 10 54 02 55 J056 HOST 02 58 05
16. gt A 31 0 TRST ge TRS too LS gt 100 TMSI gg MS TOIL TDI 900501 ERT Drug No saab Ericsson Space Designation The copuright ownershio of this document is and will remain ours The document must not be used without our authorization DEM 32 or brought to the knowledge of a third partu Contravention will be prosecuted TU RT RIT Ur CIRCUIT DIAGRAM ORGINALFORMAT Al RNS Joe Ig PUT anal a CMODE 156 d CMODE THESE i older Est 160 602M0DE MCERR bISS penato CONN_IDC20 HALT 158 HALT FPU HWERROR 7 b gt HWERROR CLK 4 gk RESET 83 RESET DOE 120 d por BHOLD S cj BHOLD MHOLDA 93 MHOLDA MHOLOB SS MHOLDB MDS S c MDS TOE Slo TOE CCCV S8 eeey FIPAR L 87 gt FIPAR CHOLD 82 4 CHOLD Fob gt FP Feco H C Feed IFPAR T9 IFPAR reet HZ gt FCCI FINS S9 FINSI Fccy ES C FCCV FINS2 S9 FINS2 FHOLD 6 89 gt FHOLD FXACK TA FXACK FEXc p 9 gt FEXC FLUSH TI FLUSH INST 4T INST FNULL O9 Dangle APAR 49 APAR PAR 24 DPAR 9 38 g a L153 9 1 38 L14 1 2 ie gt 148 2 3 35 a 3 147 3 4 D 41 15 4 5 3 s 143 5 6 saw cL 6 7 sa 7 MNT 1 8 28 g a 38 8 9 ZAR g 136 9 9 26 ig p LUS B 1 28 4 si T 2 use gt 130 2 3 22 i 3 127 8 4 2l j4 L 126 4 5 20 is p AD
17. 18 9 1 18 9 BEI 9 118 9 2 20 x ATT 2 20 m NE 2 20 u AT 2 20 d s 2 20 e NE 2 20 A AST 2 20 a s 2 20 a s avahi 3 2 lii 3 21 3 21 3 21 n ss mln 3 1 3 21 n 4 22 o 4 22 4 22 lia 4 22 lia 4 22 4 22 lua 4 22 4 22 5 28 5 23 5 23 5 23 i 5 23 i 5 23 lig 5 23 5 23 i 5 24 i 6 24 5 24 5 24 6 24 6 24 5 24 5 24 7 32 lis 7 32 lis 7 32 lis 7 32 i 18530 ie 7 32 lis 7 32 lis 7 32 lis 8 33 lis 8 38 lig gaile 8 38 lis 8 33 jp 8 33 lis 33 s 33 lis s 24 9 3 34 3 34 3 34 3 34 s 34 3 34 80 3 i 29 35 20 s lig 29 35 lig 20 s 20 35 20 35 20 35 ig 3 3 3 3 3 3 3 3 9 bm OF Jorn 4 AEN EE r OF Jorn 1 5 om r S zt rp En 9 131 ER ES slar Sc 131orac 3lojzc lc Sc G2 G2 decz G2 of G2 062 dez og xw 1 g 1 8 iv 7 15 ma 7 24 i 7 g TN 7 8 iv 7 15 ma 7 24 Al Al Al Al Al Al Al E I 3 9 8 17 8 25 8 1 E 9 8 17 3 25 T 2 T 10 T 18 T 26 T 2 T 10 T 18 il 26 12 3 12 I 12 19 12 27 12 3 12 il 12 19 12 27 25 4 25 12 25 29 25 28 25 4 25 12 25 29 25 28 26 5 26 13 26 21 26 29 26 5 26 13 26 21 26 29 29 6 29 14 29 22 29 30 29 6 29 14 29 22 29 39 30 7 20 15 30 23 30 21 20 7 30 15 30 23 30 21 M684002L 17 M684002L 17 M684002L 17 H684002L 17 M684002L 17 M684002L 17 M684002L 17 H684002L 17 TT MENS EE 4 3 3 3 IC37 Ic38 IC39 IC40 e 1 o RAM e I i RAM 21 g RAM e p RAM 3 2 5I2kx8 3 2 5248 3 2 Sl2kxg 3 2 J si2kx8 4 3 43 3 5 4g 5 4 s 4 5
18. Time to IU and MEC During Load Data shall be available at t yscr KT with a setup time of mec t71 3 ns Data shall be available at tsyscppg with a setup time of iu tDIS 6 ns The analysis is trivial since the PLD handshake logic ensures a setup time of more than four SYSCLK cycles 4 3 3 2 Data Hold Time to IU and MEC During Load Data shall be available at gsysci kt with a hold time of mec t78 1 ns Data shall be available at 4sysci KT with a hold time of iu tDIH 9 ns A hold time on the I O data bus of 4 5 ns resulting from capacitive loads is assumed Timing chain I AT AC_CE deasserted to data invalid Margin 1 pld22v10 tp tap mec t78 4 5 1 8ns Margin 2 pld22v10 tp fap 1u tDIH 4 5 9 0ns The margin is 0 ns 4 3 3 3 Data Setup Time to ATAC During Store Data shall be available at tsysci KT with a setup time of ATAC tDIS 0 ns Timing chain I IU store data available Time from DSYSCLKL to LASYSCLKT 150 ns Margin 1 t4syscLxT tasyscLKJ 1u tpDCIKB ac245 tp 150 35 10 5 104 5 The margin is 104 5 ns 4 3 3 4 Data Hold Time to ATAC During Store Data shall be available at tsysci KT With a hold time of atac tDIH The analysis is trivial since the PLD handshake logic ensures a hold time of more than three SYSCLK cycles Document No MCD TNT 0020 SE CLK2 CLK A 31 0 ALE IOSEL x IOBEN DDIR MDS D 31 0 LA 31 0 BUSRDY ATAC CE ATAC RD ATAC
19. To keep margin 1 gt 0 MEMBEN output delay mec t13 must be gt 20 ns A more realistic value for ac245 tp is 6 ns which change the condition on mec t13 to be gt 14 ns The maximum value for mec t13 is 35 ns Margin 2 IU mec t13 ac245 tp mec t69 iu tDIH mec t13 1 20 9 To keep margin 2 gt 0 MEMBEN output delay mec t13 must be gt 28 ns The maximum value for mec t13 is 35 ns Timing chain 2 OE deasserted to data invalid Worst case when SYSCLK output delay mec t69 Is maximum 20 ns ac245 tp is minimum 1 ns and OE output delay 1s minimum Margin M 65656 MEC mec t16 ramtrGHQZ teap ac245 tp mec t69 mec t78 mec tl6 154 5 6 20 1 To keep margin 1 gt 0 OE output delay mec t16 must be gt 5 ns The maximum value for mec t16 is 35 ns Margin 2 M 65608 MEC mec t16 ram trGHQZ tsap ac245 tp mec t69 mec t78 mec t16 8 5 6 20 1 To keep margin 2 gt 0 OE output delay mec t16 must be gt 2 ns The maximum value for mec t16 is 35 ns Margin 3 M 65656 IU mec t16 ram trGHQZ t4 ac245 tp mec t69 iu tDIH mec t16 15 5 6 20 9 To keep margin 3 gt 0 OE output delay mec t16 must be gt 3 ns The maximum value for mec t16 is 35 ns Margin 4 M 65608 IU mec t16 ram trGHQZ 4 ac245 tp mec t69 iu tDIH mec t16 8 5 6 20 9 To keep margin 4 gt 0 OE output delay mec t16 must be gt 10 ns The maximum value fo
20. WR RELEASE Issue 3 Date 10 Apr 1997 Page 4544 250ns 500ns ima Ons 750ns FAI muis H K r E oad dati tred tpCkQ tpCkQ Load address Figure 1616 DEM32 IO Load ATAC Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 614 Ons 250ns 500ns 750ns E M pp 8 tt CLK2 SYSCLK A 31 0 feet FAI TT TC T FA3 OF Ee IOWR DDIR rt VESTES MHOLD En D 31 0 Eu Ho X lt tpCkQ tpCkQ LAGLO NL T W 1 T T M T X A F 38 39 BUSRDY ATAC_CE ATAC_RD ATAC_WR RELEASE Figure 1717 DEM32 IO Store ATAC Document No MCD TNT 0020 SE APPENDIX 1 PLD EQUATIONS ATACIF IC 43 MODULE ic43 Copyright SAAB ERI CSSON SPACE AB Date 10 Apr 1997 Issue 3 The ownership and copyright of this document belong to Saab Ericsson Space AB and it must not be disclosed or used without the written permission of Saab Ericsson Space AB copied altered TITLE File name ABEL unit Purpose and functionality Reference Analysis Limitat Fidelit Discrepancies Usage T70 Opera Asser tions tions Development Platform Analyzer Synthesis Dependencies tions ty Ada Tasking Accelerator Coprocessor Interface
21. charaterisaion and Schematic and for DEM32 V 3 3 10 Apr 1997 3 3 1 1 4 Added DPARIO workaround 4 3 Updated after MEC specification issue 4 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 344 TABLE OF CONTENTS Page I SCOPE tassima Re nn dr M P 6 2 DOCUMENTS umanan Ja ne iii ania loas tut tta pd co didnt Laa 7 3 SYSTEM DESIGN CONSIDERATIONS 9 3 1 IntrOductfOTi Adam Se da dont E aa 9 2 25 ERC 52 Punetions OV ELVIS Wess trai dep Meta 10 3 3 ERC 32 System Con Ura ONS ise ala s 11 3 3 1 The Basic ERC32 based Computer 11 SMS UR ERC S Pillu un dedito Ray alla alodus adu Putin ne 12 oodd EPIO PRU Parity 2 67516 OAAS MUSTA nent a 12 Soke TW EPU TO MEC Panty CMC cl coe tedio tabe Me u mau passa 12 3 3 1 1 3 Memory and I O to MEC Parity Check 13 3 3 1 1 4 Memory to MEC Parity Implementation 14 3 2 ERC32 Computer with ATAC and General Purpose I O 15 Shaol ERC32 Computer with Exchange Memotry 17 3 3 4 ERC32 Computer with DMA Slave Interface 19 4 The DENIS BOAT naat D nu aa ina 21 4 1 iilrodlic IO uy na onal nie die 21 4 2 DEM32 F nc onal Description aei u xe ERU RE T 21 4 2 1 ERC Z COT cocoa Espina Uie t pis da on 22 4 2 1 1 Inte ser Mt DUIS D otc
22. oer epe p sana ne eid Le duoi 23 2 2 11 2 Floating Point Unit FPU RT 23 4 2 1 3 Memory Controller MTS san Ded EE tad be d E 24 4213 External Dus Interface ob a certe idibus 24 J R2 Erap mnan ASS runes TEE AE EU a EU 24 SHE a BS Puni a DAM rr in 25 209 2 Sepu Mamie lS Arina u E ai win 25 225552 Mate dog bi io viu ru n oyunu tus ep to Su nu ar rian 25 42 15 66 Power Dow MONS uuu u u aatal lasi 25 2229 VOP u uu e a desided O sees otn 29 4 22 DE RE A E AA EE EE E A E EE AT 129 4 2 3 CIOCK OSGI ALORS TAMM omm 26 4 2 4 Ada Tasking Accelerator Coprocessor ATAC 26 4 2 5 PAE TMM ONY makaak aa ann as 27 d 2 9 NO REIN SE TM MAN A MS AT RAN ms 24 4 2 5 2 Memory sa AMSTOM se oaa teintes 21 42 530 SA Na PR NE EA a on DO a 24 4 2 6 DEMS Memory NDD u u dede nai 28 421 Resident Software in Start Up PROM 28 4 2 7 1 ATSVYMOA Boot SATA ise osse NOH eie mau E asuy Qua as 29 4 2 7 2 GCG TAHMA BOOL sii go uu uuu Mu a Seina ee ene de 30 4 2 8 Front Panel Enctlois seen tt ae 31 4 2 8 1 S MCE AC aaa aia sa 31 4 2 8 2 Reset Button spin tite lu kasus au ull ae 31 Document No MCD TNT 0020 SE 4 2 8 3 BAIE A T t Rr 3l 4 2 8 4 ESTO Ara S SE UU DN LS 3l 4 2 9 DEMS Z Borda Sir ereinen S 32 4 3 PAS A AV Saa a ie 33 4 3 1 RANLAGC6SS Su pansa dta e md uam
23. project DEM32 is a computer board with the purpose to demonstrate the radiation tolerant SPARC V7 compatible chip set of TU RT FPU RT and MEC 4 2 DEM32 Functional Description The DEM32 is a computer board based on the ERC32 processor core The purpose of the board is to demonstrate the ERC32 core capabilities and it is also intended to be used to develop application software The DEM32 is an industry standard double Europe size 160 mm x 233 4 mm printed circuit board The board may be inserted into a standard VME crate for power supply but power may also be supplied with a custom connector The DEM32 has the following characteristics e ERC32 computer core IU FPU and MEC 2 Mbyte RAM 512 kbyte start up Flash EEPROM also called boot PROM Ada Tasking Accelerating Coprocessor ATAC optional Two RS232C standard serial ports RS232 Interface a MTM eenias TT ddress 2 MB RAM ATAC Figure 88 DEM32 Block Diagram Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2244 The full schematics for the DEM32 are presented in Appendix 2 The DEM32 includes one PLD of type 22V 10 named ATACIF implementing the handshake glue logic to the ATAC The contents of the PLD is listed in Appendix 1 ABEEM source code 4 2 1 ERC32 Core The block diagram of the ERC32 core architecture is shown in Figur amp 9 Integer Unit IU R T Floating Point Unit FPU RT Address lat
24. si S5 4 6 5 15 s s s 5 s 5 qe ka ile tatale 7 14 5 J d4 S iee 8 15 p 8 15 p s IS e s I j 9 16 s 16 s 16 j 9 17 9 17 9 17 e 9 17 Lig 9 L 19 9 L 19 9 118 9 2 om A TE 2 20 x ASTI acd NE 2 om i NE 3 21 8 21 3 21 s 21 d e 4 22 lua 4 22 o 4 22 5 s 5 5 28 s 5 eg n 5 23 a 6 24 S 24 lia 6 24 lia 6 24 i 1 32 j 7 32 lis 1 32 i 7 32 Jis 8 33 lis 8 38 lie 8 33 lig 8 33 i s 34 3 34 lig 9 34 lig 9 34 20 35 i 20 35 ig 20 35 lig 20 35 lig 3 3 3 3 9 5 m 5 Len 9 5 5e 9 5 ism 1319 2c SLofec tslat 13lf2c 8 joe 62 doge cjea ig 7 i 7 8 iy 7 15 A 1 24 Al Al AID KAD 3 1 E 9 E 17 E 25 u 2 n 19 n 18 n 26 12 3 12 il 12 19 12 27 25 4 25 12 25 29 25 28 26 5 26 13 26 21 26 29 29 6 29 14 29 22 29 30 30 7 30 15 20 23 30 21 M684002L 17 M684002L 17 M684002L 17 TS TA TA 1 l l REDUNDANT MEMORY OE 1 0 C gt Drug No Saab Ericsson Space 9241903 503 The copuright ownership of this document E55 iat ion CIRCUIT DIAGRAM must not be used without our authorization DEMS2 or brought to the knowledge of a third partu Contravention will be prosecuted Sram ORGINALFORMAT Al
25. updated to reflect the current design status of the ERC32 components The reader should consult the U RT Preliminary Device Specificationor TSC691E User s Manual FPU RT Preliminary Device Specificatioror TSC692E User s Manual and the MEC Device Specificationtor the latest information about the ERC32 In paragraph 3 of this document system design possibilities are discussed along with more detailed descriptions of system components Different system block configurations are presented and the interfaces between system components are examined In paragraph 4 the demonstration board DEM32 built around the ERC32 15 presented The detailed design 1s presented along with a functional description of the board Note that this document describes the ERC32 system using rev A of the MEC Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 714 2 ERCSPC TUSPC UUM FPUSPC FPUUM MECSPC DEM32 3 ATACI ATAC2 TAPSPC ERCSYS ERCFNC ERRDET AMONI GMON1 DOCUMENTS Specification for a 32 bit embedded computing core ERC32 WDI JG 1334 NL Issue 3 ESA ESTEC 29 05 1991 IU RT Preliminary Device Specification AMS IURT 0017 CLG issue 6 TEMIC MHS August 28th 1995 TSC691E Integer Unit User s Manual Rev H TEMIC MHS December 2 1995 FPU RT Preliminary Device Specification AMS FPURT 0018 VS issue 6 TEMIC MHS August 28th 1995 TSC692E Floating Point Unit
26. 1u tpDCIkB ram twDVWH 155 mec t15 35 15 worst case when mec t15 is 0 105 ns Note that MEMWRI output delay mec t15 has the maximun value 35 ns Margin 2 mec t15 105 ns 4 3 1 5 Data Hold Time to MEC During Store Data shall be available at 4sysciKk With a hold time of mec t20 1 ns Timing chain 1 IU store data invalid IU data output is valid fromt4syscy KL for a minimum of 4 ns which is more than 1 ns iu tDOH 10 tpDCkBI gt mec t20 gt The margin is gt 3 ns Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page B8 4 4 3 1 6 Data Hold Time to RAM During Store Data shall be available at MEMWRI see paragrapl8 3 1 1 43 3 41 4 deasserted with a hold time of ram twWHDX Timing chain I IU store data invalid Time from t4ci k2 1 to tasyscLKJ 25 ns mec t69 25 ns worst case Margin 1 M 65656 and M 65608 t4sysCLKL tacLK2J1 10 tpDCKkBI mec t15 ram twWHDX 25 4 35 0 6ns This is worst case when 1 IU data output valid has the minimum value 4 ns 2 SYSCLK output delay is 0 ns 3 MEMWRI output delay has the maximum value 35 ns However a realistic assumption is that the timing of mec t69 and mec t15 is correlated so that if t15 is maximum then t69 Is near maximum giving more hold time than worst worst case 4 3 1 7 Check Bits Setup Time to RAM During Store Check bit data shall be available at MEMWR see paragraph 3 3 1 1 4 3 3 1 1 4 deasserted wi
27. 2 goto WRITE3 state WRITE3 goto WAIT state WAIT if SEL N then goto WAIT else goto IDLE END 1c43 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 4914 APPENDIX 2 DEM32 SCHEMATICS DEM32 V 3 92 41 903 503a Document page ORGINALFORMAT Al jee BUSRDY ICI T AUCE BUSERR Bre SYSTEMBESET 1 9 800ms 9 COMP Ucc lt 4 65V V1 pi SYSRESET A Ta I COMP EN Be o X X 1 25Vp Dangle 6 8 DI Dangle WDI qp EDO o Dangle EXIINI 1 9 SALO PUSH BUTTONS AXTOS IC3 1 RI 1 SYSAV 1 p2 RERS paie TARCOA RN1 1 5 IC3 2 e 1 pa SYSERR o4 c3 TELEMETRY BS o amp 3 pe TA
28. 2 computer configurations are presented Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1044 3 2 ERC32 Functions Overview The IU RT FPU RT provides SPARC V7 compatible processing functions with extensions for error detection The MEC supplies the processor support functions e System start up control and reset e Power down mode control e System clock e Watchdog function e Memory interfaceto RAM ranging from 256 kbyte to 32 Mbyte Memory interface to PROM ranging from 12 byte to 16 Mbyte I O interface to exchange memory e g DPRAM ranging from 4 kbyte to 512 kbyte e I O interface to four peripherals e DMA interface Bus arbiter Programmable walt state generator Programmable memory data write access protection including support for block protection e Memory redundancy control e EDAC wath byte and halfword write support Trap handler including 15 level Interrupt controller One 32 bit general purpose timer with 16 bit scaler e One 32 bit timer with 8 bit scaler Real Time Clock e UART function with two serial channels e Built in concurrent error detection including support for master checking of IU and FPU e System error handler e Parity control on system bus e Test and debug support Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1144 3 3 ERC32 System Configurations Souls The Basic ERC32 based Computer The first thing to consider when selecti
29. 2J1 mec t16 ram trGLQV ac245 tp mec t71 175 35 10 10 5 3 116 5 ns Timing chain 3 ROMCS asserted to data available Time from bsysc KT l0 tasyscLKt 100 ns Margin 4 M 65656 t3sysCLKT bsvysc KT mec t10 ram trELOV ac245 tp mec t71 100 15 45 10 5 3 26 5 ns Margin 5 M 65608 t3sysCLKT t2SYSCLKT mec t10 ram trELOV ac245 tp mec t71 100 15 25 10 5 3 46 5 ns Timing chain 4 Address stable to data available Time from USYSCLKT tO tasyscLKt 200 ns Margin 6 M 65656 taSyscLKT t1SYSCLKT ac377 tpCkQ ram trAVQV ac245 tp mec t71 200 11 45 10 5 3 130 5 ns Margin 7 M 65608 taSyscLKT t1SYSCLKT ac377 tpCkQ ram trA VO V ac245 tp mec t71 200 11 25 10 5 3 150 5 ns Lowest margin is 26 5 ns Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 244 4 3 2 2 Data Setup Time to IU During Load Data shall be available at fsysci KT With a setup time of iu tDIS 7 ns Timing chain I Data available from MEC to IU Margin SSYSCLKT s tssyscLKl mec t21 1u tDIS 50 20 6 24 ns The margin is 24 ns 4 3 2 3 Data Hold Time to MEC During Load Data shall be available at t yscr KT with a hold time of mec t22 2 ns Timing chain I MEMBEN deasserted to data invalid Margin 1 ac245 tpBZ mec t22 The margin is 0 ns 4 3 2 4 Data Hold Time to IU During Load Data shall
30. 3 Dir 23 9 23 23 9 L 23 p40 RMTOO5 7 14 57 7 14 5 7 TKC245 ARCZI 7 t 7 8 17 6 8 8 17 6 8 AUTO c 9 18 8 9 3 18 3 39 p4o PD c3 4KC3T ARCAT ETE 3 R13 R14 n EA TE Ins G p dm OU 201 t wi 1 3ENI BH TOS RM1005 le BMl 05 R45 O 3EN2 O 3EN2 5 EE 18 3 m 9 f8 ley 19 dog p4G BHT O05 114 i t 3 24 2 T3 8 24 24 2 T3 8 24 RM1005 P47 12 7 12 V V c 13 8 13 V2 va 4 4 4 R48 RMT005 Ha ES 2 3 7 5 2 3 7 25 c ie Past 26 4 6 26 26 4 6 26 pm R49 2 5 5 27 2 5 5 27 a C r 18 17 6 16 REO RMT005 28 6 4 28 28 6 4 28 17 18 9 17 t j 29 7 3 29 29 7 3 29 BM1005 B51 i EE 2 30 a 8 2 30 SAB 1002 8 t a 3 31 a 3 1 3 1 SAS 3 3 4KC245 4KC245 RM1005 R63 x mm 0 94B 20 2 18 NIS N20 R52 c3 20 3 po3 mio IC15 mm i i WE RM1005 d i 62 pos mW 18 3 2 Cc i pp EC 3 RMT005 ES 3 1 s d R57 NO 19 8 9 1 co P 19 T E SENI RM1006 RSS O 3EN2 z CD 20 14 15 19 qe R59 PMTOQ5 12 18 Dangle n 2 I 808 170 7 3 7 20 18 i m RMT OOS CB 7 0 v 4KC37 AINE il i CLOGK TERMINATION 3 5 5 3 3 4 6 4 4 5 1 3 5 RIG 6 8 2 6 c 3 1 7 RM1005 SEE Drug No Issue Saab Ericsson Space 110 55 1 A CIRCUIT DIAGRAM Pree 6 13 SCB_I 7 0 ORGINALFORMAT B5 SYSRESET I ui OE CH QL BACI DI ROMCS SAA 20 2 L gt SAB 20 2 L gt MEMWRI l SD 31 10 a MEMCS 8 1 0 L2 SCB 7 09 lt gt MEMUR2 l
31. 6 2 DMAGNT l 8 eH naat D6 cea gt Bee pasa vcc 22 a 3 T MAE B6 4 19 g IS peq 33 s 910 gt SL IA donate ne 2 E 22V10 15 RD rS 7 ic WR 8 a g 9 9 2 B7 I 4 08 3 7 HEE 1 07 gt OPCODE gt Le 5 AT 2 2 07 5 Ag 7 5 7 Ce 5 4 E SAB 7 2 Q TI5BIT 5 LS res TAT 4 as Lis L2 T L 8 K4 g 9 6e 2 5 b 20 ca RN3 3 K2 21 4 K 5 22 3 g JC NI JS 23 EXTINTAKE gt Le T a 24 LS J2 INT 25 Ld g 3 J 9 26 02 9 5 1 AE 5 e 5 RNUIG RN3 4 eed oS NE 8 rni 3 3b I 13 30 3 gi H x M RN2 3 RNDS oo Hu 31 3 mme H2 i5 atty E BOS BS INTACK FAULT me CD ATAC mes me m CONN TDC20 6 RN3 5 NDS L gt BUSERR Drug No RIT Ur CIRCUIT DIAGRAM saab Ericsson Space Designation The copuright ownershio of this document is and will remain ours The document must not be used without our authorization DEMS2 or brought to the knowledge of a third partu Contravention will be prosecuted Atac ORGINALFORMAT Al TXAL TXBI SRXAL SRXBI IC26 T IRS232 ES Dangle z gx 9H 2 2 15 SV i 15 CX 2 a gt STXA b 8 C gt STXB 3 bcd 20 be 19 AX 233 gt RXA gt RXB saab Ericsson Space The copuright ounership of this document PPesiaetion is end will remain ours
32. 9 J060 JUST JUE JUE ASI 3 0 JIU2 64 kK oo iss HOT HOT e co JIU2 74 e z eo po OTS NOTE gt APAR Jige TT Jige T8 gt ASPAR Jige T8 V MAAS DMAREQ JT02 80 02 81 XFER IMPAR Jige 82 O JO To K2 K2 Jo Io Jo co lo Kn Js eo n2 VUUU LDSTO 07 83 G 3 SIZE 1 0 C20 107 34 107 35 C21 JT02 86 C22 C23 JTS f 07 88 C24 UROJE Drug No Saab Ericsson Space 9241903 503 The copuright ownership of this document PPesiaetion CIRCUIT DIAGRAM must not be used without our authorization DEM de or brought to the knowledge of a third partu Contravention will be prosecuted OMA ORGINALFORMAT Al J101 J102 J201 J202 J301 J302 Jes J204 SPARE VEC CONN_EUROSS CONN_EUR
33. EST m x DXFER DXFER DMAGNT gt gt DMAGNT nee 218 EUER BHOLD gt BHOLD WRT WRT PD 216 p HELD gt MHOLD 215 EXC gt MEXC L gt n E MDS T D gt MDS ka RDY gt DRDY 28 g 1 27 I AOE gt A0E 2 26 COE gt COE d EXTINT DBE ES 4 21 4 EXT INT ACK gt EXTINTACK 214 o 2 i EXTINT 4 0 INTACKI INTACK 205 2 BUSRDY gt SG BUSRDY i 2 206 3 4 203 95 3 TRL 3 0 ASPARI p saia Di mo j I se SIZE MECHWERR pee MECHWE RR SIZE 1 10 9 98 o SYSAV gt SYSAV i s 01 16 2 94 AST BA LH 1 3 38 a o LS 9 BACH ASI 3 0 I 2 2 3 amp 4 5 APARI SL APAR 5 6 sa g E 1 ss 2 82 gt DPARIO CBS RTS 3 isi 3 9 4 8 4 i i 5 Ich gt 2 TS 6 3 3 1 n 3 4 8 IS g 5 5 9 T4 g 6 15 g 7 1 i 72 8 2 TS 2 9 3 3 TO 3 9 9 4 171 1 4 11 5 68 jp p ADR gt 2 6 amp 7 tg 9 3 7 ss i7 4 4 8 65 9 5 B 20 E gt 1 1 21 isi gt 8 8 22 69 5 9 23 59 gt 20 20 24 58 24 21 25 ST as 35 26 gt 26 23 27 S 27 24 28 53 gt oe 29 52 ag aa 30 50 ag 2 31 ISL ai ag ANSE PXN 86 RYA a 24 RXB RXB s 14 TCK TCK DGI 0 TRST O BIG TRST t f TMS 39 TMS SS Drug No TOLL TDI TDO C Too Saab Ericsson Space 9241903 503 90C609A The copuright ownership of this document E ai ion CIRCUIT DIAGRAM is and will remain ours The document must not be used without our authorization DEM32 or brought to the knowledge of a thir
34. KT to loSySCLKT 100 ns Margin 11 M 65656 MEC tosvsc KT t1SYSCLKT ac377 tpCkO ram trA VOV ac245 tp mec t71 100 11 45 10 5 3 30 5 ns Margin 12 M 65608 MEC bsyscLKT t1SYSCLKT ac377 tpCKQ ram trAVQV ac245 tp mec t71 100 11 25 10 5 3 50 5 ns Margin 13 M 65656 IU bsyscLKT t1SYSCLKT ac377 tpCKQ ram trAVQV ac245 tp 1u tDIS 100 11 45 10 5 7 26 5 ns Margin 14 M 65608 IU t syscLKT t1SYSCLKT ac377 tpCkQ ram trAVQV ac245 tp iu tDIS 100 11 25 10 5 7 46 5 ns Lowest margin is 2 5 ns Margin 5 However this is the worst case figure calculated for military temperature range In laboratory environment a typical value for ac245 tp is 6 ns instead of 10 5 ns which is the worst case value giving a margin of 7 ns 4 3 1 2 Data Hold Time to IU and MEC During Load Data shall be available at syscr KT With a hold time of mec t78 1 ns Data shall be available at syscr KT With a hold time of iu tDIH 9 ns A hold time on the RAM data bus of tap 5 ns resulting from capacitive loads 1s assumed Timing chain I MEMBEN deasserted to data invalid Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page BOH Worst case when SYSCLK output delay mec t69 is maximum 20 ns ac245 tp 1s minimum 1 ns and MEMBEN output delay is minimum Margin 1 MEC mec t13 ac245 tp mec t69 mec t78 mec t13 1 20 I
35. LT HWERRORV D gt HWERROR CLK 8 ok doe RESET 228 RESET ERROR v bo gt ERROR J202 FPSYN 207 FPSYN teil Si RN1 10 202 INTACK V gt INTACK mur SUIMODE BHOLD eS BHOLD CONN IDC20 MHOLDA 259 MHOLDA cinsiy ED naie MHOLDB 20 MHOLDB CINS2 V 185 nonate a EXC 38 MEXE CXACK y E Dega DS 234 uns IFPAR y HS gt IFPAR AOE ADE FINSIV gt FINS COE O COE FINS2 V gt FINS2 DOE IE pop pack y 222 gt FXACK TOE E TOE FLUSH V gt FLUSH AO AO INST V gt INST IFT EE gt INULL 25i INULL vss FIPAR FIPAR FP Ta FP IMPAR gt IMPAR FCCO FCCO LOCK V gt LOCK FCCI 288 err Losro y 2 gt LDSTO FCCV 223 Fey DXFER y LS gt DXFER FHOLD 29 FHOLD ueTy S L gt NFT FEXC 2315 FEXC sp 20 T2 RD wyb L gt NE pe ESL cp 206 E CCCO cece ASPAR V gt ASPAR CCC CCC SIZEO V gt SIZEO CCCV CCCV SIZEIV gt SIZE CHOLD 28 CHOLD 9 237 CEXC d CEXC 1 2 3 ASI V 5 6 IRL 3 0 7 DPAR E 34 ASI S 0 0 APARV gt APAR 1 I ak 9 2 2 15 1 3 3 21 38 2 4 4 ate 3 5 5 4 45 4 6 6 se 5 th 7 s 6 9 8 g 34 9 3 53 9 1 131 1 9 54 2 ss E 3 2 4 33 4 3 61 3 5 SE gg vDATA gt 4 59 4 6 39 6 5 TO 5 I R ADR gt vy 16159 9 43 T2 yi 9 44 5 n g 9 8 20 43 20 9 TS 9 21 50 gt MEE 20 22 55 22 2 18 21 23 ST ag 221 29 22 24 62 54 23 82 23 25 54 25 24 81 24 27 26 28 53 2e 27156 21 30 23 31 IS a 39 L1 30 D 3110 lt gt 21 S TCKI aq TOK
36. MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page P444 4 2 1 3 Memory Controller MEC The Memory Controller MEC interfaces directly with the address data and control buses of the IU and the FPU It generates the system clock reset and control signals for the processor elements and all strobes for the memory and the Input Output ports Also it recognises external interrupt inputs and includes two serial ports UARTS For a detailed description of the MEC refer to the MEC device specification MECSPC 4 2 1 3 1 External Bus Interface The on chip bus controller generates all necessary strobes required by external memory IU and FPU and external I O units ATAC 4 2 1 3 2 Trap Handling The main objective for the ERC32 trap handling 1s to resolve internal hardware errors and memory access errors Memory access errors are signalled by assertion of the MEXC signal which force the IU to vector a data access exception For the memory access errors the MEC FAR Failing Address Register is the address of the last synchronous data error detected for IU or DMA The MEC is capable of handling nine different fault events which all result in a synchronous trap assertion of MEXC 1 Parity error on control bus Parity error on data bus Parity error on address bus Access to protected area Access to unimplemented area MEC register access violation Uncorrectable and detected error in memory Bus time out System bus
37. OSS TES TES a 10 bp Danale EE EGENT an mel rent moe mr AT TC a CONN_CAN2S CONN CAN25 CONN IDC20 wae CONN_IDC10 mr ure kii a Fuil xem sam 13 bth Danale le 4 qusazie mi mai TARCOD CONN_EUROSS ie TS mm 4 TC3 4 OT 9 mad e i 5 Dangle CONN IDC20 Ehe ET 4ACO4 JST d IC3 5 J tka 9 L o 19 Danale TBO FARGO EE e Teg e ICS piei Dangle E TAACO4 VCC IC9 1 LofEN 2 v H Dangle 4 16 Dangle 6 14 Dangle 8 12 Dangle 5440244 4 BULK CAPACITOR DECOUPLING CAPACITORS RNWIS RNWIS RNWIS RNIJIS RNUTS RNWIS e IC1 6 9 11 41 43 44 vec RN2 10 PARN2 11 f IR2 12 en2 13 ev2 14 Rv2 15 illc clc ld lc i Re ae si L e Dangle Dangle Dangle Dangle Dangle Dangle C4 Co C6 CT C8 C9 ECO SEC 2 CIS CT CT CCC CC 19 20 SEC 22 23 24 25 26 21 28 29 30 amp C31 32 33 34 35 36 37 38 39 40 C 2 g CROS TTT TTo Tr ET a IE T T T 8 Dangle Dangle 3 3 RN3 7 f RN3 8 IC7 8 10 and 42 PD RND9 CA cinia 46 74 C4 CS ico CS CS 4 CS CS CS CS CS OS 6e a C64 8 T T T gt Dummy Issue A E A CIRCUIT DIAGRAM Meet 13 193 Saab Ericsson Space Designation The copuright ownershio of this document is and will remain ours The document must not be used without our authorization DEMS2 or brought to the knowledge of a third partu Contravention will be prosecuted Power
38. PROJECT Document No MCD TNT 0020 SE Date Issue 10 Apr 1997 3 Page 162 6262 32 BIT MICROPROCESSOR AND COMPUTER SYSTEM DEVELOPMENT TITLE ERC32 SYSTEM OVERVIEW REV CBA Name Function Date Prepared Mikael Ramstr m Project Engineer Checked Bo T rnberg Design Engineer Authorized Ritva Svenningsson Project Manager Distribution Complete ESTEC 5 B2S CK MR CK MW CK AR CM BT CK JO CM TS CM DM CA Summary Reg Office M lndal Office Link ping Office Saab Ericsson Space AB Telephone Telephone Saab Ericsson Space AB S 405 15 G teborg 46 31 35 00 00 46 31 67 10 00 S 581 88 Link ping Sweden Telefax Telefax Sweden Reg No 556134 2204 46 31 35 95 20 46 31 67 38 66 Signature Telephone 46 13 28 64 00 Telefax 46 13 13 16 28 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 244 Class Host System Word 2 0c for Windows SE Macro Rev 1 0B Contract No Host File svax2 Arkiv l mcd tnt 0020_03 doc SUMMARY This document is intended as an introduction to system design using the ERC32 processor core chip set revision CBAFhis decumentis intended as an intreductionto a D A AM ce OA A GA A A AFA 2113 A CX CILO W MIA LJ v D y y y y lt C DOCUMENT CHANGE RECORD Changes between issues are marked with a left bar Issue Date Paragraphs affected Change information 1 8 May 1996 All New document 2 3 Feb 1997 1 02 3 1 42 4 5 Updated after ERC32 electrical
39. R s 124 5 6 18 ig lt DATA_ gt c 119 6 1 il zus 1 8 16 ig g 1117 8 9 IS ig 31115 9 20 14 ag 29 112 20 21 Ba Lit 21 22 H 25 22 188 22 23 io ag 23 107 23 24 E 24 104 24 25 m Sg 102 25 26 13x 26 18 26 27 s 2 100 2 28 4 5 2g LS 28 29 5 xg 29 96 29 30 AS sag 20 31 NP alg al ACS E TCKI TCLK TRST 25 TRST E vali ae 84 ng TDO C TDO TDII Se TDI 90C692EPT saab Ericsson Space The copuright ownershio of this document is end will remain ours The document must not be used without our authorization or brought to the knowledge of a third party Contravent ion will be prosecuted Drug No RIT Ur Designat ion CIRCUIT DIAGRAM DEM32 ERR ORGINALFORMAT Al
40. RCOA LED 2 P SYSRESET SA B4 o TARCOO ROMCS ROMCS ROMCS 2 SIRET MEMCS 8 1 0 meres ce 1 o EMORY p R3 SYSHALT apres MBA MEMMR2 A CPUHALT 5 LS MEMURI RLROS E n MEMRI MEMURI res TR LED 03 ni aut TEN IOSELO SCBCT 0 RS HRC32 ea LOMR SD 31 0 7 L 1 9 FNIIG mp RIS EXTINT 4 9 d SEC CLK O RN1 3 SYSCLK 1 0 M BA 1 0 IEE ees 3 Gertie Do mu OE 110 n DMAREQ 9 14 15 me SAA 20 2 a E 4 AC31 0 SAB 20 2 43202 TU EXTINT 4 0 el Le APAR Bie HHOLD suere ys LOCK saree RN3 1 SIZEO A BXMCS ATAC 7 CLK SONED D FRDS sel RESET EXTINT 1 9 EXTINTAC EXTINTACK sm EXTINTACK e OSELO LDSTO OWR 10 IODC31 0 mm 2 CPUHAL T MAE WDCLK m WDCLK BUSRDY SABCT 2 BUSERR ASIC3 0 SYSAV SCBCT 0 ASPAR Er OE SD 31 0 ALE RD SAA 20 2 e SAB 20 2 4 BA 1 0 Mem e CPUHAL T TXB 1 DMAGNT 1204 ain 10 Je01 8 J20 RXB DPARIO 2 RXA G TXA STXA EOE STXA 2 6 MEXC TXB 11 STXB 3 7 STXB Ck LES TEK CONN_CAN2S TRST puer TRST SA TMS m TMS TEKE SRXA TDI BTS TDI a PH CONN IDCIB ALES RXB J201 amp J202 RXA SPX A ears SRXB CT J304 CONN CAN25 BS TCF mz TDO CONN IDC19 0 9 CLK CLK DMAREG Pese LOCK AC3110 1 DMAGNT pur DMA AGIO D 31 0 APAR ARAR 2 DPARIO pro sinks DMAAS 3 MDS VE reri LDSTO POWER A MEXC lys 12 DER DXFER S DRDY ppbve ASIC3 0 MA S BUSRDY ASPAR RENE 13 ed IMPAR IMPAR o RD er RD CD El Design WE WE TO g
41. User s Manual Rev H TEMIC MHS December 2 1995 MEC Device Specification MCD SPC 0009 SE issue 4 SAAB Ericsson Space April 10 1997 DEM32 V 3 USER S MANUAL MCD TNT 0021 SE issue 3 SAAB Ericsson Space Januari 28 1997 ATAC 2 0 Ada Tasking Coprocessor Data Sheet draft issue 0 99 March 1993 ATAC 2 0 Ada Mechanism Performance draft 1ssud 0 March 1993 Standard Test Access Port and Boundary Scan Architecture IEEE STD 1149 1 June 20 1989 ERC32 System Design Document MCD TNT 0009 SE SAAB Ericsson Space 20 Apr 1994 ERC32 Functional Description MCD TNT 0005 SE SAAB Ericsson Space 20 Apr 1994 Concurrent Error detection for SPARC WDI JG 1734 NL Issue 1 ESA ESTEC 25 11 1992 AdaWorld Development Environment for SPARC based Workstions under Solaris 2 to ERC32 Targets release 5 5 4 Cross Development Guide MCD ALS P2 DOC 015 issue 2 revision 1 Thomson Software Products Alsys December 12 1996 The ERC32 GNU Cross Compiler System Ver 1 0 ESA ESTEC October 1996 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 844 This page is intensionally left blank Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 944 3 SYSTEM DESIGN CONSIDERATIONS 3 1 Introduction A basic computer implementation using the ERC32 chip set would consist of the tollowing components ERC32 core including Processor which consists of one Integer Unit IU and one Floating P
42. a lee aaa 34 4 3 1 1 Data Setup Time to IU and MEC During Load 34 4 3 1 2 Data Hold Time to IU and MEC During Load 35 4 3 1 3 Data Setup Time to MEC During Store 37 4 3 1 4 Data Setup Time to RAM During Store 37 4 3 1 5 Data Hold Time to MEC During Store 37 4 3 1 6 Data Hold Time to RAM During Store 38 4 3 1 7 Check Bits Setup Time to RAM During Store 38 4 3 1 8 Check Bits Hold Time to RAM During Store 39 4 3 2 EEPROM ACCES SSSR ne en die to co 41 4 3 2 1 Data Setup Time to MEC During Load 41 409522 Data Setup Time to IU During Load 42 2 35 25 Data Hold Time to MEC During Load 42 4 3 2 4 Data Hold Time to IU During Load 42 4 3 3 DECENT AC JACOBS ne dl uda ce EIL eMe 44 4 3 3 1 Data Setup Time to IU and MEC During Load 44 4 95 92 Data Hold Time to IU and MEC During Load 44 Jo has Data Setup Time to ATAC During Store
43. be available at fsysci KT With a hold time of iu tDIH 9 ns Timing chain I tesysci kt to MEC data invalid Margin 1 mec t22 iu tDIH The margin is 7 ns However at room temperature mec t22 is considerably larger than 2 ns worst case value giving a sufficient margin even if considering worst case hold time on the IU Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 4344 Ons 250ns 500ns 750ns 1000ns 0 1 2 3 4 5to8 9 10 11 12 CLK2 D SYSCLK A 31 0 B LA2 T 1 FT 1 LA2 LA2 TI _LAT _LA3 LA3 LA3 hize Ip NN MEMBEN HE kl OE j BA 1 0 HL L L t17 l Poe Ld l l kel TT 01710711 16 dr tet T T MDS At gt 37 HT gill el toEL tp t21 j t2 t71 AA tp tDIS tpZB D 7 0 tpZB CE t LE J I KR CE tp 4 D LD byte 3 LD byte 2 to 0 a IU Dati t21 t22 DPARIO FF XS C l Generated tpCkO LA 31 er KK Load address 1 lt Load address 2 Figure 1515 DEM32 PROM Load at 1 WS Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 444 4 3 8 I O ATAC Access The ATAC is addressed as I O unit 0 in the DEM32 As the ATAC cannot be connected to the ERC32 system bus directly handshaking logic must be implemented In the DEM32 the handshaking is implemented in a PLD 22V 10 see Appendix 1 The timing is thus largely controlled by the PLD 4 3 3 1 Data Setup
44. ches and data buffers MEmory Controller MEC Figure 99 ERC32 core Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2344 4 2 1 1 Integer Unit IU RT The IU is the primary processing engine in the SPARC architecture executing all instructions except for specific floating point operations The FPU performs floating point calculations concurrently with the IU The architecture also allows for concurrent operation through the use of an optional second coprocessor not implemented in the DEM32 For a detailed description of the IU see IUSPC and the IU User s Manual IUUM Significant features of the IU include e Full binary compatibility with entire SPARC V7 application software base e Architectural efficiency that sustains 1 25 to 1 5 clocks per instruction e Large windowed register file e Tightly coupled floating point interface e User supervisor modes for multitasking e Semaphore instructions and alternate address spaces for multiprocessing e Tagged arithmetic instructions to support artificial intelligence software The IU supports concurrent error detection by including parity generation and checking program flow control and possibility to work in a master slave configuration In the DEM32 it is possible to enable program flow control by forcing this input low at the board test connector 4 2 1 2 Floating Point Unit FPU RT The FPU provides high performance IEEE STD 754 1985 compatible single
45. d partu Contravention will be prosecuted Mec ORGINALFORMAT Al MEMBEN DDIRI IOBEN 0310 lt TT gt CB C6 0 o9 CLKI ALE 420 DD 1206 C2
46. da Tasking Accelerating Coprocessor which is also an I O unit from a system point of view Note that separate Address and Data buffers probably are required for I O and memory The MEC signals IOBEN and MEMBEN are used for this purpose If common buffers should be used IOBEN and MEMBEN would have to be gated resulting in a timing performance loss There are no special I O instructions in the SPARC architecture Therefore a memory mapped I O bus is used Also since the memory addressing range with 3 ddress bits is more than required in the foreseeable future for space projects part of the memory address range is reserved for I O accesses Memory external to the ERC32 core can be implemented as I O units allowing longer access times in case they are connected to an external bus e g a VME bus A reason for connecting external memory in this way is that the chip select signals for the internal memory are specially defined and decodes no more than 3Mbytes of memory The I O communication may require widely different access times and therefore a ready signal BUSRDY for signalling that the transfer has been accepted is provided The ready signal allows the processor to continue the processing as soon as the ready signal is received without unnecessary waiting To avoid the disadvantage that the I O units have to provide such a ready signal even in case their timing 1s fixed a combination of wait state generator and ready signal can be used T
47. detection on system level is able to detect faults in DMA accesses either the DMA itself flags an error or the MEC can detect erroneous behaviour such as if the DMA does not remove the DMAREQ It is possible to transfer up to 341 words within 1024 system clock cycles with a DMA If one extra WS is needed for the DMA it is possible to transfer up to 256 words within 1024 system clock cycles Note also that only the DMA will sample the Memory Exception output during DMA accesses If the DMA occupies the system bus for a longer time than expected the system can be alerted that something unexpected has occurred The time out is needed to avoid deadlocks or unexpected long access time on the bus Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page POM Such extended access time lead to indeterministic real time behaviour of the system and must therefore be aborted with a synchronous trap In case of IU access the IU both aborts the cycle and handles the trap In case of a DMA the DMA 15 responsible for aborting the bus cycle but can not process the trap Thus the trap issues an interrupt to the IU via the MEC For the ERC32 system detection of erroneous accesses is essential to guarantee the integrity of the processes Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2144 4 The DEM32 Board 4 1 Introduction This chapter describes the DEM32 evaluation board developed within the 32 Bit Microprocessor
48. ed Extended PROM area 15 5M 0x01F00000 Non implemented Exchange memory 512k Word write and Word Hword Byte read AIl data sizes allowed All data sizes allowed 0x02400000 Non implemented RAM area 0x04000000 Non implemented Extended RAM area 192M 0x10000000 I O area 0 ATAC Option 512 Parity option All data sizes allowed 0x 10000200 Non implemented I O area 0 16M 512 Figure 1212 DEM32 Memory Map 4 2 7 Resident Software in Start Up PROM Upon system reset of the DEM32 performed on power on or by pushing the RESET button on the front panel execution is started in the Start Up Prom The Start Up PROM contains a small boot strap routine hardware initialisation system self test and debugger monitor see AMON or GMON Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2944 4 2 7 1 AlsyMon Boot Strap A small boot strap routine is executed immediately after system reset The boot strap routine initialises some MEC registers and copies the contents of the PROM to RAM whereafter execution continues in RAM The following parameters are changed in the MEC register reset values MEC Control Register Access protection disabled UART baud rate 19200 UART parity disabled UART even parity MEC Memory Configuration Register 2 RAM memory banks 1 MB RAM EDAC and Parity used on RAM PROM write disabled MEC Waitstate Configuration Register 0 waitstates on RAM read 0 waitstat
49. ed or the DPARIO has to be stored in a separate memory device There are a number of possible system configurations and associated problems l For systems with no PARITY and EDAC protection on memory No memory device 15 needed for storage of EDAC DPARIO Systems with no EDAC PARITY protection on memory does not have atiming problem 2 For systems with PARITY but without EDAC protection on memory Use separate memory device one bit memory for the DPARIO or use 9 bit memory component for combined Data 0 8 DPARIO storage DPARIO is stored in the separate memory device using the MEM WR1 signal 3 For systems with PARITY and EDAC protection on memory a Systems with separate memory device for DPARIO storage DPARIO 15 stored in the separate memory device using the MEMWRI signal b Systems with memory device for combined storage of CB 0 6 DPARIO Use a transceiver registerto latch DPARIO using the MEMWR1 signal before storing to memory using the MEMWR2 signal e Systems with memory device for combined storage of B 0 6 DPARIO Use one waitstate to store the DPARIO signal to memory using the MEMWR1 signal only The DEM32 design is using the 3c solution and the timing analysis in chaptef 3 4 3 1s done based on this solution Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1544 3 3 2 ERC32 Computer with ATAC and General Purpose I O Figure 5 shows a tentative system with I O peripherals and an A
50. error oo ON a RON The MEC handles fifteen different events which all represent asynchronous trap assertion of the Interrupt Request Level IRL inputs of the IU 1 Watch Dog time out DMA time out DMA access error UART error UART A data ready UART B data ready RTC interrupt General Purpose Timer interrupt Correctable error in memory 10 Masked hardware error 11 Five external interrupts ONAN a BW ND Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2544 4 2 1 3 3 Timers The MEC includes a timer clock divider that supplies the timer functions with a timer clock derived from the system clock The timers have configurable scalers and counters The MEC has two timers e One real time clock timer e One general purpose timers 4 2 1 3 4 Serial Channels The MEC supplies the board with two asynchronous serial communication channels These channels implement full duplex serial communication The serial communication channel baud rate is programmable 4 2 1 3 5 Watchdog Timer The watch dog function is realised as a retriggerable single shot timer with programmable time out A reset timer starts counting when the watch dog timer has elapsed The reset triggering can be avoided if the watch dog interrupt is refreshed before the reset timer elapses There 15 also a trap door function which disables the watchdog 4 2 1 3 6 Power Down Mode The MEC includes a software pro
51. es on RAM write 1 waitstate on PROM read 1 waitstate on I O 0 AT AC MEC Interrupt Mask Register Masked Hardware errors interrupt enabled UART A Tx Rx Interrupt enabled UART B Tx Rx Interrupt enabled Correctable error in memory interrupt enabled UART error interrupt enabled DMA access error interrupt enabled DMA time out interrupt enabled General Purpose Timer Interrupt enabled Real Time Clock Interrupt enabled MEC Watchdog Trap Door Set Watchdog disable Refer to AMONI for a detailed description and users manual of AlsyMon Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page BOHM 4 2 7 2 GCC rdbmon Boot Strap A small boot strap routine 1s executed immediately after system reset The boot strap routine initialises some MEC registers and copies the contents of the PROM to RAM whereafter execution continues in RAM The boot strap loader operates in the following steps The register files of TU and FPU are washed to initialise register parity bits The MEC control waitstate and memory configuration registers are initialised The top 32K of the RAM is washed to initiate the EDAC checksums Part of the loader is moved to the top of RAM to speed up operation The remaining RAM is washed and the monitor is decompressed and installed The text part of the monitor is write protected except for the lower 4K where the traptable resides Finally the monitor is started
52. etected internally in the ATAC and should be connected to a non maskable or an unmasked interrupt input on the MEC Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1744 3 3 3 ERC32 Computer with Exchange Memory In ERC32 systems with multiple units that can access the main memory outside the ERC32 core control there might be indeterminism As an example an ERC32 core could be connected to a asynchronous system bus where the masters of the system bus can access the local RAM of the ERC32 core through DMA This architecture leads to a number of problem areas For instance as the arbitration of the system bus is handled outside the ERC32 core simultaneous accesses might cause a deadlock in the arbiter This could be solved by aborting either the local request or the system bus slave request which however is complicated and generally requires software overhead A better solution would be to implement a separate area with a separate arbiter for exchange of data The MEC supports this concept by dedicating a memory area called the Exchange Memory area An exchange memory can be implemented and used in various ways The most common implementation is as an non intrusive high performance data exchange channel The MEC therefore treats the exchange memory as a true dual port memory with 32 bit organisation Thus the exchange memory should only be used for transferring data 1 e programs should not be executed from the exchange
53. grammable power down mode that puts the system in a power saving mode by inactivating of the IU FPU bus controls The system wakes up from Power down mode if any enabled interrupt is detected 4 2 1 3 7 I O Ports Four general purpose I O ports are supported by the MEC Each port can be individually controlled by programming an internal MEC register On the DEM32 only one port is implemented I O port 0 which is used for the ATAC interface 4 2 2 Buffers The address bus from the IU 1s latched and buffered using D flip flops with clock enable 4 x 54AC377 The memory data bus RAM and EEPROM including check bits is buffered 5 x 54AC245 The I O data bus ATAC has separate buffers 4 x 74 AC244 4 2 3 Clock Oscillators The MEC provides the IU and FPU with a system clock This clock is derived from the external system oscillator The oscillator operates at a frequency of 20 MHz which means that the system clock frequency is 10 MHz The watchdog oscillator is connected to the WDCLK input of the MEC The watchdog oscillator frequency is 1 8432 MHz Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page P614 4 2 4 Ada asking Accelerator Coprocessor ATAC In Figure 1010 below the block schematics of the DEM32 ATAC interface is shown The ATAC cannot be connected to the ERC32 system bus directly handshaking logic must be implemented In the DEM32 the handshaking is implemented in a PLD 22V 10 see Appendix 1
54. gt IOSELO f is epe 12 BHOLD 4 d DMAREQ TOWR gt IOWR F IS P AOE FINS1 1 2 1 mE EXTINT 4 0 IOBEN TOBEN i i a ed m 3 E MDSe S INTACK EXHCS gt IMCS vec 4 24 n End 5 CCOV FIPAR B RI rach CRESET IECTL 5 0 CHOLD EPs 1 OM 2 EXTINTACK 9 3 0 I C gt BXTINTACK I a Lp 4 18 I a SYSERR gt SYSERR 2 5 F se 6 18 DXFER 3 GENI 5 6 e ro RNSJe zii T Feco 7 FPAR FCCI RNDS INS FCCV ie I 35 INS2 FHOLD 19 LDSTO FOCI LDSTO 19 E PESE zu LOCK Eu ESS E 18 L 23 cev DXFER WRT 18 ST BACI 0 BAC DXFER FHOLD WRT 2 ie 3 us Sane A FEXC R 5 4 23 URT vec WE 4 amp GUO n a hs d ee B re OT RNIB 5 gu MEXC DMAAS e ccoo ASPAR M mee 4 SIZE 1 0 2 7 al SIZEO HAS 2 CLK ASPAR e ccev SIZE A i Ne P i eae ue DI APAR COE ALE SD 31 OTI suo T poby 0E 2 AGD DOE CEXCx ASI 3 9 TD0L 4 MEMBEN EXTCCV a Oo ms gt 100 31 19 E nor ms 2 EXTHOLD DDIR s SCBC 7 O lt gt SCB 7 0 ine DPARIO CB 6 0 AGIO C A DRDY E RUFF SAA CZO 2 SAA 20 2 THY JUL Ui D 31 0 6 APARL 2 9 RXA SAB 20 2 p SAB 20 2 TCK TXA BUFF 4 20 2 1 TRST CK1100 RXB TXB A 20 2 DMAREQ C 9 2 DPAR TMS TCK TDO IOBEN DPARIO let TDI D 31 0 ns ASIC3 0 a i NI TDI D 31 0 LM
55. he wait state generator is programmed to give the minimum time to wait Then if an I O unit needs more time it can use a bus ready BUSRDY signal indicating that the processor has to wait further For I O units not requiring extra time this signal should be asserted immediately upon access indicating bus ready The MEC can be programmed to insert from one to fourteen waitstates before the BUSRDY signal is sensed An I O unit which may occasionally require more time has to deassert the BUSRDY signal within the programmed access time to make the processor wait A Bus Time out function is included in the MEC in order to eliminate the risk for blocking the system if an I O unit permanently deasserts the BUSRDY signal A typical I O unit including the ATAC will have interrupt capability towards the IU In the MEC a maximum of 5 external interrupts are provided In a system including an ATAC additional interrupts are provided to be handled by the ATAC task manager These interrupts will however have a greater latency than the interrupts directly connected to the MEC Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page kriditeisedeseseel ne tel oe TT Se eee ee ese See ee ee ees eee eee Se ee es c ee ee eae Se ees See es ee aera Se ee eee ae eee ee BOOT PROM BYTE SELECT External IRQs External IRQs Figure 55 System with I O and ATAC Complete information about the Ada Task
56. ing Accelerating Coprocessor ATAC can be found in the ATAC guides RD10 12 The ATAC 15 connected as an I O unit but some glue logic 1s required to adapt to the MEC signal timing In particular the bus cycle length varies when accessing the ATAC Therefore the number of wait states is set to a minimum in the MEC but the RELEASE signal from the ATAC must be used to create the BUSRDY signal with proper timing towards the MEC to extend the bus cycle as required Note that in the I O area the MEC will always insert one waitstate to wait for the BUSRDY signal even when the number of waitstates is set to the minimum The ATAC does not generate or check the parity on the address and data lines Therefore the MEC must be programmed to supply a parity bit for ATAC accesses The ATAC has two interrupt request outputs ATTN and FAULT These signals can be connected to external interrupt inputs on the MEC Note that these signals are active high while the default polarity for external interrupts in the MEC is active low 1 e the MEC must be programmed to be active high for the external interrupts used for ATTN and FAULT Moreover the ATAC removes the asserted ATTN signal only when it receives an acknowledge signal The external interrupt acknowledge output from the MEC EXTINTACK 15 to be used for this purpose Note that the MEC must be programmed for this purpose and also it must be programmed to use edge detection for ATIN FAULT indicates faults d
57. is used towards memory and I O see Figure 33 D D D 31 0 D 31 0 OR O s gt MEMORY IU FPU MEC DEAR P DPARIO Figure 33 Memory and I O access with no parity Read access with parity In the case that parity or parity and EDAC is used the MEC will reflect the state of the DPAR on DPARIO towards the IU FPU see Figure44 Write access with parity In this case the TU FPU will drive the DPARIO pin on the MEC The MEC will check parity on the data driven by the IU FPU The DPAR signal 15 reflected on the DPARIO pin see Figure44 D D D 31 0 D 31 0 D IU FPU lt DPAR BM DPARIO i MEC E h E I O i CB 6 0 E gt CB 6 0 4 lt DPARIO DPARIO Figure 44 Memory and 1 O access with parity Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 444 3 3 1 1 4 Memory to MEC Parity Implementation If parity is enabled for memory programmable in the MEC the parity bit of the data word is emitted on the MEC signal DPARIO during store operations Since there are seven EDAC bits the straight forward approach would be to store the memory parity bit in the same memory device as the EDAC bits However due to the fact that the timing of EDAC checkbits and DPARIO is not the same some glue logic is need
58. l For the EEPROM worst case values for Hybrid Memory Product MEM8129 150 200 ns access time has been used Clock edges are denoted as follows ta b c q Where a cycle no as denoted in timing diagram referring to SYSCLK b SYSCLK or CLK2 c T denoting rising edge ork denoting falling edge d edge no within cycle for CLK2 each SYSCLK cycle equals two CLK2 cycles The following timing parameters have been used in this analysis ac245 tp Output Enable Disable time for 54 AC245 T 55 to 125 10 5 ns ac377 tpCkQ Propagation Delay for 54 AC377 T 55 to 125 11 0 ns ram trGLQV Output Enable Access Time 20 ns for M 65656 45 ns 10 ns for M 65608 25 ns ram trELQV Chip select Access Time 45 ns for M 65656 45 ns 25 ns for M 65608 25 ns ram trA VOV Address Access Time 45 ns for M 65656 45 ns 25 ns for M 65608 25 ns ram trGHQZ OE high to high Z 15 ns for M 65656 45 ns ns for M 65608 25 ns ram twDV WH Data Setup Time 25 ns for M 65656 45 ns 15 ns for M 65608 25 ns ram twW HDX Data Hold Time O ns for M 65656 45 ns O ns for M 65608 25 ns mec t9 MEC internal MEMCS valid Delay 20 ns mec t10 MEMCS Output Delay 15 ns mec t12 MEMCS Output latch Propagation Delay 8 ns mec t13 MEMBEN Output Delay 35 ns Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page B444 mec t15 MEMWR Output Delay
59. mec t13 ac245 tp mec t71 75 35 10 5 3 26 5 ns Margin 2 IU toesyscLKT t2cLK241 mec t13 ac245 tp iu tDIS 75 35 10 5 7 22 5 ns Timing chain 2 OE asserted to data available Time from bei koli to tosyscrk 75 ns t69 75ns worst case when t69 0 Margin 3 M 65656 MEC t syscLKT t2CLK211 mec t16 ram trGLOV ac245 tp mec t71 75 35 20 10 5 3 6 5 ns Margin 4 M 65608 MEC 75 35 10 10 5 3 16 5 ns Margin 5 M 65656 IU Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 3544 bsyscLKT t2CLK241 mec t16 ram trGLOV ac245 tp iu tDIS 75 35 20 10 5 7 2 5 ns Margin 6 M 65608 IU 75 35 10 10 5 7 12 5 ns Timing chain 3 MEMCS asserted to data available Time from liSYSCLKT to loSySCLKT 100 ns Margin 7 M 65656 MEC t syscLKT tisvsci KT mec t10 ram trELOV ac245 tp mec t71 100 15 45 10 5 3 26 5 ns Margin 8 M 65608 MEC t syscLKT tisyscLk mec t10 ram trELQV ac245 tp mec t71 100 15 25 10 5 3 46 5 ns Margin 9 M 65656 IU tosysci KT tisyscLk mec t10 ram trELQV ac245 tp iu tDIS 100 15 45 10 5 7 22 5 ns Margin 10 M 65608 IU t syscLKT tisyscLk mec t10 ram trELQV ac245 tp iu tDIS 100 15 25 10 5 7 42 5 ns Timing chain 4 Address stable to data available Time from USYSCL
60. memory When it is not possible for an application to use true dual port RAM to implement the exchange memory a true dual port memory must be emulated outside the MEC 1 e the MEC does not support any special arbitration for logical dual port RAM The only difference between exchange memory accesses and main memory accesses 1s that the MEC has to wait for the BUSY signal from the DPRAM connected to BUSRDY of MEC before the write strobes can be activated For this reason the MEC will introduce address wait states 1 e wait for BUSY when accessing the exchange memory After the address wait states the MEC knows whether the access 1s 1n conflict with another unit or not as indicated by the BUSY signal This means that in the exchange area the function of the BUSRDY signal is such that when BUSRDY is deasserted the exchange memory is considered busy The delay of the BUSY signal depends on the dual port RAM chosen A typical dual port RAM needs less than 80 ns to produce the BUSY signal and therefore it 1s typically sufficient that the MEC waits one clock cycle at the start of the access for the assertion of BUSRDY signal The address wait state phase will of course slow down the accesses towards the exchange memory but on the other hand the address decoding and protection mechanism can run in parallel and therefore it might be possible to perform the later part of the access with zero wait states If BUSRDY 1s asserted in the begin
61. ng the ERC32 core configuration is the system requirements on memory The MEC provides for a wide variety of RAM organisations supporting device memory sizes ranging from 8kx1 bits to 8Mx bits Parity and EDAC protection of RAM 15 programmable in the MEC In most systems EDAC protection of RAM is desired The non volatile memory used for system boot can be implemented as a normal word wide EDAC protected memory The PROM data bus then has a width of 32 bits accompanied by 8 check bits This configuration shown in Figure below yields maximum performance for Boot PROM access Note that the Boot PROM and RAM share the same buffers F ME RE PRE NP NES PAPER CURE RCE PEER ER SERRE RE PE a AE kN SEER NEEN NEE ee a a a ie PRE in aa ante iir ala od eee oh eRe al TETEA ETEA EA SIC RIEN ELI ratas SRE TOR AE SRE BOOT PROM 2 Figure 11 Basic Configuration with 40 bit Boot PROM Check bits 8 In many systems board space power consumption and component cost are driving factors The 40 bit wide Boot PROM typically reguires 5 devices The MEC provides an option to minimise the number of Boot PROM devices by accessing the PROM with a bus width of 8 bits In this configuration the MEC will perform four accesses to form one 32 bit word and feed it to the TU FPU The drawbacks of this option shown in Figure 22 below are that the performance 15 divided by four for Boot PROM access and that no check bit protection is pro
62. ning of the second cycle the normal wait state controlled access continues If BUSRDY is deasserted during the address wait state time the MEC will delay the access until the BUSRDY signal has been asserted and continue with the programmed normal data wait state controlled access Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1844 aaaaaaaaaaaiaaaiaaiaaaaaiiaiiaiaiaittaiaiaititaiaiiitatiiMtMtaiitMiMtaMiiMiMiMtaMiiMiMiMiMtlMtlMiMtMiiiMiMiMi MM Ctrl eu Error Ctrl N ii Data Check bits Exchange Memory Figure 66 System with I O and Exchange Memory Bus Ready Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1944 3 3 4 ERC32 Computer with DMA Slave Interface Figure 77 shows a tentative system with a slave DMA interface DMA UNIT aaa r ja Erra s Error Ctrl niet tp jpt ain E EE ST D RE RE os ee NE PROC a AN a oh ais pe i Sth eh RP MP PRE RE Neo BOOT PROM BYTE SELECT Check bits wo gt Exchange Memory Bus Ready Figure 77 System with Slave DMA Interface The DMA unit must once access has been granted drive all memory access control signals that the IU normally drives In case of time criticality during execution of a special region the application program might need to run without disturbance from a DMA access The concurrent error
63. oint Unit FPU The processor includes concurrent error detection facilities Memory Controller MEC which is a unit consisting of all necessary support functions such as memory control and protection EDAC wait state generator timers interrupt handler watch dog UARTs and test and debug support The unit also includes concurrent error detection facilities One or if a separate watchdog clock source 1s required two oscillators Buffers and latches necessary to interface with memory Memory Serial communications UART interface circuitry The above configuration is the simplest possible and is probably only usable for performance measurements etc A computer in a space application is most likely to have some additional Input Output interfaces apart from the serial communication implemented by the UART function of the MEC In addition to the basic bus interface an exchange memory area providing simultaneous access from the ERC32 and the external bus is supported by ERC32 and could thus be easily implemented For efficient Ada code execution an Ada Tasking Coprocessor ATAC might also be added to the system All of the above functions typically fits onto one printed circuit board in space applications depending on memory size For high reliability applications the concurrent error checking capability of ERC32 could be used This would then double the no of IU FPU components in the system In paragraph 3 3 various ERC3
64. ondition will normally lead to CPUHALT unless the MEC has been programmed to give reset When running SPARCMon CPUHALT is default The error can originate either from the IU FPU or the MEC CPUHALT Halt Indication This LED reflects the status of the HALT inputs of the IU and the FPU The CPUHALT can be generated either from the HALT button on the front panel from software halt or from error halt see SYSERR above 4 2 9 DEM32 Board Layout The DEM32 board layout can be found in DEM32 3 DEM32 V 3 USER S MANUAL MCD TNT 0021 SE issue 3 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 3344 4 3 Timing Analysis The timing analysis for the DEM32 has been performed for the three different access areas RAM EEPROM and I O ATAC In appendix 2 the electrical schematics of the DEM32 board is shown The signal names in the timing diagrams are as denoted in appendix 2 Unless otherwise noted the worst case values have been used in the timing analysis The timing for the IU is fetched from TUUM 14 MHz version The timing for the MEC is fetched from the MEC Rev A All timing parameters namedxtwhere x is a number refer to the MEC For buffers and latches military AC logic timing has been applied For the RAM worst case values for MHS M65656 45 ns access time which is a slower RAM than the RAM actually mounted on the board has been used The worst case values for MHS M 65608 25 ns access time has been used as wel
65. orresponds to channel A of the MEC UART Channel A is used by the monitor for host communication The Serial B connector corresponds to channel B of the MEC UART Channel B is used by the monitor for remote debugging Note that no hardware handshake signals are provided AII handshaking must be implemented by software e g XON XOFF 4 2 8 2 Heset Button Pushing the reset button on the front panel will result in a hardware reset of the DEM32 A hardware reset is automatically performed when powering on the DEM32 4 2 8 3 Halt Switch There is a halt function in the DEM32 Setting the HALT switch in ON position right will halt execution in the DEM32 by asserting the SYSHALT signal of the MEC During halt the IU FPU MEC including timers and UARTS are halted 4 2 8 4 Indicators There are three indicators on the front panel named SYSAV SYSERR and CPUHALT These indicators reflect the status of the corresponding pins of the MEC see RD7 SYSAV System Availability This LED 1s under software control It is deasserted unlit by hardware reset The monitor will assert SYSAV after successful completion of start up tests If the monitor detects any hardware error during start up SYSAV will remain unlit SYSAV is automatically deasserted when CPUHALT is active Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page B244 SYSERR System Error This output 1s asserted whenever an unmaskd error 1s detected by the MEC This c
66. put signals The generation and checking of internal parity is still active 3 3 1 1 2 IU FPU to MEC Parity Check If parity check is enabled by the MEC if the NOPAR signal is deasserted and RAM memory parity protection is enabled by programming the MEC and the 601MODE 602MODE signals are not asserted by the IU FPU parity will be checked on the following signals the address bus APAR the data bus DPARIO the control signals ASI and SIZE ASPAR and the control signals LDSTO DXFER LOCK WRT RD and WE using the IMPAR signal Note especially that the IU FPU signal DPAR shall be connected to the MEC signal DPARIO Assertion of the NOPAR signal will force the MEC to disable the parity checking of all signals related to the ERC32 local buses Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 1344 3 3 1 1 3 Memory and I O to MEC Parity Check If parity is enabled for memory and I O programmable in the MEC the parity bit of the data word is emitted on the MEC signal DPARIO during store operations During read operations the parity bit of the data word 1s expected on the same signal DPARIO Read access with no parity In the case that no parity is supplied the MEC calculates the parity and drives the DPARIO pin towards the IU FPU see Figure33 Write access with no parity In this case the TU FPU will drive the DPARIO pin on the MEC The MEC will check parity on the data driven by the IU FPU No parity signal
67. r mec t16 as 35 ns This analys shows that in some cases the data hold time can not be guaranteed for the worst case when the SYSCLK output delay is maximum t69 20 ns Lowest margin is when MEMBEN output delay gt 28 ns Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 3744 However a realistic assumption is that the timing of mec t69 and mec t16 is correlated so that if t69 1s maximum then t16 is near maximum giving more hold time than worst worst case 4 3 1 3 Data Setup Time to MEC During Store Data shall be available at tsysci KL With a setup time of mec t19 20 ns 10 tpDCIkB 1u tpop 35 ns D lt 31 0 gt output delay Timing chain I IU store data available Time from DSYSCLKL to t4SYSCLKI 200 ns Margin t3SYSCLKL SYSCLKL iu tpDCIkB mec t19 200 35 20 145 ns The margin is 145 ns 4 3 1 4 Data Setup Time to RAM During Store Data shall be available at MEMWRI deasserted with a data setup time of ram twDVWH Timing chain I IU store data available Time from 6syscr kJ to tacp Ko 175 ns mec t69 175 20 155 ns Worst case when SYSCLK output delay is maximum Margin 1 M 65656 t4CLK241 tosysci KJ mec t15 10 tpDCIkB ram twDVWH 155 mec t15 35 25 worst case when mec t15 is 0 95 ns Note that MEMWRI output delay mec t15 has the maximun value 35 ns Margin 1 mec t15 95 ns Margin 2 M 65608 t4CLK241 tosyscLkJ mec t15
68. t No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 4014 h ui I I I I I I I I I 2I IO T 4 5 SYSCLK E E A 31 0 TT GEE 11 GE C li LL K S2 C O tem MEMCS 0 t10 m MEMCS 1 SS MEMBEN RAMBEN E iu DDIR MEMWR1 MEMWR2 MHOLD OE D 31 0 CB 7 0 LA 31 0 Figure 1414 DEM32 RAM Load at 0Ws and Store at 1 Ws Sequence Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 4144 4 3 2 EEPROM Access The EEPROM access timing is determined by the IU MEC buffer and memory timing In Figure 15 the timing is shown for a load operation at 1 waitstate 10 MHz system clock As byte mode access is used each word fetch takes a total of 4 2 2 10 cycles 4 3 2 1 Data Setup Time to MEC During Load Data shall be available at amp syscKkT With a setup time of mec t71 3 ns Timing chain I MEMBEN asserted to data available Time from t cLK241 to t3syscL KT 175 ns mec t69 175 ns worst case Marginl tasyscLK tici koli mec t13 ac245 tpZB mec t71 175 35 10 5 3 126 5 ns Timing chain 2 OE asserted to data available Time from tcp kali to t3syscL KT 175 ns mec t69 175 ns worst case Margin 2 M 65656 t3sysCLKT ticLK2J1 mec t16 ram trGLQV ac245 tp mec t71 175 35 20 10 5 3 106 5 ns Margin 3 M 65608 t3sysCLKT ticLK
69. tes segment by software The RAM may be accessed at zero wait states programmable in the MEC 4 2 5 2 Memory Expansion In addition to the 2 Mbytes of nominal RAM an expanded RAM area is reserved in the board The DEM32 is able to access totally 4 Mbytes two separate nominal RAM banks of 2 Mbytes utilising MEMCS 0 and MEMCS 1 signals and one redundant bank of 2 Mbytes utilising MEMCS 8 signal excluding checkbits As mentioned before only one nominal RAM bank of 512 kwords 2 Mbyte and 512 kbytes check bits are implemented 4 2 5 3 Start Up PROM The board is equipped with 512 kBytes of start up PROM byte wide organised 8 bit option set in MEC The PROM is realised with one 512k x 8 Flash EEPROM allowing access with one wait state Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 2844 The start up PROM of the DEM32 contains system start up tests and the monitor AMON or GMON which has been adapted to the DEM32 board 4 2 6 DEM32 Memory Map The memory map of the DEM32 is defined by the MEC Only a small part of the possible MEC memory configuration is implemented in the DEM32 The memory map of the DEM22 is programmed on start up as shown in Figurel 212 Address Memory contents Size Bytes Data size and parity options hexadecimal 0x00000000 Boot PROM 8 bit mode 8 to 32 bit conversion No parity Only byte write 0x00080000 Non implemented Boot PROM area 15 5M 0x01000000 Non implement
70. th a setup time of ram twDVWH 25 ns for M65656 and 15 ns for M65608 Timing chain I Check bit data available Time from amp syscr KT to tacp koji 125 ns mec t69 105 ns worst case For the worst case l 1 The SYSCLK output delay 15 maximum mec t69 20 2 MEMWRI is deasserted without any delay mec t15 0 3 CB output delay has the maximum value of 35 ns mec t23 35 Margin 1 M 65656 tact Koli tasvscL KD mec t15 mec t23 ram twDVWH 105 0 35 25 45ns Margin 2 M 65608 tact K2l1 tasyscL KT mec t15 mec t23 ram twDVWH 105 0 35 15 55 ns The CB setup time to RAM is guaranteed forboth devices 4 3 1 8 Check Bits Hold Time to RAM During Store Check bit data shall be available at MEMWR see paragraph 3 3 1 1 4 3 3 1 1 4 deasserted with a hold time of ram twWHDX 0 ns For the worst case 1 The SYSCLK output delay is minimum mec t69 0 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 3944 2 MEMWRI is deasserted with a maximum delay mec t15 35 3 CB output valid to high Z delay has the minimum value of 2 ns mec t24 2 Timing chain I CB store data invalid Time from t4cj k2l1 to tssyscLKt 75 ns mec t69 75 ns worst case Margin 1 M 65656 and M65608 tssyscLKT tacLK2J1 mec t24 mec t15 ram twWHDX 75 2 35 0 42ns According to this analys the CB hold time to RAM is guaranteed foboth memory types Documen
71. u Design reso Mgr WRT Dummy Dangle 2 i Designat ion CIRCU DIAGRAM Ty evovo DEMS2 Computer SIZE 0 Approved Top drawing LOCK The copuright ownership of this document is and will remain ours C SSO n S pa ce The docunent must not be used without our authorization or brought to the knowledge of a third party Contravention will be prosecuted ORGINALFORMAT Al 104 S 8 JUL f gt Ke E TMOL D CK1100 14 CMEXCe 0 20 LOCK E 2 21 Ee SYSRESET gt d SYSHALT CS 2 r or FICTCIL lt 6 0 2 SS YSCLK 1 0 M rem gt gt CPUHAL T EXTINT C4 AT s M C gt MEMCS 8 1 0 RIS Fees EPI 1 J CO gt MEMIR2 _J302 m Pass CET 1 CMODE a ro RNJJ16 CONN_IDC20 E ERR a RN2 4 RNDS MEC RESET 15 TUHHERR CMODE TU TUERR 8 SYSRESET suum 5 gt Pe HALT HNERROR e Pe SYSHALT B T i 2 CLK co CLK2 RTOUS RTOUS A RESET ERROR FPU 0 TN ALE gt ALE CHODE BRUTS Bute Erk ROMCS SIN 5 HALT HWERROR IUERR ER T 6 R7 5 VEMMRI RN2 B RN2 5 Le CLK IUCMPERR js MEHBEN BHOLD 16 ATTE pur 8 5 EG HESSE MEMBEN HOLDA 3 FPUHWERR noose DDIR DUIK HOLDE 4 A OE 1 0 D gt OE 1 0 mu EXC BUSRDY IOSELO
72. vided Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page RER EE IEPEN TIENE E EEEREN e t RENE ER RE ENT le EEE PRET DR RE PR CO PS TN DE a CIRE ah m SEE RCE ER RSR RER UE ER E AC DER t aaa VRP INGA muqu E EE aaa SOc hee Ae Onder E ati aya aa tu uwa UE CREER SR BOOT PROM BYTE SELECT Figure 22 Basic Configuration with 8 bit Boot PROM The MEC supports programming of boot PROM if implemented with EEPROM technology both for manufacturing pre programming and embedded system maintenance reprogramming 3 9 hell ERC32 Parity The ERC32 chipset is designed to allow for many system configurations The design information provided in ERCFNC and the IU FPU MEC specifications 1s not focused on typical applications The following is a discussion on the different parity checking options the system described in Figure22 can have 3 3 1 1 1 IU to FPU Parity Check Apart from the signals connecting the IU and FPU in a standard version 7 SPARC system ERC32 provides an additional set of signals for error detection If the 601 MODE 602MODE signals are not asserted by the IU FPU parity will be checked on the control signals between the IU and FPU The parity is provided on FIPAR IFPAR signals The HWERROR signal serves as a status output to indicate parity errors Forcing 601 MODE 602MODE signals low will disable the parity checking of all input signals The IU and FPU will operate with the standard in
73. ype reg pos istype reg pos istype reg pos is is is is type reg pos type reg pos type reg pos type reg pos No strobes active waiting for Waiting for RELEASE from ATAC Go Goto WAI Waiting Goto WR Goto WAI to READ2 T for RELEASE from ATAC TE 3 T No strobes active waiting for IOSEL N negative or IOSEL N positive or IOSEL N positive IOSEL N positive Page 4714 Document No MCD TNT 0020 SE Date 10 Apr 1997 Issue 3 Page 844 States clk CLK RD 01 fb Q2 fb WR N 01 fb O2 fb BUSRDY N States fb READ1 States fb WRITE1 States fb IDLE BUSERR is not used BUSERR N 1 tate diagram States tate IDLE if SEL_N amp IOWR_N then Start read access goto READI else if SEL N amp IOWR_N then Start write access goto WRITEI else goto IDLE n n state READI if RELEASE then Waiting for RELEASE from ATAC goto READ2 else if SEL_N then If no cycle then IDLE goto IDLE else goto READ1 Else wait here state READ2 goto READ3 state READ3 goto WAIT state WRITEI if RELEASE then Waiting for RELEASE from ATAC goto WRITE2 else if SEL N then If no cycle then IDLE goto IDLE else goto WRITE1 Else wait here state WRITE

ERC32 System Overview, Saab Ericsson, 04/1997

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