EK-KK11A-UG-001 KK11-A Cache Memory Users Guide Oct78
Contents
1. 1 2 Cache Memory i dy ee 1 2 iii Figure No v v9 t3 029 N N Table No FIGURES Cont Title Page Direct Mapping Cache Memory System 1 3 Cache Installation Diagram 2 3 Power Configurati on Schematic enne ettet eee ehe tbe abis sob aso kt 2 5 Troubleshooting Flowchart 3 3 Backplane Jumpers tease 3 8 TABLES Title Page Cache Responses to Hit Miss Operations 1 4 5 Power Consumption For Some Common Options 2 4 Maintenance Equipment Required 3 1 iv PREFACE This manual describes the 11 Cache Memory option to the KD11 EA central processing unit of the PDP 11 34A system The user must be familiar with the KD11 EA to completely understand the contents of this manual The following documents are useful references KDI11 EA Central Processor Maintenance Manual EK KDIEA MM 001 KDII EA Print Set M P00043 KK112. 1 1 CACHE MEMORY ORGANIZATION 1 1 Addressing Cache ciii 1 3 Milt processing 1 4 NPR Memory References 1 5 Unibus Regist ers a n y a 1 5 Performance aa sau a uay 1 5 INSTALLATION MT 2 1 UNPACKING AND INSPECTION 2 1 cs 2 1 Inspection inta queis 2 2 PRE INSTALLATION CHECK 2 2 BA11 KA MOUNTING BOX INSTALLATION PROCEDURE 2 2 BA11 L MOUNTING BOX INSTALLATION PROCEDURE 2 6 OPERATION xi N 2 7 CHECKOUT PROCEDURES iuie l a RO ADHI eee 2 7 SERVICE MAINTENANCE PHILOSOPHY 3 1 SYSTEM MAINTENANCE AND TESTING 3 1 TROUBLESHOOTING GUIDELINES 3 1 FIGURES Title Page General System Architecture
3. 1024 WORDS TAG FIELD i l I I 1 0 1023 _ pane 4 BLOCK SIZE OF 1 SET SIZE OF 1 VALID BITS TWO SETS SET OF 1024 A BITS SET OF 1024 B BITS 1900 Figure 1 2 Cache Memory Format 1 2 Figure 1 3 Direct Mapping Cache Memory System The 1024 cache index positions contain 28 bits each The tag field contains seven address bits Each position contains a tag parity bit and two valid bits One valid bit is currently active allowing the other bit to be cleared concurrently The use of two sets of valid bits allows the cache to be flushed cleared by switching to the second previously cleared bit set and then clearing the first set of valid bits This method allows the use of one set of valid bits while the other set is being cleared useful in multi processing applications The data field of the index position consists of two 8 bit bytes of data each with byte parity 1 4 1 Addressing Cache When addressing cache the PDP 11 34A uses an 18 bit address formatted as shown below 17 11 10 1 0 POSITION oe Ah YY CHECKED AGAINST ADDRESS OF 28 BIT WORD BYTE FIELD SELECTS TAG FIELD OF IN CACHE Hi OR LO BYTE INDEX WORD MA 1899 The lower part of the address 10 1 is applied against the IK cache matrix and the high order bits 17 11 are checked against the tag field of the index word obtained data field in cache If the tag field in the address
4. SEE NOTE 6 SEE NOTE 1 SEE NOTE 6 SEE NOTE 6 M8265 SEE NOTE 6 SEE NOTE 2 PARTS LIST 5 4 3 2 1 5 1 CACHE MEMORY IKK11 A D UA M8268 0 0 3 CONFIGURATION PAP _INTERCONN 40 PIN D UA H8821 0 0 2 SEE NOTE 3 1 TRICONN BOARD D UA H8822 0 0 1 3 42 1 3 261 De NOTES 5 44 3 2 1 SLOT CONFIGURATION C SLOT CONFIGURATION D 1 THE W9042 EXTENDER BOARD ASSY IS SLOT SEE NOTES 3 amp 4 SEE NOTE 5 STORED IN THE BACKPLANE AND IS CONFIGURATION B USED FOR SOME MAINTENANCE OPER SEE NOTE 5 MAG2272 ATIONS 2 MODULES M8265 AND M8266AREPART 4 CONFIGURATION C SHOWS SLOT UTILI 6 M8267 5412416 AND W9042 ARE PART OF KD11 EA AND ARE SHOWN FOR REF ZATION FOR EITHER KK11 A OR FP11 A OF FP11 A AND ARE SHOWN FOR REF ONLY WHEN ONLY ONE IS PRESENT ONLY 3 ALL CONFIGURATIONS SHOWN ARE 5 CONFIGURATIONS B amp D SHOW TYPICAL USED IN THE BA11 K 10 5in BOX MAINTENANCE SET UP OR BA11 L 5 1 4 BOX MA 2278 Figure 2 1 Cache Installation Diagram 2 3 Table 2 1 5 V Power Consumption For Some Common Options Mounting Code Option Number ARII 10 bit A D converter 40 DLII WA B Line interface and clock 20 Quad DRII K Digital 1 0 2 5A Quad DUP II Synchronous line interface 3 6 KY11 LB Programmer s console interface 3 0A Qua
5. ANY NPR DEVICES BETWEEN CACHE AND MEMORY ALL MEMORY MUST BE BETWEEN THE CACHE MODULE AND ALL NPR DEVICES REMOVE RESPECTIVE NPR DEVICE AND REINSTALL IT ON THE OTHER SIDE OF THE MEMORY SEE FIGURE 1 1 OF CHAPTER 1 IN CACHE MSYN IS IN HIBITED THUS ABORTING THE MAIN MEMORY TRANSFER CACHE HITS BY THE CPU RESULT IN THE DATA BEING TRANSMITTED OVER THE AMUX LINES READ MISSES AND WRITE HITS WHICH RESULT IN CACHE UPDATES ARE ACCOMPLISHED BY THE CACHE CAPTURING THE DATA FROM THE UNIBUS AS THE CPU MAIN MEMORY TRANSACTIONS OCCUR DMA TRANSFERS TO MEMORY ARE MONITORED BY THE CACHE IN ORDER TO INVALIDATE CACHED LOCATIONS THIS REQUIRES THAT MEMORY BE LOCATED ELEC TRICALLY CLOSE TO THE CACHE PRESS CONTROL START CAUSING EXECUTION OF THE INSTRUCTION HALT THE CPU AND EXAMINE THE CACHE HIT REGISTER ADDR 777752 19 DOES THIS REGISTER CONTAIN 77 22 CACHE APPEARS TO BE WORKING RUN CACHE DIAGNOSTICS 2281 Figure 3 1 Troubleshooting Flowchart Sheet 4 of 5 3 6 SHEET 4 LOAD ADDRESS OF THE CACHE CONTROL REGISTER ADDR 777746 EXAMINE CCR BITS THE CACHE MEMORY ERROR REG ADDR 777744 EXAMINE CMER BITS HIGH BIT3 OR FORCE MISS LOW ARE BIT15 THE PA es THE ONLY BIT BITS SET IN THE CMER CMER CHECK FORA INITIALIZE PARITY ERROR CPU IN BACKING STORE MAIN
6. MEMORY DID RUN CACHE THE CMER DIAGNOSTICS BITS CLEAR CFKKAA RUN CACHE RUN DECX11 MA 2289 Figure 3 1 Troubleshooting Flowchart Sheet 5 of 5 3 7 SEE VIEWA 15V JUMPER 15V JUMPER 0011 5V JUMPER PIN A01A1 NOTES 1 JUMPERS SHOWN ARE 15 TO 15B 15 TO 15B 5 TO 5B 2 USE 20 INSULATED BUS WIRE FOR JUMPERS 11 5343 Figure 3 2 Backplane Jumpers KK11 A CACHE MEMORY USER S GUIDE Reader s Comments EK K K11A UG 001 Your comments and suggestions will help us in our continuous effort to improve the quality and usefulness of our publications What is your general reaction to this manual In your judgment is it complete accurate well organized well written etc Is it easy to use What features are most useful _ am PIER NE INC RR E What faults or errors have you found in the manual _ Does this manual satisfy the need you think it was intended to satisfy Does it satisfy your needs __ I Why Please send me the current copy of the Technical Documentation Catalog which contains information on the remainder of DIGITAL s technical documentation Name _ 2 thao Mm at ALTO CL ht tee che tte Title i cce Oily Company State County Department TORNO manu ie ec t Zip Ss it S Additional copies of this document are available from Digital Equipmen
7. A Print Set MP00574 11 Print Set KY11 LB Programmer s Console Interface Module Operation and Maintenance Manual EK KY1LB M M 00 CHAPTER 1 INTRODUCTION 11 OVERVIEW The KK11 A is a cache memory option to the PDP 11 34A s KDII EA processor The cache is small high speed memory that maintains a copy of previously selected portions of main memory it is designed to decrease central processing unit CPU to memory read access time 12 PHYSICAL DESCRIPTION The KK11 A is implemented on a hex multilayer module M8268 that contains a 1024 word high speed random access memory RAM organized as a direct mapped cache with write through com patible with the current version of the PDP 11 34A The M8268 module interfaces to the KD11 EA processor M8265 module via a 40 pin over the top connector H8821 or H8822 The only power required is 5 Vdc at 4 A maximum Figure 2 2 13 SYSTEM ARCHITECTURE Cache operates as an associative memory in parallel with the Unibus main memory but with its own high speed data path AMUX lines that are also used by the FP1 1 A a floating point option Cache reads by the CPU result in data being transmitted over the AMUX lines Read misses desired data is not present in cache and write hits bus address and cache location match which result in cache updates are accomplished by the cache capturing the data from the Unibus as the CPU main memory transaction occurs Direct memory access DMA transf
8. for proper CPU verification Ensure that the CPU is operating properly by running the following diagnos tics DFKAA PDP 11 34 basic instruction test DKKTH KT exerciser PDP 11 34 CZQMC 0 124 memory exerciser 16K cache memory option for the PDP 11 34A consists of the following M8268 Cache module H8821 20 pin over the top OTT connector H8822 20 pin over the top OTT connector 24 BAII KA MOUNTING BOX INSTALLATION PROCEDURE The 11 mounting box is capable of delivering 64 A of 5 Vdc which is supplied by two H7441 regulators The 5 V is distributed to the backplane the 11 via five Mate N Lok connectors One H7441 5 Vdc regulator supplies two Mate N Lok connectors the other H7441 5 Vdc regu lator supplies the remaining three Mate N Loks The PDP 11 34A CPU backplane DDII PK attaches to the BA11 KA power distribution board via connectors J9 and J11 thus allowing the CPU backplane the full capabilities of one H7441 regulator i e 32 A of 5 Vdc To prevent overloading of the 5 Vdc the current drain of the modules contained in the DD11 PK should not exceed 32 A Table 2 1 If the total current drain used by the devices in the 11 exceeds 61 A without cache an expander box will be needed Figure 2 1 NOTE To prevent overloading of the 5 Vdc the current drain should be calculated The current drain should not exceed 32 A in the DD11 PK backplane 2 2 SEE NOTE 1
9. 1 5 Check that both FORCE MISS switches S1 and S2 are on Have both BATT switches pointing toward the console 6 Complete steps 14 18 in the previous procedure 25 MOUNTING BOX INSTALLATION PROCEDURE The 13 3 cm 5 in 11 1 mounting box can contain a power supply with either a 32 A or25 A 5 V regulator Use the following chart in determining whether you have the proper 32 A supply Current Regulator 25A H777 AA AB BA BB 32A H777 CB DA DB NOTE To prevent overloading of the 5 Vdc make sure that the 5 Vdc current consumption does not ex ceed the capacity of the regulator When using other than the M9301 YF bootstrap terminator the handle of the bootstrap terminator may inter fere with the H8822 connector Therefore carefully remove that part of the handle which interferes 2 6 Perform the following steps when installing the KK11 A in a BA11 L mounting box 2 Slide the wire frame out of the wrap around Turn CBI to off first then turn the DC ON DC OFF switch to DC OFF If the K Y11 LB is present remove the two maintenance connectors from the M8266 mod ule Make sure that the DD11 PK is Rev C or later Remove the M8266 module from slot and visually verify that ECO M8266 4 R2 1 kQ is installed NOTE When 2 is less than 1 change this resistor per instructions on M8266 ECO No 4 Replace M8266 into slot 1 Remove any module in slot 3 and careful
10. 16 over the top connector Remove the 8821 connector from the M8265 and M8267 modules 2 4 10 Remove any module in slot five and carefully reconfigure the modules in the DD11 PK backplane Figure 2 2 11 Insert the M8268 module into DD11 PK slot 5 NOTE To prevent overloading of the 5 Vdc make sure that the current drain does not exceed 32 A Calcu late power consumptions using 4 for 1 cache 7 A for FP11 A and 11 5 A for KD11 EA CPU 11 58 FP1 1 A FPP 7 08 lt NOTES 1 IF THE FP11 A IS NOT USED THE 7 0a i MAY BE USED FOR 64KW of MS11 JP 7 PARITY MEMORY OR 32KW OF 11 KK11 A CACHE 4 08 PARITY CORE MEMORY IN SLOTS 6 7 HEX OR QUAD AND 8 HEXORQUAD gt gt _HEX OR QUAD KY11 LB 3 08 2 IF THE FP11 A IS USED AN ADDITIONAL 0011 IS REQUIRED FOR ALL MEM ORY DUE TO THE POWER RESTRICTIONS UNIBUS QUAD 5 IN THE FIRST 9 SLOT BACKPLANE UNIBUS DL11 W 2 2 00 3 BEFORE PLUGGING IN ANY ADDITIONAL 10a QUAD INTERFACES INTO THE EMPTY SLOTS IN PARITY THE CPU BACKPLANE PLEASE DO A 1 64K BYTE 5 08 2 32K BYTE 4 08 MM11 YP OR MS11 JP 1 64K BYTE 5 0a 2 32K BYTE 4 0a POWER CONSUMPTION CHECK IN OROER TO ENSURE THAT THE 32 AMP POWER REGULATOR LIMIT FOR THAT CPU BACK PLANE HAS NOT BEEN EXCEEDED 11 OR MS11 JP HEX OR QUAD HEX OR QUAD QUAD 1 SYSTEM UNIT MA 2279 Figure 2 2 Power Conf
11. ANE OTHER THAN THE CPU BACKPLANE IF THE JUMPER IS IN THE CPU BACKPLANE ADD 5 AMPS OF 5 VOC FOR EACH MOS MEMORY BOARD NOT IN THE CPU BACKPLANE CPU BOX ONLY TO CURRENT DRAIN TOTAL FOR CPU BACKPLANE MA 2282 SHEET 2 CACHE MUST BE IN SLOTS 3 OR 5 ONLY 1134A SYS 15 KK11 A IN SLOT 5 INSTALL CONN AND ENSURE THATITIS SEATED PROPERLY H8822 OTT INSTALLED WITH ARROW POINTING TO SLOT 1 OTT OVER THE TOP CONNECTOR PROP PROPERLY 15 H8821 OTT REMOVE CONN CONN INSTALLED AND INSTALL WITH ARROW PROPERLY POINTING TO ARROW SLOT L I SLOT 1 BACKPLANE INSTALL HIT L ECO WIRE CONNECTIONS INSTALLED IN THE ECO WIRE CO1E1 TO BO2A1 BACKPLANE 61 AND S2 ARE BACKPLANE ON BOTH SWITCH HANDLES FACE CONSOLE BOTH FORCE MISS SWITCHES 51 AND 52 SET BOTH SWITCHES ON 15 CONTINUITY VISUALLY INSPECT CACHE HIT L BETWEEN CACHE MODULE AND HIT L AT BACKPLANE FOR BROKEN WIRES 802A1 BAI BACKPLANE AND 00 5 M8268 CONNECTORS OR ECO 4 M8266 MODULE INSTALL CACHE OTHER DEFECTS R2 1 KQ HAVE ECO 4 1 KQ R2 MODULE INSTALLED MA 2263 Figure 3 1 Troubleshooting Flowchart Sheet 3 of 5 SHEET 3 LOAD ADDRESS LOCATION 200 AND DEPOSITA BRANCH SELF 777
12. EK KK11A UG 001 KK11 A cache memory user s guide digital equipment corporation maynard massachusetts 166 Edition October 1978 The drawings and specifications herein are the property of Digital Equipment Corporation and shall not be reproduced or copied or used in whole or in part as the basis for the manufacture or sale of equipment described herein without written permission Copyright 1978 by Digital Equipment Corporation The material in this manual is for informational purposes and is subject to change without notice Digital Equipment Corporation assumes no re sponsibility for any errors which may appear in this manual Printed in U S A This document was set on DIGITAL s DECset 8000 computerized typesetting system The following are trademarks of Digital Equipment Corporation Maynard Massachusetts DIGITAL DECsystem 10 MASSBUS DEC DECSYSTEM 20 OMNIBUS PDP DIBOL OS 8 DECUS EDUSYSTEM RSTS UNIBUS VAX RSX VMS IAS PREFACE CHAPTER 1 pand jud pd Fo WN gt 2 2 1 2 2 2 2 1 2 2 2 2 3 2 4 2 5 2 6 2 7 CHAPTER 3 W U GJ U N Figure No 1 1 1 2 CONTENTS Page INTRODUCTION OVERVIEW u R quisu 1 1 PHYSICAL DESCRIPTION 1 1 SYSTEM ARCHITECTURFE
13. OES Troubleshooting Flowchart Sheet 1 of 5 CURRENT DRAIN EXCEED 28 AMPS WITHOUT YES SPACE ALLOW FOR EXPANDER BOX amp CURRENT AVAILABLE YES NO NO DOES CPU BACKPLANE EXCEED 28 AMPS WITHOUT CACHE YES MUST USE AN EXPANDER BOX BA11 KA MOUNTING CURRENT IN BOX EXCEED 61 AMPS WITHOUT KK11 A INSTALLED 6 MUST USE EXTENDER BOX NO 2284 CACHE SLOT THIS CONCLUDES THAT BATTERY BACKUP IS NOT INSTALLED SHEET 1 DOES 5 VDC 6 0 VDC 5 AT SLOT WHERE CACHE 15 INSTALLED YES ANY MOS MEMORY IN THE SYSTEM YES ARE BATTERY BACKUP JUMPERS INSTALLED ON BA11 KA BOX ADJUST 5 VDC REGULATOR H7441 TO 5 20 VOLTS NO THEN SYSTEM SHOULD HAVE CORE BATTERY BACKUP IS INSTALLED amp NO JUMPERS YES QUMPER CONFIGURATION JUMPER CONFIGURATION THE CPU ONLY SHOULD OD11 PK 5 VB gt 5 V JUMPER IN HAVE JUMPERS FIG INSTALLED 15 15 VJUMPER IN 4 5 15 VB gt 15 V JUMPER IN I eg ete J3UMPERIIN E JUMPER CONFIGURATION ALL OTHER PER CONFIGURATION BACKPLANES DD11 DK CK i IN THE CPU 5 VB gt 5 V JUMPER OUT BOX SHOULD BE 15 VB 15 V JUMPER IN 15 VB 15 V JUMPER IN EVE IS m Figure 3 1 Troubleshooting Flowchart Sheet 2 of 5 ANY MOS MEM IN ANY BACKPL
14. a DEC XII monitor the QABM monitor must be patched when the command for cache on is given The patch for this problem is MOD 13136 240 13140 240 CHAPTER 3 SERVICE 3 1 MAINTENANCE PHILOSOPHY The field maintenance and repair philosophy reflects a module replacement approach Once the cache has been identified as the failing option in the PDP 11 34A system the module should be replaced The faulty cache is returned to the Maynard facility in Massachusetts or to European Depots for repair whichever location is feasible Because of the complexity of the cache module and its etch width on site component level repair is not encouraged The standalone diagnostics should be run to detect the cache module failure 32 SYSTEM MAINTENANCE AND TESTING For a PDP 11 34A system that is unable to load diagnostics use procedures in Chapter 6 of the PDP 11 34A System User Manual to diagnose the problem Table 3 1 lists the maintenance equipment required to troubleshoot the cache Table 3 1 Maintenance Equipment Required Equipment Manufacturer Model Type Part No DEC Part No Oscilloscope Tektronix Volt Ohmmeter VOM Triplett 29 13510 Unwrapping Tool Gardner Denver 505 244 475 29 18387 DEC Catalog 11812A Hand Wrap Tool Gardner Denver A 20557 29 29 18301 DEC Catalog 11811A Wire Strippers Miller 1015 29 13467 Module Extender W9042 Boards 2 Tektronix type 453 oscilloscope is adequate for most test p
15. alid bit on cache hits Conditional Cache Bypass A virtual page can be defined such that all memory references to that page by the CPU result in being bypassed LOCK ASRB Instruction Guaranteed ownership of the cache for the duration of the destination operand cycle must operate in bypass mode Not implemented in the KD11 EA Processor 1 4 1 43 NPR Memory References Ifa DMA hit occurs during a read non bypass mode the cache is not affected bypass mode cache is invalidated unconditional cache bypass Table 1 1 DMA hit occurs during a write non bypass mode or bypass mode cache is invalidated If a DMA miss occurs during read or write bypass and non bypass modes cache is not affected 1 4 4 Unibus Registers The following hardware registers are implemented in the cache Cache Memory Error Register CME Address 777 744 Parity error detection of cache memory high byte low byte and tag Cache Control Register CCR Address 777 746 The state of specific CCR bits control 1 valid UCB and flush cache 2 the response of the cache to parity errors and 3 the occurrence of CPU forced misses Cache Maintenance Register CMR Address 777 750 Contains one read write bit used for memory system maintenance Cache Hit Register CHR Address 777 752 Contains the seven bits of the tag store memory of the last valid access and indicates the number of cache hits on the l
16. ast six CPU accesses to non I O page memory 1 4 5 Performance The cache system is intended to simulate a system having a large amount of moderately fast memory Therefore the system contains a small amount of very fast memory cache and a large amount of slow memory backing store The cache system works because it can successfully predict which words a program will require most of the time Program behavior is such that cache hits should occur 85 to 90 percent of the time substantially decreasing average access time Unibus Transactions For a normal memory read MM11 DP BUS BUSY is asserted for 1 2 us cache hit read results in the CPU asserting BUS BUSY for approximately 450 ns Thus for every cache hit about 750 ns are saved CHAPTER 2 INSTALLATION 2 1 SCOPE Information for installing the KK11 A Cache Memory option and checkout procedures to ensure proper operation of the cache and the system are provided in this chapter The following tools are required No 2 Phillips screwdriver Multimeter with ohm capability Diagonal cutting pliers Soldering iron 40 watt Solder sucker Spares kit Control Distribution Wire wrap tools 22 UNPACKING AND INSPECTION NOTE Customer should not unpack the cache memory option unless a DIGITAL representative is present to do so voids the warranty 2 2 1 Unpacking If the customer s receiving area procedures require it and or to facilitate inventory the shipment may be moved to
17. d PDP 11 34 CPU backplane 180 DECprinter 1 5 Quad MS11 FP 8K MOS memory 20 MSI1 JP 16K MOS memory 20 3 0A Hex Quad MMII DP 16K core memory 3 0A 2 Hex M7850 Parity control LOA DH module M9301 Bootstrap 20 DH module M9302 Unibus terminator DH module RX Floppy disk 1 5A Quad TMB Tape control 6 0 A 501 LPIIW V Printer 1 5A Quad 2 50 2 Hex FP1 1 A PDP 1 1 34 floating point Hex processor FPP DLI1A E Asynchronous line interface Quad DUI Synchronous line interface Quad KGII CRC generator Quad RKII D RK05 controller SUt KDII EA PDP 11 34 A CPU 2 Hex M9312 Bootstrap DH module RK611 2SUst RK06 controller DH double height 1480 single unit Perform the following steps when installing KK11 A with the FP11 A present 1 2 Turn system power OFF Extend the BA11 KA mounting box from the system Remove the top cover by loosening the screw at the side then slide the cover off If the K Y11 LB is present remove the two maintenance connectors from the M8266 Remove the 54 12416 OTT connector from the M8266 and M8267 modules Remove the M8266 module from slot 1 Visually verify that M8266 ECO No 4 is installed by checking that resistor R2 is 1 kQ NOTE Where R2 is less than 1 install a 1 resistor per instructions on M8266 ECO No 4 Replace M8266 into slot 1 and replace the 54 124
18. ers to memory are also monitored by the cache Figure 1 1 14 CACHE MEMORY ORGANIZATION Cache memory consists of twenty eight 1024 X 1 RAM chips arranged as shown in Figure 1 2 Specific implementation of the cache memory organization for the PDP 11 34A is as follows Cache Characteristics PDP 11 34A Implementation Address mechanism Direct mapping allows each word from main memory only one possible location in cache Requires only one address com parison Figure 1 3 Block size Block size of one every time a fetch to the backing store main memory occurs only one word is allocated to cache in the event of a miss Set size Set size of one there is one unique location in cache for any given word from backing store If a miss occurs only one cache location is available for data to be written into Write through Data from a write operation is written into cache and simulta neously copied into main memory Maintains main memory backing store with a valid copy of all data 1 1 Ir MISSES W HITS NPR DEVICES NOTE ALL MEMORY SHOULD BE LOCATED BETWEEN THE CACHE AND ALL NPR DEVICES 1896 Figure 1 1 General System Architecture 28 1024X1 RAM CHIPS PARITY PARITY VALID BITS i i ByrE o evre e ADDRESS 17161514 1312 11 P Bla 15 14 13 12 11109 8 7 6 5 4 3210 CACHE INDEX POSITIONS DATAFIELD 0
19. iguration Schematic 12 Install the H8822 connector on the M8265 M8267 and M8268 modules slots 2 3 and 5 respectively Make sure the arrow on this connector points toward slot 1 13 Check that both FORCE MISS switches S1 and S2 are on Have both switch handles point ing toward the console 14 Loosen both screws on the bottom of the BA11 K A mounting box and remove the cover When using other than the M9301 YF bootstrap terminator the handle of the bootstrap terminator may inter fere with the H8822 connector Therefore carefully remove that part of the handle which interferes 2 5 15 Check for continuity between backplane connection 1 1 and 02 1 This is the cache hit line if not present a jumper 30 gauge wire DIGITAL P N 91 05740 should be installed Then recheck for continuity 16 Replace the bottom and top covers and slide the BA11 K into the system chassis 17 Power up the system 18 Verify the CPU cache and FP11 A by running the diagnostics listed in Paragraph 2 7 To install cache when the FP11 A is not present perform the following steps 1 Repeat steps through 8 2 Remove any module in slot 3 and carefully reconfigure the modules in the DD11 PK back plane Figure 2 2 3 Insert the M8268 cache module into slot 3 of the DD11 PK 4 Install the H8821 connector on the M8265 and M8268 modules slots 2 and 3 respectively Make sure that the arrow on this connector points toward slot
20. ly reconfigure the system Insert the M8268 cache module into DD11 PK slot 3 or 5 Install the H8821 or H8822 connector on the M8265 and M8268 modules slots 2 and 3 or slots 2 and 5 respectively Make sure arrow points toward slot 1 Check that both FORCE MISS switches 51 and 52 on Have both switch handles point ing toward the console Reconnect the KY11 LB maintenance cable to the M8266 module Turn CBI on and slide the wire frame inside the wrap around carefully Turn DC OFF to DC ON Verify CPU memory and cache by running the diagnostics listed in Paragraph 2 7 2 6 OPERATION The cache module is program transparent The only observable effect while in operation will be reduced program run time 2 7 CHECKOUT PROCEDURES Run CPU and PDP 11 34A cache diagnostics for verification of the functionality of the options PDP 11 34 Diagnostics DFKAA PDP 11 34 Basic instruction test DFKAB PDP 11 34 Traps test DFKAC PDP 11 34 EIS instruction test DKKTH KT exerciser PDP 1 1 34 CZQMC 0 124K memory exerciser 16K 2 7 e PDP 11 34A FPP Diagnostics DFFPB PDP 11 34 FPP Diagnostic Part 1 DFFPB PDP 11 34 FPP Diagnostic Part 2 DFFPC PDP 11 34 FPP Diagnostic Part 3 PDP 11 34 Cache Diagnostics PDP 11 34 Cache diagnostics The startup procedure is non stanard form A RUN command is required in addition to the normal load and go at address 200 Procedures are included with the diagnostic medi
21. matches the tag field stored with the data in cache a hit is designated If the fields do not match it is designated as a miss The processor always looks for data in the fast cache memory first If a CPU hit occurs during a read non bypass mode Table 1 1 data is read from cache in bypass mode cache is invalidated e If a CPU hit occurs during a write non bypass mode data is written into cache in bypass mode cache is invalidated f a CPU miss occurs during a read non bypass mode data and tag are written into cache in bypass mode cache is not affected f a CPU miss occurs during a CPU write non bypass or bypass mode cache is not affected Table 1 1 Cache Responses to Hit Miss Operations DMA Miss Read Not Bypass Affected Read Not Bypass Affected Write Not Bypass Affected Write Not Affected DMA hit miss operations are discussed in Paragraph 1 4 3 Unconditional bypass 1 4 2 Multiprocessing DMA Hit Not Affected Invalidate UCB t Invalidate UCB t Invalidate Cache Read Invalidate Invalidate Write Data Write Valid Additional functionality is required to perform multiprocessing Unconditional Cache Bypass CPU Miss Write Data Write Tag Write Valid Not Affected Not Affected Not Affected In bypass mode all memory references are forced to be misses and to invalidate clear v
22. rocedures Type 454 or equivalent may be required for some measurements 33 TROUBLESHOOTING GUIDELINES The following guidelines are provided for debugging failures in the cache memory module installed in a PDP 11 34A system Standard PDP 11 34A diagnostics should be run first before attempting to follow the procedures outlined in this section 3 1 To verify the system integrity run the following diagnostics in the sequence given below DFKAB Traps Test at lease Rev C DFKAA PDP 11 34 CPU Test DFKAC EIS Test CZQMC 0 124K Memory Exerciser If the 11 option is included with the system run the following diagnostics DFFPB PDP 11 34 FPP Diagnostic Part 1 DFFPB PDP 11 34 FPP Diagnostic Part 2 DFFPC PDP 11 34 FPP Diagnostic Part 3 The flowchart in Figure 3 1 is a helpful tool in troubleshooting the system START HAVE ALL DIAGNOSTICS RUN TO COMPLETION VERIFY VIA SYSTEM SERIAL NAME TAG IS THE PDP 11 34A DRAIN IN THE 11 34A CPU BACKPLANE IS THE THE CPU BOX TYPE 10 6 INCHES CALCULATE THE 5 CURRENT REFER CHAPTER 6 OF THE 11 34 USER S MAN CACHE MEM SHOULD NOT BE INSTALLED ON ANY SYS OTHER THAN AN 11 34A Figure 3 1 THE CURRENT DRAIN EXCEED 28 AMPS WITHOUT KK11A INST MUST USE AN EXPANDER BOX DOES KK11 A DOES D
23. t Corporation 444 Whitney Street Northboro Ma 01532 Attention Communications Services NR2 M15 Customer Services Section EK K K11A UG 001 Order FIRST CLASS PERMIT NO 33 MAYNARD MASS BUSINESS REPLY MAIL NO POSTAGE STAMP NECESSARY IF MAILED IN THE UNITED STATES Postage will be paid by Digital Equipment Corporation Technical Documentation Department Maynard Massachusetts 01754
24. the computer area Otherwise unpacking and inventory must be done in the receiving area Follow steps through 4 to unpack the shipment Ensure that the shipping container is sealed If container is open notify the customer and record it on the installation report or LARS form 2 Check the shipment against the packing list to ensure that the correct number of containers has been received and that they are the correct ones If the shipment is incorrect notify the customer and the branch service manager or supervisor The customer should check with the carrier to try and locate the missing item s 3 Check all containers for external damage If any damage is found notify the customer and record it on the installation report or LARS form 4 Open containers one at a time starting with the one marked OPEN ME FIRST Inven tory the contents of each package with its packing slip and record any missing items on the installation report NOTE Packing materials such as foam fillers and plastic inserts should be retained if reshipment is con templated 2 2 2 Inspection Inspect each component for damage e g scratches chips or breaks Report any damage to the customer and record it on the installation report Report any damaged components that require re placement immediately to the branch service manager 2 3 PRE INSTALLATION CHECK The KK11 A cannot be installed unless the CPU is a PDP 11 34A Inspect the serial number tag
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