ENGINES - TF10 - Deliverable D10.2
Contents
1. cccsssscccsssssscccssssssccessssccsscsssccsesssssceees 12 SL EE Ee MON iii 12 A A a o PO E AE E O AE OM AP A TN 13 52L Genedl ass eege 13 A e A O A a e o ON o OA 13 A o a dete E A N E 13 593 OUICE sencra ls E e E 13 Ioe PON SUD rica 13 5 32 OVO ALA Bs AAA 14 6 Prototype d Mier NEESS eegenarteg geheien Bee ee h l 15 OL Genera eet EE 15 62 Bs AA A 15 A en a a A 15 AE AS A O a NE a E a ME ME RR MI VANE 16 62 3 COMO ae E 16 AE Ne OT 19800 6 ol e 16 ASS ER Ne EE 16 AE OO E 17 o C oer ege 17 634 Coniroland MOTO tte 17 6 4 Supported T2 modes and eatures eminencia 17 ZZ Prot otype3 Mier DYB 12 Capers ino ae e ea ee EENS 18 Tek o ea EN E E NE E E 18 I in o A A 18 O ue E 18 o e E 18 TAr EE ae o eT A EAE PRE EME IAE OMAKE 19 Tide Be eu ae EE 19 Tol O a a EE E A a E AEE E a A A Ra a RAM MRENE 19 AS Eu E 19 Ter Boo E eebe 20 ENGINES Page 3 Deliverable D10 2 V0 6 December 14 2012 Poe reet Eesen MI 20 S Prototype 6 LA SALLE DVB T2 Gateway ana ek ke ee ae akne enka 21 Bele e a ee e top 21 A SE 21 Sl UD EE 21 Sl mole A A station 21 522 Muelle PLE SVNA ricotta 21 Sr Muiiple PENO risotto 21 a oO E TE A 22 EN WR ut 22 E E o ninia 22 i ESC A yq 22 9 Prototype 7 MERCE SC OFDM Evaluation Platform sssscccsssssscccsssssscccsssscccscsssscsesssscceees 24 GN TEE E o EEEE AE AAEE EA A EE 24 IEL HEPC onrar Re E 25 lee ec EP TE EE 27 s Receiver EP RY E 29 A e E E V T AA EEA AEAEE2. to control configure the HTG V6HXT board 2 to implement the upper layers of the transmission system and 3 to run a powerful monitoring application ENGINES Page 26 Deliverable D10 2 V0 6 December 14 2012 PE 4 UI SITE Figure 5 HIG V6HXT x8PCIE FPGA board enclosed in the host PC 9 1 2 Transmitter HEP Tx As previously mentioned the baseband part of the transmitter is implemented by the HTG V6HXT FGPA board of the HEP Central Unit The digital baseband samples can however be forwarded to a separate platform through an optical link to allow transmissions over large distances This secondary unit is indeed meant to interface with any RF front end that would be made available for specific purposes The secondary unit relies on the ML605 Evaluation board designed by Xilinx The ML605 board is depicted on Figure 6 along with all the supported features The key features are as follows e 1x Xilinx Virtex 6 LX240 1 FPGA e 1x x4 PCI Express Gen2 Edge Connector or x8 PCI Express Genl e 1x 10 100 1000 Mbit s Ethernet interface with the onboard Marvell Alaska PHY device e 1x SFP port with EDC amp CDR support through external PHY chips e 1x DDR 3 SO DIMM currently fitted with 512 MB up to 2GB e 1x VITA 57 1 HPC FPGA Mezzanine Connector FMC 78 LVDS differential I Os and 8 GTX Serial Transceivers lx VITA 57 1 LPC FPGA Mezzanine Connector FMC 34 LVDS differential I Os and 1 GTX Serial Transceivers e Configurat
3. Deliverable D10 2 V0 6 December 14 2012 DELIVERABLE D10 2 IDENTIFICATION AND SPECIFICATION OF NGH PH 1 PROTOTYPES TO BE BUILT V0 6 DECEMBER 14 2012 ENGINES Page 1 Deliverable D10 2 V0 6 December 14 2012 Abstract This deliverable presents the different prototypes to be built within the TFI0 of the ENGINES project for further evaluation of a NGH Phase 1 transmission by TFII After a definition of the target NGH Phase 1 features the document gives for each prototype the type to be developed either a software IP block or a complete hardware and software equipment the interfaces with other prototypes in a DVB T2 chain and the preliminary DVB NGH features supported by the prototype ENGINES Page 2 Deliverable D10 2 V0 6 December 14 2012 TABLE OF CONTENT 1 Dioda CUO ua ve E a a ek 3 A PPP downed stsnsasbeasenssousbiaravensceeesanaeesusteesssasaustenats 6 3 Prototype 1 TeamCast DVB T2 MmodulatoFiionvoioscionensonicannacinncan dic coanaca rinda kos Eege Seege ee deeehen 7 Dede Generales CO PHN eege 7 EE 7 A ni 7 a E 8 o Bo A 8 3 5 supported T2 modes and KE TE 8 4 Prototype 2 Thomson Broadcast DVB T2 modulator cccccsssscccssssssccssssssccccssssccsscsssccsessssceees 10 SNE Se Kee A A 10 EE 10 A A e oo SI A In NE MAAE EME MJ 10 T22 EE 10 4 23 C ntoland MORO nt 10 Aa supported V modes ANG cares aa ii 10 5 Prototype 3 Thomson Broadcast DVB T2 transmitter
4. The NN6 T2Gateway is the central body of the operational DVB T2 network as it provides in band control and signaling to all the DVB T2 modulators throughout the T2 MI output interface When using Multiple PLP Physical Layer Pipes to provide service specific robustness the NN6 T2Gateway enables all the modulators to generate the same data in a deterministic manner When broadcasting DVB T2 services over Single Freguency Network operators must operate the NN6 T2Gateway that behaves as a SFN Adapter The NN6 T2Gateway provides in band and out of band synchronization information to all modulators to generate the same data at the very same time over the same freguency Combined with the ENENSYS A SI switch ASIGuard it implements an innovative and patented 1 1 redundancy mechanism named T2guard The whole solution offers a unique DVB T2 seamless switch over in SFN and MEN broadcasting between 2 DVB T2 Gateways that prevents for any TV blackout due to the change over operation 10 2 Interfaces 10 2 1 Inputs Control 2x Fast Ethernet for GUI and SNMP RJ45 MPEG2 TS 6x ASI inputs BNC 75 ohms lx Gigabit Ethernet IP input RJ45 GPS 1x TNC input for internal GPS 1x PPS input 50 ohms ENGINES Page 35 iy Deliverable D10 2 V0 6 December 14 2012 10 2 2 Outputs T2 MI MPEG2 TS 1x Gigabit Ethernet IP output RJ45 2x Mirrored ASI outputs BNC 75 ohms GPS 1xPPS and 1x10MHz outputs 10 2 3 Control and monitorin
5. PHY layer k e ka Bit Interleaved Input y Frame SCOFDM e TF coding nare o gt pustni EE building generation O pod Gateway Modulator functionalities y functionalities I Figure 10 General functional structure of the HEP transmitter Input processing Mode Stream adaptation adaptation Gateway functionalities PLPO Input Input stream Compensating Null packet interface synchronizer delay deletion PLP1 Input Input stream Compensating Null packet interface synchronizer delay deletion PLPn Input Input stream Compensating Null packet interface synchronizer delay deletion Figure 11 Specifications supported by the SC OFDM platform Input processing a Not supported ENGINES Page 32 Deliverable D10 2 V0 6 December 14 2012 Input processing Gateway functionalities Implemented in the modulator PHY In band signaling or padding PLPO Logical frame delay In band signaling or padding PLP1 Logical frame delay In band signaling or padding Figure 12 Specifications supported by the SC OFDM platform Input processing b PLPn Logical frame delay PLPO PLP1 Some missing coding rates commercial T2 lite IP core So far Cl with uniform law NGH uniform late to come later PLPn Not supported mem ieee Figure 13 Specifications supported by the SC OFDM platform B
6. 232 connector Interface to connect handheld terminal for local monitoring Connector RJ 45 7 3 Up converter interfaces 7 3 1 Inputs IE IN Signal type IF signal coming from the down converter Level 0 dBm Connectors SMA female 50 Q module front panel 7 3 2 Outputs RF output Signal type RF signal in the UHF band going to transmitting antenna Level 1 2 and 5Wrms Connectors SMA female 50 Q module front panel RF Sample Signal type RF output signal sample UHF band for monitoring Level 20 dB lower than RF output level Connectors SMB male 50 Q module front panel LO OUT Signal type LO signal sample for mixing process in the down converter module Level 5 dBm Connectors SMB male 50 Q module front panel LO Sample Signal type LO signal sample for monitoring Level 20 dBm Connectors SMB male 50 Q module front panel 10 MHz Sample Signal type 10 MHz reference signal sample for monitoring Level 7 dBm Connectors SMB male 50 Q module front panel ENGINES Page 19 ER Deliverable D10 2 VO 6 December 14 2012 7 3 3 Control interfaces Easy check RS 232 connector Interface to connect handheld terminal for local monitoring Connector RJ 45 7 3 4 Control and monitoring LOCAL INTERFACES Easy Check a 6 button LCD display device a To adjust and check the operation of each of module Once plugged to a specific module it will browse all possible con
7. FPGA through a GTH serial link are used to interconnect the HTG board with the two secondary boards In that purpose the cages are fitted with an optical transceiver AFBR 57J7APZ from Avago supporting data rates up to 7 4 Gbps through a pair of 850 nm multimode optical fibers The two FMC connectors not fully populated are provisioned to interconnect with a second HTG V6HXT board in case additional processing power would be needed Figure 4 compares the hardware resources count of the Virtex 6 HX380T FPGA in red to the other devices of the same family In addition to supporting 24 high speed GTH serial links the HX family provides a large number of DSP48E fast multipliers glued by more than 300 000 logic cells thus enabling the joint implementation of the HEP transmitter and receiver in the very same device The colocalization of the transmit and receive units provides a lot of flexibility to validate and evaluate the embedded functionalities by interconnecting both entities at different levels It also simplifies the evaluation of synchronization algorithms ENTES Logic Block RAM Block Maximum ENTES ocks CLBs oc OCKS Transceivers DSP48E1 Interface Ethernet Total Logic 5 t Cells Slicest4 Blocks for MACs 1 0 8 EE ee E EE e KN KON NUJ NUNE cevoo 126 000 zoom 1740 aso ses ass om 0 2 a o 5 eo Se OS penses sane somo aro sre aw se usmle 2 4 sj o w mo xcavexssor senses esco ezo sei Ile em
8. I E T T T 29 IO o AA EE E E EAT 29 KEL Sn O E E a AE ME A ERI O ME ina 29 GE Ge ONION ae s E a ENE AE AE ER A ama 30 GE O e E 30 O ent 30 E ss A A 30 M e e 30 Ta T ere 30 TO Ore d nO E eea NA A E E E A E OE EEA 31 10 Prototype 5 Enensys DVB 12 Gateway scccsssescersscesicssivedacsaveccncsecacvensianeuarsanewtsdvecsasiesusinosiaxconesauceteuacdeass 35 O A EEN 35 O ee e 35 O E e OE OR a E E a a a a EN NINA 35 O MS EE 36 10 2 3 Controlan don OO orita 36 10 3 Supported 12 modes and Lear s ssp dador 36 11 Prototype 9 Enensys DVB T2 modulator zeegeeggeuggegesiegteegeierddgeeugEeRSNERSkEENEeENE KEEN aaa kko 38 RTA SE descarada 38 RI SE ee EE 38 BM Is 38 RSC Oia 38 LE23 Control and TOMO criada 39 LL3 Supported MM ge 39 12 Prototype 10 UPV EHU DVB T2 demodulator ccooooccccconoccccnonocccncnnccccnonocccnccnocccccnnccccnonecccnccnanccos 40 AL EA a 40 1242 ee 41 RS T EE 41 EE 42 223 Comroland MOM NOTINO E 42 2 3 Supported 12 modes and E nanovo napad aa obde jao odda bela EEE E avokada 44 IS E Ee TN 45 ENGINES Page 4 Deliverable D10 2 V0 6 December 14 2012 1 INTRODUCTION Within the WP4 TF10 deals with the prototyping of Full T2 or NGH phase 1 compliant equipment This prototype eguipment will be used for evalutation and validation of the corresponding advanced functional features technologies This evaluation validation phase will rely on both laboratory tests and field tests respectively led wi
9. MERCE 9 1 General description The MERCE platform is meant to evaluate the performance of the SC OFDM waveform for the implementation of the satellite component of the DVB NGH hybrid profile As described in Deliverable D10 2 rev 0 3 4 the SC OFDM platform was initially due to be implemented on a FPGA board designed by Nallatech The so called Hardware Evaluation Platform HEP had recently been used to evaluate and demonstrate MERCE technologies related to the 3GPP LTE system in uplink The system was actually implementing a simplified version of the 3GPP Release 8 standard As the 3GPP LTE uplink relies on the SC OFDM modulation it had initially been planned to perform some functional adaptations to the existing design so as to enable the evaluation of the SC OFDM waveform in a satellite broadcasting environment At that time MERCE was in the process of selecting a new hardware platform to replace the existing equipment due to resources limitations The Nallatech platform was particularly lacking of free external memory a key feature when 1t comes to evaluate long time interleaving schemes for satellite transmissions As the specifications of the DVB NGH system were also under finalization it was decided to implement the actual SC OFDM component of the DVB NGH hybrid profile on the newly selected platform The purpose was twofold To benefit from a more powerful hardware platform especially with a large amount of external memory for the l
10. serie which allows to build flexible configurations several transmitters repeaters gapfillers in the frame including optional modules like GPS UPS monitoring The nominal output powers are Wrms 2Wrms and 5Wrms This modular serie allows up to four 1W 2Wrms channels or three 5W channels per frame with two additional slots for service modules Each channel is made up of two different modules e Down converter It moves an UHF channel to IF e Up converter It moves the IF signal to an UHF channel and amplifies it to reach the nominal output power 7 2 Down converter interfaces 7 2 1 Inputs RF IN Signal type RF signal in the UHF band coming from the receiving antenna Level range from 75 dBm to 20 dBm Connectors N female 50 Q module front panel LO input Signal type LO sample coming from the up converter and used for the down conversion mixer Level 5 dBm Connectors N female 50 O module front panel 7 2 2 Outputs RE sample Signal type Input signal sample UHF band for monitoring Connectors SMB male 50 Q module front panel ENGINES Page 18 Deliverable D10 2 V0 6 December 14 2012 IF sample Signal type IF signal sample for monitoring Level 20 dBm Connectors SMB male 50 Q module front panel IF output Signal type IF signal output to the up converter Level 0 dBm Connectors SMA female 50 Q module front panel 7 2 3 Control interfaces Easy check RS
11. 0V Connector IEC 320 C14 6 2 2 Outputs RE output Signal type RF signal in the UHF band Level 0 dBm maximum Connector N female 50 Q back panel IF output sample Signal type IF signal 36 16 MHz Level 20 dBm Connector SMA female 50 Q front panel RE output sample Signal type RF signal in the UHF band Label 30 dB lower than the nominal output power Connector SMA female 50 Q front panel 6 2 3 Control interfaces External IP communication Connector RJ 45 female back panel Local communication Connector RJ 45 female back panel Dry contacts Phoenix contact female 10 ways back panel 6 3 Power unit interfaces 6 3 1 Inputs The inputs interfaces are described below RF input Signal type RF signal in UHF band coming from driver unit Connectors N female 50 Q back panel ENGINES Page 16 Deliverable D10 2 V0 6 December 14 2012 Mains input Signal type AC 230V Connector IEC 320 C14 6 3 2 Outputs RE output Signal type RF signal in the UHF band Level 25 Wrms 50Wrms and 100Wrms Connector N female 50 Q back panel RE output sample Signal type RF signal in the UHF band Label 30 dB lower than the nominal output power Connector SMA female 50 Q front panel RE output sample driver unit feedback Signal type RF signal in the UHF band Label 30 dB lower than the nominal output power Connector SMA female 50 Q front panel 6 3 3 Contr
12. 18 2 4 a8 o a mo cavern rar raso oze ose vo raso ve o o oo o 109 Jesu eo zl 780 Lan lesen e 2 a s jo a ao coa zs soko soo se froe soe esa a 0 8 oo EE ae ore sce E e e z oe on e e Homes senc sesa caro ma raze or 30002 10 4 s 09 10 reo Notes Each Virtex 6 FPGA slice contains four LUTs and eight flip flops only some slices can use their LUTs as distributed RAM or SRLs Each DSP48E1 slice contains a 25 x 18 multiplier an adder and an accumulator Block RAMs are fundamentally 36 Kbits in size Each block can also be used as two independent 18 Kb blocks Each CMT contains two mixed mode clock managers MMCM This table lists individual Ethernet MACs per device Does not include configuration Bank 0 This number does not include GTX or GTH transceivers Poe ey a Figure 4 Virtex 6 FPGA Feature Summary by Device As shown on Figure 5 the HTG V6HXT is enclosed within a standard PC 3820 Core 17 Intel processor with 16 GB of DDR3 SDRAM running an Ubuntu Linux operating system OS installed with the Realtime Preemption PREEMPT RT patch The RT Preempt patch converts Linux into a fully preemptible kernel by simply modifying the original kernel Unlike Xenomai or RTAI it does not introduce a new layer within the Linux kernel It is thus always possible to benenfit from the large software portofolio of the Ubuntu distribution The host PC is used 1
13. 2 multi PLPs e Ready for multi PLPs but only 1 PLP validated so far e Support of the logical frames and logical super frames e Only the logical channel of type A e Support of long time convolutional interleaving CI e Also for longer durations than in NGH up to 10s The main deviations with respect to the DVB NGH specifications are e No support of TS or GSE inputs e So far only PRBS raw traffic e No implementation of the P2 symbols L1 signalling e No support of TFS e So far only uniform CI uniform late CI under completion NIN NE 2 5 MHz 5 MHz 0 5k 1k OST 1k 2k QPSK 160AM 1 16 1 32 w r t N PI ap PRO 1 5 4 45 1 3 2 5 7 45 1 2 8 45 3 5 2 3 44445 3 4 4 Feasible but not supported 6 Currently stored as tables 2 Implemented but not tested Use of a commercial T2 lite IP core Table 1 Current specifications of the HEP platform ENGINES Page 31 na AA a Deliverable D10 2 V0 6 December 14 2012 4 The system parameters supported by the platform are summarized in Table 1 Figure 8 depicts the functional structure of the HEP transmitter with respect to DVB terminology Figure 11 to Figure 15 graphically represent the DVB NGH specifications supported by the HEP platform following the same terminology as used in DVB documentation It can be noticed that a major part of the specifications are supported by the HEP platform Scope of the system
14. 75 MHz External Frequency Reference e Frequency 10 MHz e Impedance 50Q e Format TTL e Connector BNC female External Timing Reference e Frequency 1 PPS e Connector SMB female e Pulse width 10 us 5 2 3 Outputs Main Output Characteristics Shoulder gt 36 dB MER gt 33 dB average value Spurious compliant with EN 302 296 V1 1 1 5 3 Other general specifications 5 3 1 Power Supply AC input e Single phase 90V to 160V 184V to 254V e 3 phase ENGINES sa 4 Deliverable D10 2 V0 6 December 14 2012 154V to 272V 312V to 432V Power factor 0 99 typical Frequency 47 to 63 MHz 5 3 2 Environmental Compliance RoHS compliant ENGINES Page 14 Deliverable D10 2 V0 6 December 14 2012 6 PROTOTYPE 4 MIER DVB T2 TRANSMITTER Providing partner MIER Comunicaciones S A 6 1 General description The transmitter prototipe is part of the range of solutions for digital terrestrial TV broadcasting providing output powers of 20 50 100Wrms Extremely compact flexible and reliable it is designed to cover deployment needs on remote centers with harsh accesses and with space restrictions It provides an elevated efficiency and robustness allowing an easy installation and commissioning Its modular design allows configuring different types of redundancy architectures to improve system availability Additionally 1t includes a series of automatic parameter configuration a
15. Hz Level range 0 to 10dBm Connector SMA 50 Q TOD input General function TOD input to synchronize the date on the modulator absolute timestamp management Frequency 10MHz Level range 0 to 10dBm Connector RS232 serial interface 3 2 2 Outputs RF output General function DVB T2 RF signal transmission Frequency range 300 MHz to 900 MHz Level range 11 dBm to 1 dBm Supported bandwidth 5MHz 6MHz 7MHz 8MHz Connector SMA 50 Q RF monitoring output General function DVB T2 RF signal monitoring Frequency range 300 MHz to 900 MHz Level range 31 dBm to 19 dBm Supported bandwidth 5MHz 6MHz 7MHz 8MHz Connector SMA 50 Q 3 2 3 Control and monitoring The control of the modulator can be realized thanks to the Controlcast GUI through the IP interface Commands may also be sent to the module through RS232 interface The Controlcast GUI allows setting all the parameters of the modulator and monitors status information on the transmission Concerning DVB T2 parameters the GUI sets the modulation parameters when considering system A DVB T2 transmission but monitors the modulation parameters defined by the T2 MI stream when considering system B transmission 3 3 Supported T2 modes and features The different DVB T2 modes supported by the modulator are given in the following table General Frame Parameters System A MPEG TS only T2 or T2 Lite system B T2MI over TS T2 nm or mixed T2 T2 Lite Y
16. ICM and Frame building ENGINES Page 33 Deliverable D10 2 V0 6 December 14 2012 Frame building P Only data PLPs are supported gt Assembly of common Assembly of PLPn Li post Not supported Figure 14 Specifications supported by the SC OFDM platform BICM and Frame building SC OFDM generation P1 and aP1 currently fixed and stored in a table Figure 15 Specifications supported by the SC OFDM platform SC OFDM generation ENGINES Page 34 AA el y Deliverable D10 2 V0 6 December 14 2012 4 10PROTOTYPE 8 ENENSYS DVB T2 GATEWAY Providing partner Enensys CENENSYS 10 1 General description nm gt 5 KO z HU z tus The NN6 T2Gateway is ENENSYS DVB T2 Gateway that encapsulates up to 8 DVB MPEG 2 Transport Streams into a DVB T2 stream inserts synchronization data to allow Single Frequency Network SFN broadcasting possibly in MISO mode manages single and multiple PLP modes and outputs the DVB T2 stream towards the DVB T2 modulators with the synchronization information using the new T2 Modulator Interface T2 MI over ASI and IP Running at the head end right after a typical DVB T multiplexer the NN6 T2Gateway encapsulates the incoming MPEG 2 TS into baseband frames BB frame It packetizes the generated DVB T2 stream using the T2 MI Modulator Interface protocol through ASI and or IP
17. Length 100 46ms LDPC FER 0 00e 00 BCH FER 0 00e 00 Signal Properties LDPC iterations 2 CN dB 18 39 Bitrate TS 3 04 Mbps 5 73000 2 71792 3a Be Spectrum yan x freq y Resp Pls t Gu ZHRRO 1 z ZHRRO 1 z 2RQeQ a 50 T T T T T T 40 1 Spectrum ZD 3 P1 Correlation J 30 S S PO E a 3 4 20 Fi 41 e E H F 10 H E ne E ES la 2 0 4 4 10 4 2 0 2 ad 20 J 20 1 1 L 1 L 1 1 L 30 3 0 0 500 1000 1500 2000 2500 3000 3500 4000 4500 o 500 1000 1500 2000 2500 3000 3500 440500 441000 441500 442000 442500 443000 443500 444000 444500 Carrier Number K Carrier Number K Sample Number 638 063 30 8253 x 3209 22 y 42 5941 y2 3 38347 444236 1 16534 3b 3c 3d Time Resp y x Pilot Correlation E JOPLPO YOR a ZKRRO 17 a 2 QqeQ 17 amp 20 18000 7 Time Response Pilot Correlation Time Filter 16000 L J sk S n J a Ai N 14000 4 usi A d d Ny 3 12000 2 40 A A AJA mA 1 Ma AM VA NAJ E g PY Uw VN l Y wy We 4 10000 4 E a A N A Ana E 8000 4 E g JA A AN V y VV WV 6000 4 el UA 4000 100 2000 A di Mi k am le AS 60 40 20 o 20 40 60 0 50 100 150 200 250 300 350 Sample number Carrier Number 3p In Phase 3g 44 0756 26 3854 213 115 18821 0 1 92524 0 494869 3e Figure 3 Information provided by the spftware demodulator 3a Text information about the signal main parameters 3b Signal spectrum 3c Chann
18. NGINES Page 45
19. are receiver are the IQ samples sent by a TCP IP socket Supported formats are e ntl6 IQ samples through TCP IP socket In this last case the RF signal is received using the RF input interface the USRP has 12 2 1 Inputs As this is a software demodulator there are no physical input interfaces The data input is by a binary file with the IQ samples of the signal to demodulate In case of demodulating an RF signal using the USRP device the input interface is RE input when using the USRP N 210 device General function DVB T2 or DVB T2 Lite RF signal reception Freguency range From 50 MHz to 2 2 GHz Level range 90 dBm to 20dBm Connector SMA 50 Q Female Capture Bandwidth 10 MHz ENGINES Page 41 se Deliverable D10 2 V0 6 December 14 2012 12 2 2 Outputs As 1t 1s a software demodulator there is no physical output interface 12 2 3 Control and monitoring There are two different software applications in order to control the signal demodulation One of them controls the signal demodulation and carries out the measurements while the second one is used for controlling the acquisition of IQ samples when using the USRP N 210 device and a pseudo real time analysis is done Table 1 resumes the main text information monitored by the receiver Status synced or no Signal Properties CNR dB Mode EE Modulation Code rate Detected GI Egualization FFT Size EE IS ode Pilot Patern Frame Length
20. e second one consists on demodulating RF signals by using an additional RF module as shown in Figure 2 This module receives the DVB T2 or DVB T2 Lite RF signal as baseband IQ samples These samples can be saved in a file which could be later demodulated by the software demodulator or can be sent directly to the software demodulator by a TCP IP socket getting a pseudo real time analysis of the received signal This additional module is an USRP N 210 Universal Radio Software Peripherical device from Ettus Research which is connected to the computer using a GB Ethernet link ENGINES Page 40 Deliverable D10 2 V0 6 December 14 2012 IQ File RE Input et a z Figure 2 Operation with the USRP module 12 2 Interfaces When doing offline analysis the input to the software receiver is a file with the previously recorded IQ samples of the signal to demodulate Supported formats for the input files are e Binary files with double IEEE IQ samples e Text files with double IQ samples separated by spaces or newline e Binary file with I Q samples saved as signed Int16 little Endian e Binary file in the Tektronix IQT format e Binary file in the Tektronix TIQ format e Binary file in the HP VSA SDF format e Binary file in the HP VSA BIN format e Binary file in the ADIVIC TCX format after proprietary conversion e Binary file in the Anritsu DGZ format When doing pseudo real time analysis the input to the softw
21. eam generated by a standard multiplexer Then the DVB T2 GW generates independent Transport Streams per each PLP normally one PLP per service and automatically distributes common service components and PSI SI between Data PLPs and Common PLP ENGINES Page 21 3 Deliverable D10 2 V0 6 December 14 2012 8 4 Interfaces T2 MI ASI T2 MI TS UDP IP JojdePYV SLSIg9uO suds gxouuy uoneidepy Spol J9 NP9YIS guidig tre gq LI SFN clock 8 4 1 Inputs TS AST Standard DVB ASI signal via 75 04 BNC TS TS UDP IP TS UDP IP on multicast or unicast streams TS FILE Input TS Files 8 4 2 Outputs T2 MI AST Standard DVB ASI signal via 75 42 BNC with T2 MI signal T2 MI TS UDP IP TS UDP IP on multicast or unicast streams T2 MI FILE Input TS Files The input output interfaces can be combined in any form 8 5 HW specifications Power supply IP Interfaces Dual port Gigabit Dimensions H W D 43 437 597 mm 1 RU width 19 ENGINES Page 22 Deliverable D10 2 V0 6 December 14 2012 Operating Temperature Environmental spec 10 to 35 C 50 to 95 F Non operating Temperature 40 to 70 C 40 to 158 F Operating Relative Humidity 8 to 90 non condensing Non operating Relative Humidity 5 to 95 non condensing ENGINES Page 23 e Deliverable D10 2 VO 6 December 14 2012 9 PROTOTYPE 7 MERCE SC OFDM EVALUATION PLATFORM Providing partner
22. el estimation module and phase 3d PI symbol detection 3e Impulse response 3f Pilot carriers correlation 3g Constelation It is important to stress that the information obtained depends on the analysis done In case of doing an offline analysis all the information stated in Table 1 and Figure 3 is obtained However if the software demodulator 1s used in a pseudo real time analysis of the RF incoming signal using the USRP module all the information will not be available ENGINES Page 43 AA el y Deliverable D10 2 V0 6 December 14 2012 4 A There are two possible pseudo real time analysis modes One of them gives every information from Table 1 and Figure 3 but it takes between 1 and 3 seconds deppending on the configuration mode of the receiving signal to analyse the receiving signal before updating the information about the received signal However it is possible to obtain more frequent updates of the information in Table 1 and Figure 3 by using the second pseudo real time analysis mode This could be called Fast pseudo real time analysis as 1t only spends about 500 ms analysing the received signal before updating the graphic and text information Nevertheless when using the fast pseudo real time analysis mode it 1s not possible to obtain BER and FER measurements Besides if the rotated constellation feature is in used it is not possible to obtain neither a graphic of the constellation nor MER measurements On the ot
23. ent nor the terrestrial component is supported even if the platform is obviously OFDM capable The platform also focuses on the physical layer functionalities the gateway functionalities are simply emulated when needed Figure 9 shows the functional diagram of the overall SC OFDM platform It can be noticed that the platform implements a simplified LMS channel emulator in the purpose of performing basic tests on the overall system It must be pointed out that the platform does not currently implements synchronization mechanisms that will be developed in a further step The platform will be used at first to perform BER PER performance evaluation with a perfect synchronization to be compared with theoretical results ENGINES Page 30 Deliverable D10 2 V0 6 December 14 2012 Bit Interleaved Inp ut aimee E p SC OFDM processing GE NE Ing generation Bit Interleaved ue by lt coding amp de r Frame e EE SE processing De EE de b uilding demodulation Related to the specifications Figure 9 Functional diagram of the HEP platform 9 6 Supported modes As stated before the HEP platform implements a subset of the DVB NGH specifications The key functionalities supported by the HEP platform are as follows e Full support of the SC OFDM waveform spreading de spreading PP9 pilot pattern e Support of type 1 and type
24. es relative and absolute 5MHz 6MHz 7MHz 8MHz Yes up to 8 PLPs per T2 standard CH Loi Not supported Null FEFs T2 Lite FEFs TX signaling Not supported IK 2K 4K 8K 16K 32K Extended bandwidth 1 4 19 128 1 8 19 256 1 16 1 32 1 128 O Loi ENGINES Page 8 Deliverable D10 2 V0 6 December 14 2012 PP1 PP2 PP3 PP4 PP5 PP6 PP7 PP8 L1 constellation BPSK QPSK I60AM 64Q AM LDPC 16K 64K Constellation QPSK 16QAM 640AM 256QAM Rotated constellation Yes High efficiency mode Yes The modulator does not integrate TR and ACE algorithms but is able to reserved tones dedicated to TR PAPR management Dedicated to T2 frames Dedicated to T2 Lite frames ENGINES Page 9 A EEN y Deliverable D10 2 V0 6 December 14 2012 4 gt 4 PROTOTYPE 2 THOMSON BROADCAST DVB T2 MODULATOR Providing partner Thomson Broadcast 4 1 General description The Thomson Broadcast DVB T2 modulator is a complete prototype board generating a DVB T2 RF signal 1 The modulator supports both T2 MI and MPEG2 TS inputs and manages T2 frames 4 2 Interfaces 4 2 1 Inputs ASI input 1 and 2 General function MPEG TS and T2 MI inputs ASI format Data rate up to 72MHz Level range ASI standard Connector BNC 50 Q GPS input General function external antenna input for GPS reception Frequency GPS standard Connector TNC 50 Q PPS input General functio
25. figuration monitoring and status information of the module mTDT Toolkit a Proprietary software Local Graphical User Interface a Offers the most intuitive and friendly user way to manage the system by means of a laptop a When connected to a serial port it allows automatic profile loading exhaustive monitoring of the eguipment firmware updates and complete configuration REMOTE INTERFACES SNMP a The SNMP Agent provides access and control over basic parameters of the system through the open architecture SNMPV2 protocol a Embedded on the SMU System Management Unit module a It includes a GPRS EDGE modem as a backup of the communications a 10Base T interface to manage the equipment remotely over the Control module Web browser a Executable from any standard Internet browser it doesn t reguire any specific software a Allows saving on proprietary programs a Easy remote and local control and monitoring capabilities depending on user privileges a Embedded on the SMU System Management Unit module ENGINES Page 20 A en y Deliverable D10 2 V0 6 December 14 2012 4 gt 8 PROTOTYPE 6 LA SALLE DVB T2 GATEWAY Providing partner Ramon Llull University La Salle 8 1 General description La Salle DVB T2 Gateway supports both Single and Multiple PLP and it has the ability to re use existing DVB T Multiplexers with its special feature of OneBigTS Adaptation Its input output in
26. g Validation of DVB T2 parameters Easy to use web based GUI User management Full SNMP v2 support for remote management and integration with any NMS 10 3 Supported T2 modes and features Full support of BB frame modes DVB T2 network In band control of T2 modulators configuration Individual addressing FEF management SFN Adaptation Integrated SFN adapter MISO Support T2 MIP generation PLP management Single and Multi PLP handling Typel and type management Static and dynamic PLP allocation T2 MI output Generation of T2 MI packets IP output featuring Pro MPEG Forum CoP 3 SMPTE 2022 Optimized bandwidth output T2Guard Patented 1 1 seamless switch over between two T2 Gateways One click configuration The ENENSYS T2 Gateway supports the following parameters ENGINES Page 36 Deliverable D10 2 V0 6 December 14 2012 FFT size Extended bandwidth 1 4 19 128 1 8 19 256 1 16 1 32 and 1 128 Pilot pattern PP1 PP2 PP3 PP4 PP5 PP6 and PP7 PP8 PAPR TR Tone Reservation L1 constellation BPSK OPSK 16 QAM and 640AM L1 Repetition No PLP type Type 1 and Type 2 Coderate 1 2 3 5 2 3 3 4 4 5 5 6 High efficiency mode Yes Yes ENGINES Page 37 AA ga de Deliverable D10 2 V0 6 December 14 2012 A 11 PROTOTYPE 9 ENENSYS DVB T2 MODULATOR Providing partner Enensys Ke VENZNS les 11 1 General description ENENSYS NetMod DVB T2 Modulator is designed to modulate a MPEG2 Trans
27. h the product gt Intuitive GUI allowing fast learning period to get ready to manage the solution gt Can be remotely managed for automated tests gt User Manual stored in the GUI no more paper nor manual lost Full SNMP v2 support for remote management and integration with any NMS 11 3 Supported T2 modes and features The ENENSYS T2 Modulator supports the following parameters Length Frames per Superframe Subslices per Frame SEN transmission MISO Extended bandwidth PP1 PP2 PP3 PP4 PPS PP6 and PP7 PPS PAPR LI constellation LI Repetition PLP type LDPC Coderate Constellation Time interleaver High efficieney mode ISSY ENGINES Page 39 AA ga de Deliverable D10 2 V0 6 December 14 2012 SP 12 PROTOTYPE 10 UPV EHU DVB T2 DEMODULATOR Providing partner University of the Basque Country UPV EHU 12 1 General description The UPV EHU DVB T2 Test Receiver is a software based receiver for demodulating DVB T2 DVB T2 Lite and combined signal Figure 1 shows a diagram with the main blocks in which the software receiver is organized Green boxes describe the measurements carried out in each of the different blocks Various Input types Figure 1 Main blocks of the software demodulator This receiver is a software demodulator that can work in two different modes One of them is based on an offline analysis by the demodulation of the IQ samples previously recorded into an IQ samples file Th
28. her hand when the rotated constelation feature is not active both results can be obtained The other text and graphic results are always obtained 12 3 Supported T2 modes and features The main characteristic of the DVB T2 and T2 Lite modes supported by the software demodulator are summarized in Table 2 Single PLP All VV 0XX with the exception of the VV 018 MISO modes All VV 4XX with the exception of the VV 417 VV 419 VV 467 Multiple PLP MISO modes All VV 8XX with the exception of the VV 804 VV 816 VV 832 MISO modes General Frame Parameters Bandwidth 1 7 5 6 7 8 10 MHz T2 Lite Multi PLP Yes MISO FE TX signaling Extended bandwidth Guard interval Pilot pattern PAPR Table 2 Main DVB T2 and T2 Lite configuration parameters supported by the software demodulator kega TFS Deliverable D10 2 V0 6 December 14 2012 13 REFERENCES 1 Frame structure channel coding and modulation for a second generation digital terrestrial television broadcasting system DVB T2 DVB BlueBook A122 ETSI EN 302 755 V1 3 1 July 2011 2 Modulator Interface T2 MI for a second generation digital terrestrial television broadcasting system DVB T2 DVB BlueBook A136 ETSI TS 102 773 V1 2 1 3 Engines Workpackage 4 Task Force 10 description form V5 April 7 2011 4 Engines Identification and specification of NGH Ph I prototypes to be built Deliverable D10 2 rev 0 4 March 2012 E
29. ion through JTAG or Flash e USB to UART interface e ATX and DC power supplies for PCI Express and Stand Alone operations e USB 2 0 Host and Device interfaces ENGINES Page 27 Deliverable D10 2 V0 6 December 14 2012 User Clock Configuranon USB 2 0 DDR3 155 158 Mode Swnch Host 12V ATX Power FMC FMC System ACE USB 2 0 SFP LPC HPC Address 12V Wall Power Device GPIO LEDs System ACE GPIO DIP Switch SW 1 Prog SW 4 SystemACE RST SW3 USB ro UART 021 RU MGT Clock U0 8 J31 CPU RST SW 10 USB JTAG 022 PMBus Controller Erhemer System Monzor Headers PMBus U3 DVI Ouypur Plariorm Flash MGT Pon Push Bunons U27 126 129 SW5 5SW9 BPI Flash X68 PCI Express 16x2 LCD Character U4 Display Figure 6 Hardware specifications of the Xilinx ML605 FPGA board The SFP cage connected to the FPGA through a GTX link is used to interconnect the ML605 hardware to the HEP Central Unit In that purpose the cage is fitted with an optical transceiver AFBR 57J7APZ from Avago supporting data rates up to 7 4 Gbps through a pair of 850 nm multimode optical fibers Figure 4 compares the hardware resources count of the Virtex 6 LX240T FPGA in blue to the other devices of the same family The FPGA is used here to handle the different physical interfaces of the board and to generate the digital samples to be processed by a Digital to Analogue Conversion ADC module plugged into one FMC connector The versatilit
30. ked with simulation e g using a hardware LMS channel emulator ENGINES Page 24 sa Deliverable D10 2 V0 6 December 14 2012 9 1 1 HEP Central Unit The HEP Central Unit is the core processing unit of the HEP platform The physical layer funetionalities are implemented on a COTS FPGA prototyping platform designed by HiTech Global namely the HTG V6HXT FPGA PCle board See Figure 2 and Figure 5 Figure 3 provides an overview of the features supported by the HTG V6HXT These are as follows e Ix Virtex 6 HX380T 2 Xilinx FPGA e 1x x8 PCI Express Gen2 Edge Connector e 2x SFP ports with EDC amp CDR support through external PHY chips e 2x SEP ports with direct interfaces to the on board FPGA s GTH 10G serial transceivers e 2x DDR 3 SO DIMM currently fitted with 1 GB each up to 8GB e 2x QDR II SRAM 4Mx18 each e 2x HPC FPGA Mezzanine Connectors FMC FMC 1 9 LVDS I Os and 10 GTH 11 18 Gbps Serial Transceivers FMC 2 34 LVDS I Os and 10 GTX 6 6 Gbps Serial Transceivers e Configuration through JTAG or CPLD e USB to UART interface e ATX and DC power supplies for PCI Express and Stand Alone operations A r z rem 4 Ki gt E ns A KL e w UO O uma O Virtex 6 HX380T HX565I FF1923 press GerQ Figure 3 Hardware specifications of the HTG V6HXT x8PCIE FPGA board ENGINES Page 25 Deliverable D10 2 V0 6 December 14 2012 The two SFP cages directly connected to the
31. ms Table 1 Main text information provided by the software demodulator Synchronization PLP Info Besides the demodulator gives some graphic information as it can be seen on Figure 3 This information 1s related to e Constelation e Signal Spectrum e Pilot Carriers Correlation e P1 Symbol Detection e Channel Estimator Module and Phase Impulse Response ENGINES Page 42 Deliverable D10 2 V0 6 December 14 2012 Be mA SS eeo AX Summary University of the Basque Country EHU DVB T2 Receiver Synchronism PLPO Id 0 PLP2 Id 2 Status Synced Mode 16QAM 1 2 Mode OPSK 1 2 P1 Freg Shift 47 Hz Int Length 33 46ms Int Length 16 36ms x2 Norm Freq Shift 0 2 Hz WMER dB 17 41 WMER dB 17 17 CPE 1 3 MER dB 9 41 MER dB 9 60 Clock Error 0 13 ppm PreLDPC BER 1 12e 02 PreLDPC BER 6 06e 04 Detected Gl 1 4 PreBCH BER 0 00e 00 PreBCH BER 0 00e 00 LDPC FER 0 00e 00 LDPC FER 0 00e 00 Equalizer Lin Ideal BCH FER 0 00e 00 BCH FER 0 00e 00 Window Pos 408 sam LDPC iterations 2 LDPC iterations 1 Time Filter Size 20sam Bitrate TS 3 13 Mbps Bitrate TS 1 52 Mbps Delay Spread 0 28 us PLP1 Id 1 Signalling Mode 160AM 1 2 S1 S2 Pre Post OKOKOKOK Int Length 16 36ms x2 51 52 prob 100 98 WMER dB 18 02 FFT Size 4k MER dB 10 49 Mode Siso PreLDPC BER 1 20e 02 PilotPatern PP1 PreBCH BER 0 00e 00 Frame
32. n external 1pps input Level range TTL Connector BNC 50 Q 10M Hz input General function external 10MHz input Frequency 10MHz Level range TTL Connector BNC 50 Q 4 2 2 Outputs RF output General function DVB T2 RF signal transmission Frequency range UHF version 470 to 862 MHz Level range 15 dBm to 17 dBm Supported bandwidth 5MHz 6MHz 7MHz 8MHz Connector SMA 50 Q 4 2 3 Control and monitoring The control of the modulator can be realized thanks to the web interface through the IP interface The web interface allows to set all the parameters of the modulator and monitors status information on the transmission 4 3 Supported T2 modes and features ENGINES Page 10 Deliverable D10 2 V0 6 December 14 2012 The different DVB T2 modes supported by the modulator are given in the following table General Frame Parameters DVB T2 mode System A MPEG TS only and system B T2MI over TS T2 or T2 lite SFN transmission Bandwidth 5MHz 6MHz 7MHz 8MHz TFS No TX signaling No FFT size IK 2K 4K 8K 16K 32K Pilot pattern PP1 to PP8 PAPR ENGINES Page 11 na AS Deliverable D10 2 V0 6 December 14 2012 A 5 PROTOTYPE 3 THOMSON BROADCAST DVB T2 TRANSMITTER Providing partner Thomson Broadcast 5 1 General description The transmitter has been configured to fit in a standard 19 cabinet providing a compact footprint and delivering transmission power of up t
33. o 1 2 kW RMS per cabinet 125 and 250W RMS amplifier chassis offer the ability to scale output power to meet specific coverage needs Up to six parallel chassis can be combined in a single transmitter for 1 2 kW of power The transmitter delivers a robust output signal regardless of variations in typical environmental conditions A pioneer in DAP technology Thomson guarantees that the transmitters provide the highest constant performance by automatically compensating and correcting for aging of components reduction of output power or module failure Real time DAP also corrects both linear and nonlinear distortions generated by output mask filters and amplifier distortions For monitoring each transmitter includes an embedded Web server and SNMP agent to remotely deliver a real time comprehensive display of the transmitter s status as well as the identification and precise location of any fault ENGINES Page 12 3 Deliverable D10 2 V0 6 December 14 2012 5 2 Interfaces 5 2 1 General Specifications Frequency range e UHF 470 to 862 MHz Signal Bandwidth DVB T H 7 61 MHz channel 8 MHz DVB T2 7 61 MHz channel 8 MHz and 7 78 MHz channel 8 MHz extended carrier mode 5 2 2 Inputs Main Input Characteristics e Connector BNC female e Impedance 75Q e Dual TS changeover without broadcast interruption ASI MPEG 2 or MPEG 4 GPS Antenna Characteristics e Connector TNC female e Impedance 50Q e Frequency 15
34. ol interfaces Local communication Connector RJ 45 female back panel Dry contacts Phoenix contact female 20 ways back panel 6 3 4 Control and monitoring The transmitter incorporates a Remote control module in the driver unit based on an Ethernet 10Base T interface which allows external management Through this interface different services and IP protocols are implemented easing handling and maintenance of the equipment The module includes a GPRS EDGE modem for backup of the communications SNMP The SNMP Agent provides access and control over basic parameters of the system through the SNMP protocol The SNMP requests will be answered depending on the entry interface and the traps sent to one or both interfaces depending on the configuration of the corresponding object of the MIB SNMP agent parameters can also be accessed via a Web Browser in order to easy its use by accessibility by using common interfaces WEB BROWSER Web Browser interface provides embedded web control and monitoring features Executable from any standard Internet browser it doesn t require any specific software 6 4 Supported T2 modes and features The transmitter support the same features described in the paragraph 3 3 ENGINES Page 17 Deliverable D10 2 V0 6 December 14 2012 7 PROTOTYPE 5 MIER DVB T2 GAPFILLER Providing partner MIER Comunicaciones S A 7 1 General description The gapfiller prototype is part of the modular
35. ong time interleaving and to evaluate the SC OFDM waveform in a realistic DVB NGH context thus providing more relevant results As shown on Figure 1 the new HEP platform is made of three entities the HEP Central Unit and the HEP TX and RX parts The HEP platform 1s actually dedicated to the evaluation of new technologies for research purposes In that purpose both the transmitter and the receiver are implemented within the same equipment HEP Central Unit based on the HTG V6HXT x8PCIE FPGA board designed by HiTech Global See Figure 2 To still allow for transmission over long distances the main processing board is connected to 2 secondary units using 5 Gbps full duplex optical links The first unit HEP TX implements the digital to analogue conversion on an intermediate frequency IF while the second unit HEP RX implements the analogue to digital conversion from IF down to baseband These two units are built on the Xilinx ML605 board fitted with the FMC150 ADC DAC FMC board designed by 4DSP UI Ill INN Hu IH ul i I di a Figure 1 Overview of the MERCE Hardware Evaluation Platform The HEP platform is a research tool In its current version 1t does not support the DVB physical and logical standard interfaces It is not possible to interconnect the platform to other DVB compliant products Instead the platform is used in a standalone mode to carry on performance evaluation to be cross chec
36. or RJ 45 female 9 3 Receiver 9 3 1 Inputs 32x 40 7 MHz input Signal type External sinusoidal signal with frequency 182 85 MHz Level 10 dBm Connector SSMC 50 Q Low IF input Signal type Low IF analogue signal IF lt 70 MHz Level Max 10 dBm Connector SSMC female 50 2 Modulated bandwidth 5 MHz Mains input Signal type AC 230V Connector IEC 320 C14 9 3 2 Control interfaces Ethernet link Signal type Ad hoc control interface Throughput 10 100 Mbits s Connector RJ 45 female 9 4 Control interfaces The FPGA board within the HEP Central Unit is fully configured by the host PC either through the PCle interface or the 10G Ethernet interface A dedicated monitoring interface has been developed to control and monitor the whole system using a configurable Graphical User Interface GUI The same application can be used to control the two secondary units from the PCIe or the Ethernet interfaces 9 5 Features The purpose of the HEP platform is to validate the performance of the SC OFDM modulation in the context of satellite broadcasting For that reason the system does not implement the whole set of the DVB NGH specifications However all the implemented functionalities are fully compliant with the standard The platform actually focuses on the satellite component of the hybrid profile and more particularly the SC OFDM mode of the satellite component Thus neither the OFDM option of the satellite compon
37. port Stream or T2 MI stream into a DVB T2 fully compliant RF or IF signal Integrating state of the art components and sophisticated signal processing methods NetMod DVB T2 network adapter comprehensively covers all characteristics of the DVB T2 specifications With its integrated RF up converter NetMod DVB T2 Modulator outputs a RF signal that can be directly exploited for live broadcasting or testing purposes It generates the exact signal needed for any validation campaign debug test integration constraints simulation with a broadcast signal quality that is required by operators and matches with terrestrial transmitting systems 11 2 Interfaces 11 2 1 Inputs T2 MI MPEG 2 TS 2x DVB ASI BNC 75 Q lx Gigabit Ethernet IP input RJ45 Control lx Fast Ethernet for GUI and SNMP RJ45 GPS 1x RF input for internal GPS TNC 50 Q Ix PPS BNC 50 2 11 2 2 Outputs RF Outputs Ix Main RF output SMA 50 Q Ix Monitoring RF output SMA 50 Q Frequency spectrum 100 870 MHz step 1 Hz Power range 2 to 60 dBm step 0 1 dB MER over 42 dB in the whole band Shoulders Over 55 dB IF output lx Main IF output SMA 50 Q Frequency spectrum 20 85 MHz step 1 Hz Power range 0 to 30 dBm step 0 1 dB ENGINES Page 38 wtf Deliverable D10 2 V0 6 December 14 2012 MER over 45 dB in the whole band Shoulders over 55 dB 11 2 3 Control and monitoring Web Based Graphical User Interface gt Comes natively wit
38. s well as flexible monitoring and remote control tools providing an intuitive and simple OPEX Its highly compact design allows allocating a 100Wrms transmitter in a standard 19 rack unit with only 2U height Its modular conception provides the flexibility to configure the equipment as transmitter transposer or on channel repeater configurations echo canceller is available for on channel repeater configuration The transmitter is made up by two units e Driver unit 1U gi O S SMi geen e Power amplifier unit 2U gt a mme y m o mmm e em mmm a AE aaa a ani O OEA OO ee V EA 1 mm 1 M AAA MADEE 4 6 2 Driver unit interfaces 6 2 1 Inputs The inputs interfaces are described below ASI input 1 and 2 Signal type MPEG TS ASI format Connectors 2xBNC female 75 Q back panel 10M Hz input Signal type External sinusoidal signal of 10MHz for frequency synchronization Level from 0 to 10dBm Connector BNC female 50 Q back panel ENGINES Page 15 3 Deliverable D10 2 V0 6 December 14 2012 1 PPS input Signal type External 1 PPS signal for time synchronization Level TTL Connector BNC female 50 Q back panel GPS antenna input Signal type RF signal from GPS antenna Connector SMA female 50 Q back panel GSM antenna input Signal type GSM signal dual band 900MHz 1800 MHz Connector SMA female 50 Q front panel Mains input Signal type AC 23
39. smitter the baseband part of the receiver is implemented by the HTG V6HXT FGPA board of the HEP Central Unit The digital baseband samples can however be retrieved from a separate platform through an optical link to allow transmissions over large distances The interface with any RF front end that would be made available for specific purposes is carried out using a second secondary unit similar to the one used for the HEP TX unit In the present case both units are stricly similar as the FMC150 module from 4DSP implements both ADC and DAC modules The demodulation and down sampling operations are implemented in the ML605 FGPA The FPGA can also be used to implements part of the synchronization Figure 8 Xilinx ML605 board and 4DSP FMC150 daughterboard HEP TX and RX units 9 2 Transmitter 9 2 1 Inputs 32x 40 7 MHz input Signal type External sinusoidal signal with frequency 182 85 MHz Level 10 dBm Connector SSMC 50 Q Note The 4DSP FMC150 embeds a programmable oscillator that is only compatible with 3GPP LTE frequencies Mains input Signal type AC 230V Connector IEC 320 C14 9 2 2 Outputs IF output Signal type Low IF analogue signal IF 70 MHz Level Max 7 dBm Connector SSMC female 50 2 Modulated bandwidth 5 MHz ENGINES Page 29 3 Deliverable D10 2 V0 6 December 14 2012 9 2 3 Control interfaces Ethernet link Signal type Ad hoc control interface Throughput 10 100 Mbits s Connect
40. supports T2 MI rel 1 3 1 inputs and manages mixed T2 frames and T2 Lite frames Onboard GPS Input Y ai GPS J10 MHz Output 1 PPS Input TOD input ASI 1 input RF Output 4 0 dBm ASI2 input Zb Manual Rebbe bebe beets l Digital E Pre correction RF Monit Out 20 dBm IP Inputs control and RS232 Control TEAMCAST DVB I2 Modulator MT2 board 3 2 Interfaces The following figure presents the interfaces of the modulator Two ASI inputs are dedicated to reception of a MPEG TS stream or a T2 MI stream 2 GPS 10MHz PPS and TOD inputs are dedicated to synchronization of the modulator required for SFN processing The DVB T2 RF signal 1s given by RF output and RF monitoring output The control of the modulator is realized through IP or RS232 interface 3 2 1 Inputs ASI input 1 and 2 General function MPEG TS and T2 MI inputs ASI format Data rate up to 80Mbps Level range 0 to 10dBm Connector SMA 50 Q GPS input General function external 10MHz input for demodulator synchronization Frequency 10MHz Level range 0 to 10dBm Connector SMA 50 Q PPS input General function external 10MHz input for demodulator synchronization Frequency 10MHz Level range 0 to 10dBm Connector SMA 50 Q ENGINES Page 7 Deliverable D10 2 V0 6 December 14 2012 10MHz input General function external 10MHz input for demodulator synchronization Frequency 10M
41. terfaces are ASI TS UDP IP and Files It is a SW application running on a PC with PCI boards for ASI input output interfaces The configuration is currently done via ini files ia ST u fe a a S u fi me of ou pam rojas ne n TR E E il mr ales To ln To Tas lamleclan lam Las lata Taro mem lem Tan Iuaalire Teen letni lm fm Jm Tiree wem L MONM MER me og Im KIM mi fm n TC TE wem 28 MAME am me Leg It sem en Ze Pence my Th Tew VNO am 8 2 Features e Multi format input IP DVB ASI e Multi format output IP DVB ASI e Single and Multiple PLP support e SFN DVB T2 timestamp generation e OneBigTS format common extraction and AnnexD implementation for PSI SI e Different hardware options available 8 3 Supported modes 8 3 1 Single PLP VV500 La Salle DVB T2 Gateway supports configurations similar to VV500 with Single PLP 8 3 2 Multiple PLP VV413 La Salle DVB T2 Gateway supports configurations similar to VV413 with Multiple PLP in static multiplexing In this mode the allocation of BB frames is statically assigned according to the initial configuration 8 3 3 Multiple PLP VV400 La Salle DVB T2 Gateway supports configurations similar to VV400 with Multiple PLP in dynamic multiplexing In this mode the allocation of BB frames is dynamically assigned per PLP according to the instantaneous bitrate of each PLP It supports OneBigTS mode with a single input Transport Str
42. thin TF11 and TF12 Prototyping here means either hardware or software implementation The developpement work within TF10 is led in two phases e Phase 1 prototype implementation of Full T2 compliant equipment e Phase 2 prototype implementation of NGH Phase 1 compliant equipment This deliverable D10 2 reports about the phase 2 A first deliverable D10 1 dealt with the phase 1 Full T2 and NGH Phase 1 compliance are defined in the TF10 description document This document describes the prototype equipment intended to be implemented by partners contributing to TF10 and having provided data by the edition date of this document Prototype Type of equipment Provided by Nr T2 Modulator TeamCast 5 T2 Gap Filler Mier 6 T2Gatewy i ka Sale S O SC OFDM evaluation platform MERCE 7 9 LD Modulator T2 demodulator UPV EHU ENGINES Page 5 Deliverable D10 2 V0 6 December 14 2012 2 DEFINITIONS The following NGH Phase 1 features have been identified as relevant targets within the project scope of work e T2 Lite FEF with support of T2 MI rel 1 3 1 e Mixed T2 and T2 Lite e SC OFDM for satellite segment e Others TBD ENGINES Page 6 Deliverable D10 2 VO 6 December 14 2012 3 PROTOTYPE 1 TEAMCAST DVB T2 MODULATOR Providing partner TeamCast 3 1 General description The TeamCast DVB T2 modulator is a complete prototype board generating a DVB T2 or DVB T2 Lite RF signal 1 The modulator
43. y of the ML605 board comes indeed from the support of two FMC connectors one with a High Pin Count HPC interface almost but not totally populated and another one with a Low Pin Count LPC interface fully populated It is thus possible to plug on the board a great variety of FMC daughterboards featuring either digital or analogue interfaces In the present case the board is populated with a FMC150 daughterboard from 4DSP featuring 2x 14 bit A D 250 MSPS channels and 2x16 bit D A 800 MSPS channels See Figure 7 This board can be used to interface in analogue with an RF front end either in zero IF or low IF mode In the present case the system is configured to generate a signal modulated over a low IF frequency at 70 MHz The associated digital upsampling and modulation functions are carried out by the FPGA in the ML605 The 4FDP FMC150 module is shown plugged onto the ML605 on Figure 8 AC LVDS Clock 1 Channel A a ino LVDS Data 14 A D Control Channel s a mi Monitoring E L MC78 o External 2 a d Clock a Clock tree LVDS Clock 1 Se S Reference o Control External gt CDCE72010 Be Trigger SE LVDS Trigger 1 ys 22 Channel C a O o ACASA 3 D A Ni Channel D Counting Control Figure 7 Hardware specifications of the 4DSP FMC150 daughterboard ENGINES Page 28 SER Deliverable D10 2 V0 6 December 14 2012 9 1 3 Receiver HEP Rx Just like for the tran
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