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May 1982 - DSpace@MIT

1. has the most general task of the three units 1 5 duties include coordinate conversion generation of commands to and P2 user data entry processing and synchronization of the opera tion of all free CPUs Hardware failure detection is also allocated to Pl P2 the video processor accepts commands mainly from Pl although it can also handle light pen inputs P2 generates a bit map containing the picture information based on these graphic command inputs Division of a task among three CPU s has as its main advantage an increase in system throughput This throughput improvement however is highly dependent on task organization and interprocessor resource sharing PPOD PROJECT INTERPROCESSOR COMMUNICATIONS Task Subtask Breakdown NAVAT Denen gt TAS IO formatting MMPE and coordinate conversion Processor 0 Processor Is FDC 1 Figure 5 PILOT Video display generation Processor 2 x MicreAngelo 0c 21 Care must be taken in tne design of any multiprocessor algorithm to ensure that two processors do not attempt to access the same portion of memory at the same time It is desirable to exploit the maximum concurrency in any given task however this objective must be balanced against the possibi lity of resource conflicts Modern rultiprocessor systems employ spe cialized software to maximize system throughput without incurring resource conflicts The control task is gen
2. Interrupt Interrupt Jammer Vector 1 2 Communication Data Flow P2 Graphics Firmware 8 Read Strobe Inbound HCBF data latch Figure 17 S TDF EFC3 RPA E7F1 ERRCNT E6FF BTGO E7F2 BASE E7F4 START2 F852 CNTST E7F3 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 54 Variables and Flags for FUSER6 A non zero value stored at this location enables software performance monitoring code embedded in the Pl real time clock interrupt service routine This location serves as a read pointer and contains the offset from buffer base address of the next command byte to be read from the ring buffer and transmitted to P2 If enabled the software performance monitor code will store the number of errors detected and corrected since system start in this location BTGO contains the number of bytes in the ring buffer waiting to be transmitted to P2 BASE is the base address of the ring buffer All buffer operations occur relative to memory locations which are addressed as offsets of this base address Location of the start of the routine to service the interrupts generated when P2 requests another command byte from the P1 ring buffer Flag status variable Bit functions are as follows H Next attempt to put a byte in buffer will fail L Next attempt to put a byte in buffer will not fail H Ring buffer is full L Ring buffer is not full H Buffe
3. FTL REPORT R82 4 A PROGRAMMABLE PILOT ORIENTED DISPLAY SYSTEM FOR GA AIRCRAFT James A Littlefield May 1982 FTL REPORT R82 4 A PROGRAMMABLE PILOT ORIENTED DISPLAY SYSTEM FOR GA AIRCRAFT James A Littlefield May 1982 FTL REPORT R82 4 A PROGRAMMABLE PILOT ORIENTED DISPLAY SYSTEM FOR GA AIRCRAFT Abstract NS This paper presents a complete description of a digital flight data processing platform designed to support a range of airborne or flight simulator based experiments requiring the acquisition processing and display of information The Programmable Pilot Oriented Display PPOD is based on IEEE S 100 bus standard equipment and readily available software utilities The design philosophy and techniques used to achieve project objectives with a minimum of hardware software customization are discussed System resources include three Z80 processors intelligent IO complete interprocessor communications firmware and RS 170 composite video output Discussion of both PPOD capabilities and the steps required to employ PPOD in future experimental setups are presented in the context of a mobile test run Aknowledgements The results presented in this paper could not have been achieved without the individuals and organizations named below My advisors Profs A Elias and W Hollister have provided tech nical advise software expertise and valuable suggestions throughout the PPOD development effort Their di
4. Jre Sutty G J Depth Perception and Motion Cues Via Textured Scenes AIAA Flight Simulation Technologies Conf 1978 paper 46 1978 Scion Corp MicroAngelo User s Manual Scion Corp Vienna VA 1980 Spracklen K 7 80 and 8080 Assembly Language Programming Haydn Book Co Inc Rochelle Park NJ 1979 Stark E A Motion Perception and Terrain Visual Cues in Air Combat Simulation Visual and Motion Simulation onf Swallow R Goodwin R ODraudin R utrol A New Technique in Image Generation AIAA Flight Simulation Technologies Conf 1978 paper 59 1978 Teletek FDC 1 Product Specification Teletek Sacramento CA 1980 Teletek Intelligent Interface Product Specification Teletek Sacramento CA 1980 45 46 47 48 90 Texas Instruments TTL Data Book for Design Engineers Texas Instruments Incorporated 1976 Wu C A Digital System to Produce Imagery from SAR Data JPL Pasadena CA AIAA paper 76 968 1976 Young L Research on Integration of Visual and Motion Cues for Flight Simulation Manned Vehicle Laboratory MIT NASA report CR 153249 Zaks R The CP M Handbook with MP M Sybex Inc Berkeley CA 1980 91 Appendix A Software Listings Source listings for programs described in the body of the paper are provided in this appendix I ISUERS 92 is a revision of the Northstar 6000 IO control program USER3 This program controls the
5. 00H O0H DB 0A7H 00H 02H 0F FH 0C6H 047H OF 9h DB 0A7H 00HO1H O0F FH 0C8H 03H ORG 0 800 THESE PARAMETERS ARE FOR THE BUFFERED INTERFACE TO THE GRAPHICS BOARD MICROANGELO WP RPA BTGO EQU EQU EQU 0 074 COMMAND BUFFER WRITE POINTER OE D7 5H COMMAND BUFFER READ POINTER 0ED7 6H OF BYTES WAITING TO GO TO MICROANG CNTST BASE ERRCNT wo we 111 EQU OED7 7H STATUS FLAG BYTE SEE FUSER6 FOR DETAILS EQU OED78H BASE ADDRESS OF COMMAND BUFFER EQU OED7 2H DIAGNOSTIC LOCATION SHLD 08000H TEMPORARILY SAVE HL IN 08000H LXI H WP INITIALIZE PARAMETERS LISTED ABOVE MOV M A LXI H INTP SHLD INTERRUPT VECTOR FOR GRAPHICS INTERFACE IS DE LHLD 08000H RESTORE THE PREVIOUS VALUE OF HL LXI D OEEEOH RESTORE PREVIOUS VALUE OF DE JMP OFO7CH JMP BACK TO FDC 1 MONITOR INITIALIZATION CODE RST SAVE SOME ROOM FOR FUTURE EXPANSION RST RST RST RST RST MJ AJ 54 ROUTINE TO INCREMENT READ POINTER LOOPB THIS ROUTINE IS USED BY THE MICROANGELO INTERRUPT SERVICE ROUTINE TO MANIPULATE THE COMMAND BUFFER READ AND WRITE POINTERS INCRP RETURNS WITH HL ADDRESS OF NEXT BYTE IN BUFFER LXI H BTGO ANY BYTES WAITING TO GO TO MICROANG MOV A M ORA A JZ LOOPC IF NOT THEN TO TO LOOPC DCR M DECR OF BYTES WAITING TO GO DCX H MOV A M MOV E A INR A CPI 073H JC LOOPB INCR READ POINTER IF gt 073H THEN ROLL UNDER XRA A MOV M A MVI A OFFH
6. Information Control and Decision Models of Human Performance Mil Press Cambridge MA London England 1974 Hess R H Structural Model of Adaptive Human Pilots Journal of Guidance and Control vol II No 5 1980 Cornsweet T N Visual Psychophysics Academic Press New York NY 1970 Graham C H ed Vision and Visual Perception Wiley NY 1965 Green Swets Signal Detection Theory and Psychophysics Wiley NY 1966 Kelley D H Visual Contrast Sensitivity Optica Acta vol 24 No 2 1977 Cohen J C Evaluation of Alternative Instrument Landin System Displays 16 622 Experimental Projects Report MIT Dept Aeronautics and Astronautics 1981 Kayton M Fraid W ed Avionics Navigation Systems John Viley ad Sons Inc New York London Sydney Toronto 1969 10 11 12 13 14 87 Bibliography Anderson J C Leeper J L The DABS Data Link _ Airborne Intelligent Display Operator s Manual MIT Lincoln Laboratory Bedford MA 1980 Barden Wey The Z 80 Microcomputer Handbook Howard W Sams amp Co Indianapolis Ind 1978 Bergeron H P Single Pilot IFR Autopilot Complexity Benefit Tradeoff Study Fright Dynamics and Control Division Langley Research Center Hampton VA AIAA paper 80 1869 1980 Bulloch C The Speaking Computer Automatic Voice Advisory Systems Coming On Line Interavia Vol 12 1980 Bunker W M Ingalls Capt M L Circles Texture Etc A
7. Component Source Mainframe 2200 California Computer Systems Motherboard 2501 250 Carribean Drive Sunnyvale 94086 5 100 EPROM card 32k Digital Research Computers P 0 Box 401565 Garland TX 75040 214 271 3538 DM6400 S 100 Dynamic RAM Measurement Systems and Controls inc 867 North Main Street Orange CA 92668 714 633 4460 PO processor card I 2 Teletek 9767F Business Park Drive Sacramento CA 95827 916 361 1777 Pl processor card FDC 1 Teletek 9767F Business Park Drive Sacramento CA 95827 916 361 1777 P2 processor card SCION Corporation MicroAngelo 8455 D Tyco Road Vienna VA 22180 703 476 6100 132 Loran C Receiver Digital Marine Electronics Corp Northstar 6000 30 Sudbury Rd Acton MA 01720 617 897 6600 133 SOFTWARE VENDORS CP M FDC 1 3 2 b Monitor Screenware PAKI PL I 80 Vedit Full screen editor Leapac Services 8245 Mediterranean Way Sacramento CA 95826 916 381 1717 Teletek 9767F Business Park Drive Sacramento CA 9582 916 361 1777 SCION Corporation 8455 D Tycho Road Vienna VA 01720 703 476 6100 Westico Inc 25 Van Zant Street Norwalk Con 06855 203 853 6880 The Discount Software Group 6520 Selma Ave Suite 309 Los Angeles 90028
8. PUSH H COMMUNICATIONS BETWEEN FDC 1 AND PUSH PSW MICROANGELO BY CALLING START2 CALL START2 POP PSW POP H POP D LXI H ERRCNT INCREMENT THE ERROR COUNT INR M EXT4 LDA CNTST IF NO ERRORS DETECTED THEN EXIT HERE ORI O8H STA CNTST POP H POP PSW RET THIS IS THE DRIVER CODE FOR MICROANGELO WHENEVER THE KEYBOARD IS ASSIGNED AS THE INPUT DEVICE THIS DEVICE HANDLER IS ENABLED AS THE OUTPUT DEVICE USOUT PUSH PSW GET MICROANGELO STATUS LOOPD IN OF1H ANI PO JNZ LOOPD LOOP UNTIL NOT BUSY POP PSW OUT OF OH SEND TO MICROANGELO RET END The program anamen uses data compression techniques to reduce data base mamory requirements This routine can be used to compress the language data area associated with PL I programs so that less EPROM is required to initialize the data area anamen proc options main dcl 1 32767 fixed bin 7 based mlp dcl mem2 32767 fixed bin 7 based m2p dcl mlp m2p pointer dcl mipb bit 16 based mlpp dcl m pb bit 16 based m2pp dcl mlpp m2pp pointer mlpp addr mlp m2pp addr m2p dcl i j length i pos o pos fixed bin 15 put list ENTER STARTING ADDRESS get edit mlpb b4 4 donel done2 114 put skip list ENTER LENGTH get list length put skip list ENTER TARGET ADDRESS get edit m2pb b4 4 0 D0s 1 i pos 1 do while i pos lt length if i_pos 0 then do do to min 127 l
9. SNRWD 1206 The SNRWD indicates the history of the SNR levels for the first and second slaves If both SNRs were above the required minimum level then both bits 1 2 will be high If either bit is low then one of the stations is not being received well and the full GPIA data frame should be passed to the host Bit 0 H gt Next byte from receiver will contain SNR data for either 1 or S2 Bit 1 H Last SNR checked was above the required minimum Bit 2 H gt Last SNR checked was above the required minimum CONWD 1205 The CONWD location controls the type of data sent from PO to Pl The IUSER3 control program can decode either EPSCO or GPIA data frames decode both types of data or select the optimal data frame based on SNR criteria Figure 15 Sheet 1 2 45 Bit 0 H Decode data Bit 1 H gt Decode EPSCO data Bit 2 H Decode the best data based SNR levels The remaining named locations in the source code listing pertain to features of the PO hardware and are fully documented in the user s manual for that processor Figure 15 Sheet 2 2 46 Get high byte No Y No rm D Y Put high byte in ring buffer Incr write pointer WP and byte cnt BTG02 Get low byte Put in ring buffer IUSER3 Flowchart Figure 16 Old data used Attach Ident Tag to Frame Send frame to P2 47 N Save byte of frame Set XFER request Re
10. 38 Each 15 bit word is composed of 8 bits of data 3 bits of address which device the data is sent to and 4 identification bits as shown in figure 12 Four devices external to the Northstar 6000 can be addressed Fach device is expected to observe the address bits of every data word and latch those which are sent to it For the purposes of mobile testing it was desired to consider data from two of the four available devices The required data streams are those for the GPIA address 010 and for the EPSCO plotter address 001 A GPIA data frame consists of 27 bytes con taining time differences latitude and longitude and auxilliary data for one of the stations in the Loran C chain being monitored Auxilliary data provides signal to noise ratio envelope cycle discrepancy and tracking mode number for each station Latitude and longitude is based on the first slave 51 and the second slave S2 time differences TDs TDs and lat long are available about once every 2 7 seconds with auxilliary data for all stations in a given Loran chain available once every 16 seconds see fig 13 5 0 data frames consist of 12 bytes giving Sl and 52 TDs in binary coded decimal see fig 14 These data frames are available about once every 2 seconds A higher update rate is preferable so whenever S1 S2 TDs are reliable EPSCO data should be sent to Pl for further pro cessing Low SNRs as indicated by auxilliary data from the GPIA stream require a rever
11. LXI H BASE MVI D 00H DAD D ADD READ POINTER TO BASE TO GET ABS BUFFER ADDR RET 112 LOOPC LDA CNTST SET CNTST BITS TO INDICATE EMPTY BUFFER ANI OFBH STA CNTST XRA A RET INTERRUPT SERVICE ROUTINE FOR UA INTERRUPTS ive we we NTP PUSH PSW PUSH H PUSH D CALL START2 POP D POP H POP PSW EI DB OEDH ED 4D RETI DB 04DH START2 LDA CNTST SETB2 OF CNTST ORI 04H STA CNTST CALL INCRP GET ADDRESS OF NEXT BYTE TO GO ORA A JZ CLAL IF 0 ON RETURN THEN BUFFER IS EMPTY MOV A M OTHERWISE GET BYTE FROM COMMAND BUFFER OUT OFOH XE 2M SEND IT TO MICROANGELO 7 LDA CNTST SET CNTST TO INDICATE XFER IN PROGRESS ANI OF7H STA CNTST CLAL LDA CNTST RESET BUFFER FULL FLAG IN CNTST ANI OFCH SEE FUSER6 LISTING FOR FULL DETAILS STA CNTST ON 5 BIT DEFINITIONS RET RST RST RST RST RST RST RST SAVE SOME ROOM FOR FUTURE EXPANSION SN NN ON SONS IS AN EXTENSION TO THE STANDARD FDC 1 REAL TIME CLOCK INTERRUPT SERVICE ROUTINE TIMR CHECKS THE PERFORMANCE OF THE FDC 1 TO MICROANGELO DATA LINK ONCE EACH SECOND AND TAKES CORRECTIVE sACTION IF NEEDED IN ADDITION AN ERROR COUNT AT ERRCNT IS INCREMENTED WHENEVER AN ERROR IS DETECTED AND CORRECTED TIMR PUSH PSW PUSH H LDA CNTST ANI 08H HAS BIT 4 OFCNTST BEEN RESET SINCE JZ EXT4 LAST SECOND 113 LDA IF NOT THEN CHECK BTGO ORA A JZ EXT4 IF BTGO 0 THEN THERE IS NOT FAILURE NOP PUSH D IF BIT 4 0 AND BTGO 50 TRY TO RESTART
12. routine Exit returns to standard register set and enables interrupts Exit point from PAKI interrupt service routine Exit returns to standard register set but does not enable interrupts PPEND 0 then normal command processing is assumed PPEND lt gt 0 implies that SAVE RESTORE operation has been requested by the host The main command buffer is allowed to become completely empty before proceeding These two bytes contain the auxilliary stack pointer where processor registers and cursor values are stored by the SAVE special command Number of command bytes in the main command buffer waiting to be processed is stored at this location Figure 20 66 Request pending Special Comrand Set request pending flag Jump 0126 This code segment is attached to the standard PAK interrupt Special commands are the SAVE and RESTORE service routine environment functions MACOD3 Flowchart Sheet 1 4 Figure 21 67 BTGO 0 Read Special Command SAVE cursors MACOD3 Flowchart Sheet 2 4 Figure 2 68 Save HL BC DE Save old RESTR RR Y Disable Interrupts N Restore DE BC HL Get old ret addre MACOD3 Flowchart Sheet 3 4 Figure 21 69 Restore cursors Clear Pending flag Enable Interrupts MACOD3 Flowchart Sheet 4 4 Figure 2 79 of the 91 operation Whenever P2 receives an interrupt the address of t
13. 5 bits Left data port Left control port Right data port Right control port PO Memory Organization Reaion z 0000 021A 0218 07FF 0800 OFFF 1000 1400 1401 1FFF 2000 2 3FF 2400 2440 3000 5000 6000 7000 8000 8001 8002 8003 Figure 2 I is a tradename of Teletek Corp 129 FDC 1 Memory Map Region Use 0000 EDFF RAM available for user code and data EEOO EFFF Reserved RAM for interrupt table and system data base FOOO F7FF Teletek Monitor 3 2b in EPROM F800 FFFF EPROM programming socket P Memory Organization Figure FDC 1 is a trade name of Teletek Corp 130 MicroAngelo Memory Region Use 0000 Screenware EPROM 1000 7 Not Used 8000 F7FF Visible Display bit map F800 F8BF 2 5 Visible Scan lines F950 FF3F User defined characters or user code area FFhO FFFF Screenware Pak working RAM P2 Memory Organization Figure MicroAngelo is a tradename of Scion Corp 131 APPENDIX E Sources for PPOD Major System Components The vendors below are not necessarily the producers or copyright holders on the products listed In many cases the vendor markets a specialized revision of the product under a sales license from the copyright holder example is the CP M system sold by Leapac services under agreement with Digital Research The Leapac CP M BIOS has been customized for compatability with the Teletek FDC 1 processor
14. BUS OUTBTI OTE OUTBT3 ENTR CALL OUTBT3 TRY TO PUT THE BYTE IN THE BUFF LDA CNTST WAS ATTEMPT SUCCESSFUL BIT 6 A JNZ OTE YES RETURN TO CALLING CODE JMP OUTBTI NO TRY AGAIN RET DI NO INTS ALLOWED DURING BUFFER PUSH D POINTER MANIPULATIONS PUSH H MVI A OFFH STA TDF SET TDF HIGH TO ENABLE SOFTWARE CHECKS MONITOR AND ERROR CORRECTION CODE EMBEDDED IN 1SEC INTERRRUPT SERVICE ROUTINE LDA NXTBT CALL IWP CALL ROUTINE TO INCR WRITE POINTER LDA CNTST 215 BUFFER FULL BIT 0 A JNZ YES IT IS FULL RES 1 A STA CNTST NO CLEAR BUFFER FULL FLAG CALL STARTI 77 GENERATE AN INT IF NECESSARY XRA A POP H POP D EI BUFFER MANIPULATIONS DONE INTS OK RET SETB 1 A SET BUFFER FULL FLAG STA CNTST BIT 2 A IF XFER NOT IN PROGRESS THEN START ONE CZ STARTI MVI A OFFH POP H POP D EI RET ROUTINE TO INCREMENT WRITE POINTER PUSH PSW LXI H BTGO MOV A M IS COMM BUFF FULL CPI 073H JNC 1 1 YES JMP LDA CNTST NO RESET BUFFER FULL FLAG RES 0 A STA CNTST we we we we we we we we we 103 INCR OF BYTES IN BUFFER MOV A M GET WRITE POINTER OFFSET INR A INCR WRITE POINTER OFFSET CPI 073H iw IS WRITE POINTER AT TOP OF BUFF JC LP NO THE JUMP XRA A YES THEN ROLLOVER TO BUFF BASE MOV M A MVI D OOH LXI H BASE DAD D ADD WRITE POINTER TO BUFF BASE POP PSW MOV M A SAVE THE COMMAND IN BUFF LDA CNTST S
15. DATA FRAMES TO HOST PROCESSOR SEPC ROUTINE TO GENERATE OPCOM OPCO OPC1 GONE XRA A DCR A STA WTFLG LXI B 01H CALL MOVER LDA IRAM ORA A RNZ LXI H IRAM MVI A ETAG MOV M A LXI 00 LXI H OBASE2 LXI D IRAM 1 DB OEDH OBOH XRA A STA WTFLG LXI B 0DH CALL MOVER CALL OPCOM RET PUSH PSW PUSH H LXI H ICON LDA INTVCT ORA A JZ GONE LDA INTVCT STA COMSTA MOV A M DB OC BH 3 8 A 40H JNZ OPCO MVI A 010H MOV M A MOV DB 1 8 40 JZ 0 1 POP H POP PSW RET INTERRUPTS TO HOST SET WIFLG FOR XFER FROM HOST GET ONE BYTE FROM HOST MEMORY IF FRST 0 THEN THE DATA IS USED ATTACH EPSCO TAG TO FRAME OK SEND D MORE BYTES TO HOST MOVE FROM TEMPORARY BUFF TO IO BUFF SET WTFLG FOR XFER TO HOST MEMORY D BYTES TO XFER CALL ROUTINE TO DO DMA CALL ROUTINE TO GENERATE HOST INT IF INT VECTOR ZERO THEN LEAVE PUT INT VECTOR IN OUTBND DATA LATCH WAIT FOR INTERRUPT HOST HAIT FOR HOST TO AKNOWLEDGE INT CLEAR INTERRUPT TO HOST 101 FUSER6 supports both polled and interrupt driven data communication bet ween Pl and P2 FUSER6 is used to pass data and command bytes through a double buffered interface PUBLIC OUTBT PUBLIC STARTI MACLIB 780 TOF EQU OEFC3H SOFTWARE ERROR DET ENABLE RPA EQU OE7F1H BUFFER WRITE POINTER ERRCNT EQU OE6F FH ERROR COUNT BTGO EQU OE7F2H OF BYTES WAITING
16. SEGP 99 LDA CONWD DB OCBH 2 8 A 40H CNZ BSRCE MAYBE IS THE BEST SOURCE LDA STATWD DB OC BH 2 8 A 80H ALTER BUFFER STATUS FLAGS STA STATWD RET XRA A DCR A SET WTFLG FOR HOST I 2 TRANSFER STA WTFLG LXI B 01H GET IST BYTE FROM FDC 1 DATA BUFF CALL MOVER LDA IRAM ORA A IS FIRST BYTE 0 RNZ IF NOT THEN HOST IS STILL USING LXI H IRAM LAST FRAME MVI A GTAG MOV M A LXI B 01CH LXI 5 1 LXI D IRAM 1 DB OEDH 0BOH XRA A SET WTFLG FOR XFER TO HOST STA WTFLG LXI B 01CH SET UP FOR XFER TO FDC 1 1C BYTES CALL MOVER CALL ROUTINE TO DO DMA A ux CALL OPCOM CALL ROUTINE TO GENERATE INT TO HOST RET BSRCE DETERMINES WHICH OF THE TWO FRAMES GPIA OR EPSCO IS PREFERRED BSRCE SEGP2 LDA SNRWD WERE SNRS ABOVE THRESHOLD DB OCBH 1 8 A 40H 0 FIRST AND SECOND SLAVES JZ SEGP2 IF NOT THEN SEND GPIA FRAME DB OC BH 2 8 A 40H RNZ CALL SEGP CALL ROUTINE TO SEND GPIA DATA RET CODE TO SEND AN EPSCO DATA FRAME XEP BSRCE2 LDA CONWD IS EPSCO DATA WANTED DB OC BH 1 8 A 40H CNZ SEPC IF YES THEN TRY TO TRANSFER LDA CONWD DB OCBH 2 8 A 40H CNZ BSRCE2 31S PREFERRED SOURCE WANTED LDA STATWD ALTER BUFFER STATUS DB OCBH 6 8 A 80H STA STATWD RET LDA SNRWD WERE LAST TWO SNRS ABOVE THRESHOLD DB OCBH 1 8 A 40H RZ DB OCBH 2 8 A 40H RZ CALL SEPC RET RETURN IF NOT RETURN IF NOT IF BOTH OK THEN SEND EPSCO DATA CODE TO SEND EPSCO
17. acquisition error checking and formatting of the Loran C data IUSER4 IS A RELOCATABLE VERSION OF IUSER5 IUSERS IS ASSEMBLED RELATIVE TO 29A SINCE IT WILL BE PLACED AT STANDARD I 2 OPERATING CODE basker HAT ADDRESS WHEN MERGED WITH THE REVISION FOR INTERFACE TO PL 1 LORAN CODE DECODES ONLY GPIA DATA AND SENDS AN INTERRUPT TO HOST AFTER EVERY I 2 TO HOST DATA XFER INTERRUPT VECTOR IS PIOV STATWD BIT DEFINITIONS we we we we BIT 0 1 2 3 4 BIT 5 6 7 H GPIA FRAME PROGRESS RFU H GPIA FRAME READY FOR XMIT H SNRS OK ON S1 AND S2 H EPSCO FRAME IN PROGRESS RFU H EPSCO FRAME READY FOR XMIT RFU BIT DEFINITIONS BIT 0 BIT 1 BIT 2 H DECODE GPIA H DECODE EPSCO H DECODE BEST SOURCE BIT DEFINITIONS BI T 0 BIT 1 BIT 2 ICON COMSTA ADR1 PIOV GPIA EPSCO ETAG GTAG SNRTHR IRAM MOVER INTVCT DMADDR WIFLG MAXL BOTM GADDR H CHECK SNR ON NEXT BYTE H LAST SNR OK H LAST SNR OK ORG 029AH EQU 03000H EQU 05000H EQU 08000 1 2 HOST STATUS PORT EQU OF 8H HOST PIO INT VECTOR EQU 020H GPIA FRAME ID BITS EQU 010H EPSCO FRAME ID BITS EQU 01H GPIA FRAME ID TAG EQU 02H EPSCO FRAME ID TAG EQU 04H SNR LEVEL THRESHOLD EQU 01000H BASE OF TRANSMIT BUFFER EQU 0151H ADDRESS OF DMA TRANSFER ROUTINE IN 1 2 BASIC KERNEL EQU 023BFH HOST INT VECTOR STORAGE LOCATION EQU
18. and more acute needs have placed the military and commercial manufacturers in the forefront of workload human factors eng ineering research To date the techniques of this type of research have not been extensively applied to the general aviation area Special sideration has only of late been given to the needs of the general aviation pilot flying in the single pilot IFR regime In the past providing general aviation with means of travelling with increased ease and safety has been a subject of ongoing research by the participants of the NASA Tri University Program for research in Air Transportation Recent work on the applicability of Loran C to general aviation area navigation has demonstrated that this data source holds great promise Flight test experience with Omega Loran C and preliminary work on Global Positioning System Navstar combined with the previously mentioned needs for increased channel capacity for pilot craft links has provided the motivation for the work reported in this paper In the past much difficulty recording for matting and processing the output data from onboard experimental equip ment has been encountered Frequently pilots found extremely accurate position information difficult to interpret because the display format was unfamiliar or ambiguous These observations demonstrated that it is 10 possible to degrade overall pilot performance despite better situation information if this data is presented in a co
19. any running program but does not reset the system RAM thus the executable memory image loaded with DDT is not destroyed by the reset operation The monitor command P lt starting address gt lt end address gt F800 will then program the memory segment lt starting address gt to lt end address gt into the blank EPROM located at F800 FFFF Repetition of this process will place the entire executable memory image in EPROM Before execution of the EPROM based program the Pl memory map must be reconfigured so there are no address conflicts between RAM and EPROM The RAM from E700 F000 must never be deselected These locations are used by the Pl monitor initialization code will not run any code if the system RAM and stack space have been overlayed with EPROM Following reconfiguration of the memory map the ROMed code can be invoked by resetting the system and issuing a G starting ET instruction from the user consol For PL I code developed under the CP M operating system the starting address will be 0100H ANAMEM and STAR when combined with standard CP M utilities allow the production of ROM based programs written in PL I Since most experimental applications preclude disk drives the development of a technique for creating ROMed PL I programs constitutes a vital extension of the standard system software 75 Using the procedure described above a prototype Loran C based RNAV has been implemented Portions of the RNAV processin
20. board This memory block extending from FOOO FFFF con sists of two 2716 EPROM sockets Memory address conflicts between Pl onboard memory and off board RAM or EPROM are automatically resolved by Pl address decoders making it unnecessary to deselect off board memory from FOOO FFFF A block of 4k RAM 000 exists which cannot be accessed by Pl Essentially there is an additional 4k RAM available to any pro cessor capable of sharing Pl memory One of the two EPROM sockets on board Pl is occupied by a 2k monitor supplied by the manufacturer This monitor provides assembly language subroutines for basic communication with peripherals Pl has access to two serial ports one and a half parallel ports and up to eight floppy disk drives or an intelligent hard disk A real time clock is also implemented Standard Zilog interrupt daisy chaining is employed for all interrupt sources on board Pl This scheme permits nested interrupt execution The daisy chain control signals interrupt enable out IEO and interrupt enable in IEI are available at the parallel port B connector for adding other boards or external devices to the low priority end of the daisy chain Interrupt daisy chaining is fully documented in the Zilog product descriptions and applications notes for the 7 80 510 PIO and CTC chips Pl utilizes the 7 80 mode 2 interrupt protocol A time history of a mode 2 interrupt sequence is shown in figure 6 A low level on the processor INT line in
21. complex text handling procedures whose effects are immediately visible on the CRT screen It is expected that VEDIT will greatly facilitate the development and documentation of high level source code One problem with the standard PL I compiler is that the code produced js Hot formatted in such a way as to be directly put into EPROM The main difficulty is that PL I code employs a large language data area approx 8k which is accessed by various PL I library functions In order to pro perly execute code generated by the PL I compiler the 8k language data area must be initialized to the correct values Although the starting address and extent of the language data area is easily determined the function of each entry has not been documented and is not so easily determined Since the 8k data area would occupy one quarter of the available EPROM it is not 73 practical to store the entire data base with every program Prof Antonio Elias has overcome the difficulty by writing routines to compress the entire region into less than 2k bytes The program ANAMEM does this data compression Another program STAR reconstructs the entire data base from the output of ANAMEM By exploiting the large number of zero entries in the standard language data base this data compression technique allows ini tialization of large areas of RAM without having to store each byte s ini tial value Generally the compressed data base is stored in EPROM and STAR is us
22. special control byte CNTST Every time a byte is sent from Pl to P2 BTGO is decremented and control word bit 4 is reset Every second PMON sets bit 4 of the control word to a high level If after the next second PMON finds that bit 4 is still high then no transfers have taken place in the last second A malfunction is indicated if BTGO is non zero and no transmissions have taken place in the previous second In this case PMON will attempt to restart the cycle For diagnostic purposes a running total of the failures detected and corrected for is kept in the variable ERRCNT PMON contributes significantly to the reliability of the data link yet adds only a short section of code 41 bytes to the total length of the RTC real time clock interrupt service routine In addition PMON provides protection against externally induced failures and no command bytes are lost in the restart process Since the IPCP allows P1 P2 data transfer either in polled inter face or interrupt driven mode and the channel mode can be changed under software control without losing command bytes the user must choose care fully the mode appropriate to his application if the objective is to opti mize system throughput The code required to manipulate FIFO pointers and status flags adds a measurable overhead to the data transfer operation This overhead can be avoided by using the polled interface If P1 P2 data transfers will generally be in small infrequent bursts then t
23. the originally supplied graphics primitives Scion Corp is marketing a 4k extension PAKII which includes a variety of curved primitives The suggested method of communication between a host system in this case Pl and the Micro ngelo board P2 is a polled method in which the host reads the status port OFIH and passes a command byte to the data port OFOH when a ready condition is detected The objective of this com munication method is to prevent host command bytes from being written over each other in the MicroAngelo communication buffers In an application where large amounts of data are to be transmitted from host to video unit a great deal of time can be lost in polling the P2 status port This wasted time decreased system throughput since the host processor and the video processor are both tied to the communications task Another negative feature of the polled interface is that the waiting time between commands is a function of the execution speed of previous commands During execution of code with timing constraints entry into an idling loop could adversely affect performance these reasons a buffered interrupt 30 driven Interprocessor Communications Package IPCP has been written The two communication protocols are diagrammed and compared in figures 7 and 8 The firmware aspects of the IPCP will be explained in a subsequent chapter MicroAngelo only supplies status information at port Jum
24. volts and 16 volts DC was available At present attempts are being made to locate a manufacturer who will supply a switching power supply of sufficient wattage Switching supplies achieve efficiencies in excess of 90 and are capable of both step up and step down operation Because of the low dissipation in a switching supply and the absence of a large trans former switching supplies are generally smaller and lighter then conven tional power sources of the same wattage These properties recommend the switching unit for airborne applications where excess weight is to be avoided and electrical power is not abundant Resources of the system are divided among the three processors Each processor and support circuitry resides on a standard bus card In addition two memory cards a 64k dynamic RAM and a 32k EPROM card are attached to the bus There are several different standards for arranging the power and communication connections in digital systems consisting of several physically separate units The S 100 bus standard was preferred for several reasons Of primary importance was the popularity of this 25 particular bus with the manufacturers of the subsystems required for a complete microcomputer system The S 100 bus supplies a greater number of communications lines between the devices attached to the bus Compatability with newer 16 bit microprocessor chips was also an important consideration PO the IO processor has 2k dynamic R
25. 01 00 This command byte stream draws a vector from the graphics cursor location to the point with coordinates 0100H 0100H Upon receipt of the draw vector command code 91 P2 assumes the next four bytes will specify the end point of the vector to be drawn Assume an interrupt occurs after top level code has transmitted the 91 and before transmission of the vector endpoints Assume also that the interrupt service routine requires that the character E be typed in the lower left corner of the CRT Following 63 transmission of the ASCII 45 code for E Pl returns to execution of top level code and resumes sending the remainder of the draw vector com mand 01 00 01 00 The command stream sent to P2 will thus be 91 45 01 00 01 00 P2 takes the four bytes immediately following the 91 as the vector endpoints so the vector will actually be drawn to 45 01 00 01 rather than 01 00 01 00 A further complication is that the service routine may alter P2 internal status registers so that top level code execution cannot resume normally Of primary importance are the gaphic cursor location and the position of the alpha cursor The alpha cursor indicates the position of the next character to be written on the screen A similar function is assigned to the graphic cursor for vector point and region operations The garbled graphics caused by command meshing will occur whenever top level code producing graphic output can be temporarily suspended by a lower
26. 023B8H DMA ADDRESS STORAGE LOCATION EQU 023B5H DMA DIRECTION CONTROL BYTE LOC EQU 060H MAX RING BUFFER LENGTH EQU 01200H BASE OF PROGRAM SCRATCH RAM EQU BOTM 1 93 EADDR EQU GADDR 1 INLOW EQU EADDR 1 STORAGE FOR LOW BYTE INPUT INHGH EQU INLOW 1 TEMP STORAGE FOR HIGH BYTE INPUT CONWD EQU INHGH 1 LOCATION OF CONWD SNRWD EQU CONWD 1 LOCATION OF SNRWD GBASE EQU SNRWD 1 GPIA FRAME BUFFER BASE ADDR EBASE EQU GBASE 28 EPSCO FRAME BUFFER BASE ADDR BASR EQU EBASE 13 RING BUFFER BASE ADDRESS SCRAT1 EQU BASR 96 SCRATCH PAD RAM LOCATION BTGO2 EQU SCRAT1 2 CONTAINS OF BYTES IN RING BUFFER WAITING FOR PROCESSING OBASEl EQU GBASE 2 EQU EBASE STATWD EQU BTGO2 1 STATWD LOCATION MP SUPR JMP TO INITIALIZATION CODE INTSEV PUSH PSW START OF NORTHSTAR 6000 INT SERVICE ROUTINE MVI A 082H ENABLE HIGH ORDER BYTE STA 08001H LDA 08000H READ HIGH ORDER BYTE DB ODDH 077H 00 ANI 070H CHECK ADDRESS BITS FOR GPIA EPSCO JZ OK6 DB OC BH 6 8 A 40H JNZ OK6 IF WRONG DEVICE THEN QUIT LDA BTGO 2 CHECK TO SEE IF RING BUFF IS FULL CPI MAXL DB ODDH 23H CALL LCHK2 CHECK BUFFER LENGTH MVI A 081H ENABLE LOW ORDER BYTE STA 08001H LDA 08000H READ LOW ORDER BYTE DB 0DDH 077H 00 DB ODDH 23H CALL LCHK2 SAVE LOW ORDER BYTE OK6 POP PSW EI RETURN FROM INTERRUPT RETI DB OEDH 4DH LCHK2 LDA BTGO2 INCR OF BYTES IN RING BUFFER INR A STA BTG02 DB ODDH 22H DW SCRAT1 LDA SCRATI LOAD SCRAT1 INTO IX CPI MA
27. 0H OCBH 2 8 A 80H SNRWD SNR OK FLAGS SUPERVISOR ROUTINE FOLLOWING THE INITIALIZATION PROCEDURE AN IDLING LOOP IS ENTERED THIS LOOP SCANS THE RING BUFFER AND PROCESSES THE INCOMING BYTES 98 AS THEY ACCUMULATE IN THE RING BUFFER WHENEVER A COMPLETE DATA FRAME EPSCO OR GPIA IS READY AN ATTEMPT IS MADE TO TRANSFER THE DATA TO THE HOST PROCESSOR AT THE DMA TARGET ADDRESS SUPR ENABLE SUPR1 DB PUSH PSW PUSH H XRA A STA SNRWD STA EADDR STA GADDR STA STATWD STA INTVCT DISABLE I 2 TO FDC 1 INTS STA GADDR STA EADDR STA SNRWD STA STATWD STA BTGO MVI A 01H ENABLE GPIA DECODING STA CONWD MVI A 083H DISABLE OUTPUT ON DPTL STA 08001H LXI H ADR1 SHLD 023B8H SET DMA TARGET ADDRESS TO ADRI MVI A PIOV STA INTVCT 1 2 WILL RETURN PIOV DURING HOST INT 3ACKNOWLEDGE CYCLE IF PIOV lt gt 0 DB ODDH 21H INITIALIZE RING BUFFER POINTERS DW BASR DB OFDH 21H DW BASR MODE 1 INTERRUPTS DB OE DH 56H EI POP H POP PSW LDA STATWD IS A GPIA FRAME READY OC BH 2 8 A 40H CNZ XGP IF YES THEN TRY TO SEND IT LDA STATWD DB OCBH 6 8 A 40H IS AN EPSCO FRAME READY CNZ XEP IF YES THEN TRY TO SEND IT LDA BTGO 2 BYTES WAITING IN RING BUFF ORA A CNZ EXINT YES GO TO PROCESSING ROUTINE JMP SUPRI LOOP BACK TO IDLING LOOP CODE TO PROCESS A GPIA DATA FRAME XGP LDA CONWD 00 5 HOST WANT FRAMES DB DOCBH 0 8 A 40H CNZ SEGP YES TRY TO SEND
28. 40 pin 16 4 Connect the interrupt source to U40 pin 16 P1 Teletek FDC 1 Option Prewrite Compensation Set jumpers to provide 250ns compensation for eight inch disk drives p 10 Option Mini Maxi Floppy Selection Select maxi 8 inch drives p 11 124 Option Extended head load Select standard value 240ms head load time p 12 Option Wait States Select one wait state for onboard memory access only p 14 Option CPU Intelligent Controller Select CPU mode p 15 Option CPU clock Select 4Mhz operation p 16 NOTE Pl is configured with Memory option 2 p 18 The following procedure adds DMA support making P1 compatable with PO DMA operations 1 Connect S 100 pin 45 to U31 pin 9 2 Connect S 100 pin 77 to U31 pin 8 3 Connect U31 pin 10 to U30 pin 5 4 Connect U30 pin 4 to U30 pin 12 5 Connect S 100 pin 68 to U30 pin 6 6 Bend U7 pin 3 outwards no contact with socket 7 Cut trace to U12 pin 5 8 Connect U31 pin 13 to U12 pin 15 9 Connect S 100 pin 18 to U31 pins 11 12 10 Add a 1k pullup resistor to U31 pins 11 12 P2 Scion MicroAngelo Option No user options are changed from the standard values The following procedure allows command data to be passed to P2 via data port F2 1s Cut trace from U45 pin 9 to U29 pin 11 6 Cut trace from 045 9 to U53 pin 11 33 Connect remaining jumpers as indicated on figure 10 125 NOTE The P2 12v DC supply line has been connec
29. 9 CLEAR PENDING FLAG TOP OF STACK IS AT OFFOOH STACK OVERFLOW CAUSES RESET ENTRY POINT TO START A NEW COM SCHECK TO SEE IF ANYTHING IS ON STACK BOTTOM OF STACK IS AT OFAD4H IF ALREADY AT BOTTOM THEN DON T RESTORE POP OLD RETURN ADDRESS OFF STACK PUSH OLD PSW ON STACK PUT OLD HL ON STACK GET OLD BC GET OLD DE SAVE MOBY STACK POINTER VALUE RETURN TO TEMPORARY REG SET PUT MOBY STACK POINTER BACK IN HL LDDR COMMAND LDDR COMMAND EXIT3 Pl monitor program INX H SHLD MSP XRA A STA PPEND 08 OD9H DB 08H POP H POP PSW EI RET PUSH PSW XRA A STA PPEND POP PSW El RET 110 MSP MUST POINT TO A FREE LOCATION MOBY STACK POINTER CLEAR BAD XFER FLAG EXX EXAF RETURN TO WORKING REG SET POP OLD VALUE OF HL OFF STACK POP OLD VALUE OF PSW OFF STACK JUMP BACK TO OLD ADDRESS INTPS contains assembly language extensions to the 3 2 b These extensions include interrupt handlers and the appropriate interrupt table additions for the MicroAngelo and PMON service routines The enhanced capabilities of INTPS are enabled by making the changes listed below to the 3 2 b monitor 3 2 b Monitor Revision Procedure Program the instruction given at the indicated location Location F6EE Instruction JMP F800 JMP F880 JMP F8AA PARAMETER INITIALIZATION COMMANDS ENDL EQu DB 0A8H 0F9H RESTR OF900H DB 0A7H 00H 07H 0F9H 040H DB 0D4H O0FAH 00H
30. AM and 2k EPROM which con tains a control program Data transfers to Pl are via direct memory access DMA is capable of transferring up to bytes and can access or store data anywhere in the Pl memory map PO directly controls two 8 bit bidirectional data ports two 6 bit status input ports and two 8 bit latched control output ports In addition status and control command bytes be passed between Pl and PO through data port O4FH can communicate with peripheral devices either through the terminated status input lines or by 2 80 mode 1 interrupt The factory supplied IO routines have been patched at location 068H and a jump to scratch pad RAM placed at this address Any interrupt to PO will vector directly to the jump instruction at 068H The user is expected to insert the appropriate device handler at the target address of the jump instruction Pl the main processor responsible for numerical work coordinate conversions and subtask synchronization utilizes a full 64k address space A Measurement Systems and Controls 64k dynamic RAM board and a 32k EPROM card fill the P1 address space The RAM board supplies on board transparent refresh eliminating the need for external refresh generation circuitry RAM and EPROM can be overlayed in blocks as small as 4k RAM 26 can be deselected in blocks ranging from 4k to 32k EPROMs can be indivi dually enabled or deselected An additional 4k of memory is located directly on the Pl
31. CK POINTER MOV M E INX H MOV M D SAVE DE INX H MOV M C INX H MOV M B SAVE BC POP B INX H MOV M C INX H MOV M B SAVE HL POP B INX H SAVE FLAG STATUS MOV M C INX H MOV M B POP B POP RETURN ADDRESS OFF STACK INX H MOV M C SAVE RETURN ADDR ON MOBY STACK INX H MOV M B INX H ROUTINE TO RESTORE ENVIRONMENT RESTR OK SHLD MSP XRA A STA PPEND MOV A H CPI OFFH JZ 00H JMP 003BH EQY DI LHLD MSP A H CPI OFAH JNC OK MOV A L CPI OD4H JNC OK JMP EXIT3 POP H LHLD MSP DCX H MOV B M DCX H MOV C M PUSH B DCX H MOV B M DCX H MOV C M PUSH B DCX H MOV B M DCX H MOV PUSH B DCX H MOB B M DCX H MOV C M DCX H MOV E M DCX H SHLD MSP DB 08H 009 LHLD MSP LXI D CX2 LXI B 04H DB OEDH OB8H LXI D AX2 LXI B 04H DB OEDH OB8H 106 CLEAR PENDING FLAG TOP OF STACK IS AT OFFOOH STACK OVERFLOW CAUSES RESET ENTRY POINT TO START A NEW COM CHECK TO SEE IF ANYTHING IS ON STACK BOTTOM OF STACK IS AT OFAD4H IF ALREADY AT BOTTOM THEN DON T RESTORE POP OLD RETURN ADDRESS OFF STACK PUSH OLD PSW ON STACK PUT OLD HL ON STACK GET OLD BC GET OLD DE SAVE MOBY STACK POINTER VALUE RETURN TO TEMPORARY REG SET PUT MOBY STACK POINTER BACK IN HL LDDR COMMAND LDDR COMMAND 107 MACOD3 allows graphic output from several tasks to be multiplexed onto single screen MACOD3 ALLOWS THE HOST TO SAVE ALL P
32. CO BUFFER MVE2 LDA STATWD SET EPSCO FRAME FULL STATUS DB 6 8 0 STA STATWD RET SAVE EPSCO DATA BYTES SAVE2 LDA INHGH IS IT AN EPSCO DATA WORD ANI 07H CPI 07H YES BUT IT IS A LOAD RZ COMMAND SO DONT SAVE IT ORA A IT IS RESET COMMAND RZ DONT SAVE IT LXI H EBASE PUT EPSCO BUFF BASE IN HL LDA EADDR MOV E A INR A STA EADDR MVI D 00H DAD D ADD OFFSET TO BASE LDA INLOW MOV M A RET ROUTINE TO SNRCHK LDA CPI CHECK SNR LIMITS GADDR 017H CZ DCHK LDA CPI GADDR 018H CZ SNRC RET DCHK LDA ANI CPI I NHGH 07H 02H JZ SKP CPI 5 97 PUT BYTE IN FREE LOC SNR DATA WILL BE IN BYTES 23 24 IS IT BYTE 23 IS IT BYTE 24 BYTE 23 INDICATES THE SLAVE FOR SNR DATA IN BYTE 24 IS IT DATA FOR SLAVE 1 SOR SLAVE 2 IF FOR 1 2 THEN SET STATUS 350 NEXT BYTE WILL BE CHECKED AGAINST THE SNR THRESHOLD SKP 10 SNRWD DB OCBH 0 8 A 0COH STA SNRWD RET EXT5 LDA SNRWD DB OC BH 0 8 A 80H STA SNRWD RET SNRC LDA SNRWD DB OC BH 0 8 A 40H JZ EXT5 LDA INLOW CPI SNRTHR JM LSNR LDA SNRWD DB OCBH 1 8 A 40H JZ OK1 DB OCBH 2 8 A 0COH OK1 DB OC BH 1 8 A 0COH DB OCBH 0 8 STA SNRWD RET LDA SNRWD COMPARE SNR VALUE AGAINST SNR THRESH IF SNR TOO LOW THEN JMP TO LSNR OTHERWISE SET AN SNR OK FLAG LSNR IF SNR TOO LOW THEN RESET THE DB DB DB STA RET OCBH 1 8 A 80H OCBH 0 8 A 8
33. ETB 6 A SET BUFFER CONTROL BIT STA CNTST LXI H BTGO DID LAST BYTE FILL BUFFER MOV A M CPI 073H JC SKP LDA CNTST IF YES THEN SET BUFFER FULL FLAG SETB 0 A OTHERWISE JUST RETURN STA CNTST RET LDA CNTST TM SET BUFFER FULL FLAG SETB 0 A RES 6 A RESET BUFFER CONTROL BIT STA CNTST POP PSW RET ROUTINE TO INITIATE INTERRUPTS FROM MICROANGELO A TRANSFER IS PENDING IF THE COMMAND BUFFER IS NONEMPTY I E A BYTE HAS BEEN WRITTEN TO MICROANGELO AND FDC 1 IS WAITING FOR AN INTERRUPT IF NO TRANSFER IS IN PROGRESS BUFFER IS COMPLETELY EMPTY OR MICROANGELO FAILED TO GENERATE THE NEXT BYTE REQUEST INTERRUPT THEN START1 WILL CALL START2 TO RESTART THE INTERRUPT SEQUENCE LDA CNTST BIT 2 A IS XFER PENDING CZ START2 IF NOT THEN CALL START2 RET END 104 MACOD3 allows graphic output from several tasks to be multiplexed onto a single screen MACOD3 ALLOWS THE HOST TO SAVE ALL PROCESSOR REGISTERS ALPHA AND GRAPHIC CURSORS AND THE CURRENT RETURN ADDRESS VIA AN 01 COMMAND SENT TO PORT OF2H THE REGISTERS CURSORS ARE RESTORED AND EXECUTION BEGUN AT THE SAVED RETURN ADDRESS WHEN AN COMMAND IS RECEIVED AT PORT THESE TWO COMMANDS BE USED TO KEEP MULTI BYTE GRAPHICS COMMANDS FROM TWO DIFFERENT CODE SEGMENTS RUNNING IN THE HOST PROCESSOR FROM GETTING MERGED THIS REVISION CALLS RESTORE AS A SYNCHRONOUS OPERATION CX1 EQU OFFFBH CX2 EQU OF FFCH CY1 EQU OF FF9H CY2 EQU OF
34. FFAH AX1 EQU OF FDOH AX2 EQU OF FD1H 1 EQU OF FCEH AY2 EQU OF FCFH MSP EQU OF 940H sMOBY STACK POINTER 2 BYTES CMDL EQU OF942H7 SLENGTH OF CURRENT COMMAND MORE EQU OF 943H NO OF BYTES LEFT TO GET PPEND EQU OF 944H RESTORE ERROR FLAG lt gt 0 THEN RESTORE PENDING TBLBS EQU OF AC2H 080H BASE OF COMMAND LENGTH TABLE NUMB EQU OF 945H NO OF BYTES IN CURRENT COM IN MAIN BUFF TEMP EQU OF 946H TEMPORARY STORAGE FOR INPUT BYTE INX MOV INX MOV POP INX MOV INX MOV POP H M H M B SAVE BC B H M H M B INX H SAVE FLAG STATUS M H M B H M H M H SAVE HL MOV INX MOV POP INX MOV INX MOV POP RETURN ADDRESS OFF STACK C SAVE RETURN ADDR ON MOBY STACK CKBT SWBUFF gt LDA OFF42H ORA A 37 SWBUFF MVI A OFFH STA PPEND JMP 012CH LDA OFF42H ORA A JNZ 012CH IN OOH CPI O1H JZ SAVE JMP 0128H SAVE MICROANGELO ENVIRONMENT SAVE DB OEDH O5BH 040H OF9H 195 GET BUFFER FULLNESS IF BUFFER IS EMPTY THEN PROCEED OTHERWISE SET PENDING FLAG EXIT FROM WITH NO EI IS BUFFER EMPTY YET IF NON EMPTY THEN EXIT WITH NO EI AND HITHOUT READING THE COMMAND BYTE 01 5 COMMAND IF NOT 01 THEN DON T DO ANYTHING LDED MSP COMMAND LXI H AY1 LXI B 04H DB OEDH OBOH LDIR COMMAND LXI H CY1 LXI B 04H DB OEDH OBOH LDIR COMMAND MOV H D MOV L E SHLD MSP SAVE STACK POINTER DB 0D9H 08H PUSH PSW PUSH H LHLD MSP GET MOBY STA
35. ME BEEN FILLED CPI O1BH CZ MVE SIF YES THEN SET FRAME COMPLETE FLAG CALL RESYNC IF NO THEN START A NEW FRAME CALL SAVE SAVE FIRST BYTE IN NEW FRAME POP D POP H POP PSW RET RESYNC LDA STATWD SET STATUS TO INDICATE THAT A DB OCRH 0 84A 0COH GPIA FRAME IS BEING ACCUMULATED STA STATWD XRA A SET GPIA BUFFER POINTER TO BOTTOM STA GADDR BUFFER MVE LDA STATWD SET STATUS TO INDICATE THAT A FULL DB OCBH 2 8 A 0COH SFRAME IS READY TO BE SENT TO HOST DB OC BH O 8 A 0COH STA STATWD RET STORE A BYTE IN GPIA BUFFER SAVE LXI H GBASE PUT BASE ADDRESS OF GPIA BUFF IN HL LDA GADDR GET OFFSET FROM BASE FOR NEXT MOV E A EMPTY LOCATION INR A STA GADDR XRA A MOV D A DAD D LDA INLOW MOV M A SAVE BYTE IN EMPTY LOCATION CALL SNRCHK CHECK SNR LEVEL RET 96 PROCESS EPSCO DATA EPROC PUSH PSW PUSH H PUSH D LDA INHGH ANI OFH JZ ECHK LOOK FOR START OF EPSCO FRAME LDA STATWD 315 EPSCO FRAME ALREADY BEING DB OC BH 4 8 A 40H ACCUMULATED CNZ SAVE2 i YES SAVE BYTE POP D NO EXIT POP H POP PSW RET CHECK FOR START OF FRAME ECHK LDA STATWD SET STATUS TO INDICATE THAT AN DB OCBH 4 8 A OCOH EPSCO FRAME IS BEING ACCUMULATED STA STATWD LDA EADDR IS A PREVIOUS FRAME FULL OR CPI OCH 31S THIS THE FIRST ONE CZ MVE2 IF NOT FIRST ONE THEN SEND FULL XRA A FRAME TO HOST AND SET BUFFER STA EADDR POINTER TO BOTTOM OF BUFFER POP D ue POP H POP PSW RET MOVE EPS
36. P firmware IPCP routines are divided into task dependent routines and those which may be used in any experimental setup The PO control program represents the majority of the task depen dent code Specific input device formats rudimentary calculations and data stream filtering are tasks which vary from device to device A speci fic control program example is given below to illustrate the utility of the parallel processor hierarchy and the method of communication between Pl and PO Digital data from a Northstar 6000 Loran C receiver has been used in a series of experiments The Northstar supplies a serial output data stream at a rate of ipproxinstely 75 000 bits per second By taking data out of the receiver at the input to a parallel to serial converter a series of 15 bit words at a lower data rate of 5000 words sec can also be taken from the receiver The format of these words and a sample digital recording of position are given below Fifteen bit words are multiplexed into one of the PO 8 bit input ports by two of the PO control output lines Figure 11 shows the hardware used to buffer the receiver data bus and per form the multiplexing Sel lower byte lt Sel upper byte from PO ike e 03 16100 qe D7 74374 lt 7 06 MMC enses eed Shi ft Load from Northstar 6000 Northstar 6000 PPOD interface Figure 11 Northstar 6000 is a tradename of Digital Marine Electronics
37. ROCESSOR REGISTERS ALPHA AND GRAPHIC CURSORS AND THE CURRENT RETURN ADDRESS VIA AN 01 COMMAND SENT TO PORT OF2H n THE REGISTERS CURSORS ARE RESTORED AND EXECUTION BEGUN AT SAVED RETURN ADDRESS WHEN AN COMMAND IS RECEIVED AT PORT OFOH THESE TWO COMMANDS CAN BE USED TO KEEP MULTI BYTE GRAPHICS COMMANDS FROM TWO DIFFERENT CODE SEGMENTS RUNNING IN THE HOST PROCESSOR FROM GETTING MERGED THIS REVISION CALLS RESTORE AS A SYNCHRONOUS OPERATION CX1 EQU OFFFBH CX2 EQU OF FFCH EQU OF FF 9H CY2 EQU OF FFAH AX EQU OF FDOH 2 EQU OF FDIH AY EQU OF FCEH AY2 EQU OF FCFH MSP EQU 0F940H sMOBY STACK POINTER 2 BYTES CMDL EQU OF 942H LENGTH OF CURRENT COMMAND gt MORE EQU OF 9 43H NO OF BYTES LEFT TO GET PPEND EQU OF944H RESTORE ERROR FLAG lt gt 0 THEN RESTORE PENDING T8LBS EQU OF AC2H 080H OF COMMAND LENGTH TABLE NUMB EQU OF 945H NO OF BYTES IN CURRENT COM IN MAIN BUFF TEMP EQU OF 946H TEMPORARY STORAGE FOR INPUT BYTE INX MOV INX MOV POP INX MOV INX MOV POP H M C H M B H M H M B INX H SAVE FLAG STATUS M H M B H M H M H SAVE BC SAVE HL MOV M C INX MOV POP INX MOV INX MOV INX POP RETURN ADDRESS OFF STACK gt SAVE RETURN ADDR ON MOBY STACK B CKBT SWBUFF LDA OFF42H ORA A JZ SWBUFF MVI A OFFH STA PPEND JMP 012CH LDA OFF42H ORA A JNZ 012CH IN OOH CPI O
38. TO BE SENT CNTST EQU OE7F 3H STATUS CONTROL BYTE BASE EQU OE7F4H COMMAND BUFFER BASE ADDRESS START2 EQU OF8 53H ADDRESS OF ROUTINE TO INIT INTS NXTBT EQU OEGF EH TEMPORARY STORAGE LOCATION 5 BIT DEFINITIONS BIT O HIGH IF NEXT XFER TO BUFFER WILL FAIL BIT 1 HIGH IF XMIT BUFFER TO UA IS FULL BIT 2 HIGH IF A XFER IS IN PROGRESS IE INT PENDING BIT 3 CHK BIT USED FOR ERROR RECOVERY PROCESSING BIT 4 FORCE XFER BIT IF 0 THEN ROUTINE WILL WAIT UNTIL THE OUTBOUND BYTE CAN FIT IN BUFFER BIT 5 RESERVED FOR FUTURE USE BIT 6 BUFFER CONTROL BIT USED TO SYNC BUFFER EMPTYING OPERATION IN INTERRRUPT MODE OUTBT PUSH PSW STA NXTBT LDA CNTST BIT 4 A TRANSFER IN POLLED OR BUFFERED MODE CNZ OUTBT1 BUFFERED MODE LDA CNTST BIT 4 A CZ OUTBT2 POLLED MODE POP PSW RET OUTBT2 LDA BTGO CHECK TO SEE IF COMMAND BUFFER ORA A IS EMPTY IF NOT THEN WAIT TILL JNZ OUTBT2 IT IS BEFORE SENDING A BYTE IN OUTB2A IN OF1H THE POLLED MODE ANI O1H JNZ OUTB2A HAIT UNTIL MICROANGELO READY LDA NXTBT GET COMMAND BYTE OUT OFOH SEND TO MICROANGELO RET START OF CODE FOR BUFFERED COMMUNICATIONS BETWEEN FDC 1 AND MICRO ANGELO 102 COMMAND BYTES ARE STORED IN A 115 BYTE RING BUFFER AND TRANSFERED VIA AN INTERRUPT DRIVEN INTERFACE THIS CODE SHOULD NOT BE USED UNLESS THE THE FDC 1 EXT INT SUPPORT FOOO F7FF AND EXT INT TABLE F800 FFFF ARE ON BOARD FDC 1 AND THE S 100 PROTO BOARD IS ATTACHED THE
39. XL JC OVE2 DB ODDH 21H PUT BYTE INTO RING BUFFER DW BASR 0 2 RET 94 ROUT INE PROCESSES BYTES FROM THE RING BUFFER AND ACCUMULATES DATA FRAMES IN SPECIAL BUFFERS RESERVED FOR EACH TYPE OF DATA FRAME EXINT GET A BYTE FROM THE RING BUFFER PUSH PSW PUSH H PUSH B CALL GETBT STA INHGH CALL GETBT STA INLOW MVI A GPIA MOV B A LDA INHGH ANA B CNZ GPROC MVI A EPSCO MOV B A LDA INHGH ANA B CNZ EPROC POP B POP H POP PSW RET GET A BYTE FROM THE RING BUFF SAVE IN A TEMPORARY LOCATION GET THE LOW BYTE FROM RING BUFF IN A TEMPORARY LOCATION CHECK ADDRESS BIT TO SEE IF IT IS PART OF A GPIA FRAME IF NOT GPIA THEN CHECK TO SEE IF IT IS PART AN EPSCO FRAME 60 TO EPSCO PROCESSING CODE S RETURNS WITH BYTE FROM THE RING BUFFER IN THE A REGISTER GETBT DB 07 00 PUSH PSW DB OFDH 23H DB OFDH 2 2H DW SCRAT1 LDA SCRATI CPI MAXL JC OVE3 DB OFDH 21H DW BASR LDA BTGO2 DCR A STA 602 POP PSW RET PROCESS GPIA DATA GPROC PUSH PSW PUSH H PUSH D LDA INHGH RRC JNC NST DECREMENT BYTES LEFT IN BUFF 95 RRC JNC NST RRC JNC NST RRC JNC NST START OF FRAME MARKED BY BYTE JMP LCHK IF START OF FRAME GOTO LCHK NST LDA STATWD DB OC BH 0 8 A 40H IS A FRAME BEING ACCUMULATED CNZ SAVE YES THEN SAVE THE BYTE POP D NO THEN EXIT WITHOUT SAVE POP H POP PSW RET LCHK LDA GADDR HAS A PREVIOUS FRA
40. bit binary LSB TD2 24 bit binary MSB TD2 24 bit binary TD2 24 bit binary LSB TD3 24 bit binary MSB TD3 24 bit binary TD3 24 bit binary LSB TD4 24 bit binary MSB TD4 24 bit binary TD4 24 bit binary LSB Latitude 8 chars Packed BCD Latitude 8 chars Packed BCD Latitude 8 chars Packed BCD Latitude 8 chars Packed BCD Long 8 chars Packed BCD MSB Longitude 8 chars Packed BCD Longitude 8 chars Packed BCD Long 8 chars Packed BCD LSB Auxilliary data Figure 13 Sheet 1 3 24 25 26 27 41 0 Auxilliary data 0 Auxilliary data 0 Auxilliary data 0 Auxilliary data NOTE Identification bits for auxilliary data determine which of the following formats applies Identification Bits Content 1 Master auxilliary data 2 TD1 auxilliary data 3 TD2 auxilliary data 4 TD3 auxilliary data 5 TD4 auxilliary data 6 Common data Master and TD auxilliary data is given in the following format Byte 23 24 25 26 27 Content Cycle warning mode C MMMM SNR 2 words 10 bit binary in form 000SSSSS SNR 55555000 Blink SNR 10 bit binary 000SSSSS Blink SNR 10 bit binary 55555000 Common auxilliary data is given in the following format Byte 23 Content Manual cycle flag 0s manual cycle Figure 13 Sheet 2 3 42 24 GRI 16 bit binary MSB 25 GRI 16 bit binary LSB 26 Not used 27 Not used GPIA Data Frame Format Figure 13 Sheet 3 3 Ref Digita
41. ctronics Data bit 6 Reset Data bit 5 5 supply for keyboard electronics Data bit 4 Ground Data bit 3 PIO B strobe Data bit 2 PIO B ready Data bit 1 PIO A strobe Data bit 0 PIO A ready 34 36 38 40 42 44 46 48 50 122 Direction Step pulse Write data Write gate Track 00 Write protected Read data composite Not used Motor control optional Ref FDC 1 User s Manual Teletek corp 123 Appendix C Hardware Jumper Settings and Customization Procedures This appendix is organized into four subsections Each section deals with one of the three processor cards the fourth is devoted Lo configuration of the two memory cards The page numbers listed in each subsection will refer to the user s manual for the device being described PO Teletek I2 Option DMA Priority Set to FF p 4 Option Wait State Generation Set for one wait state on Ml cycles p 5 Option Interrupt line Connected to S 100 pin 73 p 6 Option Interrupt Daisy Chain IEI connected to PINTE p 7 Option EPROM sockets EPROM socket should be configured for 2716 EPROMs single supply 400ns access time p 8 The following procedure adds mode 1 interrupt capability to PO 1 Cut trace between 040 pins 16 17 This trace is located on the top side of the board under the U40 socket and can be cut by drilling through the bottom side of the PC board 2 Tie U40 pin 17 to 5 volts DC 3 Add a lk pullup resistor to U
42. der various conditions Initially PPOD will be used primarily for researching workload con ditions in the single pilot IFR regime The experimental program has been designed to progress through three levels of complexity These levels are distinguished primarily by the type of communication between aircraft equipment and the digital processors residing in PPOD Since each test 12 level contains a very large range of possible experiments the test program was not outlined as a schedule but rather as a conceptual breakdown enu merating three classes of experiments which will be of interest in the immediate future The first level involves no physical connections to the aircraft except for power cables PPOD will function primarily as an electronic copilot at this level Through a series of ground simulations and flight tests the extent to which an electronic scratchpad can aid a pilot will be determined Especially in the GA single pilot IFR situation pilots are required to utilize information from charts approach plates and instruments as well as heeding the instructions of a ground controller A small computer with easy data command entry and CRT display could provide a convenient method of organizing headings tower frequen cies takeoff or approach checklists airport elevations Projected appli cations include fuel consumption and weight and balance calculations for optimizing range An onboard real time clock will be used to sc
43. dicates an external device is requesting attention Device priority is determined by the position of the requesting device in the daisy chain The CPU acknowledges the interrrupt request by raising the INTA bus pin number 96 27 CPU completes execution of current instruction 2 before acknowledge Y L D 1 d Interrupting device puts its 8 bit interrupt vector on s the data bus during the CPU interrupt acknowledge cycle Simplified Mode 2 Interrupt Cycle Figure 6 28 to a high level Upon receipt of the INTA high level the interrupting device places an 8 bit interrupt vector on the data bus This interrupt vector is combined with an interrupt table base address to yield a 16 bit absolute memory address The contents of this address and the next sequen tial location contain the 16 bit address of the code to service the interrupting device Although the mode 2 interrupt level requires more hardware and involves more critical timing than the mode 1 interrupt level employed by PO the mode 2 level supports a greater number of interrupt sources and the location of the individual service routines can easily be altered since the table of service routine addresses resides in RAM Pl runs at 4 MHz clock speed Jumper options on the processor board program the unit to automatically men 1 wait state for all on board memory access Any reference
44. e and bearing from north of two points A a d B with known latitude and longitude Vu latitude longituie of point p s are latitude longituce of point B AA A cos sin EM C sin sind cese sint sint t cos coshA Angle of the arc from A to B measured from true North is 1 y tan Arc length from A to B is given by altan C 2555 4C jim C4 z 3443 nm Navigation Equations for RNAV Program Figure 24 80 WPF RAD CRS GS TRK TTG active waypoint display CDI arrow CDI error markings CDI centerline WPNT DISPLAY EE OFF DIST BRNG DES RAD waypoint entry review area ENTER COMMAND 2 command entry and error message display RNAV progran GRT Display igure 25 81 Chapter V Conclusions and Recommendations for Continued Research The previous chapters have covered the existing PPOD system from hardware firmware and software perspectives Clearly PPOD can support a very diverse set of experimental objectives both airborne and in the laboratory Because of PP0D s versatility any comprehensive listing of future objectives would be nothing more than a hinderance to future users rather I shall list a few areas of immediate interest some of which have served as the seeds from which the PPOD project sprang and some of which have grown out of the systems inte
45. ease in the demands placed on the pilot Of late particular attention has been focused on the transmission of data to the pilot and the reverse process means whereby the pilot can communicate his The tradenames listed below are used throughout this paper and belong to the indicated organizations MicroAngelo Screenware PakI Screenware PakII are tradenames of the Scion Corp FCD 1 I 2 are tradenames of Teletek Inc CP M PL I 80 LINK 80 are tradenames of Digital Research Inc DM6400 is a tradename of Measurement Systems and Controls Inc Vedit is a tradename of CompuView Products Inc Northstar 6000 is a tradename of Digital Marine Electronics Inc Z 80 is a tradename of Zilog Inc 8080 is a tradename of Intel control outputs to the aircraft The pilot instrument interface seems to be one of the major bottlenecks in the aircraft control loop The limited nature of the present day data paths between airplane and pilot first became evident in military applications Faced with a rapidly evolving task such as target acquisition performance of evasive maneuvers or aircraft carrier landings the combat flyer must monitor a large number of critical parameters while simultaneously providing control outputs The advent of STOL VSTOL and ducted fan types of craft has also compounded the difficulty of the control task in both the input and output areas In the civilian sector pilots are increasingly required to adsorb large amounts of da
46. ed to reconstruct the full data base at the start of processing code In addition to the ABSOLUTE CODE DATA and COMMON segments listed in a program s linking statistics there are two other portions of memory which must be preserved if reliable operation of the ROMed program is to be insured The first is that occupied by the compressed language data area This data must reside at the location expected by the reconstruction routine STAR The second auxilliary area is the region from 0000 0100 which is used by CP M for storage of system parameters These memory loca tions should be programmed int EPROM following a successful load and exe cution of the program to be ROMed Prior load and execution ensures that the system parameters put in EPROM will be x c ato 025 needed by the running program It is prudent to alter the system parameters slightly by programming a RET instruction at the BOOT and BDOS entry points 0000 and 0005 Programming of EPROMS must be preceded by creation of a fully debugged and properly executing CP M program If the program to be placed 74 in ROM is named RMCD then the executable menory image will be stored in the disk file RMCD COM following a successful tink The COM file can be loaded into system RAM via the DDT utility Once the file has been suc cessfully loaded the processor monitor is reentered by depressing the system reset button on the mainframe front panel This reset operation terminates
47. ee test levels described in chapter 1 To date most of the research effort has been devoted to definition of the PPOD architecture and implementation of a prototype Loran C based RNAV The computational power and mission flexibility of the PPOD multiprocessor should in the future be utilized at all three of the experimental levels of chapter 1 85 The current pace of hardware development makes is difficult even for rapidly moving production operations to keep abreast of the latest innovations In the space of a year most of the digital circuit boards used in PPOD have been obsoleted by new models and board revisions In spite of this fact PPOD will retain its utility as an experimental tool PPOD interfaces with much of the older equipment and its components will be compatable with the S 100 equipment of the next several years System architecture provides for modular upgrade as well Although designed to fulfill the general requirements of the three test levels described in chapter 1 already PPOD s versatility has led to unanticipated applications Two examples are use as a microprocessor development system for remote manipulator firmware simulation design and as a development environment for a microprocessor based airline scheduling system There is little doubt that PPOD multiprocessor versatility will continue to be utilized in a range of imaginative test programs 86 References Sheridan T B Ferrel W B Man Manchine Systems
48. ength 1 1 if 1 1_ 1 0 amp 1 1_ 1 1 0 then go to donel end i min 127 length i 1 mem2 o pos zi pos o 5 1 do to i mem2 o pos meml i pos 5 1 i 1 pos l end end else do do to min 127 length i 5 1 if meml i pos i g 0 then go to done2 end i min 127 length i_pos 1 2 1 0 pos o 5 1 1_ 1_ 1 mem2 o_pos 0 put edit o pos BYTES WRITTEN OUT OF i pos skip f 5 a f 5 end STAR reconstructs a data base from the compressed information contained in the output of anemem LOOP1 EXTRN TEST MACLIB 780 LXI B 0000H CLEAR BC LXI H 06800H SOURCE ADDRESS LXI 0 08000 DEST ADDRESS MOV A M LOAD NEXT BYTE ZEROS LOOP2 DONE CPI JZ UM INX MOV LDIR J MP XCHG MOV MVI MOV INX INR JN XCHG INX JMP EQU MVI STA STA JMP 0 9 0000H 0005H TEST 115 COMPARE WITH ZERO ZERO DONE IF NEGATIVE LOAD ZEROS GET NEXT BYTE PUT COUNT IN C TRANSFER LIKE CRAZY GET NEXT BLOCK REVERSE ROLES PUT NEGATIVE COUNT IN A ZERO ACCUM STORE A ZERO INC DEST ADD NOW IN HL DECREMENT NEGATIVE COUNT AGAIN UNTIL DONE ROLES OF HL AND DE PREPARE HL ADDRESS FOR NEXT BYTE AND GET NEXT BYTE PATCH A RETURN AT LOC 0000 HEX AND AT LOCATION 0005 HEX 116 Append
49. er XMIT buffe Receive Buffer FDC P ae 45 byte data transfers Figure 7 Le Main processor P1 15 byte command buffer PUSE R6 8 Interface routine 8 1 o lt Interrupt Vector Port 04FH Interrupt Jammer 1 2 Communication Data Flow P2 Graphics Firmware 8 Read Strobe Inbound HCBF data latch Figure 8 Interrupt Jammer Rev 2 Bi t 4 INTA NT 07 06 05 04 03 02 01 00 8 4 96 7343 9392 91 42 41 94 95 49 Figure 9 34 Addition of the jamming circuit to the graphics board as purchased from the manufacturer provides system users with a second high speed method of passing data from Pl to P2 In depth analysis of optimun use conditions for the two protocols is postponed until chapter III A second hardware addition to the P processor communications circuitry allows the video board to receive data command information via data port OF2H in addition to port OFOH Addition of the circuit shown in figure 10 was motivated by a need to support a high level graphics command set capable of suspending any lower level command execution Use of the added data port will be detailed in a later section Remaining hardware items are the inflight data entry device graphic output screen and development console Any video terminal uti lizing RS 232 C data tran
50. erally divided between two specialized pieces of software A control portion of the code adapted to synchroniza tion of the processors functions in an executive capacity allocating memory space and peripheral access time The executive is in turn controlled by an execution lattice Each task given to a multiprocessor is divided into subtasks A subtask is allocated to each processor The execution lattice contains all information relating to the order in which the subtasks can be performed Following the structure of the execution lattice the executive enforces the sequencing of subtask execution so that the maximum con currency of the job is exploited without causing resource conflicts Extremely careful analysis of the job is required to produce an efficient execution lattice without creating these conflicts Considerable skill is required to divide a job into a series of efficiently executing subtasks and create the proper execution lattice and executive The expertise and effort required for truly flexible multiprocessing have led to the adoption of a simpler approach in PPOD architecture Generally two of the scarcest commodities in any multiprocessor network are memory and communications channel capacity Since PPOD s processors have memory areas reserved for each CPU the communications resource is a more critical constraint An Interprocessor Commmunications Package IPCP has been implemented to ease 22 this constraint This body of firm
51. experiments with voice input output This is 34 an area which has not been extensively researched and may provide some relief for the already crowded visual data channels Addition of an S 100 compatable voice synthesis board would not require extensive software modification A simple voice feedback for keyboard input would allow pilots to enter command request data while looking at flight instruments Simulation flight testing offers unique opportunities and savings in cost Before extensive simulation testing can be done improvements will have to be made in the analog digital converters presently available Preliminary work has indicated that the conversion speed and resolution of the 12 bit A D units now installed in the PDP 11 10 computer are not adequate for pro ducing a stable display driven by analog simulator outputs Ref 7 Reduction in conversion granularity especially would improve the usefulness of the simulator PPOD PDP 11 combination Great possibilites exist for the coupling of a digital autopilot with PPOD Experiments involving RNAVs based on various raw data sources are only a few of the opportunities Implementation of weight balance and range optimization calculations do not require any additional hardware A series of qualitative workload studies would be the next logical step following implementation of an electronic copilot of the type described earlier These are some of the experiments as outlined under the thr
52. firmware modifications described in preceding chapters detracts from the operation of the units when operated in the manner intended by the manufacturer The capabilities of the PPOD system have been verified in a mobile environment through an automobile test run This test involved observation of the performance of a prototype Loran C based RNAV with CRT display Addition of a latched 8 16 bit multiplexor circuit to the Loran C receiver data bus provided a convenient method of taking position information from a Northstar 6000 receiver and the multiplexor also eliminated interference between the PPOD and receiver digital data buses An assembly language program run by the PO microprocessor controlled the viltintating and pro cessing of receiver data Following coordinate conversion calculations a CRT image providing destination cross track error and groundspeed infor mation was displayed to the operator Loran C position data was also recorded for later analysis Successful implementation of the RNAV demonstrates the power of a multiprocessor configuration the convenience of high level language capability and the ease with which PL I code can be linked to hardware dependent utility routines 83 From the results achieved a number of general conclusions can be drawn Experience date with the Loran C based RNAV and CRT display indicates that the inconvenience of time difference coordinates and hyperbolic grid navigation can be shifted t
53. g are done by the PO control program described earlier in connection with the task dependent portion of the IPCP The bulk of the data processing is done by PL I routines burned into EPROM PL I code for the RNAV was written by Prof A Elias This prototype RNAV has been tested in an automobile A plot of Loran C data from this test run is shown in figure 22 Inputs to the PL I processing code are derived from two sources the Loran C receiver and the RNAV user keyboard Present position is provided from the receiver in latitude longitude The RNAV user can program a sequence of waypoints to his destination Provision is made for adding deleting and inserting waypoints in a numbered waypoint list Although the position fix is based on Loran C signals waypoints are specified relative to the existing VOR network As with conventional RNAVs waypoints can be defined at a named VOR or at an entered range and bearing from a named VOR Use of this VOR approach to defining waypoints has several attractions Pilots are familiar with the existing VOR network and rho theta navigation The VORs and connecting radials appear on air route charts and the VOR geographic positions can easily be stored in EPROM Once the VOR positions are stored in EPROM the excellent accuracy of the Loran C network is accessable without the inconvenience of time difference coordinates Waypoints can be defined simply by entering a VOR name radial and offset through the co
54. gital data processing and flight experience are partially responsible for the flexibility of the PPOD archi tecture Prof R Simpson Flight Transportation Laboratory director has supplied both a congenial working environment and many profitable insights from his experience with pilot workload research Carter Pfaelzer Al Shaw Don Weiner Sue French and Paul Wetzel have all contributed much in the way of technical support and encouragement The research for this project was performed at the MIT Flight Transportation Laboratory facilities and staff were important throughout the project Digital Marine Electronics Inc provided one of their Northstar 6000 Loran C receivers for mobile testing The Transportation Systems Center DOT and especially Mr William Wade are to be thanked for providing a microprocessor development system during the early stages of the PPOD project Funding for the development effort was pro vided by NASA Langley Research Center through the Joint University Program for Air Transportation Research NGR 36 109 9017 Table of Contents Chapter E I Background and Introduction II System Hardware III The Interprocessor Communications Package IV Software Development Utilities and Examples V Conclusions and Recommendations for Continued Research References Bibliography Appendix A Software Listings Appendix B Hardware Modification Schematics Appendix C Jumper Setting and Custamization Procedures Appendi
55. gration and development effort The PPOD project development effort has achieved several important results A simple but nevertheless crucial task was the selection of the stock electronic boards on which the system is based From the large array of manufacturers offerring various combinations of features it was necessary to chose three or four whose products could form a substrate upon which further enhancements would be based The wide range of possible applications for the PPOD multiprocessor is an indication of success in meeting this requirement Initial component selection and purchase was followed by a series of enhancement modifications These enhancements include addition of Z80 mode 1 interrupt support to the PO processor the creation of circuitry and firmware to allow interrupt driven communication between the Pl and P2 processors and perhaps most important the addition 82 of the electronics and the graphics operating system extension required to multiplex several video data sources onto a single CRT Each of these modifications has been successfully implemented as an extension to the capabilities of the equipment as originally purchased Another objective of the process of integrating the stock components was to make the func tional extensions mentioned above without impacting the performance of the electronic submodules when operated in more conventional applications In every case this objective has been met None of the hardware
56. he next instruction to be executed 45 pushed onto the processor main stack and execution vectors to the appropriate interrupt service routine The SAVE routine pops this return address information off the main stack and saves the return address on the auxilliary stack A subsequent RESTORE will load the program counter with the return address from this auxilliary stack following restoration of the other processor registers and cursors 71 Chapter IV System Software Utilities and an Experimental Example A large amount of commercial software is available to the PPOD user The hardware and firmware sub modules described earlier provide experimen tal flexibility it is the high level language capability which makes this flexibility accessable on a rapid turn around basis The same criteria for hardware selection modularity simplicity reliability were the basis for lt software selection CP M is a widely used operating system for disk supported 8 bit microprocessors This operating system is adaptable to a range of hardware and once customized does not demand user expertise to write code exercising the full system capability In addition since CP M is extensively marketed there exists a large number of compatable software utility pack ages and special purpose IO drivers The standard CP M System includes the Basic IO System BIOS a text editor Dynamic Debugging Tool DDT and several assemblers ASM and RMAC Both ASM and RMAC
57. he buffer 61 control overhead of the interrupt driven mode may actually increase the amount of time spent on communications related tasks On the other hand tasks requiring frequent graphic output involving large amounts of vector aeneration blanking or region shading will benefit from the interrupt dri ven mode A choice between the two methods of P1 P2 communication should be based on the following benchmark data The routine to place a byte in the Pl graphics command buffer will take on the average 230 microseconds An additional 135 microseconds is required to transfer the byte from the Pl graphic command buffer to P2 The polled interface in contrast takes about 33 microseconds to transmit a single byte from Pl to P2 however this figure only applies if the first transfer attempt is successful After 12 loops the polled interface becomes slower than the interrrupt dri ven mode A conservative calculation indicates that the interrupt driven protocol should be used whenever more than 175 command data bytes are to be sent to P2 in a continuous stream More exact calculations depend on the type of graphic commands being transmitted A set of graphics primitives and utility routines is provided by the MicroAngelo manufacturer This package Screenware PAKI provides point vector region rectangular crosshairs and tracking cross graphics primitives A full ASCII character set in both single and double height is available as is a co
58. hedule the presentation of critical flight information PPOD can be instructed to measure time intervals and remind the operator to check flight status when a certain time has elapsed Storage of takeoff landing and emergency procedure checklists is also anticipated The second level involves one way data channels from aircraft instrumentation to PPOD s digital IO ports This level will include automatic selection of position information from several avilable data sources Engine status although a desirable feature may not be tested except in ground simulations Because a dedicated test aircraft is not available it is not possible to conduct tests requiring modifications to 13 PPOD Level I Objectives Real Time Clock Pacer Functions a Deliver pilot prompts on a preset schedule during critical flight phases Takeoff Landing Emergency checklists a Automatic checklist display verify Storage of information pertaining to flight conditions or destination a Information available at operator request b Information displayed at a scheduled time Flight Computer Functions a Cruise performance tables takeoff distance etc b Flight planning computations fuel consumption wind corrections weight and balance computations PPOD Level I Objectives Figure 14 PPOD Level II Objectives Navication a VOR Loran C and other interface capability 1 PPOD auto selects from several data sources 2 Coordinate transfor
59. ibed in the MicroAngelo user s manual SAVE instructions are sent to port F2 and suspend execution of any process initiated via bytes previously received at port F0 A software addition to the standard P2 operating system was also required It must be remem bered that P2 operates in a fashion similar to Pl Whenever a byte is written to P2 an interrupt to the P2 CPU is generated This interrupt invokes a service routine which determines the source of the request and takes appropriate action The code flowcharted in figure 21 has been added to the standard P2 service routine to support SAVE RESTORE operations A SAVE operation records the cursors and saves all processor registers as well as the return address in an auxilliary push down stack Subsequent RESTORE codes pop ihes values off the stack In the previous example if the service routine interrupting top level code issued a SAVE command the cursor values and the processor registers would be saved Just before return to top level the service routine would then issue a RESTORE command code resetting cursors to their former positions and restarting execution 65 Variables and Flags for MACOD3 Name Location 00E7 003B 0128 012C PPEND F944 MSP F940 1 FF42 Function Entry point to PAKI interrupt service routine Entry point to PAKI idling loop All command executions are initiated from within this loop Exit point from PAKI interrupt service
60. ill A T Optical Stimulator with Holographic Component AIAA Flight Simulation Technologies Conf 1978 paper 176 1978 McGlynn H J Jr Collins J W F Full Authority Microprocessor Digital Control GE Cos Binghamton NY Lynn MA AIAA paper 80 1149 1980 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 89 Measurement Systems and Controls Technical Manual DM6400 Series S 100 Dynamic Memory Boards Measurement Systems and Controls Inc Orange CA 1979 Miller G K Jr Riley D R The Effect of Visual Motion Time Delays on Pilot Performance in a Pursuit Tracking Task AIAA Visual andMotion Simulation Conf 1976 NASA Avionics Projections for Civil Aviation 1995 2000 Report CR 159035 NASA Langley Research Center Hampton V 1978 Palmer E Petitt J Visual Space Perception on a Computer Graphics Night Visual Attachment Visual and Motion Simulation Conference 1976 Peal R A The 767 s Flight Management System New Generation of Airborne Avionics Astronautics and Aeronautics vol No 11 Poole H H Fundamentals of Display Systems MacMillan and Co Ltd London 1966 Purser K Interactive Computer Graphics Boeing Commercial Airplane Co Seattle WA paper 8021589 1980 Reike R R Compu Scene Modular Approach to Day Night Computer Image Simulation AIAA Visual and Motion Simulation 1976 Reynolds R V Duncan
61. ite pointer WP and a count of the number of bytes waiting to be processed BTGO2 indicate the buffer status Sequential processing continues until no bytes are left in the buffer The synchronous portion of the control program reads each data word from two successive locations in the ring buffer determines the device address and enters the appropriate processing subroutine EPSCO data is transmitted with plotter control commands preceding and following each TD The EPSCO data routine deletes these command bytes from the data sent to Pl GPIA processing code assembles complete GPIA data frames Length 5 checking is done on each frame to make sure that noise has not introduced extranneous bytes or caused a byte to be lost SNR limits are continuously compared with the S1 S2 SNR values embedded in the auxilliary data portion of GPIA frames When sent to Pl both GPIA and EPSCO frames have as the first byte a special tag indicating whether the contents of the frame are EPSCO or GPIA All data transfers are by DMA operation The DMA target address in the Pl memory space can either be set at assembly time or dynamically changed by a sequence of command bytes sent to the PO command status port Before sending a fresh data frame to PO checks to see if the DMA target address location contains a non zero value If the target address contains zero then Pl is done with the last data frame and the DMA opera tion is completed If the
62. ix B Hardware Modification Schematics Interrupt Jammer Rev 2 JI HCBF INTA INT 07 06 05 04 03 02 D 00 4 96 43 93 92 91 42 41 94 95 49 Figure 8 1 118 P2 Hardware Modification 08 Pin 1 2 095 Pin 11 2112 MENT 1 45 e 93 2 Data Bus 115367 Bit 4 Pin B o Pins a U29 Pin 11 U53 Pin 11 Modification Procedure Cut trace from 045 Pin 9 to U29 Pin 11 Cut trace from Uh5 Pin 9 to US3 Pin 11 Connect remaining jumpers as indicated above NOTE All IC designations for this figure correspond with those of the P2 Scion Corp MicroAngelo user s manual Data Port F2 Addition Figure B 2 119 lt 2 5 1 1 ovte lt Sel upper byte from PO ot ro os 03 P0 Shift Load from Northstar 5000 Northstar 6000 PPOD interface figure B 3 Northstar 6000 is a tradename of Digital Marine Electronics 120 FAN FINGER GUARD of ses Jo Q Video Output 9 d Disk Drive CRCUIT 9 suem of lo y POLARIZED POWER RECEPTACLE OUTSIDE VIEW OF REAR PANEL Data IO Connector Locations Figure B 4 121 Serial I 0 Connector Wiring Contact ls 2 3 7 Function Not Used RS 232 Data input to PPOD RS 232 Data output from PPOD Ground Parallel Port A Connector Wiring Contact ls 10 11 12 13 14 15 16 Function Data bit 7 12 v dc supply for keyboard ele
63. l Marine Electronics corp Northstar Remote Serial Data Format 43 EPSCO Plotter Data Frame Format Information is transmitted from the Northstar 6000 receiver to the EPSCO plotter in a series of data frames Each data frame consists of the following sequence of words Word Number Identification Bits Contents 1 000 RESET command 2 001 Rightmost digit 1 3 010 Digit 2 4 011 Digit 3 Bs 100 Digit 4 6 101 Digit 5 Ta 110 Leftmost digit 6 8 111 LOAD command I3 is zero for the first slave TD and one for the second slave TD Each TD is encoded in BCD with one digit per data word Figure 14 Ref Digital Marine Electronics Corp Northstar 6000 Remote Serial Data Format 44 IUSER3 Variables and Flags The Northstar 6000 interface code can be configured in several dif ferent ways The various options can be selected by the user at source code assembly time by programming the control status variables listed below STATWD 1293 The STATWD provides bits for passing status information between parts of the program Bit 0 H gt A GPIA frame is being accumulated Bit 1 Reserved for future use Bit 2 H gt A GPIA frame is ready for tranmission to host Bit 3 H gt SNR levels for first and second slaves are above required thresholds Bit 4 H gt An EPSCO frame is being accumulated Bit 5 Reserved for future use Bit 6 H gt EPSCO frame is ready for transmission to host Bit 7 Reserved for future use
64. lH JZ SAVE JMP 0128H SAVE MICROANGELO ENVIRONMENT SAVE DB OEDH 05BH 040H OF 9H 108 GET BUFFER FULLNESS IF BUFFER IS EMPTY THEN PROCEED OTHERWISE SET PENDING FLAG EXIT FROM WITH NO EI 31S BUFFER EMPTY YET IF NON EMPTY THEN EXIT WITH NO EI AND WITHOUT READING THE COMMAND BYTE 01 SAVE COMMAND IF NOT 01 THEN DON T DO ANYTHING LDED MSP COMMAND LXI H AY1 LXI B 04H DB OEDH OROH LDIR COMMAND LXI H CYl LXI B 04H DB OEDH OBOH LDIR COMMAND MOV H D MOV L E SHLD MSP SAVE STACK POINTER DB OD9H O8H PUSH PSW PUSH H LHLD MSP GET MOBY STACK POINTER MOV INX H MOV M D SAVE DE INX H MOV M C INX H MOV M B SAVE BC POP B INX H MOV M C INX H MOV M B SAVE HL POP B INX H SAVE FLAG STATUS MOV M C INX H MOV M B POP B RETURN ADDRESS OFF STACK INX H MOV M C SAVE RETURN ADDR ON MOBY STACK INX H MOV M B INX H ROUTINE TO RESTORE ENVIRONMENT RESTR OK SHLD MSP XRA A STA PPEND MOV A H CPI OFFH JZ OOH JMP 003BH EQY DI LHLD MSP MOV A H CPI OFAH JNC OK MOV A L CPI 004 JNC OK JMP EXIT3 POP H LHLD MSP DCX H MOV BM DCX H MOV CM PUSH B DCX H MOV BM DCX H MOV C M PUSH B DCX H MOV BM DCX H MOV C M PUSH B DCX H MOB B M DCX H C M DCX H MOV E M DCX H SHLD MSP DB 08H 0D9H LHLD MSP LXI D CX2 LXI B 04H DB OEDH OB8H LXI D AX2 LXI B 04H DB OEDH OB8H 10
65. level routine also producing video commands The seriousness of the degra dation in CRT image will be a function of the number of possible interrupts and their frequency No degradation of video image would occur if it were possible to instruct P2 to suspend operation of the current command save graphic and alpha cursors and wait for a new command to be given Of course a command to reverse this process restore cursors and resume the previous comnand would also be needed Essentially two commands are required a SAVE and a RESTORE environment instruction The environment is assumed to consist of the positions of both cursors and the bytes already received in the current active command It might seem that all that is required is the definition of two new P2 command bytes This approach is not adequate for two 64 reasons Any byte appearing at port FO could be part of some other graphic instruction hence the SAVE RESTORE command bytes would be doubly defined A related consideration is that the SAVE RESTORE instructions must be able to override any command in progress It must be ensured that the environ ment manipulation command codes do not occur in any other possible instruc tion sequence A set of modifications was performed to solve these problems The hardware addition described earlier makes P2 sensitive to port F2 in addi tion to FO and Fl Command byte ambiguity is resolved by sending normal command data bytes to FO as descr
66. lternate Approaches to CIG Scene Detail Flight Simulation l echnologies paper 49 1978 California Computer Systems Model 2200 Mainframe Owner s Manual California Computer Systems Sunnyvale Cessna Aircraft Co Cessna Skylane Model 1820 Information Manual Cessna Aircraft Co Wichita Kansas 1978 Chang E T A VTOL Prediction Display Engineer s Thesis MIT Dept Aeronautics and 1969 Chang E T Evaluation of Elements In a Contact Analo Displa SM Thesis MIT Cambridge MA 1970 Church G W Ad vances in Avionics Bendix Corp Ft Lauderdale FL AIAA paper 79 0562 19 9 Denery Jackson Callas Berkstresser Hardy Integrated Avionics for Future General Aviation Aircraft NASA Ames Research Center AIAA paper 78 1482 1978 Digital Research Introduction to CP M _ Features and Facilities Digital Research Pacific Grove CA 19 76 1977 1978 Digital Research CP M Assembler User s Guide Digital Research Pacific Grove CA 1976 1978 Digital Research CP M Dynamic Debuqqinq Tool DDT User s Guide Digital Research acific rove 19 6 8 15 16 17 18 19 20 els 22 23 24 25 26 27 28 29 88 Digital Research CP M MAC Macro Assembler Lanquage Manual and Applications Guide Digital Research Pacific Grove CA 1976 1978 Digital Research ED Context Editor for the CP M Disk System User s Manual Digital Research Pacific Gro
67. mation and display format b Multiple waypoint storage automatic switchover when waypoint is reached c Variable display format 1 Moving Map Display 2 North Up Format 3 Expanded Scale Format Flight Status Warnings a Engine Electronics b Aircraft Configuration c Airspeed Stall warnings d Altitude Advisory e PPOD system fault detection self test Other Functions a Kalman filtering of navication data b Enhanced ILS display modes c DABS message display weather data PPOD Level II Objectives Figure 2 the instrument panel or the mounting of remote sensors in the engine com partment date most of the development work has been directed to this second level Presently a Northstar 6000 Loran C receiver is being used in a test level two mode PPOD has been programmed to monitor two data channels which the receiver multiplexes onto a single data bus Based on signal to noise thresholds PPOD automatically selects the channel which provides the best position information The raw data in the two channels provides enough information to compute position estimated time of arrival and ground speed An enroute navigation display is generated from these variables Eventually this data will be applied to final approach and enhanced ILS displays as well The third level of test complexity is characterized by two way interactions between PPOD and the on board equipment Although PPOD already contains the processing power nece
68. me The equations used for computation of position relative to a desired course are given in figure 24 and are based on those given in Ref 8 The magnitude of error incurred by the spherical earth approximation is well within acceptable limits for enroute navigation at up to 500 nm ranges These approximations would not in general be acceptable for non precision approach flying A sample RNAV output CRT image is shown in the succeeding figure In addition to the CDI arrow near the center of the screen there are three regions of interest The first is the active waypoint display shown at the top of the screen This region indicates the name number course radial ground speed and time to go relative to the waypoint whose position is used in the cross track deviation calculation the active waypoint At the lower most edge of the screen is the area used for command and error message display Immediately above the command error message display is the temporary waypoint display region This portion of the screen is used for review of previously defined and the display of other tem porary command status data The active waypoint display is independent of the content of the temporary waypoint display Only the A B cormands directly alter the contents of the active waypoint region 79 Arc length and Bearing Calculations Under the assumption of a spherical earth the following equations be used to the arc distanc
69. mmand entry keyboard The entire operator command set for entering deleting and changing waypoints is given in figure 23 Calculations involving geographic coordinates are done assuming a spherical earth however a series of linearized correction factors are v 4 Mobile Test Run Data Plot Unfiltered Loran C Data Figure 22 1 nm 94 77 Command Code Format Effect 6 10 Set CDI gain to 10 T Current course is toward Way point F F Current course is from Way point R 1 110 Set desired radial to 110 D D Delete waypoint shown S Sn Show name radial off set of nth waypoint A An Navigate toward nth Way point B B Navigate toward previous Way point E E 1 805 Define BOS VOR as first Waypoint l Insert waypoint before Way point shown Error Messages INSUFFICIENT DATA Command string too short INCORRECT DATA Alpha numeric expected in place of numeric alpha in command string WP NOT DEFINED User has tried to navigate to a way point which has not yet been entered via the E command AMED WP NOT FOUND User has tried to define a waypoint not contained in the system waypoint data base INTERNAL CONVERSION ERROR Overflow underflow in software arithmetic function RNAV program commands and error messages Figure 23 78 used to account for the deviation in bearing angle with longitude The correction factors are computed preflight and are entered directly into the program at compile ti
70. mplete set of user definable characters for high resolution character mode graphics A significant lack is curved pri mitives such as circular regions or portions of arcs The gaphics board 62 manufacturer SCION corp has recently made available a 4k extension to ae T correct these omissions This extension will be integrated in the near future Generally PPOD will be operated in a task environment requiring a large synchronously executed body of code hereafter referred to as the top level code and one or more smaller code segments invoked asynchronously by interrupt requests interrupt service routines Pl is responsible for coordinating operation of the other two processors and will usually execute the top level code and interrupt service routines with interrupt requests generated by PO P2 and other devices external to the PPOD multiprocessor All command and status information is passed between Pl and P2 via data ports FO and Fl however the status information supplied by P1 does not indicate whether the command bytes passed to P2 originate from top deve code or service routine code If the P1 P2 command byte stream contained only single byte commands this absence would not be important Since most P2 commands require more that one byte top level code interrupted by a service routine may produce garbled graphic output from P2 To draw a vec tor the following sequence of command bytes must be passed to P2 91 01 00
71. nfusing format Ideally it should be possible to alter the presentation of flight information indepen dent of the source of the raw data This paper contains documentation on a flight data processing platform which provides a means of addressing all of the questions detailed above The Programmable Pilot Oriented Display PPOD project has as its objectives the creation of a digital flight data processing and display system which supports the testing of both new navigation and new display concepts An additional objective was to determine the extent to which standard microprocessor technology could be conveniently adapted to the airborne environment These goals have resulted in a development program which differs considerably from market prototype production Size weight factors while still a consideration have been relaxed Room for future expansion and easy access for hardware maintenance modification have taken precedence over visual appeal Every attempt has been made to allow for system upgrade and to support the greatest possible range of experiments Such a development philosophy can result in a device which the potential user with such a bewildering set of features options and recon figuration choices that overall device utility is minimal A major motiva tion for the use of standard hardware and proven software was the desire to avoid complexity PPOD and the documentation contained in this paper constitute a compromise between
72. ng the command bytes one by one until its own 115 byte buffer is not full Whenever P2 s buffer becomes not full an interrupt will be generated to Pl Upon receipt of a buffer not full interrupt from P2 Pl will check to see if there are any bytes remaining in its own control command buffer Bytes remaining will then be send to the P2 command buffer until the P2 buffer is once again filled or until BTGO is zero Since the 1 2 data transfer is interrupt driven P1 is not occupied polling the P2 status port during execution of the entire map regeneration example The interrupt driven protocol allows P2 to excecute autonomously for up to one second Data transfer between P1 P2 depends on cyclic flow of command data status information sends a byte to P2 when P2 reads the byte an interrupt request is sent to the interrupt jammer circuit described in chapter II The jammer passes the INT request to Pl Pl responds by passing the next byte to P2 Clearly momentary hardware failure at any point in this cycle will cause the operation to hang indefinitely Especially critical are the status generation circuitry on board P2 and the 60 jammer circuit Due to the high noise environment and the catastrophic nature of even momentary hardware malfunction a performance monitor PMON routine has been created PMON executes once each second Execution history of the P1 P2 data link is contained in the bytes to go word BTGO and bit 4 of a
73. o a digital processing system with moderate intelligence Once these details are relegated to a computer use of the Loran C system will cause no increase in pilot workload as compared to a conventional RNAV system Use of the PPOD system has demonstrated that off the shelf electronics be used to achieve variety of experimental objectives both in the air and on the ground Detailed knowledge of the internal structure of the standard components can be used to integrate several modules into a multiprocessor In addition the PPOD development effort has shown that some of the advantages of multiprocessing can be achieved with ordinary equipment and carefully engineered interface modifications Throughput increases are available without the necessity of formulating the experimental task in terms of many subtasks an execution lattice and a multiprocessor executive Most of the immediate needs relate to improvements dn the peripheral equipment A high resolution direct drive CRT of standard instrument bay size would ease the logistics of flight testing The rather awkwardly packaged unit in use does not allow mounting close to other critical flight instruments A similar need exists on the input side A small key array perhaps kneepad or instrument panel mounted would contribute greatly to flight tests and add to the realism of ground simulations PPOD s multiprocessor organization and multiple memory maps provide a solid platform for
74. ol systems involving human decision making in a hybrid man machine environment Qualitative models of isolated sensory motor subsystems under rigidly controlled test conditions are available however the performance of the human operator under any realistic task constraint requiring the interaction of many sensory control subsystems has only been characterized in task specific terms This type of task specific characterization does not lend insight into the internal functioning of the human operator as a control loop element and thus is of limited usefulness in anticipating human performance in an environnent only slightly altered from that of the original test conditions Many instruments in use today especially in general aviation trace their ancestry back to the early days of aircraft development when the skies were not crowded and night or bad weather operations were rare Before new display and other man machine interface technologies can with confidence be integrated into the cockpit further quantitative and qualitative experiments oriented toward athemati cal characterization of the pilot as a control elenent wil be required Today researchers in a variety of disciplines are actively pur Suing the answers to questions which have a bearing on instrument design This type of inquiry has taken on a particular urgency as the capabilities of both airframe power plant and electronics have continued to expand in concert with a rapid incr
75. ons into a single board thus reducing power use and keeping mother board slots open for future experimental projects PPOD hardware resides in a metal case containing a 12 slot mother board AC power supply and cooling fan Forced air cooling is required for several of the logic cards because of the high component density A circuit breaker is included in the power on switch No front panel controls are available to the user except for a system reset button Connectors for two RS 232 C serial ports with handshaking lines disk drive composite video and parallel port are provided at the back of the cabinet Cabinet dimensions are approximately 12X8X18 inches The AC input power supply is sufficient for all laboratoy simula tion and software development work For flight tests a 300 watt DC AC 24 power inverter is used The inverter unit takes as input 10 18 volts DC ana supplies 120 volts 60Hz output Some undesirable characteristics of the power inverter are its square wave output and the inefficiency inherent in two levels of voltage conversion The harmonics in the square wave power output do not effect the digital logic but increased jitter in CRT images has been observed This noise source does not affect the Loran C reception if care is taken to ground the receiver Both electrical waste and the added weight of a combined DC AC power inverter and AC DC power supply could be saved if an airborne power supply capable of supplying 8
76. pers are provided to patch the status signals to the vectored interrupt lines of the S 100 bus however Pl expects all interrupts to conform to Z 80 mode 2 specifications To remedy this incompatability the interrupt jammer diagrammed in figure 9 was created Jammer circuitry monitors the S 100 INT INTA lines the P2 status lines and the P2 status port Whenever P2 status port bit 0 falls to a low level indicating a ready condition the jammer latchs an interrupt request pending signal The D FF and nand gate Save this pending interrupt until all prior interrupts are no longer being serviced P2 interrupt request is then latched by the upper S R flip flop which passes the request to the S 100 bus interrupt line S 100 INT is held at a low level until an INTA signal from Pl indicates that the request has been aknowledged The rising edge of INTA clears the interrupt request and enables the outputs of two 74LS173s which are connected directly to the S 100 bus An interrupt vector unique to P2 is thus placed on the data bus INTA falling edge disables the 173s freeing the data bus for other operations 7415221 dual monostables have been used for edge level and level pulse conversions An S 100 compatable prototyping card carries all of the jammer hardware Communication between P2 and the jammer card is via vectored interrupt line 0 S 100 pin 4 PPOD INTERPROCESSOR COMMUNICATIONS Fi Status Ca Data Single byte data transf
77. ponten contains the offset from base address where the next byte to be read and transmitted to P2 is located The difference mod 115 of the two pointer values is the number of bytes currently waiting to be sent to P2 Number of bytes left in buffer is stored in a separate location BTGO The FIFO is defined to be empty when BTGO 0 i e both read and write pointers are indicating the same location In addition to the 115 byte FIFO created in Pl memory space an equivalent FIFO exists in P2 memory Thus a total buffer space of 230 bytes is reserved for command storage Consider an example in which it is desired to create a moving map display or some other form of visual output which evolves in real time Assume that new data is available every 2 seconds as with the Northstar 6000 and that a new map indicating position with respect to certain land marks is to be generated with each position update In addition the entire map requires 200 bytes to specify 200 bytes 40 vectors Since vector generation routines are among the slower elements in the manufacturer supplied graphics package Pl will load up the 115 byte FIFO buffers Before placing a byte in the FIFO Pl checks to see if BTGO is zero If Main processor P1 115 byte command buffer N lt FUSE R6 8 Interface routine Port 04 8 8 i i 3 3 L i 1 t l i i l L
78. produce executable code from 8080 assembly language mnemonics In addition RMAC supports a full line of macro facilities These macro facilities have been used to implement the Z80 command set through the RMAC 8080 assembler and a 280 macro library RMAC produces relocatable object modules which can sub sequently be linked together forming an executable memory image DDT is used for loading tracing and executing 8080 hexadecimal instruction codes Via DDT memory locations and processor registers can be examined and altered 72 Although DDT and RMAC allow relatively convenient assembly language programming a high level language is generally preferred In the disk based development configuration PPOD supports a PL I compiler The compiler accepts PL I source code and produces relocatable object modules similar to those generated by RMAC Through the LINK utility PL I modules can be linked directly to assembly language IO drivers or interrupt service code PL I was selected as the high level language because it allows character _and bit string manipulations Bit string manipulations are vital when it is necessary to control specialized hardware from a high level language The CP M operating system is compatable with a number of languages including BASIC FORTRAN and APL however these high level languages have not been purchased To further increase the convenience of high level programming the VEDIT text editor has been purchased VEDIT allows
79. r is non empty and transfer is in progress L Transfer is not in progress H Check bit used for error recovery processing H gt Use buffered transfer mode L Use polled transfer mode H Reserved for future use L Reserved for future use H Buffer control bit used to synchronize buffer emptying operation when an overflow condition occurs Figure 18 55 Save byte in temporary location Put byte in buffer XFER in progres FUSER6 Flowchart Sheet 1 4 Figure 19 56 Read data Port Fl Logical AND with 01 Send byte to P2 out FO Set XFER in progress flag RETI FUSER6 Flowchart Sheet 2 4 Figure 19 Cont 57 Read data port fl Logical AND with 01 Send byte to P2 RETI FUSER6 Flowchart Sheet 3 4 Figure 19 Cont 58 from comm buffer Send byte to P2 Reset XFER in progress flag FUSER6 Flowchart Sheet 4 4 Figure 19 Cont 59 BTGO is in fact zero then Pl will write the byte to P2 command port Since P2 has a second 115 byte FIFO in addition to Pl s command buffer FUSER6 will pass the first 115 bytes written into the Pl command buffer directly to the P2 command buffer When P2 s FIFO is full the remaining bytes will be accumulated in Pl s FIFO buffer Once all 200 bytes have been placed in one of the two FIFO command buffers Pl can continue execution of some other task P2 will begin pro cessi
80. s underlying task structure dictated a modular approach at the hardware Flight Instruments Auditory Vestibular Tactile Cues Control Outputs Aircraft dynamics Enroute Control Chart Data 4 u s s A A ow PPOD PPOD Pilot Aircraft Data Flow Figure 4 8l 19 firmware level of system integration Following the outline of the test program the choice of hardware and software utilities was reduced to selec tion of components able to perform IO formatting and data acquisition coordinate conversion and arithmetic processing and finally generation of video output The rich array of experiments both in progress and pro jected is dependent on this modularity PPOD actually consists of three Z 80A CPU chips and support circuitry hereafter designated 0 1 2 In any of the operational modes PPOD s task can be divided into three distinct subtasks 1 data 10 2 control coordinate conversion number crunching and 3 video display generation 0 1 2 are assigned to each of these three subtasks as illustrated in figure 5 PO handles storage formatting and control functions related to the two 8 bit bidirectional data ports 16 latched control output lines and 12 status input lines PO may also handie reformatting and transmission checking before the data is passed to Pl All code dependent on the IO format of the device being tested in allocated to
81. s mentioned above Ground Simulation work is not correspondingly limited Extracting flight and engine status information from a simulator is electrically simpler and does not compromise flight crew safety Some work has been done with simulated landings using a prototype ILS display generated by PPOD and driven by digitized position signals from within the analog simulator Ref 7 These experiments have demonstrated that the combination of analog flight Simulator PDP 11 10 computer and PPOD represent an expensive yet ver satile simulation setup The PDP 11 can be used to simulate the digital outputs from navigation devices ranging from VOR to Loran C to scaning DME In addition the PDP 11 could be used to generate digitized engine status data Digitized information whether artificially generated or based on flight simulator outputs can then be fed to PPOD for processing and display generation A human subject completes the test control loop as shown in figure 4 The level I II III test plan organization has served as a quide in determining the required capabilities of the hardware and software included in the PPOD system Since the experiments at each level demand different performance it was necessary to select several component sub systems able to support the experimental objectives and to operate in a conceptually straight forward fashion The PPOD system architecture reflects the underlying structure of the objectives mentioned above Thi
82. set buffe address cnt Figure 16 Cont 48 Save byte frame Set XFER request Reset buffe address cnt Save byte Figure 6 cont 49 Check SNR against thresnold Change SNR status ind Save byte Figure 6cont 50 receiver produces a mode 1 interrupt to PO PO enables the outputs of the high order latch reads the contents of the latch and examines the address bits If the device address is not EPSCO or GPIA then no further pro cessing occurs If address bits are correct then the data is placed ina a ring buffer where it is stored for subsequent processing PO places the high order latch outputs in the high impedence or disabled condition and enables the low order output data which is also placed in the ring buffer at the location immediately following the high order byte Enough space in the ring buffer is allocated to contain two entire frames one of EPSCO and one of GPIA data Thus the buffer will be filled once every 2 7 seconds under normal operating conditions Use of the ring buffer as a temporary storage location for incoming data significantly relieves the software timing requirements The double buffered scheme allows processing to con tinue during the gaps when no data is being transmitted from receiver to PO Idle time is used to process any bytes in the ring buffer Once data has been placed in the PO ring buffer processing is synchrenous A read pointer RP a wr
83. sion back to the longer although slower data stream All communication between PPOD and the Northstar 6000 is handled by PO which is in turn directed by its control program This control program IUSER3 is flowcharted in figure 16 Control program processing follows the sequence described below Latching of new 15 bit word at the 39 Northstar 6000 Data Word Format Data representation inside the Northstar 6000 Loran receiver is as Shown below These data words are available in serial form at the receiver digital output jack and can also be accessed in parallel directly from the receiver s internal data bus 2 gt lt 1 gt lt 0 gt lt 13 gt lt 12 gt lt 11 gt lt 10 gt lt 07 gt lt 06 gt lt 05 gt lt 04 gt lt 03 gt lt 02 gt lt 01 gt lt 00 gt Where A2 A0 determine which of four possible output devices is being addressed 13 10 identify which word in the device data frame is being transmitted see device data frame formats D7 DO contain the data for the device and word specified by the contents of the A and I fields Figure 12 Ref Digital Marine Electronics Corp Northstar 6000 Remote Serial Data Format word Number 40 Northstar 6000 GPIA Data Output Format F o o cC C C QO O O O See Note Identification Bits Content GRI count 16 bit binary MSB GRI count 16 bit binary LSB 01 24 bit binary MSB 1 24 bit binary TD1 24
84. smission be used the laboratory Graphic and alphanumeric output from P2 is displayed on a 9 inch diagonal Motorola monitor display phosphor is P31 a relatively long per Sistance green phosphor Both 120 220 volt AC power settings are standard for the video monitor The unit used with PPOD has been modified to accept 12 volt DC as well In flight data entry is through a full size alpha numeric keyboard Such a unit is not practical for pilot data entry on pro duction equipment where an 8 12 16 key unit provides the necessary number of inputs PPOD s research orientation demands a full size keyboard capable of modest inflight system reconfiguration The 8 bit PIO port on the Pl card is used for keyboard input Power for the keyboard is taken directly from the P2 processor card 35 P2 Hardware Modification Pin 1 15 I 1 U4S Pin 11 2 ol 13 gt 4 gt 98 P2 Data Bus LS 367 i Bit 4 029 Pin 11 U53 Pin 11 Modi fication Procedure Cut trace from Uh5 Pin 9 to U29 Pin 1l Cut trace from Uh5 Pin 9 to U53 Pin 11 Connect remaining jumpers as indicated above NOTE All IC designations for this figure correspond with those of the P2 Scion Corp MicroAngelo user s manual Data Port F2 Addition Figure 10 36 Chapter III The Interprocessor Communications Package Complete subroutines for data transmission between the processors are provided by the Interprocessor Communications Package IPC
85. ssary to handle rudimentary auto matic control functions a great deal of work remains before any signifi cant experiments at the third test level can be conducted Instrumenting an aircraft with sensors which would allow PPOD to monitor all aspects of the flight will be a time consuming task If a digitized measure of fuel flow were available the data could be combined with navigation data to com pute projected range As modern autopilots are providing digital ports it will be possible to connect PPOD to these devices providing automatic course following ability Digital tuning of nav com receivers is another application to which PPOD is well suited Although scanning DME receivers are very expensive costs are dropping Coupled with the processor speed and IO flexibility of PPOD one of the scanning DME receivers would provide a wide coverage RNAV dependent only on an existing network of transmitters 16 PPOD Level III Objectives Lg PPOD Autopilot Link for automatic course following 2 Message Downlink capability 3 Avionics freguency mode control a Automatic selection of Loran chain and stations based on SNR and grid orthogonality considerations b Digital tuning of conventional Nav Com receivers PPOD Level III Cbjectives Figure 3 17 Although lack of a dedicated test aircraft has limited the type of experiments done to date PPOD has been designed to support a long range flight test program encompassing all of the level
86. ta Crowded skies a proliferation of navigation data sources and increased night marginal weather operations have demonstrated the inadequacy of many of the common techniques for presenting flight data As the necessity for increasing the capacity of the aircraft pilot data channel has been more clearly demonstrated more basic research has been focused on the human operator and his input output channels Results from modern control theory have been combined with conclusions based on data gathered from rigidly controlled experiments with human subjects to yield mathematical models describing the internal functioning of the human opera tor In addition information transmission theory and statistics have been used to construct measures of channel capacity which can be applied to both machine nachine and man machine data links The Shannon Weiner information measure provides a useful measure of data channel performance According to this result information is quantized in units of bits with khe d nds mation provided by an event x concerning event y given as I x y Log2 P x y P x Ref 1 The utility of this measure has been denonstrated in a variety of experiments involving humans in control and pattern recagni tion tasks Ref 1 6 Although most of the asks described in the experiments referenced are simple they highlight many of the individual characteristics which are combined in a complex task such as vehicle control Large budgets
87. target address location contains a non zero value then the previous frame is still being processed and PO begins accu mulation of another data frame Another degree of communications control is provided by the CONWD Various bits control the decoding of the EPSCO devices Bit 0 high enables GPIA device decoding bit 1 high enables EPSCO decoding bit 2 high causes conditional decoding of either EPSCO or GPIA device channels according to the SNR criteria mentioned previously Task independent code consists primarily of FUSER6 This body of code passes command bytes to P2 from Pl 1 2 communications occur either according to the manufacturer suggested polled mode or by an interrupt dri ven mode Operation of the polled transmission link has been described To pass a command byte to MicroAngelo P2 via the interrupt driven link all the user must do is place the byte to be transmitted in the A register 52 and call an FUSER6 subroutine named OUTBT OUTBT places the command byte to be sent to P2 in a 115 byte first in first out FIFO buffer This pro cess is illustrated schematically in figure 17 FIFO buffer stored in the form base address offset so the entire buffer is easily relocated in memory simply by changing the buffer base address Buffer organization is preserved by two pointers the write pointer location indi cates the offset from base address of the next empty location in the buffer the read
88. ted to the PIO connector pin 2 on the mainframe back panel This voltage is required by the keyboard presently used for flight data entry 32k EPROM memory board set up Various options on the EPROM card may be selected by the settings of four banks of DIP switche Most of the switches are set by the user to determine the system memory map These settings are fully documented in the user s manual for the card A few of the settings depend on the hardware operating environment Specifically Sl 5 disable should be off 51 6 enable should be on S1 7 wait state generation should be on and S1 8 C NS should be off In addition the Bank Data swithes S4 should all be in the off position Measurement Systems and Controls DM6400 RAM Board The 64k RAM card is configured by adding jumper wires to two DIP headers The headers should be wired as follows Header 1 18 pin DIP 1 2 Jumper 4 5 Jumper 6 5 Jumper 9 11 Jumper 126 13 12 15 14 17 18 Jumper Header 2 16 pin DIP 9 8 Jumper Jumper Jumper Jumper Jumper Jumper 127 Appendix D PO P1 P2 Memory Maps are given in this appendix 128 12 Memory Use Basic kernel of control program in EPROM Space in EPROM for user control program Not used byte communi cations buffer Not Used Scratch pad RAM and User code area System Stack Control Status port Command Status port Read Write buffer Address latch upper
89. to locations in the range F000 FFFF automatically generates a wait state The 32k EPROM card generates 1 wait state independent of processor wait state mode Pl and support circuitry consists of a Teletek FDC 1 r 2 In addi tion to the jumper settings which are fully documented in appendix C several slight modifications have been made to the Pl card DMA operations require that the S 100 address data status and control lines be tri stated according to rigidly specified bus timing instructions as part of the transfer of control to a temporary bus master The stock FDC 1 r 2 unit does not handle the transfer of bus control properly Two minor manu facturer suggested modifications were performed to correct this problem The changes are fully described in appendix C Future revisions of the FDC 1 processor card should not require this alteration 29 P2 the video processor is a Scion Corp MicroAngelo monochrome graphics board This unit accepts command bytes at port OFOH and provides status information at OF1H In addition provision is made for a light pen graphic input however this feature is not utilized at present Outputs from the MicroAngelo board are both direct drive and composite video A graphics package is supplied by the manufacturer The graphics routines are contained in two 2k EPROMs and are described in chapter III Sockets are provided for bu additional EPROMs This extra space is reserved for the addition of extensions to
90. ultimate flexibility and basic simplicity PPOD hardware software and the Interprocessor Communications Package pro vide a coherent operating environment in which it is possible to design 11 experiments This paper also provides a description of the boundaries to the operating environment and various techniques for exploiting the available system capabilities to their greatest extent One in flight function of PPOD is workload experimentation Especially critical for the evaluation of new display technologies is the question of how the new medium affects the intelligability of the data represented When a programmable link connects the data source with a CRT the type of data presented to the pilot and the way in which this data is Shown can be altered in flight In addition PPOD is able to generate secondary tasks or to contaminate valid flight data with extranneous visual information while simultaneously monitoring and recording the subject pilot s performance Essentially PPOD functions as one of the primary data paths between the pilot and his flight environment Since PPOD is program mable this data link can be artificially loaded until it saturates or dif ferent display formats can be subjectively evaluated in a similar flight regime In addition the information processed by PPOD can be recorded for post flight analysis Similar techniques have yielded important insights about the maximum channel capacity of the human sensory system un
91. ve CA 1976 1978 Ditital Research Link 80 Operators Guide Digital Research Pacific Grove CA 1980 Digital Research PL I 80 Language Manual Digital Research Pacific Grove CA 1980 Digital Research Computers 32K S 100 EPROM Product Specification Digital Research Computers Garland TX 1980 Electonics Division Electronics Research and Development for Civil Aviation Electronics Division of the Institution of Electrical Engineers Savoy Place London 1963 Eskenazi R Williams D S Modular On board Adaptive Imaging JPL Pasadena CA paper 7801 15 1978 Freuler R J Hoffman M J Experiences with an Airborne Digital Computer System for General Aviation Flight Testing hio State University AIAA paper 9 1834 1979 Green T VEDIT A Visual Editor User s Manual CompuView Products Inc Ann Arbor Michigan 1980 1981 Honeywell Demonstration Advanced Avionics System Function Description Honeywell Avionics Division Minn Minnesota King Radio Corp Kansas 1980 Imrich T Concept Development and Evaluation of Airborne Traffic Displays MIT Flight Transportation Laboratory report R77 2 Cambridge MA 1971 Kayton M Freid W ed Avionics Navigation Systems John Wiley and Sons Inc New York London Sydney Toronto 1969 Kirkpatrick G M Real Time Weather Display in the General Aviation Cockpit CMK Consulting Services Syracuse NY AIAA Paper 79 1821 1979 LaRusso J A G
92. ware is written in assembly language but can be accessed from high level languages Thus the multiprocessor hierarchy is largely transparent to the experimenter despite the potential for vastly increased throughput which results The preceding pages have desribed some of the experiments which PPOD makes possible Considerable effort has been put into creating a basic structure of compatable hardware and software forming a skeleton upon which high level experiments can be based Because the capabilities and limitations of PPOD are to a large extent defined by the interaction of the submodules outlined above the remainder of this paper is devoted primarily to their documentation Subsequent chapters will detail the hardware and software associated with each submodule or task element 23 Chapter II System Hardware PPOD hardware consists of a variety of S 100 bus compatable cards an S 100 mainframe keyboard entry device and CRT In addition a dual 8 inch floppy disk drive video terminal and line printer are used during software development Hardware selection was based on the following criteria versatility low cost ease in system upgrade reliability low power consumption A secondary consideration affecting choice of com ponents was size The GA aircraft places severe space restrictions on avionics While these space considerations are less important in a research application every attempt has been made to integrate several functi
93. x D Processor Memory Allocation Appendix E Hardware Software Vendors Page 23 36 71 81 86 87 91 116 123 127 131 18 19 20 21 22 23 24 25 List of Figures PPOD Level I Objectives PPOD Level II Objectives PPOD Level III Objectives PPOD Pilot Aircraft Data Flow Task Subtask Breakdown Simplified Mode 2 Interrupt Cycle 145 Byte Data Transfers P1 P2 Communication Data Flow Interrupt Jammer 2 Data Port F2 Addition Loran Data Buffer Circuit Northstar 6000 Data Word Format GPIA Data Frame Format EPSCO Data Frame Format IUSER3 Variables and Flags IUSER3 Flowchart P1 P2 Communication Data Flow FUSER6 Variables and Flags FUSER6 Flowchart MACOD3 Variables and Flags MACOD3 Flowchart Mobile Test Run Data Plot RNAV User Command Set Navigation Equations for RNAV Program RNAV CRT Display 13 14 18 20 27 31 32 33 35 37 39 40 43 44 46 53 54 55 65 66 76 77 79 80 PPOD Programmable Pilot Oriented Display A Digital Platform for Airborne Experimentation Chapter I Introduction and Background The innovative application of advanced electronics to the needs of the general aviation community has been slow process Economics govern ment certification requirements reliability considerations and pilot resistance are some of the factors which have caused this lag These reservations have been aggravated by a scarcity of reliable experimental information concerning contr

May 1982 - DSpace@MIT

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