Integrated circuit with embedded emulator and emulation system for
Contents
1. 3331 suoyonujsul 3431 3431 euo sejnoex3 0064 p 4 0063 F fick 0064 uut E Od OF jsenbay NOONINI Ul DIJO SMHDIS uUOHp nu Ja deis ejBuis sjes pues oj spuodse US 6 230 119 B1 Sheet 5 of 7 May 8 2001 U S Patent ZH vje YS pupululoo JO OJJUOOOJONA X enuyuoD JO shJOJS PDEA julodydelg ey uouonutsul Jeyp uounoexe 0000 jujodypelg poD anuuoo gt 3331 pop Jes sejnoex3 3431 weno ey 0064 0067 se n99x Od Ol jsenbey uoyp nu3 NOONWA UL q ejnoexe sos D 19 B 8 pipq snipis pues oj spuodsey ZNAJ Ul 61n9ex3 o4 VOIONAJSU eAOJA DHO oo ezio v YG v VQ CCLO V ONI V ONI Lelo uoponysuj YOOJg uoOup nug3 S Y V MIO OZLO dr 4ujocbipeug epoodo Sseippv uouonasuj jproeds p Busy juro d ioeig U S Patent May 8 2001 Sheet 6 of 7 US 6 230 119 B1 EMUCON Register EMUCON RD TE TESTUES JAN EAOUT TE CERE ERRARE EGER TN BETTE ET BM Pew Pew mw uw mw mw r RW Fig 8 U S Patent May 8 2001 Sheet 7 of 7 US 6 230 119 B1 TARGET DATA PROCESSOR US 6 230 119 B1 1 INTEGRATED CIRCUIT WITH EMBEDDED EMULATOR AND EMULATION SYSTEM FOR USE WITH SUCH AN INTEGRATED CIRCUIT TECHNICAL FIELD The present invention relates to an integrated circuit having an emulator embedded therein and to an emulation system for use with such an integrated circuit BACKGROUND OF THE INVENTION Executable code for a data processor such as a microcontroller requires testing2. expressed in hexadecimal are provided for internal user programme code and the addresses 2000H to FFFFH are allocated to external user code space The emulation memory is placed on another page of memory such that it remains hidden from the user Thus for example external US 6 230 119 B1 5 memory addresses F900H to FFFFH may contain a user programme whereas internal addresses F900H and above contain the emulation programme FIG 4 schematically illustrates the internal arrangement of a data processor generally illustrated as 20 whereby a programme address controller 22 holds the address of the next memory location to be read from This location nor mally points to a boot strap memory 24 which contains executable code to be used during power up sequences or for data exchange routines or to a user programme 26 which may be stored in an internal user code memory 28 or in external memory not shown The programme address controller 22 is responsive to an interrupt request handler 30 which as is well known in the art allows normal execution of a programme to be interrupted in order to respond in a predetermined way to specific events The data processor is arranged to execute an interrupt routine in response to an interrupt request and then to return to the user code when the interrupt routine has been completed The data processor constituting an embodiment of the present invention is also provided with an emulation request controll
3. the communications pod may commu nicate with the control data processor over a radio or optical based such as infra red communications link Advanta geously the or each communications pod has a unique identity such that a plurality of pods may be independently addressed by a single emulation control data processor Thus the emulation control data processor can control and or debug a plurality of target data processors within a target system Advantageously the or each interface element contains a local data processor for handling may timing features or handshaking required to communicate over the data link The local data processor may contain registers or memory for temporarily storing the register contents of an associated target data processor or may handle the modification of a block user program code i e changing the code or inserting a break point instruction In a preferred embodiment the or each interface element is a pod having three pins one for connection to ground one for connection to the power rail Vcc and one for connection to the pin on the target data processor for communication therewith It is thus possible to integrate emulation and debug features with a data processor thereby ensuring that emu lation has minimal effect on the operation of the target board As used herein emulation includes software debugging carried out using the target processor 10 15 20 25 30 35 40 45 50
4. 2 troller for causing the data processor to enter an emulation mode and dedicated registers for use in the emulation mode It is thus possible to provide a software driven emulator within a data processor which leaves the registers used by the data processor to execute tasks unaltered during an emulation or debug operation A software driven emulator is flexible and allows for practical purposes for an unlimited number of break points to be implemented Preferably the registers dedicated for use by a data pro cessing core also known as an arithmetic logic unit of the data processor during emulation can only be altered during emulation Advantageously a programme for controlling the opera tion of the data processing core during emulation is stored in a reserved non volatile memory area which is hidden from the use of the data processor Preferably the emulation controller can operate in a single step mode wherein the register status of the data processor or other information such as the contents of a stack or memory can be output after executing a single instruction of the user s programme Additionally or alternatively the emulation controller is responsive to a single byte instruc tion placed in the user code in order to initiate the emulation mode The single byte instruction is in general written over another instruction in the user s programme In order to ensure that the user s program performs as intended the overwritten ins
5. 4 A development system for use with a target data processor including an emulator wherein bi directional communication between said development system and the target data processor occurs via a serial data link utilising only a single pin of the data processor said development system comprising a control data processor and at least on interface element each providing an interface between the control data processor and a respective target data processor 5 A development system as claimed in claim 4 in which said at least one interface element provides electrical isola tion between the target data processor and the control data processor 6 A development system as claimed in claim 4 in which the at least one interface element contains means for causing a transition on the data link in order to cause the target data processor to enter an emulation mode 7 development system as claimed in claim 6 in which said transition causing means is controllable to transmit instructions to the target data processor 8 A development system as claimed in claim 4 further comprising a plurality of interface elements wherein each interface element is individually addressable by the control data processor 9 A development system as claimed in claim 4 wherein bi directional communication between the at least one inter face element and the control data processor is via a radiative data link 10 A development system as claimed in claim 9 in which
6. and correction during its development cycle Software debugging is initially done in a simulator or debugger offline Once the software is debugged it is then down loaded into the target system However if the software does not work correctly for example due to a timing problem it is then necessary to do an in circuit examination of the software and the data that it is manipulating It is known to perform this be removing the target data processor and replacing it with a replica of the data processor which can be probed or interrogated via an emulation pod The replica data processor emulates the real data processor and this process is called in circuit emula tion A disadvantage of known in circuit emulators is that the additional sockets clips adaptors or pods can induce extra parasitic components into the target system which alter its performance This usually restricts the emulation to a slow speed in order to avoid timing problems introduced by the parasitic components The use of such in circuit emulators can cause problems where debugging is to be performed in hybrid digital analogue systems where analogue accuracy is a critical issue especially when more than 6 or 7 bit resolution of analogue variables is used It was also known in the case of microcontrollers where the internal address and data busses do not come out to the pins of the data processor to produce a special bond out version of the circuit This has
7. contents of the target processor and allows for editing of instructions via a graphical user interface GUI The large size of the emu lation pod makes it inconvenient to use and also can give rise to subtle changes in operation of the target board due to the extra load and parasitic components introduced by the emulation pod Furthermore the known emulation pod uses a different or modified data processor which gives rise to changes in output driving characteristics and loadings which can effect signal timings and degrade analogue performance where analogue circuits or DAC or ADC s are involved As shown in FIG 2 an emulation system comprising a data processor constituting and embodiment of the present invention and an interface card 3 for providing galvanic isolation between the customer s target board and the emu lation control data processor 2 provides for a more compact emulation system and more importantly does not change the operating characteristics of the customer s target board due to the introduction of parasitic components The data processor having an emulator according to the present invention performs emulation under software con trol In order to achieve this a reserved memory containing emulation instructions is provided as an integral part of the data processor As shown in FIG 3a a data processor may have for example a memory space in which addresses 0000H to 1FFFH where H indicates that the addresses are
8. in the target board Similarly calibration coefficients in digital or hybrid digital analogue systems can be modified It is also possible when the interface element communicates using a radiative link to leave the interface element attached to the target board permanently thereby allowing for the target data processor to be re programmed even after it has been installed in a working environment The provision of an emulator as an integral part of the target data processor has the additional advantage that the board and processor being debugged developed are identical to the final system This contrasts with prior art emulators of the type shown in FIG 1 whereby the data processor on the emulation pod synthesises the functions of the target data processor but in often a physi cally different type of processor which may have additional hardware attached thereto to simulate the ports of the target data processor US 6 230 119 B1 9 What is claimed is 1 A data processor including an emulator wherein the emulator is arranged to perform bi directional communica tion with an external development system via only a single terminal 2 A data processor as claimed in claim 1 in which said single terminal is a control pin of said data processor said pin only controlling said data processor during a predeter mined operation 3 A data processor as claimed in claim 2 in which said predetermined operation is an initialisation sequence
9. the radiative data link is an infra red data link 11 A development system as claimed in claim 4 wherein the status and register contents of the registers of the target data processor used for program code execution are retrieved and stored during emulation 12 A development system as claimed in claim 11 wherein the status and register contents of the target data processor are returned to the target data processor before recommencing execution of a user program 13 A development system as claimed in claim 11 wherein the status and register contents of the target data processor are stored in an associated interface element 14 A development system as claimed in claim 4 wherein the development system is arranged to read a block of program code from an area of EEPROM within the data processor to modify the program code and to re present the modified code to the EEPROM of the target data processor 15 A development system as claimed in claim 14 in which the program code is modified by the insertion of a break point instruction at a chosen location so as to over write an instruction in the program code without changing the length of the program code 10 15 20 25 30 35 40 45 50 55 60 10 16 A development system as claimed in claim 4 in which the interface element automatically detects the data trans mission rate of an associated target data processor operating in an emulation mode 17 A developmen
10. to be manufactured into a bigger package to bring these extra signals to the pins so that the emulator can monitor them The bond out version is disadvantageous since it requires the chip manufacturer to create a second version of the chip and package with consequent timing differences from the read chip increases complexity and a need to provide an adaptor for connecting the bond out version of the chip to target systems in place of the standard chip package It is known to integrate emulation address comparators and emulation break point registers within an integrated circuit and then to perform a hardware compare of the contents of the address resister with the emulation break point register in order to determine when to force a break point for emulation purposes However the additional reg isters and comparators are wasteful of space on the silicon die of the integrated circuit and are inflexible in their operation An additional register and comparator is required for each break point Typically a designer may wish to have between eight and sixteen break points available The addi tion of sixteen or so additional registers and comparators can add a significant cost to the production cost of the integrated circuit SUMMARY OF THE INVENTION According to a first aspect of the present invention there is provided a data processor including an emulation con 10 15 20 25 30 35 40 45 50 55 60 65
11. 55 60 65 4 BRIEF DESCRIPTION OF THE DRAWINGS The present invention will further be described by way of example with reference to the accompanying drawings in which FIG 1 schematically illustrates a prior art emulator arrangement FIG 2 schematically illustrates an emulator constituting an embodiment of the present invention FIGS 3a and 3b schematically illustrate the memory organisation within a data processor constituting an embodi ment of the present invention in normal operation and in emulation mode respectively FIG 4 schematically illustrates the internal layout of a microcontroller constituting an embodiment of the present invention FIG 5 schematically illustrates the internal layout of a microcontroller constituting a further embodiment of the present invention FIG 6a to 6d schematically an emulation in a single step mode FIG 7 schematically illustrates an emulation using a single step break point instruction FIG 8 shows a layout of a special purpose emulation register and FIG 9 schematically illustrates the emulation system DESCRIPTION OF THE PREFERRED EMBODIMENT FIG 1 schematically illustrates a prior art emulator in which a large emulation pod plugs into the data processor socket on a customer s target board in order to provide interconnection with an emulator system comprising an emulation control processor running an emulator software package which typically displays register
12. a United States Patent Mitchell US006230119B1 US 6 230 119 B1 May 8 2001 10 Patent No 45 Date of Patent 54 INTEGRATED CIRCUIT WITH EMBEDDED EMULATOR AND EMULATION SYSTEM FOR USE WITH SUCH AN INTEGRATED CIRCUIT 76 Inventor Patrick Michael Mitchell Carrigeeval Ballyvalley Killaloe County Clare IE Notice Subject to any disclaimer the term of this patent is extended or adjusted under 35 U S C 154 b by 0 days 21 Appl No 09 019 789 22 Filed Feb 6 1998 51 Int CLA ies re GO06F 9 455 59 SC ooo entes 703 27 703 28 714 30 714 35 58 Field of Search 395 500 44 500 48 395 500 49 183 06 183 01 703 23 25 28 203 25 710 7 714 30 33 35 56 References Cited U S PATENT DOCUMENTS 4 272 760 6 1981 Prazak et al 341 120 5 313 618 5 1994 Pawloski ees 703 28 5 375 228 12 1994 Leary et al sss 714 33 5 467 200 11 1995 Ohsawa et al 358 426 5 488 688 1 1996 Gonzales et al 714 34 5 752 077 5 1998 Yiu etal 710 7 5 758 059 5 1998 Alexander 714 30 5 872 954 2 1999 Matsushita e 703 23 5 898 862 4 1999 Vajapey s 703 28 OTHER PUBLICATIONS Motorola DSP56100 Technical Data Section 10 On Chip Emulation OnCE online Motorola Corp Oct 7 1996 retrieved Aug 10 1999 Retrieved from the internet at Interrupt Request Next EA Step Break Pin single poin
13. e status of the various pro gramme registers to the emulation data processor 2 Once 10 15 20 25 30 35 40 45 50 55 60 65 8 the data has been sent to the emulation data processor the emulation data processor toggles the EES bit and issues a command causing the emulation to continue The emulator then returns control to the user programme Because the break point instruction is interrupt driven the control is returned to address 0120 which holds the A5 break point instruction This time the EES bit indicates that emulation should not be recommenced but in fact that the instruction in the EMU2 register should be executed The data process ing core executes the instruction in the EMU2 register and returns control to the user programme at the address fol lowing the break point instruction FIG 9 schematically illustrates a multi target develop ment system in which a single control data processor 2 communicates with a plurality of target data processors via a plurality of interface elements 3 each of which contain a local data processor 100 which reduces the computational load on the control data processor by performing the com munications protocols and also buffers and modified data in the target data processors in response to commands from the emulation control data processor 2 It is thus possible to provide a data processor having a software driven emulator embedded therein which uses dedicated regi
14. e step enabled and interrupt request is issued via the emulation controller 32 thereby causing control to be returned to the emulation code after a single instruction of the user code has been executed as shown in FIG 6c The emulation code then down loads data to the emulation control data processor 2 via the EA pin Down loaded data may include the status of the internal registers of the data processor but may also depending on instructions received from the emulation control data processor include the contents of the stack and also the contents of selected areas internal or external memory or the contents of an internal cache US 6 230 119 B1 7 FIG 7 illustrates an example of an emulation request initiated via the break point instruction The data processor has a data processing core supporting the 8051 instruction set The 8051 instruction set has a unused instruction code of AS The AS instruction has been implemented as the break point instruction It is known to initiate a software emulation or debug by including a jump instruction to the emulation code However there is a significant problem with this approach since the jump instruction is a 3 byte instruction and if this was inserted at address 0120 as shown in FIG 7 then the inc A and DAA instructions at addresses 0121 and 0122 respectively would be overwritten by the jump instruction Thus it would be necessary to change the addresses of the subsequent steps in order t
15. em as claimed in claim 25 where in graphical form is an oscilloscope trace 27 A development system as claimed in claim 4 wherein the development system is arranged to retrieve data from the at least one target data processor and to perform frequency domain analysis of the data said target data processor being production version of the data processor and not a special emulation version 28 An interface member for performing serial commu nication with a target data processor and for communicating with an emulation control data processor said target data processor including an emulator wherein bi directional communication between said development system and the data processor occurs via a serial data link utilising a only single pin of the target data processor 29 A development system as claimed in claim 4 in which the interface member is left permanently connected to the target data processor and communicates with the control data processor via a radiative communications link 30 An interface member as claimed in claim 28 in which the interface member includes local memory such that the interface member can read a block of program code form EEPROM of the target data processor modify the contents of the block of program code and rewrite it to the target data processor
16. er 32 which issues a priority non maskable interrupt request which takes precedence over all other interrupt functions The interrupt controller 30 is arranged to buffer incoming interrupts while the programme address controller is responsive to the emu lation request controller 32 in order to ensure that interrupt requests are properly serviced upon return from the emula tion mode The emulation request controller is responsive to three inputs A first input 40 is responsive to a voltage transition on a single pin of the data processor package In the preferred embodiment the pin is a EA pin provided on all ADuC812 data processor which is used to tell the data processor and it should execute from internal EA high or external EA low memory during the power up The state of the pin is latched by the data processor at power up or reset and thereafter it can be used as the emulation control pin The EA pin is also used when emulation has been initiated as a bi directional serial communications pin The emulation request controller is also responsive to a single step flag 42 which ensures that an emulation request occurs after execution of a single instruction of the user programme code Preferably the emulation controller 32 is responsive to a break point instruction 43 whose occurrence in the user code causes the emulation controller 32 to issue an emulation request As shown in FIG 5 a break point instruction decoder 50 is p
17. in the data processor i e within a single chip package are not critical to the present invention but a suitable memory and memory controller is described within a co pending application filed by Analog Devices and titled A MEMORY AND A DATE PROCESSOR INCLUDING A MEMORY The interface element 3 may provide a local buffer such that as the block of program code usually two rows on the internal non volatile reprogrammable user code memory of the data processor is buffered in the interface element and the local data processor modifies the data to change instructions or insert the break point and then re presents the data to the target data processor in order that it can rewrite the data into in s internal memory During execution of the user programme the programme counter will eventually point to the address 0120 which has the A5 emulation break point instruction written therein in place of the clear A instruction The instruction decoder of the data processor decodes the break point instruction and causes the emulation request controller 32 to issue a priority interrupt Thus the data processing core 54 discontinues execution of the user s programme and starts executing instructions from the emulation memory provided that the EES bit in the EMUCON register cleared Assuming that the EES bit is cleared the data processing core executes the emulation instructions using the reserved EMU1 register and outputs data concerning th
18. k involving one pin of the data processor package 30 Claims 7 Drawing Sheets Program Memory Instruction Decoder 52 50 Program Address U S Patent May 8 2001 Sheet 1 of 7 US 6 230 119 B1 Prior Art Microcontroller Emulator GUI Emulator Emulating Emulation Customer s i Target Board 2 Fig 1 g Emulator GUI Same Build in Chip used for Emulation Customer s Target Board U S Patent May 8 2001 Sheet 2 of 7 US 6 230 119 B1 NB User Does Not During Emulation Requests see Internal Emulation The Internal Emulation b uisi Memory is Activated External User gt Mode Interface Emulator GUI Internal User Mode Interface d ADuC812 E ADuC812 a b Fig 3 42 y EA Step Pin single kpoints 40 gle Breakpoin Emulation Request Interupt Request 30 2KB Boot EEPROM Next Program Program Address Address Controller 8KB Code Flash EEPROM 26 22 28 U S Patent May 8 2001 Sheet 3 of 7 US 6 230 119 B1 53 Program Memory 52 Instruction Decoder 90 EA Step Break Pin single points Emulation Request Interrupt Request Next Program Program Address Address Controlle EMU REG Fig 5 US 6 230 119 B1 Sheet 4 of 7 May 8 2001 U S Patent C DOJO YS JO JOJJUOOOJOI A PUDWLUOD JO SNOJS Poeti dejs ejDuis 9 9 0000 0000
19. ns between emulator programme operations The final two bits EA in and EA out enable the status of the EA pint to be read and written to respectively FIGS 6a to 6d schematically illustrate operation of the emulator in a single step code execution mode The emula tion routine takes advantage of the fact that the emulation interrupt will not respond until at least one instruction of the user code has been executed Thus once control has been passed from the emulator to the user code the emulator issues via a hardware resource a highest priority non maskable interrupt that ensures that programme execution is immediately returned to the emulator irrespective of what instruction was being performed Thus as shown in FIG 6a the emulation control data processor is arranged to issue an emulation request via the EA pin which causes a jump to the emulation memory This initially allows communication between the emulation con trol data processor 2 and the emulator in order that new instructions can be set in the emulator such as changing one or more of the flags in the EMUCON register in this example the control data processor sets the single step instruction ESS flag in the EMUCON register Once the emulation control data processor has indicated that it does not wish to set any further instruction changes control is relinquished from the emulation code and the user code is executed However since the EMUCON register was set with the singl
20. o incorporate the addition of this jump driven emulation instruction Secondly in order to use this approach the emulation memory programme must be visible for the jump to work and consequently the incorpo ration of the emulation code within the data processor would limit the user s programming options A third problem is that if the addresses of all the remaining code was not changed it would result in the instructions at 0121 and 0122 being lost and also an additional break point could not be inserted at the overwritten addresses By adding a single byte break point instruction only one address of programme is over written Thus in the example in FIG 7 only the clear A instruction at 0120 is overwrit ten by the inclusion of the software driven emulation break point instruction However the clear A instruction is written into the EMU2 register in order to ensure that it is executed as if the break point instruction were not there If a break point instruction is to be written into the user code for debugging development purposes the emulator reads out a block of memory containing the program code containing the address of the instruction to be changed An internal memory controller then erases the block of memory and in co operation with the emulation control data processor re programs the block of memory adding the break point instruction The precise memory control strategies for per forming the modification of internal memory with
21. responsive to a signal on the pin such as a voltage transition in order to activate the emulator Preferably the emulator is a software controlled emulator and comprises emulation instructions held as software within a reserved memory integrated into the data processor The receipt of the instruction to start emulation either by a signal on the emulator control pin or via a software instruc tion within the software being debugged forces the data processing core of the data processor to suspend execution of the user s programming code and to execute instructions from the emulation instruction code Preferably the receipt of an instruction to commence emulation causes a high level US 6 230 119 B1 3 non maskable interrupt to be issued to the data processing core of the data processor Preferably the data processor executes emulation instruc tions using reserved emulation registers thereby leaving the contents of the registers used for programme code execution unaltered except possibly for the programmed address con troller and the stack which may experience some minor and wholly reversible alterations Advantageously an auxiliary stack and or auxiliary programme address counters may also be provided solely for use within the emulation routine such that the registers programme counter and stack used by user executable code may be left entirely unaltered As an alter native dedicated registers may also be provided for storing the con
22. rovided to specifically handle the occurrence of the additional single byte emulation instruction break point instruction contained within user programme memory 52 which may be external memory or more likely internal memory area 28 Additionally a special register EMUZ 53 is provided to hold the instruction which was overwritten by the emulation request instruction thereby ensuring that the addresses of the remaining programme code are unaltered As shown in FIG 5 the processing core 54 also known as an arithmetic logic unit ALU has a dedicated set of reserved registers 56 EMUCON EMUI and EMU2 for using during emulation The reserved register set may also include an alternative stack and or programme counter for use during emulation FIG 8 illustrates the emulation control register EMUCON provided within a data processor including an embedded software controlled emulator Workings from the left to right the first three bits of the register form a control word which causes internal timers and clocks of the data 10 15 20 25 30 35 40 45 50 55 60 65 6 processor to be disabled if the correct code in this example 101 is written into these bits of this function register This enables the emulator to halt internal timers and interrupts when executing an emulation function The fourth bit is an emulation enable bit EE which is placed in the enable condition by default and enables emulation to be sta
23. rted when an appropriate emulation request is received by the emulation request controller The fifth bit enables execution of the contents of the special function register EMU2 When an emulation routine is started by the occurrence of the emulation break point in the user programme code this EES register is inspected in order to determine whether the break point instruction should actually be executed If the contents of this register are not set then the emulation will be performed When the emulation routine is completed the address pointer points to the address of the break point As mentioned earlier the original instruction which was over written by the break point is loaded into the EMU2 special function register and the bit EES is cleared As the emulation programme returns control to user code it sets the EES bit The address programme counter will return control at the address of the break point instruction However this time the EES bit is set and instead of re executing the emulation routine the processing core of the data processor is caused to execute the instruction held in the EMU2 special function register The EES bit is then toggled once the instruction in the EMU2 register is executed thereby ensuring that the next occurrence of the break point instruction will cause the emulation routine to be re entered The sixth bit is an emulation single step ESS bit which causes the data processor to only execute single instructio
24. sters thereby ensuring that registers used in execution of a user s programme do not become altered once the emulation mode is commenced It is also possible to provide a development system for use with such a micro processor in order that the internal registers may be inspected or blocks of memory may be inspected and analysis performed thereon For example a block of memory may hold values resulting from analogue to digital conversions The values may be displayed by the emulation control data processor in order to form an oscilloscope trace of the analogue value or additionally or alternatively may be Fourier transformed in order to perform frequency domain analysis The emulator may be used to perform a software controlled series of Analogue to Digital conversion and to send these to the emulator control processor which can then display a graph or trace of the converted variable The emulator 2 may display a plurality of windows with each displaying the status of and or controlling the function of a respective target data processor within a multi processor target board Thus the operation of master and slave pro cessors may be analysed possibly on a single step basis in order to check their data exchange operations and mutual performance The emulator has authority to modify the internal memory contents of program and data memory within the target data processor Thus the target data processor may be re programmed whilst it is in situ
25. t system as claimed in claim 4 in which the interface element performs handshaking and data exchange with the target data processor 18 A development system as claimed in claim 4 in which the interface element performs handshaking and data exchange with the control data processor 19 A development system as claimed in claim 4 in which the interface element moves control and data information between the target and control data processors 20 A development system as claimed in claim 4 in which the interface element communicates with the target data processor via a serial communications link 21 A development system as claimed in claim 4 and arranged to communicate with a target data processor such that a program code stored in an EEPROM of the target data processor can be programmed in situ 22 A development system as claimed in claim 4 in which the development system can modify programme instructions stored in an EEPROM within the target data processor and also modify data 23 A development system as claimed in claim 22 wherein said data includes calibration coefficients 24 A development system as claimed in claim 4 wherein the development system interfaces simultaneously with a plurality of target data processors 25 A development system as claimed in claim 4 wherein the development system is arranged to retrieve data from at least one target data processor and display the data in a graphical form 26 A development syst
26. tents of the program address controller In yet a further alternative the data processor may be arranged to down load the stack and register contents to virtual registers with an emulator control data processor or within an inter face element and to up load the register and stack contents when exiting the emulation mode According to a further aspect of the present invention there is provided a development system comprising a control data processor for monitoring the status of a target data processor wherein the target data processor includes an embedded emulator for communicating information con cerning the internal status of the target data processor via a serial communications link the development system includ ing interface element adapted to communicate via the serial communications link The interface element may be in the form of a pod providing electrical isolation between the target and control data processor Advantageously the pod provides bi directional communication between the target and control data processors and includes a controllable voltage generator for causing a voltage transient on an emulation control pin of the target data processor for forcing it to enter the emulation mode The voltage generator may also be used to communicate data and instructions to the target data pro cessor Advantageously the interface element communicates with the control data processor via a conductive link such as a cable Alternatively
27. truction is held in a special purpose register so that it is executed when the emulation mode is excited Additionally or alternatively the data processor may also be responsive to a signal on one of the data processor control pins in order to initiate the emulation mode According to a second aspect of the present invention there is provided a data processor having an emulator embedded therein and in which the emulator is initiated by a single work instruction According to a further aspect of the present invention there is provided a data processor including an emulator therein arranged to communicate information concerning the internal status of the data processor via a serial commu nication link Preferably the serial data link utilises a pin in the data processor package Advantageously the pin is multiplexed with a control function of the data processor For example some data processors include control pins which are only relevant during the power up initialisation of the data processor The pin may indicate to the processor whether it is to initially execute instructions from an internal or an external memory Once this information has been conveyed to the processing core of the data processor the pin becomes effectively redundant Such a pin may then be used as a communication link between the embedded emulation sys tem within the data processor and an external development system or emulator controller Preferably the emulator is
28. ts http www mot com pub SPS DSP LIBRARY 56100 FM REVO0 10 PDF Oct 1996 Motorola Digital Signal Processor Application Development System User s Manual Sections 1 5 online Motorola Corp Aug 13 1997 retrieved Aug 9 1999 Retrieved from http www mot com pub SPS DSP LIBRARY TOOLSDOC ADS DSPADSUM PDE Aug 1997 Ikos Grabs Emulation Firm VMW Electronic Engineer ing Times p 1 Mar 18 1996 Babb et al Virtual Wires Overcoming Pin Limitations in FPGA based Logic Emulators Proc IEEE Workshop on FPGAs for Custom Comp Machines pp 142 151 Apr 1993 Babb et al Logic Emulation with Virtual Wires IEEE Trans on Computer Aided Design of Int Circuits and Systems vol 16 Issue 6 pp 609 626 Jun 1997 Dahl et al Emulation of the SPARCLE Microprocessor with the MIT Vritual Wires Emulation System Proc IEEE Workshop FPGAs for Custom Comp Machines pp 14 22 Apr 1994 Babb et al The RAW Benchmark Suite Comuatation Structures for General Purpose Computing Proc 5th Ann IEEE Symp on Field PRogrammable Custom Computing Machines pp 134 143 Apr 1997 cited by examiner Primary Examiner Kevin J Teska Assistant Examiner Douglas W Sergent 74 Attorney Agent or Firm Wolf Greenfield amp Sacks P C 57 ABSTRACT A data processor is provided in which an embedded emu lator communicates with a control emulation system using a serial communications lin
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