FLT V4 User Manual
Contents
1. ShapingTime L 2 8 E 224 38 4916 5232 6264 7128 8256 GapLength N 0 7 N 0 7 Note N 0 if L2256 All parameters are in units of the time atom 50ns ADCdata Filter I E7 Filter II 4 eg zero point detector Filter amp Pixel Trigger Implementation Trigger An internal FIFO is used for delay element Z The depth of FIFO is limited to 512 so maximal delay 2 shaping time gap length is 512 This means also that settings of ShapingTime 8 256 and a gap non zero would excess the maximal FIFO length To avoid the overflow when ShapingTime is set to 256 the GapLength parameter will reset automatically and an warning flag at bit2 of PStatus is set PCI address 0x00000038 Bits Function Description Bit 0 StoreData store data into external RAM QDRII Bit 1 RunADC start ADC sampling Bit 2 FilterRun run the filter unit Bit 3 TriggerRun run the trigger unit 07 04 GapLength max 7 13 08 ShapingTime min 2 shaping time 15 14 00 reserved 31 16 reserved Table RunParam Register PCI address 0x00002080 31 20 19 Threshold channel i Table Threshold Format An example right shows behavior of the filter parameterized with ShapingTime 4 2 16 GapLength 5 and Threshold 19200 The measured energy is the height of trapeze triangle if GapLength 0 delivered by first2. A write of 0x02 data bit25 1 to any gain address causes a reset of the read pointer TP_switch TP_MEM_OUT AND TestPulseEnable TP EN 0 when TestPulseEnable 0 The amplitude and shape of the pulse are given by the SLT module The output of test pattern is delayed with respect to begin of the TPulse strobe by 100ns TEST PULSE STROBE TP_ENABLE AB SWITCH 000000 TestPulseEnable Mask 000000 FF 000000 I The TP MEM can be used as well as direct test pattern for the pixel trigger if registers PixelTriggerMode PixelSettings1 PixelSettings2 are set accordingly see Pixel Trigger Unit In this case each 24bit pixel trigger word is replaced by 24 output bits of TP MEM TestPatMem Test Pattern Memory 128x32 PCI address 0x001100 Addr 31 26 25 24 23 0 0x00 0 rst rep Test pattern first 0 rst rep 0 rst rep gef Ox7F 0 rst rep Test pattern 123 Table TP_MEM Format 9 Filter Unit Two cascaded FIR shaping filters are used in the actual KATRIN design to provide the accurate amplitude Filter I and time aaa stamp Filter II of a pulse A pixel trigger occurs when the extracted amplitude represents the energy of particle exceeds the threshold adjustable Both filter parameters shaping time L and gap length N are adjustable as shown below Frequency Response 1 stage Parameter Label Range Interpretation
3. Fco User test mode 00 off default 01 on single alternate 10 on single once 11 on alternate once Res et PN long gen on 0 def ault Reset PN short gen 1 on 0 off default standby 011 reset Duty cycle stabilizer 1 on default 0 off Output test mode see Table 9 in the Digital Outputs and Timing section 0000 off default 0001 midscale short 0010 FS short 0011 FS short 0100 checker board output 0101 PN 23 sequence 0110 PN 9 0111 one zero word toggle 1000 user input 1001 one zero bit toggle 1010 1x sync 1011 one bit high 1100 mixed bit frequency format determined by output_mode 8 Control of Analog Board Gain amp Offset Settings Sequence of Settings IPE AB Several gains and common offset on the analog board are controlled by three octal 3 8 24 12bit DACs MAX5306 for gains and one 12bit MAX5530 for offset connected as a chain via SPI bus to the CFPGA Gain and Offset values may be set read as e ablock of 25 words a common offset word 24 individual gains or e sequence of single access to OffsetAddr address 0x00080000 followed by a block of 24 gains addressed to GainStart address 0x00080001 or e sequence of single accesses Loading of data starts after setting of bit 8 LG in the Command register The load routine takes about 150us due to slow serial data transmission
4. a GPS unit and produces a zero phase delayed 20MHz system clock This is distributed to several FLT boards via clock fanout chips and aligned clock lines on the backplane The resulting delay of 3 5 nsec is compensated by internal PLLs in the FLTs GPS 1PPS SecStrb addr BEE RAM Address Timing Pixel Trigger PixTr extend PixTr p E Transmit Pixel Trigger Timing 20 Abbreviations FD fluorescence detector PMT photomultiplier FPGA field programmable gate array FLT first level trigger AB analog board SLT second level trigger JTAG joint test action group QDR quad data rate 21 References SLTman SLT user manual ADCds ADC datasheet PEbus Specification of PE bus ABman Analog Board manual 22 Appendix A
5. energy interpretation of event e precise time stamp of occurrence e to 100 us deep corresponding ADC trace in Run mode only else histogram The paging schema is used to handle the bursts of triggers The page lengths are 512 per board and 64 per channel All incoming pixel trigger are OR ed together to an overall trigger event whose occurrence causes an increment of the write pointer and storage the appropriate data into the EventFIFO consists of EventTable and PageTable see below EventFIFO is organized as FIFO depth of 512 so only one latest item can be read by SW Event Status register shows the current number of triggers write pointer and read accesses read pointer The overflow behavior of the FIFO is selected by setting of bit 24 of Control Register 1 stop when full 0 enable overflow EventFIFO Status Register 29 28 25 16 113 12 9 0 AE EF read pointer FF AF write pointer While fifo not empty is observed the program reads the last entry consisting of time stamp and channel list multiple pixels can trigger simultaneously decides on the channel number and gets then under specification of channel number the corresponding page number When channel and page indexes are known appropriate energy and ADC trace data can be read ADC data in Run mode only Event Table 512x64 11 blocks EventID Channel Map EventID Time
6. gt Trigg Timer lu uw e ou Unit Figure Trigger Concept 3 Subrack Architecture SLT slot FLT 1 10 FLT 11 20 Fan Unit Figure 1 19 Subrack 4 Backplane GTLP control bus i a d e m H a o M LVDS bus 16 bits 4 cntl 40MHz gt 80MB s BAR Eg CIk20MHz FanOut PTrigger bus LVDS 240 Mb s M LVDS Multipoint LVDS GTLP Gunning Transceiver Logic Plus Figure 2 Backplane Block Diagram 5 FLT Architecture The frontend module FEboard is separated in two submodules Analog Board AB and digital trigger board FLT to keep digital signal lines far away from the analog circuitry The main tasks of FLT are e A D conversion of 24 incoming analog channels e settings of gain individually per channel and offset common on the analog board e activation of the test pulse circuits on the analog board bac kades digital filtering threshold setting and eentrel for each channel pixel trigger detection measurement of trigger rate for each channel storage of ADC data into the QDRII memory ADC RAM or storage of energy histograms memory page management transmission of pixel trigger data to SLT transmission of ADC data to SLT overall FLT control CFPGA Timer Hit Rate RAM CNTRL Ser Transmit Event table Page counters Page table Energy RAM 300ns l Energy Ch 24 ee e Page Histogra
7. gt 32sec histMeasTime define histogram measurement period in sec PCI address 0x00004C 31 0 set time in seconds histRecTime second counter in range of 0 to histMeasTime 1 PCI address 0x000050 31 0 time in seconds histNofMeas number of histogram measurement cycles PCI address 0x000054 31 0 time in seconds postTrigTime post trigger time in bins of 50ns PCI address 0x000058 31 0 post trigger time 50ns steps Offset analog offset PCI address 0x001000 11 0 common offset Gain adjustable gain value per channel PCI address 0x001004 11 0 gain HitRate Hit Rate Memory 24x32 indiv channel PCI address 0x001100 B x5 us 18 17 16 n a x x Ov measured hit rate Ov overflow flag TestPattern Test Pattern Memory 128x32 PCI address 0x001100 31 25 24 23 0 rep Test pattern rep repeat flag pStatusA pStatusB pStatusC Peripheral Status Registers PCI address PStatusA 0x002000 PStatusB 0xC 0000 P Statuse 0x02A000 3128 27 20 19 1211110918 3 2 10 FID Histogram QUO es E err run page notempty E D 2 1 Cir Pg F mode P1 PLL1 unlocked P2 PLL2 unlocked OD QDR II DLL unlocked QDR RAM don t deliver the clock QE QDR II self test error flag mode mode of operation copy of Control register bits17 16 errF error invalid f
8. stage of the filter The first condition is met because of energy gt threshold The second trigger condition occurs when sloping curve of Filter II crosses zero The gradient at zero point determines the most precise time point as given be clock of 20Mhz This allows a time stamp resolution of tee 2 25 ns The time precision bit marks the appropriate half 0 left half 1 right half ADC trace 200 emp I 1 I I I I I 1 I l l I I 2543 130 140 150 160 170 180 190 200 210 220 230 240 251 Filter I out threshold Filter II out 50k Zero crossing 10 Pixel Trigger Handling A Pixel Trigger occurs in FPGA8 when filter output exceeds the threshold A trigger bit as well as energy value and two time precision bits packed to a telegram are sent serial each channel individually to CFPGA to store there the trigger data measure the hit rate and to send these further to the SLT via 240Mbit s serial LVDS link The transmission of a telegram takes 300ns so the equal dead time after a trigger is to respect for the very short filter lengths lt 2 When the CFPGA detects the first bit of a trigger telegram it takes the actual timer state and stores this together with received data into EventFIFO Timer Unit The timer in CFPGA consists of two counters e 13 bit second counter and e 25 bit subsecond count
9. 21 23 2 4 6 8 10 12 14 16 18 20 22 24 Trigger Chi Trigger Ch i 1 Pair Trigger Chi Pair Trigger Chi 1 Sum and Coincidence Triggering The veto triggering schema based on coincidence of at least N channels fiber ends with a sum of all six inputs The sum building occurs outside the crate analog Coincidence window and N are programmed in range of 0 250ns and 0 to 7 respectively Note that the involved thresholds should be adopted appropriate and the numbers of involved channels is fixed see below FLT group veto channels sum channel unused channel Groupl 00 02 04 06 08 10 14 channel 12 0 Group2 16 18 20 22 01 03 07 channel 05 0 Group3 09 11 13 15 17 19 23 channel 21 0 SumChannel A prolong Filter Channels 0 5 Unit ES stage 2 A prolong N fold coincidence time window 0 250 ns Figure 3 Sum amp Coincidence Trigger Block Diagram Further processing of veto triggers is identical to the standard mode RunControl Global Settings Run Parameters PCI address 0x000038 Bits Function Description Bit O StoreData store data into external RAM QDRII Bit 1 RunADC start ADC sampling Bit 2 FilterRun run the boxcar filter amp trigger units Bit 3 reserved 07 04 GAP length length of filter gap 13 08 FilterLength min 2 shaping time 15 14 00 reserved 19 16
10. Accessory new gains are stable only after 30ms settling time caused by blocking capacitor on the DAC outputs The summary delay 30 150 ms is indicated by the busy flag bit 8 in Status register Note Avoid any accesses to the gains while first 150us PCI Addr Chan Addr Data default base RAM 31 15 ll 0 0x00080000 0x00 Offset 0x0800 0x00080004 0 oxo serge ee Gain Chl 0x0800 0x00080004 TEM Gain Ch2 0x0800 0x00080004 EES 0x00080004 23 0x18 Gain Ch24 0x0800 Ox19 0x8000 update offset 0x8000 OXIA OxFFFF update gains OxFFFF OXIB OxFFFF update gains OxFFFF OxIC OxFFFF update gains OXFFFF Table GainRAM Format Test Pulse Circuit The test pulses are used to test the analog channels and trigger logic The SLT module provides the pulse shape and timings the FLT switches the several channels on off depending on the test pattern stored in the internal memory The internal FIFO TP MEM consists of 128 words of 25 bits 22 2 outputs repeat flag Each word represents the state of the 22 test pulses outputs The 50ns long strobe on the TPulse line forces the next memory word AND masked with TestPulseEnable to be put on the FPGAs output and increments the address afterwards The bit 24 repeat flag marks the end of pattern and cause the restart of read pointer This may be used to build the repeat loops
11. D PF power fail P1 PLL1 unlocked P2 PLL2 unlocked 00 FZK HEAT UP unlock phase 10MHz 01 FZKKATRIN ABFW Firmware type of analog board 10 FZK USCT ABHW Hardware type of analog board 11 ITALY HEAT SNE BoardiD error flag Bsy action busy flag EF eventFIFOstatus empty flag AE eventFIFOstatus almost empty flag AF eventFIFOstatus almost full flag FF eventFlFOstatus full flag hPg histogram page toggle bit hClr histogram cleared flag IRQ interrupt request Control FLT Module Settings PCI address 0x000004 31 25 24 23 20 19 16 15 54 32 1 0 fBeh mode MRE O LED stby LED set 1 to switch LED off stby FLT standby mode TPE enables the Test Pulse activities mode mode of operation 00 standby 01 Run I 10 Run II 11 test fBeh FIFO behaviour 0 enable overflow 1 stop when full Command FLT Command Register PCI address 0x000004 31 17 16 817 5 4 3 2 1 0 swTr rstPg rPoint LG rstTp swR rstTP reset TestPulse pointers swR set interrupt request for test LG load gains now rPoint reset pointers rstPg reset pages swTr SW trigger Version Number FLT Version Management PCI address 0x00000C 0x000010 PCI Addr 31 Version Number 15 8 7 0 0x0000000C Project N Doc Revision Version Revision CFPGA 0x00000010 Project N Doc Revision V
12. FLT V4 User Manual Project KATRIN Version 1 1 Denis Tcherniakhovski 25 November 2010 Contents Lo Introduction eege 3 2 Trigger COCO A A est 3 32 W brack EE 4 E ET EE 3 2 pd TC Iter ea ee ee tows tues chases EN DUE 6 6 KATRIN Modes of Operations una eh H un Model standard modes rede A 7 Run Mode II ET ea rennen 7 Test Maler aeia aa E n TA SANUS TE eeler 7 To A ede ei i uda dut ana QM D IN Gd uduss 8 8 GontroLof Analog Bridal 10 Gain amp Offset Settings Sequence of Settings IPE AB sse 10 Test Pulse A a e a N e a E E E A 11 Ke Ee EES 12 LO Bixel Trisser Handling eme toner see trad ee A A RER 14 Timer EE 14 Pixel Trigger Transmission to SET 2a 14 11 Trigger Data Storage internal DP RAM seen 16 12 ADC Data Storage 1M x 18bit ODRJD a ea na En 18 ADC DIAS ote tooo ec loe E A eticue 18 ADC Page Management O Dae 18 15 Histogram UNIN A A 19 14 Hit R te Me asar eN bs 21 O A A atone eta tenes 24 16 KATRIN FET Register Vel View c lodo 25 17 In Crate Communication PE Bus 5 inner ann es 30 Ne OT E E EE 31 19 Clock Distribution Synchronization Schema sse 32 205 JAbbrevidtiOns uo iia etes e dte req us ise acre LI Wardens seed a date ted 33 21 EE 33 225 JApDendbe A e east epa edevisd ven SU eo M eun sce cit un eT E 34 1 Introduction 2 Trigger SLT up to 20 FLTs m 24 channels E A T irs T D E
13. Stamp 9bit 24bit Seconds 32bit Subseconds 26bit Address EE 72 LONE EM 27 v 2 0 1 A E I mod 511 L Page Table 512 x 24channels x 6bit 16 blocks Event Page Number of Channels 1 24 ID 123 45 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 1 a A o EM m GESCETE o A ss E ORAN Energy Table per channel 24 blocks Page N Energy 20bit 0 1 Bey EH ADC traces per channel extern QDR RAM Page N ADC traces 0 block of 2048 ADC samples a 16 bit 1 block of 2048 ADC samples a 16 bit EN block of 2048 ADCsamplesal bit Event Handling Procedure Observe the event status read EventFIFOstatus not empty empty Event i TimeStamp i Read EventTable read EventTable Get the channel list a time stamp Channel List ChannelN Which channel s has have triggered hi Select channel number Channels loop Channel j Eventi read PageTable Pagek Channel j read Energy Pagek Channel j read ADCtrace Get the page number Energy i Read corresponding energy TimeStamp i Read corresponding ADC data ADC trace i If multichannel trigger select next channel 12 ADC Data Storage 1M x 18bit QDRII ADC Data Format Three 1Mx18 synchronous QDRII RAMs ar
14. clear mode 1 in sufficient time the histogram unit stops when HM 1 Set the CM 1 and HM 0 causes further accumulating of histograms The age of a histogram is shown in registers HistRecTime and HistNofMeas Programmable settings E Min HistgrSettings 19 00 E_Bin HistgrSettings 23 20 HistMeasTime HistMeasTime 31 00 HM HistgrSettings 28 CM HistgrSettings 29 Control bits CLR Command 17 Status HistRecTime HistRecTime HistNofMeas HistNofMeas FirstEntry HistLastFirst 15 00 LastEntry HistLastFirst 15 00 page not empty pStatusABC 19 12 Fixed parameters N_of_bins 2048 MaxHistCount 2432 1 32bit Timing histogram begin 0 15 gt 0 1 2 4 8 16 32K 0 2432 1 sec histogram mode 0 continuous 1 stop if not cleared before clear mode 0 automatically 1 clear by user clear histogramming page second counter 0 HistMeasTime 1 number of measurement cycles first bin last bin a flag per channel HistMeasTime in seconds i 4 I E Stop 1 1 1 f t 1 1 PageB PageA Page B y Readout Page B clear page B mode 0 i i continuous Page B Stop Readout Page B mode 1 stop if not cleared 14 Hit Rate Measurement The trigger rate is measured periodically for all enabled channels The measurement time is programmable in range of Teount 1 2 4 8 16 or 32 sec The overflow of some counters
15. e used to store the ADC data of 24 channels The address space of each SRAM is partitioned into 64 pages a 2K words Normally no trigger occurred the ADC data are written into the actual page organized as a ring buffer depth 2048 The 2K data frame as shown below consists of the 100us history and may be read out as block or via single Each data word consist of 12 bit ADC data and four auxiliary flags 15 14 13 12 11 0 PT Inh AF ADC Value 0 4095 PT Pixel Trigger flag Inh global Inhibit flag readout page AP Append this Page flag E ADC p samples t 8 NxtPage i read address E amp AppendThisPage Inhibit flag actual page write address Pixel Trigger ADC Page Management Each channel has a simplified page management implemented as a free running trigger counter The number of the actual page 0 63 equates to the trigger count 0 63 which increments delayed after post trigger time PostTrigTime When a next trigger i 1 occurs during the TE post trigger time of previous trigger i the page number increases immediately i 1 and flag AppendThisPage bit13 is set to mark the pile up AppendThisPage flag Page i lt TrostTrigTime gt Ti Tin 13 Histogram Unit For higher trigger rates above kHz the standard mode Run 1 is not capable handling several events The histogram mode Run ll can be used in order to dete
16. er The second counter can be set by sw ET Secstb _ and increments with every SecStrobe FLT SecStrb pulse The subsecond counter runs STI with internal 20MHz clock and restarts S cCount _ Second i second i n after every SecStrobe pulse Therefore d s Con NN o 1 first second is always to waiting for synchronization after each start of run mode Pixel Trigger Transmission to SLT The CFPGA sends a pixel trigger word filled out with start and parity bits to the central card SLT every 100 ns The start of transmission is synchronized to the internal 10MHz 23 22 1 00 S Pixel Trigger 21 00 P Table Pixel Trigger Link Data Fomat mM S Start Bit 1 P Parity Bit odd Several pixel triggers can be tied to a fixed value or replaced by different test pattern before sending to SLT This may be useful to mark the damaged pixels and for tests Both PixelSettings1 amp 2 registers define the state of the outgoing pixel triggers PCladdress 31 22 21 0 0x000030 0 LSBits 21 0 0x000034 0 MSBits 21 0 Table PixelSettings1 2 Registers The state of a pixel trigger is defined thus as MSBit LSBit Pixel Trigger Output 010 normal state 011 test pattern taken from the TestPatternMem 110 always 0 always 1 11 Trigger Data Storage internal DP RAM For each trigger event following data should be stored for readout e
17. ersion Revision FPGA8 Project N 1 for Auger HEAT Board ID unique Silicon Serial Number PCI address 0x000014 0x000018 PCI Addr 31 24 23 16 15 0 0x00000018 BoardiD 31 0 0x0000001C trcok Slot ID 0 BoardiD 47 32 IntMask Interrupt Mask Register PCI address 0x00001C 31 24 23 0 000 Interrupt Mask IntRequest Interrupt Sources PCI address 0x000020 31 29 28 24 23 0 SlotID Interrupt Sources hrMeasEnable Enable Hite Rate Measurement PCI address 0x000024 31 22 21 0 0 disabled default 1 enabled PixSettings Pixel Trigger Output Settings 1 amp 2 PCI address 0x000030 0x000034 Address 21 0 0x000030 LSBits 21 0 0x000034 MSBits 21 0 MSBit i LSBit i 00 0 1 0 1 _ Pixel Trigger i Output normal state test pattern taken from the TestPatternMem always 0 always 1 AccessTestReg Communication Test Register PCI address 0x000040 31 0 no effects SecTimer second counter PCI address 0x000044 31 0 set time to get actual time hrControl Parameters for Hit Rate Measurement PCI address 0x000048 31 24 16 15 3 0 zero HRsampl zero HRmeas HRsampl _ trigger sampling period for long triggers HRmeas Meas Time 0 1 sec 2 gt 2sec 3 gt 4sec 5 16sec 6
18. ilter parameters hPg actual histogram Page copy of Status register bit28 hClr cleared flag copy of Status register bit29 FID PFPGA number 00 A 01 B 10 C RunControl Global Settings Run Parameters PCI address 0x000038 Bits Function Description Bit 0 StoreData store data into external RAM QDRII Bit 1 RunADC start ADC sampling Bit 2 FilterRun run the boxcar filter amp trigger units Bit 3 reserved 07 04 GAP length Length of filter gap 13 08 FilterLength min 2 shaping time 15 14 00 reserved 19 16 veto overlap time 23 20 n fold 31 20 reserved HistgrSettings Histogram Parameters PCI address 0x00003C Bits Function Description 19 00 E Min 23 20 E Bin expected offset of ADC data 30 28 reserved bit 28 HM Mode of histogram bit29 CM Clear mode Energy energy value of last trigger indiv channel PCI address 0x002040 31 20 19 0 zero energy histFirstLast histogram first and last bins indiv channel PCI address 0x002044 E TE 0 Lastfnm FimtEnty Threshold Pixel Trigger Threshold indiv channel PCI address 0x002080 31 20 19 18 17 0 Previous 12 lower bits 00 Actual Threshold ADCsettings ADC settings status info ADCsettings 0x000400 ADCsettingsB 0x010400 ADCsettingsC 0x050400 7 0 ADC byte 17 In C
19. m counters Unit Channel 1 pages 0 63 eee e Run Model Channel 24 pages 0 63 e Run Mode II 3x e always running tasks DRII RAM 1M x 18 Figure FLT Block Diagram 6 KATRIN Modes of Operations Three different measurement schemas are available depending on preset mode e Run Mode I standard e Run Mode II for higher trigger rates e Test Mode for hardware and software test Run Mode I standard mode Active tasks are e Trigger logic filter comparator per channel e Trigger data storage energy timestamp e ADC traces storage e Hit Rate Measurement Run Modell histogram mode Active tasks are e Trigger logic filter comparator per channel o Trieeer data storage enerey timestamp per channel alecated inte 128 pages o _ADC traces storage alocated inte 128 pages aS50 uster 64 pages a400us andse terth e Histogram Unit per channel e Hit Rate Measurement Test Mode for test of the HW FW SW routines 7 A D Conversion ADC SPI port ADC PCI address space 0x000400 0x0007FC 256 Registers Table 15 Addr Param Bit 7 Memory Map Hex Name MSB Register Default Notes Comments Chip chip_port Soft Soft LSB first Configuration _ config reset 1 reset 1 1 0n0 Registers on 0 off on 0 7 off off default default default The nibbles should be mirrored so that LSB or MSB first mode registers correctly regardless of shift mode Defa
20. overlap veto overlap time 0 5 gt 0 250 ns 23 20 n fold n fold 0 7 31 24 reserved Interrupt Logic Two level interrupt mechanism is implemented at the FLT hardware layer Level 0 interrupt transmitted via INT line signals some error cases in FLTs Four possible error flags bits 3 0 are allocated for it Level 1 interrupt SpareOut P2 D2 line is used to inform SLT about the transaction status Interrupt signals on the backplane are active low when INT IntrptSources 3 0 amp not IntrptMask 3 0 SpareOut IntrptSources 7 4 amp not IntrptMask 7 4 PCI address 0x000014 31 29 28 24 23 16 15 8 7 0 000 Slot ID 0x00 Intrpt Mask Intrpt Sources RO RW RO Table Interrupt Register Bit Settings Interrupt Sources Bit 0 ConfigError Error0 FPGA configuration failed Bit 1 SyncError Errorl Second strobe in an unexpected time window Bit 2 HitRateOver Error2 hit rate counter s overflow Bit 3 ParamError Error3 settings conflict Bit 4 Action Done Bit 5 Action2Done Bit 6 Actios3Done Bit 7 Action4Done 16 KATRIN FLT Register Overview Status FLT Module Status Register PCI address 0x000000 31 23 16 1159 8 7 6 54 3 2 1 0 IRQ hIhHIEIATIATIEI interrupt Bsy AB AB U P P P Cri Pg be PURE LE sources HW FW EMEN
21. rate Communication PE Bus PE Bus Address Format 3 3 2 2 2 7212 217212 2 a ee 0 0 0 0 0 1 0 9 8 7 6 5 4 3 2 oloro 7 6 5 4 e 1 0 7 AEN 2 1 slot id channel z DS z page number lower address 1 20 31 0 23 31 MINO 0 63 PCI Address Format 2 2 2 2 J J 1 1 1 OI ON OO ON ON En 3 2 1j0 9 8 7 6 5 4 aa A OA SA Zu slot id channel DS lower address X 1 20 31 0 23 31 0 3 21 see SLT specification 0 x unused z for future DS Destination Select 00 CFPGA Registers global Registers analog settings etc 01 CFPGA Memory iRAM TestPattern HitRate SODIMM 10 Periph Registers Thresh Settings ADC SPI settings Statistics etc 11 Periph Memory QDR iRAM lower address 10 bit 00 Channel address 0 23 select channel 31 all channels Example long get_address long slot long base_addr return slot lt lt 19 base_add r long get_address long slot long channel long base_addr return slot lt lt 19 channel lt lt 14 base_addr 18 FLT Address Map See KA FLT MemoryMap pdf 19 Clock Distribution Synchronization Schema All the clocks in a subrack are synchronized with a global system clock of 20MHz to allow all the synchronous communications between several boards The SLT module receives the external 10MHZ clock from
22. rmine the energy distribution of each channel Histogramming Schema The energy range and resolution are adjustable using E Min and E Bin parameters to get a best fit to expected energy spectrum To limit the readout time two margins FirstEntry and LastEntry marking an area that contains data are calculated by hardware Every bin of the histogram contains a 32 bit counter Bo first Bi last Bn 1 in range BEL E Min E Max If e i is the measured energy of a trigger i then the appropriate bin is calculated as B e E Min gt gt E Bin All triggers that don t match the defined range will be absorbed into the bins Bo and Bn respectively If no triggers are observed during the measurement period HistMeasTime page not empty flags in pStatus registers remain zero The histogram building works without dead times during readout For this reason two memory fields two pages are used per channel one working area to build the actual histogram and one containing last measurements for readout Both pages are toggled after programmable time HistMeasTime Bits 29 28 bit28 histogram mode HM and bit 29 clear mode CM determinate behaviour of the histogram unit At the end of measurement period the readout page can be cleared to cleanup the old data and begin the histogram ab initio The cleanup can start either automatically by hardware clear mode CM 0 or by user CM 1 If the readout page was not cleared by user in
23. ult is unique chip grade Child ID 6 4 chip ID different identify for each device device This is a read variants of only register Chip ID 011 50 MSPS 001 40 MSPS Child ID used to differentiate graded devices Device Index 04 device_in Data Channel H1 on Data Data and Transfer dex_2 default Channel Channel Registers 0 off G1 on F1 on default default 0 off 0 off 05 Bits are set to device_in Clock Clock Channel Data Data Data determine which dex_1 Channel FCO 1 on0 Channel Channel Channel on chip device DCO 1 off default D1 on C1 on B1 on receives the next on 0 off default default default write command 0 off 0 off 0 off Bits are set to FF device_u x X X X X determine which pdate on chip device receives the next write command Synchronously transfers data from the master shift register to the slave default ADC Functions Bit 0 LSB 8 bit Chip ID Bits 7 0 AD9222 0x07 default Data Channel E 1 on default 0 off Data Channel A 1 on default 0 off SW transfer 1 on 0 off default Internal power down mode 000 chip run default 001 full power down 010 Determines various generic modes of chip operation Turns the internal duty cycle stabilizer on and off When set the test data is placed on the output pins in place of normal data i d Deserializer WEM x Cine Dco De
24. will cause an interrupt flag The hit rate measurement is disabled after reset and can be started for each channel separately by setting HitRateMeasEnable register While Veto is active all hit rate counters keep unaltered PCI start address 0x00080100 31 24 16 15 0 HRover HitRate Hz Table Hit Rate Memory Data Format PCI address 0x00000048 31 24 16 15 3 0 Fuighength T count Table HitRateMeasParameters Teoun Q 15 0 gt 1 sec 2 gt 2sec 3 gt 4sec 4 gt 8sec 5 gt 16sec 6 gt 32sec PCI address 0x00000024 31 23 0 Enable Bits 1 enabled 0 disabled Table HitRateMeasEnable 15 Veto Mode Pixel Trigger Building The veto triggering concept makes use of short pulse shape of signals In Veto Mode the first filter stage is bypassed to the second stage The filter becomes a triangle function as shown below The shaping time oa and threshold 100 N should be set adequately 80 Note that the energy en value in this mode corresponds to the absolute pulse nor amplitude with 730 offset 50 0 50 120 Pai Trigger The pair trigger based on coincidence of two channels corresponding to two ends of a fiber The coincidenc time is programmable in range of 200ns 200ns However the pair assignment is fix 24 pixel per FLT board 1 24 build 12 pairs 1 3 5 7 9 11 1345 17 19
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