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1. OFFSET 0 SLAVE ENDING ADDRESS 1 4 SLAVE ENDING ADDRESS 2 8 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER SNP WP SUP usr 2 24 PRGM DATA VE EE cu uc NINE d 14 MASTER ENDING ADDRESS 1 18 MASTER ENDING ADDRESS 2 16 MASTER ENDING ADDRESS 3 20 MASTER ENDING ADDRESS 4 24 MASTER ADDRESS TRANSLATION ADDRESS 4 MAST MAST MAST MAST 28 D16 WP MASTER AM 4 D16 WP MASTER AM 3 EN EN EN EN GCSR MAST MAST MAST MAST 1 2 GCSR GROUP SELECT BOARD SELECT E 2 di 31 30 29 25 24 23 22 21 20 19 18 17 16 WAIT ROM DMA TB SRAM 30 RMW ZERO SNP MODE SPEED 34 38 DMA CONTROLLER 3C DMA CONTROLLER 40 DMA CONTROLLER 44 DMA CONTROLLER TICK TICK CLR IRQ VMEBUS 48 p 2A n IRQ STAT INTERRUPT VMEBUS INTERRUPT VECTOR LEVEL This sheet continues on facing page gt 1 18 Computer Group Literature Center Web Site Memory Maps 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER SNP SUP USR A32 A24 Dod BLK PRGM DATA 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MASTER STARTING ADDRESS 1 MASTER STARTING A
2. 1 49 MIB ILE di c 1 50 Proper Use wi Dus 1 50 MVME1X2P4 MC680x0 Indivisible Cycles eee 1 51 Illegal Access to IP Modules from External VMEbus Masters 1 52 2 VMEchip2 Mo arpea 2 1 Perera PERRO T T 2 4 Local Bus to VM bus Interface ice cereo ert Hr e rk ER ER DE FPE 2 4 Lacal Bus to VMEbus R quester estet bnt 2 7 ve 2 9 Local Bus to VMEbus DMA Controller eese 2 10 No Address Increment DMA Transfers 2 12 DMAC VMEbus Ret Bebt t 2 13 pus Watchdog noc E 2 14 ip E ELE REDE PUER ARRA 2 14 t 2 15 pore quine n 2 15 ki lord 2 16 UE 2 17 ADOT er 2 17 LACK uan USE aae ia RTR 2 17 TIE cien A 2 17 EU MED E ernie 2 18 viii Local Bus Interrupter and Interrupt Handler cse 2 18 Global Control and Status 2 20 LCSR Programming Model opere roten hn enn erae Ae PERSE FUR 2 20 Programming the VMEbus Slave Map
3. 2 26 VMEbus Slave Ending Address Register 1 2 2 2 2 2 28 VMEbus Slave Starting Address Register 1 2 2 2 2 2 28 VMEbus Slave Ending Address Register 2 2 29 VMEbus Slave Starting Address Register 2 esse 2 29 VMEbus Slave Address Translation Address Offset Register 2 29 VMEbus Slave Address Translation Select Register 1 2 30 VMEbus Slave Address Translation Address Offset Register 2 2 31 VMEbus Slave Address Translation Select Register 2 2 31 VMEbus Slave Write Post Snoop Control Register 2 2 32 VMEbus Slave Address Modifier Select Register 2 2 33 VMEbus Slave Write Post and Snoop Control Register 1 2 35 VMEbus Slave Address Modifier Select Register 1 2 36 Programming the Local Bus to VMEbus Map Decoders 2 37 Local Bus Slave VMEbus Master Ending Address Register 1 2 40 Local Bus Slave VMEbus Master Starting Address Register 1 2 40 Local Bus Slave VMEbus Master Ending Address Register 2 2 40 Local Bus Slave VMEbus Master Starting Address Register 2 2 41 Local Bus Slave VMEbus Master Ending Address Register 3
4. ADR SIZ FFF40088 8 bits of 32 BIT 15 14 13 12 11 10 9 8 GPIOO3 GPIOO2 GPIOOI GPIOOO GPIOI3 GPIOI2 GPIOII GPIOIO OPER R W R W R W R W R R R R RESET 0 PSL OPS 0 PS 0 PS X X X X GPIOO1 Connects to pin 16 of the Remote Status and Control register GPIOO2 Connects to pin 17 of the Remote Status and Control register GPIOO3 Connects to pin 18 of the Remote Status and Control register Not used GPIOI2 Not used GPIOI3 Not used Control Register ADR SIZ FFF40088 8 bits of 32 This function is not used on MVME1X2P4 http www motorola com computer literature 2 97 VMEchip2 Miscellaneous Control Register ADR SIZ FFF4008C 8 bits of 32 BIT 7 6 5 4 3 2 1 0 DISSRAM DISMST NOELBBSY DISBSYT DISBGN OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL 0 PS 0 PS 0 PS 0 PS 0 PS DISBGN When this bit is high the VMEbus BGIN filters are disabled When this bit is low the VMEbus BGIN filters are enabled This bit should not be set ENINT When this bit is high the local bus interrupt filters are enabled When this bit is low the local bus in terrupt filters are disabled This bit should not be set DISBSYT When this bit is low the minimum VMEbus BBS Y time when the local bu
5. ICLR IEN optional ADR SIZ FFF4201C 8 bits BIT 31 30 29 28 27 26 25 24 INT IL2 IL1 ILO OPER R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the DRAM parity error detection Level 0 does not generate an interrupt Writing a logic 1 to this bit clears the DRAM parity error detection interrupt This clears the INT bit in this register This bit is always read as 0 This bit set to a 1 enables the parity error interrupt If this bit is set to a 1 and the PAREN and PARINT bits are set to 01 or 11 and a parity error occurs an interrupt is generated at the level programmed in the IL2 ILO bits The PAREN PARINT bits are located at FFF42048 at bit 26 and 25 When this bit is high a interrupt is being generated due to a DRAM parity error The interrupt is at the level programmed in IL2 ILO http www motorola com computer literature 3 21 MC2 Functions SCC Interrupt Control Register ADR SIZ FFF4201C 8 bits BIT 23 22 21 20 19 18 17 16 NAME INT IEN IL2 IL1 ILO OPER R R R R W R R W R W R W RESET 0 0 0 PL 0 PL 0 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the SCC controller Level 0 does not generate an interrupt When this bit is set high the interrupt is enabled The interrupt is disabled when
6. Register Register Register Bit Names Offset Name D7 06 05 D4 D3 D2 D1 DO DMAC for IndustryPack a request 0 This register set is referred to as DMACa the text 20 DMA_a 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 21 DMA_a INT 0 0 DINT DIEN DICLR DIL2 DILI DILO CTRL 22 DMA 0 0 0 0 0 0 0 DEN ENABLE 23 RESERVED 0 0 0 0 0 0 0 0 24 DMA a DHALT 0 DTBL ADMA WIDTHI WIDTHO 0 XXX CONTROL 1 25 DMA a INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 26 RESERVED 0 0 0 0 0 0 0 0 27 RESERVED 0 0 0 0 0 0 0 0 28 DMA_aLB LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 29 DMA_aLB LBA23 LBA22 LBA21 LBA20 LBAI9 LBAI18 LBAI7 16 ADDR 2A DMA_aLB 15 14 LBAI13 LBAI2 LBAII LBAIO LBA9 LBAS8 ADDR 2B DMA aLB LBA7 5 4 LBA2 LBAI LBAO ADDR 2C DMA aIP 0 0 0 0 0 0 0 0 ADDR 2D DMA_a IP 23 22 21 20 19 18 17 16 ADDR 2 DMA_a IP 15 14 13 12 11 10 9 ADDR 2 DMA_a IP IPA7 5 4 IPA2 IPAI IPAO ADDR 30 DMA a 0 0 0 0 0 0 0 0 BYTE CNT 31 DMA a BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 BYTE CNT 32 DMA_a 15 BCNT14 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 BCNTS8 BYTE CNT 33 DMA a BCNT7 BCNT6 BCNTS 4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 34 DMA a TBL TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADDR 35 DMA a TBL TA23 TA22 TA21 TA20 19 18 17
7. 1 39 VMEb s Memory 1 39 VMEbus Accesses to rhe Local BUS sssri serrr ros 1 40 VMEbus Short VO Memory Map erre eret onn 1 40 Solbware Support Considerations i oce bipes p tob 1 40 hia e 1 40 Cache ear MUTTER 1 41 Sources ot Local BERR 1 41 Local Bus Pi m 1 41 VMEDbiis Access TIME OUT so uus epp tet 1 42 BERE oeii 1 42 Local DRAM Parity 1 42 vii VME chipa M M M 1 42 Dus Emor Protesti EE 1 43 Description of Error Conditions the 2 1 43 MPU Parity Er c 1 43 MPU Otfftbosrd Error 1 44 MPU TEA Cause sissors 1 44 MPU Local Bus 1 44 DIAC VMEbus EMOT siccome 1 45 blu ied hi dco A 1 45 DMAC Offboard Barr P H 1 46 DMAC LTO eee 1 46 DMAC Undenbibiegd 1 47 LAN Parity 1 47 LAN Erroi 1 48 1 48 BC oL aoa uen 1 49
8. 2592 9908 6 6 http www motorola com computer literature 4 17 2 Functions Chip ID Register The read only Chip ID register is hard wired to a hexadecimal value of 23 Although writes to this register do nothing the Petra IP2 chip terminates them normally with TA ADR SIZ FFFBCOOO 8 bits BIT 7 6 3 4 3 2 1 0 CID7 CID6 CID5 CID4 CID3 CID2 CIDI CIDO OPER R R R R R R R R RESET 0 0 1 0 0 0 1 1 Chip Revision Register The read only Chip Revision register is hard wired to reflect the revision level of the Petra IP2 ASIC The current value of this register is 03 Although writes to this register do nothing the Petra IP2 chip terminates them normally with TA ADR SIZ FFFBCOOO 8 bits 4 18 Computer Group Literature Center Web Site Programming Model Vector Base Register ADR SIZ FFFBCO03 8 bits BIT 7 6 5 4 3 2 1 0 7 IV6 IV5 IVA IV3 IV2 IVO OPER R W R W R W R W R W R R R RESET 0 0 0 0 1 1 1 1 The interrupt Vector Base register is an 8 bit read write register that is used to supply the vector to the CPU during an interrupt acknowledge cycle for the four DMA controller interrupts and for the programmable clock interrupt Only the most significant five bits are used The least significant three bits encode th
9. 3 12 General Up ER dE REM La 3 12 Intercupt Vector Base apr pit Mesue Mace MR 3 13 PCR eID the Tek POTIS oup e ep ee eet bari ea e MIHI I tyr 3 15 Tick Timer 1 and 2 Compare and Counter Registers 3 15 Lob Prescaler Count iocis ERE de bg Eqs 3 17 Pissceler Clock Adjust Registef ione cucina int ceps 3 17 Tick Timer Land 2 Control uei ee nire 3 18 Tick Timer Interrupt Control Begisters uuiuu aset iet tar caves tate iaa 3 19 DRAM Parity Error Interrupt Control Register 3 21 SCC Integup E onbpol 3 22 Tack Timer d Conbol Registers crnom 3 23 DRAM and SRAM Memory Controller Registers eene 3 24 DRAM Space Base Address bte soe tee ete deste 3 24 SRAM Space Base Address Register rant Ere 3 25 DRAN Space Sure Bed SUBE o coi ae bo plici 3 25 DRAM SRAM Options Register i ccs uoce taroen taste 3 27 SRAM 3 28 LANC Error status BEIGE 3 29 2596C A LANC Interrupt Control 3 30 LANC Bus Error Interrupt Control 3 31 Por 3 32 General Purpose Inputs RgISter iuueni 3 33 MYMEIX2PA
10. FFF584FC 111110 IP_b or ab FFF584FD 20111111 IP b FFF584FE 111110 IP_a FFF584FF 111111 IP a 4 54 Computer Group Literature Center Web Site Local Bus to IndustryPack Addressing IP a ID Space This example is for a ID space The relationship of the IndustryPack address to the local bus address is IPA lt 5 0 gt LBA lt 5 0 gt Note that lt 22 6 gt do not pertain to ID space LBA 58080 58081 58082 58083 FFF580BC FFF580BD FFF580BE FFF580BF IPA lt 5 0 gt 000000 000001 000010 000011 111100 111101 111110 111111 Comments http www motorola com computer literature 4 55 2 Functions to Local Bus Data Routing This section shows data routing from an IP to the local bus Memory Space Accesses The following table shows the data routing when accessing IP memory space IPWIDTH LBSIZE LBA IPA LD lt 31 24 gt LD lt 23 16 gt LD lt 15 8 gt LD lt 7 0 gt 0 1 IPXD lt 7 0 gt 1 3 IPXD lt 7 0 gt BYTE 2 5 IPXD lt 7 0 gt 8 Bits 3 7 IPXD lt 7 0 gt 0 1 3 IPXD lt 7 0 gt IPXD lt 7 0 gt WORD 2 5 7 IPXD lt 7 0 gt IPXD lt 7 0 gt LWORD 0 2 IPXD lt 7 0 gt IPXD lt 7 0 gt IPXD lt 7 0 gt IPXD lt 7 0 gt 0 0 IPXD lt 15 8 gt
11. ADR SIZ FFF40078 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SYSFLEVEL WPE LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the SYSFAIL interrupt and the master write post bus error interrupt WPE LEVEL These bits define the level of the master write post bus error interrupt SYSF LEVEL These bits define the level of the SYSFAIL interrupt Interrupt Level Register 1 bits 8 15 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME PE LEVEL IRQIE LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the VMEbus IRQ1 edge sensitive interrupt and the level of the external parity error interrupt IRQIE LEVEL PE LEVEL These bits define the level of the VMEbus IRQ1 edge sensitive interrupt Used if the ECC memory model is enabled Not used in the parity model Refer to Chapter 5 MCECC Functions for interrupt setup details Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 1 bits 0 7 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 TICK2 LEVEL TICK1 LEVEL OPER R W R W RESET 0 PSL PSL This register is used to define the level of the tick timer 1 interrupt and the tick timer 2 interrupt TICK1 LEVEL These bits define the level of the tick timer
12. ADRISIZ FFF42028 8 bits 15 14 13 12 11 10 9 8 NAME PLTY E L INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level for the 82596 LANC Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the INT status bit This bit has no function in level sensitive mode This bit is always read as 0 Interrupt Enable When this bit is set high the interrupt is enabled The interrupt is disabled when this bit is low INT This status bit reflects the state of the INT pin from the LANC qualified by the bit When this bit is high a LANC INT interrupt is being generated at the level programmed in IL2 ILO E L Edge or Level When this bit is high the interrupt is edge sensitive The interrupt is level sensitive when this bit is low PLTY Polarity When this bit is low interrupt is activated by a rising edge high level ofthe LANC INT pin When this bit is high interrupt is activated by a falling edge low level of the LANC INT pin Note that if this bit is changed while Computer Group Literature Center Web Site Programming Model the E L bit is set or is being set a LANC interrupt may be generated This can be avoided by setting the ICLR bit during write cycles that change the E L bit LANC Bus Error Inter
13. ab trib babeat 3 34 SCSI Iuteiupt Control ica secs Mp ERR 3 35 Tick Timer and 4 Compare and Counter Registers eerte terne 3 36 DO Qr d irj d VEU 3 37 EPROM Access Time Control oue 3 38 Flash Access Tune Control Register uus ri seii paso Mat ES Rte HRS ERE 3 39 ABORT Switch Interrupt Control Register 1 tetti 3 40 RESET Switch Control Reg stem ie RUE ERE ARD 3 41 Watchdog Timer Control pti eno rnein 3 42 Access and Watchdog Time Base Select Register sss 3 43 DRAM Control Register uoces 3 44 MPU Status lui TT 3 46 32 bit Prescaler Count 3 47 CHAPTER 4 IP2 Functions sis mann 4 1 Summary ol Major 4 1 Bug FIRB 4 2 Command Clin Table Update ere e n e i 4 2 DMA Eid Js secare bai tid A GN aia 4 2 IP Bus Reset 4 3 lura iHi einst Pet 4 3 TICS OTN as aae denne canta eH X Bree lap Eus DNE MAD 4 3 4 4 Local Bus to IndustryPack DMA 4 4 Clocking Environments qud Performante
14. e 4 6 ERRi 4 8 Eror REON N 4 8 Eror Reporting Local Bus Slave 4 8 Error Reporting Local Bus Master ee te eerie tte ts 4 8 Industry Pack Eror esas cots suns epist Rupee tepore Raus 4 9 lucu NT t 4 0 there Meniory 4 10 i dirum 4 11 Chp O REINE EU 4 18 Chp Revision E 4 18 Vector Base RECN G E EA 4 19 Memory Base Address Registers IP b IP c 4 20 a or Double Size ab Memory Base Address Registers 4 20 IP Memory Base Address Registers eae en peto Ie qe edes Hes 4 21 c or Double Size cd Memory Base Address Registers 4 21 IP d Memory Base Address Registers ee ite re gea tede oec aad 4 21 Memory Size Registers IP a IP b IP e IP duse sapete 4 22 IRQO IRQI Interrupt Control Registers a IP b IP c IP d 4 23 General Control Registers IP s UP e meint 4 24 irs UT 4 28 xiii DMA Arbitration Control Register i 4 29 RESET qe 4 30 Programming the DMA Controllers 4 31 DMA Enable PUncton 4 34 Control and Status Register Set Definition
15. 1 2 5 4 3 2 1 0 NAME dmaeil chain_dmaeil OPER R W R W RESET 0 PLS 0 PLS 0 PLS V PLS V PLS VPLS V PLS V PLS Address F FFBCOAO selects Alternate DMA Control register Address F FFBCOA selects Alternate DMA Control register Address F FFBCOA2 selects Alternate DMA Control register b Address F FFBCOA3 selects Alternate DMA Control register chain dmaeil Refer to the description for dmaeil control dmaeil The dmaeil and chain dmaeil bits are part of an IP2 bug fix which allows flushing of the FIFOs when the dmaend signal is detected on IP read operations This function enables the early termination of DMA if the data flow is to the host MVME1X2P4 board When the dmaend signal is driven by the IP device the DMA service is terminated and the data path is flushed To enable this function the dmaeil bit must be set in the Alternate DMA Control Register 2 and the dmaei bit must be set in the DMA Control Register 2 If the chain dmaeil bit is set the dmaeil bit is updated by the Control Word during the chained operation The chain dmaeil bit is not updated by the DMA chained operation If only the dmaeil bit is set in DMA Control Register 2 the DMA channel will behave in the manner of the IP2 ASIC That is the flawed operation is still available if a requirement for it exists 4 48 Computer Group Literature Center Web S
16. ADR SIZ FFF42044 8 bits BIT 23 22 21 20 19 18 17 16 NAME WDCS WDCC WDTO WDBFE WDRSE WDEN OPER R R W R R W R W RESET 0 OP OP OP 0 PL 0 0 PL 0 PL WDEN When this bit is high the watchdog timer is enabled When this bit is low the watchdog timer is not enabled WDRSE When this bit is high and a watchdog time out occurs a LRESET is generated When this bit is low a watchdog time out does not cause a reset WDBFE When this bit is high and the watchdog timer has timed out the MC2 chip asserts the BRDFAIL signal pin When this bit is low the watchdog timer does not contribute to the BRDFAIL signal on the MC2 chip WDTO When this status bit is high a watchdog time out has occurred When this status bit is low a watchdog time out has not occurred This bit is cleared by writing a 1 to the WDCS bit in this register 3 42 Computer Group Literature Center Web Site Programming Model Access and Watchdog Time Base Select Register WDCC WDCS When this bit is set high the watchdog counter is reset The counter must be reset within the time out period or a watchdog time out occurs When this bit is set high the watchdog time out status bit WDTO bit in this register is cleared The watchdog timer control logic in the MC2 sector is used if the board is built in a VMEbus interface configuration This function is duplicated at the same bit locations in the VMEchip2 at location
17. 2 107 Generi Purpose MO inte M MEN RM 2 108 General Purpose iaceo Hd Seq 2 108 Generil Purpose pos MIRI ME MEA MI MM 2 108 CHAPTER3 MC2 Functions 3 1 Malor 3 1 E 3 2 Pera ME 2 hip Bob S e DIA E d UO QE EEG qtue td 3 2 Flash and BPROM Interlace 56 asini pie vised 3 2 BBEANI n E 3 3 no MAP T Np T 3 3 MPU Port and MPU Channel Attention ee cec treten ante rero n 3 3 xi MC680x0 Bus Master Support for 82596 3 4 LANG ENUF MEM 3 4 LANC Interntplt 3 5 33C210 5C 5I Controller Intetfage 3 5 SRAM Memory Contollat 3 5 SDRAM Memory 3 6 283230 SCC Lar P 3 7 Tiek Wh m 3 8 Watchdog TIMET e 3 9 Local 3 9 Petta MC2 Registers Memory teens 3 10 Mode M 3 11 MCA Sector ID Registaf crecer tierra E eren rra Ip 3 12 Revision
18. DATA 1 1 1 1 1 1 1 1 1 1 1 15 14 13 12 11 10 9 8 F 6 5 4 3 2 1 0 MASTER STARTING ADDRESS 1 MASTER STARTING ADDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST MAST 016 WP MASTER AM 2 016 WP MASTER AM 1 EN EN EN EN 102 102 102 102 101 101 101 101 ROM ROM BANK ROM BANK A EN WP S U P D EN D16 WP S U SIZE SPEED SPEED EN EN EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MST MST MASTER DMA DMA DMA DMA DM DMA ROBN DHB DWB FAIR VMEBUS HALT EN TBL FAIR RELM VMEBUS DMA DMA LB DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA TBL SNP MODE INC INC WRT 016 064 BLK AM AM AM AM AM AM INT VME LB BLK 5 4 3 2 1 0 LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER DMA TABLE MPU MPU MPU MPU MPU DMA DMA DMA DMA DMA DMA CLR LBE LPE LOB LTO LBE LPE LOB LTO TBL VME DONE INTERRUPT COUNT STAT ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR 1360 9403 4 This sheet begins on facing page http www motorola com computer literature 2 23 VMEchip2 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 2 of 2 VMEchip2 LCSR Base Address FFF40000 OFFSET 31 30 29 28 27 26 25 24 28 2
19. This register is a general purpose I O control register Bits 16 19 control the direction of the four General Purpose pins GPIOO 3 GPOENO GPOEN2 GPOEN3 ABRTL ACFL SYSFL MIEN When this bit is low the GPIOO pin is an input When this bit is high the GPIOO pin is an output When this bit is low GPIO1 pin is an input When this bit is high the GPIOI pin is an output When this bit is low the GPIO2 pin is an input When this bit is high the GPIO2 pin is an output When this bit is low the pin is an input When this bit is high the GPIO3 pin is an output This bit indicates the status of the ABORT switch When this bit is high the ABORT switch is depressed When this bit is low the ABORT switch is not depressed This bit indicates the status of the ACFAIL signal line on the VMEbus When this bit is high the ACFAIL signal line is active When this bit is low the ACFAIL signal line is not active This bit indicates the status of the SYSFAIL signal line on the VMEbus When this bit is high the SYSFAIL signal line is active When this bit is low the SYSFAIL signal line is not active When this bit is low all interrupts controlled by the VMEchip2 are masked When this bit is high all interrupts controlled by the VMEchip2 are not masked 2 96 Computer Group Literature Center Web Site LCSR Programming Model Control Register 2
20. 2 41 Local Bus Slave VMEbus Master Starting Address Register 3 2 41 Local Bus Slave VMEbus Master Ending Address Register 4 2 42 Local Bus Slave VMEbus Master Starting Address Register 4 2 42 Local Bus Slave VMEbus Master Address Translation Address Register 4 eet 2 42 Local Bus Slave VMEbus Master Address Translation Select Register 2 43 Local Bus Slave VMEbus Master Attribute Register 4 2 43 Local Bus Slave VMEbus Master Attribute Register 3 2 44 Local Bus Slave VMEbus Master Attribute Register 2 2 45 Local Bus Slave VMEbus Master Attribute Register 1 2 46 VMEbus Slave GCSR Group Address Register 2 47 VMEbus Slave GCSR Board Address Register 2 48 Local Bus to VMEbus Enable Control Register sess 2 49 Local Bus to VMEBbus Control Register eec to eres 2 50 ROM Control ip indiana 2 51 Programming the VMEchip2 DMA Controller eret eren 2 51 PMAC 2 53 EPROM Decoder SRAM and DMA Control Register 2 53 Local Bus to VMEbus Requester Control Register
21. This bit defines the direction in which DMAC transfers data When this bit is high data is transferred to the IndustryPack When it is low data is transferred from the IndustryPack ENTO ENTO set to a 1 will enable the watchdog time out function for DMA cycles on the IP bus The time out period is fixed at approximately 1 msec If a time out does occur the IP bus cycle is terminated and the IPTO bit is set in the DMA Status register Note that the IndustryPack interface in the Petra IP2 ASIC will wait indefinitely if the ENTO bit is cleared and DMA cycle on the IP bus is not acknowledged The IP2 sector must be reset to clear this condition It is recommended that ENTO be set to a 1 DMAEO When DMAEO is set DMA drives DMAEND and asserts it during the DMA IP cycle in which the byte count expires When DMAEO is cleared DMA s DMAEND driver is disabled 4 40 Computer Group Literature Center Web Site Programming Model DMAEI When DMAEI is set DMA terminates if the assertion of DMAEND is detected and the sDMA function is enabled That is the ADMA control bit in the DMA Control Register 1 must be setto a 0 If the assertion of DMAEND is not detected DMA will terminate according to the byte count value and the command chaining mode Note that in previous implementations in cases where DMA was halted due to the DMAEI function the DMA operation stopped immediately and did not flush the inbound data paths In such i
22. lt 5 7031405 7051405 viva viva viva gt H31S VW SNEAWA S31A8 t A8 AHIN3 91 lt 5 7051409 lt viva 7031405 1OH LNOO 5 7051409 4 1 TOYLNOO gt viva viva 0314 SN 1 201 OL SNAIWA YALSVW sna 1 201 Ss3uaav Ssauaav 7031409 7031409 15 518 WOOT 7OHINOO 7031405 5 5 55 7051405 7031405 7031405 7TOHLNOO S31A8 t A8 AHLN3 91 viva viva SNEAWA Odi4 5 OL SNE 1v201 7031405 ToulNOO ssayqqv 5 Ss3uadav 70519405 7051405 7031405 1 2 44 gt S31A8 p A8 AHIN3 t 3315 SNESWA 0314 TOHLNOD ssayqqv TOHLNOD TOHLNOD viva viva SN W907 ssauaav TOHLNOD viva sng voo1 Figure 2 1 VMEchip2 Block Diagram 2 5 iterature www motorola com computer l http VMEchip2 Using the four programmable map decoders separate VMEbus maps can be created each with its own attributes For ex
23. 2 54 DNIAC Control Register I bite 027 2 55 DMNIAC Control Register 2 DIS 8 13 2 57 DNIAC Control Register 2 bits OeT isole tera er rere eR 2 58 DMAC Local Bus Address Counter isse pietre Mr EA te ab Ho Ride EAE 2 59 DMAC VMEbus Address Counter etre tin 2 60 ll dl rie ng T 2 60 Table Address Countat CERE RUN RUE 2 60 VMEbus Intertupter Control Re 18068 2 61 VMEbus Interrupter Vector Rep ister 2 62 MPU Status and DMA Interrupt Count Register 2 2 2 62 DIAC Status 2 63 Programming the Tick Watchdog 2220 2 64 VMEbus Arbiter Time Out Control Register 2 2 2 24 2 2 64 DMAC Ton Toff Timers and VMEbus Global Time out Control Register 2 65 VME Access Local Bus and Watchdog Time out Control Register 2 66 Pigseslor Control RG Geter Coat ata 2 67 Tick Timer Compare 2 68 TEE Tiner aet 2 68 Tick 2 Compie 2 69 Tick Tiner 2 69 Contol uiris e 2 70 Watchdog Timer Control USE uui teeth ti estia ingens
24. 4 44 Computer Group Literature Center Web Site Programming Model Programmable Clock General Control Register ADR SIZ FFFBC081 8 bits BIT 7 6 2 4 3 2 1 0 PLTY PLS 0 EN CLR PS2 PS1 PSO OPER R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR PS2 0 These three bits select the frequency of the pre scale logic output The MC680x0 bus clock is used as the input to the pre scale logic is either 25MHz or 32MHz BCK frequency can be determined by examining the Version register in the MC2 sector PS2 PS0 Pre scaler Output Frequency PLS 0 PLS 1 0 BCK 2 No Output 1 BCK 4 BCK 2 2 BCK 8 BCK 4 3 BCK 16 BCK 8 4 BCK 32 BCK 16 5 BCK 64 BCK 32 6 BCK 128 BCK 64 7 BCK 256 BCK 128 CLR Setting this bit forces the programmable clock s internal registers except for the interrupt and general control registers to zero These registers include the prescaler and timer counters Note that these registers will remain cleared until the CLR bit is set to a 0 EN When the EN bit is set the programmable clock is enabled When it is cleared the programmable clock is suspended EN performs its function by http www motorola com computer literature 4 45 IP2 Functions enabling disabling the prescaler s counter Note that clearing EN does not clear any of the programmable clock s registers PLS When PLS is
25. ADR SIZ FFF400368 32 bits BIT 31 2 0 DMAC Local Bus Address Counter OPER R W RESET 0 PS In direct mode this counter is programmed with the starting address of the data in local bus memory http www motorola com computer literature 2 59 VMEchip2 DMAC VMEbus Address Counter ADR SIZ FFF4003C 32 bits BIT 31 0 NAME DMAC VMEbus Address Counter OPER R W RESET OPS In direct mode this counter is programmed with the starting address of the data in VMEbus memory DMAC Byte Counter ADR SIZ FFF40040 32 bits BIT 31 0 DMAC Byte Counter OPER R W RESET 0 PS In direct mode this counter is programmed with the number of bytes of data to be transferred Table Address Counter ADR SIZ FFF40044 32 bits BIT 31 ur 0 NAME Table Address Counter OPER R W RESET OPS In command chaining mode this counter should be loaded by the processor with the starting address of the list of commands This register gets reloaded by the DMAC with the starting address of the current command The last command in a list should have bits 0 and 1 set in the next command pointer 2 60 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Interrupter Control Register ADR SIZ FFF40048 8 bits 7 used of 32 BIT 3 30 29 28 27 26 25 24 18015 IRQC IRQS IRQL
26. Support for byte two byte four byte and cache line read or write transfers Programmable base address for DRAM Built in refresh timer and refresh controller Programmable period automatic scrub operation Error Handling ECC Single Bit Error Detect and Correct Software enabled Interrupt on Single Bit Error Double Bit Error Detect Software programmable Bus Error and or Interrupt on double bit error 5 2 Computer Group Literature Center Web Site Functional Description Functional Description The following sections provide an overview of the functions provided by the Petra MCECC sector For a detailed programming model for the Petra MCECC control and status registers refer to the Programming Model section General Description The Petra MCECC sector is a single chip solution for memory control functions The memory architecture is a single bank of SDRAM 32 bits wide plus seven check bits The MCECC sector provides all the functions required to implement a memory system These include programmable map decoding memory control refresh and a memory scrubber The scrubber when enabled periodically scans memory for errors If the scrubber finds a single bit error in the memory array it corrects the error This prevents soft single bit errors from becoming double bit errors Performance The Petra MCECC sector maintains tags for each internal bank of SDRAM Each bank may be in an active or
27. kieva il tevet 8C This sheet continues on facing page gt 2 24 Computer Group Literature Center Web Site LCSR Programming Model EGE eee D VME LOCAL W ACCESS BUS TIME OUT PRESCALER TIMER TIMER SELECT CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW eus LEE E OVERFLOW Ae COUNTER 2 A COUNTER 1 1 1 SCALER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sw swe sws sw4 sws sw2 Swi swo VME VME VME VME VME RQ Ra RQ RQ IRQ7 IRQS 1804 IRQ2 IRQI EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN IRQ IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET SET set set SET SET SET IRQ IRQ IRQ 15 14 13 12 11 10 9 8 CLR CLR CLR IRQ IRQ IRQ 15 14 13 12 11 10 9 8 IRQ1E TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SIG 1 SIG 0 LM 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL sws swe swi swo IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IRQ 4 VMEB IRQ 3 VME IRQ 2 VME IRQ 1 IRQ LEVEL IRQ LEVEL IRQ
28. 5 23 5 22 BASE21 5 20 8 c BASEI7 5 16 BASE LOWER OA IPdMEM d 5 d BASE30 d BASE29 d BASE28 d BASE27 d BASE26 d BASE25 d BASE24 BASE UPPER OB dMEM BASE23 d BASE22 d BASE21 BASE20 d 5 19 BASE18 5 17 d BASE16 BASE LOWER IP MEM a_SIZE23 a_SIZE22 a_SIZE21 a SIZE20 a SIZEI9 SIZE18 a_SIZE17 a SIZEI6 SIZE OD IP b MEM b SIZE23 b SIZE22 b SIZE21 b SIZE20 b 517519 b 512818 b SIZEI7 b_SIZE16 SIZE OE IP c MEM c SIZE23 c SIZE22 c SIZE21 c SIZE20 SIZEI9 c SIZEI8 c SIZEI7 c SIZEI6 SIZE OF IP d MEM d SIZE23 d SIZE22 d_SIZE21 d SIZE20 a sizE19 512818 d SIZEI7 d SIZE16 SIZE 10 a INTO a0 PLTY a0 E L a0 INT a0 IEN a0 ICLR a0 IL2 a0 ILI a0 ILO CONTROL 11 IP a INTI al PLTY al E L al INT al IEN al ICLR al IL2 al ILI al ILO CONTROL 12 IP b INTO bO_PLTY 0 bO INT 0 bO_IL2 bO ILI bO ILO CONTROL 13 IP bINTI bl PLTY bl E L bl INT bl IEN bl ICLR bl IL2 bl ILI bl ILO CONTROL 14 IP c INTO c0 PLTY c0 E L INT c0 c0 ICLR cO IL2 cO ILI cO ILO CONTROL 15 IP c INTI cl PLTY cl E L cl INT cl IEN cl ICLR cl IL2 cl ILI cl ILO CONTROL 16 IP d INTO 40 PLTY 40 E L dO INT dO dO dO IL2 dO ILI dO ILO CONTROL 17 dINTI dl PLTY dl E L dl INT dl IEN dl ICLR dl IL2 dl ILI dl ILO CONTROL 18 aGENERAL ERR 0 RTI a_WI
29. ADR SIZ 1st FFF43048 2nd FFF431468 8 bits BIT 31 30 29 28 27 26 25 24 8577 5 6 STS ST4 ST3 ST2 STI STO OPER R W R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS OPLS Scrub Address Counter Bits 26 24 This read write register is the Scrub Address counter Each time the scrubber performs a scrub memory cycle the Scrub Address counter increments For an entire scrub the Scrub Address counter starts at 0 and increments until it reaches the DRAM size that is indicated by the MEMSIZ pins Writes to this address update the Scrub Address counter reads to this address yield the value in the counter The ability to read and write this counter is provided for test purposes Note that if scrubbing is in process the Scrub Time On Time Off register should be set for the minimum time on and the maximum time off during any writes to this register This register reflects the current value in the Scrub Address counter bits 26 24 ADR SIZ 1st FFF4304C 2nd FFF4314C 8 bits NAME 0 0 0 0 0 SAC26 SAC25 SAC24 OPER R wW R W R W R W R W R W R W R W RESET X X X X X OPLS OPLS OPLS http www motorola com computer literature 5 25 MCECC Functions Scrub Address Counter Bits 23 16 This register reflects the current value in the Scrub Address counter bits 23 16 ADR SIZ 1st FFF43050 2nd FFF43150 8 bits BIT
30. 0 0 0 0 0 PRIO OPER R R R W R W R W RESET OR OR OR OR OR OR OR OR ROTAT ROTAT set to a 0 enables a rotating arbitration method where each DMAC has equal access to the MC680x0 local bus If ROTAT is set to a 1 the priority is fixed according to the following table PRI PRIO Fixed priority assignment is defined by the following tables Priority with one DMA channel at IP sockets b c amp d PRIO Highest Next Highest Next Lowest Lowest 00 DMA_a DMA_b DMA c DMA d 01 DMA b DMA c DMA d DMA a 10 DMA c DMA d DMA a DMA b 11 DMA_d DMA_a DMA_b DMA c Priority with two DMA channel at IP sockets a and c 0 Highest Next Highest Next Lowest Lowest 00 DMA a chan 0 DMA achan 1 DMA c chan 0 DMA cchan 1 01 DMA achan 1 DMA c chan 0 DMA cchan 1 DMA a chan 0 10 DMA c chan 0 DMA cchan 1 DMA a chan 0 DMA achan 1 _ chan 1 DMA a chan 0 DMA achan 1 DMA c chan 0 http www motorola com computer literature 2 Functions RESET Register ADR SIZ FFFBCO1F 8 bits BIT 7 6 4 3 2 1 0 0 0 0 0 0 0 IPLRES RES OPER R R R R R R R RESET OR OR OR OR OR OR OR OR RES Setting RES to a asserts the IP2 sector IPRESET signal IPRESET is intended to be connected to the Reset signal on all four IndustryPacks When software sets the RES bit IPRESET stays asserted until software clears RES RES When RES is initiali
31. 16 ADDR 36 DMA_a TBL 15 14 13 12 11 10 9 8 ADDR 37 DMA a TBL 7 6 5 4 TA2 TAI TAO ADDR 2592 9908 2 6 1 26 Computer Group Literature Center Web Site Memory Maps Table 1 8 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address FFFBCOO0 Register Register Register Bit Names Offset Name D7 D6 D5 04 D3 D2 D1 DO DMAC for IndustryPack b request 0 or for IndustryPack a request 1 This register set is referred to as DMACb in the text 38 DMA_b 0 DLBE 0 CHANI TBL IPTO DONE STATUS 39 DMA_b INT 0 0 DINT DIEN DICLR DIL2 DILI DILO CTRL 3A DMA 0 0 0 0 0 0 0 ENABLE 3B RESERVED 0 0 0 0 0 0 0 0 3C DMA_b DHALT 0 DTBL ADMA WIDTHI WIDTHO A CHI XXX CONTROL 1 3D DMA b INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 3E RESERVED 0 0 0 0 0 0 0 0 3F RESERVED 0 0 0 0 0 0 0 0 540 DMA_bLB LBA3I LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 41 DMA_bLB LBA23 LBA22 LBA21 LBA20 19 18 LBAI7 16 ADDR 42 DMA_bLB 15 14 LBAI2 LBAII LBAIO LBA9 LBA8 amp ADDR 43 DMA_bLB LBA7 5 LBA4 LBA3 LBA2 LBAI LBAO ADDR 44 DMA_b IP 0 0 0 0 0 0 0 0 ADDR 45 DMA_b IP 23 22 21 20 19 18 17 16 ADDR 46 DMA_b IP 15 14 13 12
32. 18 17 16 ADDR 7E DMA d TBL 15 14 13 12 11 10 9 8 ADDR 7F DMA d TBL TA7 TAG TAS TA4 TA3 TA2 TAL TAO ADDR 80 PACER INT 0 INT IL2 ILI ILO CONTROL 81 PACER GEN PLTY PLS 0 EN CLR PS2 PSI PSO CONTROL 82 PACER 15 T14 T13 T12 11 10 T9 T8 TIMER 83 PACER 7 6 5 4 TA2 TIMER 2592 9908 5 6 http www motorola com computer literature 1 29 Board Description and Memory Maps Table 1 8 Petra IP2 Memory Map Control Status Registers Cont d 2 Sector Base Address 000 Register Register Register Bit Names Offset Name D7 D6 D5 D4 D3 D2 D1 DO 90 ALTERNATE 0 0 0 0 0 0 0 0 91 icc rai A_BCNT23 A_BCNT22 A_BCNT21 A_BCNT20 A BCNTI9 A BCNTIS BCNTI7 A_BCNTI6 92 A BCNTIS A 4 BCNTI3 BCNTI2 A_BCNTI A_BCNTI10 A BCNT9 A_BCNT8 893 A_BCNT7 A_BCNT6 BCNTS A_BCNT4 BCNT3 A BCNT2 A BCNTI A_BCNTO 94 ALTERNATE 0 0 0 0 0 0 0 0 DMA_b BYTE 95 COUNT A_BCNT23 A_BCNT22 A BCNT21 A BCNT20 BCNTI9 A BCNTIS BCNTI7 A_BCNTI6 896 A BCNTIS 4 BCNTI3 BCNTI2 lt A 0 BCNT9 _ 8 897 A_BCNT7 A_BCNT6 BCNTS A_BCNT4 BCNT3 A BCNT2 A BCNTI A_B
33. Addressing capabilities A16 A24 A32 Data transfer capabilities D16 D32 D16 BLT D32 BLT D64 BLT BLT block transfer Using the DMA AM Address Modifier control register the address modifier code that the VMEbus DMA controller places on the VMEbus can be programmed under software control In addition the DMAC can be programmed to execute block transfer cycles over the VMEbus Complying with the VMEbus specification the DMAC automatically terminates block transfer cycles whenever a 256 byte D32 BLT or 2 KB D64 BLT boundary is crossed It does so by momentarily releasing AS Address Strobe and then in accordance with its bus release bus request configuration initiating a new block transfer cycle To optimize VMEbus use the DMAC automatically adjusts the size of individual data transfers until 64 bit transfers D64 BLT mode 32 bit transfers D32 mode or 16 bit transfers D16 mode can be executed Based on the address of the first byte the DMAC transfers single bytes double bytes or a mixture of both and then continues to execute transfer cycles based on the programmed data width Based on the address of the last byte the DMAC transfers single bytes double bytes or a mixture of both to end the transfer To optimize local bus use when the VMEbus is operating in D16 mode the data FIFO converts D16 VMEbus transfers to D32 local bus transfers The FIFO also aligns data if the source and destination addresses are n
34. FFF4004C It is permissible to enable the watchdog timer in both the VMEchip2 and the MC2 sector ADR SIZ FFF42044 8 bits BIT 15 14 13 12 11 10 NAME LBTO WDTO OPER R W R W R W RESET 0 OPL WDTO These bits define the watchdog time out period Time out mew Time out 0 512 us 8 128 ms 1 1 ms 9 256 ms 2 2 ms 10 512 ms 3 4 ms 11 ls 4 8 ms 12 4s 5 6 ms 13 16s 6 32 ms 14 32s 7 64 ms 15 64s http www motorola com computer literature 3 43 MC2 Functions LBTO These bits define the local bus time out value The timer begins timing when TS is asserted on the local bus If TA or TEA is not asserted before the timer times out a TEA signal is sent to the local bus Note that Version register bit V1 must be set to a 1 to enable the access timer in the MC2 sector i e it must be a No VMEbus Interface option 0 8 us 1 64 us 2 256 Us 3 The timer is disabled DRAM Control Register This register enables access to the SDRAM array in the MC2 memory model Note that the SDRAM array is capable of single bit error correction and multi bit error detection The error correction mode is enabled in the MC2 model by the added definitions of the RAMEN PAREN and PARINT control bits ADR SIZ FFF42048 8 bits BIT 31 30 29 28 27 26 25 24 NAME WWP PARINT PAREN
35. This register reflects the current value in the scrub prescaler bits 7 0 ADR SIZ BIT 1st FFF43040 2nd FFF43140 8 bits 31 30 29 28 27 26 25 24 NAME SPS7 SPS6 SPS5 5 54 5 53 5 52 SPSI SPSO OPER R W R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS 5 OPLS OPLS 5 Scrub Timer Counter Bits 15 8 This read write register is the Scrub Timer counter If scrubbing is enabled and the Scrub Period register is non zero the Scrub Timer counter increments approximately once every two seconds until it matches the value programmed into the Scrub Period register at which time it clears and resumes incrementing Writes to this address update the Scrub Timer counter and reads to this address yield the counter s value The ability to read and write this register is provided for test purposes Programming this counter is not recommended This register reflects the current value in the Scrub Timer counter bits 15 8 ADR SIZ 1st FFF43044 2nd FFF43144 8 bits BIT 31 30 29 28 27 26 25 24 5715 ST14 ST13 ST12 5 10 579 5 8 OPER R W R W R W R W R W R W R W RESET OPLS 8 OPLS OPLS OPLS OPLS OPLS 0PLS Computer Group Literature Center Web Site Programming Model Scrub Timer Counter Bits 7 0 This register reflects the current value in the Scrub Timer counter bits 7 0
36. boards in the system which are not participating in the broadcast interrupt function should not drive or respond to any signals on the IRQ signal line There are two ways to broadcast an IRQI interrupt The VMEbus interrupter in the VMEchip2 may be programmed to generate a level 1 interrupt This interrupt must be cleared using the interrupt clear bit in the control register because the interrupt is never acknowledged on the VMEbus The VMEchip2 allows the output of one of the tick timers to be connected to the IRQI interrupt signal line on the VMEbus When this function is enabled a pulse appears on the IRQI signal line at the programmed interrupt rate of the tick timer 2 16 Computer Group Literature Center Web Site Functional Blocks VMEbus System Controller With the exception of the optional SERCLK driver and the Power Monitor the chip includes all the functions that a VMEbus system controller must provide The system controller is enabled disabled with the aid of an external jumper J1 the only jumper required in a VMEchip2 based VMEbus interface Arbiter The arbitration algorithm used by the chip arbiter is selected by software All three arbitration modes defined in the VMEbus Specification are supported Priority PRI Round Robin Select RRS as well as Single SGL When operating in the PRI mode the arbiter asserts the BCLR line whenever it detects a request for the bus whose level is higher that the one b
37. 2 Functions Introduction The IndustryPack Interface Controller IP2 chip ASIC is one of three ASICs used on earlier MVME162 172 models the MC2 chip the IP2 chip and the MCECC chip whose functions are now incorporated into a single ASIC the Petra chip on the MVMEIX2PA For ease of use in conjunction with programming models and documentation developed for earlier boards however the structure of this manual preserves the functional distinctions that formerly characterized those three ASICs This chapter describes the IP2 functionality of the Petra chip The Petra IP2 chip interfaces up to four IndustryPack modules IPs to the MC680x0 processor Summary of Major Features IP2 functions now implemented on the Petra chip include Table 4 1 IP2 Functions on the Petra ASIC Function IndustryPack I O Support Features logic required to interface the MC680x0 bus to four IndustryPacks Support for IndustryPack I O Memory Interrupt Acknowledge and ID interface cycles Support for 8 bit 16 bit and 32 bit double size IndustryPack cycles Programmable clock for strobe generation to the IndustryPack interface Fixed base addressing for IndustryPack I O and ID spaces 4 1 IP2 Functions Table 4 1 IP2 Functions on the Petra ASIC Continued Function Features Memory Control Programmable base address size for IndustryPack memory space Support for four DMA channels
38. 21 20 19 18 17 16 ADDR 76 DMA_d IP 15 14 13 12 11 10 9 ADDR 77 DMA_d IP IPA7 5 4 IPA2 IPAI IPAO ADDR 78 DMA d 0 0 0 0 0 0 0 0 79 DMA_d BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 BYTE CNT 7 DMA_d 15 BCNT14 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 BCNTS8 BYTE CNT 7B DMA d BCNT7 BCNT6 BCNTS BCNT4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 7C d TBL TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADDR 7D DMA d TBL TA23 TA22 TA21 TA20 19 18 17 16 ADDR 7 DMA d TBL 15 14 13 12 11 10 9 8 ADDR DMA d TBL TA7 TA6 TAS 4 TA2 TAI TAO ADDR 80 PACER INT 0 IL2 ILI ILO CONTROL 81 PACER GEN PLTY PLS 0 EN CLR PS2 PSI PSO CONTROL 82 PACER 1 105 T14 T13 T12 11 10 T9 T8 TIMER 83 PACER 7 6 5 4 TA2 TI TO TIMER 2592 9908 5 6 4 16 Computer Group Literature Center Web Site Programming Model Table 4 4 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address FFFBCOO0 Register Register Register Bit Names Offset Name D7 06 05 04 D3 D2 D1 590 ALTERNATE 0 0 0 0 0 0 0 0 91 bic E A BCNT23 A BCNT22 BCNT21 BCNT20 A BCNTI
39. 4 34 Computer Group Literature Center Web Site Programming Model Status Register ADR SIZ BIT FFFBC020 38 50 68 8 bits each 5 4 3 2 1 0 IPENDI IPEND CHANI TBL IPTO DONE OPER R W R R R R R RESET OR OR OR OR OR TBL CHANI IPEND This bit is set when DMAC has finished executing commands and there were no errors or DMAC has finished executing commands because the DHALT bit was set This bit is cleared when DMAC is enabled A DMAC interrupt will be generated if interrupts are enabled When this bit is set a DMAC access to an IndustryPack timed out This bit is cleared when DMA is enabled A DMAC interrupt will be generated if interrupts are enabled When this bit is set DMAC received an error on the local bus while it was reading commands from the command packet Additional information is provided in bit 6 DLBE This bit is cleared when DMAC is enabled When this bit is set the INTE bit in DMA Control Register 2 was detected This bit is cleared when DMA is enabled or the interrupt status bit is cleared in the DMA interrupt control register or the DHALT bit was detected in DMA Control register 1 A DMAC interrupt will be generated if interrupts are enabled When this bit is set the DMA process was terminated if the DMAEND signal was asserted by the Industry Pack and the DMAEI bit is set in DMA Control
40. DMAC VMEbus Requester The chip contains an independent VMEbus requester associated with the Controller This allows flexibility in instituting different bus tenure policies for the single transfer oriented master and the block transfer oriented DMA controller The DMAC requester provides all the signals necessary to allow the on chip DMA Controller to request and be granted use of the VMEbus Requiring no external jumpers the chip provides the means for software to program the DMAC requester to request the bus on any one of the four bus request levels automatically establishing the bus grant daisy chains for the three inactive levels http www motorola com computer literature 2 13 VMEchip2 The DMAC requester requests the bus as required to transfer data to or from the FIFO buffer The requester implements a fair mode By setting the DFAIR bit the requester refrains from requesting the bus until it detects its assigned request line in its negated state The requester releases the bus when requested to by the DMA controller The DMAC always releases the VMEbus when the FIFO is full VMEbus to local bus or empty local bus to VMEbus The DMAC can also be programmed to release the VMEbus when another VMEbus master requests the bus when the time on timer has expired or when the time on timer has expired and another VMEbus master is requesting the bus To minimize the timing overhead of the arbitration process the DM
41. IL2 IL1 ILO OPER R R R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL IL2 ILO These three bits select the interrupt level for the tick timers Level 0 does not generate an interrupt ICLR Writing a logic 1 to this bit clears the tick timer interrupt i e INT bit in this register This bit is always read as 0 When this bit is set high the interrupt is enabled The interrupt is disabled when this bit is low INT When this bit is high a Tick Timer interrupt is being generated at the level programmed in IL2 ILO if nonzero This bit is edge sensitive and can be cleared by writing a logic 1 into the ICLR control bit 3 20 Computer Group Literature Center Web Site Programming Model DRAM Parity Error Interrupt Control Register The DRAM Parity Error Interrupt Control register controls the interrupt logic for parity error interrupts In the MVME1X2P4 the parity control and interrupt logic is contained in the DRAM Parity Error Interrupt Control register and the DRAM Control register located at FFF4201C and FFF42048 respectively This Interrupt Control register can also be used to generate interrupts if the MCECC memory controller detects conditions that require an interrupt In the first generation architectures this interrupt was generated from the VM Echip2 If no VMEbus interface was present no MCECC interrupt was possible Since this is added capability its use is
42. SIG1 LEVEL These bits define the level of the GCSR SIGI interrupt Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 2 bits 0 7 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 LEVEL LM0 LEVEL OPER R W R W RESET 0 PSL PSL This register is used to define the level of the GCSR LMO interrupt and the interrupt LEVEL These bits define the level of LMO interrupt LM1 LEVEL These bits define the level of GCSR interrupt Interrupt Level Register 3 bits 24 31 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 31 30 29 28 27 26 25 24 SW7 LEVEL SW6 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 6 interrupt and the software 7 interrupt SW6 LEVEL These bits define the level of the software 6 interrupt SW7 LEVEL These bits define the level of the software 7 interrupt http www motorola com computer literature VMEchip2 Interrupt Level Register 3 bits 16 23 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SW5 LEVEL SW4 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 4 interrupt and the software 5 interrupt SW4 LEVEL These bits define the level of the software 4
43. The chip includes both a global and a local reset driver When the chip operates as the VMEbus system controller the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET A SYSRESET may be generated by the RESET switch a power up reset a watch dog timeout or by a control bit in the LCSR SYSRESET remains asserted for at least 200 msec as required by the VMEbus specification Similarly the chip provides an input signal and a control bit to initiate a local reset operation The local reset driver is enabled even when the chip is not the system controller A local reset may be generated by the RESET switch a power up reset a watch dog time out a VMEbus signal or a control bit in the GCSR Local Bus Interrupter and Interrupt Handler There are 31 interrupt sources in the VMEchip2 ASIC VMEbus ACFAIL interrupter Tick timer 2 1 ABORT switch DMAC done VMEbus SYSFAIL interrupter GCSR SIG3 0 Write post bus error GCSR location monitor 1 0 External input Software interrupts 7 0 VMEbus IRQI edge sensitive interrupter VMEbus 7 1 interrupts VMEchip2 VMEbus interrupter acknowledge 2 18 Computer Group Literature Center Web Site Functional Blocks Each of the 31 interrupts can be enabled to generate a local bus interrupt at any level For example VMEbus 5 can be programmed to generate level 2 local bus interrupt The VMEbus AC
44. bit in this register This bit is cleared by an LM3 cycle on the VMEbus This bit is set when the local processor or a VMEbus master writes a 1 to the LM3 bit in this register http www motorola com computer literature 2 105 VMEchip2 VMEchip2 Board Status Control Register ADR SIZ Local Bus FFF40104 VMEbus XXY2 8 bits 5 used BIT 7 6 5 4 3 2 1 0 NAME RST ISF BF SCON SYSFL OPER S R R W R R R RESET OPSL OPSL PS X PSL This register is the VMEchip2 board status control register SYSFL SCON BF ISF RST This bit is set when the VMEchip2 is driving the SYSFAIL signal This bit is set if the VMEchip2 is system controller When this bit is high the Board Fail signal is active When this bit is low the Board Fail signal is inactive When this bit is set the VMEchip2 drives SYSFAIL if the inhibit SYSFAIL bit is not set When this bit is set the VMEchip2 is prevented from driving the VMEbus SYSFAIL signal line When this bit is cleared the VMEchip2 is allowed to drive the VMEbus SYSFAIL signal line This bit allows a VMEbus master to reset the local bus Referto the note on local reset in the GCSR Programming Model section earlier in this chapter When this bit is set a local bus reset is generated This bit is cleared by the local bus reset 2 106 Computer Group Literature Center Web Site GCSR Programming Model General Purpose Regi
45. esses 4 34 Programming the Programmable 220 4 44 Local Bus to IndustryPack Addressing rirnori 4 49 Bight Bit Memory 4 50 16 Bit Memory Spaces ouis EUER 4 51 Exodum dero T 4 52 HUE co XXX 4 53 MC UM E 4 54 IP TD CL 4 55 IP diu Local Bus Data Roning uc vets rese Mt Kir 4 56 Memory Space dat aite 4 56 HO and UD Henri 4 58 CHAPTER5 Functions MEC EE 5 1 ln e ETE 5 2 DESGUIB DIE uvae ute 5 3 D Hebe qe i RH pM THp ete 5 3 E 5 3 5 4 21 E 5 5 ere ere eee ee 5 5 Biror 5 5 tide 5 8 ev 5 8 5 8 n 5 9 e dro fepe DT 5 9 Programmis
46. 1 1 IPXD lt 7 0 gt BYTE 2 2 IPXD lt 15 8 gt 16 Bits 3 3 IPXD lt 7 0 gt 0 0 IPXD lt 15 8 gt IPXD lt 7 0 gt WORD 2 2 IPXD lt 15 8 gt IPXD lt 7 0 gt LWORD 0 0 2 IPXD lt 15 8 gt IPXD lt 7 0 gt IPXD lt 15 8 gt IPXD lt 7 0 gt 0 0 IPBD lt 15 8 gt 1 1 IPBD lt 7 0 gt BYTE 2 0 IPAD lt 15 8 gt 32 Bits 3 1 IPAD lt 7 0 gt 0 0 IPBD lt 15 8 gt IPBD lt 7 0 gt WORD 2 0 IPAD lt 15 8 gt IPAD lt 7 0 gt LWORD 0 0 IPBD lt 15 8 gt IPBD lt 7 0 gt IPAD lt 15 8 gt IPAD lt 7 0 gt 4 56 Computer Group Literature Center Web Site to Local Bus Data Routing IPWIDTH refers to the memory space width that has been programmed into the general control register for the IndustryPack being accessed LBSIZE refers to local bus transfer size LBA refers to local bus address signals 1 and 0 LD refers to the local data bus IPA refers to IndustryPack address signals 2 1 0 The 2 sector implements dynamic bus sizing for memory space accesses whose local bus size is greater than the port width of the IndustryPack that is being accessed Because of this the IP2 sector performs 1 2 or 4 IP memory space cycles for each local bus cycle The IPA column in the table lists 1 2 or 4 addresses to indicate the address for each IP cycle that is performed IPXD refers to the a data bus IPAD when accessing IP a or IP c It refers to the IP b data bus IPBD when accessing IP b or IP d http www motorola com c
47. Bclock MHz For example for operation at 25MHz the prescaler value is E7 and at 32MHz it is 0 Non integer local bus clocks introduce an error into the specified times for the various counters and timers This is most notable in the tick timers The tick timer clock can be derived by the following equation tick timer clock Bclock 256 prescaler value Ifthe prescaler is not correctly programmed the bus timers do not generate their specified values and the VMEbus reset time may be violated The maximum clock frequency for the tick timers is the B clock divided by two The prescaler register control logic does not allow the value 255 SFF to be programmed http www motorola com computer literature 2 67 VMEchip2 Tick Timer 1 Compare Register ADR SIZ FFF40050 32 bits BIT 31 oes 0 NAME Tick timer 1 Compare Register OPER R W RESET OP The tick timer 1 counter is compared to this register When they are equal an interrupt is sent to the local bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to calculate the compare register value for a specific period T compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initia
48. Block Diagram Figure 1 2 is a general block diagram of the MVME1X2P4 http www motorola com computer literature 1 7 Board Description and Memory Maps 2 Serial Ports DB 25 Front Panel Optional or Via P2 and Ethernet SCSI Transition Module Transceiver Peripherals LJ VMEbus Connections Connections A32 24 D64 32 16 08 Via P2 and Via P2 and A A Master Slave Transition Modules Transition Modules EIA 232 E Q Transceivers IndustryPack Y VMEchip2 O 82596CA 530710 285230 VMEbus 4 Channels Ethernet SCSI Serial Interface Controller Coprocessor EPROM Controller Socket IP2 MCECC MC2 posse Chip Chip Chip 1 MUR Functions Functions Functions Petra ASIC MC68040 MC68LC040 48 58 S SM REM Battery Backed MC68060 MC68L C060 ynenonovs 8KB RAM Clock MPU 1 4 8 1 6MB Parity 4 8 16 32 ECC DRAM Array Memory Array 512KB SRAM Memory Array Configuration Dependent Emulations w Battery 2498 0003 1 2 Figure 1 2 MVME1X2P4 Block Diagram Computer Group Literature Center Web Site 1 8 Functional Description Functional Description This section highlights few specific features of the MVME1X2P4 Embedded Controller For a complete functional des
49. STONI STONO STOFF2 STOFFI STOFFO OPER R W R W R W R W R W R W R W RESET OPLS 0 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS STOFF2 STOFF0 STOFF2 STOFFO control the amount of time that the scrubber refrains from requesting use of the DRAM each time it gives it up during a scrub They control the off time as follows http www motorola com computer literature Functions STOFF2 STOFF1 STOFFO Scrubber Time Off 0 0 0 Request DRAM immediately 0 0 1 Request DRAM after 16 BCLK cycles 0 1 0 Request DRAM after 32 BCLK cycles 0 1 1 Request DRAM after 64 BCLK cycles 1 0 0 Request DRAM after 128 BCLK cycles 1 0 1 Request DRAM after 256 BCLK cycles 1 1 0 Request DRAM after 512 BCLK cycles 1 1 1 Request DRAM never STON2 STONO STON2 STONO control the amount of time that the scrubber occupies the DRAM before providing a window during which the local bus and refresher might use it They control the on time as follows STON2 STON1 STONO Scrubber Time On 0 0 0 Keep DRAM for 1 memory cycle 0 0 1 Keep DRAM for 16 BCLK cycles 0 1 0 Keep DRAM for 32 BCLK cycles 0 1 1 Keep DRAM for 64 BCLK cycles 1 0 0 Keep DRAM for 128 BCLK cycles 1 0 1 Keep DRAM for 256 BCLK cycles 1 1 0 Keep DRAM for 512 BCLK cycles 1 1 1 Keep DRAM for TOTAL SCRUB TIME 5 22 Computer Group Literature Center Web Site Programming Model RW
50. Special precautions apply in a few cases Refer to the section on the Serial Communications Interface the MVME1X2P4 Installation and Use manual for more information 1 4 Computer Group Literature Center Web Site Overview VMEbus Interface The VMEbus interface is implemented with an ASIC called the VMEchip2 The VMEchip2 includes Two tick timers A watchdog timer Programmable map decoders for the master and slave interfaces A VMEbus to from local bus DMA controller A VMEbus to from local bus non DMA programmed access interface A VMEbus interrupter a VMEbus system controller a VMEbus interrupt handler and a VMEbus requester Processor to VMEbus transfers can be D8 D16 or D32 VMEchip2 DMA transfers to the VMEbus however can be D16 D32 D16 BLT D32 BLT or D64 MBLT Petra ASIC The Petra ASIC combines the functions of the MC2 chip the 2 chip and the MCECC chip in a single device Former MC2 chip functions now implemented by the Petra ASIC include four tick timers the interfaces to the LAN chip SCSI chip serial port chip and BBRAM the programmable interface for the DRAM and or SRAM and Flash write enable Former IndustryPack Interface Controller 2 chip functions now implemented by the Petra ASIC include control and status information including DMA control for up to two single size IndustryPacks IPs or one double size IP that can be plugged into the MVME1X2
51. 2 71 Tick Timer 2 Control et c 2 72 Tick Tiner LContol 1 EP Ga A 2 73 Pisscalep 2 73 Programming the Local Bus nterrupter isi 2 74 Local Bus Interrupter Status Register bits 24 31 2 77 Local Bus Interrupter Status Register bits 16 23 2 78 Local Bus Interrupter Status Register bits 8 15 2 79 Local Bus Interrupter Status Register bits 0 7 22 241 2 80 Local Bus Interrupter Enable Register bits 24 31 2 81 Local Bus Interrupter Enable Register bits 16 23 2 82 Local Bus Interrupter Enable Register bits 8 15 2 83 Local Bus Interrupter Enable Register bits 0 7 sess 2 84 Software Interrupt Set Register bits 8 15 sss 2 85 Interrupt Clear Register bits 24 31 ein RUE Hb 2 85 Interrupt Clear Register bits 10 23 siste canoe 2 86 Interrupt Clear Regrster Due 2 87 Interrupt Level Register 1 bits 24 31 2 87 Interrupt Level Register 1 bits 2 88 Interrupt Level Register 1 bits 8 19 iussisse eas PA pipe 2 88 Interrupt Level Register 1 bits D 7 2 89 Intercupt
52. 3 8 Computer Group Literature Center Web Site Functional Description When a match occurs in either mode an interrupt is sent to the local bus interrupter and the overflow counter is incremented An interrupt to the local bus is only generated if the tick timer interrupt is enabled by the local bus interrupter The overflow counter can be cleared by writing a 1 to the overflow clear bit Watchdog Timer A watchdog timer function is provided the VMEchip2 as well as the Petra MC2 chip The watchdog timer implemented in the Petra MC2 chip is used if the board is built in a No VMEbus Interface configuration When the watchdog timer is enabled it must be reset by software within the programmed time or it times out The watchdog timer can be programmed to generate a board level reset signal or board fail signal if it times out Note that unlike the VMEchip2 the Petra MC2 chip timer cannot generate a system reset because it is not connected to the VMEbus Local Bus Timer The MVMEI X2P4 provides a time out function for the local bus When the timer is enabled and a local bus access times out a Transfer Error Acknowledge TEA signal is sent to the local bus master The time out value is selectable by software for 8 usec 64 usec 256 usec or infinity The local bus timer does not operate during VMEbus bound cycles VMEbus bound cycles are timed by the VMEbus access timer and the VMEbus global timer Refer to the section on Exampl
53. Base register 0 by writing to bits 28 31 Refer to the Vector Base Register description and to Table 2 4 Local Bus Interrupter Summary in Chapter 2 6 Interrupt Level register 1 Write desired level of Tick Timer 1 interrupt to bits 0 2 bits 0 7 FFF40078 8 of 32 bits 7 Local Bus Interrupter Set bit 24 ETIC1 to 1 to enable Tick Timer 1 interrupts Enable register FFF4006C 8 of 32 bits 8 I O Control Register 1 Write a 1 to bit 23 to enable interrupts from the FFF40088 8 of 32 bits VMEchip2 A 0 masks all interrupts from the VMEchip2 Periodic Tick Timer 1 interrupts now occur so you need an interrupt handler Section 3 gives the details as follows 3 Set up an interrupt handler routine Step Action and Reference Your interrupt handler should include the following features 1 Be sure the 680 0 Vector Base register is set up Set the proper MC680x0 exception vector location so the processor vectors to your interrupt handler location You can determine the proper exception vector location to set from the MC680x0 Vector Base register the VMEchip2 Base register and Table 2 4 Local Bus Interrupter Summary in Chapter 2 from which you can determine the actual interrupt vector given on Tick Timer 1 interrupt Lower the MC680x0 mask so the interrupt level you programmed is accepted The interrupt handler itself should include the following steps 2 through 5 B 2 Computer Gro
54. Index L LAN interface 3 3 error 1 48 off board error 1 48 parity error 1 47 LANC bus error processing 3 4 LANC interrupt processing 3 5 LCSR Local Control Status Registers VMEchip2 2 20 base address 2 20 memory map 2 22 programming model 2 20 LEDs 2 99 LM SIG register VMEchip2 2 104 local control and status registers LCSRs VMEbus 2 7 DRAM parity error 1 42 I O devices memory map 1 14 reset driver VMEbus 2 18 reset VMEbus 2 18 local bus accesses from VMEbus 1 40 address counter DMAC 2 59 address range 2 39 base address GCSR 2 100 error signals 1 41 interrupt filters VMEchip2 ASIC 2 98 interrupter summary 2 75 interrupter how to set up B 2 map decoder registers 2 38 memory map 1 11 1 12 reset 2 106 time out 1 41 time out value 2 66 local bus interrupter DMAC and 2 12 programming 2 74 VMEchip2 2 18 local bus interrupter registers I O Control register 1 2 96 I O Control register 2 2 97 I O Control register 3 2 97 Interrupt Level register 4 bits 0 7 2 95 Miscellaneous Control register 2 98 Status register bits 16 23 2 78 Status register bits 24 31 2 77 Vector Base register 2 95 local bus master 2 9 VMEbus and 2 10 local bus slave VMEbus master registers Address Translation Address Register 4 2 42 Address Translation Select Register 4 2 43 Attribute Register 1 2 46 Attribute Register 2 2 45 Attribute Register 3 2 44 Attribute Register 4 2 43 Ending Address Register 1 2 40 Ending Addr
55. MC2 sector ADR SIZ FFF42040 8 bits BIT 7 6 5 4 3 2 1 0 NAME ABS INT IEN ICLR IL2 IL1 ILO OPER R R R R W R W R W R W RESET 0 0 PL IL2 ILO These three bits select the interrupt level for the ABORT switch Level 0 does not generate an interrupt ICLR Writing a logic 1 to this bit clears the abort interrupt i e the INT bit in this register This bit is always read as 0 With this bit set high the interrupt is enabled The interrupt is disabled when this bit is low 3 40 Computer Group Literature Center Web Site Programming Model ABS When this bit is high an interrupt is being generated for the ABORT switch Therefore the interrupt is level sensitive to the presence of the INT bit The interrupt is at the level programmed in IL2 ILO The ABORT switch status bit set to a 1 indicates that the ABORT switch is pressed When it is 0 the switch is inactive RESET Switch Control Register The RESET switch on the MVME1X2P4 front panel and several status control bits are defined by this register ADR SIZ BIT 31 30 FFF42044 8 bits 29 28 27 26 25 24 NAME BRFLI PURS CPURS BDFLO RSWE OPER R R R W R W RESET 0 1 PL 1P 0 1 PL 1P RSWE BDFLO CPURS PURS The RESET switch enable bit is used if the board is built in a VMEbus interfa
56. OPSL OPSL OPSL OPSL 0 PSL This is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled EIRQI EIRQ2 EIRQ3 EIRQ4 5 EIRQ7 SPARE Enable VMEbus IRQI interrupt Enable VMEbus IRQ interrupt Enable VMEbus IRQ3 interrupt Enable VMEbus IRQ4 interrupt Enable VMEbus 5 interrupt Enable VMEbus IRQ6 interrupt Enable VMEbus IRQ7 interrupt SPARE 2 84 Computer Group Literature Center Web Site LCSR Programming Model Software Interrupt Set Register bits 8 15 ADR SIZ FFF40070 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SSW7 SSW6 SSW5 SSW4 SSW3 SSW2 SSWI1 SSWO OPER 5 5 5 5 5 5 5 5 RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is used to set the software interrupts An interrupt is set by writing a 1 to it The software interrupt set bits are SSWO0 SSWI SSW2 SSW3 SSW4 SSWS SSW6 SSW7 Set software 0 interrupt Set software 1 interrupt Set software 2 interrupt Set software 3 interrupt Set software 4 interrupt Set software
57. RAMEN OPER R W R W R W R W R W R W R W R W RESET 0 0 0 0 0 PL 0 PL 0 PL RAMEN This bit enables the access of the DRAM The DRAM should be enabled after the DRAM Space Base Address register is enabled and the ROMO bit has been cleared The DRAM Space Base Address register is located at FFF42020 bits 31 16 and the ROMO bit is located at FFF42040 bit 20 3 44 Computer Group Literature Center Web Site Programming Model PARINT PAREN PARINT PAREN MPU None Alternate None Error Correction Disabled Interrupt None Enabled Checked Checked Enabled O Interrupt Checked Enabled WWP None means no parity checking Parity errors are not detected or reported Interrupt means that the MPU receives a parity interrupt if a parity error occurs The bus cycle is terminated with TA and runs at the same speed as unchecked cycles Checked means that the cycle is terminated by TEA if a parity error occurs Note that Checked cycles lengthen the DRAM accesses by one clock tick Setting WWP to a 1 causes check bits 6 and 7 to be inverted when writing to the SDRAM array This will generate a multi bit error when read cycles are executed The MC2 DRAM memory controller architecture will interpret the error as a parity error http www motorola com computer literature 3 45 MC2 Functions MPU Status Register
58. Round Robin Select RRS Single level SGL Programmable arbitration timer IACK daisy chain driver Programmable bus timer SYSRESET logic Global Control Status Register Set Four location monitors Global control of locally detected failures Global control of local reset Four global attention interrupt bits A chip ID and revision register Four 16 bit dual ported general purpose registers Interrupt Handler All interrupts level programmable All interrupts maskable All interrupts providing a unique vector Software and external interrupts Watchdog timer Control and status bits 4 bit counter Two tick timers Control and status bits 32 bit counter http www motorola com computer literature 2 VMEchip2 Functional Blocks The following sections provide an overview of the functions implemented by the VMEchip2 ASIC See Figure 2 1 for a block diagram of the VMEchip2 Detailed programming models for the local control and status registers LCSRs and the global control and status registers GCSRs appear in subsequent sections Local Bus to VMEbus Interface The local bus to V MEbus interface allows local bus masters access to global resources on the VMEbus This interface includes a local bus slave a write post buffer and a VMEbus master Using programmable map decoders with programmable attribute bits the local bus to V M
59. SRAM MST ga BSYT INT BGN 1361 9403 lt _ This sheet begins on facing page http www motorola com computer literature 1 21 Board Description and Memory Maps VMEchip2 GCSR Base Address FFF40100 Table 1 5 VMEchip2 Memory Map Sheet 3 of 3 Offsets Bit Numbers VME Loa 15 14 pn 6 5 2 1 0 bus Bus 0 0 Chip Revision Chip ID 2 4 s rR 68 X X X 1 s C FL 3 2 1 0 G G G Gi T 3 2 1 0 N 4 8 General Purpose Control and Status register 0 6 General Purpose Control and Status register 1 8 10 General Purpose Control and Status register 2 A 14 General Purpose Control and Status register 3 18 General Purpose Control and Status register 4 E 1C General Purpose Control and Status register 5 1 22 Computer Group Literature Center Web Site Memory Maps Table 1 6 Petra MC2 Functions Register Map MC2 Sector Base Address FFF42000 Offset D31 D24 D23 D16 D15 D8 D7 D0 00 MC2 chip ID MC2 chip General Interrupt Vector Revision Control Base Register 04 Tick Timer 1 Compare Register 08 Tick Timer 1 Counter Register 0 Tick Timer 2 Compare Register 10 Tick Timer 2 Counter Register 14 LSB Prescaler Prescaler Tick Timer 2 Tick Timer 1 Count Regist
60. The second register can be loaded by the processor in the direct mode and by the DMAC in the command chaining mode There is a case when the byte count for a DMA to local bus operation is initially set larger than the actual received data In this case there is residual data in the internal data paths of the DMA controller To flush the data set the byte count register to 0 A normal termination of the DMA occurs after the byte count register has been initialized to zero If an inbound DMA session is terminated before the byte count reaches zero data may remain in the FIFO You can purge the FIFO by having software write the byte count register to a zero This will have the effect of creating a normal termination for the transaction the FIFO will be emptied and a DMA termination interrupt will be generated An alternative method of terminating the DMA is available with the Petra ASIC In this case the IP module asserts a DMA end signal The FIFO empties a DMA termination interrupt is generated and the DMA end Status is set Once a DMAC is enabled its counter and control registers should not be modified by software When the command chaining DMA mode is used the list of commands must be in local not IP 32 bit memory and the entries must be aligned to a 16 byte boundary That is the address which is loaded into the DMA table address counter must have bits 3 through 0 set to a 0 This is true for the initial value which is loaded by
61. VIRQ2 VIRQI LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the VMEbus level 1 IRQ1 interrupt and the VMEbus level 2 IRQ2 interrupt The IRQ1 and IRQ2 interrupts may be mapped to any local bus interrupt level VIRQ1 LEVEL These bits define the level of the VMEbus interrupt VIRQ2 LEVEL These bits define the level of the VMEbus IRQ interrupt Vector Base Register ADR SIZ FFF40088 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME VBR 0 VBR 1 R W R W RESET 0 PSL 0 PSL This register is used to define the interrupt base vectors VBR 1 These bits define the interrupt base vector 1 0 These bits define the interrupt base vector 0 Note Refer to Table 2 4 Local Bus Interrupter Summary for further information A suggested setting for the VMEchip2 Vector Base register is VBRO 6 VBRI 7 i e setting the Vector Base register at address FFF40088 to 67xxxxxx This produces a Vector Base0 of 60 corresponding to the X in Table 2 4 and a Vector Basel of 70 corresponding to the Y in Table 2 4 http www motorola com computer literature 2 95 VMEchip2 Control Register 1 ADR SIZ FFF40088 8 bits of 32 BIT 23 21 20 19 18 17 16 NAME MIEN SYSFL ACFL ABRTL 2 GPOENI GPOENO OPER R W R R R W R W R W R W RESET OPSL X X 0 PS 0 PS 0 PS 0 PS
62. When parity checking is enabled the current bus master receives a bus error and a parity error occurs while it is accessing the local DRAM VMEchip2 An 8 or 16 bit write to the LCSR in the VMEchip2 causes a local BERR 1 42 Computer Group Literature Center Web Site Software Support Considerations Bus Error Processing Because different conditions can cause bus error exceptions the software must be able to distinguish the source To aid in this status registers are provided for every local bus master The next section describes the various causes of bus errors and the associated status registers Generally the bus error handler can interrogate the status bits and proceed with the result However an interrupt can happen during the execution of the bus error handler before an instruction can write to the status register to raise the interrupt mask If the interrupt service routine causes a second bus error the status that indicates the source of the first bus error may be lost Software must be written to deal with such cases Description of Error Conditions on the MVME1X2P4 This section lists the various error conditions that may be reported by the MVME1X2P4 hardware A subsection heading identifies each type of error condition A standard format gives a description of the error indicates how notification of the error condition is made indicates which status register s have information about the error and concludes with
63. When this bit is low write posting is disabled to the VMEbus short I O segment When this bit is high D16 data transfers are performed to the VMEbus short I O segment When this bitis low D32 data transfers are performed to the VMEbus short I O segment When this bit is high the VMEbus short I O map decoder is enabled When this bit is low the VMEbus short I O map decoder is disabled When this bit is high the VMEchip2 drives a program address modifier code when the F page is accessed When this bit is low the VMEchip2 drives a data address modifier code when the F page is accessed When this bit is high VMEchip2 drives a supervisor address modifier code when the F page is accessed When this bit is low the VMEchip2 drives a user address modifier code when the F page is accessed 2 50 Computer Group Literature Center Web Site LCSR Programming Model DWP When this bit is high write posting is enabled to the local bus F page When this bit is low write posting is disabled to the local bus F page IZEN When this bit is high the F page F0000000 through FF7FFFFF map decoder is enabled The FO page is defined as A24 D16 on the VMEbus while the F1 FE pages are defined as A32 D16 When this bit is low the F page is disabled ROM Control Register ADR SIZ FFF4002C BIT 7 6 5 4 3 2 1 0 NAME SIZE BSSPD ASPD OPER R W R W R W RESET OPS OPS OPS This function is not used on
64. controller in the MC680x0 to monitor the local bus addresses Local Bus to VMEbus DMA Controller The DMA Controller DMAC operates in conjunction with the local bus master the VMEbus master and a 16 four byte FIFO buffer The DMA controller has a 32 bit local address counter 32 bit table address counter a 32 bit VMEbus address counter a 32 bit byte counter and control and status registers The Local Control and Status register LCSR provides software with the ability to control the operational modes of the DMAC Software can program the DMAC to transfer up to 4GB of data in the course of a single DMA operation The DMAC supports transfers from any local bus address to any VMEbus address The transfers may be from 1 byte to 4GB in length To optimize local bus use the DMAC automatically adjusts the size of individual data transfers until 32 bit transfers can be executed Based on the address of the first byte the DMAC transfers a single byte a double byte or a mixture of both and then continues to execute quad byte block transfer cycles When the DMAC is set for 64 bit transfers the octal byte transfers takes place Based on the address of the last byte the DMAC transfers a single byte a double byte or a mixture of both to end the transfer 2 10 Computer Group Literature Center Web Site Functional Blocks Using control register bits in the LCSR the DMAC can be configured to provide the following VMEbus capabilities
65. some comments pertaining to each particular error MPU Parity Error Note Although the MVMEIX2PA series contains synchronous DRAM SDRAM rather than parity DRAM it can be made to emulate parity DRAM for compatibility with the MC2 programming model Description A DRAM parity error MPU Notification TEA is asserted during an MPU DRAM access Status Bit 9 of the MPU Status and DMA Interrupt Count register in the VMEchip2 Address FFF40048 Comments After memory has been initialized this error normally indicates a hardware problem http www motorola com computer literature 1 43 Board Description and Memory Maps MPU Offboard Error Description MPU Notification Status Comments An error occurred while the MPU was attempting to access an offboard resource TEA is asserted during offboard access Bit 8 of the MPU Status and DMA Interrupt Count register Address FFF40048 This can be caused by a VMEbus timeout a VMEbus BERR an MVME1X2P4 VMEbus access timeout The latter is the time from when the VMEbus has been requested to when it is granted MPU TEA Cause Unidentified Description MPU Notification Status Comments MPU Local Bus Timeout Description MPU Notification Status Comments An error occurred while the MPU was attempting an access TEA is asserted during an MPU access Bit 10 of the MPU Status and DMA Interrupt Count register Address FF
66. 0 0 0 0 0 0 58 DMA_c LB LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 59 DMA cLB LBA23 LBA22 LBA21 LBA20 LBAI9 LBAI18 LBAI7 16 ADDR SA DMA_cLB 15 14 LBAI13 LBAI2 LBAII LBAIO LBA9 LBAS8 ADDR 5B DMA cLB LBA7 5 4 LBA2 LBAI LBAO ADDR 5C DMA cIP 0 0 0 0 0 0 0 0 ADDR 5D DMA _c IP 23 22 21 20 19 18 17 16 ADDR 5E DMA cIP 15 14 13 12 11 10 9 ADDR SF DMA _c IP IPA7 5 4 IPA2 IPAI IPAO ADDR 60 DMA c 0 0 0 0 0 0 0 0 BYTE CNT 61 DMA c BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 BCNT18 BCNT17 BCNT16 BYTE CNT 62 DMA_c 15 BCNT14 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 BCNTS8 BYTE CNT 63 DMA c BCNT7 BCNT6 BCNTS 4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 64 DMA c TBL TA31 TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADDR 65 DMA c TBL TA23 TA22 TA21 TA20 19 18 17 16 ADDR 66 DMA c TBL 15 14 13 12 11 10 9 8 ADDR 67 DMA_c TBL 7 6 5 4 TA2 TAI TAO ADDR 2592 9908 4 6 1 28 Computer Group Literature Center Web Site Memory Maps Table 1 8 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address FFFBCOO0 Register Register Register Bit Names Offset Name D7 D6 05 D
67. 0 PS 0 PS O PS This register is the attribute register for the first local bus to V MEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 1 Because the local bus to V MEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to the segment defined by map decoder 1 When this bit is low write posting is disabled to the segment defined by map decoder 1 When this bit is high D16 data transfers are performed to the segment defined by map decoder 1 When this bit is low D32 data transfers are performed to the segment defined by map decoder 1 2 46 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave GCSR Group Address Register ADR SIZ FFF4002C 8 bits of 32 BIT 31 24 GCSR Group Address Register 4 OPER R W RESET 00 PS This register defines the group address of the GCSR as viewed from the VMEbus The GCSR address is defined by the group address and the board address Once enabled the GCSR register should not be reprogrammed unless the VMEchip2 ASIC is VMEbus master GCSR Group These bits define the group portion of the GCSR address These bits are compared with VMEbus address lines A8 through A15 The recommended group address for the
68. 0F PS This register controls the VMEbus interrupter vector MPU Status and DMA Interrupt Count Register ADR SIZ FFF40048 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME DMAIC MCLR MLBE MLPE MLOB OPER R C R R R RESET 0 PS 0 PS 0 PS 0 PS 0 PS This is the MPU status register and DMAC interrupt counter MLOB MLPE MLBE MCLR When this bit is set the MPU received a TEA and the status indicated off board This bit is cleared by writing a 1 to the MCLR bit in this register When this bit is set the MPU received a TEA and the status indicated a parity error during a DRAM data transfer This bitis cleared by writing a 1 to the MCLR bit in this register This bit is not defined for MVME1X2P4 implementation When this bit is set the MPU received a TEA and no additional status was provided This bit is cleared by writing a 1 to the MCLR bit in this register Writing a 1 to this bit clears the MPU status bits 7 8 9 and 10 MLTO MLOB MLPE and MLBE in this register Computer Group Literature Center Web Site LCSR Programming Model DMAIC The DMAC interrupt counter is incremented when an interrupt is sent to the local bus interrupter The value in this counter indicates the number of commands processed when the DMAC is operated in command chaining mode If the interrupt count exceeds 15 the counter rolls over This counter operates regardless of whether the DMAC
69. 2 96 general purpose registers VMEchip2 2 101 global control status registers General Purpose Register 0 2 107 General Purpose Register 2 2 107 General Purpose Register 3 2 108 General Purpose Register 4 2 108 General Purpose Register 5 2 108 ID register VMEchip2 2 104 VMEchip2 Board Status Control register 2 106 VMEchip2 ID register 2 104 VMEchip2 LM SIG register 2 104 VMEchip2 Revision register 2 103 global control status registers GCSRs 2 100 global reset driver VMEbus 2 18 global reset VMEbus 2 18 GPI inputs addresses 1 9 general purpose input 3 bit 1 13 GPI3 bit EPROM Flash select 3 33 group address GCSR 2 47 H hexadecimal number symbol for xxiv T O and ID space accesses 4 58 interfaces 1 6 I O map decoders 2 6 2 37 2 39 IN 4 Computer Group Literature Center Web Site memory maps 1 17 T O space 32 bit IP_ab 4 54 IP_a 4 53 cycle VMEbus 2 20 daisy chain driver VMEbus and 2 17 TACK daisy chain VMEbus 2 16 ID space IP 4 55 indivisible cycles MC680x0 1 51 IndustryPack addressing 4 49 error reporting 4 9 ID bytes 1 38 Interface Controller ASIC Petra IP2 chip 4 1 initialization DRAM 5 34 interrupt base vectors VMEbus 2 95 control MCECC 3 21 control register VMEchip2 2 101 counter DMAC 2 62 handler routine how to set up B 2 handler VMEbus 2 16 priority 1 40 sources VMEchip2 2 18 status bit 2 77 Vector Base register encoding and
70. 27 26 25 24 LTO SCLR OPER R R R R R R R R RESET 0 0 0 0 SCLR Writing a 1 to this bit clears bits LTO EXT and PRTY Reading this bit always yields 0 LTO EXT PRTY These bits indicate the status of the last local bus error condition encountered by the SCSI processor while performing DMA accesses to the local bus A local bus error condition is flagged by the assertion of TEA When the SCSI processor receives if the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the is due to an error in going to the VMEbus then EXT is set and the other two status bits are cleared If the source of the error is DRAM parity check error then PRTY is set and the other two status bits are cleared If the source of the error Computer Group Literature Center Web Site Programming Model is none of the above conditions then all three bits are cleared Writing a 1 to bit 24 SCLR also clears all three bits General Purpose Inputs Register The contents of a PAL in conjunction with board level configuration resistors and an array of software switches produce the bit settings of the General Purpose Inputs register Version register and DRAM SRAM Options register when the Petra ASIC s MC2 sector is reset These are read only registers Writes to these registers are terminated without exception but do not change their con
71. 37 programming DMA controller VMEchip2 ASIC 2 51 controllers IP2 sector 4 31 GCSR global control status registers VMEchip2 2 102 GCSR base address registers 2 37 IP2 sector programmable clock 4 44 LCSR VMEchip2 2 20 local bus interrupter 2 74 programming continued local bus to VMEbus map decoders VMEchip2 2 37 local bus to VMEbus requester register 2 51 MPU Status register 2 51 tick and watchdog timers VMEchip2 2 64 tick timers Petra MC2 chip 3 15 VMEbus interrupter 2 51 VMEbus slave map decoders 2 26 programming model MCECC control status registers 5 10 Petra IP2 chip 4 11 Petra MC2 chip 3 11 VMEchip2 GCSR 2 100 VMEchip2 LCSR 2 20 PROM Access Time Control register 3 38 PROM EPROM sockets 1 6 PROM Flash interface 3 2 PWB number field 1 38 R refresh function MCECC sector 5 8 register definitions LCSR 2 21 registers local bus map decoders 2 38 VMEbus slave map decoder 2 26 related publications 1 related specifications C 3 release on acknowledge ROAK mode VMEbus 2 16 release on request ROR mode VMEchip2 ASIC 2 8 reset drivers VMEbus 2 18 reset status Petra IP2 chip 4 11 RESET switch enabling disabling 2 70 reset Petra MC2 chip 3 33 revision register VMEchip2 2 103 ROM Control register VMEchip2 ASIC 2 51 http www motorola com computer literature IN 9 lt moz xXmoz Index Round Robin Select RRS arbitration mode VMEbus 2 17 S SCC serial communication
72. 4 Programmable IP_b Memory D32 D8 64KB 8MB 2 4 Programmable IP_c Memory D32 D8 64KB 8MB 2 4 Programmable IP_d Memory D32 D8 64KB 8MB 2 4 FF800000 FF9FFFFF Flash EPROM D32 2MB N 1 5 FFA00000 FFBFFFFF EPROM Flash D32 2MB N 6 FFC00000 FFCFFFFF Not decoded 7 FFD00000 FFDFFFFF Not decoded 7 FFE00000 SFFE7FFFF SRAM default D32 512 FFE80000 FFEFFFFF Not decoded 512 7 FFFO0000 FFFEFFFF Local I O D32 D8 878KB Y 3 FFFF0000 SFFFFFFFF VMEbus 16 D32 D16 64KB 2 4 1 12 Computer Group Literature Center Web Site Notes 1 Reset enables the decoder for this space of the memory map so that it will decode address spaces FF800000 SFF9FFFFF 00000000 003FFFFF The decode at 0 must be disabled in the chip before DRAM is enabled DRAM is enabled with the DRAM Control register at address FFF42048 bit 24 EPROM Flash is disabled at the low address space with the EPROM Control register at address FFF42040 bit 20 This area is user programmable The DRAM and SRAM decoder is programmed in the Petra chip the local to VMEbus decoders are programmed in the VMEchip2 and the IP memory space is also programmed in the Petra chip Size is approximate Cache inhibit depends on devices in area mapped The EPROM and Flash are sized by the Petra chip from an 8 bit private bus to the 32 bit MPU local bus Because the de
73. 5 8 error reporting Petra IP2 chip 4 9 as a local bus master 4 8 as a local bus slave 4 8 error reporting Petra MCECC chip 5 5 error sources local 1 41 error types MCECC sector 5 5 http www motorola com computer literature IN 3 lt moz xXmoz Index errors DMAC local bus time out 1 46 DMAC off board access 1 46 DMAC 1 47 LAN local bus time out 1 48 LAN off board access 1 48 MPU local bus time out 1 44 MPU off board access 1 44 MPU TEA 1 44 SCSI local bus time out 1 50 SCSI off board access 1 49 VMEbus DMAC 1 45 Ethernet address 1 37 Ethernet LAN memory map 1 31 examples generating tick timer periodic interrupt 1 setting up interrupt handler routine B 2 setting up local bus interrupter B 2 extended access cycles VMEbus 2 34 2 37 F fair mode VMEchip2 2 8 2 14 features IP2 function 4 1 MC2 function 3 1 MCECC sector 5 1 MVMEIx2PA 1 6 VMEchip2 ASIC 2 1 Flash memory 1 6 write enable via BBRAM 3 3 write protection and MC1 MC2 mode 1 16 3 39 Flash EPROM interface 3 2 selection 1 13 sizing 1 13 functional description 1 9 MCECC sector 5 3 Petra MC2 sector 3 2 VMEchip2 ASIC 2 4 G GCSR global control status registers programming 2 102 VMEchip2 2 20 2 100 base address registers programming 2 37 board address 2 48 group address 2 47 map decoder 1 40 programming model 2 100 SIG3 0 interrupters VMEbus 2 19 General Purpose Register 1 2 107 general purpose I O pins direction
74. 82596CA Ethernet LAN Directly Accessible Registers Data Bits Address D31 sss D16 D15 m DO FFF46000 Upper Command Word Lower Command Word FFF46004 MPU Channel Attention CA Notes 1 Refer to the MPU Port and MPU Channel Attention registers in Chapter 3 2 After reset you must write the System Configuration Pointer to the command registers prior to writing to the MPU Channel Attention register Writes to the System Configuration Pointer must be upper word first lower word second http www motorola com computer literature 1 31 Board Description and Memory Maps Table 1 11 53C710 SCSI Memory Map Base Address is F FF47000 ea 53C710 Register Address Map Pan n 00 SIEN SDID SCNTL1 SCNTLO 00 04 SOCL SODL SXFER SCID 04 08 SBCL SBDL SIDL SFBR 08 0 SSTAT2 55 SSTATO DSTAT 0 10 DSA 10 14 CTEST3 CTEST2 CTESTI CTESTO 14 18 CTEST7 CTEST6 CTESTS CTEST4 18 20 LCRC 8 ISTAT DFIFO 20 24 DCMD DBC 24 28 DNAD 28 2C DSP 2C 30 DSPS 30 34 SCRATCH 34 38 DCNTL DWT DIEN DMODE 38 3C ADDER 3C Note Accesses may be 8 bit or 32 bit but not 16 bit Computer Group Literature Center Web Site Memory Maps BBRAM TOD Clock Memory Map The M48T58 BBRAM also called Non Volatile RAM or NVRAM is divided into six areas as shown in Table 1 12 The first five areas are defined by software whi
75. Any other combinations generate unpredictable results DZ2 DZO are set equal to the DZ2 DZO bits of the DRAM SRAM Options register Note that changing DZ2 DZO so that the DRAM architecture changes between interleaved and non interleaved relocates the data DZ2 70 are programmable to facilitate diagnostic software Table 3 6 DRAM Size Control Bit Encoding DZ2 DZ0 Memory Size 0 1MB 1 Not defined for MVMEIX2P4 2 Not defined for MVMEIX2P4 3 Not defined for MVME1 X2P4 4 4MB 5 8MB 6 DRAM not present 7 16MB Computer Group Literature Center Web Site Programming Model DRAM SRAM Options Register This is a read only register It is initialized at reset ADR SIZ FFF42024 8 bits BIT 23 22 21 20 19 18 17 16 NAME FO 571 570 DZ2 071 070 R R R R R R R R RESET Application Specific DZ2 DZ0 Bits DZ2 DZO indicate the size and architecture of the non ECC DRAM array Software must initialize the DRAM Space Size register FFF42024 bits 26 24 based on the value of DZ2 DZ0 DZ2 DZO are initialized at reset to a value which is determined by the contents of a factory programmed resident device Table 3 7 DRAM Size Control Bit Encoding 072 070 DRAM Configuration 0 1 Not defined MVMEIX2PA 2 Not defined MVMEIX2PA 3 Not defined for MVMEIX2PA 4 4 5 8MB 6 DRAM is not pr
76. DMA_b DHALT 0 DTBL ADMA WIDTHI WIDTHO A CHI XXX CONTROL 1 3D DMA b INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 3E RESERVED 0 0 0 0 0 0 0 0 RESERVED 0 0 0 0 0 0 0 0 40 DMA_bLB LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 41 DMA_bLB LBA23 LBA22 LBA21 LBA20 LBAI9 LBA18 LBAI7 16 ADDR 42 DMA_bLB 15 14 LBAI3 LBAI2 LBAIO LBA9 LBAS8 ADDR 43 DMA bLB LBA7 LBA6 LBAS LBA4 LBA3 LBA2 LBAI LBAO ADDR 44 DMA_b IP 0 0 0 0 0 0 0 0 ADDR 45 DMA_b IP IPA23 IPA22 21 20 19 18 17 16 ADDR 46 DMA_b IP 15 14 13 12 11 10 IPA9 ADDR 47 DMA_b IP IPA7 6 5 4 IPA2 1 ADDR 48 DMA_b 0 0 0 0 0 0 0 0 49 DMA_b 23 22 21 BCNT20 BCNT19 BCNTIS8 BCNTI7 BCNTI6 BYTE CNT 4 DMA_b 15 BCNT14 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 BCNTS8 BYTE CNT 4B DMA b BCNT7 BCNT6 BCNTS 4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 4 DMA_b TBL TA31 TA30 TA29 28 27 26 25 24 ADDR 4D DMA_b TBL 23 22 21 20 19 18 17 16 ADDR 4E DMA_b TBL TA15 TA14 TA13 TA12 11 10 9 ADDR 4 DMA_b TBL 7 6 5 4 TA2 TAI TAO ADDR 2592 9908 3 6 4 14 Computer Group Literature Center Web Site Programming Model Table 4 4 Petra IP2 Memory Map Control Status Registers Cont d IP2 S
77. LAN Parity Error An error occurred while the DMAC was Local Bus master and additional status was not provided DMAC interrupt when enabled The DLBE bit is set in the DMAC Status register Address FFF40048 bit 6 An 8 or 16 bit write to the LCSR in the VMEchip2 causes this error If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access Note Although the MVMEIX2PA series contains synchronous DRAM SDRAM rather than parity DRAM it can be made to emulate parity DRAM for compatibility with the MC2 programming model Description MPU Notification Status Comments Parity error while the LANCE was reading DRAM Petra MC2 Sector Interrupt LAN ERROR IRQ Petra MC2 Sector LAN Error Status register Address FFF42028 The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the Petra MC2 sector Control for the interrupt is in the MC2 sector s LAN Error Interrupt Control register FFF4202B http www motorola com computer literature 1 47 Board Description and Memory Maps LAN Offboard Error Description Error encountered while the LANCE was attempting to go to the VMEbus MPU Notification Petra MC2 Sector Interrupt LAN ERROR IRQ Status Petra MC2 Sector LAN Error Status register Address FFF42028 Comments The LANCE has no ability to respond to TEA so the error inte
78. LEVEL IRQ LEVEL GPIOO GPIOI GPI REV DIS DIS My DIS EN DIS EN FROM SRAM MST gay BSYT INT BGN 1361 9403 lt _ This sheet begins on facing page http www motorola com computer literature 2 25 VMEchip2 Programming the VMEbus Slave Map Decoders This section includes programming information for the VMEbus to local bus map decoders The VMEbus to local bus interface allows off board VMEbus masters access to local on board resources The address of the local resources as viewed from the VMEbus is controlled by the VMEbus slave map decoders which are part of the VMEbus to local bus interface Two VMEbus slave map decoders in the VMEchip2 allow two segments of the VMEbus to be mapped to the local bus A segment may vary in size from 64KB to 4GB in increments of 64KB Address translation is provided by the address translation registers The upper 16 bits of the local bus address come from the address translation address register rather than from the upper 16 bits of the VMEbus address Each VMEbus slave map decoder has the following registers address translation address register address translation select register starting address register ending address register address modifier select register and attribute register The tables on the following pages list the addresses and bit definitions of these registers The VMEbus slave map decoders described in this section are disabled by local
79. Local Control and Status registers LCSR in the VMEchip2 ASIC The local bus map decoder for the LCSR is included in the VMEchip2 The base address of the LCSR is FFF40000 and the registers are 32 bits wide Single byte double byte and quad byte read operations are permitted but single byte and double byte write operations are not Single and double byte write operations return a TEA signal to the local bus Read modify write operations should be used to modify a byte or a two byte of a register 2 20 Computer Group Literature Center Web Site LCSR Programming Model Each register definition includes a table with five lines 1 The base address of the register and the number of bits defined in the table 2 The bits defined by this table 3 The name of the register or the name of the bits in the register 4 The operations possible on the register bits defined as follows R This bit is a read only status bit R W This bit is readable and writable W AC This bit can be set and it is automatically cleared This bit can also be read Writing a 1 to this bit clears this bit or another bit This bit reads 0 5 Writing a 1 to this bit sets this bit or another bit This bit reads 0 5 The state of the bit following a reset defined as follows The bit is affected by powerup reset The bit is affected by SYSRESET The bit is affected by local reset bit is not affected by reset Table 2
80. MVME1X2P4 Programming the VMEchip2 DMA Controller This section includes programming information on the DMA controller VMEbus interrupter MPU status register and local bus to VMEbus requester register The VMEchip2 features a local bus to VMEbus DMA controller DMAC The DMAC has two modes of operation command chaining and direct In direct mode the local bus address the VMEbus address the byte count and the control register of the DMAC are programmed and the DMAC is enabled The DMAC transfers data as programmed until the byte count is zero or an error is detected When the DMAC stops the status bits in the DMAC status register are set and an interrupt is sent to the local bus interrupter If the DMAC interrupt is enabled in the local bus interrupter the local bus is interrupted The time on and time off timers should be programmed to control the VMEbus bandwidth used by the DMAC http www motorola com computer literature 2 51 VMEchip2 A maximum of 4GB of data may be transferred with one DMAC command Larger transfers can be accomplished using the command chaining mode In command chaining mode a singly linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands The DMAC control register is programmed and the DMAC is enabled The DMAC executes commands from the list until all commands are executed or an error is dete
81. MVMEIX2PA is D2 http www motorola com computer literature 2 47 VMEchip2 VMEbus Slave GCSR Board Address Register ADR SIZ FFF4002C 4 bits of 32 BIT 23 20 GCSR Board Address OPER R W RESET F PS This register defines the board address of the GCSR as viewed from the VMEbus The GCSR address is defined by the group address and the board address Once enabled the GCSR register should not be reprogrammed unless the VMEchip2 is VMEbus master The value F in the GCSR board address register disables the map decoder The map decoder is enabled when the board address is not F GCSR Board These bits define the board number portion of the GCSR address These bits are compared with VMEbus address lines A4 through A7 The GCSR is enabled by values 0 through SE The address XXFY in the VMEbus A16 space is reserved for the location monitors LMO through LM3 Note that XX is the group address and Y is the location monitor 1 LMO 3 LM1 5 LM2 7 LM3 2 48 Computer Group Literature Center Web Site LCSR Programming Model Local Bus to VMEbus Enable Control Register ADR SIZ FFF4002C 4 bits of 32 BIT 19 18 17 16 NAME EN4 EN3 EN2 R W R W R W R W RESET OPSL OPSL OPSL 0 PSL This register is the map decoder enable register for the four programmable local bus to VMEbus map decoders EN1 EN2 EN
82. Size 0 0 JO 16 64KB 0 0 0 0 0 0 0 1 1 17 128 O 10 JO JO 0 JO I I A31 A18 256KB O 0 0 0 0 1 1 1 1 19 512 O JO JO JO 1 I 1 A31 A20 1MB O JO JO 1 1 1 1 1 A31 A21 2MB O 0 1 1 1 1 1 1 A31 A22 4MB O 1 1 1 1 1 1 1 23 8 1 1 1 1 1 1 1 A31 A24 16MB Note that 16MB is only possible using a double size IP 4 22 Computer Group Literature Center Web Site Programming Model IRQO IRQ1 Interrupt Control Registers ADR SIZ FFFBCO10 through FFFBCO17 8 bits each BIT 7 6 5 4 3 2 1 0 10 20PLTY a0EL a0IEN 0 2 a0 ILI a0 ILO NAME 11 1 EL al IIR a2 al ILI al ILO NAME 12 bOPLTY 12 b0 ILO NAME 13 biPLTY bLINT bLIEN bl ILO NAME 14 cOPLTY c0EL cOINT OEN c0 ILI c0 ILO 15 clPLTY clIEN 2 cl ILI cl JLO 16 d PLTY do Fa dOIEN 912 0 d0 ILO NAME 17 diPLTY dl ILO OPER R W R W R R W C R W R W R W RESET OR OR OR OR OR OR OR OR IL2 IL0 These three bits select the interrupt level for the corresponding Indust
83. Source dirty invalidate line Snoop enabled 1 1 Snoop disabled Reserved Snoop disabled ROMO This bit is not used on the MVME1X2P4 Its function is performed by the ROMO bit in the Petra MC2 PROM Access Time Control register Refer to Chapter 3 WAIT RMW This function is not used on the MVME1X2P4 Local Bus to VMEbus Requester Control Register ADR SIZ FFF40030 8 bits 7 used OF 32 BIT 15 14 13 12 11 10 9 8 NAME ROBN DHB DWB LVFAIR LVRW LVREQL D OPER R W R R W R W R W R W RESET OPS OPS 0 PSL OPS OPS 0 PS This register controls the VMEbus request level the request mode and release mode for the local bus to V MEbus interface LVREQL These bits define the VMEbus request level The request level can only change while the VMEchip2 is bus master The VMEchip2 always requests at the old level until it becomes bus master and the new level takes effect If the VMEchip2 is bus master when the level is changed the new level does not take effect until the bus has been released and re requested at the old level The requester always requests the VMEbus at level 3 the first time following a SYSRESET 2 54 Computer Group Literature Center Web Site LCSR Programming Model LVRWD LVFAIR DWB DHB ROBN The request level is 0 The request level is 1 The request level is 2 The request level is 3 When this bit is high the requester operates in release
84. This logic is duplicated in the VMEchip2 ASIC at location FFF40048 bits 11 10 9 and 7 The duplication is to enable No VMEbus Interface operation if necessary ADR SIZ BIT FFF42048 8 bits 13 12 11 10 9 8 NAME MCLR MLBE MLPE MLTO OPER R R R R R RESET 0 0 0 PL 0 PL 0 PL MLPE MLBE MCLR When this bit is set the MPU received a TEA and the status indicated a local bus time out This bit is cleared by writing a 1 to the MCLR bit in this register The MLTO bit is used if the board is built in a VMEbus interface configuration and is duplicated in the VMEchip2 at address FFF40048 bit 7 When this bit is set the MPU received a TEA and the status indicated a parity error during a DRAM data transfer This bit is cleared by writing a 1 to the MCLR bit in this register The MLPE bit is used if the board is built in a VMEbus interface configuration and is duplicated in the VMEchip2 at address FFF40048 bit 9 When this bit is set the MPU received a TEA and additional status was not provided This bit is cleared by writing a 1 tothe MCLR bit in this register The MLBE bit is used if the board is built in a VMEbus interface configuration and is duplicated in the VMEchip2 at address FFF40048 bit 10 Writing a 1 to this bit clears the MPU status bits 8 9 and 10 MLTO MLPE and MLBE in this register 3 46 Compu
85. VMEbus map decoder Local Bus Slave VMEbus Master Ending Address Register 2 ADR SIZ FFF40018 16 bits of 32 BIT 31 Je 16 NAME Ending Address Register 2 OPER R W RESET 0 PS This register is the ending address register for the second local bus to VMEbus map decoder 2 40 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Slave VMEbus Master Starting Address Register 2 ADR SIZ FFF40018 16 bits of 32 BIT 15 0 Starting Address Register 2 OPER R W RESET 0 PS This register is the starting address register for the second local bus to VMEbus map decoder Local Bus Slave VMEbus Master Ending Address Register 3 ADR SIZ FFF4001C 16 bits of 32 BIT 31 16 Ending Address Register 3 OPER R W RESET 0 PS This register is the ending address register for the third local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 3 ADR SIZ FFF4001C 16 bits of 32 BIT 15 96 0 Starting Address Register 3 OPER R W RESET 0 PS This register is the starting address register for the third local bus to VMEbus map decoder http www motorola com computer literature 2 41 VMEchip2 Local Bus Slave VMEbus Master Ending Address Register 4 ADR SIZ FFF40020 16 bits of 32 BIT 31 16 Ending A
86. affected by reset A summary of the IP2 sector CSR registers appears in Table 4 4 The CSR registers can be accessed as bytes words or longwords They should not be accessed as lines They are shown in the table as bytes and the bits in most of the following register descriptions are labeled as bits 7 through 0 http www motorola com computer literature 4 11 2 Functions Table 4 4 Petra 2 Memory Map Control Status Registers IP2 Sector Base Address FFFBCOO0 Register Register Register Bit Names Offset Name D7 06 05 D4 D3 D2 D1 Do 00 CHIP ID 0 0 1 0 0 0 1 1 01 0 0 0 0 0 0 1 X REVISION 02 RESERVED 0 0 0 0 0 0 0 0 03 IV6 IV5 IVA IV3 IV2 IVI IVO BASE 04 IPaMEM BASE30 a BASE29 a BASE28 a BASE27 a BASE26 a BASE25 a BASE24 BASE UPPER 05 IPaMEM 5 23 a BASE22 a BASE21 BASE20 BASEI9 BASEIS a BASEI7 BASE16 BASE LOWER 06 IPbMEM b_BASE31 b BASE30 b 5 29 b BASE28 b BASE27 b BASE26 b BASE25 b BASE24 BASE UPPER 07 IPbMEM BASE23 b BASE22 b BASE21 b 5 20 b BASEI9 b 8 b BASEI7 b 5 16 BASE LOWER 08 5 5 30 BASE29 BASE28 c BASE27 5 26 BASE25 c BASE24 09 IP_cMEM
87. and a low level is detected on the SCC INT pin The 785230 provides the interrupt vector for the interrupt acknowledge cycle Table 3 3 SCC Device Addressing SCC Device Address Range Number MVME1X2P4 FFF45000 FFF453FF 0 Used FFF45400 FFF457FF 1 Not Used FFF45800 FFF45BFF 2 Not Used FFF45C00 FFF45FFF 3 Not Used The MC2 SCC interface had a bug that prevented direct access to the data register in the SCC device This has been remedied in the Petra ASIC Tick Timers The Petra MC2 chip implements four 32 bit tick timers These timers are identical to the timers in the VMEchip2 The timers run on a IMHz clock which is derived from the processor clock by a prescaler Each timer has a 32 bit counter a 32 bit compare register and a clear on compare enable bit The counter is readable and writable at any time The timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing There are two modes of operation for these timers free running and clear on compare In free running mode the timers have a resolution of 1 us and roll over after the count reaches the maximum value FFFFFFFF The terminal count period for the timers is 71 6 minutes When the counter is enabled in the clear on compare mode it increments every 1 us until the counter value matches the value in the compare register When a match occurs the counter is cleared
88. bus interface 1 9 2 9 VMEchip2 ASIC 1 5 block diagram 2 5 functional blocks 2 4 GCSR programming model 2 100 local BERR 1 42 programming model 2 20 VMEchip2 Petra chip redundancies 1 9 W watchdog timer Petra MC2 ASIC 3 9 VMEchip2 2 14 2 15 write post buffer 2 6 2 9 bus error interrupter VMEbus 2 19 enable bits 2 39 enabling 2 32 2 35 2 43 2 44 2 50 2 51 register 2 32 timer VMEchip2 ASIC 2 7 write posting VMEchip2 ASIC 2 6 2 9 write protect feature of Flash memory 3 2 Z Z85230 SCC interface 3 7 register addresses 1 31 IN 12 Computer Group Literature Center Web Site
89. bus usage when the IndustryPack is less than 32 bits wide the FIFO converts 8 bit and 16 bit IP transfers to 32 bit local bus transfers The FIFO data path logic also aligns data if the source and destination addresses are not aligned so the local bus and the IndustryPack can operate at their maximum data transfer sizes The FIFO also buffers enough data so that accesses to the local bus are in the burst mode Each DMAC also supports command chaining through the use of a singly linked list built in local not IP memory Each entry in the list includes an IP address a local bus address a byte count a control word and a pointer to the next entry When the command chaining mode is enabled the DMAC reads and executes commands from the list in local memory until all commands are executed Each DMAC can be programmed to generate an interrupt request when any specific table entry has completed when the byte count reaches 0 when an error condition occurs or when the DMAEND signal is asserted by the IndustryPack The DMA arbiter has two modes of operation One mode is to implement a round robin type of arbitration which guarantees equal access to the local bus The other method is to set the arbitration priority to one of four states In this case the priority is constant with one DMA channel having the highest priority and the other three having the second third and fourth highest priority Note that the IP specification supports a DMA
90. by software the counter reaches its terminal count When this occurs the WDTO status bit is set and if the local or SYSRESET function is enabled the selected reset is generated if the board fail function is enabled the board fail signal is generated http www motorola com computer literature 2 15 VMEchip2 VMEbus Interrupter The interrupter provides all the signals necessary to allow software to request interrupt service from a VMEbus interrupt handler The chip connects to all signals that a VMEbus interrupter is required to drive and monitor Requiring no external jumpers the chip provides the means for software to program the interrupter to request an interrupt on any one of the seven interrupt request lines In addition the chip controls the propagation of the acknowledge on the ACK daisy chain The interrupter operates in release on acknowledge ROAK mode An 8 bit control register provides software with the means to dynamically program the status ID information Upon reset this register is initialized to status ID of 0F the uninitialized vector in the 68K based environment The VMEbus interrupter has an additional feature not defined in the VMEbus specification The VMEchip2 supports a broadcast mode on the IRQI signal line When this feature is used the normal IRQI interrupt to the local bus interrupter should be disabled and the edge sensitive IRQ1 interrupt to the local bus interrupter should be enabled
91. bytes are the whole number of MHz and the second two bytes are fractions of MHz For example for a 60 00 MHz board this field contains 6000 6 Six bytes are reserved for the Ethernet address The address is stored in hexadecimal format Refer to the detailed description earlier in this chapter If the board does not support Ethernet this field is filled with zeros 7 These two bytes are reserved http www motorola com computer literature 1 37 Board Description and Memory Maps 8 Note 10 11 12 13 14 15 16 17 Two bytes are reserved for the local SCSI ID The SCSI ID is stored in ASCII format Eight bytes are reserved for the printed wiring board PWB number assigned to the memory mezzanine board in ASCII format Although no memory mezzanine is present on MVMEIX2P4 series boards the on board memory is modeled as such for backward compatibility The firmware fills this and other fields relating to memory mezzanines with an n a Eight bytes are reserved for the serial number assigned to the memory mezzanine board in ASCII format Eight bytes are reserved for the printed wiring board PW B number assigned to the serial port 2 personality board in ASCII format Static Memory Mezzanine PWB identifier in ASCII Static Memory Mezzanine serial number in ASCII Memory Mezzanine PWB identifier in ASCII Memory Mezzanine serial number in ASCII ECC2 Memory Mezz
92. c d ADR SIZ SFFFBCO090 94 98 9c BIT 23 0 abc23 abcO OPER R W R W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS Address F FFBCO090 selects Alternate DMA Byte Count register Address F FFBC094 selects Alternate DMA Byte Count register b Address F FFBCO98 selects Alternate DMA Byte Count register c Address F FFBCO9C selects Alternate DMA Byte Count register abc 23 0 Associated with each DMA Byte Count register is an Alternate DMA Byte Count register These registers are part of an IP2 bug fix which allows flushing of the FIFOs when the DMA end signal is detected on IP read operations This counter is set to 0 when the dmaend signal is detected A count of zero will have the effect of flushing the FIFOs manner similar to the condition where the byte counter reaches a terminal count of zero When the DMA end is detected the contents of the DMA Byte Count register will equal the initial byte count minus the number of bytes that were transferred to the local bus memory For all other cases the Alternate DMA Byte counter and the DMA Byte counter contain the same value These registers are presented in the register map for test purposes It is not anticipated that they will serve any purpose to application software http www motorola com computer literature 4 47 2 Functions Alternate DMA Control Register 2 a b c d ADR SIZ BIT 7 6
93. cycle will be write posted and the local bus will be acknowledged in two ticks If another bus cycle is initiated while the write post operation is in progress that cycle will be stalled until write posting is complete Bear in mind that memory bandwidth on MVME1X2P4 boards is higher than before For some memory architectures it has increased significantly Software will execute more quickly as a result Table 3 2 SDRAM Performance Memory States Access Type Idle Active Hit Active Miss Read Single 4 3 5 Read Burst 4 1 1 1 3 1 1 1 5 1 1 1 Write Burst 2 1 1 1 2 1 1 1 2 1 1 1 WR 2 WR 1 or 2 bytes 9 8 10 785230 SCC Interface The Petra MC2 chip supports as many as four Z85230 devices for serial communications control There is only Z85230 on the MVME1 X2P4 Refer to the Board Level Hardware Description in your Installation and Use manual for details The addresses for the devices are defined as shown in the following table Note that the General Control register at location FFF42000 contains CSR bits SSCIT lt 1 0 gt to control the delay time for the Z85230 IACK cycle The Petra MC2 provides a map decoder and an interrupt handler for the Zilog Z85230 The base address is FFF45000 The Petra MC2 requests an interrupt at the level programmed in the SCC interrupt control register if http www motorola com computer literature 3 7 MC2 Functions the interrupt is enabled
94. data that is in error Each MCECC sector segment performs this logging function independently of the other Once the MCECC sector has logged an error it does not log any new errors that occur until the ERRLOG control status bit has been cleared by software The MCECC sector contains programmable registers and circuitry to implement the memory scrubbing function Programmable registers determine how often the entire DRAM is scrubbed During a scrub the scrubber holds the memory for a programmable amount of time and then releases it for the local bus or for a refresher if one of them is requesting local bus mastership The scrubber then refrains from using the DRAM again for a programmable amount of time Each scrub cycle is made up of a full 39 bit read of DRAM a correction of any single bit errors and a write of the full 39 corrected bits back to the same location If a single or double bit error occurs and if such interrupts are enabled in the control register the local bus master is notified A software bit is available to disable the read portion of the scrub cycle The MCECC sector provides refresh control for the DRAM It performs a single CAS before RAS refresh cycle to the two DRAM blocks approximately once every 15 6 us 5 8 Computer Group Literature Center Web Site Functional Description Arbitration The MCECC sector has three different entities that can request use of the DRAM cycle controller 1 the local bus ma
95. fail interrupter is an edge sensitive interrupter connected to the VMEbus ACFAIL signal line This interrupter is filtered to remove the ACFAIL glitch which is related to the BBSY glitch The SYS fail interrupter is an edge sensitive interrupter connected to the VMEbus signal line The write post bus error interrupter is an edge sensitive interrupter connected to the local bus to VMEbus write post bus error signal line The VMEbus IRQI edge sensitive interrupter is an edge sensitive interrupter connected to the VMEbus IRQI signal line This interrupter is used when one of the tick timers is connected to the IRQ1 signal line When this interrupt is acknowledged the vector is provided by the VMEchip2 and a VMEbus interrupt acknowledge is not generated When this interrupt is enabled the VMEbus IRQ level sensitive interrupter should be disabled The VMEchip2 VMEbus interrupter acknowledge interrupter is an edge sensitive interrupter connected to the acknowledge output of the VMEbus interrupter An interrupt is generated when an interrupt on the VMEbus from VMEchip2 is acknowledged by a VMEbus interrupt handler The tick timer interrupters are edge sensitive interrupters connected to the output of the tick timers The DMAC interrupter is an edge sensitive interrupter connected to the DMAC The GCSR SIG3 0 interrupters are edge sensitive interrupters connected to the output of the signal bits in the GCSR The locat
96. generated on the local bus When this bit is high and the watchdog timer has timed out the VMEchip2 asserts the BRDFAIL signal pin When this bit is low the watchdog timer does not contribute to the BRDFAIL signal on the VMEchip2 When this status bit is high a watchdog time out has occurred When this status bit is low a watchdog time out has not occurred This bit is cleared by writing a 1 to the WDCS bit in this register When this bit is set high the watchdog counter is reset The counter must be reset within the time out period or a watchdog time out occurs http www motorola com computer literature 2 71 VMEchip2 WDCS SRST When this bit is set high the watchdog time out status bit WDTO bit in this register is cleared When this bitis set high a SYSRESET signal is generated on the VMEbus SYSRESET resets the VMEchip2 and clears this bit Tick Timer 2 Control Register ADR SIZ FFF40060 8 bits 7 used of 32 BIT 15 14 13 12 11 10 9 8 NAME OVF COVF COC EN OPER R C R W R W RESET 0 PS 0 PS 0 PS 0 PS EN When this bit is high the counter increments When this bit is low the counter does not increment COC When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when a 1 is written to this bit OVF These bits are the output of the overflow c
97. idle state SDRAM access time is a function of the state of the bank of memory being addressed If the bank addressed is active performance is additionally a function of the page of memory being referenced If the page referenced is open access time is the shortest possible Maximum access time will occur when the page referenced is not open since the open page must be first closed and the desired page then opened Page sizes are determined by the configuration of the SDRAM device Sizes range from 256 to 1024 memory locations per page The Petra MCECC sector design is targeted for SDRAM devices of the PC100 type Memory access time are not influenced by the settings of mode bits or SDRAM speed selections The basic performance specifications for the MCECC sector are listed in Table 5 2 http www motorola com computer literature 5 3 MCECC Functions Note The table is not complete because it cannot account for the effects of a write posting operation If the Petra MCECC sector is idle and a write cycle is initiated on the local bus the cycle is write posted and the local bus is acknowleged in two clock ticks If another bus cycle is initiated while the write post operation is in progress the new cycle is stalled until the write posting is complete The Read cycles are extended by one clock cycle if the NCEBEN bit is set in the SDRAM Control register Since the bandwidth between the SDRAM and the processor local bus is gen
98. interrupt SWS LEVEL These bits define the level of the software 5 interrupt Interrupt Level Register 3 bits 8 15 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME SW3 LEVEL SW2 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 2 interrupt and the software 3 interrupt SW2 LEVEL These bits define the level of the software 2 interrupt SW3 LEVEL These bits define the level of the software 3 interrupt Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 3 bits 0 7 ADR SIZ FFF40080 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0 NAME SW1 LEVEL SWO LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the software 0 interrupt and the software 1 interrupt SWO0 LEVEL These bits define the level of the software 0 interrupt SWILEVEL These bits define the level of the software 1 interrupt Interrupt Level Register 4 bits 24 31 ADR SIZ FFF40084 8 bits 6 used of 32 BIT 3l 30 29 28 27 26 25 24 SPARE LEVEL VIRQ7 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the VMEbus IRQ7 interrupt and the spare interrupt The VMEbus level 7 IRQ7 interrupt may be mapped to any local bus interrupt level VIRQ7 LEVEL These bits define the level
99. may be enabled for this segment using the write post enable bit The transfer size may be D16 or D32 as defined by the D16 bit in the control register The second I O map decoder provides support for the other I O map of the VMEbus This decoder maps the local bus address range F0000000 to FOFFFFFF to the A24 map of the VMEbus and the address range 1000000 to SFF7FFFFF to the A32 map of the VMEbus The transfer size is always D16 This segment may be enabled using the enable bit Write posting may be enabled using the write post enable bit The local bus map decoders should not be programmed such that more than one map decoder responds to the same local bus address or a map decoder conflicts with on board resources You may however program the map decoders to allow a VMEbus address to be accessed from more than one local bus address http www motorola com computer literature 2 39 VMEchip2 Local Bus Slave VMEbus Master Ending Address Register 1 ADR SIZ FFF40014 16 bits of 32 BIT 31 ses 16 NAME Ending Address Register 1 OPER R W RESET 0 PS This register is the ending address register for the first local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 1 ADR SIZ FFF40014 16 bits of 32 BIT 15 va 0 NAME Starting Address Register 1 OPER R W RESET 0 PS This register is the starting address register for the first local bus to
100. of certain ASICs used on first and second generation MVME162 172 series boards has ended The discontinued ASICs are the MC MC2 IP2 and MCECC chips The Petra chip was developed to replace these discontinued ASICs The Petra ASIC is functionally compatible with each of the components that it replaces In cases where functionality between ASICs is exclusive configuration switches or jumpers are provided to let you select the desired functionality For instance the MC and MC2 chips differed in their implementation of Flash write protection Boards built with the Petra ASIC accordingly have a configuration switch so that you can determine which method to use In several areas of functionality the configuration switches provide backward compatibility with earlier MVME162 172 implementations but their settings can be overridden in software if desired A R W by the corresponding register table entry denotes instances where this capability is present Where the older technology supported fast page or EDO DRAM chips the Petra memory controllers support SDRAM devices The two memory controllers modeled in Petra duplicate the functionality of the parity memory controller found in the MC ASICs as well as that of the single bit error correcting double bit error detecting memory controller found in the MCECC ASICS see Figure 1 1 1 2 Computer Group Literature Center Web Site Overview line with th
101. of the VMEbus IRQ7 interrupt SPARE LEVEL Not used on the MVMEIX2PA http www motorola com computer literature 2 93 VMEchip2 Interrupt Level Register 4 bits 16 23 ADR SIZ FFF40084 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME VIRQ6 5 LEVEL OPER R W R W RESET 0 PSL 0 PSL Interrupt Level Register 4 bits 8 15 This register is used to define the level of the VMEbus level 5 1 5 interrupt and the VMEbus level 6 IRQ6 interrupt The 5 and interrupts may be mapped to any local bus interrupt level 5 LEVEL These bits define the level of the VMEbus IRQ 5 interrupt VIRQ6 LEVEL These bits define the level of the VMEbus IRQ6 interrupt ADR SIZ FFF40084 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME VIRQ4 VIRQ3 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the VMEbus level 3 interrupt and the VMEbus level 4 IRQ4 interrupt The IRQ3 and IRQ4 interrupts may be mapped to any local bus interrupt level VIRQ3 LEVEL These bits define the level of the VMEbus IRQ3 interrupt VIRQ4 LEVEL These bits define the level of the VMEbus IRQ4 interrupt Computer Group Literature Center Web Site LCSR Programming Model Interrupt Level Register 4 bits 0 7 ADR SIZ FFF40084 8 bits 6 used of 32 BIT 7 6 5 4 3 2 1 0
102. parts or perform any unauthorized modification of the equipment Contact your local Motorola representative for service and repair to ensure that all safety features are maintained Observe Warnings in Manual Warnings such as the example below precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment caution when handling testing and adjusting this equipment and its Warning components prevent serious injury death from dangerous voltages use extreme Flammability All Motorola PWBs printed wiring boards are manufactured with a flammability rating of 94V 0 by UL recognized manufacturers Caution EMI Caution This equipment generates uses and can radiate electromagnetic energy It may cause or be susceptible to electromagnetic interference EMI if not installed and used with adequate EMI protection Lithium Battery Caution This product contains a lithium battery to power the clock and calendar circuitry Caution Attention Vorsicht Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Il y a danger d explosion s il y a remplacem
103. priority 3 14 vectors 1 40 Interrupt Acknowledge map 1 39 interrupt handler VMEchip2 ASIC 2 18 interrupter acknowledge interrupter VMEbus 2 19 interrupter control VMEbus 2 61 interrupts broadcast 2 15 2 16 edge sensitive VMEchip2 ASIC 2 74 hardware vectored 1 40 how to use B 1 masked 2 96 Petra IP2 chip 4 9 IP to local bus data routing 4 56 IP2 functions overall memory map 1 24 IP2 sector Alternate DMA Byte Count register 4 47 Chip ID register 4 18 Chip Revision register 4 18 Arbitration Control register 4 29 DMA Byte counter 4 43 DMA Control Register 1 4 38 DMA Control Register 2 4 40 DMA Enable register 4 37 IndustryPack Address counter 4 42 Interrupt Control register 4 36 DMA Local Bus Address counter 4 42 DMA Status register 4 35 DMA Table Address counter 4 43 features 4 1 functional description 4 3 General Control registers 4 24 IP Clock register 4 28 IP RESET register 4 30 IP to local bus data routing 4 56 IRQO IRQ Interrupt Control registers 4 23 Memory Base Address registers 4 20 Memory Size registers 4 22 overall memory map 4 10 Programmable Clock General Control register 4 45 Programmable Clock Interrupt Control register 4 44 Programmable Clock Timer register 4 46 programming model 4 11 snoop control 4 4 4 31 Vector Base register 4 19 IRQI interrupter VMEbus 2 19 IRQ7 1 interrupters VMEbus 2 19 http www motorola com computer literature IN 5 lt moz xXmoz
104. register or the name of the bits in the register The operations possible on the register bits defined as follows R This bit is a read only status bit R W This bit is readable and writable S R Writing a to this bit sets it Reading it returns its current status The state of the bit following a reset defined as follows This bit is affected by power up reset The bit is affected by SYSRESET The bit is affected by local bus reset The bit is not affected by reset 2 102 Computer Group Literature Center Web Site GCSR Programming Model Table 2 5 shows a summary of the GCSR Table 2 5 VMEchip2 Memory Map GCSR Summary VMEchip2 GCSR Base Address FFF40100 Offsets Bit Numbers Loca E lBus 15 14 13 12 11 10 9 8 7 6 5 4 53 2110 bus 0 0 Chip Revision Chip ID 2 4 s st st st Rs Is B sco sysF XI X X 3 2 1 0 T F F NIL 4 8 General Purpose Control and Status Register 0 6 General Purpose Control and Status Register 1 8 10 General Purpose Control and Status Register 2 A 14 General Purpose Control and Status Register 3 18 General Purpose Control and Status Register 4 E General Purpose Control and Status Register 5 VMEchip2 Revision Register ADR SIZ Local Bus FFF40100 VMEbus XXYO 8 bits BI
105. selected with a board level configuration switch S5 segment 4 BBRAM Interface The Petra MC2 chip supports read write access to the BBRAM by any bus master on the MC680x0 bus The BBRAM interface operates identically to the Flash in that it performs dynamic sizing for accesses to the 8 bit BBRAM to make it appear contiguous This feature allows code to be executable from the BBRAM Burst accesses to Flash EPROM are inhibited by the interface so that they are broken into four longword accesses The BBRAM device access time must be no greater than 5 BCLK periods in fast mode or 9 BCLK periods in slow mode The BBRAM speed option is controlled by control bit 8 in the General Control register at address FFF42000 in the Petra MC2 chip 82596CA LAN Interface The LAN controller interface is described in the following sections MPU Port and MPU Channel Attention The Petra MC2 chip allows the MC680x0 bus master to communicate directly with the Intel 82596CA LAN Coprocessor by providing a map decoder and required control and timing logic Two types of direct access are feasible with the 82596CA MPU Port and MPU Attention MPU Port access enables the MPU to write to an internal 32 bit 82596CA command register This allows the MPU to do four things 1 Write an alternate System Configuration Pointer address 2 Write an alternative dump area pointer and perform a dump 3 Execute a software reset 4 Execute a self test http www m
106. set the programmable clock output is asserted for one BCK period When PLS is cleared the programmable clock output toggles creating a square wave PLTY PLTY controls the polarity of the programmable clock output When PLTY is cleared the negated and cleared state of the output is a logic 0 and the asserted state is a logic 1 When PLTY is set the opposite is true Programmable Clock Timer Register ADR SIZ FFFBC082 16 bits BIT 15 2 0 Programmable Clock Timer Register OPER R W RESET OR When enabled the programmable clock timer counter increments until it matches the value contained in this register at which time it rolls over and resumes counting The effect is that the frequency of the programmable clock output is the frequency of the pre scaler output the value in this register 1 For example if the PLS bit is cleared PLS2 0 are 000 and the timer register contains 0001 then the programmable clock output frequency is BCK 4 8MHz if BCK 32MHz For the pulsed output the formula for the period of the frequency of the recurring pulse is 1 pre scaler output the value in this register 1 For example if the PLS bit is set PLS2 0 are 001 and the timer register contains 0001 then the programmable clock frequency of the pulsed output is BCK 4 8MHz if BCK 32MHz 4 46 Computer Group Literature Center Web Site Programming Model Alternate DMA Byte Count a b
107. signals 31 16 respectively The IP2 sector can address the IndustryPacks only at even multiples of their size Consequently any bits that are set within SIZE23 SIZE16 mask the value programmed into BASE23 BASE16 respectively Masked bits always compare regardless of the value of the corresponding address bit For example if a_SIZE16 were set then the MC680x0 address signal A16 would not affect comparisons for accesses to IP a memory space This would allow the base address for IP a to be programmed for one of 00000000 00020000 800040000 00060000 etc If both a SIZE16 and a_SIZE17 were set then the base address for IP a could be programmed for one of 00000000 00040000 00080000 000C0000 etc Note Memory Bases for any registers among IP a b IP c or d that are enabled should be programmed not to overlap each other IP a or Double Size IP ab Memory Base Address Registers ADR SIZ 004 and FFFBCOO05 8 bits each BIT 7 6 5 4 3 2 1 0 0 4 5 BAS a 1 0 9 8 7 6 5 4 05 3 2 1 0 9 8 7 6 R W R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR 4 20 Computer Group Literature Center We
108. the descriptions here also apply to the control word in the command packet VME AM These bits define the address modifier codes the DMAC drives on the VMEbus when it is bus master During non block transfer cycles bits 0 5 define the VMEbus address modifiers During block transfers bits 2 5 define 2 58 Computer Group Literature Center Web Site LCSR Programming Model VMEbus address modifier bits 2 5 and address modifier bits 0 and 1 are provided by the DMAC to indicate a block transfer Block transfer mode should not be set in the address modifier codes The special block transfer bits should be set to enable block transfers If non block cycles are required to reach a 32 or 64 bit boundary bits 0 and 1 are used during these cycles BLK These bits control the block transfer modes of the DMAC 0 Block transfers disabled 1 The DMAC executes D32 block transfer cycles on the VMEbus In block transfer mode the DMAC may execute byte and two byte cycles at the beginning and ending of a transfer in non block transfer mode If the D16 bit is set the DMAC executes D16 block transfers 2 Block transfers disabled 3 The DMAC executes D64 block transfer cycles on the VMEbus In block transfer mode the DMAC may execute byte two byte and four byte cycles at the beginning and ending of a transfer in non block transfer mode If the D16 bit is set the DMAC executes D16 block transfers DMAC Local Bus Address Counter
109. the processor as well as for the subsequent values which are loaded by the command chaining logic If they are not set to 0 the command chaining process will halt 4 32 Computer Group Literature Center Web Site Programming Model A command packet includes a control word that defines Single command interrupt enable DMA transfer direction Q IndustryPack data width sDMA or aDMA selection DMAEND direction and usage The format of the control word is the same as that of control register 2 The command packet also includes a local bus address an IP address a byte count and a pointer to the next command packet in the list The end of a command is indicated by setting bit 0 or 1 of the next command address The command packet format is shown in the following table Entry Function 0 Address of Next Command Packet 1 Local Bus Address 2 Control Word Byte Count 3 1 IndustryPack Address DMA d http www motorola com computer literature 4 33 2 Functions DMA Enable Function There are certain DMA channel contexts which are illegal If an attempt is made to program the DMA control register 1 for each channel a and b or c and d to an illegal state the DEN DMA enable control bit will not set toa 1 when it is loaded via a processor store instruction This condition can be tested by writing a 1 to the DEN bit and reading a 0 Refer to the descript
110. this bit is low INT This bit reflects the state of the INT pin from the Z85230 controller qualified by the bit When this bit is high an SCC controller interrupt is being generated at the level programmed in IL2 ILO When the interrupt is cleared in the 785230 INT returns to 0 Computer Group Literature Center Web Site Programming Model Tick Timer 3 and 4 Control Registers Tick Timer 4 Control Register ADR SIZ FFF4201C 8 bits BIT 15 14 13 12 11 10 9 8 NAME OVF3 OVF2 1 OVFO R R R R R R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 0 PL 0 PL Tick Timer 3 Control Register ADR SIZ FFF4201C 8 bits BIT 7 6 5 4 3 2 1 0 NAME OVF3 OVF2 OVFI OVFO COVF COC CEN OPER R R R R R R W R W RESET OPL OPL OPL OPL 0 0 PL 0 PL CEN When this bit is high the counter increments When this bit is low the counter does not increment COC When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when 1 is written to this bit OVF3 OVF0 These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to
111. use an Intel 28F160S5 The Flash and EPROM memory map locations can be swapped based upon the setting of a configuration switch 54 pin 5 line GPI3 input to the initialization PAL The initialization device was discussed in the previous section This enables the MVMEIX2PA to execute reset code from either the EPROM or Flash The Petra MC2 chip executes multiple cycles to the eight bit Flash EPROM devices so that byte word or longword accesses are allowed Burst accesses to Flash EPROM are inhibited by the interface so that they are broken into four longword accesses The Petra MC2 chip supports write cycles to EPROM memory space with a normal cycle termination by asserting transfer acknowledge Data is not changed The Petra MC2 chip allows the write cycle to time out The Flash memory has a number of write protect features A CSR bit in the Flash Parameter register FWEN bit 11 inhibits write cycles to Flash There is also a jumper J24 that will inhibit writes to Flash refer to your MVME162P4 or MVME172P4 Installation and Use manual for details 3 2 Computer Group Literature Center Web Site Functional Description The Petra ASIC also supports the MCI ASIC s method of Flash write enable This method puts Flash memory in write enable mode by referencing the BBRAM at locations F FFCCO00 FFFCFFFF Conversely the Flash can be write protected by referencing the BBRAM at locations F FFC8000 F FFCBFFF The MCI mode is
112. vector generation found in the Petra MC2 chip The Z85230 also supports a scheme where the base register value is changed based upon the interrupt requested Programming the Tick Timers There are four programmable tick timers in the Petra MC2 chip These timers are identical in function to the timers implemented in the PCCchip2 and the VMEchip2 Tick Timer 1 and 2 Compare and Counter Registers The Tick Timer Counter is compared to the Compare register When they are equal an interrupt is sent to the local bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to calculate the compare register value for a specific period T T us Compare Register When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected The rollover time for the counter is 71 6 minutes The Tick Timer Counter when enabled increments every microsecond Software may read or write the counter at any time http www motorola com computer literature 3 15 MC2 Functions Tick Timer 1 Compare Register ADR SIZ FFF42004 32 bits BIT 31 0 NAME Tick Timer 1 Comp
113. which can operate in the SDMA or aDMA mode The DMA controllers can be configured so one controller is attached to each of the four possible IndustryPack interfaces or so that DMA controllers a and b are attached to IP a and controllers c and d are attached to IP c The DMA controllers support 8 16 and 32 bit IndustryPack widths The four DMA channels can operate concurrently Each DMA controller has a 32 bit local address counter a 32 bit table address counter a 24 bit byte counter control registers status registers and a 24 bit IP address counter The data path for each DMA controller passes through a FIFO which is eight locations deep and four bytes wide sDMA transfers and byte count parameters must accommodate the I O port width If the port width is 16 bits then the byte count must be initialized to an even value if the width is 32 bits then the byte count must be set to a value which is a multiple of four This implies that transfer to I O space 4 4 Computer Group Literature Center Web Site Functional Description under DMA control will always be the same size as the port width The IP address register must be initialized to 0 before sDMA is enabled This counter is used to align data in the IP2 sector The data has no alignment restrictions as it is moved to or from the memory on the local bus This would typically be DRAM on the MC680x0 local bus but it could also be memory on the VMEbus To optimize local
114. 0 0 0 0 0 SAC26 SAC25 SAC24 ADDR CNTR 50 SCRUB SAC23 SAC22 SAC21 SAC20 5 19 18 SACI7 SAC16 ADDR CNTR 54 SCRUB 15 14 SACI3 SACI2 SACIO SACO 8 ADDR CNTR 58 SCRUB SAC7 SAC6 SACS SAC4 07 0 0 0 ADDR CNTR 5C ERROR ERRLO ERD ESCRB ERA EALT 0 MBE SBE LOGGER G 60 ERROR EA31 EA30 EA29 EA28 EA27 EA26 EA25 EA24 ADDRESS 64 ERROR EA23 EA22 EA21 EA20 19 18 EA17 EA16 ADDRESS 68 ERROR 15 14 EA13 EA12 11 10 9 8 ADDRESS 6C ERROR EA7 EA6 EAS EA4 07 0 0 0 ADDRESS 70 ERROR S7 S6 55 54 53 52 51 50 SYNDROME 74 DEFAULTS RWB7 RWB6 FSTRD SELII SELIO RSIZ2 RSIZ1 RSIZO 78 DEFAULTS2 RWB7 REFDIS NOCACHE RESST2 RESST1 RESSTO 7C SDRAM SDCFG2 SDCFGI SDCFG0 CONFIG 5 12 Computer Group Literature Center Web Site Programming Model Chip ID Register The Chip ID register is hard wired to a hexadecimal value of 87 The Petra MCECC sector can be given a software reset by writing a value of OF to this register This write is terminated properly with TA and sets most internal registers to their default power up state Although writes of any value other than 0F to this register are ignored the MCECC sector always terminates the cycles properly with TA ADR SIZ 1st FFF43000 2nd FFF43100 8 bits BIT 31 30 29 28 27 26 25 24 NAME CID7 CID6 5 CID4 CID3 CID2 CID1 CIDO OPER
115. 0 19 18 17 16 NAME TIME OFF TIME ON VGTO OPER R W R W R W RESET OPS OPS OPS This register controls the DMAC time off timer the DMAC time on timer and the VMEbus global time out timer VGTO TIME ON TIME OFF These bits define the VMEbus global time out value When DSO or 051 is asserted on the VMEbus the timer begins timing If the timer times out before the data strobes are removed a BERR signal is sent to the VMEbus The global time out timer is disabled when the VMEchip 2 is not system controller These bits define the maximum time the DMAC spends 256 Us 512 us 1024 us When done or no data These bits define the minimum time the DMAC spends 0 8 us 1 64 us 2 256 Us 3 The timer is disabled on the VMEbus 0 16 us 4 1 32 us 5 2 64 us 6 3 128 us 7 off the VMEbus 0 0 us 4 1 16 us 5 2 32 us 6 3 64 us 7 128 us 256 Us 512 us 1024 us http www motorola com computer literature 2 65 VMEchip2 VME Access Local Bus and Watchdog Time out Control Register ADR SIZ FFF4004C 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME VATO LBTO WDTO OPER R W R W R W RESET 0 PS 0 PS 0 PS WDTO These bits define the watchdog time out period Bit Encoding Time out Bit Encoding Time out 0 512 us 8 128 ms 1 1 028 9 256 ms 2 2 10 512 105 3 4 1 11 11 4 8 ms 12 418 5 16 m
116. 0 for the MCECC sector on the second mezzanine board Note that several bits in the register map have changed in functionality from the MCECC ASIC pair In most cases these bits were defined to be nonoperational in the MCECC model but were also defined as to their original intent This specification entirely omits those bit definitions The possible operations for each bit in the CSR are as follows R R W R C The bit is a read only status bit The bit is readable and writable The status bit is cleared by writing a to it Writing a 0 to the bit clears it or another bit This bit reads 0 Writing a 1 to the bit sets it or another bit This bit reads 0 The possible states of the bits after local reset software reset and power up reset are as defined below P L S The bit is affected by power up reset The bit is affected by local reset The bit is affected by software reset writing 0F to the Chip ID register The bit is not affected by reset The effect of reset on this bit is variable Computer Group Literature Center Web Site Programming Model Table 5 3 MCECC Sector Internal Register Memory Map MCECC Sector Base Address FFF43000 first board FFF43100 second board Register Register Bit Names Offset Name D31 D30 D29 D28 D27 D26 025 024 00 CHIP ID CID7 CID6 5 CID4 CID3 CID2 CID1 CID
117. 1 interrupt TICK2 LEVEL These bits define the level of the tick timer 2 interrupt Interrupt Level Register 2 bits 24 31 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 31 30 29 28 27 26 25 24 VIA LEVEL DMA LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the DMA controller interrupt and the VMEbus acknowledge interrupt DMA LEVEL These bits define the level of the DMA controller interrupt VIA LEVEL These bits define the level of the VMEbus interrupter acknowledge interrupt http www motorola com computer literature 2 89 VMEchip2 Interrupt Level Register 2 bits 16 23 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME SIG3 LEVEL SIG2 LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the GCSR SIG2 interrupt and the GCSR SIG3 interrupt SIG2 LEVEL These bits define the level of the GCSR SIG2 interrupt SIG3 LEVEL These bits define the level of the GCSR SIG3 interrupt Interrupt Level Register 2 bits 8 15 ADR SIZ FFF4007C 8 bits 6 used of 32 BIT 15 14 13 12 11 10 9 8 NAME 5 LEVEL SIGO LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the GCSR SIGO interrupt and the SIGI1 interrupt SIGO LEVEL These bits define the level of GCSR SIGO interrupt
118. 11 10 9 IPA8 ADDR 47 DMA_b IP 7 5 4 IPA2 IPAI IPAO ADDR 48 DMA b 0 0 0 0 0 0 0 0 BYTE CNT 49 DMA b BCNT23 BCNT22 BCNT21 BCNT20 BCNT19 8 BCNTI7 BCNTI6 BYTE CNT 4A DMA b BCNTI5 BCNT14 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 8 4B DMA_b BCNT7 BCNT6 5 BCNT4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 4C DMA b TBL TA3I TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADDR 4D DMA_b TBL TA23 TA22 TA21 TA20 19 18 17 16 ADDR 4E DMA_b TBL 15 14 13 12 TAI 10 9 8 ADDR 54 DMA_b TBL 7 6 5 4 TA2 TAI TAO ADDR 2592 9908 3 6 http www motorola com computer literature 1 27 Board Description and Memory Maps Table 1 8 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address Register Register Register Bit Names Offset Name D7 D6 05 04 D3 D2 D1 DO DMAC for IndustryPack c request 0 This register set is referred to as in the text 50 DMA c 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 51 DMA cINT 0 0 DINT DIEN DICLR DIL2 DILI DILO CTRL 52 DMA 0 0 0 0 0 0 0 DEN ENABLE 53 RESERVED 0 0 0 0 0 0 0 0 54 DMA c DHALT 0 DTBL ADMA WIDTHI WIDTHO 0 XXX CONTROL 1 55 DMA c INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 56 RESERVED 0 0 0 0 0 0 0 0 57 RESERVED 0 0
119. 16 four byte deep read ahead pipeline When responding to a block read cycle the chip performs block read cycles on the local bus to keep the FIFO buffer full Data for subsequent transfers is then retrieved from the on chip buffer significantly improving the response time of the slave in block transfer mode The VMEchip2 includes an on chip map decoder that allows software to configure the global addressing range of onboard resources The decoder allows the local address range to be partitioned into two separate banks each with its own start and end address in increments of 64KB as well as setting each bank s address modifier codes write post enable and snoop enable http www motorola com computer literature 2 9 VMEchip2 Each map decoder includes an alternate address register and an alternate address select register These registers allow any or all of the upper 16 VMEbus address lines to be replaced by signals from the alternate address register This allows the address of local resources to differ from their VMEbus address The alternate address register also provides the upper eight bits of the local address when the VMEbus slave cycle is A24 The local bus master requests the local bus and executes cycles as required To reduce local bus loading and improve performance it always attempts to transfer data using a burst transfer as defined by the MC680x0 When snooping is enabled the local bus master requests the cache
120. 2 21 20 19 18 17 16 ARB VME DMA DMA BGTO 4C EN TIME OFF TIME ON 50 1 54 TICK TIMER 1 58 TICK TIMER 2 5 2 SCON sys BRD PURS CLR BRD RST sys WD WD WD TO WD WD WD 60 FAIL FAIL STAT PURS FAIL SW RST CLR CLR TO BF SRST RST STAT STAT OUT EN TO CNT STAT EN LRST EN EN 64 PRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AC SYS MWP TIC2 VME DMA 963 962 961 5160 LMO 68 FAIL IRQ FAIL IRQ IRQ IRQ IRQ IACK IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN 6C IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 70 CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR 74 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 78 FAIL ABORT SYS FAIL MST WP ERROR IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IACK DMA SIG 3 SIG 2 7C IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 80 sw7 SW6 SW5 sw4 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 84 IRQ7 VME IRQ 6 VME IRQ 5 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL T VECTOR BASE VECTOR BASE d S D ABORT GPIOEN REGISTER 0 REGISTER 1 EN C
121. 2 Counter OPER R W RESET OP This is the tick timer 2 counter When enabled it increments every microsecond Software may read or write the counter at any time http www motorola com computer literature 2 69 VMEchip2 Board Control Register ADR SIZ BIT 31 FFF40060 8 bits 7 used of 32 29 28 27 26 25 24 NAME SCON SFFL BRFLI PURS CPURS BDFLO RSWE OPER R R R R W R W RESET X 1 PSL OPS 1 PSL 1P RSWE BDFLO CPURS PURS BRFLI SFFL SCON The RESET switch enable bit is used with the no VMEbus interface option This bit is duplicated at the same bit position in the MC2 chip at location FFF42044 When this bit or the duplicate bit in the MC2 chip is high the RESET switch is enabled When both bits are low the RESET switch is disabled When this bit is high the VMEchip2 asserts the BRDFAIL signal pin When this bit is low this bit does not contribute to the BRDFAIL signal on the VMEchip2 When this bit is set high the powerup reset status bit is cleared This bit is always read 0 This bit is set by a powerup reset It is cleared by a write to the CPURS bit When this status bit is high the BRDFAIL signal pin on the VMEchip2 is asserted When this status bit is low the BRDFAIL signal on the VMEchip2 is not asserted The BRDFAIL pin may be asserted by an external device the BDFLO bit in this regist
122. 2 bits Byte reads should be used to read the interrupt vector This area returns no acknowledge signal If the local bus timer is enabled the access times out and is terminated by a TEA signal Size is approximate Port commands to the 82596CA must be written as two 16 bit writes upper word first and lower word second Ifthe MCI Flash write enable mode is set a memory map reference to these areas has the added functionality of enable disable Flash write protect A board configuration switch S5 pin 4 sets the MCI mode Computer Group Literature Center Web Site Detailed I O Memory Maps Tables 1 5 through 1 14 give the detailed memory maps for VMEchip2 functions Petra chip IP2 functions Petra chip IP2 Control and Status registers Petra chip Z85230 SCC register addresses 82596CA Ethernet LAN chip 53C710 SCSI chip M48T58 BBRAM TOD clock BBRAM configuration area TOD clock Table 1 5 Table 1 6 Table 1 7 Table 1 8 Table 1 9 Table 1 10 Table 1 11 Table 1 12 Table 1 13 Table 1 14 You can obtain manufacturers errata sheets for the various chips listed above by contacting your local Motorola sales representative A non disclosure agreement may be necessary http www motorola com computer literature Board Description and Memory Maps Table 1 5 VMEchip2 Memory Map Sheet 1 of 3 VMEchip2 LCSR Base Address FFF40000
123. 2 shows a summary of the LCSRs http www motorola com computer literature 2 21 VMEchip2 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 VMEchip2 LCSR Base Address FFF40000 OFFSET T 0 SLAVE ENDING ADDRESS 1 4 SLAVE ENDING ADDRESS 2 8 SLAVE ADDRESS TRANSLATION ADDRESS 1 SLAVE ADDRESS TRANSLATION ADDRESS 2 ADDER SNP WP SUP USR A32 A24 e BLK PRGM DATA I 2 s 2 2 2 s 14 MASTER ENDING ADDRESS 1 18 MASTER ENDING ADDRESS 2 1C MASTER ENDING ADDRESS 3 20 MASTER ENDING ADDRESS 4 24 MASTER ADDRESS TRANSLATION ADDRESS 4 MAST MAST MAST MAST 28 016 WP MASTER AM 4 016 WP MASTER AM 3 EN EN EN EN GCSR MAST MAST MAST MAST 2C GCSR GROUP SELECT BOARD SELECT a 2 31 30 29 25 24 23 22 21 20 19 18 17 16 WAIT ROM DMA TB SRAM 30 RMW ZERO SNP MODE SPEED 34 38 DMA CONTROLLER 3C DMA CONTROLLER 40 DMA CONTROLLER 44 DMA CONTROLLER TICK TICK CLR IRQ VMEBUS 48 EE ME INTERRUPT VMEBUS INTERRUPT VECTOR LEVEL This sheet continues on facing page 2 22 Computer Group Literature Center Web Site LCSR Programming Model 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SLAVE STARTING ADDRESS 1 SLAVE STARTING ADDRESS 2 SLAVE ADDRESS TRANSLATION SELECT 1 SLAVE ADDRESS TRANSLATION SELECT 2 ADDER SNP WP SUP usr 2 aza
124. 3 EN4 When this bit is high the first local bus to VMEbus map decoder is enabled When this bit is low the first local bus to VMEbus map decoder is disabled When this bit is high the second local bus to VMEbus map decoder is enabled When this bit is low the second local bus to VMEbus map decoder is disabled When this bit is high the third local bus to VMEbus map decoder is enabled When this bit is low the third local bus to VMEbus map decoder is disabled When this bit is high the fourth local bus to VMEbus map decoder is enabled When this bit is low the fourth local bus to VMEbus map decoder is disabled http www motorola com computer literature 2 49 VMEchip2 Local Bus to VMEbus I O Control Register ADR SIZ FFF4002C 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME 2 I2WP 1259 I2PD I1D16 1150 R W R W R W R W R W R W R W R W RESET 0PSL 0 PS O PS 0 PS 0 PS O PS 0 PS O PS This register controls the VMEbus short I O map and the F page F0000000 through FF7FFFFF map TISU I1D16 I2PD DSU When this bit is high the VMEchip2 drives a supervisor address modifier code when the short I O space is accessed When this bit is low the VMEchip2 drives a user address modifier code when the short I O space is accessed When this bit is high write posting is enabled to the VMEbus short I O segment
125. 3 U updates from previous boards 1 user access cycles VMEbus 2 34 2 37 using bus timers 1 50 V V11 control bit Petra MC2 chip 3 33 vector base registers VMEchip2 ASIC 2 74 VME LED 2 99 VMEbus access time out 1 42 access time out value DMAC 2 66 address counter DMAC 2 60 BBSY signal 2 98 BERR signal 1 42 capabilities 2 4 2 9 2 11 interface 1 7 interrupter function VMEchip2 ASIC 2 16 interrupter programming 2 51 IRQ1 IRQ2 interrupts 2 95 mapping 1 39 maps creating 2 6 master bus sizing and 2 6 request level DMAC 2 54 2 55 requester DMAC 2 13 segment size translating 2 30 slave 2 9 slave map decoders 2 26 slave map decoders programming 2 26 system controller function 2 17 timer 2 18 VMEbus Slave registers Address Modifier Select Register 1 2 36 Address Modifier Select Register 2 2 33 Address Translation Address Offset Register 1 2 29 Address Translation Address Offset Register 2 2 31 Address Translation Select Register 1 2 30 Address Translation Select Register 2 2 31 Ending Address Register 1 2 28 Ending Address Register 2 2 29 GCSR Board Address Register 2 48 GCSR Group Address Register 2 47 Starting Address Register 1 2 28 Starting Address Register 2 2 29 http www motorola com computer literature IN 11 lt moz lt moz Index VMEbus Slave registers continued Write Post and Snoop Control Register 1 2 35 Write Post and Snoop Control Register 2 2 32 VMEbus to local
126. 3 39 functional description 3 2 General Control register 3 12 General Purpose Inputs register 3 33 ID register 3 12 Interrupt Vector Base register 3 13 LANC Bus Error Interrupt Control register 3 31 LANC Error Status register 3 29 LANC Interrupt Control register 3 30 LSB Prescaler Count register 3 17 MPU Status register 3 46 Prescaler Clock Adjust register 3 17 Prescaler Count register 3 47 registers 3 10 RESET Switch Control register 3 41 Revision register 3 12 SCC Interrupt Control register 3 22 SCSI Error Status register 3 32 SDRAM Control register 3 44 SRAM Space Base Address register 3 25 SRAM Space Size register 3 28 Tick Timer 1 and 2 Compare and Counter registers 3 15 Tick Timer 1 and 2 Control registers 3 18 Tick Timer 3 and 4 Compare and Counter registers 3 36 Tick Timer Interrupt Control registers 3 19 Watchdog Timer Control register 3 42 MC680x0 processor indivisible cycles 1 51 indivisible RMW memory accesses 1 51 MCECC chip Memory Controller ASIC see Petra ASIC MCECC functions 1 5 MCECC functions 5 1 memory model additional functionality 3 25 MCECC sector arbitration 5 9 Base Address register 5 15 BCLK Frequency register 5 16 Chip ID register 5 13 Chip Prescaler counter 5 21 Chip Revision register 5 13 Data Control register 5 17 http www motorola com computer literature IN 7 lt moz xXmoz Index MCECC sector continued Defaults register 1 5 30 Defaults register 2 5 32 DRAM
127. 31 30 29 28 27 26 25 24 SAC23 SAC22 SAC21 5 20 SACI9 SACI8 SACI7 5 6 OPER R W R W R W R W R W R W R W RESET OPLS 8 OPLS OPLS OPLS OPLS OPLS OPLS Scrub Address Counter Bits 15 8 This register reflects the current value in the Scrub Address counter bits 15 8 ADR SIZ 1st FFF43054 2nd FFF43154 8 bits BIT 31 30 29 28 27 26 25 24 SACI5 SACIA SACI3 SACI2 SACII SACIO SACO SAC8 OPER R W R W R W R W R W R W R W RESET OPLS 8 OPLS OPLS OPLS OPLS OPLS OPLS Scrub Address Counter Bits 7 4 This register reflects the current value in the Scrub Address counter bits 7 4 ADR SIZ 1st FFF43058 2nd FFF43158 8 bits BIT 31 30 29 28 27 26 25 24 5 7 SAC6 5 5 5 4 0 0 0 0 OPER R W R W R W R R R R OPLS 8 OPLS OPLS X X X X 5 26 Computer Group Literature Center Web Site Programming Model Error Logger Register ADR SIZ BIT 1st FFF4305C 2nd FFF4315C 8 bits 31 30 29 28 27 26 25 24 NAME ERRLOG ERD 5 ERA EALT 0 MBE SBE OPER R C R R R R R R R RESET 0 PLS 0 PLS 0 PLS OPLS OPLS X OPLS SBE MBE ERA EALT ESCRB ERD ERRLOG SINGLE BIT ERROR
128. 4 D3 D2 D1 DO DMAC for IndustryPack d request 0 or for IndustryPack c request 1 and for PACER CLOCK This register set not including the Pacer Clock is referred to as in the text 68 DMA_d 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 69 DMA_d INT 0 0 DINT DIEN DICLR DIL2 DILO CTRL 56 DMA 0 0 0 0 0 0 0 ENABLE 6B RESERVED 0 0 0 0 0 0 0 0 56 DMA_d DHALT 0 DTBL ADMA WIDTHI WIDTHO C CHI XXX CONTROL 1 6D DMA d INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 56 RESERVED 0 0 0 0 0 0 0 0 6F RESERVED 0 0 0 0 0 0 0 0 70 DMA_dLB LBA3I LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 71 DMA_dLB LBA23 LBA22 LBA21 LBA20 LBAI9 LBAI18 LBAI7 LBAI6 ADDR 72 DMA dLB 15 14 LBAI2 10 LBA8 ADDR 73 DMA_dLB LBA7 LBA6 5 LBA4 LBA3 LBA2 LBAI LBAO ADDR 74 DMA_d IP 0 0 0 0 0 0 0 0 ADDR 75 DMA_d IP 23 22 21 20 19 18 17 16 ADDR 76 DMA 15 14 IPA13 IPA12 10 IPA9 IPA8 ADDR 77 DMA IPA7 IPA6 IPAS 4 IPA2 IPAI IPAO ADDR 78 DMA d 0 0 0 0 0 0 0 0 BYTE CNT 79 DMA d BCNT23 BCNT22 BCNT21 BCNT20 BCNTI9 BCNT18 BCNT17 BCNTI6 BYTE CNT 7A DMA d BCNTIS BCNTI4 BCNTI3 BCNTI2 BCNTII 10 BCNT9 8 7 DMA_d BCNT7 BCNT6 5 BCNT4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 7C DMA d TBL TA3I TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADDR 7D DMA d TBL TA23 TA22 TA21 TA20 19
129. 40048 7 FFF42048 8 4 FFF40048 9 FFF42048 9 4 5 FFF40048 10 FFF42048 10 4 5 FFF40048 11 FFF42048 11 4 5 FFF40064 31 0 FFF4204C 3 0 8 FFF42040 6 0 6 FF800000 FFBFFFFF 31 0 FF800000 FFBFFFFF 31 0 7 FFE00000 FFEFFFFF 31 0 Programmable 31 0 7 Notes 1 RESET switch control 2 Watchdog timer control 3 Access and watchdog timer parameters 4 MPU TEA bus error status 5 Bit numbering for the VMEchip2 and Petra ASICs has a one to one correspondence ABORT switch interrupt control Implemented also in the VMEchip2 but with a different bit organization refer to the VMEchip2 description in Chapter 2 In the MVMEIX2PA the ABORT switch is wired to the Petra chip not the VMEchip2 The SRAM and EPROM decoder in the VMEchip2 version 2 must be disabled by software before any accesses are made to these address spaces Computer Group Literature Center Web Site 8 32 bit prescaler prescaler also be accessed at FFF40064 when the optional VMEbus is not enabled Memory Maps There are two points of view for memory maps 1 The mapping of all resources as viewed by local bus masters local bus memory map 2 The mapping of onboard resources as viewed by VMEbus masters VMEbus memory map The memory maps and I O maps described in the following tables are correct for all local bus masters Some address translation capability exists in the VMEchip2 This capability
130. 5 10 Chip ID 5 13 Chip Revision 5 13 Memory Conbpurauon ROPISIGE 5 14 Base Address Registe 5 15 DRAM Contool 5 15 Prequency Register 5 16 Data ath 5 17 Srub Control Registe gs V R 5 19 Scrub Period Register Bits 19 8 5 20 Scrub Period Register Bits 7 0 5 20 5 21 Serb Tune Ons Time Off 5 21 Scrub Prescaler Counter Bits 21 5 23 Semb Prescaler Counter Bits 158 anaes 5 23 Scrub Pr scaler Counter Bits 7 0 5 24 Litter Counter i 5 24 Somb Timer Counter Bits Ra anita EM 5 25 scrub Address Counter Bits 20 22 5 25 Address Counter Bits 231 se bte ele 5 26 scrub Address Counter Bits D398 eere rt 5 26 Address Counter Bris 7 5 26 Emor Loeser REEI R 5 27 Error Address Bit 9 1 24 iuuat vie 5 28 Error Address Bits 23 DO EHE ERE REPE HERCLE pO Met 5 28 Emor Address BUS 53 8 iet etr nt Hw RADI MEHR DIE Epit EUR ERES 5 2
131. 5 interrupt Set software 6 interrupt Set software 7 interrupt Interrupt Clear Register bits 24 31 ADR SIZ FFF40074 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME CAB CSYSF CMWP CPE CTIC2 OPER C C C C RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is used to clear the edge sensitive interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are defined below CTIC1 CTIC2 Clear tick timer 1 interrupt Clear tick timer 2 interrupt http www motorola com computer literature 2 85 VMEchip2 CMWP CSYSF CAB CACF Clear VMEbus IRQI edge sensitive interrupt Not used on MVME1 X2P4 Clear VMEbus master write post error interrupt Clear VMEbus SYSFAIL interrupt Not used on MVME1 X2P4 Clear VMEbus ACFAIL interrupt Interrupt Clear Register bits 16 23 ADR SIZ FFF40074 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME CVIA CDMA CSIG3 CSIG2 CSIGI CSIGO CLMI CLMO OPER C C C C C C C C RESET X X X X X X X X This register is used to clear the edge sensitive interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are defined below CLMO0 CLMI CSIGO CSIG1 CSIG2 CSIG3 CDMA CVIA Clear GCSR LMO interrupt Clear GCSR interrupt Clear GCS
132. 7 6 5 4 3 2 1 0 SPARE VME7 5 VME4 VMEI R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL 0 PSL This register is the local bus interrupter status register When an interrupt status bit is high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are 1 VMEbus IRQ Interrupt VME2 VMEbus IRQ Interrupt VME3 VMEbus IRQ3 Interrupt VME4 VMEbus IRQ4 Interrupt VMES VMEbus IRQS Interrupt VME6 VMEbus IRQ6 Interrupt VME7 VMEbus IRQ7 Interrupt SPARE Not used 2 80 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Enable Register bits 24 31 ADR SIZ FFF4006C 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME EACF EAB ESYSF EMWP OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove a
133. 9 A BCNTI8 A BCNTI7 BCNTI 92 A BCNTI5 A BCNTI4 A BCNTI3 A BCNTI2 A BCNTI A BCNTIO A BCNT9 A BCNTS 93 A BCNT7 A BCNT6 A BCNTS A BCNT4 A BCNT3 BCNT2 A BCNTI A BCNTO 94 ALTERNATE 0 0 0 0 0 0 0 0 DMA_b BYTE 95 COUNT A BCNT23 A BCNT22 A BCNT21 A BCNT20 A BCNTI9 A BCNTIS A BCNTI7 A BCNTI 96 A BCNTI5 A BCNTI4 A BCNTI3 A BCNTI2 A BCNTI A BCNTIO A BCNT9 A BCNTS 97 A BCNT7 A 6 A BCNTS A BCNT4 A BCNT3 A BCNT2 A BCNTI A BCNTO 98 ALTERNATE 0 0 0 0 0 0 0 0 599 _ BYTE A_BCNT23 BCNT22 BCNT21 A_BCNT20 BCNTI9 A_BCNTI8 A BCNTI7 A BCNTI COUNT 59 A BCNTI5 BCNTI4 BCNTI3 A BCNTI2 A_BCNTI A BCNTIO A BCNT9 _ 8 9B A BCNT7 A_BCNT6 A BCNTS A_BCNT4 A_BCNT3 A_BCNT2 A BCNTI A_BCNTO 9C ALTERNATE 0 0 0 0 0 0 0 0 DMA BYTE 9D COUNT A BCNT23 A BCNT22 A BCNT21 A BCNT20 A BCNTI9 A BCNTIS A BCNTI7 A BCNTI 59 A BCNTI5 A BCNTI4 BCNTI3 A BCNTI2 A_BCNTI A BCNTIO A_BCNT9 A_BCNTS 9 A BCNT7 A 6 A_BCNTS BCNT4 A_BCNT3 A BCNT2 BCNTI A BCNTO A0 ALTERNATE SC DMAEII CHAIN _ 5 5 0 CTL 2 ALTERNATE EN_SC DMAEII CHAIN 5 5 0 DMA_b CTL 2 DMAEII A 2 ALTERNATE EN SC DMAEII CHAIN 5 5 0 2 DMAEII A 3 ALTERNATE EN SC DMAEII CHAIN 5 5 0 CTL 2
134. 9 Error Address Bits JD uides e ae Dk Dele di EI SEPA UE EROR UE RUP 5 29 5 30 aS 5 30 MOG TGS 5 32 SDRAM Configuration Register iuit iq beoe pud toi deeds 5 33 AAR WAIN AEA 5 34 5 36 APPENDIX A Summary of Changes 1 APPENDIX Using Interrupts on the MVME1X2P4 Example Tiek Timer Penodie Intettupk 1 APPENDIX C Related Documentation Motorola Computer Group eeni C 1 2 C 3 XV List of Figures Figure 1 1 MVMEIX2P4 Memory Control Options eee 1 4 Figure 1 2 Black Dia gran reet 1 8 2 1 Block Diagrami 2 5 xvii List of Tables Table 1 1 MY MELA PS Features 1 6 Table 1 2 Functions Duplicated in VMEchip2 and Petra 81 5 1 10 Table 1 3 Local Bus Memory 1 12 Table 1 4 MVME1X2P4 Local Devices Memory 1 14 Table 1 5 VMEchip2 Memory Map
135. A channels page 4 31 IP cache coherency Cache coherency bug with IP memory space IP2 interface did not ignore lower address bits 0 1 during burst cycles Cache coherency with IP memory space now functional page 4 4 MCECC memory control MCECC ASIC revision 00 Petra ASIC revision 01 page 5 13 Check bits Two banks of eight bits each Single bank of seven bits page 5 3 Register shadowing Registers shadowed by a second set of registers No register shadowing page 5 5 Performance Standard MCECC performance Faster than previous MCECC page 5 3 Ethernet N82C501AD device LXT901 device software transparent DRAM No parity fast page SDRAM with ECC protection page 1 2 User configuration Jumper headers Jumper headers and hardware software switches Flash memory device Combination of 28 008 and 28 0165 100 devices 12V programming voltage Manufacturing ID 89 device ID 0A 28F008SA in MVME162P4 versions 28F160S5 in MVME172P4 versions 5V programming voltage Manufacturing ID B0 device ID DO page 1 6 LEDs Through hole wave soldered Surface mount with light pipes SRAM battery Through hole dual battery Surface mount holder A 2 Computer Group Literature Center Web Site Using Interrupts the MVME1X2P4 Example Tick Timer 1 Periodic Interrupt This appendix describes how to use interrupt
136. AC requester executes an early release of the bus If it is about to release the bus and it is executing a VMEbus cycle the requester releases BBSY before its associated VMEbus master completes the cycle This allows the arbiter to arbitrate any pending requests and grant the bus to the next requester at the same time that the DMAC completes its cycle Tick and Watchdog Timers Prescaler The VMEchip2 has two 32 bit tick timers and a watchdog timer The tick timers run on a 1MHz clock which is derived from the local bus clock by the prescaler The prescaler is used to derive the various clocks required by the tick timers VME access timers reset timer bus arbitration timer local bus timer and VMEbus timer The prescaler divides the local bus clock to produce the constant frequency clocks required Software is required to load the appropriate constant depending upon the local bus clock following reset to ensure proper operation of the prescaler 2 14 Computer Group Literature Center Web Site Functional Blocks Tick Timers The VMEchip2 includes two general purpose tick timers These timers can be used to generate interrupts at various rates or the counters can be read at various times for interval timing The timers have a resolution of 1 us When free running they roll over every 71 6 minutes Each tick timer has a 32 bit counter a 32 bit compare register a 4 bit overflow register an enable bit an overflow clear bi
137. ADDR 2C DMA aIP 0 0 0 0 0 0 0 0 ADDR 2D DMA aIP IPA23 IPA22 IPA21 IPA20 IPA19 18 17 16 ADDR 2E DMA_a IP 15 14 13 12 IPA11 IPA10 IPAQ IPA8 ADDR 2F DMA aIP IPA7 IPA6 IPAS 4 IPA2 IPAI IPAO ADDR 30 DMA a 0 0 0 0 0 0 0 0 BYTE CNT 31 DMA a BCNT23 BCNT22 BCNT21 BCNT20 BCNTI9 BCNTIS8 BCNT17 BCNT16 BYTE CNT 32 DMA_a BCNTIS BCNTI4 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 8 33 DMA_a BCNT7 BCNT6 5 BCNT4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 34 DMA a TBL TA3I TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADDR 35 DMA a TBL TA23 TA22 TA21 TA20 19 18 17 16 ADDR 36 DMA a TBL 15 14 13 12 11 10 9 8 ADDR 37 DMA a TBL TA7 TA6 TAS TA4 TA3 TA2 TAL TAO ADDR 2592 9908 2 6 http www motorola com computer literature 4 13 2 Functions Table 4 4 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address Register Register Register Bit Names Offset Name D7 D6 05 04 D3 D2 D1 DO DMAC for IndustryPack b request 0 or for IndustryPack a request 1 This register set is referred to as DMACb in the text 38 DMA b 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 39 DMA_b INT 0 0 DINT DIEN DICLR DIL2 DILI DILO CTRL 3A DMA 0 0 0 0 0 0 0 ENABLE 3B RESERVED 0 0 0 0 0 0 0 0
138. AM device and size options now applicable to the 2 boards refer to Table 1 1 FSTRD FSTRD reflects the state of the FSTRD bit in Defaults Register 1 When 1 this bit indicates that DRAM reads are operating at full speed When 0 it indicates that DRAM read accesses are slowed by one clock cycle Computer Group Literature Center Web Site Programming Model Base Address Register These eight bits are combined with the two most significant bits in Register 7 the next register to form BAD31 BAD22 which defines the base address of the memory For larger memory sizes the lower significant bits are ignored The bit assignments for the Base Address register are ADR SIZ 1st FFF43014 2nd FFF43114 8 bits BIT 31 30 29 28 27 26 25 24 NAME BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 OPER R W R W R W R W R W R W R W RESET O0PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS DRAM Control Register The bit assignments for the DRAM Control register are ADR SIZ 1st FFF43018 2nd FFF43118 8 bits BIT 31 30 29 28 27 26 25 24 BAD23 BAD22 RWB5 RWB4 RWB3 NCEBEN RAMEN OPER R W R W R W R W R W R R W RESET JOPLS OPLS OPLS OPLS 5 5 0 PLS 0 PLS RAMEN RAM Enable This control bit is used to enable the local bus to perform read write accesses to the memo
139. ASIC 1 40 Computer Group Literature Center Web Site Software Support Considerations Cache Coherency The MC680x0 has the ability to monitor local bus cycles executed by other local bus masters such as the SCSI DMA controller the LAN the VMEchip2 DMA controller the VMEbus to local bus controller and the Petra s IP sector DMA controller When snooping is enabled the MPU can invalidate cache entries as required by the current cycle In addition boards equipped with an MC68040 or MC68LC040 processor can also source data as required by the current cycle The MPU cannot monitor VMEbus cycles that do not access the local bus on the MVMEIX2P4 Software must ensure that data shared by multiple processors is kept in memory that is not cached The software must also mark all onboard and off board I O areas as cache inhibited and serialized Sources of Local TEA signal indicating bus error is returned to the local bus master when a local bus time out occurs a DRAM parity error occurs and parity checking is enabled or a VME bus error occurs during a VMEbus access Note Although the MVMEIX2PA series contains synchronous DRAM SDRAM rather than parity DRAM it can be made to emulate parity DRAM for compatibility with the MC2 programming model The MVMEI X2P4 devices that are capable of asserting a local bus error are described below Local Bus Time Out A Local Bus time out occurs whenever a local b
140. B31 B17 OPER R W R RESET FFEO PL DRAM Space Size Register B31 B17 B31 B17 are compared to local bus address signals A31 A17 for memory reference cycles If they compare an SRAM cycle is initiated Note that the same linkage that exists between the DRAM Base and Size registers also exists for the SRAM decode logic Refer to the DRAM Space Base register description The setting of 6 for DZ 2 0 signifies DRAM mezzanine not present In the Petra context it has the additional functionality of enabling the decoding of the control and status registers CSRs in the MCECC memory model which is also implemented by the Petra ASIC The CSRs are located in address range F FF 43000 through FFF430FF for the first MCECC model in the range F FF43100 through FFF431FF for the second MCECC model The use of the code 6 allows backward compatibility with old software It is also amethod of selecting between the parity or ECC memory controller models ADR SIZ FFF42024 8 bits BIT 31 30 29 28 27 26 25 24 NAME DZ2 DZ1 DZO OPER R W R W R W R W R W R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL http www motorola com computer literature 3 25 MC2 Functions DZ2 DZ0 The size bits configure the non ECC DRAM decoder for a particular memory size The following table defines their encoding Note that the table specifies the allowed bit combinations for DZ2 DZ0
141. B7 Note that if STON2 0 is zero the scrubber always releases the DRAM after one memory cycle even if neither the local bus nor refresher need it Read Write Bit 7 is a general purpose read write bit Scrub Prescaler Counter Bits 21 16 The Scrub Prescaler counter uses the 1 MHz clock as an input to create the 0 5 Hz clock that is used for the scrub period Writes to this address update the scrub prescaler Reads to this address yield the value in the scrub prescaler The ability to read and write to the scrub prescaler is provided for test purposes Programming this counter is not recommended This register reflects the current value in the scrub prescaler bits 21 16 ADR SIZ 1st FFF43038 2nd FFF43138 8 bits BIT 31 30 29 28 27 26 25 24 0 0 SPS21 SPS20 SPS19 5 518 5 517 SPS16 OPER R W R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0 PLS Scrub Prescaler Counter Bits 15 8 This register reflects the current value in the scrub prescaler bits 15 8 ADR SIZ 1st FFF4303C 2nd FFF4313C 8 bits BIT 31 30 29 28 27 26 25 24 5 515 SPS14 SPS13 SPS12 SPS11 SPS10 SPS9 5 58 OPER R W R W R W R W R W R W R W RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0PLS http www motorola com computer literature MCECC Functions Scrub Prescaler Counter Bits 7 0
142. CNTO 898 ALTERNATE 0 0 0 0 0 0 0 0 99 DMA_c BYTE A BCNT23 A_BCNT22 A BCNT21 A_BCNT20 _ 19 8 BCNTI7 A_BCNTI6 COUNT 89 _ 15 4 BCNTI3 BCNTI2 lt BCNTIO BCNT9 A_BCNTS8 9B A_BCNT7 A_BCNT6 BCNTS A_BCNT4 A_BCNT3 A_BCNT2 A BCNTI A_BCNTO 9C ALTERNATE 0 0 0 0 0 0 0 0 4 90 COUNT A_BCNT23 A_BCNT22 A BCNT21 20 BCNTI9 A_BCNTI8 BCNTI7 A_BCNTI6 89 A BCNTIS 4 BCNTI3 BCNTI2 lt A BCNTIO A BCNT9 _ 8 9F A_BCNT7 A_BCNT6 A BCNTS A_BCNT4 A_BCNT3 A BCNT2 A BCNTI A_BCNTO A0 ALTERNATE EN SC DMAEII CHAIN _ 5 5 0 DMA CTL2 DMAEII ALTERNATE EN_SC DMAEII CHAIN 5 5 0 DMA b CTL2 DMAEII A 2 ALTERNATE EN SC DMAEII CHAIN 5 SCO DMA_c CTL 2 DMAEII A 3 ALTERNATE EN SC DMAEII CHAIN 5 SCO DMA d CTL 2 DMAEII 2592 9908 6 6 1 30 Computer Group Literature Center Web Site Memory Maps Table 1 9 Z85230 SCC Register Addresses SCC 785230 SCC Register Address Port B Control FFF45001 Port B Data FFF45003 SCC 1 Port A Control FFF45005 Port A Data FFF45007 Port B Control FFF45801 Port B Data FFF45803 SCC 2 Port A Control FFF45805 Port A Data FFF45807 Table 1 10 82596CA Ethernet LAN Memory Map
143. COVE http www motorola com computer literature 3 23 MC2 Functions DRAM and SRAM Memory Controller Registers The DRAM decode logic consists of a base register a size register and an options register The SRAM decode logic consists of a similar set of registers The reset logic initializes the DRAM and SRAM Base registers so that DRAM space starts at address 0 SRAM space starts at FFEO0000 DRAM and SRAM are inhibited by reset Software can examine the MVME1X2P4 DRAM SRAM Options register at address FFF42024 bits 20 16 to determine the size of the SRAM and DRAM DRAM Space Base Address Register ADR SIZ FFF42020 16 bits BIT 31 20 19 16 B31 B20 OPER R W RESET 0 B31 B20 31 20 compared to local bus address signals A31 A20 for memory reference cycles If they compare a DRAM cycle is initiated Note that there is linkage between the Base Address register and its associated Size register The Size register masks the least significant address signals for the comparison Therefore the Base Address register contents must be set to a multiple of the Size register For example if the size is set for 4096KB the Base register must be set to 0 or 4096KB or 8192KB or 12288KB etc 3 24 Computer Group Literature Center Web Site Programming Model SRAM Space Base Address Register ADR SIZ FFF42020 16 bits BIT 15 1 0 NAME
144. Control register 5 15 Error Address register bits 15 8 5 29 Error Address register bits 23 16 5 28 Error Address register bits 31 24 5 28 Error Address register bits 7 4 5 29 Error Logger register 5 27 Error Syndrome register 5 30 features 5 1 functional description 5 3 internal register memory map 5 11 Memory Configuration register 5 14 Scrub Address counter bits 15 8 5 26 Scrub Address counter bits 23 16 5 26 Scrub Address counter bits 26 24 5 25 Scrub Address counter bits 7 4 5 26 Scrub Control register 5 19 Scrub Period register bits 15 8 5 20 Scrub Period register bits 7 0 5 20 Scrub Prescaler counter bits 15 8 5 23 Scrub Prescaler counter bits 21 16 5 23 Scrub Prescaler counter bits 7 0 5 24 Scrub Time On Time Off register 5 21 Scrub Timer counter bits 15 8 5 24 Scrub Timer counter bits 7 0 5 25 SDRAM Configuration register 5 33 SDRAM implementation 5 5 specifications 5 4 memory controller models parity vs ECC 1 3 3 6 memory cycles 1 51 memory devices used on board 1 6 memory map BBRAM configuration area 1 34 BBRAM TOD clock 1 33 Ethernet LAN 1 31 interrupt acknowledge 1 39 IP2 functions all devices 1 24 local bus 1 11 1 12 memory map continued local I O devices 1 14 MC2 functions 1 23 MCECC sector internal registers 5 11 Petra MC2 chip registers 3 10 Petra IP2 chip devices 4 10 SCSI 1 32 time of day clock 1 35 VMEbus 1 39 VMEchip2 GCSR 1 22 VMEchip2 GCSR global control status
145. D of the chip and its revision level The VMEchip2 has a chip ID of ten ID codes 0 and 1 are used by the old VMEchip The initial revision of the VMEchip2 is 0 If mask changes are required the revision level is incremented 2 100 Computer Group Literature Center Web Site GCSR Programming Model The Location Monitor Status register provides the status of the location monitors A location monitor bit is cleared when VMEchip2 detects a VMEbus cycle to the corresponding location monitor address When the or LM1 bits are cleared an interrupt is set to the local bus interrupter If the or LMI interrupt is enabled in the local bus interrupter then local bus interrupt is generated The location monitor bits are set by writing a 1 to the corresponding bit in the location monitor register LMO and LM1 can also be set by writing a 1 to the corresponding clear bits in the local interrupt clear register The Interrupt Control register provides four bits that allow the VMEbus to interrupt the local bus An interrupt is sent to the local bus interrupter when one of the bits is set If the interrupt is enabled in the local bus interrupter then a local bus interrupt is generated The interrupt bits are cleared by writing a 1 to the corresponding bit in the interrupt clear register The Board Control register allows a VMEbus master to reset the local bus prevent the VMEchip2 from driving the SYSFAIL signal line and detect if
146. D7 D6 05 D4 D3 D2 D1 DO 00 CHIP ID 0 0 1 0 0 0 1 1 801 0 0 0 0 0 0 REVISION 02 RESERVED 0 0 0 0 0 0 0 0 803 7 IV6 IV5 IVA IV3 IV2 IVI IVO BASE 04 IP a MEM a BASE31 a BASE30 a BASE29 a BASE28 a BASE27 a BASE26 a BASE25 a BASE24 BASE UPPER 05 IP a MEM a BASE23 a BASE22 BASE21 a BASE20 BASEI9 a 8 a BASE17 a BASE16 BASE LOWER 06 IP b MEM b BASE31 b BASE30 b BASE29 b BASE28 b BASE27 b BASE26 b BASE25 b BASE24 BASE UPPER 07 IP b MEM b BASE23 b BASE22 b BASE21 b BASE20 b BASEI9 b 8 b BASEI7 b 5 16 BASE LOWER 08 IP c MEM c 1 c BASE30 c 5 29 BASE28 c BASE27 c BASE26 c BASE25 BASE24 BASE UPPER 09 MEM c BASE23 BASE22 BASE21 BASE20 5 19 8 c BASEI7 BASEI6 BASE LOWER 0 IP_d MEM d_BASE31 d_BASE30 d_BASE29 d_BASE28 d_BASE27 d_BASE26 d_BASE25 d_BASE24 BASE UPPER 0B IP_d MEM d_BASE23 d 5 22 d BASE21 d BASE20 d BASEI9 8 7 d BASEI6 BASE LOWER 0C IP a MEM a SIZE23 a SIZE22 a SIZE21 a SIZE20 a SIZEI9 a SIZEIS a SIZEI7 a SIZEI6 SIZE 02 IP_b MEM b_SIZE23 b_SIZE22 b_SIZE21 b SIZE20 b_SIZE19 b SIZEIS b SIZEI7 b SIZEI6 SIZE SOE IP c MEM c SIZE23 c SIZE22 c SIZE21 c SIZE20 c SIZEI9 c SIZEI8 c SIZEI7 c SIZEI6 SIZE 0 IP_d MEM d_SIZE23 d_SIZE22 d_SIZE21 d SIZE20 d_SIZE19 d_SIZE18 d
147. DDRESS 2 MASTER STARTING ADDRESS 3 MASTER STARTING ADDRESS 4 MASTER ADDRESS TRANSLATION SELECT 4 MAST MAST MAST MAST 016 2 016 1 EN EN EN 02 102 01 101 lO1 107 ROM ROM BANK B ROM BANK A EN we su po EN 016 WP sw SIZE SPEED SPEED EN EN EN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARB MAST MAST MST MST MASTER DMA DMA DMA DMA DM DMA ROBN DHB DWB FAIR RWD VMEBUS HALT EN TBL FAIR RELM VMEBUS DMA DMA LB DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA DMA TBL SNP MODE INC INC WRT 016 064 BLK AM AM am INT LB BLK 5 4 3 2 1 0 LOCAL BUS ADDRESS COUNTER VMEBUS ADDRESS COUNTER BYTE COUNTER TABLE ADDRESS COUNTER MPU MPU MPU MPU MPU DMA DMA DMA DMA DMA DMA DMA CLR LBE LPE LOB LTO LBE LPE LOB LTO TBL DONE INTERRUPT COUNT STAT ERR ERR ERR ERR ERR ERR ERR ERR ERR ERR 1360 9403 This sheet begins on facing page http www motorola com computer literature 1 19 Board Description and Memory Maps Table 1 5 VMEchip2 Memory Map Sheet 2 of 3 VMEchip2 LCSR Base Address FFF40000 OFFSET 31 30 29 28 27 26 25 24 28 22 21 20 19 18 17 16 ARB VME DMA DMA BGTO 4C EN TIME OFF TIME ON 50 1 54 TICK TIMER 1 58 TICK TIM
148. DTHI a WIDTHO CONTROL 19 IP_bGENERAL b ERR 0 b RTI b RTO b WIDTHI b WIDTHO b BTD b MEN CONTROL 1A IP c GENERAL c ERR 0 c RTI c RTO c WIDTHI c WIDTHO c BTD c MEN CONTROL 1B dGENERAL d ERR 0 d RTI d RTO d WIDTHI d WIDTHO d BTD d MEN CONTROL 1C RESERVED 0 0 0 0 0 0 0 0 ID IP CLOCK 0 0 0 0 0 0 0 1 2 1E DMA 0 0 0 0 0 ROTAT PRI PRIO ARBITRATION CONTROL IF IP RESET 0 0 0 0 0 0 IPI RES RES 2592 9908 1 6 4 12 Computer Group Literature Center Web Site Programming Model Table 4 4 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address FFFBCOO00 Register Register Register Bit Names Offset Name D7 D6 05 D4 D3 D2 D1 DO DMAC for IndustryPack a request 0 This register set is referred to as DMACa in the text 20 DMA a 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 21 DMA_a INT 0 0 DINT DIEN DICLR DIL2 DILO CTRL 22 DMA 0 0 0 0 0 0 0 ENABLE 23 RESERVED 0 0 0 0 0 0 0 0 524 DMA_a DHALT 0 DTBL ADMA WIDTHI WIDTHO 0 XXX CONTROL 1 25 DMA a INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 526 RESERVED 0 0 0 0 0 0 0 0 527 RESERVED 0 0 0 0 0 0 0 0 528 DMA_aLB LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 29 DMA_aLB LBA23 LBA22 LBA21 LBA20 LBAI9 LBAI18 LBAI7 16 ADDR 2A DMA_aLB LBAI5 LBAI4 LBAI3 LBAI2 LBAII LBAIO LBA9 LBA8 ADDR 2B DMA_aLB LBA7 LBA6 5 LBA4 LBA3 LBA2 LBAI LBAO
149. ER R R R R R R R RESET OPLS OPLS OPLS OPLS OPLS OPLS OPLS 0PLS Error Address Bits 7 4 This register reflects the value that was on bits 7 4 of the local MC680x0 bus at the last logging of an error ADR SIZ 1st FFF4306C 2nd FFF4316C 8 bits BIT 31 30 29 28 27 26 25 24 EA7 EA6 5 4 0 0 0 0 R R R R R R R RESET OPLS OPLS OPLS OPLS X X X X http www motorola com computer literature Functions Error Syndrome Register Defaults Register 1 ADR SIZ 1st FFF43070 2nd FFF43170 16 bits BIT 31 30 29 28 27 26 25 24 0 56 55 54 53 52 51 50 OPER R R R R R R R R RESET 0 5 OPLS OPLS OPLS OPLS OPLS OPLS 5 56 50 Bits 5 0 reflect the syndrome value at the last logging of an error The seven bit code indicates the position of the data error When all the bits are 0 there is no error Note that if the logged error was non correctable then these bits are meaningless refer to the Syndrome Decoding section ADR SIZ 1st FFF43074 2nd FFF43174 8 bits BIT 31 30 29 28 27 26 25 24 RWB7 RWB6 FSTRD SELII SELIO RSIZ2 RSIZ1 RSIZO OPER R W R W R W R W R W R W RESET 0 PL V PLS VPLS V PLS V PLS V PLS VPLS V PLS It is not recommended that non tes
150. ER 2 5 2 SCON sys BRD PURS CLR BRD RST sys WD WD WD TO WD WD WD 60 FAIL FAIL STAT PURS FAIL SW RST CLR CLR TO BF SRST RST STAT STAT OUT EN TO CNT STAT EN LRST EN EN 64 PRE 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 AC SYS MWP TIC2 VME DMA 963 962 961 5160 LMO 68 FAIL IRQ FAIL IRQ IRQ IRQ IRQ IACK IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN EN 6C IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 70 CLR CLR CLR CLR CLR CLR CLR CLR CLR CLR 74 IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ IRQ 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 78 FAIL ABORT SYS FAIL MST WP ERROR IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IACK DMA SIG 3 SIG 2 7C IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 80 sw7 SW6 SW5 sw4 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL 84 IRQ7 VME IRQ 6 VME IRQ 5 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL T VECTOR BASE VECTOR BASE d S D ABORT GPIOEN REGISTER 0 REGISTER 1 EN C kieva il tevet 8C This sheet continues on facing page gt 1 20 Computer Group Literature Center Web Site Mem
151. Ebus program access cycles BLK When this bit is high the second map decoder responds to VMEbus block access cycles When this bit is low the second map decoder does not respond to VMEbus block access cycles D64 When this bit is high the second map decoder responds to VMEbus D64 block access cycles When this bit is low the second map decoder does not respond to VMEbus 064 block access cycles http www motorola com computer literature 2 33 VMEchip2 A24 A32 USR SUP When this bit is high the second map decoder responds to VMEbus 24 standard access cycles When this bit is low the second map decoder does not respond to VMEbus 24 access cycles When this bit is high the second map decoder responds to VMEbus A32 extended access cycles When this bit is low the second map decoder does not respond to VMEbus A32 access cycles When this bit is high the second map decoder responds to VMEbus user non privileged access cycles When this bit is low the second map decoder does not responded to VMEbus user access cycles When this bit is high the second map decoder responds to VMEbus supervisory access cycles When this bit is low the second map decoder does not respond to VMEbus supervisory access cycles 2 34 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Write Post and Snoop Control Register 1 ADR SIZ FFF40010 8 b
152. Ebus interface can be configured to provide the following VMEbus capabilities Addressing capabilities A16 A24 A32 Data transfer capabilities D08 D16 D32 The ocal bus slave includes six local bus map decoders for accessing the VMEbus The first four map decoders are general purpose programmable decoders while the other two are fixed and are dedicated for I O decoding The first four map decoders compare local bus address lines A31 through A16 with a 16 bit start address and a 16 bit end address When an address in the selected range is detected a VMEbus select is generated to the VMEbus master Each map decoder also has eight attribute bits and an enable bit The attribute bits are for VMEbus AM address modifier codes D16 enable and write post WP enable The fourth map decoder also includes a 16 bit alternate address register and a 16 bit alternate address select register This allows any or all of the upper 16 address bits from the local bus to be replaced by bits from the alternate address register The feature allows the local bus master to access any VMEbus address 2 4 Computer Group Literature Center Web Site Functional Blocks 6076 vvEL 331 1934 SNLVLS 1V8019 ssayqqv TOYXLNOD viva Ss3uaav Ss3uaav 7051405 TOYLNOOD viva uso5 H3T10HINOO 55 7031409 TOYLNOO
153. F VMEchip2 GCSR D32 D8 256B 1 3 FFF40200 FFFA0FFF Reserved 3 5KB 4 5 41000 FFF41FFF Reserved 4 4 FFF42000 FFF42FFF MC2 chip D32 D8 4KB 1 FFF43000 FFF430FF MCECC 1 D8 256B 1 FFF43100 FFF431FF MCECC 2 D8 256B 1 FFF43200 FFF43FFF MCECCs repeated 3 5KB 1 9 FFF44000 FFF44FFF Reserved 8KB 4 FFF45000 FFF45FFF SCC 285230 D8 4KB 1 2 FFF46000 FFF46FFF LAN 82596CA D32 4KB 1 6 FFF47000 FFF47FFF SCSI 53C710 D32 D8 4KB 1 FFF48000 FFF57FFF Reserved 64KB 4 FFF58000 FFF5807F IP2 chip IP_a I O D16 128B 1 FFF58080 FFF580FF IP2 chip IP_a ID D16 128B 1 FFF58100 FFF5817F IP2 chip IP_b I O D16 128B 1 FFF58180 FFF581FF IP2 chip IP_b ID Read D16 128B 1 FFF58200 FFF5827F IP2 chip IP c I O D16 128B 1 FFF58280 FFF582FF IP2 chip IP_c ID D16 128B 1 FFF58300 FFF5837F IP2 chip IP d I O D16 128B 1 FFF58380 FFF583FF IP2 chip IP_d ID Read D16 128B 1 FFF58400 FFF584FF IP2 chip IP_ab I O D32 D16 256B 1 FFF58500 FFF585FF IP2 chip IP cd I O D32 D16 256B 1 FFF58600 FFF586FF IP2 chip IP ab I O repeated 232 016 256B 1 FFF58700 FFF587FF IP2 chip I O repeated D32 D16 256B 1 Computer Group Literature Center Web Site Memory Maps Table 1 4 MVME1X2P4 Local I O Devices Memory Map Continued Address Range Device s Size Note s FFF58800 FFF5887F Reserved 128B 1 F
154. F40048 in the VMEchip2 No status was given as to the cause of the TEA assertion An error occurred while the MPU was attempting to access a local resource TEA is asserted during the MPU access Bit 7 of the MPU Status and DMA Interrupt Count register actually in the DMAC Status register Address FFF40048 The Local Bus timer timed out This usually indicates the MPU tried to read or write an address at which there was no resource Otherwise it indicates a hardware problem 1 44 Computer Group Literature Center Web Site Software Support Considerations DMAC VMEbus Error Description MPU Notification Status Comments DMAC Parity Error The DMAC experienced a VMEbus error during an attempted transfer DMAC interrupt when enabled The VME bit is set in the DMAC Status register Address FFF40048 bit 1 This indicates the DMAC attempted to access a VMEbus address at which there was no resource or the VMEbus slave returned a signal Note Although the MVMEIX2PA series contains synchronous DRAM SDRAM rather than parity DRAM it can be made to emulate parity DRAM for compatibility with the MC2 programming model Description MPU Notification Status Comments Parity error while the DMAC was reading DRAM DMAC interrupt when enabled The DLPE bit is set in the DMAC Status register Address FFF40048 bit 5 If the TBL bit is set address FFF40048 bit 2 the error occ
155. FF58880 FFF588FF Reserved 128B 1 FFF58900 FFF5897F Reserved 128B 1 FFF58980 FFF589FF Reserved 128B 1 FFF58A00 FFF58A7F Reserved 128B 1 FFF58A80 FFF58AFF Reserved 128B 1 FFF58B00 FFF58B7F Reserved 128B 1 FFF58B80 FFF58BFF Reserved 128B 1 58 00 FFF58CFF Reserved 256B 1 FFF58D00 FFF58DFF Reserved 256B 1 FFF58E00 FFF58EFF Reserved 256B 1 58 00 SFFF58FFF Reserved 256B 1 FFFBC000 FFFBCO1F IP2 chip registers D32 D8 2KB 1 FFFBC800 FFFBC81F Reserved 2KB 1 FFFBDO000 FFFBFFFF Reserved 12 4 FFFC0000 FFFC7FFF M48T58 D32 D8 32KB 1 BBRAM TOD clock FFFC8000 FFFCBFFF M48T58 D32 D8 16KB 1 7 Clear FWEN if MCI 00 SFFFCFFFF M48T58 232 08 16KB 1 7 Set FWEN if MC1 FFFD0000 FFFEFFFF Reserved 128KB 4 http www motorola com computer literature 1 15 Board Description and Memory Maps Notes 1 For a complete description of the register bits refer to the data sheet for the specific chip For a more detailed memory map refer to the following detailed peripheral device memory maps The SCC is an 8 bit device located on a Petra chip private data bus Byte access is required Writes to the LCSR in the VMEchip2 ASIC must be 32 bits LCSR writes of 8 or 16 bits terminate with a TEA signal Writes to the GCSR may be 8 16 or 32 bits Reads to the LCSR and GCSR may be 8 16 or 3
156. FFF43128 8 bits BIT 31 30 29 28 27 26 25 24 SBPD15 SBPD14 SBPD13 SBPD12 SBPD11 SBPDIO SBPD9 SBPD8 OPER R W R W R W R W R W R W R W RESET 1 PLS 1 PLS 1 PLS 1 PLS 1 PLS 1 PLS IPLS 1PLS Scrub Period Register Bits 7 0 This register contains bits 7 0 of the Scrub Period register ADR SIZ 1st FFF4302C 2nd FFF4312C 8 bits BIT 31 30 29 28 27 26 25 24 SBPD7 SBPD67 SBPD5 SBPD4 SBPD3 SBPD2 SBPDI SBPDO OPER R W R W R W R W R W R W R W R W RESET 1PLS 1 PLS 1PLS 1PLS 1PLS 1PLS 1PLS 1PLS Computer Group Literature Center Web Site Programming Model Chip Prescaler Counter This register reflects the current value in the prescaler counter The Prescaler counter is used with the BCLK Frequency register to produce a 1MHz clock signal for use by the refresher and by the scrubber The register is readable and writable for test purposes Programming of this register is not recommended ADR SIZ 1st FFF43030 2nd FFF43130 8 bits BIT 31 30 29 28 27 26 25 24 CPS7 CPS6 557 CPS4 CPS3 52 CPS1 CPSO OPER R wW R W R W R W R W R W R W R W RESET Scrub Time On Time Register ADR SIZ 1st FFF43034 2nd FFF43134 8 bits BIT 31 30 29 28 27 26 25 24 RWB7 0 STON2
157. FFF58180 FFF581BF IP_b ID Space D16 64B FFF581C0 FFF581FF IP_b ID Space Repeated D16 64B FFF58200 FFF5827F IP_c I O Space D16 128B FFF58280 FFF582BF IP cID Space D16 64B FFF582CO SFFF582FF IP_c ID Space Repeated D16 64B FFF58300 FFF5837F IP_d I O Space D16 128B FFF58380 FFF583BF IP_d ID Space D16 64B FFF583CO SFFF583FF IP_d ID Space Repeated D16 64B FFF58400 FFF584FF IP_ab I O Space D32 D16 256B FFF58500 FFF585FF I O Space D32 D16 256B FFF58600 FFF586FF IP_ab I O Space Repeated D32 D16 256B FFF58700 FFF587FF IP I O Space Repeated D32 D16 256B FFFBC000 FFFBC083_ Control Status Registers D32 D8 32B 4 10 Computer Group Literature Center Web Site Programming Model Programming Model This section defines the programming model for the control and status registers CSRs in the IP2 sector The base address of the CSRs is hardwired to FFFBC000 The possible operations for each bit in the CSR are as follows R This bit is a read only status bit R W This bit is readable and writable R C This status bit is cleared by writing a 1 to it Writing 0 to this bit clears this bit or another bit This bit reads as 0 S Writing 1 to this bit sets this bit or another bit This bit reads as 0 The possible states of the bits after assertion of the RESET pin powerup reset or any local reset are as defined below R The bit is affected by reset X The bit is not
158. FFFCIFF8 W R S Calibration Control FFFCIFF9 ST Seconds 00 FFFCIFFA x Minutes 00 FFFCIFFB x x Hour 00 FFFCIFFC x FT x x x Day 01 FFFCIFFD x x Date 01 FFFCIFFE x x x Month 01 FFFCIFFF Year 00 Notes W Write Bit R Read Bit S Sign Bit ST Stop Bit FT Frequency Test x Must be set to 0 http www motorola com computer literature 1 35 Board Description and Memory Maps The data structure of the configuration bytes starts at SFFFCIEFS It is organized as shown below struct brdi cnfg Q G GQ GQ OQ Q Q Q 0 nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar nar version serial 1 id 16 pwa 16 4 ethernet 11 27 lscsiid pmem pwb pmem ser smem Smem ser ecclmem_pwb 8 ecclmem_ 41 21 6 21 8 ial 8 8 ial 8 serial 8 ecc2mem pwb 8 ecc2mem port2 pwb 8 port2 se ipa brdi ipa seri ipa pwb ipb brdi ipb seri ipb pwb ipc brdi ipc seri ipc pwb ipd brdi ipd seri ipd pwb reserved 17 cksum 1 The fields are defined as follows srial 8 ri
159. FFFFF IPA 000000 000001 000000 000001 000002 000003 000002 000003 000004 7FFFFD 7FFFFE 7FFFFF 7FFFFE 7FFFFF Comments IP borab IP b IP_b or ab IP_b IP_b or ab IP borab IP b 4 52 Computer Group Literature Center Web Site Local Bus to IndustryPack Addressing a I O Space This example is for IP a I O space The relationship of the IndustryPack address to the local bus address is IPA lt 6 0 gt LBA lt 6 0 gt Note that IPA lt 22 7 gt do not pertain to I O space LBA 58000 58001 58002 58003 5807 FFF5807D FFF5807E FFF5807F IPA lt 6 0 gt 0000000 0000001 0000010 0000011 1111100 1111101 1111110 1111111 Comments http www motorola com computer literature 4 53 2 Functions IP ab I O Space This example is for 32 bit IP ab I O space The relationship of the IndustryPack address to the local bus address is IPA lt 6 1 gt LBA lt 7 2 gt and IPA lt 0 gt LBA lt 0 gt Note that IPA 22 7 do not pertain to I O space LBA IPA lt 6 0 gt Comments FFF58400 000000 IP_b or ab FFF58401 000001 IP_b FFF58402 000000 IP_a FFF58403 000001 IP_a FFF58404 000010 IP_b or ab FFF58405 000011 IP_b
160. HI XXX or R W R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR XXX This bit must remain cleared If it is set to a 1 the Petra IP2 ASIC will not function correctly CH1 C CHI When CHI is set to a0 DMA request 0 from Industry Pack b is associated with the DMACb register set When itis set to a 1 DMA request 1 from Industry Pack a is associated with the DMACb register set When CHI is set to a zero DMA request 0 from Industry Pack d is associated with the DM ACd register set When it is set to a 1 request 1 from Industry Pack c is associated with the DMACd register set Note that DMACa register set is always associated with DMA request 0 from Industry Pack a and DMAC register set is always associated with DMA request 0 from Industry Pack c Therefore these bit positions are not defined for these two register sets Refer to the section on the Enable DMA Function for information and restrictions on the operation of A CHI and C CHI 4 38 Computer Group Literature Center Web Site Programming Model WIDTHI WIDTHO WIDTH bits specify the width of the IndustryPack interface at position a or position a b The following table defines the bit encoding Note that these width control bits are independent of the width control bits in the General Control registers Also note that unlike the width control bits in the General Control registers these width control bits define the width of
161. Interrupt Control Interrupt Control 1C DRAM Parity Error SCC Interrupt Tick Timer 4 Tick Timer 3 Interrupt Control Control Control Control 20 DRAM Space Base Address Register SRAM Space Base Address Register 24 DRAM Space DRAM SRAM SRAM Space Reserved Size Options Size 28 LANC Error Status Reserved LANC Interrupt LANC Bus Error Control Interrupt Control 2C SCSI Error Status General Purpose Board Version SCSI Interrupt Inputs Control 30 Tick Timer 3 Compare Register 34 Tick Timer 3 Counter Register 38 Tick Timer 4 Compare Register 3C Tick Timer 4 Counter Register 3 10 Computer Group Literature Center Web Site Programming Model Table 3 4 Petra MC2 Functions Register Map Continued MC2 Sector Base Address FFF42000 Offset D31 D24 D23 D16 D15 D8 D7 D0 40 Bus Clock EPROM Access Flash Parameter ABORT Switch Time Control Control Interrupt Control 44 RESET Switch Watchdog Timer Access Watchdog Reserved Control Control Time Base Select 48 DRAM Control Reserved MPU Status Reserved 4C 32 bit Prescaler Count Register Programming Model This section defines the programming model for the control and status registers CSR in the Petra MC2 chip The base address of the CSR is FFF42000 The operations possible for each bit in the CSR are as follows R R W This bit is a read only status bit This bit is readable and writable Writing a 1 to this bit clears this bit or another bit
162. L 0 PSL This register is the address modifier select register for the first VMEbus to local bus map decoder There are three groups of address modifier select bits DAT PGM BLK D64 A24 and A32 and USR and SUP At least one bit must be set from each group to enable the first map decoder DAT When this bit is high the first map decoder responds to VMEbus data access cycles When this bit is low the first map decoder does not responded to VMEbus data access cycles PGM When this bit is high the first map decoder responds to VMEbus program access cycles When this bit is low the first map decoder does not respond to VMEbus program access cycles BLK When this bit is high the first map decoder responds to VMEbus block access cycles When this bit is low the first map decoder does not respond to VMEbus block access cycles D64 When this bit is high the first map decoder responds to VMEbus D64 block access cycles When this bit is low the first map decoder does not respond to VMEbus D64 block access cycles A24 When this bit is high the first map decoder responds to VMEbus A24 standard access cycles When this bit is low the first map decoder does not respond to VMEbus A24 access cycles 2 36 Computer Group Literature Center Web Site LCSR Programming Model A32 When this bit is high the first map decoder responds to VMEbus A32 extended access cycles When this bit is low
163. Level Register 2 bits 24 31 Lisa rri 2 89 Interrupt Level Register 2 bits 16 23 1e reto ena 2 90 Intercupt Level Register 2 bits 8 13 2 90 Interropt Level Register 2 bits 0 7 2 91 Level Register 3 bits 24 31 Lise 2 91 Level Register 3 bits 16 23 iusserit kot eren 2 02 Intetcupt Level Register 2 bits 8 13 2 02 Interropt Level Register 3 bits D 7 2 93 Intemupt Level Register 4 bits 24 31 2 93 Interr pt Level Register bits 16 23 1a rrr renean anna 2 94 Intercupt Level Register 4 bits 5 15 2 94 Interr pt Level Register 4 bits D T 2 95 Vector Base Repister Fiere 2 95 BE Control curs dier 2 96 DUO Contol 2 97 2 97 Muscellaneous Control 2 98 COSR Bs SV ATOMS 2 100 2 102 Revision Register 2 103 VNE chipa ID 1 C TE 2 104 LM SIG MI ce a E 2 104 VMEchip2 Board Status Control Register 2 106 General Purpose Register rumes 2 107 Gener Purpose E iussa pit 2 107 General Parpose Register 2 pis de REIHE
164. MVME1 X2P4 are covered in the chapters devoted to those ASICs Note MVME1X2P4 s new Petra ASIC combines the functions previously covered by the MC2 chip the IP2 chip and the MCECC chip in a single ASIC For ease of use in conjunction with programming models and documentation developed for earlier boards however the structure of this manual preserves the functional distinctions that formerly characterized those three ASICs Chapter 2 describes the VMEchip2 ASIC Chapters 3 4 and 5 respectively cover MC2 chip functions 2 chip functions and MCECC chip functions all three of which are now implemented by the Petra ASIC Appendix A describes the use of interrupts Readers more interested in programmable register bit definitions than in hardware functionality may wish to focus on Chapters 2 3 4 and 5 The related background information found in Chapter 1 this chapter may be of use in some cases 1 1 Board Description and Memory Maps Overview The MVME162P4 is based the MC68040 MC68LC040 microprocessor The MVME172P4 is based on the MC68060 or MC68LC060 microprocessor The board artwork is otherwise the same for both MVMEIX2P4 models Both models are available in various versions with the features listed in Table 1 1 on page 1 6 No IP no SCSI and no LAN options are available as well The Petra ASIC and Second Generation MVME1X2 Boards Due to rapid changes in technology the production
165. MVME1X2P4 VME Embedded Controller Programmer s Reference Guide V1X2P4A PG2 Edition of November 2000 Copyright 2000 Motorola Inc All rights reserved Printed in the United States of America Motorola and the Motorola logo are registered trademarks of Motorola Inc MC68040 and MC68060 are trademarks of Motorola Inc IndustryPack and IP are trademarks of GreenSpring Computers Inc All other products mentioned in this document are trademarks or registered trademarks of their respective holders Safety Summary The following general safety precautions must be observed during all phases of operation service and repair of this equipment Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment The safety precautions listed below represent warnings of certain dangers of which Motorola is aware You as the user of the product should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment Ground the Instrument To minimize shock hazard the equipment chassis and enclosure must be connected to an electrical ground If the equipment is supplied with a three conductor AC power cable the power cable must be plugged into an approved three contact electrical outlet with the grounding wire green yellow reliably connected to an electrical ground
166. MW cycles and there is no defined protocol for supporting multiple address RMW cycles which start onboard and then access off board resources The MVME1X2P4 does not fully support all RMW operations in all possible cases MVMEIX2PA supports a limited subset of RMW instructions and makes the following assumptions The MVME1X2P4 supports single address RMW cycles caused by TAS and CAS instructions Because it is not possible to tell if the MC680x0 is executing a single or multiple address read modify write cycle software should only execute single address RMW instructions Multiple address RMW cycles caused by CAS or CAS2 instructions are not guaranteed indivisible and may cause illegal VMEbus cycles Lock cycles caused by MMU table walks do not cause illegal VMEbus cycles and they are not guaranteed indivisible Illegal Access to IP Modules from External VMEbus Masters When a device other than the local MVME1X2P4 is operating as VMEbus master access by that device to the local IP modules is subject to restrictions Access to the IndustryPack memory space is supported in all cases Due to the difference in data width between the VMEbus and the IP modules D32 versus D16 however access to the IndustryPack I O ID and Interrupt Acknowledge space is not supported for single IP modules This applies to IndustryPacks A B C and D 1 52 Computer Group Literature Center Web Site VMEchip2 Introduction
167. O 04 CHIP REV7 REV6 REVS REV47 REV3 REV2 REVO REVISION 08 MEMORY 0 0 FSTRD 1 0 MSIZ2 MSIZI MSIZO CONFIG 0C 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 14 BAD31 BAD30 BAD29 BAD28 BAD27 BAD26 BAD25 BAD24 ADDRESS 18 DRAM BAD23 BAD22 RWB5 RWB4 RWB3 NCEIEN NCEBEN RAMEN CONTROL 1C BCLK BCK7 BCK6 BCK5 BCK47 BCK3 BCK2 BCKO FREQUENCY 20 DATA 0 0 DERC ZFILL RWCKB 0 0 0 CONTROL 24 SCRUB 0 0 0 SCRB SCRBEN 0 SBEIEN RWBO CONTROL 28 SCRUB SBPD15 SBPD14 SBPDI3 SBPDI2 SBPDII SBPD10 SBPD9 SBPD8 PERIOD 2C SCRUB SBPD7 SBPD6 SBPD5 SBPD4 SBPD3 SBPD2 SBPDI SBPD07 PERIOD 30 CHIP CPS7 CPS6 CPS5 CPS4 CPS3 CPS2 CPS1 CPSO PRESCALE 34 SCRUB SRDIS 0 STON2 STONI STONO STOFF2 STOFF1 SRDIS TIME ON OFF 38 SCRUB 0 0 SPS21 SPS20 SPS19 SPS18 SPS17 SPS16 PRESCALE 3C SCRUB SPS15 SPS 14 SPS 13 SPS12 SPS11 SPS 10 SPS9 SPS85 PRESCALE 40 SCRUB SPS7 SPS6 SPSS SPS4 SPS3 SPS2 SPS1 SPSO PRESCALE 44 SCRUB ST15 ST14 ST13 ST12 STII ST10 ST9 ST8 TIMER http www motorola com computer literature 5 11 MCECC Functions Table 5 3 MCECC Sector Internal Register Memory Map Continued MCECC Sector Base Address FFF43000 first board FFF43100 second board Register Register Bit Names Offset Name D31 D30 D29 D28 D27 D26 025 024 48 SCRUB ST7 ST6 STS ST4 ST3 ST2 STI STO TIMER 4C SCRUB
168. OPER R W S R S RESET 0 PS OPS OPS 0 PS This register controls the VMEbus interrupter IRQL IRQS IRQC IRQIS These bits define the level of the VMEbus interrupt generated by the VMEchip2 A VMEbus interrupt is generated by writing the desired level to these bits These bits always read 0 and writing 0 to these bits has no effect This bit is the IRQ status bit When this bit is high the VMEbus interrupt has not been acknowledged When this bit is low the VMEbus interrupt has been acknowledged This is a read only status bit This bitis the VMEbus interrupt clear bit When this bit is set high the VMEbus interrupt is removed This feature is only used when the IRQ1 broadcast mode is used Normal VMEbus interrupts should never be cleared This bit always reads 0 writing a 0 to it has no effect These bits control the function of the IRQI signal line on the VMEbus 0 The IRQI signal from the interrupter is connected to the VMEbus IRQI signal line 1 The output from tick timer 1 is connected to the VMEbus signal line 2 The IRQI signal from the interrupter is connected to the VMEbus signal line 3 The output from tick timer 2 is connected to the VMEbus signal line http www motorola com computer literature 2 61 VMEchip2 VMEbus Interrupter Vector Register ADR SIZ FFF40048 8 bits of 32 BIT 23 16 NAME Interrupter Vector OPER R W RESET
169. P4 main module The Petra ASIC also performs the memory control functions previously carried out by the MCECC chip Memory Controller ASIC It supplies the programmable interface for the ECC protected 16 32 DRAM emulation http www motorola com computer literature 1 5 Board Description and Memory Maps The following table summarizes the features of the MVME162P4 and MVME172P4 Embedded Controllers Table 1 1 MVME1X2P4 Features Summary Feature MVME162P4 MVME172P4 Processor 25 32 32 bit MC68040 or 60MHz 32 bit MC68060 MC68LC040 microprocessor microprocessor or 64MHz 32 bit MC68LC060 microprocessor DRAM 16 32MB synchronous DRAM SDRAM Configurable to emulate 1 4 8 16MB parity protected DRAM or 4 8 16 32MB ECC protected DRAM 2 boards use SDRAM Synchronous DRAM in place of DRAM SRAM 512KB SRAM with battery backup EPROM One JEDEC standard 32 pin PLCC EPROM socket EPROMs may be shipped separately Flash One Intel 28 0085 1 8 or One Intel 28F160S5 1Mx8 or 2Mx8 2Mx8 Flash memory device with Flash memory device with optional optional write protection write protection NVRAM and 8K by 8 Non Volatile RAM NVRAM and Real Time Clock RTC with RTC battery backup and watchdog function SGS Thomson M48T58 Timers Four 32 bit tick timers and watchdog timer in Petra ASIC Two 32 bit tick timers and watchdog timer in VMEchip2 ASIC Software Ei
170. R 65 DMA c TBL TA23 TA22 TA21 TA20 19 18 17 16 ADDR 66 DMA_c TBL 15 14 13 12 11 10 9 8 ADDR 67 DMA_c TBL 7 6 5 4 TA2 TAL TAO ADDR 2592 9908 4 6 http www motorola com computer literature 4 15 2 Functions Table 4 4 Petra 2 Memory Map Control Status Registers Cont d 2 Sector Base Address 000 Register Register Register Bit Names Offset Name D7 D6 D5 D4 D3 D2 D1 DO DMAC for IndustryPack d request 0 or for IndustryPack c request 1 and for PACER CLOCK This register set not including the Pacer Clock is referred to as DMACd in the text 68 DMA d 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 69 DMA dINT 0 0 DINT DIEN DICLR DIL2 DILI DILO CTRL 6A DMA 0 0 0 0 0 0 0 DEN ENABLE 6B RESERVED 0 0 0 0 0 0 0 0 6 DMA_d DHALT 0 DTBL ADMA WIDTHI WIDTHO C CHI XXX CONTROL 1 6D DMA d INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 6E RESERVED 0 0 0 0 0 0 0 0 GF RESERVED 0 0 0 0 0 0 0 0 70 DMA_dLB LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 71 DMA_dLB LBA23 LBA22 LBA21 LBA20 LBAI9 LBA18 LBAI7 16 ADDR 72 DMA_dLB 15 14 LBAI13 LBAI2 LBAII LBAIO LBA9 LBAS8 ADDR 73 DMA dLB LBA7 5 4 LBA2 LBAI LBAO ADDR 74 DMA_d IP 0 0 0 0 0 0 0 0 ADDR 75 DMA_d IP IPA23 IPA22
171. R R R R R R R RESET X X X X X X X X Chip Revision Register The Chip Revision register is hard wired to reflect the revision level of the Petra MCECC ASIC The current value of the register is 07 Although writes to this register are ignored the MCECC sector pair always terminates the cycles properly with ADR SIZ 1st FFF43004 2nd FFF43104 8 bits BIT 31 30 29 28 27 26 25 24 NAME REV7 REV6 REVS REV4 REV3 REV2 REVI REVO OPER R R R R R R R RESET X X X X X X X X http www motorola com computer literature Functions Memory Configuration Register ADR SIZ 1st FFF43008 2nd FFF43108 8 bits BIT 31 30 29 28 27 26 25 24 NAME 10 0 FSTRD 0 0 MSIZ2 MSIZ1 MSIZO OPER R R R R R R R RESET X X X X X X X X 8172 8170 MSIZ2 MSIZO together define the size of the total memory to be controlled by the MCECC sector These bits reflect the RSIZ2 RSIZO bits in Defaults Register 1 MSIZ2 MSIZ1 MSIZO Memory Size MSIZ2 MSIZ1 MSIZO Memory Size 0 0 0 4MB 1 0 64MB 0 0 1 8MB 1 0 1 128 0 1 0 16 1 1 0 Reserved 0 1 1 32MB 1 1 1 Reserved Note Remember that the DRAM organization presented in the table above is relevant to the extent that it aids in emulating DRAM configurations from earlier programming models For the actual SDR
172. R SIGO interrupt Clear GCSR SIGI interrupt Clear GCSR SIG2 interrupt Clear GCSR SIG3 interrupt Clear DMA controller interrupt Clear VMEbus interrupter acknowledge interrupt 2 86 Computer Group Literature Center Web Site LCSR Programming Model Interrupt Clear Register bits 8 15 ADR SIZ FFF40074 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME CSW7 CSW6 CSW5 CSW4 CSW3 CSW2 CSWI CSWO OPER C C C C C C C C RESET X X X X X X X X This register is used to clear the edge software interrupts An interrupt is cleared by writing a 1 to its clear bit The clear bits are CSWO0 CSWI CSW2 CSW3 CSW4 CSWS CSW6 CSW7 Clear software 0 interrupt Clear software 1 interrupt Clear software 2 interrupt Clear software 3 interrupt Clear software 4 interrupt Clear software 5 interrupt Clear software 6 interrupt Clear software 7 interrupt Interrupt Level Register 1 bits 24 31 ADR SIZ FFF40078 8 bits 6 used of 32 BIT 31 30 29 28 27 26 25 24 ACF LEVEL AB LEVEL OPER R W R W RESET 0 PSL 0 PSL This register is used to define the level of the abort interrupt and the ACFAIL interrupt AB LEVEL Not used on MVMEIX2P4 LEVEL These bits define the level of ACFAIL interrupt http www motorola com computer literature 2 87 VMEchip2 Interrupt Level Register 1 bits 16 23
173. S This register is the address translation select register for the first VMEbus to local bus map decoder The address translation select register value is based on the segment size the difference between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size Segment Segment ees Size Translation Size Translation Select Value Select Value 6KB FEO 128 FFFE 64MB 00 256 128 800 512 FFF8 256MB F000 FFFO 512MB E000 2MB FFEO 1GB C000 4MB FFCO 2GB 8000 8MB FF80 4GB 0000 16MB 00 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Address Translation Address Offset Register 2 ADR SIZ FFF4000C 16 bits of 32 BIT 31 s 16 NAME Address Translation Address Offset Register 2 OPER R W RESET 0 PS This register is the address translation address register for the second VMEbus to local bus map decoder It should be programmed to the local bus starting address When the adder is enabled this register is the offset value VMEbus Slave Address Translation Select Register 2 ADR SIZ FFF4000C 16 bits of 32 BIT 15 0 Address Translation Select Register 2 OPER R W RESET 0 PS This register is the address translation se
174. Sheet 1 2 222 1 1 18 Table 1 6 Petra MC2 Functions Register iecore ete 1 23 Table 1 7 Petra IP2 Functions Overall Memory 1 24 Table 1 8 Petra IP2 Memory Map Control Status Registers 1 25 Table 1 9 785230 SUC Register Addresses e eiae arde dures ep aede 1 31 Table 1 10 82596C A Ethernet LAN Memory Map etate tette Rete 1 31 Table 1 00 356 210 SC SE Memory as ise reir eere eire elena Eee p 1 32 Table 1 12 M48T58 BBRAM TOD Clock Memory Map 1 33 Table 1 13 BBRAM Configuration Area Memory Map eese 1 34 Table t 14 TOD Clock Memory 1 35 Table 2 I Features of tlie ViVIBehip2 ASIC 2 1 Table 2 2 VMEchip2 Memory Map LCSR Summary Sheet 1 of 2 2 22 Table 2 3 DMAC Command Packet Format oe eta 2 53 Table 2 4 Local Bus Intern pter Summary iiie eere raptu 2 75 Table 2 5 VMEchip2 Memory 2 103 Table 3 1 MC Puncbons the Petra Fons rne 3 1 Table 3 2 SDRAM ie ie inan pe 3 7 Table 3 5 SEC Deyice PIES UID Lisa aber redet 3 8 Table 3 4 Petra MC Functions Register Map oerte 3 10 Table 3 5 Interrupt Vector Base Register Encoding and Prio
175. Space D32 D8 64KB 16MB Programmable IP_d Memory Space D16 D8 64KB 8MB FFF58000 FFF5807F IP_a I O Space D16 128B FFF58080 FFF580BF IP_a ID Space D16 64B FFF580C0 FFF580FF ID Space Repeated D16 64B FFF58100 FFF5817F IP_b I O Space D16 128B FFF58180 FFF581BF IP_b ID Space D16 64B FFF581C0 FFF581FF IP_b ID Space Repeated D16 64B FFF58200 FFF5827F IP_c I O Space D16 128B FFF58280 FFF582BF cID Space D16 64B FFF582CO SFFF582FF IP_c ID Space Repeated D16 64B FFF58300 FFF5837F IP_d I O Space D16 128B FFF58380 FFF583BF IP_d ID Space D16 64B FFF583C0 FFF583FF IP_d ID Space Repeated D16 64B FFF58400 FFF584FF IP_ab I O Space D32 D16 256B FFF58500 FFF585FF I O Space D32 D16 256B FFF58600 FFF586FF IP_ab I O Space Repeated D32 D16 256B FFF58700 FFF587FF IP I O Space Repeated D32 D16 256B FFFBCOO FFFBCO083 Control Status Registers D32 D8 32B summary of the IP2 sector CSR registers appears in Table 1 8 The CSR registers can be accessed as bytes words or longwords They should not be accessed as lines They are shown in the table as bytes 1 24 Computer Group Literature Center Web Site Memory Maps Table 1 8 Petra IP2 Memory Map Control Status Registers 2 Sector Base Address 000 Register Register Register Bit Names Offset Name
176. T 15 m 8 NAME VMEchip2 Revision Register OPER R RESET 01 PS This register is the VMEchip2 revision register The revision level for the VMEchip2 starts at 0 and is incremented if mask changes are required The VMEchip2 used on the MVME1X2P4 is revision 01 or greater http www motorola com computer literature 2 103 VMEchip2 VMEchip2 ID Register ADR SIZ Local Bus FFF40100 VMEbus XXYO 8 bits BIT 7 24 0 VMEchip2 ID Register OPER R RESET 10 PS This register is the VMEchip2 ID register The ID for the VMEchip2 is 10 VMEchip2 LM SIG Register ADR SIZ Local Bus FFF40104 VMEbus 2 8 bits BIT 15 14 13 12 11 10 9 8 NAME LM3 LM2 LMI LMO SIG3 SIG2 SIGI SIGO OPER R R R R S R S R S R S R RESET 1 PS 1 PS 1 PS 1 PS 0 PS 0 PS 0 PS 0 PS This register is the VMEchip2 location monitor register and the interrupt register SIGO The SIGO bit is set when a VMEbus master writes a 1 to it When the SIGO bit is set an interrupt is sent to the local bus interrupter The SIGO bit is cleared when the local processor writes a 1 to the SIGO bit in this register or the CSIGO bit in the local interrupt clear register SIG1 The 5 bit is set when a VMEbus master writes a 1 to it When the SIGI bit is set an interrupt is sent to the local bus interrupter The SIGI bit is cleared when the local processor writes 1 to the SIGI bit in th
177. THO b BID b MEN N AME 1 A c ERR 0 c RTI c RTO c WIDTHI c WIDTHO BTDO c MEN NAME 1B d ERR 0 d RTI d RIO d WIDTHI d WIDTHO d BID d 6 OPER R R W R W R W R W R W R W R W RESET OR OR OR OR OR OR MEN a_MEN b_MEN c_MEN d_ MEN enable the local bus to perform read write accesses to their corresponding IndustryPack memory space when set and disable such accesses when cleared When a double size IndustryPack is used in ab MEN should be set and the WIDTH and MEN control bits in the IP b General Control register should be cleared When a double size IndustryPack is used in cd c MEN should be set and the WIDTH and MEN control bits in the IP d General Control register should be cleared BTD Setting BTD bus turnaround delay to a 1 will insert one inactive clock period following a read cycle on the IP bus This idle cycle is to eliminate bus contention which would occur if the time to assert a valid address by the IP2 sector is less than the time required by the Industry Pack to put the bus in a high impedance state following the read cycle The IP2 sector will drive the bus valid following the positive edge of the IP clock typically in seven nanoseconds worst case in 15 Note that IndustryPack modules which were designed to meet the 0 7 or earlier revision of the GreenSprings IndustryPack Specification 4 24 Computer Group Literature Center Web Site Programming Model were allowed 40 ns to three state the b
178. Table 3 1 MC2 Functions on the Petra ASIC Function Memory Control Features BBRAM and time of day clock M48T58 interface with bus sizing EPROM interface with bus sizing Flash interface with bus sizing SRAM controller supporting several configurations DRAM controller supporting several configurations T O Interfacing Four Zilog serial interfaces implemented with Z85230 SCC device NCR 53C710 SCSI Coprocessor interface Intel 82596CA LAN Coprocessor interface Timers Four 32 bit tick timers Local bus access timer Watchdog timer Interrupt Handling Interrupt support for ABORT switch LAN SCSI SCC DRAM and timers 3 1 MC2 Functions Functional Description The following sections give an overview of the functions implemented by the Petra MC2 chip A detailed programming model for control and status registers in the Petra MC2 chip appears in a later section Petra MC2 Chip Initialization The Petra MC2 chip accommodates several memory configurations and MVME1X2P4 population versions Configuration registers are used to initialize the MVME1X2P4 Version register General Purpose Inputs register and DRAM SRAM Options register read only Flash and EPROM Interface The Petra MC2 chip interfaces the MC680x0 local bus to one 1M x 8 or 2M x 8 Intel Flash device and to one PLCC socket MVME162P4 models use an Intel 28 0085 device while MVME172P4 models
179. This bit reads 0 The possible bit states after local and power up reset are as defined below L X 0 1 The bit is affected by power up reset The bit is affected by local reset The bit is not affected by reset The bit is always 0 The bit is always 1 http www motorola com computer literature 3 11 MC2 Functions MC2 Sector ID Register FFF42000 8 bits ADR SIZ BIT 31 30 29 28 27 26 25 24 ID7 ID6 ID5 104 ID3 ID2 ID1 IDO OPER R R R R R R R R RESET 0 PL 0 PL 0 PL 0 PL ID7 IDO chip ID number is 84 This register is read only It ignores a write but ends the cycle with TA i e the cycle terminates without exceptions MC2 Sector Revision Register FFF42000 8 bits ADR SIZ BIT 23 22 21 20 19 18 17 16 NAME RV7 RV6 RV5 RV4 RV3 RV2 RV1 RVO OPER R R R R R R R R RESET 0 PL 0 PL 0 PL RV7 RV0 The current value of the chip revision is 03 This register is read only It ignores a write but ends the cycle with i e the cycle terminates without exceptions General Control Register FFF42000 8 bits ADR SIZ BIT 15 14 13 12 11 10 9 8 NAME SCCIT1 SCCITO MIEN OPER R R R R W R W R R W R RESET 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL MIEN Master Interrupt Enable When t
180. This chapter describes the VMEchip2 ASIC the local bus VMEbus interface chip The VMEchip2 interfaces the local bus to the VMEbus In addition to its VMEbus defined functions the VMEchip2 includes a local bus to VMEbus DMA controller VME board support features and Global Control and Status Registers GCSRs for interprocessor communications The following table summarizes the characteristics of the VMEchip2 ASIC Table 2 1 Features of the VMEchip2 ASIC Function Features Local Bus to Programmable local bus map decoder VMEbus Interface Programmable short standard and extended VMEbus addressing Programmable AM codes Programmable 16 bit and 32 bit VMEbus data width Software enabled write posting mode Write post buffer one cache line or one four byte Automatically performs dynamic bus sizing for VMEbus cycles Software configured VMEbus access timers Local bus to VMEbus Requester with Software enabled fair request mode Software configured release modes Release When Done RWD and Release On Request ROR Software configured BRO BR3 request levels VMEchip2 Table 2 1 Features of the VMEchip2 ASIC Continued Function VMEbus to Local Bus Interface Features Programmable VMEbus map decoder Programmable AM decoder Programmable local bus snoop enable Simple VMEbus to local bus address translation 8 bit 16 bit and 32 b
181. _SIZE17 d_SIZE16 SIZE 10 IP_a INTO a0 PLTY a0 E L a0 INT a0 IEN a0 ICLR a0 IL2 a0 ILI a0 ILO CONTROL 11 _ al_PLTY al E L al INT al IEN al ICLR al IL2 al ILI al ILO CONTROL 12 IP b INTO 0 PLTY b0 E L bO INT b0 b0 bO_IL2 bO ILI bO ILO CONTROL 13 IP bINTI bl PLTY bl E L bl INT bl IEN bl ICLR bl IL2 bl ILI bl ILO CONTROL 14 IP c INTO c0 PLTY c0 E L c0 INT c0 IEN c0 ICLR cO IL2 cO ILI cO ILO CONTROL 15 IP c INTI cl PLTY cl E L cl INT cl IEN cl ICLR cl IL2 cl ILI cl ILO CONTROL 16 IP d INTO 40 PLTY 40 E L dO INT dO dO dO IL2 dO ILI dO ILO CONTROL 17 d di PLTY dl E L dl INT dl IEN dl dl IL2 dl ILI dl ILO CONTROL 18 IP aGENERAL ERR 0 a RTI a RTO a WIDTHI a WIDTHO a BTD a MEN CONTROL 19 IP b GENERAL b ERR 0 b RTI b RTO b WIDTHI b WIDTHO b BTD b MEN CONTROL IP c GENERAL ERR 0 c RTI c RTO c WIDTHI c WIDTHO c BTD MEN CONTROL IP dGENERAL d ERR 0 d RTI d RTO d WIDTHI d WIDTHO d BTD d MEN CONTROL SIC RESERVED 0 0 0 0 0 0 0 0 1D IP CLOCK 0 0 0 0 0 0 0 IP32 1E DMA 0 0 0 0 0 ROTAT PRII PRIO ARBITRATION CONTROL 1F IP RESET 0 0 0 0 0 0 IPI RES RES 2592 9908 1 6 http www motorola com computer literature 1 25 Board Description and Memory Maps Table 1 8 Petra IP2 Memory Map Control Status Registers Cont d IP2 Sector Base Address
182. a Local Bus Master The IP2 sector does not connect to the ST1 and STO signal lines Consequently when it receives a TEA termination to any cycle for which it is local bus master no status will be available to indicate the source of the bus error There is a status bit in each DMAC status register which 4 8 Computer Group Literature Center Web Site Functional Description indicates that a local bus error did occur as a consequence of a DMA operation The contents of the local bus address counter can be examined for the address that caused the bus error IndustryPack Error Reporting Interrupts Each IndustryPack interface has an error pin The error status from the four interfaces are available in the General Control registers The IP2 sector can be programmed to interrupt the local bus master via the signal pins when one or more of the eight IndustryPack interrupts asserted The interrupt control registers allow each interrupt source to be level edge sensitive and high low true When the local bus master acknowledges an interrupt if the IP2 sector determines that it is the source of the interrupt being acknowledged it waits for IACKIN to be asserted then it performs an interrupt acknowledge cycle to the appropriate IndustryPack in order to obtain the vector number It then passes the vector number on to the local bus master and asserts TA to terminate the cycle When the local bus master acknowledges
183. al 8 d 8 al 8 8 d 8 al 8 8 ares al 8 8 d 8 al 8 8 1 Four bytes are reserved for the revision or version of this structure This revision is stored in ASCII format with the first two bytes being the major version numbers and the last two bytes being the 1 36 Computer Group Literature Center Web Site minor version numbers For example if the version of this structure is 1 0 this field contains 0100 2 Twelve bytes are reserved for the serial number of the board in ASCII format For example this field could contain 000000470476 3 Sixteen bytes are reserved for the board ID in ASCII format For example for an MVME162P4 board with MC68040 SCSI Ethernet 16 MB SDRAM and 512KB SRAM this field might contain 162 3445 The 14 characters followed by two blanks 4 Sixteen bytes are reserved for the printed wiring assembly PWA number assigned to this board in ASCII format This includes the 01 prefix This is for the main logic board if more than one board is required for a set Additional boards in a set are defined by a structure for that set For example for an MVME162P4 board with MC68040 SCSI Ethernet 16MB SDRAM 512KB SRAM at revision D the PWA field might contain 01 W3528F50D The 12 characters are followed by four blanks 5 Four bytes contain the speed of the board in MHz The first two
184. ample one map can be configured as A32 D32 with write posting enabled while a second map can be A24 D16 with write posting disabled The first I O map decoder decodes local bus addresses FFFF0000 through FFFFFFFF as the short I O A16 D16 or A16 D32 area The other provides an A24 D16 space at F0000000 to FOFFFFFF and A32 D16 space at F 1000000 to FF7FFFFF Supervisor non privileged and program data space is determined by attribute bits Write posting may be enabled or disabled for each decoder I O space and this map decoder may be enabled or disabled When write posting is enabled the VMEchip2 stores the local bus address and data and then acknowledges the local bus master The local bus is then free to perform other operations while the VMEbus master requests the VMEbus and performs the requested operation The write post buffer stores data in single byte double byte quad byte or one cache line four quad bytes form Write posting should only be enabled when bus errors are not expected If a bus error is returned on a write posted cycle and the interrupt is enabled the local processor is interrupted The address of the error is not saved Normal memory never returns a bus error on a write cycle However some VMEbus ECC memory cards perform a read modify write operation and therefore may return a bus error if there is an error on the read portion of a read modify write Write posting should not be enabled when this type of m
185. an interrupt if the 2 sector determines that it is not the source of the interrupt being acknowledged it waits for IACKIN to be asserted then it passes the acknowledge on down the daisy chain by asserting IACKOUT The interrupter also provides interrupt capability for the programmable clock and for each of the four DMA controllers Additionally interrupts from the programmable clock can be programmed for rising and or falling edge sensitivity The vector passed to the local bus master during an interrupt acknowledge for the programmable clock and DMAC interrupts is from the vector base register in the IP2 sector Part of the vector is programmable the other part encodes the source of the interrupt http www motorola com computer literature 4 9 2 Functions Overall Memory The following memory map table includes all devices selected by the IP2 sector map decoder Table 4 3 IP2 Sector Overall Memory Map Address Range Selected Device Port Width Size Programmable IP_a IP_ab Memory D32 D8 64KB 16MB Space Programmable IP_b Memory Space D16 D8 64KB 8MB Programmable IP_c IP_cd Memory D32 D8 64KB 16MB Space Programmable IP_d Memory Space D16 D8 64KB 8MB FFF58000 FFF5807F IP_a I O Space D16 128B FFF58080 FFF580BF IP_a ID Space D16 64B FFF580C0 FFF580FF IP_a ID Space Repeated D16 64B FFF58100 FFF5817F IP_b I O Space D16 128B
186. anine PWB identifier in ASCII ECC2 Memory Mezzanine serial number in ASCII Eight bytes are reserved for the serial number assigned to the serial port 2 personality board in ASCII format Eight bytes are reserved for the board identifier in ASCII assigned to the optional first IndustryPack module IP a Eight bytes are reserved for the serial number ASCII assigned to the optional first IndustryPack module IP a Eight bytes are reserved for the printed wiring board PW B number assigned to the optional first IndustryPack module IP a Eight bytes are reserved for the board identifier in ASCII assigned to the optional second IndustryPack module IP b Eight bytes are reserved for the serial number ASCII assigned to the optional second IndustryPack module IP b Computer Group Literature Center Web Site 18 19 20 21 22 23 24 25 26 Eight bytes reserved for the printed wiring board PWB number assigned to the optional second IndustryPack module IP b Eight bytes are reserved for the board identifier in ASCII assigned to the optional third IndustryPack module IP c Eight bytes are reserved for the serial number in ASCII assigned to the optional third IndustryPack module IP c Eight bytes are reserved for the printed wiring board PWB number assigned to the optional third IndustryPack module IP c Eight bytes are reserved for the board
187. are Register OPER R W RESET OP Tick Timer 1 Counter ADR SIZ FFF42008 32 bits BIT 31 0 NAME Tick Timer 1 Counter OPER R W RESET X Tick Timer 2 Compare Register ADR SIZ FFF4200C 32 bits BIT 31 i34 0 NAME Tick Timer 2 Compare Register OPER R W RESET Tick Timer 2 Counter ADR SIZ FFF42010 32 bits BIT 31 0 NAME Tick Timer 2 Counter OPER R W RESET X Computer Group Literature Center Web Site Programming Model LSB Prescaler Count Register This register is used to generate the 1MHz clock for the four tick timers This register is read only It increments to FF at the processor frequency then it is loaded from the Prescaler Clock Adjust register ADR SIZ BIT FFF42014 8 bits 31 24 NAME LSB Prescaler Count OPER R RESET X Prescaler Clock Adjust Register This register adjusts the prescaler so that it maintains IMHz clock source for the tick timers To provide a 1MHz clock the prescaler adjust register should be programmed based on the following equation Prescaler Clock Adjust Register 256 processor clock MHz As an example For operation at 20MHz the prescaler value is SEC at 25MHz it is E7 and at 33MHz it is DF Non integer processor clocks introduce an error into the specified times for the tick timers The tick timer clock can be derived by the following equation Tick clock processor clock 256 Prescaler Value The maximum clock f
188. are will enable either the parity or the ECC memory controller model depending on board configuration The board configuration is a function of switch settings and resistor population options User code can modify Petra register settings to operate in either mode The benefit of operating with the ECC memory model is that single bit errors will be scrubbed so that they cannot degenerate into double bit errors User code can also modify map decoder switch settings to enable the maximum amount of memory available The minimum SDRAM configuration is 16MB The Petra memory controller maintains tags for each internal bank of SDRAM Each bank may be in an active or idle state Performance is then a function of the state of the memory bank being addressed If that bank of memory is active then the access time is also a function of the page of memory being referenced If that page is open access time is the fastest If it is not open then the open page must be closed and the new one opened That would be the slowest access mode Page size is determined by the SDRAM device Pages range from 256 to 1024 locations 3 6 Computer Group Literature Center Web Site Functional Description The following table summarizes the memory specifications The table is of necessity incomplete since it cannot account for the effects of the write posting operation If the Petra memory controller is idle and a write cycle is initiated on the local bus that
189. ase register 1 3 Referto the Vector Base register description later in this chapter for recommended Vector Base register values 2 76 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Status Register bits 24 31 ADR SIZ FFF40068 8 bits of 32 BIT 31 30 29 28 27 26 25 24 NAME ACF AB SYSF MWP PE TIC2 R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter status register When an interrupt status bit is high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are TIC2 VILE PE MWP SYSF AB ACF Tick timer 1 interrupt Tick timer 2 interrupt VMEbus IRQI edge sensitive interrupt Not used on MVME1X2P4 VMEbus master write post error interrupt VMEbus SYSFAIL interrupt Not used on 2 VMEbus ACFAIL interrupt http www motorola com computer literature 2 77 VMEchip2 Local Bus Interrupter Status Register bits 16 23 ADR SIZ FFF40068 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME VIA DMA SIG3 SIG2 5 SIGO LM1 LMO OPER R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL 0 PSL This register is the local bus interrupter status register W
190. atic Mezz PWB SFFFCIFAE FFFC1F4D Static Mezz Serial FFFC1F56 FFFCIFSD Mezz PWB SFFFCIFSE FFFC1F5D Mezz Serial FFFC 1F66 FFFC1F65 ECC2 Mezz PWB FFFC 1F6E FFFC1F75 ECC2 Mezz Serial SFFFCIF76 FFFC1F7D Ser Port 2 Pers PWB SFFFCIFTE FFFC1F85 Ser Port 2 Pers Serial No FFFC 1F86 FFFC1F8D IP_a Board ID FFFC 1F8E FFFC1F95 IP_a Board Serial Number SFFFCIF96 FFFC1F9D IP_a Board PWB SFFFCIF9E FFFC1FAS IP_b Board ID FFFC 1FA6 SFFFCIFAD IP_b Board Serial Number FFFC1FB5 b Board PWB SFFFCIFB6 IP_c Board ID FFFC1FBE SFFFCIFC5 IP_c Board Serial Number FFFC 1FC6 SFFFCIFCD IP_c Board PWB 4FFFC1FCE FFFC1FDS IP_d Board ID 00 CO CO CO CO CO CO CO CO CO CO CO CO CO OO CO CO CO CO CH NI NI DA gt 1 34 Computer Group Literature Center Web Site Memory Maps Table 1 13 BBRAM Configuration Area Memory Map Continued Address Range Description Size Bytes FFFC1FD6 FFFC1FDD IP_d Board Serial Number 8 FFFC1IFDE FFFC1FES IP_d Board PWB 8 FFFC1FE6 FFFC1FF6 Reserved 65 FFFCIFF7 Checksum 1 Table 1 14 TOD Clock Memory Data Bits Address D Function 7 6 5 4 3 2 1 0
191. b Site Programming Model IP_b Memory Base Address Registers ADR SIZ FFFBCOO06 and FFFBCOO7 8 bits each BIT 7 6 5 4 3 2 1 0 06 b 5 b BASE3 b BASE2 b b b b b 1 0 9 8 7 6 5 4 NAME 07 b b b b b b b b BASEI 3 2 1 0 9 8 7 6 OPER R W R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR ADR SIZ FFFBCOO8 and FFFBCOO9 8 bits each BIT 7 6 5 4 3 2 1 0 08 5 c 1 0 9 8 7 6 5 4 09 3 2 1 0 9 8 7 6 R W R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR BIT 7 6 5 4 3 2 1 0 NAM E 0 d d 5 d d d 1 0 9 8 7 6 3 4 NAM E 0 B d d d BASEI d d BASEI 3 2 1 0 9 8 7 6 R W R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR http www motorola com compute
192. both the memory and I O interface WIDTHI1 WIDTHO Assumed Data Bus Width 32 bits 8 bits 16 bits O m c Reserved ADMA DTBL DHALT Setting ADMA to a 1 will enable the address mode DMA operation Setting it to a 0 will enable the standard mode of DMA operation Refer to the section on the DMA Enable Function for information and restrictions on the operation of the ADMA control bit DMAC operates in the direct mode when this bit is low and it operates in the command chaining mode when this bit is high When this bit is high DMA halts at the end of a command when DMA is operating in the command chaining mode When this bit is low DMA executes the next command in the list Software must be careful not to change the state of bits 0 through 6 of this control register when the DHALT bit is set http www motorola com computer literature 4 39 IP2 Functions DMA Control Register 2 This register is loaded by the processor or by DMA when it loads the command word from the command packet Because this register is loaded from the command packet in the command chaining mode the descriptions here also apply to the control word in the command packet ADR SIZ FFFBC025 3D 55 6D 8 bits each BIT 7 6 5 4 3 2 1 0 INTE 0 DMAEI DMAEO ENTO TOIP 0 0 OPER R R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR
193. burst where the DMA cycles can be executed back to back The DMA arbiter logic will not release a DMA channel until a burst of IP cycles are completed if the burst protocol is observed However if the burst protocol is not observed the arbiter is released and the next DMA request grant is resolved This takes two clock cycles due to the asynchronous clocks controlling the MC680x0 local bus and the IP buses The IP designer should take this into consideration if maximum DMA bandwidth availability is required http www motorola com computer literature 4 5 IP2 Functions Note also that when the DMA register context is updated for the next command packet a DMA function is used The state of the snoop control signals for this DMA function as well as the state of the snoop control signals for all other DMA cycle types depends on the status of configuration bits SC1 and SCO in the Petra ASIC Bits 1 and SCO are under the control of configuration switch S5 pins I and 2 55 1 55 2 Requested Snoop Operation BED ocu MC68040 MC68060 On On Snoop disabled Snoop disabled On Off Source dirty sink byte word longword Snoop enabled Off On Source dirty invalidate line Snoop disabled Off Off Snoop disabled Reserved Snoop enabled Clocking Environments and Performance The IP2 sector has two clock domains The majority of the logic is controlled by the MC680x0 local bus clock 25MHz or 32MHz in the ca
194. bus to the IndustryPack bus for different IndustryPack memory widths described later in this chapter Note For sDMA operations the IndustryPack address counter must be cleared before the DMAC is enabled ADR SIZ FFFBCO2C 44 5C 74 32 bits each BIT 31 23 22 0 NAME 0 DMA Industry Pack Address Counter OPER R W RESET OR 4 42 Computer Group Literature Center Web Site Programming Model DMA Byte Counter In direct mode this counter is programmed with the number of bytes of data to be transferred For sDMA operations if the port width is 16 bits then the byte count must be initialized to an even value if the width is 32 bits then the byte count must be initialized to a multiple of four bytes If the port width is 8 bits the byte count value has no restrictions ADR SIZ FFFBCO30 48 60 78 32 bits each BIT 31 24 23 0 0 DMA a Byte Counter OPER R W RESET OR DMA Table Address Counter In the command chaining mode this counter should be loaded by the processor with the starting address of the list of commands Note that the command packets in local bus memory must always be 16 byte aligned That is the starting address of any command packet must have the least significant nibble of the address set to a 0 If the Table Address counter is initialized with a value where the four least significant bits are not a 0 the logic will interpret it as a hal
195. ce configuration This bit is duplicated at the same bit position in the VMEchip2 at location FFF40060 When this bit is high or the duplicate bit in the VMEchip2 is high the RESET switch 15 enabled When both bits are low the RESET switch is disabled When this bit is high the MC2 sector asserts the BRDFAIL signal pin This signal is wire ORed to the VMEchip2 board fail pin It controls the board fail FAIL LED on the MVME1X2P4 When this bit is set high the power up reset status bit is cleared This bit is always read as 0 This bit is set by a power up reset It is cleared by a write to the CPURS bit http www motorola com computer literature 3 41 MC2 Functions BRFLI When this status bit is high the BRDFAIL signal pin on the Petra MC2 chip is asserted When this status bit is low the BRDFAIL signal pin on the Petra MC2 chip is not asserted The BRDFAIL pin may be asserted by an external device the BDFLO bit in this register or a watchdog time out Watchdog Timer Control Register The watchdog timer control logic in the MC2 sector is used if the board is built in a VMEbus interface configuration This function is duplicated at the same bit locations in the VMEchip2 at location FFF40060 The VMEchip2 has the additional option of selecting SYSRESET i e VMEbus reset It is permissible to enable the watchdog timer in both the VMEchip2 ASIC and the Petra MC2 sector
196. ck 4 49 local bus to VMEbus interface 2 4 VMEbus to local bus interface 2 9 VMEchip2 DMAC 2 11 aDMA addressed DMA 4 4 alternate address register VMEchip2 ASIC 2 10 arbiter time out timer VMEbus 2 64 VMEbus 2 17 arbitration MCECC sector 5 9 arbitration modes VMEbus 2 17 ASICS replaced by Petra 1 2 attribute register VMEchip2 2 28 snoop bits 2 28 IN 1 xmo backward compatibility 1 2 1 38 3 6 3 25 base address VMEchip2 LCSR 2 20 BBRAM configuration area memory map 1 34 Flash write enable 3 3 memory map 1 33 BBSY signal VMEbus 2 98 signal VMEbus 2 17 BGIN filters VMEbus 2 98 binary number symbol for xxiv block D64 access cycles VMEbus 2 33 2 36 block access cycles VMEbus 2 33 2 36 block diagram MVME1x2P4 1 7 block diagram VMEchip2 ASIC 2 5 block transfer cycles VMEchip2 DMAC 2 11 mode 2 9 modes DMAC 2 59 board address GCSR 2 48 documentation C 1 failure signal VMEchip2 ASIC 2 70 ID field configuration data structure 1 37 overview 1 2 status control register VMEchip2 2 106 Board Control register VMEchip2 2 101 BRDFAIL signal pin VMEchip2 ASIC 2 70 2 71 broadcast interrupt function VMEchip2 timers 2 15 broadcast mode VMEbus 2 16 BSY signal and arbitration timer 2 17 bug fixes IP2 sector 4 2 bus error handler 1 43 error processing 1 43 error signals 1 41 map decoder LCSR 2 20 bus continued sizing 2 6 timer enable disable VMEbus 2 17 t
197. cremented This bit should normally be set high In special situations such as transferring data to or from a FIFO it may be desirable to not increment the counter http www motorola com computer literature 2 57 VMEchip2 SNP These bits control the snoop signal lines on the local bus when the DMAC is local bus master and it is not accessing the command table The snooping functions differ according to processor type as shown Requested Snoop Operation MC68040 MC68060 Snoop disabled Snoop enabled Source dirty sink byte word longword Snoop disabled Source dirty invalidate line Snoop enabled o0 o OLR Snoop disabled Reserved Snoop disabled INTE This bit is used only in command chaining mode It is only modified when the DMAC loads the control register from the control word in the command packet When this bit in the command packet is set an interrupt is sent to the local bus interrupter when the command in the packet has been executed The local bus is interrupted if the DMAC interrupt is enabled DMAC Control Register 2 bits 0 7 ADR SIZ FFF40034 8 bits of 32 BIT 7 5 4 3 2 1 0 NAME BLK VME AM OPER R W R W RESET OPS OPS This portion of the control register is loaded by the processor or the DMAC when it loads the command word from the command packet Because this byte is loaded from the command packet in command chaining mode
198. cription of the major blocks of the MVME1X2P4 refer to the Installation and Use manual VMEbus Interface and VMEchip2 The local bus to VMEbus interface and the VMEbus to local bus interface are provided by the VMEchip2 ASIC The VMEchip2 can also provide the VMEbus system controller functions Refer to the VMEchip2 description in Chapter 2 for detailed programming information In support of possible future configurations in which the MVME1X2P4 might be offered as an embedded controller without the VMEbus interface certain logic the VMEchip2 has been duplicated in the Petra chip Table 1 2 shows the location of the overlapping logic As long as the VMEchip2 ASIC is present the redundant logic is inhibited in the Petra chip Note that the ABORT switch logic in the VMEchip2 is not used Likewise unused are the GPI inputs to the VMEchip2 which are located at FFF40088 bits 7 0 Instead the ABORT switch interrupt is integrated into the Petra ASIC at location FFF42043 The GPI inputs are integrated into the Petra ASIC at location FFF4202C bits 23 16 http www motorola com computer literature 1 9 Board Description and Memory Maps Table 1 2 Functions Duplicated in VMEchip2 and Petra ASICs VMEchip2 Petra Chip Notes Address Bit Address Bit FFF40060 28 24 FFFA2044 28 24 1 5 FFF40060 22 19 FFFA2044 22 19 2 5 17 16 17 16 FFF4004C 13 8 FFF42044 13 8 3 5 FFF
199. cted When the DMAC stops the status bits are set in the DMAC status register and an interrupt is sent to the local bus interrupter If the DMAC interrupt is enabled in the local bus interrupter the local bus is interrupted When the DMAC finishes processing a command in the list and interrupts are enabled for that command the DMAC sends an interrupt to the local bus interrupter If the DMAC interrupt is enabled in the local bus interrupter the local bus is interrupted The DMAC control is divided into two registers The first register is only accessible by the processor The second register can be loaded by the processor in direct mode and by the DMAC in command chaining mode Once the DMAC is enabled the counter and control registers should not be modified by software When you use the command chaining mode the list of commands must be in local 32 bit memory and the entries must be quad byte aligned A DMAC command list includes one or more DMAC command packets A DMAC command packet includes a control word that defines the VMEbus AM code the VMEbus transfer size the VMEbus transfer method the DMA transfer direction the VMEbus and local bus address counter operation and the local bus snoop operation The format of the control word is the same as the lower 16 bits of the control register The command packet also includes a local bus address a VMEbus address a byte count and a pointer to the next command packet in the list The end
200. ddress Register 4 OPER R W RESET 0 PS This register is the ending address register for the fourth local bus to VMEbus map decoder Local Bus Slave VMEbus Master Starting Address Register 4 ADR SIZ FFF40020 16 bits of 32 BIT 15 n 0 NAME Starting Address Register 4 OPER R W RESET 0 PS This register is the starting address register for the fourth local bus to VMEbus map decoder Local Bus Slave VMEbus Master Address Translation Address Register 4 ADR SIZ FFF40024 16 bits of 32 BIT 31 TF 16 NAME Address Translation Address Register 4 OPER R W RESET 0 PS This register is the address translation address register for the fourth local bus to VMEbus bus map decoder 2 42 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Slave VMEbus Master Address Translation Select Register 4 ADR SIZ FFF40024 16 bits of 32 BIT 15 0 Address Translation Select Register 4 OPER R W RESET 0 PS This register is the address translation select register for the fourth local bus to VMEbus bus map decoder Local Bus Slave VMEbus Master Attribute Register 4 ADR SIZ FFF40028 8 bits of 32 BIT 31 30 29 28 27 26 25 24 D16 WP AM OPER R W R W R W RESET 0 PS OPS OPS This register is the attribute register for the fourth local bus to VMEbus bus map decoder AM T
201. depends upon the GCSR group select value XX and GCSR board select value Y programmed in the LCSR The board value Y may be 0 through E allowing 15 boards in one group The value F is reserved for the location monitors The VMEchip2 includes four location monitors LMO LM3 The location monitors provide a broadcast signaling capability on the VMEbus When a location monitor address is generated on the VMEbus all location monitors in the group are cleared The signal interrupts 5160 5163 should be used to signal individual boards The location monitors are located in the VMEbus short I O space and the specific address is determined by the VMEchip2 group address The location monitors LMO LM3 are located at addresses XXF1 XXF3 XXF5 and XXF7 respectively A location monitor cycle on the VMEbus is generated by a read or write to VMEbus short I O address where XX is the group address and N is the specific location monitor address When the VMEchip2 generates a location monitor cycle to the VMEbus within its own group the VMEchip2 DTACKs itself A VMEchip2 cannot DTACK location monitor cycles to other groups The GCSR section of the VMEchip2 contains the following registers a Chip ID register a Chip Revision register a Location Monitor Status register an Interrupt Control register a Board Control register and six General Purpose registers The Chip ID and Revision registers are provided to allow software to determine the I
202. difier select register should be programmed for the required address modifier codes A VMEbus slave map decoder is disabled when the address modifier select register is cleared The address translation registers allow local resources to have different VMEbus and local bus addresses Only address bits A31 through A16 may be modified The address translation registers also provide the upper eight local bus address lines when an A24 VMEbus cycle is used to access a local resource The address translation register should be programmed with the translated address and the address translation select register should be programmed to enable the translated address If address translation is not desired then the address translation registers should be programmed to 0 The address translation address register and the address translation select register operate in the following way If you set a bit in the address translation select register then the corresponding bit in the address translation address register drives the appropriate local bus address line If you clear the bit in the address translation select register then the corresponding VMEbus address line drives the appropriate local bus address line The most significant bit of the address translation select register corresponds to the most significant bit of address translation register and to A32 of the local bus and A32 of the VMEbus In addition to the address translation method previously descr
203. ditions occur 1 The local bus master initiates either a data transfer cycle or an interrupt acknowledge cycle to the VMEbus 2 The chip is requested to acquire control of the VMEbus as signaled by the DWB input signal pin 3 The chip is requested to acquire control of the VMEbus as signaled by the DWB control bit in the LCSR The local bus to VMEbus requester in the VMEchip2 implements a fair mode By setting the LVFAIR bit the requester refrains from requesting the VMEbus until it detects its assigned request line in its negated state The local bus to VMEbus requester attempts to release the VMEbus when the requested data transfer operation is complete the DWB pin is negated the DWB bit in the LCSR is negated and the bus is not being held by a lock cycle The requester releases the bus as follows 1 When the chip is configured in release when done RWD mode the requester releases the bus when the above conditions are satisfied 2 When the chip is configured in release on request ROR mode the requester releases the bus when the above conditions are satisfied and there is a bus request pending on one of the VMEbus request lines To minimize the timing overhead of the arbitration process the local bus to VMEbus requester the VMEchip2 executes an early release of the VMEbus If it is about to release the bus and it is executing a VMEbus cycle the requester releases BBSY before its associated master completes the c
204. double size IndustryPack can occupy positions and B or it can occupy positions C and D http www motorola com computer literature 4 3 2 Functions The Petra 2 sector monitors the snoop control SC1 SCO and memory inhibit MI signals to maintain cache coherency When SC1 and SCO indicate that snooping is inhibited the IP2 sector ignores the memory inhibit MI signal line When SC1 and SCO do not indicate that snooping is inhibited the IP2 sector waits for the negation of MI before responding to a cycle If TA or is asserted by another local bus slave before MI is negated then the IP2 sector assumes that the cycle is over and that it is not to participate Local Bus to IndustryPack DMA Controllers The IP2 supports two basic types of DMA cycles standard DMA sDMA and addressed DMA aDMA sDMA cycles are requested by the IP When the DMA controller DMAC detects a DMA request and if that DMA controller is enabled it will acknowledge the request by transferring data between the local bus and the I O space of the requesting IP device Alternatively aDMA transfers are not linked to a request acknowledge protocol aDMA cycles are initiated by the DMA controller as soon as its control registers have been initialized by the 680 0 It will transfer data between the local bus and a selected IP module memory space The IP2 sector implements four DMA controllers
205. drome code values denote an error The bit in error is decoded as shown in the table Table 5 4 Syndrome Bit Encoding Bit in Error Syndrome Code Bit in Error Syndrome Code Bit 0 4F Bit 16 0E Bit 1 4A Bit 17 0B Bit 2 52 Bit 18 13 Bit 3 54 Bit 19 15 Bit4 57 Bit 20 16 Bit 5 58 Bit 21 19 Bit 6 5B Bit 22 1A Bit7 5D Bit 23 1C Bit 8 23 Bit 24 62 Bit 9 25 Bit 25 64 Bit 10 26 Bit 26 67 Bit 11 29 Bit 27 68 Bit 12 2A Bit 28 6B Bit 13 2C Bit 29 6D Bit 14 31 Bit 30 70 Bit 15 34 Bit 31 77 Check Bit 0 01 Check Bit 4 10 Check Bit 1 02 Check Bit 5 20 Check Bit 2 04 Check Bit 6 40 Check Bit 3 08 5 36 Computer Group Literature Center Web Site Syndrome Decoding Since the memory architecture is 32 data bits plus seven syndrome bits with a non interleaved architecture there is no corresponding entry for Bank in Error The selection of the physical SDRAM bank is decoded from the address bus Consequently the Error Address register must be examined to determine which bank contains the error Given a specific SDRAM configuration the following table relates bits in the Error Address register to the physical bank where the error originated Table 5 5 Identifying SDRAM Bank in Error SDCFG2 0 SDCFG1 0 SDCFG0 0 DRAM Array Size and Bank with the Error Device is 64Mbit x 16 data with one bank comp
206. duces a 1MHz clock that is used by the refresh timer and the scrubber When the BCLK Frequency register is correctly programmed with the BCLK frequency the DRAMs are refreshed approximately once every 15 6 microseconds After power up this register is initialized to 19 for 25MHz Computer Group Literature Center Web Site Programming Model Note This register is configured only during power up reset and is unchanged by software or local reset ADR SIZ 1st FFF4301C 2nd FFF4311C 8 bits BIT 31 30 29 28 27 26 25 24 BCK7 6 BCKS BCK4 BCK3 BCK2 BCKO OPER R W R W R W R W R W R W R W 1 1 1 Data Control Register ADR SIZ 1st FFF43020 2nd FFF43120 16 bits BIT 31 30 29 28 27 26 25 24 NAME 0 0 DERC ZFILL RWCKB 0 0 0 OPER R R R W R W R W R R R RESET X X PLS 0 PLS 0 PLS X X X RWCKB READ WRITE CHECKBITS when set enables the data from the seven checkbits in the Petra MCECC sector bits 30 24 to be written and read on the local MC680x0 data bus This bit should be cleared for normal system operation Note that if test software forces a single bit error to a location line using this function the scrubber may correct the location before the test software gets a chance to check for the single bit error at that location This can be avoid
207. e interrupt source during the acknowledge cycle The exception to this is that after reset occurs the interrupt vector passed is 07 which remains in effect until a write is generated to the Vector Base register Note Note that this register does not affect the vector supplied during an interrupt acknowledge cycle for any of the eight IndustryPack IRQ signals A normal read access to the Vector Base register yields the value 0F if the read happens before it has been initialized A normal read access yields all 075 on bits 0 2 and the value that was last written on bits 3 7 if the read happens after the Vector Base register was initialized The encoding for the interrupt sources is shown below where IV2 IVO refer to bits 2 0 of the vector passed during the IACK cycle IV2 0 Interrupt Source 0 DMA a 1 DMA b 2 DMA c 3 DMA d 4 Programmable Clock http www motorola com computer literature 4 19 2 Functions Memory Base Address Registers IP_a IP_b IP_c IP_d The memory base address registers define the base address at which the IP2 sector initiates memory cycles for their corresponding IndustryPacks If a 32 bit double size IndustryPack is used then the memory base address and memory size registers for IP a control access for double size ab and those for IP c control accesses for double size cd For each of the four sets of registers BASE31 BASE16 are compared to MC680x0 address
208. e of the ERROR signal from the d interface http www motorola com computer literature 4 27 IP2 Functions IP Clock Register ADR SIZ FFFBCO1D 8 bits OR OR OR OR OR OR Setting IP32 to 1 enables the IndustryPack bus to operate synchronously with the MC680x0 local bus clock Setting it to a 0 will enable 8MHz operation In this mode the IndustryPack bus cycles and 680 0 local bus cycles operate asynchronously The IP32 bit controls clock synchronization logic It does not change the clock frequency on the bus Jumper J14 controls the IP bus clock source If J14 pins 1 and 2 are jumpered then the IP clock source is set to 8MHz For this setting the IP32 control bit must be a 0 If pins 3 and 2 are jumpered then the IP clock source is set to be synchronous with the 680 0 local bus clock This clock may be 25MHz 30MHz or 32MHz depending on the model For this setting the IP32 control bit must be 1 4 28 Computer Group Literature Center Web Site Programming Model DMA Arbitration Control Register The DMA arbitration control register contents determine whether a fixed or fair arbitration algorithm is used to determine how MC680x0 local bus is attached to the internal DMA data paths ADR SIZ FFFBCO1E 8 bits BIT 7 6 5 4 3 2 1 0
209. e of the Proper Use of Bus Timers in Chapter 1 for more information The access timer logic is duplicated in the VMEchip2 and Petra MC2 ASIC Because the local bus timer in the VMEchip2 can detect an offboard access and the Petra MC2 local bus timer cannot the timer in the VMEchip2 is used in all cases except when a No VMEbus Interface configuration is implemented http www motorola com computer literature 3 9 MC2 Functions Petra MC2 Registers Memory Map The register map and address of the Petra ASIC s MC2 memory controller sector is documented in the following table If the register is depicted as a 32 bit entity it must be accessed as a longword If it is accessed as a byte or word the cycle is terminated with an error If the register is depicted as an 8 or 16 bit entity it can be accessed as a byte word or longword Table 3 4 Petra MC2 Functions Register Map MC2 Sector Base Address FFF42000 Offset D31 D24 D23 D16 D15 D8 D7 D0 00 MC2 Chip ID MC2 Chip General Interrupt Vector Revision Control Base Register 04 Tick Timer 1 Compare Register 08 Tick Timer 1 Counter Register 0C Tick Timer 2 Compare Register 10 Tick Timer 2 Counter Register 14 LSB Prescaler Prescaler Tick Timer 2 Tick Timer 1 Count Register Clock Adjust Control Control 18 Tick Timer 4 Tick Timer 3 Tick Timer 2 Tick Timer 1 Interrupt Control Interrupt Control
210. e wide range of EPROM speeds the contents can be changed by software to adjust for a specific speed ADR SIZ FFF42040 8 bits BIT 23 22 21 20 19 18 17 16 NAME ROMO ET2 R R R W R R W R W R W RESET 0 0 0 0 1 PL 2 0 EPROM access time is controlled by the state of ET2 ETO The following table defines the ET2 ETO encoding note that for the MVME1X2P4 whose bus frequency is 2 the processor frequency only the 33MHz column applies ET2 EPROM Access N EPROM Access N ETO at 25MHz where N at 33MHz where N 0 60 ns 40 ns 1 100 ns 70 ns 2 140 ns 100 ns 3 180 ns 130 ns 4 220 ns 160 ns 5 260 ns 190 ns 6 300 ns 210 ns 7 340 ns 240 ns ROMO Refer to the table on the Local Bus Memory Map Note 1 in Chapter 1 3 38 Computer Group Literature Center Web Site Programming Model Flash Access Time Control Register MVMEI X2P4 is populated with 120ns Flash memory device Due to the wide range of Flash speeds the contents can be changed by software to adjust for a specific speed ADR SIZ FFF42040 8 bits BIT 15 14 13 12 11 10 9 8 NAME FWEN FT2 OPER R R R R R W R W R W R W RESET 0 0 0 0 0 1PL 1 PL 1 PL FWEN A Flash write enable function is internal to the ASIC for the Petra MC2
211. ecause hardware duplicates control register writes to both MCECCs clearing ERRLOG in one MCECC sector clears it in the other Any available error information in either MCECC should be recovered before clearing ERRLOG Error Address Bits 31 24 This register reflects the value that was on bits 31 24 of the local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43060 2nd FFF43160 8 bits BIT 31 30 29 28 27 26 25 24 EA31 EA30 29 EA28 EA27 EA26 25 EA24 OPER R R R R R R R R RESET OPLS 8 OPLS OPLS OPLS OPLS OPLS 0PLS Error Address Bits 23 16 This register reflects the value that was on bits 23 16 of the local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43064 2nd FFF43164 8 bits BIT 31 30 29 28 27 26 25 24 NAME 23 EA22 EA21 EA20 19 18 EA17 EA16 OPER R R R R R R R R RESET OPLS 8 OPLS OPLS OPLS OPLS OPLS 0PLS 5 28 Computer Group Literature Center Web Site Programming Model Error Address Bits 15 8 This register reflects the value that was on bits 15 8 of the local MC680x0 address bus at the last logging of an error ADR SIZ 1st FFF43068 2nd FFF43168 8 bits BIT 31 30 29 28 27 26 25 24 15 14 EA13 EA12 10 EA9 8 OP
212. ector Base Address FFFBCOOO Register Register Register Bit Names Offset Name D7 D6 05 04 D3 D2 D1 DO DMAC for IndustryPack c request 0 This register set is referred to in the text 50 DMA_c 0 DLBE 0 IPEND CHANI TBL IPTO DONE STATUS 51 DMA_c INT 0 0 DINT DIEN DICLR DIL2 DILO CTRL 52 DMA 0 0 0 0 0 0 0 ENABLE 53 RESERVED 0 0 0 0 0 0 0 0 554 DMA_c DHALT 0 DTBL ADMA WIDTHI WIDTHO 0 XXX CONTROL 1 55 DMA c INTE 0 DMAEI DMAEO ENTO TOIP 0 0 CONTROL 2 556 RESERVED 0 0 0 0 0 0 0 0 57 RESERVED 0 0 0 0 0 0 0 0 558 DMA_c LB LBA31 LBA30 LBA29 LBA28 LBA27 LBA26 LBA25 LBA24 ADDR 59 DMA_c LB LBA23 LBA22 LBA21 LBA20 LBAI9 LBAI18 LBAI7 LBAI6 ADDR 5A DMA cLB 15 14 LBAI3 LBAI2 LBAII LBAIO LBA9 LBA8 ADDR 5B DMA_c LB LBA7 LBA6 5 LBA4 LBA3 LBA2 LBAI LBAO ADDR 55 DMA cIP 0 0 0 0 0 0 0 0 ADDR 5D DMA _c IP IPA23 IPA22 IPA21 IPA20 IPA19 18 17 16 ADDR 5E DMA _c IP 15 14 13 12 IPA11 IPA10 IPAQ IPA8 ADDR 55 DMA_c IP IPA7 IPA6 IPAS 4 IPA2 IPAI IPAO ADDR 60 DMA c 0 0 0 0 0 0 0 0 BYTE CNT 61 DMA c BCNT23 BCNT22 BCNT21 BCNT20 BCNTI9 BCNTIS8 BCNT17 BCNTI6 BYTE CNT 62 DMA c BCNTIS BCNTI4 BCNT13 BCNTI2 BCNTII BCNTIO BCNT9 8 63 DMA_c BCNT7 BCNT6 5 BCNT4 BCNT3 BCNT2 BCNTI BCNTO BYTE CNT 64 DMA c TBL TA3I TA30 TA29 TA28 TA27 TA26 TA25 TA24 ADD
213. ed by disabling scrubbing and making sure that all previous scrubs have completed before performing the test Also note that writing bad checkbits can set the ERRLOG bit in the Error Logger register The writing of checkbits causes the MCECC sector to perform a read modify write to DRAM If the location to which check bits are being written has a single or double bit error data in the location may be altered by the write http www motorola com computer literature 5 17 Functions checkbits operation To avoid this it is recommended that the bit also be set while the RWCKB bit is set A suggested sequence for performing read write checkbits is as follows 1 Stop all scrub operations by clearing all of the STON bits and setting all of the STOFF bits in the Scrub Time On Time Off register A N Set the DERC and RWCKB bits in the Data Control register Perform the desired read and or write checkbit operations Clear the DERC and RWCKB bits in the Data Control register Perform the desired testing related to the location locations that have had their checkbits altered 6 Allow the scrubber to proceed by restoring the STON and STOFF bits to their original state ZFILL DERC ZERO FILL memory when set forces all zeros to be written to the DRAM during any kind of write cycle or scrub cycle It is intended for use with the zero fill function refer to the section on nitialization at t
214. eing serviced The chip includes an arbitration timer preventing a bus lockup when no requester assumes control of the bus after the arbiter has issued a grant Using a control bit this timer can be enabled or disabled When enabled it assumes control of the bus by driving the BBSY signal after 256 usecs releasing it after satisfying the requirements of the VMEbus specification and then re arbitrating any pending bus requests 1 Daisy Chain Driver Complying with the latest revision of the VMEbus specification the System Controller includes an ACK Daisy Chain Driver ensuring that the timing requirements of the ACK daisy chain are satisfied Bus Timer The Bus Timer is enabled disabled by software to terminate a VMEbus cycle by asserting BERR if any of the VMEbus data strobes is maintained in its asserted state for longer than the programmed time out period The time out period can be set to 8 64 or 256 secs The bus timer terminates an unresponded VMEbus cycle only if both it and the system controller are enabled http www motorola com computer literature 2 17 VMEchip2 Reset Driver In addition to the VMEbus timer the chip contains a local bus timer This timer asserts the local TEA when the local bus cycle maintained in its asserted state for longer that the programmed time out period This timer can be enabled or disabled under software control The time out period can be programmed for 8 64 or 256 seconds
215. emory card is used Also memory should not be sized using write operations if write posting is enabled I O areas that have holes should not be write posted if software may access non existent memory Using the programmable map decoders write posting can be enabled for safe areas and disabled for areas which are not safe Block transfer is not supported because the MC680x0 block transfer capability is not compatible with the VMEbus The VMEbus master supports dynamic bus sizing When a local device initiates a quad byte access to a VMEbus slave that only has the D16 data transfer capability the chip executes two double byte cycles on the VMEbus acknowledging the local device after all requested four bytes 2 6 Computer Group Literature Center Web Site Functional Blocks have been accessed This enhances the portability of software because it allows software to run on the system regardless of the physical organization of global memory Using the local bus map decoder attribute register the AM code that the master places on the VMEbus can be programmed under software control The VMEchip2 includes a software controlled VMEbus access timer It starts ticking when the chip is requested to do a VMEbus data transfer or an interrupt acknowledge cycle The timer stops ticking once the chip has started the data transfer on the VMEbus If the data transfer does not begin before the timer times out the timer drives the local bus
216. ent incorrect de la batterie Remplacer uniquement avec une batterie du m me type ou d un type quivalent recommand par le constructeur Mettre au rebut les batteries usag es conform ment aux instructions du fabricant Explosionsgefahr bei unsachgem Dem Austausch der Batterie Ersatz nur durch denselben oder einen vom Hersteller empfohlenen Typ Entsorgung gebrauchter Batterien nach Angaben des Herstellers Notice European Community Motorola Computer Group products with the CE marking comply with the EMC Directive 89 336 EEC Compliance with this directive implies conformity to the following European Norms EN55022 Limits and Methods of Measurement of Radio Interference Characteristics of Information Technology Equipment this product tested to Equipment Class EN50082 1 1997 Electromagnetic Compatibility Generic Immunity Standard Part 1 Residential Commercial and Light Industry System products also fulfill EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC safety performance In accordance with European Community directives a Declaration of Conformity has been made and is on file within the European Union The Declaration of Conformity is available on reque
217. er or a watchdog time out When this status bit is high the SYSFAIL signal line on the VMEbus is asserted When this status bit is low the SYSFAIL signal line on the VMEbus is not asserted When this status bit is high the VMEchip2 is configured as system controller When this status bit is low the VMEchip2 is not configured as system controller 2 70 Computer Group Literature Center Web Site LCSR Programming Model Watchdog Timer Control Register ADR SIZ BIT 23 FFF40060 8 bits of 32 21 20 19 18 17 16 NAME SRST WDCS WDCC WDTO WDBFE WDS L WDRSE WDEN OPER C R R W R W R W R W RESET 0 PS 0 OPSL OPSL 1 PSL OPSL WDEN WDRSE WDS L WDBFE WDTO WDCC When this bit is high the watchdog timer is enabled When this bit is low the watchdog timer is not enabled When this bit is high and a watchdog time out occurs a SYSRESET or LRESET is generated The WDS L bit in this register selects the reset When this bit is low a watchdog time out does not cause a reset When this bit is high and the watchdog timer has timed out and the watchdog reset enable WDRSE bit in this register is high a SYSRESET signal is generated on the VMEbus which in turn causes LRESET to be asserted When this bit is low and the watchdog timer has timed out and the watchdog reset enable WDRSE bit in this register is high an LRESET signal is
218. er 16 bits of the VMEbus address to be provided by the address translation address register rather than the upper 16 bits of the local bus http www motorola com computer literature 2 37 VMEchip2 Each of the four programmable local bus map decoders has a starting address an ending address an address modifier register with attribute bits and an enable bit The fourth decoder also has address translation registers The addresses and bit definitions for these registers are in the tables below A local bus slave map decoder is programmed by loading the starting address of the segment into the starting address register and the ending address of the segment into the ending address register The address modifier code is programmed into the address modifier register Because the local bus to V MEbus interface does not support VMEbus block transfers block transfer address modifier codes should not be programmed The address translation register allows a local bus master to view a portion of the VMEbus that may be hidden by onboard resources or an area of the VMEbus may be mapped to two local address For example some devices in the I O map may support write posting while others do not The VMEbus area in question may be mapped to two local bus addresses one with write posting enabled and one with write posting disabled The address translation registers allow local bus address bits A31 through 16 to be modified The address translatio
219. er Clock Adjust Control Control 18 Tick Timer 4 Tick Timer 3 Tick Timer 2 Tick Timer 1 Interrupt Control Interrupt Control Interrupt Control Interrupt Control 1C DRAM Parity Error SCC Interrupt Tick Timer 4 Tick Timer 3 Interrupt Control Control Control Control 20 DRAM Space Base Address Register SRAM Space Base Address Register 24 DRAM Space DRAM SRAM SRAM Space Reserved Size Options Size 28 LANC Error Status Reserved LANC Interrupt LANC Bus Error Control Interrupt Control 2C SCSI Error Status General Purpose Board Version SCSI Interrupt Inputs Control 30 Tick Timer 3 Compare Register 34 Tick Timer 3 Counter Register 38 Tick Timer 4 Compare Register 3C Tick Timer 4 Counter Register 40 Bus Clock EPROM Access Flash Parameter ABORT Switch Time Control Control Interrupt Control 44 RESET Switch Watchdog Timer Access Watchdog Reserved Control Control Time Base Select 48 DRAM Control Reserved MPU Status Reserved 4C 32 bit Prescaler Count Register http www motorola com computer literature 1 23 Board Description and Memory Maps The following memory map table includes all devices selected by the Petra IP2 sector map decoder Table 1 7 Petra IP2 Functions Overall Memory Map Address Range Selected Device Port Width Size Programmable IP_a IP_ab Memory Space D32 D8 64KB 16MB Programmable IP_b Memory Space D16 D8 64KB 8MB Programmable IP_c IP_cd Memory
220. er bit descriptions for the MVME162P 244 and 344 as well as the MVME172P 644 series of embedded controllers known collectively as the MVME1X2P4 because they are equipped with the Petra chip and accommodate up to four IP modules The Petra chip that distinguishes MVMEI X2P4 embedded controllers is an application specific integrated circuit ASIC which combines the functions previously covered by the MC2 chip the IP2 chip and the MCECC chip in a single ASIC As of the publication date the information presented in this manual applies to the following MVME1X2P4 models Model Number MVME162P 244L Characteristics 25MHz 68LC040 16MB SDRAM 2 SIO 4 DMA IP MVME162P 244LE 25MHz 68LC040 16MB SDRAM 2 SIO 4 DMA IP Ethernet MVME162P 244LSE 25MHz 68LC040 16 SDRAM 2 SIO 4 DMA IP SCSI Ethernet MVME162P 344 32MHz 68040 16 SDRAM 2 SIO 4 DMA IP MVME162P 344S 32MHz 68040 16 SDRAM 2 SIO 4 DMA IP SCSI MVME162P 344E 32MHz 68040 16 SDRAM 2 SIO 4 DMA IP Ethernet MVME162P 344SE MVME172P 644L 32MHz 68040 16 SDRAM 2 SIO 4 DMA IP SCSI Ethernet 64MHz 68LC060 16 SDRAM 2 SIO 4 DMA IP MVME172P 644LE 64MHz 68LC060 16MB SDRAM 2 SIO 4 DMA IP Ethernet MVME172P 644LSE 60MHz 68060 16 SDRAM 2 SIO 4 DMA IP SCSI Ethernet If the part number of your board includes for example MVMEI162PA 244L your board i
221. erally higher than that of the logic it replaces the MCECC pair and EDO DRAMs software will take less time to execute This could change the behavior of certain applications Table 5 2 Memory System Cycle Timing Access Memory States Description Idle Active Hit Active Miss Read Single 4 clock cycles 3 clock cycles 5 clock cycles Read Burst 4 1 1 1 clock cycles 3 1 1 1 clock cycles 5 1 1 1 clock cycles Write Burst 2 1 1 1 clock cycles 2 1 1 1 clock cycles 2 1 1 1 clock cycles Write Longword 2 clock cycles 2 clock cycles 2 clock cycles Write 1 or 2 9 clock cycles 8 clock cycles 10 clock cycles Bytes Cache Coherency The MCECC sector supports the MC680x0 caching scheme on the local bus by always providing 32 bits of valid data during DRAM read cycles regardless of the number of bytes requested by the local bus master for the cycle It also supports cache coherency by monitoring the memory inhibit MI signal For a write or read cycle the MCECC sector always waits for MI to be negated before it begins a read or write cycle to the DRAM If another local bus slave asserts TA or TEA before is negated then the MCECC sector never begins the DRAM write cycle Computer Group Literature Center Web Site Functional Description ECC The Petra MCECC sector pair performs single bit error correction and double bit error detection SECDED Since the SDRAM device can deliver data fr
222. erness Way East Revision 10c Englewood CO 80112 5704 4 Computer Group Literature Center Web Site Numerics 53C710 SCSI controller interface 3 5 82596CA LAN interface 3 3 A A16 D16 space VMEbus 2 37 A16 D16 space VMEchip2 ASIC 2 6 A16 D32 space VMEbus 2 37 A16 D32 space VMEchip2 ASIC 2 6 A24 D16 space VMEbus 2 37 2 51 A24 D16 space VMEchip2 ASIC 2 6 A32 D16 space 2 37 A32 D16 space VMEbus 2 51 A32 D16 space VMEchip2 ASIC 2 6 ABORT switch interrupt address 1 9 AC fail interrupter VMEbus 2 19 access cycles VMEbus 2 34 access timer VMEbus 2 7 ACFAIL signal line 2 19 2 96 adder in address translation 2 31 2 32 2 35 adders VMEchip2 2 27 address GCSR VMEchip2 1 40 2 100 LCSR VMEchip2 2 20 VMEbus resources 2 37 address counter VMEbus 2 13 address decoders 1 13 address modifier codes 2 43 2 44 address modifier codes DMAC 2 58 address modifier register VMEbus slave 2 38 address modifier select bits 2 33 2 36 address range devices 1 11 local bus 2 39 address space decoding 1 13 address translation address register 2 38 address translation address register slave map decoder 2 27 address translation registers 2 38 address translation registers slave map decoder 2 27 address translation select register 2 38 address translation select register slave map decoder 2 27 address Ethernet 1 37 addressed DMA aDMA 4 4 addressing capabilities local bus to IndustryPa
223. error signal and sets the appropriate status bit in the Local Control and Status Register LCSR Using control bits in the LCSR the timer can be disabled or it can be enabled to drive the local bus error signal after 64 us 1 ms or 32 ms The VMEchip2 includes a software controlled VMEbus write post timer It starts ticking when a data transfer to the VMEbus is write posted The timer stops ticking once the chip has started the data transfer on the VMEbus If this does not happen before the timer times out the chip aborts the write posted cycle and sends an interrupt to the local bus interrupter If the write post bus error interrupt is enabled in the local bus interrupter the local processor is interrupted to indicate a write post time out has occurred The write post timer has the same timing as the VMEbus access timer Local Bus to VMEbus Requester The requester provides all the signals necessary to allow the local bus to VMEbus master to request and be granted use of the VMEbus The chip connects to all signals that a VMEbus requester is required to drive and monitor Requiring no external jumpers the chip provides the means for software to program the requester to request the bus on any one of the four bus request levels automatically establishing the bus grant daisy chains for the three inactive levels http www motorola com computer literature 2 7 VMEchip2 The requester requests the bus if any of the following con
224. esent Also enables MCECC functionality Refer to Chapter 5 7 16MB http www motorola com computer literature MC2 Functions 571 570 57 bits indicate the size of the SRAM array Software must initialize the SRAM Space Size register SFFF42024 bits 9 8 based on the value of 571 570 571 570 are initialized at reset to a value which is determined by the contents of a factory programmed resident device Table 3 8 SRAM Size Control Bit Encoding 571 570 SRAM Configuration 0 128KB 1 512KB 2 1MB 3 2MB F0 FO set to a 0 indicates that one 2820165 A 2M x 8 Flash memory device is used FO set to a 1 indicates that four 28F020 256K x 8 Flash memory devices are used SRAM Space Size Register ADR SIZ FFF42024 8 bits BIT 15 14 13 12 11 10 9 8 NAME SEN 571 570 R RESET SRAM ENABLE must be set to 1 before the SRAM be accessed 571 570 size bits configure the SRAM decoder for a particular memory size The following table defines their use Note that the table specifies the allowed bit combinations for 521 570 Any other combinations generate unpredictable results 3 28 Computer Group Literature Center Web Site Programming Model SZ1 SZO are set equal to 571 570 bits of the DRAM SRAM Options register 571 570 are programmable to facilitate diagnostic software Table 3 9 SRAM Size Control Bi
225. eset These are read only registers Writes to these registers are terminated without exception but do not change their contents ADR SIZ FFF4202C 8 bits BIT 15 14 9 8 NAME V7 V6 VO OPER R R R RESET Application Specific vo VO and V4 indicate the speed of the processor and local bus Refer to the following table for the bit definitions Board V0 v4 Processor Type Frequency 0 25 25MHz 0 MC68LC040 MVME162P4 1 32 32MHz 1 MC68040 1 64 32MHz 0 MC68LC060 MVME172P4 1 60 30MHz 1 MC68060 32MHz not applicable to MC68LC040 V0 always set to 1 on MVME172P4 boards 3 34 Computer Group Literature Center Web Site Programming Model 1 V2 4 5 V6 V7 set to a 1 indicates that the VMEchip2 ASIC is not present V1 setto a O indicates that a VMEbus interface is present If V1 20 the MC2 sector reset logic and local bus access timer are inhibited V2 set to a 1 indicates that the SCSI interface is not present V2 set to 0 indicates that an SCSI interface is present V3 set to a 1 indicates that the Ethernet interface is not present V3 set to a 0 indicates that an Ethernet interface is present V4 set to a 1 indicates that the 680 0 is present V4 set to a 0 indicates that an MC68LCOXO is present Reserved for internal use only 0 indicates the board is an MVME1X2P4 model P2 I O and 4 Indus
226. ess Register 2 2 40 Ending Address Register 3 2 41 Ending Address Register 4 2 42 Starting Address Register 1 2 40 Starting Address Register 2 2 41 Starting Address Register 3 2 41 Starting Address Register 4 2 42 local bus slave composition of 2 4 local bus timer Petra MC2 ASIC 3 9 VMEchip2 ASIC 2 18 local bus to IndustryPack addressing 4 49 local bus to VMEbus Enable Control register 2 49 Control register 2 50 interface 1 9 interface VMEchip2 2 4 map decoders programming 2 37 requester 2 7 requester register programming 2 51 IN 6 Computer Group Literature Center Web Site location monitors interrupters VMEbus 2 19 LMO0 LMG VMEchip2 ASIC 2 100 status register VMEchip2 ASIC 2 101 LVFAIR bit VMEchip2 ASIC 2 8 M M48T58 memory map 1 33 manufacturers documents C 2 map decoders 2 4 2 37 GCSR 1 40 VMEbus interface 1 40 VMEchip2 ASIC 2 6 2 9 master interrupt enable MIEN bit 2 74 2 96 3 12 MCI MC2 mode and Flash write protection 1 16 3 39 MC2 chip ASIC see Petra ASIC MC2 functions 1 5 MC2 functions 3 1 features 3 1 initialization 3 2 memory map 1 23 MC2 sector ABORT Switch Interrupt Control register 3 40 Access and Watchdog Time Base Select register 3 43 Bus Clock register 3 37 DRAM Control register 3 44 DRAM Parity Error Interrupt Control register 3 21 DRAM Space Base Address register 3 24 DRAM Space Size register 3 25 DRAM SRAM Options register 3 27 Flash Access Time Control register
227. evices 1 0 1 SDRAM device is 128MBit x 8 data with two banks composed of 5 devices each 1 1 0 reserved 1 1 reserved http www motorola com computer literature 5 33 MCECC Functions Initialization Most DRAM vendors require that the DRAMs be subjected to some number of access cycles before the DRAMs are fully operational The MCECC does not perform this initialization automatically but depends on software to perform enough dummy accesses to DRAM to meet the requirement The number of cycles required is fewer than 10 If there are multiple blocks of DRAM software has to perform at least 10 accesses to each block The MCECC pair provides a fast zero fill capability The sequence shown below performs such a zero fill It zeroes all of the DRAM controlled by this MCECC pair at the rate of 100 when the BCLK pin is operating at 25MHz This sequence may have to be altered to perform the scrub more slowly if the scrub causes the DRAM to consume too much power at full speed 1 Make sure that the scrubber is disabled by clearing the SCRBEN bit in the Scrub Control register Clear bit 27 of offset 24 2 Make sure that the scrubber is done with any old scrub cycles by waiting for the SCRB bit in the Scrub Control register to be cleared Wait for bit 28 of offset 24 0 3 Discontinue all accesses from the MC680x0 bus to the DRAM 4 Ensure that all accesses have stopped by clearing the RAMEN bit i
228. f not already logged 5 6 Computer Group Literature Center Web Site Functional Description 4 Notify the local MPU via interrupt if so enabled Triple or Greater Bit Error Cycle Type Non Burst Write Some of these errors are detected correctly and are handled the same as a double bit error The rest may show up as no error or single bit error both of which are incorrect Single Bit Error Cycle Type Scrub 1 Write corrected data to the DRAM 2 Log the error if not already logged 3 Notify the local MPU via interrupt if so enabled Double Bit Error Cycle Type Scrub 1 Do not perform the write portion of the cycle This causes the location to continue to indicate a non correctable error when accessed 2 Log the error if not already logged 3 Notify the local MPU via interrupt if so enabled Triple or Greater Bit Error Cycle Type Scrub Some of these errors are detected correctly and are treated the same as a double bit error The rest may show up as no error or single bit error both of which are incorrect http www motorola com computer literature 5 7 Functions Error Logging Scrub Refresh ECC error logging is facilitated by the Petra MCECC sector because of its internal latches When an error single or double bit occurs in the to which the MCECC sector is connected it freezes the address of the error and the syndrome bits associated with the
229. function FWEN set to a 1 enables writes to the Flash memory space FWEN set to a 0 inhibits writes to the Flash memory but the cycle completes without exception The Petra ASIC supports both MCI ASIC MC2 ASIC modes of Flash write protection The mode is controlled by a board level configuration jumper J24 J24 enables or inhibits all Flash writes The associated switch S5 pin 4 must be in the MC2 Flash write enable mode to enable FWEN bit functionality The following table shows the correspondence between the settings of J24 and S5 Flash Write Mode J24 S5 Pin 4 No write possible Out Don t care MCI mode In Open MC2 mode In Closed For a definition of the Flash write enable function refer to the BBRAM memory map http www motorola com computer literature 3 39 MC2 Functions FT2 FTO Flash memory access time is controlled by the state of FI2 FTO The following table defines the FT2 FTO encoding for the MVME1X2P4 whose bus frequency is 2 the processor frequency only the 33MHz column applies FT2 Flash Access N Flash Access N FTO at 25MHz where N at 33MHz where N 0 60 ns 40 ns 1 100 ns 70 ns 2 140 ns 100 ns 3 180 ns 130 ns 4 220 ns 160 ns 5 260 ns 190 ns 6 300 ns 210 ns 7 340 ns 240 ns ABORT Switch Interrupt Control Register The following table describes the ABORT switch interrupt logic in the Petra
230. ght software interrupts in MVMEIX2P4 versions equipped with the Interrupts VMEchip2 ASIC VO Two EIA 232 D EIA 530 EIA 422 or EIA 425 configurable serial ports via front panel and transition module Optional SCSI interface with DMA via P2 or LCP2 adapter board Optional Ethernet transceiver interface via DB15 connector on transition module Four MVIP IndustryPack interface channels with DMA 1 6 Computer Group Literature Center Web Site Overview Table 1 1 MVME1X2P4 Features Summary Continued Feature MVME162P4 MVME172P4 VMEbus VMEbus system controller functions interface VMEbus to local bus interface A32 A24 D32 D16 D8 Local bus to VMEbus interface A16 A24 A32 D8 D16 D32 Programmable interrupter and interrupt handler Global Control Status register for interprocessor communications capability for fast local memory V MEbus transfers A16 A24 A32 D16 D32 D16 D32 D64 BLT Switches Two pushbutton switches ABORT and RESET Status Indicators Eight LEDs Board Fail FAIL CPU Status STAT CPU Activity RUN System Controller SCON LAN Activity LAN Fuse Status FUSE SCSI Activity SCSI VME Activity VME Applicable Industry Standards These boards conform to the requirements of the following documents VMEbus Specification IEEE 1014 87 EIA 232 D Serial Interface Specification EIA SCSI Specification ANSI IndustryPack Specification GreenSpring
231. gister DMAC 2 63 status register MPU DMAC 2 62 supervisor address modifier code VMEbus 2 50 VMEchip2 ASIC 2 50 supervisory access cycles VMEbus 2 34 2 37 switches ABORT and RESET 1 7 syndrome decoding 5 36 SYSFAIL interrupter 2 19 SYSFAIL signal line 2 19 2 70 2 96 SYSRESET function VMEchip2 ASIC 2 15 SYSRESET signal 2 18 2 71 system controller function VMEchip2 ASIC 2 70 enable disable 2 17 T TAS cycles 1 51 TEA signal bus error 1 41 Tick Timer 3 and 4 Control registers 3 23 IN 10 Computer Group Literature Center Web Site tick timers 1 6 interrupters 2 19 periodic interrupt example xxiii B 1 Petra MC2 ASIC 3 8 VMEchip2 2 14 time of day clock 1 6 memory map 1 33 1 35 time out local bus 1 41 VMEbus access 1 42 time out period VMEbus 2 17 time out period watchdog 2 66 timer registers VMEchip2 ASIC Board Control register 2 70 DMAC time on off timers 2 65 Prescaler Control register 2 67 Prescaler counter 2 73 Tick Timer 1 Compare register 2 68 Tick Timer 1 Control register 2 73 Tick Timer 1 counter 2 68 Tick Timer 2 Compare register 2 69 Tick Timer 2 Control register 2 72 Tick Timer 2 counter 2 69 VME Access Local Bus and Watchdog Time Out Control register 2 66 VMEbus Arbiter Time Out Control register 2 64 VMEbus global time out timer 2 65 Watchdog Timer Control register 2 71 timers 1 6 timers VMEbus 2 7 transfer mode VMEbus 2 12 Transfer Type TT signals 1 11 transition boards 1
232. he bus maintain mastership for a specific amount of time and then after relinquishing it refrain from requesting it for another specific amount of time No Address Increment DMA Transfers During normal memory to memory DMA transfers the DMA controller is programmed to increment the local bus and VMEbus address This allows a block of data to be transferred between VMEbus memory and local bus memory In some applications it may be desirable to transfer a block of data from local bus memory to a single VMEbus address This single VMEbus address may be a FIFO or similar type device which can accept a large amount of data but only appears at single VMEbus address The controller provides support for these devices by allowing transfers without incrementing the VMEbus address The DMA controller also allows DMA transfers without incrementing the local bus address although the MVME1X2P4 has no onboard devices that benefit from not incrementing the local bus address The transfer mode on the VMEbus may be D16 D16 BLT D32 D32 BLT or D64 BLT When the no increment address mode is selected some of the VMEbus address lines and local bus address lines continue to increment in some modes This is required to support the various port sizes 2 12 Computer Group Literature Center Web Site Functional Blocks and to allow transfers which are not an even byte count or which start at an odd address with respect to the port size A 16 b
233. he end of this chapter This bit should be cleared for normal system operation When ZFILL is set the read portion of a scrub cycle is suppressed and writes of all zeros are executed DISABLE ERROR CORRECTION when set to 1 disables single bit error correction by the Petra MCECC sector Specifically data read from the DRAM array is presented to the local MC680x0 data bus unaltered Less than line write data performs a read modify write without correcting single bit errors that may occur on the read portion of the read modify write Note that DERC does not affect the generation of check bits DERC should be cleared during normal system operation DERC also allows the write portion of a read modify write to Computer Group Literature Center Web Site Programming Model complete regardless of whether or not there was a multiple bit error during the read portion of the read modify write DERC also affects scrub cycles Scrub Control Register ADR SIZ 1st FFF43024 2nd FFF431 24 8 bits 29 28 27 26 25 24 0 SCRB SCRBEN 0 SBEIEN RWBO R R R W R R W R W RESET 0 PLS 0 PLS 0 PLS 0 PLS 0 PLS X 0 PLS 0 PLS RWBO SBEIEN SCRBEN SCRB RWBO is a general purpose read write bit Setting SBEIEN causes the logging of a single bit error to create a true pulse on the INT signal pin This control bit enables the scrubber to operate When SCRBEN is set the MCECC sect
234. he modifiers to which the MVMEIX2PA responds VMEbus Short I O Memory The VMEchip2 includes a user programmable map decoder for the GCSR The GCSR map decoder allows you to program the starting address of the GCSR in the VMEbus short I O space Software Support Considerations Interrupts The MVMEI X2P4 is a complex board that interfaces to both the VMEbus and the SCSI bus These multiple bus interfaces raise the issue of cache coherency and support of indivisible cycles There are also many sources of bus error First let us consider how interrupts are handled The MC680x0 uses hardware vectored interrupts Most interrupt sources are level and base vector programmable Interrupt vectors from the Petra MC2 sector and the VMEchip2 have two sections a base value which can be set by the processor usually the upper four bits and the lower bits which are set according to the particular interrupt source There is an onboard daisy chain of interrupt sources with interrupts from the Petra MC2 sector having the highest priority those from the Petra IP2 sector having the next highest priority and interrupt sources from the VMEchip2 having the lowest priority Refer to Appendix B for an example of interrupt usage The VMEchip2 ASIC and the MC2 and IP2 sectors of the Petra chip are used to implement the multilevel MC68030 interrupt architecture A PLD programmable logic device is used to combine the individual IPLx signals from each
235. hen an interrupt status bit is high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are 0 SIGO SIG1 SIG2 SIG3 DMA VIA GCSR LMO interrupt GCSR LM1 interrupt GCSR SIGO interrupt interrupt GCSR SIG2 interrupt GCSR SIG3 interrupt DMAC interrupt VMEbus interrupter acknowledge interrupt 2 78 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Status Register bits 8 15 ADR SIZ FFF40068 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME SW7 SW6 SW5 SWA SW3 SW2 SWI SWO OPER R R R R R R R R RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the local bus interrupter status register When an interrupt status bitis high a local bus interrupt is being generated When an interrupt status bit is low a local interrupt is not being generated The interrupt status bits are Swo SWI1 SW2 SW3 Sw4 SWS SW6 SW7 Software 0 interrupt Software 1 interrupt Software 2 interrupt Software 3 interrupt Software 4 interrupt Software 5 interrupt Software 6 interrupt Software 7 interrupt http www motorola com computer literature 2 79 VMEchip2 Local Bus Interrupter Status Register bits 0 7 ADR SIZ FFF40068 8 bits of 32 BIT
236. hese bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 4 Because the local bus to VMEbus interface does not support block transfers the block transfer address modifier codes should not be used WP When this bit is high write posting is enabled to the segment defined by map decoder 4 When this bit is low write posting is disabled to the segment defined by map decoder 4 D16 When this bit is high D16 data transfers are performed to the segment defined by map decoder 4 When this bit is low D32 data transfers are performed to the segment defined by map decoder 4 http www motorola com computer literature 2 43 VMEchip2 Local Bus Slave VMEbus Master Attribute Register 3 ADR SIZ FFF40028 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME D16 WP AM OPER R W R W R W RESET OPS OPS OPS This register is the attribute register for the third local bus to VMEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 3 Because the local bus to V MEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to the segment defined by map decoder 3 When this bit is low write posting is disabled to the segment defined by map decode
237. his bit is low the early release feature of bus busy feature on the VMEbus is not disabled DISMST When this bit is high the VME LED on the MVME1X2P4 illuminates on assertion of Local Bus Reset or when the VMEchip2 ASIC is driving Local Bus Busy When this bit is low VME LED on the MVME1 X2P4 illuminates on assertion of Local Bus Reset when the VMEchip2 is driving Local Bus Busy or when the VMEchip2 is driving the VMEbus address strobe DISSRAM When this bit is high the SRAM decoder in the VMEchip2 is disabled When this bit is low the SRAM decoder in the VMEchip2 is enabled Because the SRAM decoder in the VMEchip2 is not used on the MVMEI1X2P4 this bit must be set REVEROM This function is not used on MVME1X2P4 This bit must not be set MPIRQEN This function is not used on the MVMEI X2P4 This bit must not be set http www motorola com computer literature 2 99 VMEchip2 GCSR Programming Model This section describes the programming model for the Global Control and Status Registers GCSR in the VMEchip2 The local bus map decoder for the GCSR registers is included in the VMEchip2 The local bus base address for the GCSR is FFF40100 The registers in the GCSR are 16 bits wide and they are byte accessible from both the VMEbus and the local bus The GCSR is located in the 16 bit VMEbus short I O space and it responds to address modifier codes 29 or 2D The address of the GCSR as viewed from the VMEbus
238. his bit is high interrupts from and via the Petra MC2 sector are allowed to reach the MPU When it is low all interrupts from the MC2 Computer Group Literature Center Web Site Programming Model sector are disabled Also when the bit is low all interrupt acknowledge cycles to the Petra MC2 chip are passed on via the IACKOUT pin This bit is cleared by a reset SCCIT lt 1 0 gt These bits define the IACK daisy chain time for the SCC chips They must be set based on the number of SCC devices SCCIT lt 1 0 gt Number of Z85230s 00 1 01 2 10 3 11 4 Because MVME1X2P4 boards contain a single 785230 device the SCCIT bits must be initialized to 00 for these boards Caution Interrupt Vector Base Register The interrupt vector base register is an 8 bit read write register that is used to supply the vector to 8 0 0 during interrupt acknowledge cycles Only the most significant four bits are used The least significant four bits encode the interrupt source during the acknowledge cycle The exception to this rule is that after reset occurs the interrupt vector passed is 0F which remains in effect until a write is generated to the vector base register http www motorola com computer literature 3 13 MC2 Functions A normal read access to the vector base register yields the value 0F if the read happens before it has been initialized A normal read access yields all Os on b
239. ibed the VMEchip2 as used on the MVME1X2P4 includes an adder which can be used for address translation When the adder is enabled the local bus address is generated by adding the offset value to the VMEbus address lines VA lt 31 16 gt The offset is the value in the address translation offset register If the VMEbus transfer is A24 then the VMEbus address lines VA lt 31 24 gt are forced to 0 before the addition The adders are enabled by setting bit 11 for map decoder 1 and bit 27 for map decoder 2 in register http www motorola com computer literature 2 27 VMEchip2 FFF40010 The adders allow any size board to be mapped on any 64KB boundary The adders are disabled and the address replacement method is used following reset Write posting is enabled for the segment by setting the write post enable bit in the attribute register Local bus snooping for the segment is enabled by setting the snoop bits in the attribute register The snoop bits in the attribute register are driven on to the local bus when the VMEbus to local bus interface is local bus master VMEbus Slave Ending Address Register 1 ADR SIZ FFF40000 16 bits of 32 BIT 31 has 16 NAME Ending Address Register 1 OPER R W RESET 0 PS This register is the ending address register for the first VMEbus to local bus map decoder VMEbus Slave Starting Address Register 1 ADR SIZ FFF40000 16 bits of 32 BIT 15 iss 0 NAME S
240. identifier in ASCII assigned to the optional fourth IndustryPack module IP d Eight bytes are reserved for the serial number in ASCII assigned to the optional fourth IndustryPack module IP d Eight bytes are reserved for the printed wiring board PWB number assigned to the optional fourth IndustryPack module IP d Growth space 65 bytes is reserved This pads the structure to an even 256 bytes The final byte of the area is reserved for a checksum as defined in the Debugging Package for Motorola 68K CISC CPUs User s Manual for security and data integrity of the configuration area of the NVRAM This data is stored in hexadecimal format Interrupt Acknowledge Map The local bus distinguishes interrupt acknowledge cycles from other cycles by placing the binary value 11 on 1 It also specifies the level that is being acknowledged using TM2 TMO The interrupt handler selects which device within that level is being acknowledged VMEbus Memory Map This section describes the mapping of local resources as viewed by VMEbus masters Default addresses for the slave master and GCSR address decoders are provided by the ENV command http www motorola com computer literature 1 39 Board Description and Memory Maps VMEbus Accesses to the Local Bus The VMEchip2 includes a user programmable map decoder for the VMEbus to local bus interface The map decoder allows you to program the starting and ending address and t
241. il certain areas of the text in this manual are printed in italics and marked with change bars as is done here Readers should compare those sections to the corresponding sections of the first generation manuals I O Routing Two DB25 front panel I O connectors furnish the I O connection for the serial ports The balance of the I O is routed to the VMEbus P2 connector A P2 transition board and cables link the main board to a user selected transition board http www motorola com computer literature 1 3 Board Description and Memory Maps Previous memory model emulates parity memory may be desirable for compatibility with existing implementations Petra Memory Controller New memory model has error correction circuitry may be desirable for the improved performance or in applications where memory requirements exceed 16MB 2610 9908 Figure 1 1 MVME1X2P4 Memory Control Options The MVME1X2P4 supports the MVME712M and MVME712B transition boards It is also compatible with older discontinued boards of the MVME712 series MVME712 12 MVME712 13 MVME712A or MVME712AM all referred to in this manual collectively as MVME712x unless separately specified These transition boards provide configuration headers serial port drivers and industry standard connectors for the I O devices Though originally designed to support MVME167 boards the MVME712 series transition boards are compatible with the MVME1 X2P4 as well
242. ime Recovery Time with IP 8MHz with IP 32MHz 0 microseconds 0 microseconds 2 microseconds 0 5 microsecond 4 microseconds 1 microsecond o c 8 microseconds 2 microseconds 4 26 Computer Group Literature Center Web Site Programming Model a_ERR b_ERR c_ERR d_ERR There are some restrictions on using recovery timers with double size IndustryPacks When using a double size IndustryPack programmed recovery times for back to back I O and or ID accesses are ensured if a single size access is followed by a single size access or if a double size longword access is followed by a single or double size access However if a single size or byte or word I O or ID access is followed by a double size I O access the double size access may be allowed to happen before the recovery times for both a and b or both c and d have expired This behavior is avoided if I O accesses are restricted to single size only or if they are restricted to double size longword only and the double size accesses are not interspersed with ID accesses Note that memory accesses do not affect nor are they affected by this behavior This bit reflects the state of the ERROR signal from the IP a interface This bit reflects the state of the signal from the IP b interface This bit reflects the state of the ERROR signal from the IP c interface This bit reflects the stat
243. imer can also be disabled for debug purposes Before an MVMEIX2PA access to another MVME1X2P4 can complete however the VMEchip2 on the accessed MVMEIX2P4 must decode a slave access and request the local bus of the second MVMEI X2P4 When the local bus is granted any in process onboard transfers having completed then the local bus timer of the accessed MVMEIX2PA starts Normally this is also set to 256 usec When the memory has the data available a transfer acknowledge signal TA is given This translates into a DTACK signal on the VMEbus which is then translated into a TA signal to the first requesting processor and the transfer is complete If the VMEbus global timer expires on a legitimate transfer the VMEbus to local bus controller in the VMEchip2 may become confused and the VMEchip2 may misbehave therefore the bus timers values must be set correctly The correct settings depend on the system configuration MVME1X2P4 MC680x0 Indivisible Cycles The MC68040 and MC68060 perform operations that require indivisible read modify write RMW memory accesses These RMW sequences occur when the MMU modifies table entries or when the MPU executes a TAS CAS or CAS2 instruction TAS cycles are always single address http www motorola com computer literature 1 51 Board Description and Memory Maps RMW operations while the CAS CAS2 and MMU operations can be multiple address RMW cycles The VMEbus does not support multiple address R
244. imer interrupt on an MVMEIX2PA that has a VMEbus connection Appendix C Related Documentation lists all documentation related to the MVME162P4 and MVME172P4 Comments and Suggestions Motorola welcomes and appreciates your comments on its documentation We want to know what you think about our manuals and how we can make them better Mail comments to Motorola Computer Group Reader Comments DW 164 2900 S Diablo Way Tempe Arizona 85282 You can also submit comments to the following e mail address reader comments mcg mot com In all your correspondence please list your name position and company Be sure to include the title and part number of the manual and tell how you used it Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements xxiii Conventions Used This Manual The following typographical conventions are used in this document dollar specifies a hexadecimal number percent specifies a binary number amp ampersand specifies a decimal number Unless otherwise specified all address references are in hexadecimal An asterisk following the signal name for signals which are level significant denotes that the signal is true or valid when the signal is low An asterisk following the signal name for signals which are edge significant denotes that the actions initiated by that signal occur on high to low transition bold is used for user input
245. imers use of 1 50 byte counter DMAC 2 60 C cache coherency 1 41 MCECC sector 5 4 Petra IP2 chip 4 4 cache inhibit function 1 11 CAS instruction 1 51 cautions for use of reset VMEchip2 2 101 changes from previous boards 1 checksum field board configuration structure 1 39 chip arbiter VMEbus 2 17 chip defaults MCECC sector 5 9 chip ID and revision registers VMEchip2 ASIC 2 100 clear on compare mode VMEchip2 counters 2 15 clock domains IP2 sector 4 6 clock programming IP2 sector 4 44 clocks for VMEchip2 counters and timers 2 67 command chaining mode VMEchip2 DMAC 2 12 2 52 command packets DMAC 2 52 compatibility backward 1 2 1 38 3 6 3 25 configuration bytes data structure of 1 36 CSR decoding in Petra chip 3 25 cycle types memory access 5 5 D data access cycles VMEbus 2 33 2 36 data transfer capabilities local bus to V MEbus interface 2 4 VMEbus to local bus interface 2 9 VMEchip2 DMAC 2 11 data transfer size VMEchip2 DMAC 2 11 data transfers DMA VMEchip2 ASIC 2 52 IN 2 Computer Group Literature Center Web Site data transfers VMEbus 2 43 2 44 decimal number symbol for xxiv decoders programmable 2 4 VMEchip2 2 26 devices normal address range 1 11 DFAIR bit 2 14 differences from previous boards A 1 direct mode DMAC 2 51 DMA control and status registers 4 34 enable function 4 34 implementation IP2 sector 4 4 transfers no address increment 2 12 DMA C
246. iminary and the revision levels of the documents are subject to change without notice Table C 3 Related Specifications Document Title and Source Interface Between Data Terminal Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange EIA 232 D Global Engineering Documents Suite 400 1991 M Street NW Washington DC 20036 Telephone 1 800 854 7179 Telephone 303 397 7956 Web http global ihs com Publication Number ANSI EIA 232 D Standard VME64 Specification IndustryPack Logic Interface Specification Revision 1 0 VITA VMEbus International Trade Association 7825 E Gelding Drive Suite 104 Scottsdale AZ 85260 Telephone 602 951 8866 Web http www vita com ANSI VITA 1 1994 ANSI VITA 4 1995 http www motorola com computer literature C 3 Related Documentation Table C 3 Related Specifications Continued 2 Publication Document Title and Source Number Versatile Backplane Bus VMEbus ANSI IEEE Std 1014 The Institute of Electrical and Electronics Engineers Inc 345 East 47th Street 195 New York 10017 VMEbus Specification This is also Microprocessor System Bus for 1 to 4 Byte Data 821 BUS Bureau Central de la Commission Electrotechnique Internationale 3 rue de Varemb Geneva Switzerland ANSI Small Computer System Interface 2 SCSI 2 Draft Document Global Engineering Documents 3 131 198 15 Inv
247. interrupts are enabled This counter is cleared when the DMAC is enabled DMAC Status Register ADR SIZ FFF40048 8 bits of 32 BIT 7 6 5 4 3 2 1 0 DLBE DLOB TBL DONE 0 5 OPS 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS This is the DMAC status register DONE VME TBL DLTO DLOB This bit is set when the DMAC has finished executing commands either without errors or because the halt bit was set This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received a VMEbus BERR during a data transfer This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received an error on the local bus while it was reading commands from the command packet Additional information is provided in bits 3 6 DLTO DLOB DLPE This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received a TEA and the status indicated a local bus time out This bit is cleared when the DMAC is enabled If this bit is set the DMAC has received a TEA and the status indicated off board This bit is cleared when the DMAC is enabled http www motorola com computer literature 2 63 VMEchip2 DLPE DLBE MLTO If this bit is set the DMAC has received a TEA and the status indicated a parity error during a DRAM data transfer This b
248. ion defined in the IndustryPack specification The programmable clock s clock source is the MC680x0 bus clock This clock input is fed through an 8 bit programmable pre scaling counter whose output is fed to a 16 bit counter The 16 bit counter increments at rising edges of the output of the pre scale logic and clears every time it reaches the value programmed into the 16 bit programmable timer register Depending on its programmed mode the programmable clock output either pulses or toggles each time the 16 bit counter matches and clears Additional control bits in the programmable clock control register allow software to stop start clear and reverse the polarity of the programmable clock output The programmable clock output s programmable frequency range is from approximately 4Hz to 16MHz The programmable clock logic also includes local bus interrupt control Error Reporting The following paragraphs describe the IP2 sector error reporting Error Reporting as a Local Bus Slave The IP2 sector does not have the ability to assert the TEA signal as a local bus slave Because of this the only bus error cycles that should ever be encountered when accessing to or through the 1 2 sector are those that come from an external local bus timer due to no response from an IndustryPack Note that any external local bus timer should be set for no less than 5 microseconds to allow for normal accesses to the slowest IndustryPack Error Reporting as
249. ion monitor interrupters are edge sensitive interrupters connected to the location monitor bits in the GCSR The software 7 0 interrupters can be set by software to generate interrupts The VMEbus 7 1 interrupters level sensitive interrupters connected to the VMEbus IRQ7 IRQ1 signal lines http www motorola com computer literature 2 19 VMEchip2 The interrupt handler provides all logic necessary to identify and handle all local interrupts as well as VMEbus interrupts When a local interrupt is acknowledged a unique vector is provided by the chip Edge sensitive interrupters are not cleared during the interrupt acknowledge cycle and must by reset by software as required If the interrupt source is the VMEbus the interrupt handler instructs the VMEbus master to execute a VMEbus IACK cycle to obtain the vector from the VMEbus interrupter The chip connects to all signals that a VMEbus handler is required to drive and monitor On the local bus the interrupt handler is designed to comply with the interrupt handling signaling protocol of the MC680x0 microprocessor Global Control and Status Registers The VMEchip2 ASIC includes a set of registers that are accessible from both the VMEbus and the local bus These registers are provided to aid in interprocessor communications over the VMEbus These registers are fully described in a later section LCSR Programming Model This section defines the programming model for the
250. ion of the DMA Enable register for the required programming sequence of the control registers and enable bits The following are legal contexts for DMA channel configurations Note that configuration rules for DMA controllers for IP a and IP b are defined The same relationships exist for IP c and IP d If the IP a data bus is 8 or 16 bits no restrictions are placed on IP b If the IP a data bus is 32 bits and ADMA mode is selected the DMA controller associated with b cannot be used a If the CHI bit is set in DMA controller register associated with IP b and channels A and B both operate in the SDMA mode the DMA channels associated with IP a and IP b can both be used if the data widths for channels A and B are set equal This case allows the DMA channel that normally responds to the IP b DMaAreq 0 pin to respond to the IP a DMAreq 1 pin This enables full duplex operation at IP a DMA Control and Status Register Set Definition The four sets of DMA controller CSRs are almost identical in functionality Each register set is grouped as DMACa DMACb DMACc and DMACd These register sets are shown pictorially in the CSR register summary section Only one register set is defined except that the offset is noted for the four possible values Refer to the definitions of bit 1 in DMA Control Register 1 for a description of how the register sets are associated with the physical DMA request from the Industry Packs
251. is flexibility in memory control where previous MVMEIX2LX series 21 Programmer s Reference Guides documented only the parity memory controller model this guide describes the parity model in Chapter 3 as well as the MCECC model in Chapter 5 You can enable the ECC function if you so desire There is logic to prevent you from using both SDRAM memory controllers at the same time Regardless of which memory controller is enabled the same SDRAM memory array is targeted The SDRAM array is 32 data bits wide with 7 checkbits The array architecture is a non interleaved single bank for sizes below 32MB For array sizes above 32MB additional physical memory banks are added but the architecture remains non interleaved Since the 7 checkbits enable error detection and correction the MC parity memory controller actually interfaces to an error correcting memory array In this case a parity error is defined to be a multibit error that cannot be corrected Memory scrubbing is not available with the parity memory controller A final note on the SDRAM implementation The bandwidth between the SDRAM and local bus is greater than it was with the earlier DRAM array As a result software takes less time to execute Applications that incorporate elapsed time functions which are dependent on code execution may have problems For readers who need to know the ASIC specific differences between the MVMEIX2P2 programming models in deta
252. is register or the CSIGI bit in the local interrupt clear register SIG2 The SIG2 bit is set when a VMEbus master writes a 1 to it When the SIG2 bit is set an interrupt is sent to the local bus interrupter The SIG2 bit is cleared when the local processor writes a 1 to the SIG2 bit in this register or the CSIG2 bit in the local interrupt clear register 2 104 Computer Group Literature Center Web Site GCSR Programming Model SIG3 0 LM1 LM2 LM3 The SIG3 bit is set when a VMEbus master writes a 1 to it When the SIG3 bit is set an interrupt is sent to the local bus interrupter The SIG3 bit is cleared when the local processor writes a 1 to the 5163 bit in this register or the CSIG3 bit in the local interrupt clear register This bit is cleared by an LMO cycle on the VMEbus When this bit is cleared an interrupt is set to the local bus interrupter This bit is set when the local processor or a VMEbus master writes a to the LMO bit in this register or the CLMO bit in local interrupt clear register This bit is cleared by an LMI cycle on the VMEbus When this bit is cleared an interrupt is set to the local bus interrupter This bit is set when the local processor or a VMEbus master writes a 1 to the LMI bit in this register or the CLMI bit in local interrupt clear register This bit is cleared by an LM2 cycle on the VMEbus This bit is set when the local processor or a VMEbus master writes a 1 to the
253. is set when the last error logged was due to a single bit error It is cleared when 1 is written to the ERRLOG bit The syndrome code reflects the bit in error Refer to the Syndrome Decoding section MULTIPLE BIT ERROR is set when the last error logged was due to a multiple bit error It is cleared when a 1 is written to the ERRLOG bit The syndrome code is meaningless if MBE is set This bit provides status for a function that is not currently used in the MCECC sector EALT indicates that the last logging of an error occurred on a DRAM access by an alternate MI not asserted local bus master ESCRB indicates the entity that was accessing DRAM at the last logging of a single or double bit error If ESCRB is 1 it indicates that the scrubber was accessing DRAM If ESCRB is 0 it indicates that the local MC680x0 bus master was accessing DRAM ERD reflects the state of the local bus READ signal pin at the last logging of a single or double bit error ERD 1 corresponds to READ high and ERD 0 to READ low ERD is meaningless if ESCRB is set When set ERRLOG indicates that a single or a double bit error has been logged by this MCECC and that no more will be logged until it is cleared The bit can only be set by logging an error and cleared by writing a 1 to it http www motorola com computer literature 5 27 Functions When ERRLOG is cleared the is ready to log new error Note that b
254. it VMEbus data width 8 bit 16 bit and 32 bit block transfer Standard and extended VMEbus addressing Software enabled write posting mode Write post buffer 17 four bytes in BLT mode two four bytes in non BLT mode An eight four byte read ahead buffer BLT mode only 32 bit Local Bus to VMEbus DMA Controller Programmable 16 bit 32 bit and 64 bit VMEbus data width Programmable short standard and extended VMEbus addressing Programmable AM code Programmable local bus snoop enable 16 four byte FIFO data buffer Up to 4 GB of data per DMA request Automatically adjustment of transfer size to optimize bus utilization DMA complete interrupt DMAC command chaining supported by a singly linked list of DMA commands VMEbus DMA controller requester with Software enabled fair request modes Software configured release modes Release On Request ROR and Release On End Of Data ROEOD Software configured BRO BR3 request levels and Software enabled bus tenure timer VMEbus Interrupter Software configured IRQ1 IRQ7 interrupt request level 8 bit software programmed status ID register Computer Group Literature Center Web Site Introduction Table 2 1 Features of the VMEchip2 ASIC Continued Function VMEbus System Controller Features Arbiter with software configured arbitration modes Priority
255. it device should respond with VA 1 high or low Devices on the local bus should respond to any combination of LA lt 3 2 gt This is required to support the burst mode on the MC680x0 bus Normally when the non increment mode is used the starting address and byte count would be aligned to the port size For example a DMA transfer to a 16 bit FIFO would start on a 16 bit boundary and would have an even number of 16 bit transfers If the starting address is not aligned or the byte count is odd the DMA controller will increment the lower address lines This is required because the lower order address lines are used to define the size of the transfer and the byte lanes The VMEbus uses VA lt 2 1 gt LWORD and DS lt 1 0 gt to define the transfer size and byte lanes If the VMEbus port size is D32 then VA 1 LWORD and DS lt 1 0 gt are used to define the transfer size and byte lanes During D16 transfers the VMEbus address line VA lt 1 gt toggles If the VMEbus port size is D64 then VA lt 2 1 gt LWORD and DS lt 1 0 gt are used to define the transfer size and byte lanes Local bus address LA lt 3 0 gt SIZ lt 1 0 gt are used to define the transfer size and byte lanes on local bus During local bus transfers LA lt 3 2 gt count The DMA controller internally increments the VMEbus address counter and if the transfer mode is BLT the DMA controller generates a new address strobe AS when a block boundary is crossed
256. it is cleared when the DMAC is enabled This bit is not defined for MVMEIX2P4 implementation If this bit is set the DMAC has received a TEA and no additional status was provided This bit is cleared when the DMAC is enabled If this bit is set the MPU has received a TEA and the status indicated a local bus time out This bit is cleared by writing a 1 to the MCLR bit in this register Programming the Tick and Watchdog Timers The VMEchip2 has two 32 bit tick timers and one watchdog timer This section provides addresses and bit level descriptions of the prescaler tick timer watchdog timer registers and various other timer registers VMEbus Arbiter Time Out Control Register ADR SIZ FFF4004C 8 bits 1 used of 32 BIT 31 30 29 28 27 26 25 24 NAME ARBTO OPER R W RESET 0 PS This register controls the VMEbus arbiter time out timer ARBTO When this bit is high the VMEbus grant time out timer is enabled When this bit is low the VMEbus grant timer is disabled When the timer is enabled and the arbiter does not receive a BBSY signal within 256 us after a grant is issued the arbiter asserts BBSY and removes the grant The arbiter then rearbitrates any pending requests 2 64 Computer Group Literature Center Web Site LCSR Programming Model DMAC Ton Toff Timers and VMEbus Global Time out Control Register ADR SIZ FFF4004C 8 bits of 32 BIT 23 22 21 2
257. ite Functional Description The 82596CA interface logic monitors all bus cycles initiated by the 82596CA and if a bus error is indicated TAE 0 and TA 1 the Back Off signal BOFF to the 82596CA is asserted to keep the 82596CA off the local bus and prevent it from transmitting bad data or corrupting local memory The LANC Error Status register in the Petra MC2 chip is updated and a LANC bus error interrupt is generated if it is enabled in the MC2 sector The Back Off signal remains asserted until the 82596 is reset via a port reset command After the 82596 is reset pending operations must be restarted LANC Interrupt The Petra MC2 chip provides an interrupt control register for normal LANC termination and another register for bus error termination of LANC operation The Petra MC2 chip requests an interrupt at the level programmed in the LANC interrupt control registers if the interrupt is enabled and a positive edge is detected on the 82596CA INT pin or if the LANC bus error condition is detected 53C710 SCSI Controller Interface The Petra MC2 chip provides a map decoder and an interrupt handler for the NCR 53C710 SCSI I O Processor The base address for the 53C710 is FFF47000 The Petra MC2 chip requests an interrupt at the level programmed in the SCSI interrupt control register if the interrupt is enabled and a low level is detected on the 53C710 IRQ pin SRAM Memory Controller The SRAM base address and size a
258. ite Local Bus to IndustryPack Addressing DMA Status Register 1 The status bit is added to the DMA Status register for each DMA channel The ipendl bit is set when an early termination of the DMA data is detected and the dmaeil bit is set in the Alternate Control Register 2 The setting of this bit does not cause an interrupt The DMA interrupt associated with this activity will be generated when the DONE bit in the DMA Status register is set The ipendl bit is cleared when the channel is enabled by setting the DEN bit Local Bus to IndustryPack Addressing The following sections provide examples that illustrate local bus versus IndustryPack addressing for different IndustryPack spaces and programmed port widths Throughout the examples LBA refers to the local bus address defined by LA lt 23 0 gt and IPA refers to the IndustryPack address PA lt 22 7 gt is the value on signal pins IPAD lt 15 0 IPBD 15 0 during the select state these only apply to memory accesses IPA lt 6 1 gt is the value on signal pins IPA lt 6 1 gt and lt 0 gt is the value inferred by IPBS1 where lt 0 gt is 0 if IPBS1 is asserted and 1 if IPBS1 is negated http www motorola com computer literature 4 49 2 Functions Eight Bit Memory Space This example is for IP_a where the IP_a memory space is programmed with a base address of 00000000 a size of 4MB and a port width of 8 bits The relationship
259. its 4 used of 32 BIT 15 14 13 12 11 10 8 NAME ADDER SNP1 WPI 1 OPER R W R W R W RESET OPS OPS OPS This register is the slave write post and snoop control register for the first VMEbus to local bus map decoder SNP1 When this bit is high write posting is enabled for the address range defined by the first VMEbus slave map decoder When this bit is low write posting is disabled for the address range defined by the first VMEbus slave map decoder These bits control the snoop enable lines to the local bus for the address range defined by the first VMEbus slave map decoder The snooping functions differ according to processor type as shown SNP1 Requested Snoop Operation MC68040 Snoop disabled MC68060 Snoop enabled Source dirty sink byte word longword Snoop disabled Source dirty invalidate line Snoop enabled oj OF Snoop disabled Reserved Snoop disabled When this bit is high the adder is used for address translation When this bit is low the adder is not used for address translation http www motorola com computer literature 2 35 VMEchip2 VMEbus Slave Address Modifier Select Register 1 ADR SIZ FFF40010 8 bits of 32 BIT 7 6 5 4 3 2 1 0 SUP USR A32 24 D64 BLK PGM DAT OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPS
260. its 0 3 and the value that was written on bits 4 7 if the read happens after the register has been initialized ADR SIZ FFF42000 8 bits BIT 7 6 5 4 3 2 1 0 NAME IV7 IV6 IV5 4 IV3 IV2 IVO OPER R W R W R W R W R R R R RESET 0 PL 0 PL 0 PL 0 PL The encoding for the interrupt sources is shown in the next table where IV3 IVO refer to bits 3 0 of the vector passed during the ACK cycle The priority referenced in the following table is established in the MC2 logic by implementing a daisy chain request grant network There is a similar request grant daisy chain at the board level At the board level the Petra ASIC s 2 sector is wired to have the highest priority followed by the Petra s IndustryPack interface IP2 sector and the VMEchip2 ASIC Table 3 5 Interrupt Vector Base Register Encoding and Priority Interrupt Source 0 IV3 IV0 Daisy Chain Priority Unused 0 amp 1 amp 2 Timer 4 3 Lowest Timer 3 4 SCSIIRQ 5 LANC ERR 6 LANC IRQ 7 Timer 2 8 Timer 1 9 Unused A Parity Error B Unused C amp D Serial I O 785230 Note 1 Next Highest ABORT Switch E Highest Unused F 3 14 Computer Group Literature Center Web Site Programming Model Note The Z85230 controller has an integrated interrupt vector register which is separate from the
261. k rate and then they are loaded from the prescaler adjust register When the load occurs the upper 24 bits are incremented When the prescaler adjust register is correctly programmed the lower 8 bits increment at the local bus clock rate and the upper 24 bits increment every microsecond The counter may be read at any time http www motorola com computer literature 2 73 VMEchip2 Programming the Local Bus Interrupter The local bus interrupter is used by devices that need to interrupt the local bus There are 31 devices that can interrupt the local bus through the VMEchip2 In the general case each interrupter has a level select register an enable bit a status bit a clear bit and a set bit for the software interrupts Each interrupter also provides a unique interrupt vector to the processor The upper four bits of the vector are programmable in the vector base registers The lower four bits are unique for each interrupter There are two base registers one for the first 16 interrupters and one for the next 8 interrupters The VMEbus interrupters provide their own vectors A summary of the interrupts appears in Table 2 4 The status bit of an interrupter is affected by the enable bit If the enable bit is low the status bit is also low Interrupts may be polled by setting the enable bit and programming the level to 0 This enables the status bit and prevents the local bus from being interrupted The enable bit does not clear edge
262. le the sixth area the time of day TOD clock is defined by the chip hardware The first area is reserved for user data The second area is used by Motorola networking software The third area may be used by an operating system The fourth area is used by the MVME1X2P4 board debugger MVMEI X2Bug The fifth area detailed in Table 1 13 is the configuration area The sixth area the TOD clock detailed in Table 1 14 is defined by the chip hardware Table 1 12 48 58 BBRAM TOD Clock Memory Address Range Description Size Bytes 0000 FFFCOFFF User Area 4096 1000 FFFC10FF Networking Area 256 FFFC1100 FFFC16F7 Operating System Area 1528 FFFC16F8 FFFC1EF7 Debugger Area 2048 FFFC1EF8 FFFC1FF7 Configuration Area 256 FFFCIFFS8 FFFC1FFF TOD Clock 8 http www motorola com computer literature 1 33 Board Description and Memory Maps Table 1 13 BBRAM Configuration Area Memory Map Address Range Description Size Bytes SFFFCIEFS FFFC1EFB Version 4 FFFCIEFC FFFC1F07 Serial Number 12 FFFCIFO08 FFFC1F17 Board ID 16 FFFCIF18 FFFC1F27 PWA 16 28 FFFC1F2B Speed FFFC1F2C FFFC1F31 Ethernet Address FFFC1F32 FFFC1F33 Reserved FFFC 1F34 FFFC1F35 Local SCSI ID FFFC1F36 FFFC1F3D Memory Mezz PWB FFFC1F3E FFFC1F45 Memory Mezz Serial Number FFFC 1F46 FFFC1F4D St
263. lect register for the second VMEbus to local bus map decoder The address translation select register value is based on the segment size the difference between the VMEbus starting and ending addresses If the segment size is between the sizes shown in the table below assume the larger size Segment Segment dde Size Translation Size Translation Select Value Select Value 64KB FFFF 32MB FE00 128KB FFFE 64MB 00 256 FFFC 128 800 512 FFF8 256MB F000 FFFO 512MB E000 2MB FFEO 1GB C000 4MB FFCO 2GB 8000 8MB FF80 4GB 0000 16MB 00 http www motorola com computer literature 2 31 VMEchip2 VMEbus Slave Write Post Snoop Control Register 2 ADR SIZ FFF40010 8 bits 4 used of 32 BIT 31 30 29 28 27 26 25 24 NAME ADDER SNP2 WP2 2 OPER R W R W R W RESET 0 PS 0 PS 0 PS This register is the slave write post and snoop control register for the second VMEbus to local bus map dec oder WP2 When this bit is high write posting is enabled for the address range defined by the second VMEbus slave map decoder When this bit is low write posting is disabled for the address range defined by the second VMEbus slave map decoder SNP2 These bits control the snoop enable lines to the local bus for the address range defined by the second VMEbus slave map decoder The snooping function
264. lly start at 0 the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 1 Counter ADR SIZ FFF40054 32 bits BIT 31 iss 0 NAME Tick timer 1 Counter OPER R W RESET This is the tick timer 1 counter When enabled it increments every microsecond Software may read or write the counter at any time 2 68 Computer Group Literature Center Web Site LCSR Programming Model Tick Timer 2 Compare Register ADR SIZ FFF40058 32 bits BIT 31 0 Tick timer 2 Compare Register OPER R W RESET OP The tick timer 2 counter is compared to this register When they are equal an interrupt is sent to the local bus interrupter and the overflow counter is incremented If the clear on compare mode is enabled the counter is also cleared For periodic interrupts the following equation should be used to determine the compare register value for a specific period compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected Remember the rollover time for the counter is 71 6 minutes Tick Timer 2 Counter ADR SIZ FFF4005C 32 bits BIT 31 0 Tick timer
265. lways requests at the old level until it becomes bus master and the new level takes effect If the VMEchip2 is bus master when the level is changed the new level does not take effect until the bus has been released and re requested at the old level The requester always requests the VMEbus at level 3 the first time following a SYSRESET 0 VMEbus request level 0 1 VMEbus request level 1 2 VMEbus request level 2 3 VMEbus request level 3 DRELM These bits define the VMEbus release mode for the DMAC requester The DMAC always releases the bus when the FIFO is full VMEbus to local bus or empty local bus to VMEbus 0 Release when the time on timer has expired and a BRx signal is active on the VMEbus 1 Release when the time on timer has expired 2 Release when a BRx signal is active on the VMEbus 3 Release when a BRx signal is active on the VMEbus or the time on timer has expired DFAIR When this bit is high the DMAC requester operates in fair mode It waits until its request level is inactive before requesting the VMEbus When this bitis low the DMAC requester does not operate in fair mode DTBL The DMAC operates in direct mode when this bit is low and it operates in command chaining mode when this bit is high DEN The DMAC is enabled when this bit is set high This bit always reads 0 DHALT When this bit is high the DMAC halts at the end of a command when the DMAC is operating in command chaining mode When this bi
266. makes it possible to have multiple MVME1X2P4 modules on the same VMEbus with different virtual local bus maps as viewed by different VMEbus masters Local Bus Memory Map The local bus memory map is split into different address spaces by the transfer type TT signals The local resources respond to the normal access and interrupt acknowledge codes Normal Address Range The following tables show the memory maps of devices that respond to the normal address range The normal address range is defined by the Transfer Type TT signals on the local bus On the MVME1X2P4 Transfer Types 0 1 and 2 define the normal address range Table 1 3 is the entire map from 00000000 to FFFFFFFF Many areas of the map are user programmable and suggested uses are shown in the table The cache inhibit function is programmable in the MC68xx0x0 MMU The onboard space must be marked cache inhibit and serialized in its page table Table 1 4 on page 1 14 further defines the map for the local devices on MVME1X2P4 http www motorola com computer literature 1 11 Board Description and Memory Maps Table 1 3 MVME1X2P4 Local Bus Memory Map Devices Port SONATE Address Range Accessed Width Size Cache Note s Inhibit Programmable DRAM on board D32 4MB 16MB N Programmable SRAM D32 128KB 2MB N Programmable VMEbus D32 D16 A32 A24 Programmable IP_a Memory D32 D8 64KB 8MB 2
267. mally set to quite different values When the processor or another local bus master initiates an access to the VMEbus it first waits until any other local bus masters get off the bus Then the master begins its cycle and the local bus timer starts counting It continues to count until an address decode of the VMEbus address space is detected and then terminates This is normally a very short period of 1 50 Computer Group Literature Center Web Site Software Support Considerations time In fact all local bus non error bus accesses such as the time to access onboard memory are normally very short Therefore it is advisable to set this timer to a small value such as 256 usec The next timer to take over when one MVME1X2P4 accesses another is the VMEbus access timer This measures the time between when the VMEbus has been address decoded and hence a VMEbus request has been made and the time when VMEbus mastership has been granted Because we have found in the past that some VME systems can become very busy we recommend that this time out be set to a large value such as 32 msec Once the VMEbus has been granted a third timer takes over This is the global VMEbus timer This timer starts when a transfer actually begins DSO or DS1 goes active and ends when that transfer completes DSO or DS1 goes inactive This time should be longer than any expected legitimate transfer time on the bus We normally set it to 256 usec This t
268. n the DRAM Control register Clear bit 0 of offset 18 5 Set the ZFILL bit in the MCECC pair Set Bit 28 of offset 20 6 Setthe Scrub Time On Time Off register for the maximum rate and to do write cycles by setting the SRDIS bit setting all of the STON bits and clearing all of the STOFF bits Write B8 to offset 34 7 Enable scrubbing by setting the SCRBEN bit in the Scrub Control register Set bit 27 of offset 24 8 Ensure that the zero fill has started by waiting for the SCRB bit in the Scrub Control register to be set Wait for bit 28 of offset 24 1 Computer Group Literature Center Web Site Programming Model 9 Ensure that the zero fill stops after one pass by clearing the SCRBEN bit in the Scrub Control register Clear bit 27 of offset 24 10 Wait for the zero fill to complete by waiting for the SCRB bit in the Scrub Control register to be cleared Wait for bit 28 of offset 24 0 11 Clear the ZFILL bit in the MCECC pair Clear Bit 28 of offset 20 12 The entire DRAM that is controlled by this MCECC is now zero filled The software can now program the appropriate scrubbing mode and other desired initialization and enable DRAM for operation http www motorola com computer literature 5 35 MCECC Functions Syndrome Decoding The following table defines the syndrome bit encoding for the Petra MCECC ASIC A syndrome code value of 00 indicates no error found All other syn
269. n register should be programmed with the translated address and the address translation select register should be programmed to enable the translated address If address translation is not desired then the address translation registers should be programmed to 0 The address translation address register and the address translation select register operate in the following way If you set a bit in the address translation select register then the corresponding bit in the address translation address register drives the appropriate VMEbus address line If you clear the bit in the address translation select register then the corresponding local bus address line drives the appropriate VMEbus address line The most significant bit of the address translation select register corresponds to the most significant bit of the address translation address register and to A32 of the local bus and A32 of the VMEbus 2 38 Computer Group Literature Center Web Site LCSR Programming Model Write posting is enabled for the segment by setting the write post enable bit in the address modifier register D16 transfers are forced by setting the D16 bit in the address modifier register A segment is enabled by setting the enable bit Segments should not be programmed to overlap The first I O map decoder maps the local bus address range FFFF0000 to FFFFFFFF to the A16 short I O map of the VMEbus This segment may be enabled using the enable bit Write posting
270. nostics User s Manual V172DIAA UM Debugging Package for Motorola 68K CISC CPUs User s Manual 68KBUGI D and Parts 1 and 2 68KBUG2 D Single Board Computers SCSI Software User s Manual SBCSCSI D MVME712M Transition Module and P2 Adapter Board Installation VME712MA IH and Use MVME712 12 MVME712 13 MVME712A MVME712AM and MVME712A D MVME712B Transition Modules and LCP2 Adapter Board User s Manual SIMMOO Serial Interface Module Installation Guide SIMMOO9A IH To locate and view the most up to date product information in PDF or HTML format visit http www motorola com computer literature 1 Related Documentation Manufacturers Documents For additional information refer to the following table for manufacturers data sheets or user s manuals and related specifications As an additional help a source for the listed document is also provided Please note that in many cases the information is preliminary and the revision levels of the documents are subject to change without notice Table C 2 Manufacturers Documents Publication Document Title and Source Number M68040 Microprocessors User s Manual M68040UM M68060 Microprocessors User s Manual M68060UM M68000 Family Reference Manual M68000FR Literature Distribution Center for Motorola Telephone 1 800 441 2447 FAX 602 994 6430 or 303 675 2150 E mail Idcformotorola hibbertco com Web http www mot com SPS 82596CA Local Area Net
271. nstances there was valid data which had been transferred from an device as far as the IP interface but not on to the MVME162 172 host memory The Petra implementation has preserved this functionality The Petra implementation also incorporates a DMA end function which does flush the inbound data path For details refer to the Alternate Control Register 2 description INTE This bit is used only in command chaining mode It is modified only when DMA loads its control register from the control word in the command packet When this bit in the command packets is set an interrupt is sent to the local bus interrupter when the command in the packet has been executed The local bus is interrupted if DMA s interrupt is enabled http www motorola com computer literature 4 41 IP2 Functions DMA Local Bus Address Counter In the direct mode this counter is programmed with the starting address of the data in local bus memory ADR SIZ FFFBC028 40 58 70 32 bits each BIT 31 m 0 NAME DMA Local bus Address Counter OPER R W RESET OR IndustryPack Address Counter In direct mode this counter is programmed with the starting address of the data buffer in IndustryPack memory The value programmed in the IndustryPack address counter is the address that would be used when referencing the IndustryPack memory space from the local bus Refer to the addressing mapping from the local
272. ny old interrupts and then re enabled ETIC2 ESYSF EAB EACF Enable tick timer 1 interrupt Enable tick timer 2 interrupt Enable VMEbus IRQI edge sensitive interrupt Not used on MVMEIX2P4 Enable VMEbus master write post error interrupt Enable VMEbus SYSFAIL interrupt Not used on MVME1 X2P4 Enable VMEbus ACFAIL interrupt http www motorola com computer literature VMEchip2 Local Bus Interrupter Enable Register bits 16 23 ADR SIZ FFF4006C 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME EVIA EDMA ESIG3 ESIG2 ESIGI ESIGO ELMI ELMO OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL 0 PSL This register is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ELMO ELMI ESIGO ESIG1 ESIG2 ESIG3 EDMA EVIA Enable GCSR LMO interrupt Enable GCSR interrupt Enable GCSR SIGO interrupt Enable GCSR SIGI interrupt Enable GCSR SIG2 interrupt Enable GCSR 5163 interrupt Enable DMAC interrupt VMEbus interrupter acknowledge inter
273. of a command is indicated by setting bit 0 or 1 of the next command address Table 2 3 shows the command packet format Computer Group Literature Center Web Site LCSR Programming Model Table 2 3 DMAC Command Packet Format Entry Function 0 bits 0 15 Control Word 1 bits 0 31 Local Bus Address 2 bits 0 31 VMEbus Address 3 bits 0 31 Byte Count 4 bits 0 31 Address of Next Command Packet DMAC Registers This section provides addresses and bit level descriptions of the DMAC counters control registers and status registers Other control functions are also included in this section EPROM Decoder SRAM and DMA Control Register ADR SIZ FFF40030 8 bits 6 used of 32 BIT 23 22 21 20 19 18 17 16 NAME WAITRMW ROMO TBLSC SRAMS OPER R W R W R W R W RESET OPSL 1 PSL OPS OPS This register controls the snoop control bits used by the DMAC when it is accessing table entries SRAMS These VMEchip2 bits not used on the MVME1X2P4 http www motorola com computer literature 2 53 VMEchip2 TBLSC These bits control the snoop signal lines on the local bus when the DMAC is table walking The snooping functions differ according to processor type as shown TBLSC Requested Snoop Operation 19 18 MC68040 MC68060 0 0 Snoop disabled Snoop enabled 0 1 Source dirty sink byte word longword Snoop disabled 1 0
274. of the IndustryPack address to the local bus address is IPA LBA x 2 1 LBA 00000000 00000001 00000002 00000003 003FFFFC 003FFFFD 003FFFFE 003FFFFF IPA 000001 000003 000005 000007 7FFFF9 7FFFFB 7FFFFD 7FFFFF Comments 4 50 Computer Group Literature Center Web Site Local Bus to IndustryPack Addressing 16 Bit Memory Space This example is for a where the IP a memory space is programmed with a base address of 00000000 a size of 8MB and a port width of 16 bits The relationship of the IndustryPack address to the local bus address is IPA LBA LBA IPA Comments 00000000 000000 00000001 000001 00000002 000002 00000003 000003 007FFFFC 7FFFFC 007FFFFD 7FFFFD 007FFFFE 7FFFFE 007FFFFF 7FFFFF http www motorola com computer literature 4 51 2 Functions 32 Bit Memory Space This example is for IP_ab where the IP_ab memory space is programmed with a base address of 00000000 a size of 16MB and a port width of 32 bits The relationship of the IndustryPack address to the local bus address is lt 22 1 gt LBA lt 23 2 gt and IPA lt 0 gt LBA 0 LBA 00000000 00000001 00000002 00000003 00000004 00000005 00000006 00000007 00000008 00FFFFFB 00FFFFFC 00FFFFFD 00FFFFFE 00F
275. om incremental addresses with each clock tick subject to boundary limitations the Petra MCECC sector does not implement an interleaved memory architecture The SDRAM array is 32 data bits plus seven checkbits wide The depth is dependent on the number and type of SDRAM devices Cycle Types The Petra MCECC sector always initiates burst read write accesses to the SDRAM device If the bus access is not a burst the cycle is terminated early Single and double byte write cycles are read modify write accesses but longword write accesses require no read cycle Error Reporting The Petra MCECC sector generates ECC check bits for write cycles It also checks read data from the DRAM and corrects the data if it contains a single bit error If a non correctable error occurs within the read data the Petra MCECC sector so indicates by asserting its non correctable error NCE pin The following paragraphs describe the actions that the MCECC sector will take in different error situations single Bit Error Cycle Type Burst Read or Non Burst Read 1 Correct the data that is driven to the local MC680x0 bus 2 Do not correct the data in DRAM The DRAM is not corrected until the next scrub of that address which happens only if scrubbing is enabled 3 Terminate the cycle normally Assert to the local bus 4 Log the error if not already logged 5 Notify the local MPU via interrupt if so enabled http www motorola com comp
276. omputer literature 4 57 2 Functions and ID Space Accesses The following table shows the data routing when accessing IP I O or ID space SPACE LBSIZE LBA IPA LD lt 31 24 gt LD lt 23 16 gt LD lt 15 8 gt LD lt 7 0 gt 0 0 IPXD lt 15 8 gt 1 1 IPXD lt 7 0 gt BYTE 2 2 IPXD lt 15 8 gt IP_a b c or d 3 3 IPXD lt 7 0 gt W O or ID 0 0 IPXD lt 15 8 gt IPXD lt 7 0 gt WORD 2 2 IPXD lt 15 8 gt IPXD 7 0 LWORD 0 0 IPXD lt 15 8 gt IPXD lt 7 0 gt 0 0 IPBD lt 15 8 gt 1 1 IPBD lt 7 0 gt BYTE 2 0 IPAD lt 15 8 gt IP_ab 3 1 lt 7 0 gt 0 0 IPBD lt 15 8 gt IPBD lt 7 0 gt WORD 2 0 IPAD lt 15 8 gt IPAD lt 7 0 gt LWORD 0 0 IPBD lt 15 8 gt IPBD lt 7 0 gt IPAD lt 15 8 gt IPAD lt 7 0 gt SPACE refers to the IndustryPack space being accessed LBSIZE refers to local bus transfer size LBA refers to local bus address signals 1 0 IPA refers to IndustryPack address signals 2 1 0 LD refers to the local data bus IPXD refers to the IP a data bus IPAD when accessing IP a or IP c It refers to the b data bus IPBD when accessing b or IP d 4 58 Computer Group Literature Center Web Site MCECC Functions Introduction The ECC DRAM Controller ASIC MCECC is one of three ASICs used on earlier MVME162 172 models the MC2 chip the IP2 chip and the MCECC chip whose functions are now incor
277. one each per IndustryPack interface or two channels on IP_a and IP_c Dynamic bus sizing for accesses to IndustryPack memory space Timers Recovery timer for each IndustryPack to provide dead time between back to back accesses Interrupt Handling Thirteen Interrupt Handler Control registers two for each IndustryPack one per DMA controller DMAC and programmable clock IP2 IP1 Bug Fixes The Petra ASIC incorporates fixes and workarounds for a number of bugs that existed in previous versions of the IP2 chip This section describes those solutions Command Chain Table Update The IP2 chip would not update the DMA registers correctly if the IP bus was operating at 32Mhz and the local bus memory inserted wait states between the second or third beats of a burst operation This problem has been corrected in the Petra implementation DMA End The IP2 implementation did not flush the FIFOs for inbound DMA when the DMA_END signal was asserted by the Industry Pack device The workaround for this problem was to have software set the Byte Count register to 0 This would flush the FIFO This workaround was not effective if the application required the DMA command chaining operation To maintain backward compatibility with the old programming model and fix the problem an alternate Byte Count register and Control Register 2 have been added to the programming model on a per DMA channel basis 4 2 Computer Group Literatu
278. ontroller DMAC VMEchip2 ASIC 2 10 2 51 DMAC command packets 2 52 interrupter VMEbus 2 19 LTO error 1 46 off board error 1 46 parity error 1 45 TEA error cause unidentified 1 47 VMEbus error 1 45 VMEbus requester 2 13 DMAC registers VMEchip2 ASIC DMAC byte counter 2 60 DMAC Control register 1 bits 0 7 2 55 DMAC Control register 2 bits 0 7 2 58 DMAC Control register 2 bits 8 15 2 57 DMAC local bus address counter 2 59 DMAC Status register 2 63 DMAC VMEbus address counter 2 60 Local Bus to V MEbus Requester Control register 2 54 MPU Status and DMA Interrupt Count register 2 62 PROM Decoder SRAM and DMA Control register 2 53 table address counter 2 60 DMAC registers VMEchip2 continued VMEbus Interrupter Control register 2 61 VMEbus Interrupter Vector register 2 62 documentation C 1 DRAM and SRAM Memory Controller registers 3 24 initialization 5 34 memory controller see SDRAM memory controller Petra MC2 chip 3 6 size control bit encoding Petra MC2 chip 3 26 3 27 specifications 1 6 signal 2 9 DWB bit VMEchip2 LCSR 2 8 E ECC error correcting code 5 5 edge sensitive interrupters VMEbus 2 19 edge sensitive interrupts VMEchip2 ASIC 2 74 ending address register VMEbus slave 2 38 VMEbus slave map decoder 2 27 EPROM socket 1 6 EPROM Flash interface 3 2 selection 1 13 sizing 1 13 errata sheets chip 1 17 error conditions descriptions of 1 43 error handler 1 43 error logging ECC
279. or immediately performs a scrub of the entire DRAM array When the scrub is complete if software has cleared SCRBEN then scrubbing is not done again until software sets the SCRBEN bit If software has not cleared the SCRBEN bit then when the amount of time indicated in the Scrub Period SBPD register expires the MCECC sector scrubs the DRAM array again It continues to perform scrubs of the entire DRAM array at the frequency indicated in the SBPD register The scrubber does not start a new scrub once the SCRBEN bit is cleared The time between scrubs is approximately two seconds times the value stored in the SBPD register Note that a power up local or software reset stops the scrubber This status bit reflects the state of the scrubber When the scrubber is in the process of doing a scrub this bit is set When the scrubber is between scrubs this bit is cleared http www motorola com computer literature 5 19 MCECC Functions Scrub Period Register Bits 15 8 The Scrub Period Control register controls how often a scrub of the entire memory is performed if the SCRBEN bit is set in the Scrub Control register The time between scrubs is approximately two seconds times the value programmed into the Scrub Period register The scrub period can be programmed from once every four seconds to once every 36 hours This register contains bits 15 8 of the Scrub Period register ADR SIZ 1st FFF43028 2nd
280. ory Maps LOCAL WD ACCESS BUS TIME OUT PRESCALER TIMER TIMER SELECT CLOCK ADJUST COMPARE REGISTER COUNTER COMPARE REGISTER COUNTER OVERFLOW M e OVERFLOW ce COUNTER 2 5 5 COUNTER 1 i 1 1 SCALER 15 14 13 12 11 10 9 8 6 5 4 3 2 1 0 sw7 swe sw5 SW4 sw3 Swe swt Swo SPARE IRQ 1807 IRQs IRQ5 1804 IRQ2 IRQ1 RQ IRQ RQ IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SET SET SET SET SET SET SET SET RQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 CLR CLR CLR CLR CLR IRQ IRQ IRQ IRQ IRQ IRQ 15 14 13 12 11 10 9 8 P ERROR IRQIE TIC TIMER 2 TIC TIMER 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL SIG 1 SIG 0 LM 1 LM 0 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL sws swe swi swo IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL VME IRQ 4 VMEB IRQ 3 VME IRQ 2 VME IRQ 1 IRQ LEVEL IRQ LEVEL IRQ LEVEL IRQ LEVEL GPIOO GPIOI GPI Pa REV DIS DIS DIS EN DIS EN EROM
281. ory Maps describes the board level hardware features of MVMEIX2PA single board computers It includes memory maps and a discussion of some general software considerations such as cache coherency interrupts and bus errors Chapter 2 VMEchip2 describes the VMEchip2 ASIC the local bus VMEbus interface chip on MVME1X2P4 boards Chapter 3 MC2 Functions describes MC2 functionality as implemented in the Petra ASIC The MC2 Memory Controller ASIC is one of three ASICs the MC2 chip the IP2 chip and the MCECC chip used on earlier MVME162 172 models whose functions are now incorporated into the Petra chip on the MVME1X2P4 Chapter 4 2 Functions describes IP2 functionality as implemented in the Petra ASIC The IP2 IndustryPack Interface Controller ASIC is the second of three ASICs used on earlier MVME162 172 models whose functions are now incorporated into the Petra chip on the MVMEIX2P4 xxii Chapter 5 Functions describes functionality as implemented in the Petra ASIC The ECC DRAM Controller ASIC MCECC is the third of three ASICs used on earlier MVME162 172 models whose functions are now incorporated into the Petra chip on the MVMEIX2PA Appendix A Summary of Changes lists the modifications that accompanied the introduction of the Petra ASIC on the MVME162P4 and 72 4 Appendix Using Interrupts the MVME1X2P4 illustrates an approach to generating and handling a VMEchip2 tick t
282. osed of 3 devices Device is 64Mbit x 8 data with one bank composed of 5 devices Device is 64Mbit x 8 data with two banks composed of 5 devices each If EA24 0 Bank 0 If EA24 1 Bank 1 Device is 64Mbit x 8 data with four banks composed of 5 devices each If EA 25 24 00 Bank 0 If EA 25 24 01 Bank 1 If EA 25 24 10 Bank 2 If EA 25 24 11 Bank 3 Device is 128Mbit x 8 data with one bank composed of 5 devices Device is 128Mbit x 8 data with two banks composed of 5 devices each If EA25 0 Bank 0 If EA25 1 Bank 1 http www motorola com computer literature 5 37 MCECC Functions 5 38 Computer Group Literature Center Web Site Summary of Changes Introduction This appendix summarizes the modifications that accompanied the introduction of the Petra ASIC on the MVME162P4 and MVME172P4 Embedded Controller boards Differences in function and implementation between previous MVME162FX and MVMEI72FX models and the new MVME1X2P4 boards are listed in the following table Table A 1 List of Changes Function MC2 memory control Previous Implementation MC2 ASIC revision 01 MVME1X2P4 Implementation Petra ASIC revision 03 page 3 12 Serial I O MC2 ASIC did not support direct access to data port Software used indirect access Both direct and indirect access modes supported page 3 7 Flash memory write Flash writes enabled di
283. ot aligned so the local bus and VMEbus can operate at their maximum data transfer sizes To allow other boards access to the VMEbus the DMAC has bus tenure timers to limit the time the DMAC spends on the VMEbus and to ensure a minimum time off the VMEbus Since the local bus is generally faster than the VMEbus other local bus masters may use the local bus while the DMAC is waiting for the VMEbus http www motorola com computer literature 2 11 VMEchip2 The DMAC also supports command chaining through the use of a singly linked list built in local memory Each entry in the list includes a VMEbus address a local bus address a byte count a control word and a pointer to the next entry When the command chaining mode is enabled the DMAC reads and executes commands from the list in local memory until all commands are executed The DMAC can be programmed to send an interrupt request to the local bus interrupter when any specific table entry has completed In addition the DMAC always sends an interrupt request at the normal completion of a request or when an error is detected If the DMAC interrupt is enabled in the DMAC the local bus is interrupted For increased flexibility in managing the bus tenure to optimize bus usage as required by the system configuration the chip contains control bits that allow the DMAC time on and off the bus to be programmed Using these control bits software can instruct the DMA controller to acquire t
284. ote 2 Note 3 25MHz 8MHz 4 IP clocks 10 IP clocks 4 IP clocks 8MB sec 12 8MB sec 8MB sec 32MHz 8MHz 3 IP clocks 10 IP clocks 4 IP clocks 10 6MB sec 12 8MB sec 8MB sec 32MHz 32MHz 6 IP clocks 12 IP clocks 6 IP clocks Note 5 21MB sec 42MB sec 21MB sec Note 4 Notes 1 This column is a measure of IndustryPack bandwidth for back to back cycles for a local bus master which is accessing a memory or I O space location on an IndustryPack It assumes a zero wait state acknowledge reply from the IndustryPack 2 This column is a measure of IndustryPack bandwidth for DMA burst cycles between a local bus slave and a memory or I O space location on an IndustryPack It assumes a zero wait state acknowledge reply from the IndustryPack 3 This column is a measure of IndustryPack bandwidth for DMA single cycles between a local bus slave and a memory or I O space location on an IndustryPack It assumes a zero wait state acknowledge reply from the IndustryPack 4 Burst mode sDMA is not supported when both bus frequencies are 32MHz 5 Because the specified bandwidth assumes a zero wait state IndustryPack cycle it would be difficult to achieve the stated bandwidths for an IP bus frequency of 32MHz http www motorola com computer literature 2 Functions Programmable Clock The IP2 sector implements a general purpose programmable clock output for external connection to the IndustryPacks This feature complies with the STROBE funct
285. otorola com computer literature 3 3 MC2 Functions Each MPU Port access must consist of two 16 bit writes Upper Command Word two bytes and Lower Command Word two bytes The Upper Command Word two bytes is mapped at FFF46000 and the Lower Command Word two bytes is mapped at FFF46002 The Petra MC2 chip only supports decodes MPU Port writes It does not decode MPU Port reads Nor does the 82596CA support MPU Port reads MPU Channel Attention access is used to cause the 82596CA to begin executing memory resident Command blocks To execute an MPU Channel Attention the MC680x0 processor bus master performs a simple read or write to address FFF46004 MC680x0 Bus Master Support for 82596CA The 82596CA has DMA capability with an Intel i486 bus interface When it is the local bus master external hardware is needed to convert its bus cycles into MC680x0 bus cycles When the 82596CA has local bus mastership the Petra MC2 chip drives the following MC680x0 signal lines Snoop Control SC1 SCO with the value programmed into the LAN Interrupt Control register Transfer Types TT1 TTO with the value of 00 Transfer Modifiers TM2 TMO with the value of 76101 a Transfer Start Read Size Transfer in progress LANC Bus Error The 82596 does not provide a way to terminate a bus cycle with an error indication Bus errors are processed as follows 3 4 Computer Group Literature Center Web S
286. ounter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to the bit Computer Group Literature Center Web Site LCSR Programming Model Tick Timer 1 Control Register Prescaler Counter ADR SIZ FFF40060 8 bits of 32 BIT 7 5 4 3 2 1 0 COVF COC EN OPER R R W R W RESET 0 PS 0 PS 0 PS 0 PS EN When this bit is high the counter increments When this bit is low the counter does not increment COC When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The overflow counter is cleared when a 1 is written to this bit OVF These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to the COVE bit ADR SIZ FFF40064 32 bits BIT 31 0 NAME Prescaler Counter OPER R W RESET OP The VMEchip2 has a 32 bit prescaler that provides the clocks required by the various timers in the chip Access to the prescaler is provided for test purposes The counter is described here because it may be useful in other applications The lower 8 bits of the prescaler counter increment to FF at the local bus cloc
287. paragraph b 3 of the Rights in Technical Data clause at DFARS 252 227 7013 Nov 1995 and of the Rights in Noncommercial Computer Software and Documentation clause at DFARS 252 227 7014 Jun 1995 Motorola Inc Computer Group 2900 South Diablo Way Tempe Arizona 85282 Contents About This Manual Summary of CHANGES xxii Piera OL DTE xxii Comments and Suggesting xxiii Conventions Used in This och He anced anid nied Xxiv CHAPTER 1 Board Description and Memory Maps riui T 1 1 E 1 2 The Petra ASIC and Second Generation MVME1X2 Boards 1 2 TORON 1 3 e 1 5 1 5 Applicable Industry Standards 1 7 ric gr AAO 1 7 qure lc 1 9 VMEbus Interface and 1 9 Memory Mapi R R 1 11 Local Bus Memory 1 11 Address 1 11 Detailed doro PES 1 17 BBRAM TOD Clock Memory 1 33 Interrupt Acknowledge
288. porated into a single ASIC the Petra chip on the MVME1X2P4 The two memory controllers modeled in Petra duplicate the functionality of the parity memory controller found in the MC2 ASICs as well as that of the single bit error correcting double bit error detecting memory controller found in the MCECC ASICs For ease of use in conjunction with programming models and documentation developed for earlier boards however the structure of this manual preserves the functional distinctions that formerly characterized the MC2 IP2 and MCECC ASICs This chapter describes the MCECC sector of the Petra chip The MCECC ASICs used in a set of two provided the interface to a 144 bit wide DRAM memory array The Petra implementation provides an interface to a 40 bit SDRAM memory array There are 32 bits for data 7 for check bits and one bit that is not used SDRAM configurations that allow array sizes of 16MB to 128MB are supported For a complete description of the memory configurations that are supported refer to the definition of the SDCFG2 SDCFGO0 bits in the SDRAM Configuration register 5 1 Functions Features MCECC functions now implemented on the Petra chip include Table 5 1 MCECC Functions on the Petra ASIC Function Memory Control Features 2 1 1 1 memory accesses sustained for burst writes 4 1 1 1 memory accesses sustained for burst reads 5 1 1 1 with BERR on or when FSTRD is cleared
289. pt is disabled DINT When this bit is high an interrupt will be generated for a DMAC if the DIEN bit is set to a 1 The interrupt is at the level programmed in DL2 DLO The DINT bit is set when one of the following bits are set in the Status register DLBE IPEND CHANI IPTO and DONE 4 36 Computer Group Literature Center Web Site Programming Model DMA Enable Register ADR SIZ FFFBC022 3A 52 6A 8 bits each OR OR OR OR OR OR Setting the DEN bit to a 1 will enable the DMA function Software should not write to the DMA control registers between the time the DEN bit is set and the DMA process is completed In general this is true on a per channel basis but there are interrelationships between the DMA channels board architecture which require the initialization of certain bits for each pair of DMA channels before the DEN bits can be set That is if DMA channels a and b are going to be used concurrently DMA Control Register 1 should be initialized for both channels before either channel is enabled This is also true for DMA channels c and d Refer to the section on the DMA Enable function for further details http www motorola com computer literature 4 37 IP2 Functions DMA Control Register 1 ADR SIZ FFFBCO24 3C 54 6C 8 bits each BIT 7 6 5 4 3 2 1 0 DHALT 0 DTBL ADMA WIDTH WIDTHO A C
290. r 3 When this bit is high D16 data transfers are performed to the segment defined by map decoder 3 When this bit is low D32 data transfers are performed to the segment defined by map decoder 3 2 44 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Slave VMEbus Master Attribute Register 2 ADR SIZ FFF40028 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME D16 WP AM OPER R W R W R W RESET OPS OPS OPS This register is the attribute register for the second local bus to VMEbus bus map decoder AM WP D16 These bits define the VMEbus address modifier codes that the VMEbus master uses for the segment defined by map decoder 2 Since the local bus to VMEbus interface does not support block transfers the block transfer address modifier codes should not be used When this bit is high write posting is enabled to the segment defined by map decoder 2 When this bit is low write posting is disabled to the segment defined by map decoder 2 When this bit is high D16 data transfers are performed to the segment defined by map decoder 2 When this bit is low D32 data transfers are performed to the segment defined by map decoder 2 http www motorola com computer literature 2 45 VMEchip2 Local Bus Slave VMEbus Master Attribute Register 1 ADR SIZ FFF40028 8 bits of 32 BIT 7 6 2 4 3 2 1 0 NAME D16 WP AM OPER R W R W R W RESET
291. r example if offset 19 is set to the value 09 then offset http www motorola com computer literature 4 25 IP2 Functions 18 can be set to 04 05 08 or 09 but not to 00 or 01 The same relationship also pertains to IP c and IP d i e when programming d WIDTHI d WIDTHO for either 8 bits or 16 bits c_WIDTH1 c_WIDTHO must be programmed for a width of 8 bits or 16 bits This applies whether or not c MEN is set RTO The recovery timers determine the time that must expire from the acknowledgment of an IndustryPack I O ID or Interrupt Acknowledge cycle until the IP2 sector asserts a new I O ID or Int SEL to the same IndustryPack This may help with some devices on IndustryPacks that require dead time between cycles Each recovery timer s counter starts incrementing at the assertion of its IPACK signal and continues to increment until it matches the value encoded from its two recovery timer control bits When it reaches that value the recovery time has expired and a new cycle can be generated to the IndustryPack The recovery timer counters are cleared at reset The recovery times encoded by the recovery timer control bits are shown in the following table When a double size IndustryPack is used at ab and the I O space for ab is accessed in the double size address range the RT bits for a and b should be programmed identically The same pertains to the RT bits for c and d 0 Recovery T
292. r literature 4 21 2 Functions Memory Size Registers IP_a IP_b IP_c IP_d As with the memory base address registers the IP_a size register is also used to control accesses to double size IP_ab and the IP_c size register is used to control accesses to double size IP_cd ADR SIZ FFFBCOOC through FFFBCOOF 8 bits each BIT 7 6 5 4 3 2 1 0 NAME 0C 257523 512822 51701 SIZE20 a SIZEI9 a SIZEI8 a SIZEI7 a SIZEI6 NAME 0D b SIZE23 b_SIZE22 b SIZE21 b_SIZE20 b SIZEI9 b SIZEI8 b SIZEI7 b_SIZEI6 0 SIZE c SIZE2 c SIZE c SIZE0 c SIZEI9 c SIZEI8 c SIZEI7 SIZEI 0 d 512223 SIZE22 SIZE21 d SIZE20 d SIZEI9 d SIZEIS d SIZEI7 d SIZEIG OPER R W R W R W R W R W R W R W R W RESET OR OR OR OR OR OR OR OR SIZE23 16 A B C D SIZE should be programmed to match the size of the corresponding IndustryPack memory space The IP2 sector performs its IP memory sizing by masking any bit in BASE23 BASE16 whose corresponding SIZE23 SIZE16 bit is set The following table shows this Note that only certain combinations of the SIZE bits those shown in the table make sense Any other combination of the SIZE bits yields unpredictable results Size Bits Address Lines Resulting that Are 23 22 21 20 19 18 17 16 Compared Memory
293. r that can be set and cleared under software control The term true is used to indicate that a bit is in the state that enables the function it controls The term false is used to indicate that the bit is in the state that disables the function it controls In all tables the terms 0 and are used to describe the actual value that should be written to the bit or the value that it yields when read The term status bit is used to describe a bit in a register that reflects a specific condition The status bit can be read by software to determine operational or exception conditions XXV Board Description and Memory Maps Introduction This manual supplies programming information for the MVME162P4 and MVME172P4 Embedded Controllers known collectively as the MVME1X2P4 Extensive programming information is provided for the Application Specific Integrated Circuit ASIC devices used on the board Reference information is also included for the Large Scale Integration LSI devices used on the board and sources for additional information are provided as well This chapter briefly describes the board level hardware features of the MVMEIX2P4 Embedded Controller The chapter begins with a board level overview and features list Memory maps are next and the chapter closes with some general software considerations such as cache coherency interrupts and bus errors All programmable registers that reside in ASICs on the
294. re Center Web Site Functional Description IP Bus Reset Compatibility 1 2 implementations for the IP bus reset are different configuration switch S5 pin 3 determines the method Petra will emulate IP Bus Reset Mode S5 Pin 3 mode Off IP2 mode On A new status bit in the IP RESET register at address F FFBCOIF reflects the bus reset mode At bit location 01 RESET indicates that the IP reset will follow the programmatic interface established in the ASIC If the bit is cleared the IP2 interface is used Functional Description The following sections provide an overview of the functions provided by the Petra IP2 sector A detailed programming model for the Petra IP2 chip control and status registers appears in a later section of this chapter General Description The IP2 sector converts IP bound MC680x0 Read Write Interrupt Acknowledge cycles to IndustryPack cycles Control registers within the IP2 sector control the assumed width of the IndustryPack that is being accessed The IP2 sector interfaces to four 16 bit IndustryPack positions The naming convention for single size IndustryPack population of each of these positions is IndustryPack a IP a IndustryPack b IP b IndustryPack c IP c and IndustryPack d IP d The naming convention for double size IndustryPack population of these positions is IndustryPack a b IP ab and IndustryPack c d IP cd A
295. re programmable The SRAM controller is designed to operate with 100 ns devices The size of the SRAM is initialized in the DRAM SRAM Options register when the MVMEIX2PA is reset SRAM performance at 25MHz is 5 3 3 3 for read and write cycles SRAM performance at 33MHz is 6 4 4 4 for read cycles and 6 3 3 3 for write cycles http www motorola com computer literature 3 5 MC2 Functions SDRAM Memory Controller The Petra ASIC presents two interfaces to the SDRAM memory array The two memory controllers modeled in Petra duplicate the functionality of the parity memory controller found in the MC2 ASICs as well as that of the single bit error correcting double bit error detecting memory controller found in the MCECC ASICs The SDRAM memory array itself is always a single bit error correcting and multi bit error detection memory irrespective of which interface model you use to access the SDRAM When the MC2 memory controller interface is used to access the SDRAM single bit errors are undetectable to the user and multi bit errors are defined to be parity errors Memory scrubbing is not functional when the MC2 memory model is enabled Firmware will initialize the memory controller to maintain backward compatibility with MVMEIX2LX 21 or FX 41 products If the Petra ASIC is supporting MVME1X2FX functionality the parity memory controller model will be enabled If the Petra ASIC is supporting MVMEIX2LX functionality firmw
296. register 2 This bit is cleared when DMA is enabled A DMAC interrupt will be generated if interrupts are enabled http www motorola com computer literature 4 35 IP2 Functions IPENDI DLBE The IPEND 1 bit is set if an early termination of DMA data is detected and the dmaeil bit is set in Alternate Control Register 2 Setting this bit does not in itself cause an interrupt the DMA interrupt associated with this activity occurs when the Done status bit 0 is set The IPENDI bit is part of the fix to allow the use of the IP bus protocol which asserts the DMA DONE signal The IPEND bit functionality remains unchanged so that it is backward compatible with the IP2 design When this bit is set DMAC received a TEA TEA is a transfer error acknowledge signal on the MC680x0 local bus It indicates that a time out has occurred This bit is cleared when DMAC is enabled A DMAC interrupt will be generated if interrupts are enabled DMA Interrupt Control Register ADR SIZ FFFBC021 39 51 69 8 bits each BIT 7 6 5 4 3 2 1 0 0 0 DINT DIEN DICLR DIL2 DIL1 DILO OPER R R R R W R W R W R W RESET OR OR IR OR OR OR OR OR DIL2 DILO These three bits select the interrupt level for DMA Level 0 does not generate an interrupt DICLR Writing a logic 1 to this bit clears the DINT status bit DIEN When DIEN is set the interrupt is enabled When DIEN is cleared the interru
297. registers 2 103 VMEchip2 LCSR 1 18 VMEchip2 LCSR summary 2 22 785230 SCC registers 1 31 memory mezzanine serial number 1 38 memory space 16 bit IP a 4 51 32 bit IP ab 4 52 8 bit IP a 4 50 memory space accesses IP 4 56 microprocessors used on board 1 6 MIEN master interrupt enable bit 2 74 2 96 3 12 MPU local bus time out 1 44 off board error 1 44 parity error 1 43 Status register programming 2 51 TEA error cause unidentified 1 44 MVME1x2P4 features 1 6 functional description 1 9 microprocessors 1 6 Version register 3 34 MVME712x transition boards 1 3 N no address increment DMA transfers 2 12 non privileged access cycles VMEbus 2 34 2 37 IN 8 Computer Group Literature Center Web Site Non Volatile RAM NVRAM 1 6 memory map 1 33 see BBRAM 1 33 overflow counter VMEchip2 ASIC 2 72 2 73 overview MVME1x2P4 1 2 parity errors 1 42 1 43 performance MCECC sector 5 3 Petra ASIC functionality of 1 2 IP2 functions 4 1 MC2 functions 3 1 MCECC functions 5 1 periodic interrupt example B 1 Petra 2 redundancies 1 9 power monitor function VMEbus 2 17 powerup reset VMEchip2 ASIC 2 70 prescaler VMEchip2 2 14 Priority PRI arbitration mode VMEbus 2 17 priority of interrupts 1 40 processor bus master support for 82596CA 3 4 processor to VMEbus transfers 1 5 program access cycles VMEbus 2 33 2 36 program address modifier code VMEbus 2 50 programmable map decoders 2
298. requency for the tick timers is the processor clock divided by two The value FF is not allowed to be programmed into this register If a write with the value of FF occurs to this register the cycle terminates correctly but the register remains unchanged ADR SIZ FFF42014 8 bits BIT 23 m 16 NAME Prescaler Clock Adjust OPER R W RESET DFP http www motorola com computer literature MC2 Functions Tick Timer 1 and 2 Control Registers Each tick timer has a control register The control registers for timers and 2 are defined in this section Control registers for timers 3 and 4 are described in a later section Tick Timer 2 Control Register ADR SIZ FFF42014 8 bits BIT 15 14 13 12 11 10 9 8 NAME OVE2 OVFI OVFO COVF COC CEN OPER R R R R R C R W R W RESET 0 PL 0 PL 0 PL 0 Tick Timer 1 Control Register ADR SIZ FFF42014 8 bits BIT 7 6 5 4 3 2 1 0 NAME OVE2 OVHI OVFO OPER R R R R R R W RESET 0 When this bit is high the counter increments When this bit is low the counter does not increment COC When this bit is high the counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF The ove
299. reset SYSRESET or power up reset Use caution when enabling the map decoders or when modifying their registers after they are enabled The safest time to enable or modify the map decoder registers is when the VMEchip2 is VMEbus master To modify the map decoder registers follow this procedure Set the DWB bit in the LCSR and then wait for the DHB bit in the LCSR to be set indicating that VMEbus mastership has been acquired The map decoder registers can then be modified and the VMEbus released by clearing the DWB bit in the LCSR Because the VMEbus is held during this programming operation the registers should be programmed quickly with interrupts disabled The VMEbus slave map decoders can be programmed without obtaining VMEbus mastership if they are disabled and the following procedure is followed The address translation registers and starting and ending address registers should be programmed first and then the map decoders should be enabled by programming the address modifier select registers 2 26 Computer Group Literature Center Web Site LCSR Programming Model You program a VMEbus slave map decoder by loading the starting address of the segment into the starting address register and the ending address of the segment into the ending address register If the VMEbus address modifier codes indicate an A24 VMEbus address cycle then the upper eight bits of the VMEbus address are forced to 0 before the compare The address mo
300. rflow counter is cleared when 1 is written to this bit OVF3 OVF0 These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter can be cleared by writing a 1 to Computer Group Literature Center Web Site Programming Model Tick Timer Interrupt Control Registers There are four tick timer interrupt control registers The register format is the same for all four registers Tick Timer 4 Interrupt Control Register ADR SIZ FFF42018 8 bits BIT 31 30 29 28 27 26 25 24 NAME INT IEN ICLR IL2 ILI ILO OPER R R R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL Tick Timer 3 Interrupt Control Register ADR SIZ FFF42018 8 bits BIT 23 22 21 20 19 18 17 16 INT IL2 IL1 ILO OPER R R R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL 0 PL Tick Timer 2 Interrupt Control Register ADR SIZ FFF4201A 8 bits BIT 15 14 13 12 11 10 9 8 NAME INT IEN ICLR IL2 IL1 ILO OPER R R R W C R W R W R W RESET 0 0 0 PL 0 PL 0 PL 0 PL 0 PL http www motorola com computer literature MC2 Functions Tick Timer 1 Interrupt Control Register ADR SIZ FFF4201B 8 bits BIT 7 6 5 4 3 2 1 0 INT
301. rity 3 14 Table 3 6 DRAM Size Control Bit Encoding 2 22222002 retine sonis 3 26 Table 3 7 DRAM Size Control Bit Encoding aa seen erp rp epe 3 27 Table 3 8 SRAM Size Control Bit Encoding esent tarte ER iioi 3 28 Table 3 9 SRAM 5126 Control Bit Encodifig ee narices 3 20 Table 4 T TP2 Functions on the Petra ASIC EARS Eb op Rede nas 4 1 Table 4 2 sector Clock 4 7 Table 4 3 Sector Overall Memory eset ettet stants sande tates tapas 4 10 Table 4 4 Petra IP2 Memory Map Control Status Registers 4 12 Table 5 1 MCECC Functions on the Petra ASIC 5 2 Table 3 2 Memory System Cycle TUIS uiis vo imet E 5 4 xix Table 5 3 MCECC Sector Internal Register Memory 5 11 Table 5 4 Syndrome Bit ERCOUNYB 5 36 Table 5 5 Identifying SDRAM Bank in Error eee 5 37 Table A 1 List of 1 Table 1 Motorola Computer Group Documents oreet 1 Table C 2 Manufacturers DoCut ents suis Laver capes C 2 Table 0 3 Related Specific OFS C 3 XX About This Manual This manual provides board level information and detailed ASIC information including regist
302. rrupt and status are provided in the Petra MC2 sector Control for the interrupt is in the MC2 sector s LAN Error Interrupt Control register FFF4202B LAN LTO Error Description Local Bus Time out occurred while the LANCE was Local Bus master MPU Notification Petra MC2 Sector Interrupt LAN ERROR IRQ Status Petra MC2 Sector LAN Error Status register Address FFF42028 Comments The LANCE has no ability to respond to TEA so the error interrupt and status are provided in the Petra MC2 sector Control for the interrupt is in the MC2 sector s LAN Error Interrupt Control register FFF4202B 1 48 Computer Group Literature Center Web Site Software Support Considerations SCSI Parity Error Note Description MPU Notification Status Comments SCSI Offboard Error Description MPU Notification Status Comments Although the MVME1X2P4 series contains synchronous DRAM SDRAM rather than parity DRAM it can be made to emulate parity DRAM for compatibility with the MC2 programming model Parity error detected while the 53C710 was reading DRAM 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register Petra MC2 Sector SCSI Error Status register Address FFF4202C 53C710 interrupt enables are controlled in the 53C710 and in the Petra MC2 sector s SCSI Interrupt Control register SFFF4202F Error encountered while the 53C710 was attempting to go to the VMEb
303. rupt 2 82 Computer Group Literature Center Web Site LCSR Programming Model Local Bus Interrupter Enable Register bits 8 15 ADR SIZ FFF4006C 8 bits of 32 BIT 15 14 13 12 11 10 9 8 NAME ESW7 ESW6 ESW5 ESW4 ESW3 ESW2 ESWI ESWO OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This is the local bus interrupter enable register When an enable bit is high the corresponding interrupt is enabled When an enable bit is low the corresponding interrupt is disabled The enable bit does not clear edge sensitive interrupts or prevent the flip flop from being set If necessary edge sensitive interrupters should be cleared to remove any old interrupts and then re enabled ESWO0 ESWI1 ESW2 ESW3 ESW4 ESWS ESW6 ESW7 Enable software 0 interrupt Enable software 1 interrupt Enable software 2 interrupt Enable software 3 interrupt Enable software 4 interrupt Enable software 5 interrupt Enable software 6 interrupt Enable software 7 interrupt http www motorola com computer literature 2 83 VMEchip2 Local Bus Interrupter Enable Register bits 0 7 ADR SIZ FFF4006C 8 bits of 32 BIT 9 6 5 4 3 2 1 0 SPARE EIRQ7 EIRQ6 EIRQS EIRIQ4 EIRQ3 EIRQ2 EIRQI OPER gw RW RW RW RW RW RW RESET oPsL OPSL OPSL
304. rupt Control Register ADR SIZ FFF42028 8 bits BIT 7 6 5 4 3 2 1 0 NAME 5 5 0 INT IEN ICLR IL2 IL1 ILO OPER R W R W R R W C R W R W R W RESET 0 PL 0 PL 0 PL 0 PL 0 0 PL 0 PL 0 PL IL2 ILO Interrupt Request Level These three bits select the interrupt level for the 82596 LANC bus error condition Level 0 does not generate an interrupt ICLR Writing a logic 1 into this bit clears the INT status bit This bit is always read as 0 Interrupt Enable When this bit set high the interrupt is enabled The interrupt is disabled when this bit is low INT Interrupt Status When this bit is high a LANC Bus Error interrupt is being generated at the level programmed in IL2 ILO http www motorola com computer literature 3 31 MC2 Functions SC1 SCO Snoop Control These control bits determine the value that the Petra MC2 chip drives onto the local processor bus 5 and SCO pins when the 82596CA LANC performs DMA accesses The snooping functions differ according to processor type as shown Requested Snoop Operation 5 0 MC68040 MC68060 0 0 Snoop disabled Snoop enabled 0 1 Source dirty sink byte word longword Snoop disabled 1 0 Source dirty invalidate line Snoop enabled 1 1 Snoop disabled Reserved Snoop disabled SCSI Error Status Register ADR SIZ FFF4202C 8 bits BIT 31 30 29 28
305. ry Accesses are enabled when this bit is set and are disabled when this bit is cleared This bit should only be set after BAD31 BAD22 have been initialized http www motorola com computer literature 5 15 Functions NCEBEN Setting the control bit enables the MCECC pair RWB3 RWB4 RWB5 to assert TEA when a non correctable error occurs during a local bus access to memory In some cases setting NCEBEN causes DRAM accesses to be delayed by one clock This delay is incurred when the access is a local bus or scrub read and the FSTRD bit is set When NCEIEN is set the logging of a non correctable error causes the INT signal pin to pulse true Note that NCEIEN has no effect on DRAM access time Read Write Bit 3 is a general purpose read write bit Read Write Bit 4 is a general purpose read write bit Read Write Bit 5 is a general purpose read write bit BAD22 BAD23 These are the lower two bits of the DRAM base address described in the previous register BCLK Frequency Register The Bus Clock BCLK Frequency register should be programmed with the hexadecimal value of the operating clock frequency in MHz i e 19 for 25MHz and 21 for 33MHz The MCECC sector pair uses the value programmed in this register to control the Prescaler counter The Prescaler counter increments to FF and then it is loaded with the two s complement of the value in the BCLK Frequency register This pro
306. ryPack interrupt request Level 0 does not generate an interrupt ICLR In edge sensitive mode writing a logic 1 to this bit clears the corresponding INT status bit In level sensitive mode this bit has no function It always reads as 0 IEN When IEN is set the interrupt is enabled When IEN is cleared the interrupt is disabled INT When this bit is high an interrupt is being generated for the corresponding IndustryPack IRQ The interrupt is at the level programmed in IL2 ILO E L When this bit is high the interrupt is edge sensitive When the bit is low the interrupt is level sensitive PLTY When this bit is low interrupt is activated by a falling edge low level of the IndustryPack IRQ When this bit is high interrupt is activated by a rising edge high level of the IndustryPack IRQ Note that if this bit is changed while the E L bit is set or is being set an interrupt may be generated This can be avoided by setting the ICLR bit http www motorola com computer literature 4 23 IP2 Functions during write cycles that change the PLTY bit Because IndustryPack IRQ signals are active low PLTY would normally be cleared General Control Registers IP_a IP_b IP_c IP_d ADR SIZ FFFBCO18 through FFFBCO1B 8 bits each BIT 7 6 5 4 3 2 1 0 1 8 a_ERR 0 a RTI a_RTO a WIDTHI a WIDTHO a BTD a MEN NAME 19 b ERR 0 b RTI b RTO b WIDTHI b_WID
307. s 13 16 6 32 ms 14 32 5 7 64 ms 15 64 5 These bits define the local bus time out value The timer begins timing when TS is asserted on the local bus If TA or TAE is not asserted before the timer times out a TEA signal is sent to the local bus The timer is disabled if the transfer is bound for the VMEbus 0 86 2 256 us 1 64 3 The timer is disabled VATO These bits define the VMEbus access time out value When a transaction is headed to the VMEbus and the VMEchip2 is not the current VMEbus master the access timer begins timing If the VMEchip2 has not received bus mastership before the timer times out and the transaction is not write posted a TEA signal is sent to the local bus If the transaction is write posted a write post error interrupt is sent to the local bus interrupter 0 64 5 2 3215 1 lms 3 The timer is disabled 2 66 Computer Group Literature Center Web Site LCSR Programming Model Prescaler Control Register ADR SIZ FFF4004C 8 bits of 32 BIT 1 0 Prescaler Adjust OPER R W RESET DF P The prescaler provides the various clocks required by the counters and timers in the VMEchip2 In order to specify absolute times from these counters and timers the prescaler must be adjusted for different local bus clocks The prescaler register should be programmed based on the following equation This provides a 1MHz clock to the Tick timers prescaler register 256
308. s controller interface 3 7 register addresses 1 31 scrubbing function MCECC sector 5 8 SCSI controller interface 3 5 ID 1 38 Interrupt Control register 3 35 error 1 50 memory map 1 32 off board error 1 49 parity error 1 49 sDMA standard DMA 4 4 SDRAM implementation 1 3 3 6 5 1 5 5 SDRAM memory controller Petra MC2 chip 3 6 segment size VMEbus addressing 2 31 segment size translating 2 30 SERCLK driver 2 17 serial communications interface 3 7 short I O area VMEchip2 ASIC 2 6 short I O map decoder VMEbus 2 50 short I O memory map 1 40 short I O segment VMEbus 2 50 short I O space VMEbus 2 37 2 100 signal interrupts SIGO SIG3 VMEchip2 ASIC 2 100 Single SGL arbitration mode VMEbus 2 17 size VMEbus segment 2 30 2 31 slave map decoders VMEbus 2 26 snoop bits enabling 2 28 snoop control 4 4 4 31 bits 2 53 register 2 32 snoop function enabling 2 32 2 35 snoop signal lines DMAC 2 58 snooping definition of 1 41 2 10 software 7 0 interrupters VMEbus 2 19 software interrupts 1 6 software support considerations 1 40 specification documents C 3 specifications applicable 1 7 MCECC sector 5 4 speed board 1 37 SRAM memory controller 3 5 size control bit encoding Petra MC2 chip 3 28 3 29 specifications 1 6 standard access cycles VMEbus 2 34 2 36 standard DMA sDMA 4 4 starting address register VMEbus slave 2 38 starting address register slave map decoder 2 27 status LEDs 1 7 status re
309. s differ according to processor type as shown SNP2 Requested Snoop Operation 26 25 MC68040 MC68060 0 0 Snoop disabled Snoop enabled 0 1 Source dirty sink byte word longword Snoop disabled 1 0 Source dirty invalidate line Snoop enabled 1 1 Snoop disabled Reserved Snoop disabled ADDER2 When this bit is high the adder is used for address translation When this bit is low the adder is not used for address translation Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Address Modifier Select Register 2 ADR SIZ FFF40010 8 bits of 32 BIT 23 22 21 20 19 18 17 16 NAME SUP USR A32 A24 D64 BLK PGM DAT OPER R W R W R W R W R W R W R W R W RESET OPSL OPSL OPSL OPSL OPSL OPSL OPSL OPSL This register is the address modifier select register for the second VMEbus to local bus map decoder There are three groups of address modifier select bits DAT PGM BLK and D64 A24 and A32 and USR and SUP At least one bit must be set from each group to enable the map decoder DAT When this bit is high the second map decoder responds to VMEbus data access cycles When this bit is low the second map decoder does not respond to VMEbus data access cycles PGM When this bit is high the second map decoder responds to VMEbus program access cycles When this bit is low the second map decoder does not respond to VM
310. s equipped with a second generation Petra ASIC All other particulars of the board remain the same This manual is intended for anyone who designs OEM systems adds capability to an existing compatible system or works in a lab environment for experimental purposes A basic knowledge of computers and digital logic is assumed To use this manual you may also wish to become familiar with the publications listed in Appendix C Related Documentation Summary of Changes This is the second edition of the Programmer s Reference Guide It supersedes the July 2000 edition and incorporates the following updates Date Description of Change October 2000 The part number of the manual was changed from V1X2PFXA PGI to V1X2P4A PG1 to better reflect board nomenclature October 2000 Descriptions of the snoop function on boards equipped with the MC68060 processor as described on page 2 32 for example have been updated October 2000 References to IP2 and MC2 revision levels at various points in the text in Chapter 3 under MC2 Sector Revision Register for example were incremented from 02 to 03 to reflect this change in the Petra chip October 2000 References in Chapter 4 to an irregularity in the behavior of the DMA halt function across DMA channels A B C and D as described on page 4 32 for example were dropped as this anomaly has been corrected Overview of Contents Chapter 1 Board Description and Mem
311. s master has been retried off the local bus is 32 local bus clocks When this bit is high the minimum VMEbus 5 time when the local bus master has been retried off the local bus is 3 local bus clocks When a local bus master attempts to access the VMEbus and a VMEbus master attempts to access the local bus a deadlock is created The VMEchip2 detects this condition and requests the local bus master to give up the local bus and retry the cycle This allows the VMEbus master to complete the cycle to the local bus If the VMEchip2 receives VMEbus mastership the local master has not returned from the retry and this bit is high VMEchip2 drives VMEbus BBSY for the minimum time about 90 ns and then releases the VMEbus If the local master does not return from the retry within this 90 ns window the board loses its turn on the VMEbus If the VMEchip2 receives VMEbus mastership the local master has not returned from the retry and this bit is low VMEchip2 drives VMEbus BBSY for a minimum of 32 local bus clocks which allows the local bus master time to return 2 08 Computer Group Literature Center Web Site LCSR Programming Model from the retry and the board does not lose its turn on the VMEbus For this reason it is recommended that this bit remain low NOELBBSY When this bit is high the early release feature of bus busy feature on the VMEbus is disabled The VMEchip2 drives BBSY low whenever VMEbus AS is low When t
312. s on the MVMEIX2PA It gives an example of how to generate and handle a VMEchip2 Tick Timer 1 interrupt on an MVME1X2P4 that has a VMEbus connection Specific values have been given for the register writes Read this entire appendix before performing any of these procedures 1 Set up Tick Timer Step Register and Address Prescaler Control register FFF4004C Action and Reference If not already initialized by the debugger initialize as follows Prescaler register 256 Bclock MHz This gives a 1 MHz clock to the tick timers Bclock is the bus clock rate such as 25MHz 256 25 E7 2 Tick Timer 1 For periodic interrupts set the Compare Register value Compare register Period s For example if you want an interrupt every FFF40050 millisecond set the register value to 1000 3E8 Refer to the Tick Timer 1 Compare Register description in Chapter 2 3 Tick Timer 1 Write a zero to clear the register Counter register FFF40054 4 Tick Timer 1 Write 07 to this register set bits 0 1 and 2 This Control register FFF40060 8 bits enables the Tick Timer 1 counter to increment resets the count to zero on compare and clears the overflow counter 1 Using Interrupts the MVME1X2P4 2 Set up local bus interrupter Step Register and Address Action and Reference 5 Vector Base register If not already initialized by the debugger set Interrupt FFF40088 8 of 32 bits
313. sabled via Flash writes enabled disabled via enable control bit in register board configuration jumper page 3 39 MC2 memory model No parity protection for MC2 memory MC2 memory has ECC capability if due to availability of DRAM devices parity is enabled Multibit errors are announced as parity errors Scrubbing is not enabled Debugger firmware should enable parity for optimum functionality page 3 6 IP interface control IP2 ASIC revision 00 Petra ASIC revision 03 page 4 18 IP reset IP Reset Control bit in local bus IP Reset bit is under control of memory map at location FFFBCOIF software configuration switch page Local bus resets power up resets and 4 30 software writes to this location all influence IP reset status IP DMA flush DMA bug in IP2 ASIC no flush New control register bit supplies flush mechanism mechanism IP DMA FIFOs will flush if a DMA data stream ends before the byte count reaches zero page 4 47 1 Summary of Changes Table A 1 List of Changes Continued Function Previous Implementation MVME1X2P4 Implementation IP DMA chaining IP chained DMA functional at MHz Chained DMA now functional with but not at 32MHz 32MHz IP bus frequency as well as 8MHz page 4 2 IP DMA snoop DMA Snoop control bug IP2 ASIC Two reliable snoop control bits for occasional loss of snoop control signals SC 1 0 each of the four DM
314. safety ground at the power outlet The power jack and mating plug of the power cable meet International Electrotechnical Commission IEC safety standards and local electrical regulatory codes Do Not Operate an Explosive Atmosphere Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage Keep Away From Live Circuits Inside the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries such personnel should always disconnect power and discharge circuits before touching components Use Caution When Exposing or Handling a CRT Breakage of a Cathode Ray Tube CRT causes a high velocity scattering of glass fragments implosion To prevent CRT implosion do not handle the CRT and avoid rough handling or jarring of the equipment Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves Do Not Substitute Parts or Modify Equipment Do not install substitute
315. se of an MC68040 MC68L C040 processor 60MHz for an MC68060 or 64MHz for an MC68LC060 The IndustryPack interface is controlled by the IndustryPack clock The IndustryPack clock can be 8MHz or set equal to the local bus clock When logic signals cross from one clock domain to another they must be synchronized to the new clock frequency The latency time due this synchronization is generally hidden due to the FIFOs in the data path However there are two functions where the latency time affects performance One of them is when a local bus master such at the MC680x0 accesses an IndustryPack resource such as reading back to back memory locations One to two IP clock cycles of overhead is associated with this function The other is when arbitration logic must resolve inputs from both clock domains to determine which IndustryPack will be granted DMA service There are two IP clock cycles of overhead associated with this function The following table explains the effect of this latency for given clocking environments The bandwidth specified in thetable is the bandwidth available to the IndustryPack bus It can be split between one two three or four IP modules 4 6 Computer Group Literature Center Web Site Functional Description Table 4 2 IP2 sector Clock Cycles Bus Frequency Period and Bandwidth to 32 Bit IP Space Back to Back Four Cycle Single Cycle MC68060 IP Examine DMA Burst DMA Note 1 N
316. sensitive interrupts If necessary edge sensitive interrupts should be cleared in order to remove any old interrupts and then re enabled The master interrupt enable MIEN bit must be set before the VMEchip2 can generate any interrupts The MIEN bit is in I O Control Register 1 Computer Group Literature Center Web Site LCSR Programming Model Table 2 4 Local Bus Interrupter Summary Vector UN icio VMEbus IRQI External Lowest VMEbus IRQ2 External A VMEbus IRQ3 External VMEbus IRQ4 External VMEbus 5 External VMEbus IRQ6 External VMEbus IRQ7 External Spare Y7 Software 0 Y8 Software 1 Y9 Software 2 YA Software 3 YB Software 4 Software 5 YD Software 6 YE Software 7 YF GCSR LMO X0 GCSR LM1 X1 GCSR SIGO 2 SIGI 3 5162 4 6163 5 http www motorola com computer literature 2 75 VMEchip2 Table 2 4 Local Bus Interrupter Summary Continued interrupt Vector DMAC X6 VMEbus Interrupter Acknowledge X7 Tick Timer 1 8 2 9 VMEbus 1 Edge Sensitive XA Not used on MVME1 X2P4 XB VMEbus Master Write Post Error XC VMEbus SYSFAIL XD Not used on MVME1X2P4 XE Y VMEbus ACFAIL XF Highest Notes 1 X The contents of vector base register 0 2 The contents of vector b
317. st Please contact your sales representative Notice While reasonable efforts have been made to assure the accuracy of this document Motorola Inc assumes no liability resulting from any omissions in this document or from the use of the information obtained therein Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to the Motorola Computer Group website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Motorola Inc It is possible that this publication may contain reference to or information about Motorola products machines and programs programming or services that are not available in your country Such references or information must not be construed to mean that Motorola intends to announce such Motorola products programming or services in your country Limited and Restricted Rights Legend If the documentation contained herein is supplied directly or indirectly to the U S Government the following notice shall apply unless otherwise agreed to in writing by Motorola Inc Use duplication or disclosure by the Government is subject to restrictions as set forth in sub
318. ster 2 the refresher and 3 the scrubber The MCECC pair arbiter accepts requests and provides grants to the requesting entities as follows Priority is highest to lowest refresher local bus and scrubber When no requests are pending the arbiter defaults to providing local bus grant for fast response to local bus cycles Although the arbiter operates on a priority basis it also performs a pseudo round robin algorithm in order to prevent starving any of the requesting entities Chip Defaults Certain parameters in the Petra MCECC sector have to be configured These include DRAM size DRAM speed Control and Status register selection etc The configuration parameters are loaded into the Defaults 1 Defaults 2 and SDRAM Configuration registers on the first clock edge after reset negation Software can override this initial setting by writing to the Defaults registers It is not recommended that non test software alter the contents of the Defaults registers however The actual values loaded into the Defaults registers are determined by board level jumpers and configuration resistors http www motorola com computer literature 5 9 MCECC Functions Programming Model This section defines the programming model for the control and status registers CSRs in the MCECC sector The base address of the CSRs is hard coded to the address FFF43000 for the MCECC sector on the first mezzanine board and to FFF4310
319. ster 0 ADR SIZ Local Bus FFF40108 VMEbus XXY4 16 bits BIT 15 0 General Purpose Register 0 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose Register 1 ADR SIZ Local Bus FFF4010C VMEbus XXY6 16 bits BIT 15 is 0 NAME General Purpose Register 1 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose Register 2 ADR SIZ Local Bus FFF40110 VMEbus 8 16 bits BIT 15 SA 0 NAME General Purpose Register 2 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification http www motorola com computer literature 2 107 VMEchip2 General Purpose Register 3 ADR SIZ Local Bus FFF40114 VMEbus 16 bits BIT 15 us 0 NAME General Purpose Register 3 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is no
320. t and a clear on compare enable bit The counter is readable and writable at any time When enabled in free run mode it increments every 115 When the counter is enabled clear on compare mode it increments every lus until the counter value matches the value in the compare register When a match occurs the counter is cleared When a match occurs in either mode an interrupt is sent to the local bus interrupter and the overflow counter is incremented An interrupt to the local bus is only generated if the tick timer interrupt is enabled by the local bus interrupter The overflow counter can be cleared by writing a 1 to the overflow clear bit Tick timer 1 or 2 can be programmed to generate a pulse on the VMEbus IRQI interrupt line at the tick timer period This provides a broadcast interrupt function which allows several VME boards to receive an interrupt at the same time In certain applications this interrupt can be used to synchronize multiple processors This interrupt is not acknowledged on the VMEbus This mode is intended for specific applications and is not defined in the VMEbus specification Watchdog Timer The watchdog timer has a 4 bit counter four clock select bits an enable bit a local reset enable bit a SYSRESET enable bit a board fail enable bit counter reset bit WDTO status bit and WDTO status reset bit When enabled the counter increments at a rate determined by the clock select bits If the counter is not reset
321. t defined by the hardware specification General Purpose Register 4 ADR SIZ Local Bus FFF40118 VMEbus XXYC 16 bits BIT 15 um 0 NAME General Purpose Register 4 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification General Purpose Register 5 ADR SIZ Local Bus FFF4011C VMEbus XXYE 16 bits BIT 15 1 0 General Purpose Register 5 OPER R W RESET 0 PS This register is a general purpose register that allows a local bus master to communicate with a VMEbus master The function of this register is not defined by the hardware specification 2 108 Computer Group Literature Center Web Site 2 Functions Introduction The Memory Controller ASIC MC2 chip is one of three ASICs the MC2 chip the IP2 chip and the MCECC chip used on earlier MVME1 62 172 models whose functions are now incorporated into a single ASIC the Petra chip on the MVME1X2P4 For ease of use with programming models and documentation developed for earlier boards however the structure of this manual preserves the functional distinctions that formerly characterized those three ASICs This chapter describes the MC2 functionality of the Petra chip Summary of Major Features MC2 functions now implemented on the Petra chip include
322. t Encoding 71 570 Memory Size 0 Reserved do not use 1 512KB or 128KB 2 53 2 Note Foran MVME1X2P4 with 128KB of SRAM the software must program SZ1 SZ0 1 512KB Therefore the SRAM contents will repeat in the memory map LANC Error Status Register ADR SIZ FFF42028 8 bits BIT 31 30 29 28 27 26 25 24 NAME PRTY EXT LTO SCLR OPER R R R R R R R 0 0 0 0 0 PL 0 PL 0 PL SCLR Writing a 1 to this bit clears bits LTO EXT and PRTY Reading this bit always yields 0 LTO EXT PRTY These bits indicate the status of the last local bus error condition encountered by the LANC while performing DMA accesses to the local bus A local bus error condition is flagged by the assertion of TEA When the LANC receives TEA if the source of the error is local time out then LTO is set and EXT and PRTY are cleared If the source of the TEA is due to an error in going to the VMEbus then EXT is set and the other two status bits are http www motorola com computer literature 3 29 MC2 Functions cleared If the source of the error is DRAM parity check error then PRTY is set and the other two status bits are cleared If the source of the error is none of the above conditions then all three bits are cleared Writing a 1 to bit 24 SCLR also clears all three bits 82596CA LANC Interrupt Control Register
323. t condition and the command chaining process will not start Therefore the entry in the last command packet which is loaded into the Table Address counter should have one or more of these address bits set to a 1 to halt the command chaining process ADR SIZ FFFBCO034 4C 64 7C 32 bits each BIT 31 T 0 NAME DMA Table Address Counter OPER R W RESET OR http www motorola com computer literature 4 43 2 Functions Programming the Programmable Clock Programmable clock registers are defined in the following paragraphs Programmable Clock Interrupt Control Register ADR SIZ FFFBC080 8 bits BIT 7 6 5 4 3 2 1 0 0 INT IL2 IL1 ILO OPER R R W R R W C R W R W R W RESET OR OR OR OR OR OR OR OR 2 0 These three bits select the interrupt level for the programmable clock interrupt Level 0 does not generate an interrupt ICLR Writing a logic 1 to this bit clears the INT status bit This bit always reads as 0 When is set the programmable clock interrupt is enabled When IEN is cleared the interrupt is disabled INT When this bit is high an interrupt is being generated for the programmable clock at the level programmed in IL2 ILO IRE This bit controls which action of the programmable clock output causes interrupts Programmable Clock Action IRE That Causes Interrupts 0 Rising edge 1 Falling edge
324. t is low the DMAC executes the next command in the list 2 56 Computer Group Literature Center Web Site LCSR Programming Model DMAC Control Register 2 bits 8 15 ADR SIZ FFF40034 8 bits 7 USED of 32 BIT 15 14 13 12 11 10 9 8 NAME INTE SNP VINC LINC TVME D16 OPER R W R W R W R W R W R W RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS This portion of the control register is loaded by the processor or by the DMAC when it loads the command word from the command packet Because this register is loaded from the command packet in command chaining mode the descriptions here also apply to the control word in the command packet D16 TVME LINC VINC When this bit is high the DMAC executes D16 cycles on the VMEbus When this bit is low the DMAC executes D32 D64 cycles on the VMEbus This bit defines the direction in which the DMAC transfers data When this bit is high data is transferred to the VMEbus When it is low data is transferred to the local bus When this bit is high the local bus address counter is incremented during DMA transfers When this bit is low the counter is not incremented This bit should normally be set high In special situations such as transferring data to or from a FIFO it may be desirable to not increment the counter When this bit is high the VMEbus address counter is incremented during DMA transfers When this bit is low the counter is not in
325. t software write to this register Computer Group Literature Center Web Site Programming Model RSIZ2 RSIZO0 Bits RSIZ2 RSIZO determine the size of the DRAM array that is assumed by the MCECC They control the size as follows RSIZ2 RSIZ1 RSIZO DRAM Array Size 0 0 0 4MB 0 0 1 8 0 1 0 16 0 1 1 32 1 0 0 64MB 1 0 1 128MB 1 1 0 Reserved 1 1 1 Reserved The states of RSIZ2 0 after reset power up soft or local match those of the RSIZ2 0 bits from the reset serial bit stream SELI1 SELIO The SELI1 SELIO control bits determine the base address at which the control and status registers respond as shown below SELI1 SELIO Register Base Address 0 1 43000 1 0 FFF43100 SELII and SELIO are initialized by hardware after a power up soft or local reset Their initialized state is determined by board level configuration resistors FSTRD FSTRD control bit determines the speed at which SDRAM reads occur When itis 1 SDRAM reads happen at full speed When it is 0 SDRAM reads are slowed by one clock unless they are already slowed by NCEBEN http www motorola com computer literature 5 31 Functions being set The state of FSTRD after a reset power up soft or local is determined by board level configuration resistors RWB6 Read Write Bit 6 is a general purpose read write bit RWB7 Read Wri
326. tarting Address Register 1 OPER R W RESET 0 PS This register is the starting address register for the first VMEbus to local bus map decoder 2 28 Computer Group Literature Center Web Site LCSR Programming Model VMEbus Slave Ending Address Register 2 ADR SIZ FFF40004 16 bits of 32 BIT 31 16 Ending Address Register 2 OPER R W RESET 0 PS This register is the ending address register for the second VMEbus to local bus map decoder VMEbus Slave Starting Address Register 2 ADR SIZ FFF40004 16 bits of 32 BIT 15 0 Starting Address Register 2 OPER R W RESET 0 PS This register is the starting address register for the second VMEbus to local bus map decoder VMEbus Slave Address Translation Address Offset Register 1 ADR SIZ FFF40008 16 bits of 32 BIT 31 re 16 NAME Address Translation Address Offset Register 1 OPER R W RESET 0 PS This register is the address translation address register for the first VMEbus to local bus map decoder It should be programmed to the local bus starting address When the adder is engaged this register is the offset value http www motorola com computer literature 2 29 VMEchip2 VMEbus Slave Address Translation Select Register 1 ADR SIZ FFF40008 16 bits of 32 BIT 15 2 0 Address Translation Select Register 1 OPER R W RESET 0 P
327. te Bit 7 is a general purpose read write bit Defaults Register 2 ADR SIZ 1st FFF43078 2nd FFF43178 8 bits BIT 31 30 29 28 27 26 25 24 0 0 0 0 0 RESST2 RESSTI RESSTO OPER R W R W R W R W R W R W R W RESET 0 PLS 0 PLS 0 PLS VPLS VPLS VPLS 5 It is not recommended that non test software write to this register RESST2 RESSTO These general purpose read write bits are initialized by a power up soft or local reset to match the RESST2 RESSTO bits from the reset serial bit stream 5 32 Computer Group Literature Center Web Site Programming Model SDRAM Configuration Register ADR SIZ 1st FFF4307c 2nd FFF4317c 8 bits BIT 31 30 29 28 27 26 25 24 0 0 0 0 0 SDCFG2 SDCFGI SDCGFO OPER R R R R R R R R RESET 0 PLS 0 PLS 0 PLS VPLS VPLS V PLS V PLS V PLS SDCFG2 SDCFG0 Define the physical SDRAM memory population on the printed circuit board SDCFG2 SDCFG1 SDCFG0 DRAM Array Size 0 0 0 SDRAM device is 64MBit x 16 data with one bank composed of 3 devices 0 0 1 SDRAM device is 64MBit x 8 data with one bank composed of 5 devices 0 1 0 SDRAM device is 64MBit x 8 data with two banks composed of 5 devices each 0 1 1 SDRAM device is 64MBit x 8 data with four banks composed of 5 devices each 1 0 0 SDRAM device is 128MBit x 8 data with one bank composed of 5 d
328. tents ADR SIZ BIT 23 FFF4202C 8 bits 22 17 16 15 V14 V9 V8 OPER R R RESET Application Specific Caution V10 V8 V10 V8 general purpose inputs derived from three configuration bits in the Petra ASIC The configuration bits for V10 V8 are bits GPIO GPI1 and GPI2 respectively in the MC2 General Purpose Inputs register Refer to the notes following the MVMEIX2P4 Local Bus Memory Map in Chapter 1 The input for V11 is derived from configuration bit GPI3 in the MC2 General Purpose Inputs register in the Petra ASIC GPI3 is controlled by board configuration switch S4 segment 5 Setting bit GPI3 to 0 will cause the reset code to execute from EPROM instead of Flash as described in the MVMEIXO2PA Installation and Use manual http www motorola com computer literature 3 33 MC2 Functions V15 V12 15 12 are four additional general purpose inputs derived from configuration bits in the Petra ASIC refer also to the description for V10 V8 The configuration bits for V15 V12 are bits GPI4 GPI5 GPI6 and GPI7 respectively in the MC2 General Purpose Inputs register MVME1X2P4 Version Register The contents of a PAL in conjunction with board level configuration resistors and an array of software switches produce the bit settings of the General Purpose Inputs register Version register and DRAM SRAM Options register when the MC2 sector is r
329. ter Group Literature Center Web Site Programming Model 32 bit Prescaler Count Register The prescaler register is used to clock timing functions in the MC2 sector The lower 8 bits of the prescaler is programmed to generate an output with a one microsecond period Refer to the section on the LSB Prescaler Count register under Programming the Tick Timers in this chapter The upper 24 bits are used to clock the local bus access timer and watchdog timer To facilitate testing the upper 24 bits can be written Writes to this register must be 32 bits ADR SIZ FFF4204C 32 bits BIT Blix ak 7 0 NAME MSB LSB OPER R W R RESET LSB7 0 The least significant bits of the 32 bit prescaler These bits are read only They are duplicated in the memory map in the Petra MC2 sector at FFF42014 MSB31 8 The most significant bits of the prescaler Note that if the board is built in a VMEbus interface configuration the 32 bit Prescaler Count register is located at FFF40064 in addition to FFF4204C This means that this register is located at the same address FFF40064 on an MVME1X2P4 with the VMEchip2 as well as an MVME1X2P4 without the VMEchip2 This feature is provided for those applications which require a Prescaler Count register to run on all MVME1X2P4 versions http www motorola com computer literature 3 47 MC2 Functions 3 48 Computer Group Literature Center Web Site
330. that you type just as it appears it is also used for commands options and arguments to commands and names of programs directories and files italic is used for names of variables to which you assign values Italic is also used for comments in screen displays and examples and to introduce new terms courier is used for system output for example screen displays reports examples and system prompts lt Enter gt lt Return gt or lt CR gt represent the carriage return or Enter key CTRL represents the Control key Execute control characters by pressing the Ctrl key and the letter simultaneously for example Ctrl d this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes are defined as follows A byte is eight bits numbered 0 through 7 with bit 0 being the least significant A word is 16 bits numbered 0 through 15 with bit 0 being the least significant A longword is 32 bits numbered 0 through 31 with bit 0 being the least significant The terms control bit status bit true and false are used extensively in this document The term control bit is used to describe a bit in a registe
331. the VMEchip2 wants to drive the SYSFAIL signal line The six General Purpose registers can be read and written from both the local bus and the VMEbus These registers are provided to allow local bus masters to communicate with VMEbus masters The function of these registers is not defined by this specification The GCSR supports read modify write cycles such as TAS The GCSR allows a VMEbus master to reset the local bus This feature is very dangerous and should be used with caution Caution The local reset feature is a partial system reset not a complete system reset such as powerup reset or SYSRESET When the local bus reset signal is asserted a local bus cycle may be aborted The VMEchip2 is connected to both the local bus and the VMEbus and if the aborted cycle is bound for the VMEbus erratic operation may result Communications between the local processor and a VMEbus master should use interrupts or mailbox locations reset should not be used in normal communications Reset should be used only when the local processor is halted or the local bus is hung and reset is the last resort http www motorola com computer literature 2 101 VMEchip2 Programming the GCSR A complete description of the GCSR appears in the following tables Each register definition includes a table with five lines 1 The base address of the register and the number of bits defined in the table The bits defined by this table The name of the
332. the first map decoder does not respond to VMEbus A32 access cycles USR When this bit is high the first map decoder responds to VMEbus user non privileged access cycles When this bit is low the first map decoder does not respond to VMEbus user access cycles SUP When this bit is high the first map decoder responds to VMEbus supervisory access cycles When this bit is low the first map decoder does not respond to VMEbus supervisory access cycles Programming the Local Bus to VMEbus Map Decoders This section includes programming information on the local bus to VMEbus map decoders and the GCSR base address registers The local bus to VMEbus interface allows onboard local bus masters access to off board VMEbus resources The address of the VMEbus resources as viewed from the local bus is controlled by the local bus slave map decoders which are part of the local bus to VMEbus interface Four of the six local bus to VMEbus map decoders are programmable while the two I O map decoders are fixed The first I O map decoder provides an A16 D16 or A16 D32 space at SFFFF0000 to FFFFFFFF which is the VMEbus short I O space The second I O map decoder provides an A24 D 16 space at F000000 to FOFFFFFF an A32 D16 space at F1000000 to FF7FFFFF A programmable segment may vary in size from 64KB to 4GB in increments of 64KB Address translation for the fourth segment is provided by the address translation registers which allow the upp
333. tomatically invoked using the command chaining mode In the command chaining mode a singly linked list of commands is built in local memory and the table address register in the DMAC is programmed with the starting address of the list of commands DMAC Control Register 1 is programmed and the DMAC is enabled The DMAC executes commands from the list until all commands are executed or until an error is detected When the DMAC stops the status bits are set in the DMAC status register and an interrupt is sent to the local bus master if the DMAC interrupts are enabled Additionally when the DMAC finishes processing a command in the list and interrupts are enabled for that command the DMAC sends an interrupt to the local bus master if its interrupts are enabled Note that when the DMA register context is updated for the next command packet a DMA function is used The state of the snoop control signals for this DMA function as well as the state of the snoop control signals for all other DMA cycle types depends on the status of configuration bits SCO 5 in the Petra ASIC Bits SCI and SCO are under the control of configuration switch S5 pins 1 and 2 Referto the Hardware Preparation section of your MVMEI X2P2 Installation and Use manual for details on S5 http www motorola com computer literature 4 31 IP2 Functions Each DMAC s control is divided into two registers The first register is only accessible by the processor
334. tryPack connector pairs 1 indicates the board is an MVMEIX2P2 model front panel I O and 2 IndustryPack connector pairs Reserved for internal use only SCSI Interrupt Control Register ADR SIZ FFF4202C 8 bits BIT 6 5 4 3 2 1 0 NAME INT IEN IL2 ILI ILO OPER R R W R R W R W R W RESET 0 R 0 IL2 ILO Interrupt Level These three bits select the interrupt level for the SCSI processor Level 0 does not generate an interrupt http www motorola com computer literature 3 35 MC2 Functions Interrupt Enable When this bit is set high the interrupt is enabled The interrupt is disabled when this bit is low INT Interrupt Status This status bit reflects the state of the INT pin from the SCSI processor qualified by the bit When this bit is high a SCSI processor interrupt is being generated at the level programmed in IL2 ILO This status bit does not need to be cleared because it is level sensitive Tick Timer 3 and 4 Compare and Counter Registers Tick timers 3 and 4 are defined here because they maintain this relative position in the memory map Refer to the sections on tick timers and 2 in this chapter for an overall description of the tick timers Tick Timer 3 Compare Register ADR SIZ FFF42030 32 bits BIT 31 T 0 NAME Tick Timer 3 Compare Register OPER R W RESET Tick Timer 3 Co
335. unter ADR SIZ FFF42034 32 bits BIT 31 Led 0 NAME Tick Timer 3 Counter OPER R W RESET X 3 36 Computer Group Literature Center Web Site Programming Model Tick Timer 4 Compare Register ADR SIZ FFF42038 32 bits BIT 31 ee 0 NAME Tick Timer 4 Compare Register OPER R W RESET OP Tick Timer 4 Counter ADR SIZ FFF4203C 32 bits BIT 31 0 Tick Timer 4 Counter OPER R W RESET X Bus Clock Register The Bus Clock register should be programmed with the hexadecimal value of the operating clock frequency in MHz i e 21 for 33MHz The MC2 sector uses the value programmed in this register to control the refresh timer so that the DRAMs are refreshed every 15 6 microseconds After power up this register is initialized to 10 for 16MHz ADR SIZ FFF42040 8 bits BIT 31 30 29 28 27 26 25 24 NAME 5 BCK4 BCK3 BCK2 BCKO R W R W R W RESET OP OP OP 1P OP OP OP OP 5 0 The refresh rate is defined by the following equation Refresh Rate BCK BUS CLOCK x 16 http www motorola com computer literature 3 37 MC2 Functions where BCK is the value programmed in the Bus Clock register and BUS CLOCK is the MC68xx0x0 bus clock frequency EPROM Access Time Control Register The 2 4 is populated with 150ns EPROM memory device Due to th
336. up Literature Center Web Site Example Tick Timer Periodic Interrupt Step Action and Reference 2 Confirm that the Tick Timer 1 interrupt occurred by reading the status of bit 24 in the Interrupter Status register at FFF40068 A high indicates an interrupt present 3 Clear the Tick Timer 1 interrupt by writing a 1 to bit 24 of the Interrupt Clear register at FFF40074 4 Increment a software counter to keep track of the number of interrupts if desired Output a character or some other action such as toggling the FAIL LED on an appropriate count such as 1000 5 Return from exception http www motorola com computer literature B 3 Using Interrupts the MVME1X2P4 B 4 Computer Group Literature Center Web Site Related Documentation Motorola Computer Group Documents The Motorola publications listed below are applicable to the MVME1X2P4 You can obtain paper or electronic copies of Motorola Computer Group publications by Contacting your local Motorola sales office Visiting MCG s World Wide Web literature site http www motorola com computer literature Table C 1 Motorola Computer Group Documents Document Title Publication Number MVME162P4 VME Embedded Controller Installation and Use 162 MVME172P4 VME Embedded Controller Installation and Use V172PFXA IH MVME162Bug Diagnostics User s Manual V162DIAA UM MVME172Bug Diag
337. urred during a command table access otherwise the error occurred during a data access http www motorola com computer literature 1 45 Board Description and Memory Maps DMAC Offboard Error Description MPU Notification Status Comments DMAC LTO Error Description MPU Notification Status Comments Error encountered while the Local Bus side of the DMAC was attempting to go to the VMEbus DMAC interrupt when enabled The DLOB bit is set in the DMAC Status register Address FFF40048 bit 4 This is normally caused by a programming error The Local Bus address of the DMAC should not be programmed with a Local Bus address that maps to the VMEbus If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access A Local Bus timeout LTO occurred while the DMAC was Local Bus master DMAC interrupt when enabled The DLTO bit is set in the DMAC Status register Address FFF40048 bit 3 This indicates the DMAC attempted to access a Local Bus address at which there was no resource If the TBL bit is set address FFF40048 bit 2 the error occurred during a command table access otherwise the error occurred during a data access 1 46 Computer Group Literature Center Web Site Software Support Considerations DMAC TEA Cause Unidentified Description MPU Notification Status Comments
338. us 53C710 Interrupt 53C710 DMA Status register 53C710 DMA Interrupt Status register Petra MC2 Sector SCSI Error Status register Address FFF4202C 53C710 interrupt enables are controlled in the 53C710 and in the Petra MC2 sector s SCSI Interrupt Control register FFF4202F http www motorola com computer literature 1 49 Board Description and Memory Maps SCSI LTO Error Description Local Bus Timeout occurred while the 53C710 was Local Bus master MPU Notification 53C710 Interrupt Status 53C710 DMA Status register 53C710 DMA Interrupt Status register Petra MC2 Sector SCSI Error Status register Address FFF4202C Comments 53C710 interrupt enables are controlled in the 53C710 and in the Petra MC2 sector s SCSI Interrupt Control register SFFF4202F Proper Use of Bus Timers Asan example of how to use the bus timers consider the sequence of events that occur when the MPU on one MVME1X2P4 accesses the local bus memory on another MVME1X2P4 using the VMEbus This scenario would involve three bus timers The Local Bus timer The VMEbus Access timer The Global VMEbus timer The local bus timer measures the time an access to an onboard resource takes The VMEbus timer measures the time from when the VMEbus request has been initiated to when a VMEbus grant has been obtained The global bus timer measures the time from when a VMEbus cycle begins to when it completes These timers are nor
339. us cycle does not complete within the programmed time VMEbus bound cycles are not timed by the local bus timer As long as the system is configured properly this should only happen if software accesses a nonexistent location within the onboard address range http www motorola com computer literature 1 41 Board Description and Memory Maps VMEbus Access Time Out A VMEbus Access time out occurs whenever a VMEbus bound transfer does not receive a VMEbus bus grant within the programmed time This is usually caused by another bus master holding the bus for an excessive period of time VMEbus A VMEbus BERR occurs when BERR signal line is asserted on the VMEbus while a local bus master is accessing the VMEbus VMEbus BERR should occur only if one of the following occurs Q An initialization routine samples to see if a device is present on the VMEbus and if it is not software accesses a nonexistent device within the VMEbus range Incorrect configuration information causes VMEchip2 to incorrectly access a device on the VMEbus such as driving LWORD low to a 16 bit board A hardware error occurs the VMEbus A VMEbus slave reports an access error such as parity error Local DRAM Parity Error Note Although 2 series contains synchronous DRAM SDRAM rather than parity DRAM it can be made to emulate parity DRAM for compatibility with the MC2 programming model
340. us following a read cycle The state of BTD affects IP bus cycles which are a result of the DMA function because they are the only cycles which can occur back to back When BTD is set to a 0 the IndustryPack interface will start the next cycle as soon as possible Note The default BTD setting is to insert the additional one clock period delay between read cycles WIDTHI WIDTHO The IP2 sector assumes the memory space data bus width of each of IP a b IP c and IP d to be the value decoded from its control bits WIDTH1 and WIDTHO Note that the width bits control the assumed memory width for the load stored programmed I O data path There is a similar set of bits for the DMA logic memory width control The following table shows widths inferred by these bits When a double size IndustryPack is used in ab then IP_a should be programmed for 32 bit width and the WIDTH and MEN control bits in the IP_b General Control register should be cleared When a double size IndustryPack is used at cd then IP_c should both be programmed for 32 bit width and the WIDTH and MEN control bits in the IP_d General Control register should be cleared WIDTHI WIDTHO Memory Space Data Width 0 0 32 bits 0 1 8 bits 1 0 16 bits 1 1 Reserved Note When programming b_WIDTH1 b_WIDTHO for either 8 bits or 16 bits WIDTH1 a_WIDTHO must be programmed for width of 8 bits or 16 bits This applies whether or not a_MEN is set Fo
341. uter literature 5 5 MCECC Functions Double Bit Error Cycle Type Burst Read or Non Burst Read You cannot correct the data that is driven to the local MC680x0 bus 1 3 4 Leave the error in DRAM Note that the error is not corrected DRAM during the next scrub of that address Terminate the cycle with Bus Error assert TEA to the local bus if so enabled Log the error if not already logged Notify the local MPU via interrupt if so enabled Triple or Greater Bit Error Cycle Type Burst Read or Non Burst Read Some of these errors are detected correctly and are treated the same as a double bit error The rest could show up as no error or single bit error both of which are incorrect Cycle Type Burst Write Because all of the bits are written during a burst write no checking is done Single Bit Error Cycle Type Non Burst Write 1 Correct the data read from the DRAM merge with the write data and write the correct merged data to the DRAM Terminate the cycle normally Assert to the local bus Log the error if not already logged Notify the local MPU via interrupt if so enabled Double Bit Error Cycle Type Non Burst Write 1 Do not perform the write portion of the cycle This causes the location to continue to indicate a non correctable error when accessed Terminate the cycle normally Assert to the local bus Log the error i
342. vice size is less than the allocated memory map size for some entries the device contents repeat for those entries If bit MC2_GPI3 is set bit 20 in the MC2 General Purpose Inputs register or pin 5 on switch S4 the Flash device is accessed If bit 2 is not set the EPROM 15 accessed The Flash and EPROM are sized by the Petra chip from an 8 bit private bus to the 32 bit MPU local bus Because the device size is less than the allocated memory map size for some entries the device contents repeat for those entries If bit MC2_GPI3 is set bit 20 in the MC2 General Purpose Inputs register or pin 5 on switch S4 the EPROM is accessed If bit MC2_GPI3 is not set the Flash device is accessed These areas are not decoded unless one of the programmable decoders is initialized to decode this space If they are not decoded an access to this address range will generate a local bus time out The local bus timer must be enabled http www motorola com computer literature 1 13 Board Description and Memory Maps Table 1 4 below describes the Local I O Devices portion of the local bus main memory map for the MVME1X2P4 Table 1 4 MVME1X2P4 Local I O Devices Memory Map Address Range Device H Size Note s FFF00000 FFF3FFFF Reserved m 256KB 4 FFF40000 FFF400FF VMEchip2 LCSR D32 256B 1 3 FFF40100 FFF401F
343. when done mode When this bit is low the requester operates in release on request mode When this bit is high the requester operates in fair mode When this bit is low the requester does not operate in fair mode In fair mode the requester waits until the request signal line for the selected level is inactive before requesting the VMEbus When this bit is high the VMEchip2 requests the VMEbus and does not release it When this bit is low the VMEchip2 releases the VMEbus according to the release mode programmed in the LVRWD bit When the VMEbus has been acquired the DHB bit is set When this bit is high the VMEbus has been acquired in response to the DWB bit being set When the DWB bit is cleared this bit is cleared When this bit is high the VMEbus arbiter operates in round robin mode When this bit is low the arbiter operates in priority mode DMAC Control Register 1 bits 0 7 ADR SIZ FFF40030 8 bits of 32 BIT 7 6 5 4 3 2 1 0 NAME DEN DTBL DFAIR DRELM DREQL OPER 5 5 R W R W R W R W RESET OPS OPS OPS OPS OPS OPS This control register is loaded by the processor it is not modified when the DMAC loads new values from the command packet DREQL These bits define the VMEbus request level for the DMAC requester The request level can only change while the VMEchip2 is bus master The VMEchip2 http www motorola com computer literature 2 55 VMEchip2 a
344. work Coprocessor Data Sheet 290218 82596CA Local Area Network Coprocessor User s Manual 296853 28 0088 Flash Memory Data Sheet 209435 28 0168 Flash Memory Data Sheet 209435 Intel Corporation Web http developer intel com design M48T58 B Timekeeper 8Kx8 Zeropower RAM data sheet M48T58 SGS Thomson Microelectronics Group North amp South American Marketing Headquarters 1000 East Bell Road Phoenix Arizona 85022 Telephone 602 867 6100 Web http www st com stonline books SYM 53C710 was NCR 53C710 SCSI I O Processor Data Manual NCR53C710DM SYM 53C710 was NCR 53C710 SCSI I O Processor Programmer s Guide NCR53C710PG Symbios Logic Inc 1731 Technology Drive Suite 600 San Jose CA 95110 NCR Managed Services Center Telephone 1 800 262 7782 Web http www lsilogic com products symbios C 2 Computer Group Literature Center Web Site Related Specifications Table C 2 Manufacturers Documents Continued Zilog Inc 210 Hacienda Avenue Campbell CA 95008 6609 Web http www zilog com products Publication Document Title and Source ublicatio Number 785230 Serial Communications Controller Product Brief Z85230pb pdf Related Specifications For additional information refer to the following table for related specifications As a further aid sources for the listed documents are also provided Please note that in many cases the information is prel
345. ycle This allows the arbiter to arbitrate any pending requests and grant the bus to the next requester at the same time that the active master completes its cycle 2 8 Computer Group Literature Center Web Site Functional Blocks VMEbus to Local Bus Interface The VMEbus to local bus interface allows an off board VMEbus master access to onboard resources The VMEbus to local bus interface includes the VMEbus slave write post buffer and local bus master Adhering to the IEEE 1014 87 VMEbus standard the s ave can withstand address only cycles as well as address pipelining and respond to unaligned transfers Using programmable map decoders it can be configured to provide the following VMEbus capabilities Addressing capabilities A24 A32 Data transfer capabilities DOS EO D16 D32 D8 BLT D16 BLT D32 BLT D64 BLT BLT block transfer The slave can be programmed to perform write posting operations When in this mode the chip latches incoming data and addressing information into a staging FIFO and then acknowledges the VMEbus write transfer by asserting DTACK The chip then requests control of the local bus and independently accesses the local resource after it has been granted the local bus The write posting pipeline is two deep in non block transfer mode and 16 deep in block transfer mode To significantly improve the access time of the slave when it responds to a VMEbus block read cycle the VMEchip2 contains a
346. zed to a 1 the IPIC reset mode is enabled The IPIC reset mode works as follows Setting RES to a 1 asserts the IPRESET signal It remains set for at least 1 millisecond and then clears When RES is set to 0 the IP2 reset mode is enabled IPI RES is initialized when Petra is reset The IP2 method of IP reset is used on MVME1X2P4 series boards 4 30 Computer Group Literature Center Web Site Programming Model Programming the DMA Controllers The Petra IP2 sector implements four DMA channels They can operate in the standard or addressed mode sDMA transfers must accommodate the T O port width If the port width is 16 bits then the byte count must be even if the width is 32 bits then the byte count must be a multiple of four bytes The IP address counter must be initialized to zero before an SDMA transfer is enabled No other restrictions are placed on DMA operations Each DMAC has two modes of operation command chaining and direct In the direct mode the local bus address the IndustryPack address the byte count and the control register of a DMAC are programmed and the DMAC is enabled The DMAC transfers data as programmed until the byte count is zero DMAEND is detected true as an input or an error is detected When the DMAC stops the status bits in the DMAC status register are set and an interrupt is sent to the local bus master if the DMACs interrupts are enabled Multiple DMAC commands can be au

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