Home

User`s Manual

1. logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design User s Manual Xylon July 20 2015 Version v1 0 0 Designed by XYLON For instructions on how to find your Ethernet MAC or host ID please visit http www logicbricks com Documentation Article aspx article D KBA 01186 MOJXKD Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS SEH Evaloatien reo Change Password S Xylon logicBRICKS e D at gf Request Eval IP Core py Graphics for Xilinx Zynq 7000 WH K IP Core Activation Ka f Click to get reference designs for Xilinx ZC 702 Evaluation Board NS A Create Case Click to get the IP license key Subscribe to Newsletter Mate Status Downloads logiC VC ML EVAL 1M Not Activated Obtain evaluation license key logiWVIN EVAL 1M Not Activated Obtain evaluation license key logiBITBLT EVAL 1M Not Activated Obtain evaluation license key Figure 27 Step 2 Selecting logicBRICKS IP Core for Licensing Home About us Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS a Evaluation Late Change Password Xylon logicBRICKS Request Eval IP Core Graphics for Xilinx Zynq 7000 IP Core Activation lt J Click to get reference designs for Xilinx ZC702 Evaluation Board IS Create Case Subscribe to Newsletter Name Status Downloads logiC VC ML EVAL 1M Acti
2. Evaluation logicBRICKS IP XACT cores zip archives cere Evaluation logicBRICKS IP XACT extracted IP cores IP cores User s Manuals are stored in doc subfolders a Sw_services fat_fs Open source FAT file system fmc_iic_sw Avnet FMC card 12C library fmc_imageon_sw Avnet FMC Imageon sensor library platform Xylon board hardware abstraction library x12 Xylon graphical library xyl_oslib Xylon OS abstraction library for Xilinx Xilkernel embedded kernel use in standalone non OS Eege WM Hardware description file used by platform _ description file used by platform enger SE Ee Location of nea platform files software o o e Application source files or libs Libraries EMBV_drv EMBVPlatform _lib o er of ay Bana applications emt Navigation page through the software files and instructions for building binaries Copyright Xylon d o o 2015 All Rights Reserved Page 32 of 40 SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 it logiREF SDSoC FACE EVK um 9 9 GETTING LOGICBRICKS EVALUATION LICENSES Please note that the logiREF SDSoC FACE EVK reference design installation provides you with everything needed to run the provided demo applications or to use change the provided software source code However to implement any changes to the design files such as to remove add or reconfigure some of the provided IP cores you have to obtain evaluation IP li
3. Details i IP available for purchase from Alliance Partner Name Multilayer Video Controller Interfaces AXI4 Description The logiCVC ML Compact Multilayer Video Controller is a graphics video display controller optimized for Xilinx Zyng 7000 All Programmable AP SoC and FPGA devices logiCVC ML rir provides all the necessary control signals to interface directly with LCD and other flat panel displays A wide veriaty of LCD doisplay types is supported Its compact size low slice cor configuration by VHDL code parameterization Its functions indude refreshing the display image by reading the video memory and converting the read data into a data stream accap for the display Multilayer support provides alpha blending transparency hardware cursors and fast scrolling by using low CPU processing power By means of an external video digi composite video devices and CRT displays Additionally Digital Visual Interface DVI compliant displays can be controlled by using the appropriate devices http www xilinx com products intellectual property JlogiCVC ML htm Figure 11 logicBRICKS IP Cores in the Vivado IP Catalog Some of the latest logicBRICKS IP cores are provided in the Vivado compatible version only Please visit our web site or contact Xylon to learn more about the tools compatibility of the specific logicBRICKS IP core Copyright Xylon d o o 2015 All Rights Reserved Page 18 of 40 logiREF SDSOC FACE EVK mm SDSoC FD
4. SES Obtain Evaluation License s een Request Eval IP Core AS Graphics for Xilinx Zynq 7000 WAIT E IP Core Activation SS Click to get reference designs for Xilinx ZC702 Evaluation Board ay Create Case A Subscribe to Newsletter Downloads MAC Address You will be able to use evaluation license on one Omens development workstation Please enter your G workstation MAC address for MS Windows and Linux 00 00 00 00 00 00 platforms or Sun HostiD for Solaris platforms My logicBRICKS SE d a Obtain Evaluation License Change Password b gt E Xylon logicBRICKS SEN i Graphics for Xilinx Zynq 7000 Sy Click to get reference designs for Xilinx ZC702 Evaluation Board E Request Eval IP Core IP Core Activation Create Case Subscribe to Newsletter Downloads License key will be created and send to your e mail address Figure 31 Step 3 Confirmation Message Step 4 You will get an e mail with the license key file and full instructions for setting up the license key and downloading the logicBRICKS IP core Please follow the provided instructions From Xylon License Key Generator To GE Subject Xylon Core License Delivery 1D 03512090617423596 Sent 6 9 2012 17 47 Attachments 035120906 17423596_ip_xap_349logicveml_eval_flexim lic 568 B RICKS THIS IS AN AUTOMATICALLY GENERATED EMAIL Please do not reply to this message gt DI Designed by XYLON All req
5. Xylon d o o 2015 All Rights Reserved Page 38 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 11 REFERENCES Table 2 List of References Description REF 1 Xylon logiREF FACE TRACK EVK logiREF FACE TRACK EVK_v1_01_a pdf REF 2 Xilinx UG1146 ug1146 sdsoc_platforms_and_libraries pdf REF 3 Xilinx UG1027 ug1027 intro_to_sdsoc pdf Copyright Xylon d o o 2015 All Rights Reserved Page 39 of 40 F logiREF SDSoC FACE EVK RICKS SDSoC FDT Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 12 REVISION HISTORY Version Dee Author Approved by Note July 20 2015 M Polovic G Galic Initial ee es Copyright Xylon d o o 2015 All Rights Reserved Page 40 of 40
6. _ BOOT BIN _ cand3 fdp _ cand3 wim a facedet cfg _ facef bdf head cfg _ Ip22 bdf _ Ip23 bdf _ Ip32 bdf _ Ip34 bdf _ Ip38 bdf _ Ip42 bdf _ Ip44 bdF _ Ip46 bd _ p8i bdf _ p82 bdF _ Ip84 bdf _ Ip92 bd _ Ip93 bdF _ Ip312 bof _ pup bd _ pup new bdf Figure 7 The Contents of Properly Programmed SD Card Set up your MicroZed Embedded Vision Kit as follows Plug the programmed SD card into the micro SD card connector J6 on the MicroZed board Select the MicroZed configuration mode by setting up JP1 JP3 jumpers as shown on Figure 8 The presented setup selects the SD card as the boot device Plug the MicroZed board into the Carrier Card board as shown on Figure 9 Attach the On Semiconductor PYTHON 1300 camera module to the MicroZed Carrier Card as shown on Figure 10 Connect the Full HD 1920x1080 PC monitor and the Carrier Card HDMI OUT CONNS by the HDMI video cable connect the 5VDC power supply to the Carrier Card Copyright Xylon d o o 2015 All Rights Reserved Page 16 of 40 E logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 Figure 8 The MicroZed Board Jumpers Settings Figure 9 The MicroZed Board Plugged Inthe Figure 10 The PYTHON 1300 Camera Module Carrier Card Plugged In the Carrier Card 6 2 Running the Precompiled Demo from the SD Card Image To quickly start the pr
7. a free cross platform API for full function 2D and 3D graphics on embedded systems Including consoles phones appliances and vehicles Product is based on a published Khronos specification and is expected to pass the Khronos Conformance Testing Process Current conformance status can be found at www khronos org conformance Figure 14 Screenshots from Some Demos Provided with the Reference Designs logiREF ZGPU ZED logiREF ZGPU ZC702 and logiREF ZGPU ZC706 Copyright Xylon d o o 2015 All Rights Reserved Page 25 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 8 GET AND INSTALL THE REFERENCE DESIGN Xylon offers several logicBRICKS reference designs for different hardware platforms Short descriptions of all Xylon logicBRICKS reference designs can be found at htto www logicbricks com logicBRICKS Reference logicBRICKS Design aspx A quick access to specific reference design is also possible through the main downloads navigation page http Awww logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Navigation Page aspx Only registered logicBRICKS users can download logicBRICKS reference designs Unregistered users will be re directed to the User Login page The download link is automatically sent by an e mail which means that the registration process requires access to the e mail account Xylon ref
8. v1 0 0 5 2 Using and configuring logiFDT IP core In the provided software demo application the C function fdtu_match_template_hw fdt_util cpp serves for the communication with the face tracking accelerator and as an instruction to the SDSoC compiler to instantiate the logiFDT IP core into the provided evk_fdt platform The logiFDT IP core is used by the face tracking engine and user does not need to change anything related to the accelerator call The logiFDT IP core is packaged as a C callable IP for the SDSoC development environment It is warped in Xilinx Vivado compatible IP XACT format and includes additional description files and caller function prototype compiled by the sdslib tool REF 2 The associated C callable IP project is called logifdt_1ib and it is an imported makefile project in the SDSoC GUI User can configure the logiFDT IP core s parameters which are described in the logiFDT IP core s users manual by editing the fdtu params xml file Each logiFDIT IP core generic parameter has an assigned default value from the defined range of valid parameter values If some generic parameter is not listed in the fdtu params xml a default generic parameter s value is assumed Use a clean build of the library project in order to apply generic parameters 5 3 Terminate SDSoC exported unused ACP port The axi_acp AXI Interconnect block in the Xilinx Vivado Block Design Figure 6 contains one unconnected Slave AXI port SOO
9. LICENSE AGREEMENT AGREEMENT BY CLICKING THE ACCEPT OR AGREE BUTTON OR OTHERWISE ACCESSING DOWNLOADING INSTALLING OR USING THE LICENSED MATERIALS YOU AGREE ON BEHALF OF LICENSEE TO BE BOUND BY THIS AGREEMENT LICENSEE OR YOU MEANS THE CORPORATION OR OTHER LEGAL ENTITY TO WHICH XYLON don A CROATIAN CORPORATION WITH AN OFFICE AT FALLEROVO SETALISTE 22 10000 ZAGREB REPUBLIC OF CROATIA XYLON HAS ISSUED THE LICENSE DESCRIBED HEREIN IF YOU DO NOT AGREE TO ALL OF THE TERMS AND CONDITIONS OF THIS AGREEMENT DO NOT CLICK THE ACCEPT OR AGREE BUTTON AND DO NOT ACCESS DOWNLOAD INSTALL OR USE THE LICENSED MATERIALS AS USED HEREIN THE EFFECTIVE DATE MEANS THE DATE ON WHICH LICENSEE CLICKS THE ACCEPT OR AGREE BUTTON IDENTIFIED ABOVE PURCHASES OR OTHERWISE ACCESSES DOWNLOADS INSTALLS OR USES THE LICENSED MATERIALS WHICHEVER OCCURS FIRST 1 Definitions Licensed Materials means the Xylon design files also referred to as a core and documentation that is made available to you _ snibiect to the terms of this XEST A 2 Figure 20 Installation Process Step 1 8 Xylon logiREF ZGPU ZED_120919 RK Sao Designed by XYLON Select the installation path D Program Files ylon ZGPU ZED_120919 E Browse Previous even _ uit Figure 22 Installation Process Step 3 H
10. Marketing part number for more details visit www microzed org Figure 2 Avnet MicroZed Embedded Vision Kit 1 4 Required Development Software The logiREF SDSoC FACE EVK reference design and Xylon logicBRICKS IP cores are compatible with the Xilinx SDSoC Development Environment 2015 2 1 5 How to Get the Reference Design This reference design is available for free and with no obligations to registered logicBRICKS web users To get the design please visit our web site and follow instructions from the Chapter 8 www logicbricks com logicBRICKS Reference logicBRICKS Design Face Detection Iracking SDSoC Demo aspx Copyright Xylon d o o 2015 All Rights Reserved Page 7 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 2 DESIGN DELIVERABLES 2 1 SDSOC platform Supports standalone applications Includes software drivers for included logicBRICKS and Avnet IP cores Contains the pre built hardware files for faster software development Xylon evaluation logicBRICKS IP cores logiWIN Versatile Video Input logiC VC ML Compact Multilayer Video Controller logiCLK Programmable Clock Generator logiBAYER Color Camera Sensor Bayer Decoder 2 2 Software logicBRICKS standalone bare metal drivers with driver examples Zynq FSBL sources and the Xilinx SDK project custom version for standalone applications Bare metal demo app
11. Xylon logiREF ZGPU ZED_120919 j E balak Designed by XYLON Installation has completed successfully N 2 Done Figure 24 Installation Process Step 5 Copyright Xylon d o o 2015 All Rights Reserved logiREF SDSoC FACE EVK SDSoC FDT Ref Design User s Manual Sulon Version v1 0 0 e H Xylon logiREF ZGPU ZED_120919 i Ri Lea El Ki By clicking Next you are accepting the following mm XYLON SOFTWARE EVALUATION LICENSE AGREEMENT XSWELA IMPORTANT READ BEFORE COPYING INSTALLING OR USING Do not use or load this software and any associated materials collectively the Software 1 until you have carefully read the following terms and conditions By loading or using the Software you agree to the terms of this Agreement If you do not wish to so agree do not install or use the Software Designod by XYLON LICENSED MATERIALS logi3D LNX software drivers for logi3D for Linux LICENSED PERIOD unlimited LICENSE This Software is licensed for use only in conjunction with Xylon FPGA IP cores products Use of the Software in conjunction with non Xylon FPGA IP cores or component products is not licensed hereunder Subject to the terms of this Agreement Xylon grants to You a nonexclusive nontransferable license under Xylon s copyrights to use modify and copy Software internally for evaluation purposes You may not reverse compile disassemble or otherwise reverse e
12. graphics To get Xylon free GUI reference designs please visit http Awww logicbricks com logicBRICKS Reference logicBRICKS Design aspx To learn more about the available software support for graphics logicBRICKS IP cores please visit http Awww logicbricks com logicBRICKS Reference logicBRICKS Design OS IP Core Support aspx Copyright Xylon d o o 2015 All Rights Reserved Page 24 of 40 gt logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 logiBITBLT Bit Block Transfer 2D Graphics Accelerator This 2D graphics accelerator speeds up the most common GUI operations and off loads the processor The logiBITBLT transfers graphics objects from one to another A part of system s on screen or off screen video memory and performs different gt X eS operations during transfers such as ROP2 raster operations bitmap scaling stretching and flipping Porter amp Duff compositing rules or transparency More info http Awww logicbricks com Products logiBITBLT aspx Datasheet http www logicbricks com Documentation Datasheets IP logiBITBLT be od logi3D Scalable 3D Graphic Accelerator The logi3D Scalable 3D Graphics Accelerator IP core is a 3D Graphics Processing Unit GPU IP core developed for embedded systems based on the Xilinx Zynq 7000 All Programmable SoC at e The IP is designed to support the OpenGL ES 1 1 API specifications a royalty
13. ports from 3 to 15 The Xylon evk_fdt platform supports standalone applications and contains precompiled Standalone drivers for the included logicBRICKS IP cores IP software drivers source files are included within the reference design deliverables please see the Table 1 in Chapter 8 4 The provided platform also includes the pre built SoC bitstream for faster user workflow described in REF 3 The bitstream enables users to run and verify custom developed applications entirely in software and without engaging in the lengthy process of hardware implementation However that process cannot be used with the provided demo application as it is using an HDL defined and preconfigured IP from a C callable IP library for application acceleration Alternatively user can generate bitstream for the Face Detection and Tracking application and then uncheck the Generate Bit Stream It will enable the tools to rebuild only software portions of the design 5 1 Using evk_fdt SDSoC platform and logiFDT IP core To get more information about the demo setup please check the Chapter 6 and readme htm1 file in the reference demo installation folder Please copy the evk_fdt platform folder to folder lt SDSoC_install_dir gt platforms within your SDSOC installation folders Copyright Xylon d o o 2015 All Rights Reserved Page 13 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version
14. 00 All Programmable SoC and FPGAs This IP core is the cornerstone of all 2D and 3D GPUs Though its main function is to provide flexible display control it also includes hardware acceleration functions three types of aloha blending panning buffering of multiple frames etc Supports all Xilinx FPGA families Supports LCD and CRT displays easily tailored for special display types 64x1 to 2048x2048 display resolutions Available SW drivers for Linux Android QNX and Microsoft Windows Embedded Compact OS Support for higher display resolutions available on request Supports up to 5 layers the last one configurable as a background layer Configurable layers size position and offset Alpha blending and Color keyed transparency Pixel layer or Color Lookup Table CLUT alpha blending mode can be independently set for each layer Packed pixel layer memory organization o RGB 8 bpp 8 bpp using CLUT 16bpp Hi color RGB 565 and True color 24bpp o YCbCr 16bpp 4 2 2 and 24bpp 4 4 4 Configurable CoreConnect PLBv4 6 Xylon XMB or ARM AMBA AXI4 memory interface data width 32 64 or 128 Programmable layer memory base address and stride Simple programming due to small number of control registers Support for multiple output formats Parallel display data bus RGB 12x2 bit 15 bit 16 bit 18 bit or 24 bit YCbCr 4 4 4 or 4 2 2 output format s Digital Video ITU 656 PAL and NTSC LVDS output format 3 or 4 data pairs pl
15. AAT ACP The SDSoC uses the SOO _AXI port to connect user generated logic to cache coherent memory space Xylon demo uses this port to connect the logiFDT Face Detector and Tracker IP core If you are using the Xylon platform files without the logiFDT IP core please make sure to terminate the AXI SOO_AXI port or the Validate design phase will generate an error If you connect some other cache coherent IP core to that port and use Xylon platform files no errors shall be generated Otherwise to properly terminate the port open platform s Vivado Block design and connect the S00 ACLK and the SOO ARESETN as shown by Figure 6 It is advised to connect the GOU ACLK port to the same clock net as the ACLK port Similarly the SOO ARESETN port should be connected to the same net as SO1_ ARESETN port Copyright Xylon d o o 2015 All Rights Reserved Page 14 of 40 E logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual Y July 20 2015 Version v1 0 0 Slas evk fat aan 21 aE S_axi ot eko xiconcat_0 vdata_in_0 23 0 inof0 0 Ini 0 0 dout 2 0 Se In2 0 0 as ant ug rmo ct OK dk AE mn au D as vm me om vdata_in_fid_0 RICKS curr_vouff 1 0 disant ACP wg i XI_ACP_ARCACHE 3 next_vbuff 1 0 sw_vbuff_req K ANLACE 3 0 P r FIXED_IO F AGE garnt kee PS_AXI_ACP_AWCACHE 3 0 IXED_IO3F D z Eege bs S_AXI_ACP_ARUSER 4 0 USBIND_0 A ad SC Designed by KYLON tea We PeS_AXI_ACP
16. C FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 1 INTRODUCTION The logiREF SDSoC FACE EVK is free and pre verified logicBRICKS reference design that includes evaluation logicBRICKS IP cores and hardware design files prepared for the Xilinx SDSoC Development Environment It also includes the SDSoC platform files for the targeted hardware platform demo software and documentation The showcased application example is a real time face and facial features tracking Fig 1 in video sequences from a video camera REF 1 The design is prepared for the Xilinx Zynq 7000 All Programmable SoC based MicroZed Embedded Vision Development Kit from Avnet Electronics Marketing fitted with the ON Semiconductor s PYTHON 1300 1 3 MP video camera The Xilinx SDSoC development environment enables developers to easily combine HDL based IP cores and the C C implemented IP cores within a single familiar framework and this demo demonsirates how an existing Xylon s logiFDT Face Detector and Tracker IP core can be wrapped into a C function and used within software defined SDSoC development environment Face Detection and Tracking demo by Xylon Xilinx SDSoC Design Example Using an existing HDL IP core as a callable C function bel Face Detector and et f Tracker IP Core Optimized for Xilinx Zynq 7000 AP Sot Real time face and facial features tracking Delivers full 3
17. D and 2D cOordinates of facial features and head pose Figure 1 Screenshot from the Xylon Face Tracking Demo This reference design is functionally equal to Xylon s logiIREF FACE TRACK EVK Face Detection and Tracking reference design which is implemented fully in the Xilinx Vivado Design Suite http www logicbricks com logicBRICKS Reference logicBRICKS Design Face Detection for Zyng AP SoC aspx Please check Xylon s Video Gallery web pages http www logicbricks com logicBRICKS IP Library Video Galleries logicBRICKS Face I racking Demo aspx to preview the Face Tracking demo provided with the logiIREF SDSoC FACE EVK installation for your MicroZed EVK development kit Copyright Xylon d o o 2015 All Rights Reserved Page 5 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 1 1 About Face Detection and Tracking Application A human face provides a variety of different communication functions in complex interactions between humans Beside to identification humans use head pose and facial expressions during conversation to express emotions reveal intents display attention and more The face detection and tracking is a computer technology that uses video images captured by the video camera to determine and track those distincttive facial features This technology significantly improves human machine interaction and opens a very wide ran
18. ER Color Camera Sensor Bayer Decoder 22 7 3 5 logiCLK Programmable Clock Generator 23 7 4 LOGICBRICKS IDGopEetopVIpEoObpOoCESeoING 23 7 5 LOGICBRICKS IP CORES FOR GRAPHICAL USER INTERFACE GU 24 8 GET AND INSTALL THE REFERENCE DESIGN ee KEEN KENE KEE EEN ENN NN 26 8 1 REGISTRATION PROCESS aanuannunnunnnnnnnnnnnnnnnnnn nnana annann n naunan EAn EL REEL EA LEELEE REAA LAR LARLA A LEALE A nnna nannan 26 8 2 INSTALLATION DpOCESS 29 8 3 FILESYSTEM PERMISSIONS OF THE INSTALLED FOLDER WINDOWS 7 csccceececeeeeeeeeteeeeseees 29 8 4 FOLDER STRUCTURE EE 31 9 GETTING LOGICBRICKS EVALUATION LICENSES c cccccccccesececeeeceeeeeceneeeneneneneneneneas 33 10 SOFTWARE DOCUNENTATION see ENEE ENNEN ENKEN ENKEN NENNEN NENNEN ENNEN ENKEN EN EN EN 36 10 1 LOGIFDT SDK DOCUMENTATION nnsenannsnnnnnnnnunnnnnnnnnnnnnnnnnnnnrnnrrnnnrrnnrrnnurrnarrrnurrnnnnrnurrnnnrrnnrrnnn 36 10 2 LOGIFDT TRACKING GONFEIGURATION rnunana rruan annann annann ann nnrann 36 10 3 DIFFERENCES TO THE LOGIREF FACE TRACK EVK GOETWARE 38 NICI lei CH 39 12 REVISION HISTORY ccccccececscecscecscecscececececececececececeeeeeeeeeeececeeecececececeneneneaeaeaeaeaeaeaeaeaenensaeesass 40 Copyright Xylon d o o 2015 All Rights Reserved Page 3 of 40 F logiREF SDSoC FACE EVK RICKS SDSoC FDT Ref Design Designed by XYLON User s Manual Y July 20 2015 Version v1 0 0 Copyright Xylon d o o 2015 All Rights Reserved Page 4 of 40 gt logiREF SDSO
19. KS reference design and installer for your operating system from the Downloads Navigation Page link bellow you will get an e mail with the download link for the selected reference design installation http www logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Designs Navigation Page aspx Figure 19 Registration Process Step 5 Copyright Xylon d o o 2015 All Rights Reserved Page 28 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 8 2 Installation Process Installation process is quick and easy Each logicBRICKS reference design can be downloaded as a cross platform Java JAR self extracting installer Please make sure that you have a copy of the JRE Java Runtime Environment version 6 or higher on your system to run Java applications and applets Double click on the installer s icon to run the self installing executable to unpack and install the reference design on your PC At the beginning you will be requested to accept two evaluation licenses Figure 20 and Figure 21 For installation in Linux OS please follow instructions http Awww logicbricks com logicBRICKS Reference logicBRICKS Design Xylon Reference Desiqns Linux Installation aspx lf you agree with the conditions from the evaluation licenses click NEXT and select the installation path for your logicBRICKS reference design Figure 22 T
20. MicroZed Embedded Vision development kit Table 1Error Reference source not found explains the purpose of folders 9 INSTALLATION ROOT BINARIES DOC HARDWARE SDSOC SOFTWARE ia bin JJvisagespK rivers platforms aus logiREF FACE al Fmc imageon vita evk_fdt TRACK EVK pdf E receiver files Sal libs _ al logiCLK SW Files Start html Eat SDSoC_ Eval licenses pdf _ al logiCVC SW Files workspace Es al logiWIN SW Files _ Readme html _Jsw_services al Fat_fs at FMC_liC SW at FMC_IMAGEON SW at Platform at XL2 al Xyl_Ivlib al Xyl_oslib Cam LOGICBRICKS Jib al logiCVC ML IP XACT core logiFDT IP XACT core al logiWIN IP XACT core TC al logiCLK IP XACT core al logiBAYER IP XACT core S avnet_embv_cores SP al fmc_imageon_vita_receiver at embv_hdmi at embv_hdmi kg interfaces Figure 25 Installed Reference Design The Folder Structure Copyright Xylon d o o 2015 All Rights Reserved Page 31 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 Table 1 Explanation of Folders in logiREF SDSoC FACE EVK Reference Design e Folder Purpose navigation page through the reference design binaries Pin Prepared binaries ready for download to SD card er drivers EE bare metal drivers for logicBRICKS IP cores with documentation and examples
21. T Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 Figure 11 shows imported logicBRICKS IP cores into Vivado Design Suite while the Error Reference source not found shows a typical logicBRICKS IP core s configuration GUI I Face Tracker and Decoder 1 0 fe l J Documentation I IP Location Show disabled ports Component Name logifdt_0 Source Size Number of parallel calcuations 4 Figure 12 Example of logicBRICKS IP Configuration GUI Example of logicBRICKS IP Configuration GUI Click on the Documentation icon in the GUI opens the User s Manual of the logicBRICKS IP core 7 2 Evaluation logicBRICKS IP Cores Xylon offers free evaluation logicBRICKS IP cores which enable full hardware evaluation Imported into the Xilinx ISE Platform Studio XPS and Vivado IP Integrator IPI P parameterization through the tool GUI interface Bitstream generation lf you need to simulate logicBRICKS IP cores please contact Xylon The logicBRICKS evaluation IP cores are run time limited and cease to function after some time Proper operation can be restored by reloading the bitstream Besides this run time limitation there are no other functional differences between the evaluation and fully licensed logicBRICKS IP cores Evaluation logicBRICKS IP cores are distributed as parts of the Xylon reference designs http Awww logicbricks com logicBRICKS Referen
22. Tongue Feature points affected by FAPs o Other feature points Figure 34 MPEG 4 FAB Standard Defined Facial Feature Points Red dots on Figure 34 mark the facial features tracked by the logiFDT setup with the delivered High Profile configuration Copyright Xylon d o o 2015 All Rights Reserved Page 37 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 Figure 35 logiFDT Tracked Points in the Low Profile Configuration 10 3 Differences to the logiREF FACE TRACK EVK software The demo application in the logiIREF SDSoC FACE EVK reference design consists of two major projects and two smaller library projects In the logiIREF FACE TRACK EVK reference design which is fully Vivado based version of the Face Detection and Tracking there are application project and a library project The two main projects are a library project that has essentially all of the sources from the logiREF FACE TRACK EVK and an SDSoC project that has application start point and the C callable IP call They are partitioned this way because Face Detection and Tracking application uses OpenCV library that is different from the Xilinx s implementation of OpenCV in SDSoC and Vivado HLS And thus this causes incompatibilities that prevent building of application when configured as single project The other two provided projects are C callable IP library and a utility library Copyright
23. VELOPMENT ENVIRONMENT 6 1 3 REQUIRED HARDWARE PLATFORM easaanannnnnnnnnunnnnnnnnnnnnnnnnnn rnanan n aaran a naea nE A REAREA LARRA REAR anana a nannt 7 1 4 REQUIRED DEVELOPMENT DOETWARE 7 1 5 HOW TO GET THE REFERENCE DESIGN 7 2 DESIGN DELINERARLESGS NNN ENNEN NENNEN ENKEN ENKEN EN ENKEN ENKEN NENNEN ENEE ENEE KKK NNN NNN 8 2 1 SDSOC BLATEORNM 8 2 2 SOFTWARE tee 8 2 3 Ed e 8 3 USAGE MODES EE 9 3 1 QUICK EVALUATION WITH NO HW AND OR SW CLHANGES 9 3 2 CHANGE THE HW SW THROUGH THE SDSOC wWORKELOWW 9 LOGIREF SDSOC FACE EVK DESIGN cccccccscecsescscecseecseeceeeeeeececececeneneneneaeasaeaeaeaeneueneeeaes 10 SDS0C PLATFORM RE 13 5 1 USING EVK_FDT SDSOC PLATFORM AND LOGIFDT IP CORE c cccccccceseeseeseeseeseeseeseueeaeeaeees 13 5 2 USING AND CONFIGURING LOoGIkDlTIbcopE 14 5 3 TERMINATE SDSOC EXPORTED UNUSED AChpOopnr 14 I E A RE 16 6 1 SET UP THE MICROZED EMBEDDED VISION KIT FOR USE WITH THE DEMOG 16 6 2 RUNNING THE PRECOMPILED DEMO FROM THE SD CGAaApplMAGE 17 T LOGICBRICKS IP e ail 18 7 1 ABOUT LOGICBRICKS IP LIBRARY aaannannnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnrnnrrnnnrrnnrrnnnrrnnrrnns 18 7 2 EVALUATION LOGICBRICKS IDCGopse 19 7 3 LOGICBRICKS IP CORES USED IN THIS DESIGN nnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnrrnnrnnnrnnrnns 20 7 3 1 logiFDT Face Detector and Trachker AA 20 7 3 2 logiCVC ML Compact Multilayer Video CGontroller 21 7 3 3 logiWIN Versatile Video Input 22 7 3 4 logiBAY
24. _AWUSER 4 0 M_AXI_GPO fi m3 ep g a Ge e ar S_AXI_HPO ZYNQ FCLK_CLKO i i SE 4ES_AXI_HP2 FCLK_CLKI She M_AXI_GPO_ACLK FCLK_CLK2 s axi_aresetn S_AXI_ACP_ACLK FCLK_CLK3 Capture stop S_AXI_HPO_ACLK FCLK_RESETO_N Versatile Video Input 00_ACLK S_AXI_HP2_ACLK IRQ_F2P 2 0 ZYNQ7 Processing System See pel Pax logiclk_0 logicvc_0 ae m_axisk j vid_io DE RICKS NEE rd _AXI_ARESETN iin ia Dm Ch no maen Designed by XYLON interrupt ac ARESETN S L Sai E ES MO A1 4 Multilayer Video Controller SO0_ARESETN 0 0 py e MOO SCLK MOO_ARESETN 0 0 AXI Interconnect loakclk i fmc_imageon_vita_receiver_0 xSVI_OuT xsvi_vsync_oP xsvi_video_data_of7 0 gt xsvi_active_video_o e ES At Sain a Figure 6 Terminated S00_ACLK and S00_ARESETN Ports Copyright Xylon d o o 2015 All Rights Reserved Page 15 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 6 QUICK START 6 1 Set up the MicroZed Embedded Vision Kit for Use with the Demo Xylon provides the demo binaries in the binaries bin folder of the delivery In order to quickly run the precompiled Xylon demo please copy the contents of the binaries bin folder to the root folder on the FAT32 formatted SD card and use it with the hardware kit The programmed SD card s root folder should look as shown by the Figure 7 Name
25. ation folder doc visageSDK doc Xylon doc html File Edit View History Bookmarks Tools Help o E e visage SDK documentation x tb B Geog Pies tr DHE 2 Most Visited Getting Started L Xylon logicBRICKS IP A Xcell Daily Blog Xilinx M EZmove m Classic Games logiFDT SDK ogiFDT SE Welcome to logiFDT SDK e Xylon and Visage Technologies have entered a technology partnership with the goal of jointly delivering Visage Technologies oe API powerful face detection and tracking technology through the Xylon s logicBRICKS IP library The result of this parnership is the E Licensing logiFDT Face Detector and Tracker IP core which is optimized for use in Xilinx Zynq 7000 All Programmable SoC System on ES References Chip The logiFDT SDK is a software development kit encapsulating Visage Technologies powerful face detection and tracking i technology for use with the logiFDT IP core Documentation logiFDT Face Detector and Tracker logiFDT SDK documentation consists ofthis user manual and additional reference manuals for specific purposes MPEG 4 Face and body animation overview tracker configuration etc These additional manuals are accessed through links in this document or directly in the doc folder Getting started logiFDT SDK provides a flexible API Supporting a variety of applications An overview of the API is given in the AP section logiFDT SDK includes sample projects with full source code demonst
26. ce logicBRICKS Design aspx Specific IP cores can be downloaded from Xylon s web shop Copyright Xylon d o o 2015 All Rights Reserved Page 19 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 htto www logicbricks com Products IP Cores aspx 7 3 logicBRICKS IP Cores Used in This Design 7 3 1 logiFDT Face Detector and Tracker The logiFDT Face Detector and Tracker IP core finds and tracks the face and facial features in video sequences in real time and returns full 3D head pose gaze direction facial features coordinates and a wealth of other information that can be used in different applications developed on top of it Supports Xilinx Zyng 7000 All Programmable SoC Real time face and facial features tracking in video sequences from a camera or a file Easy to Use API for accessing the tracking data 3D head pose translation and rotation Gaze direction and eye closure Facial feature coordinates in global 3D space Feature points specified according to the MPEG 4 FBA standard Action units describing the current facial expressing i e brow raise lips stretch jaw drop etc 3D model of the face in current pose and expression returned as single textured 3D triangle mesh Other tracking data Fully automatic operation and robust recovering from losses due to occlusions face turning away and similar Tracking internally wo
27. censes from Xylon The following pages describe the procedure for getting and licensing evaluation logicBRICKS IP cores that takes several minutes to complete If you experience any troubles during this process please contact Xylon Technical Support Service support logicbricks com You must be logged in to the Xylon website using your logicBRICKS user name and password to get an access to evaluation logicBRICKS IP cores Unregistered users will be re directed to the User Login page Paragraph 8 1 Registration Process explains this simple registration procedure Step 1 Logged in users get the My logicBRICKS tab in the main www logicbricks com navigation menu Click on it and you will be directed to your main web page for communication with Xylon logicBRICKS Figure 26 Please select the Request Eval IP Core tab in the left menu Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp Events MylogicBRICKS My logicBRICKS Ge F Quick Info My logicBRICKS Video for Xiinx Zynq 7000 EPP and FPGAS View Data Change Password Request Eval IP Core IP Core Activation Create Case Subscribe to Newsletter Downloads Welcome to logicBRICKS Registered Users Section Within this section you can Quickly get instructions on how to download install or purchase logicBRICKS products View Data View and update your user data logicBRICKS profile Change Password Change y
28. d a comprehensive design environment for heterogeneous Zynq All Programmable SoC and MPSoC deployment Complete with the industry s first C C full system optimizing compiler SDSoC delivers system level profiling automated software acceleration in programmable logic automated system connectivity generation and libraries to soeed programming To access the capabilities of SDSoC please visit www xilinx com sdsoc Xylon is an SDSoC development environment qualified Xilinx Alliance Member and offers logicBRICKS IP cores complete Xilinx All Programmable based solutions and design services Copyright Xylon d o o 2015 All Rights Reserved Page 6 of 40 SDSoC FDT Ref Design logiREF SDSoC FACE EVK um 9 User s Manual Sulon Version v1 0 0 Designed by XYLON July 20 2015 1 3 Required Hardware Platform The logiREF SDSoC FACE EVK prepared for the MicroZed Embedded Vision Kit from Avnet Electronics Marketing The compatible demonstration platform requires the following hardware components MicroZed Embedded Vision Development Kit Part Number AES MBCC EMBV DEV KIT or the equivalent combination built of D H a Ss HHH d e Di mam l MicroZed 7020 SOM Part Number AES Z7MB 7Z020 SOM G a E Ai Cian U MicroZed Embedded Vision Carrier Card Kit Part Number AES MBCC EMBV G and ON Semiconductor PYTHON 1300 COLOR Camera Part Number AES CAM ON P1300C G Avnet Electronics
29. ecompiled Face Detection and Tracking demo make sure that you have the SD card with the precompiled image plugged in the board s slot and all jumpers setup as described in the previous paragraph The demo supports two tracking modes single face tracking and detection of multiple faces To switch between these modes please push the SW1 push button on the MicroZed board Copyright Xylon d o o 2015 All Rights Reserved Page 17 of 40 SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 it logiREF SDSoC FACE EVK um 9 7 LOGICBRICKS IP CORES 7 1 About logicBRICKS IP Library Xylon s logicBRICKS IP core library provides IP cores optimized for Xilinx All Programmable devices logicBRICKS IP cores shorten development time and enable fast design of complex embedded systems based on Xilinx All Programmable devices The key features of the logicBRICKS IP cores are Compatibility with the Xilinx Vivado and ISE Design Suites logicBRICKS can be used in the same ways as Xilinx IP cores and require no skills beyond general tools Knowledge IP core feature sets and programmable logic utilization can be setup through Xilinx tool GUI Each logicBRICKS IP core comes with the extensive documentation reference design examples and can be evaluated on reference hardware platforms Xylon provides evaluation logicBRICKS IP cores to enable risk free evaluation prior to purchase Broad software
30. edded image color enhancements brightness contrast hue saturation ARM AMBA AXI4 and AXI4 Lite bus compliant Available for Xilinx Vivado IP Integrator and ISE XPS implementation tools More info htto www logicbricks com Products logiWIN aspx Datasheet htto www logicbricks com Documentation Datasheets IP logiWIN_hds pdf 7 3 4 logiBAYER Color Camera Sensor Bayer Decoder Converts Bayer color coded video inputs into RGB video Supports all possible Bayer patterns Supports input resolutions up to 4096x4096 including 4K2K Also supports input video scaling Supports Xilinx Zyng 7000 AP SoC and FPGAs Converts camera sensor video from Bayer color space to RGB or YCrCb 4 2 2 Supports all possible Bayer pattern combinations first two pixels BG RG GB GR Maximum input and output resolutions 4096x4096 Supports different input interface standards Parallel data control and clock signals AxX1 4 Stream AXI4 compliant video interface LVDS 1 12 deserialization with embedded clock Supports different output interface standards Parallel data control and clock signals AxX1 4 Stream AXI4 compliant video interface Memory XMB PLBv46 NPI and AXI4 Cropping two pixels or two lines from each side of the input image RGB 24 bit RGB888 or 32 bit ARGB8888 or YCrCb 16 bit 4 2 2 output color representation Available for Xilinx Vivado IP Integrator and ISE XPS implementation tools Copyri
31. eo Controller IP core displays the camera video overlaid by graphically presented face tracking results The logiWIN frame grabbers store the video in video frame buffers implemented in external DDR3 memories The logiWIN is AXI4 bus protocol compliant and can be easily connected to Zynq 7000 AP Copyright Xylon d o o 2015 All Rights Reserved Page 11 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 SoC memory controller The logiWIN IP cores are synchronized with the logiCVC ML Compact Multilayer Video Controller and the logiFDT Face Detector and Tracker The IP core enables easy implementation of the multiple buffering video storage method that assures a flicker free video output The memory subsystem is an essential part of any video and graphics based system It must ensure enough storage space for video buffers GUI elements and application code as well as a fast interface to assure enough memory bandwidth for a smooth and uninterrupted SoC operation The MicroZed board includes two 16 bit DDR3 memories connected as one 1GB 32 bit memory module The memory is connected to the hard memory controller in the Zynq 7000 AP SoC Processor Subsystem PS The logiGVC ML Compact Multilayer Video Controller IP core drives a common PC monitor through the ADV7511 High Definition Multimedia Interface HDMI transmitter available on the MicroZed Embedded Visi
32. erence logicBRICKS designs can be downloaded as cross platform Java JAR self extracting installers For quick registration and other general instructions please visit http Awww logicbricks com logicBRICKS logicBRICKS Quick Info aspx 8 1 Registration Process Registration is very quick and simple If you experience any troubles during the registration process please contact Xylon Technical Support Service support logicbricks com Copyright Xylon d o o 2015 All Rights Reserved Page 26 of 40 gt logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Sulon Version v1 0 0 Designed by XYLON User s Manual July 20 2015 RICKS Login St Shopping Cart e Home Aboutus Products Markets Solutions logicBRICKS Downloads Documentation News amp Events English SES Login About us Products Markets IP Cores for Your Low Volume FPGA Products Solutions logicBRICKS Downloads Documentation s gt i Register get and evaluate logicBRICKS IP cores in just a few clicks News amp Events L SS Ste 1 X ES N For registration and other general instructions please CLICK HERE p If you are the registered logicBRICKS user please type in your Username and Password Unregistered users should click on the Register button which will open the registration form Figure 15 Registration Process Step 1 Register Ges gt EE a errs fi Step 2 wate Se Unregistered users should fill
33. ge of applications such as driver drowsiness detection in automotive safety systems that prevent accidents speaker detection in video conferencing systems capable to automatically zoom to the current speaker hands free interfacing helping disabled people to improve their daily lives character animations in virtual reality entertainment and gaming health robotics audio processing and others Xylon and Visage Technologies AB have entered a technology partnership with the goal of jointly delivering Visage Technologies state of the art face detection and tracking technology through the Xylon logicBRICKS IP library As the result of this partnership Xylon has designed the logiFDT Face Detector and Tracker IP core optimized for use with Xilinx Zynq 7000 All ProgrammableSoC The logiFDT IP core finds and tracks the face and facial features in video sequences in real time up to 30 fps and returns full 3D head pose gaze direction facial features coordinates and a wealth of other information that can be used in different applications developed on top of it LVA r Visage Technologies logiFDT I SDK Face Track tracking engine is sourced from FACE TRACKING L AMIHATION Technology Partner Visage Technologies AB 1 2 About Xilinx SDSoC Development Environment The Xilinx SDSoC development environment is a member of the Xilinx SDx family that provides a greatly simplified ASSP like C C programming experience including an easy to use Eclipse IDE an
34. ght Xylon d o o 2015 All Rights Reserved Page 22 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 More info htto www logicbricks com Products logiBAYER aspx Datasheet htto www logicbricks com Documentation Datasheets IP logiIBAYER_ hds pdf 7 3 5 logiCLK Programmable Clock Generator The logiCLK is a programmable clock generator IP core featuring twelve independent and fully configurable clock outputs While six clock outputs can be fixed by generic parameters prior to the implementation the other six clock sl outputs can be either fixed by generics or dynamically reconfigured in a i working device The Dynamic Reconfiguration Port DRP interface gives system designers the ability to change the clock frequency and other clock parameters while the design is running by mean of a set of PLL registers Supports Xilinx Zynq 7000 All Programmable SoC 7 series and Spartan 6 FPGAs Provides 12 independent clock outputs that can be configured by generic parameters o 6 outputs can be dynamically configured through the DRP interface o 6 outputs can be configured by generics only Input clock frequency range o Spartan 6 19 540 MHz o 7 series 19 1066 MHz Output clocks frequency range o Spartan 6 3 125 400 MHz o 7 series 6 25 741 MHz Configurable ARM AMBA AXI4 Lite and CoreConnect PLBv46 compliant registers inte
35. he installation process takes several minutes It generates the folder structure described in the paragraph 8 3 Folder Structure 8 3 Filesystem permissions of the installed folder Windows 7 The reference design installed in the default path C Program Files xylon will inherit read only filesystem permissions from the parent directory This will block you in opening the hardware project file in Xilinx Vivado tools Therefore it is necessary to change the filesystem permissions for the current user to Full control preferably To change the user permissions for C Program Files xylon folder and all of its subfolders right click on the C Program Files xylon folder and select Properties Under Security tab select Edit Select Users group in the list and check Full control checkbox in the Allow column Copyright Xylon d o o 2015 All Rights Reserved Page 29 of 40 ak Designed by XYLON July 20 2015 Kl Xylon logiREF ZGPU ZED_120919 Mires Designed by XYLON 3 By clicking Next you are accepting the following XYLON EVALUATION SEAT LICENSE AGREEMENT XESLA IMPORTANT UNLESS SUPERSEDED BY A SIGNED LICENSE AGREEMENT BETWEEN YOU AND XYLON THIS XYLON EVALUATION SEAT LICENSE AGREEMENT XESLA IS A LEGAL AGREEMENT BETWEEN YOU AND XYLON doo PROVIDING YOU WITH THE LICENSE TO USE THE LICENSED MATERIALS UNDER THE TERMS AND CONDITIONS OF THIS AGREEMENT CAREFULLY READ THIS
36. in the registration form ane i from the Fig 16 Please take care on required form s Sg si fields Your Username is an actual e mail account used for communication with Xylon logicBRICKS e Seenen Xylon accepts only valid company e mail accounts Figure 16 Registration Process Step 2 ang oe Kee zem Register Step 3 Ge D s egmas Si mae SE r afi As soon as your registration form gets accepted by Pena m gP Xylon you get a confirmation message Please a check your e mail to find a link that activates your logicbaicxs logicBRICKS account If you do not get the P BW confirmation message in several minutes please check your Spam Filter or Junk Mail Folder If you have not received the confirmation message please contact Xylon support Figure 17 Registration Process Step 3 Copyright Xylon d o o 2015 All Rights Reserved Page 27 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 Activate Account EECH anc Video Z Ce e About us el Xylon logicBRICKS RNR ES vn be ZA Produc ts Graphics for Xilinx Zeng 2000 Markets Sick KO get reference designs for irx 2C702 Evauaton Board KS 7 uccess act Our a t Step 4 Click on the logicBRICKS web account activation link in the received e mail and you will get the confirmation status message Please login to proceed Step 5 As soon as you select an appropriate logicBRIC
37. lication for face detection and tracking 2 3 Binaries Precompiled SD Card image for the fastest demo startup Copyright Xylon d o o 2015 All Rights Reserved Page 8 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 3 USAGE MODES The logiREF SDSoC FACE EVK reference design can be used in different ways which are listed in this paragraph and thoroughly explained through this document 3 1 Quick Evaluation with no HW and or SW Changes Download and install the logiIREF SDSoC FACE EVK reference design chapter 8 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware and use the provided SD card image to run the precompiled demo application paragraph 6 1 Set Up the MicroZed EVK kit for Use with the Precompiled Demo From the SD Card 3 2 Change the HW SW through the SDSoC workflow In order to develop standalone software applications and optionally to add your own C C or HDL based hardware accelerators in the programmable logic please follow these steps Download and install the logIREF SDSoC FACE EVK reference design chapter 8 GET AND INSTALL THE REFERENCE DESIGN Setup the demo hardware paragraph 6 1 Set Up the MicroZed EVK kit for Use with the Precompiled Demo From the SD Card Obtain logicBRICKS IP core evaluation licenses from Xylon chapter 9 GETTING LOGICBRICKS EVALUATION LICENSES To set up the working envir
38. logiREF SDSoC FACE EVK Using an Existing HDL IP Core as a C Function in the Xilinx SDSoC Development Environment Demo Xylon Face Detection and Tracking User s Manual Version 1 0 0 logiIREF SDSoC FACE EVK_v1_0_1 docx aac g ff f P 28 L Seal SS i logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 BRICKS Designed by XYLON All rights reserved This manual may not be reproduced or utilized without the prior written permission issued by Xylon Copyright Xylon doo logicBRICKS is a registered Xylon trademark All other trademarks and registered trademarks are the property of their respective owners This publication has been carefully checked for accuracy However Xylon does not assume any responsibility for the contents or use of any product described herein Xylon reserves the right to make any changes to product without further notice Our customers should ensure to take appropriate action so that their use of our products does not infringe upon any patents Copyright Xylon d o o 2015 All Rights Reserved Page 2 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Sulon Designed by XYLON User s Manual July 20 2015 Version v1 0 0 1 INTRODUCTION BE 5 1 1 ABOUT FACE DETECTION AND TRACKING APPLICATION nnnanannannannnnnnnnnnnnnnnrrnrrerrnrrerrnrrnnrnnrnnrnnne 6 1 2 ABOUT XILINX SDSOC DE
39. ngineer the Software You may not copy modify rent sell distribute or transfer any part of the Software except as provided in this Agreement and you agree to prevent unauthorized copying of the Software Except as expressly stated in this Agreement no license or right is granted to You directly or by implication inducement estoppel or otherwise Xylon shall have the right to inspect or have an independent auditor inspect Your relevant records to verify Your compliance with the terms and conditions of this Agreement with a prior written notice of ten 10 days CONFIDENTIALITY You shall not disclose the terms or existence of this Agreement or use Xylon s name in any publications advertisements or other announcements without Xylon s prior written consent OWNERSHIP OF SOFTWARE AND COPYRIGHTS Title to all copies of the Software remains with Xylon Lei Figure 21 Installation Process Step 2 H Xylon logiREF ZGPU ZED_120919 j 9 Lea Designod by XYLON 4 Pack installation progress D Users 8 Overall installation progress Figure 23 Installation Process Step 4 Page 30 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 8 4 Folder Structure Figure 25 gives a top level view of the folders and files included with the logiIREF SDSoC FACE EVK reference design for the
40. ollects video analytics data for various control algorithms and manipulates video data formats and color domains The IP core can be used with processor based control algorithms for Auto White Balancing AWB and Auto Exposure AE that can be licensed from Xylon Figure 13 Screenshots from the Xylon logilSP Demo logiREF VIDEO ISP EVK To get Xylon free ISP reference design please visit htto www logicbricks com logicBRICKS Reference logicBRICKS Design ISP Pipeline for Xilinx All Programmable aspx To learn more about other Xylon logicBRICKS IP cores for the video processing please visit http www logicbricks com Products IP Cores aspx 7 5 logicBRICKS IP Cores for Graphical User Interface GUI Xylon s logicBRICKS library of IP cores optimized for Xilinx All Programmable devices includes several graphics logicBRICKS IP cores for full range implementation of 2D and 3D Graphics Processing Units GPU on Xilinx Zyng 7000 All Programmable SoC and FPGAs Xylon s graphics logicBRICKS IP cores can be quickly combined with the graphic processing IP cores when it Is necessary to support complex GUI interfaces Graphics logicBRICKS IP cores are well supported by Xylon provided software drivers for the most popular operating systems Linux Android QNX and Microsoft Windows Embedded Compact A number of Xilinx partners who provide BSPs Board Support Package for different operating systems support Xylon logicBRICKS IP cores for
41. on Carrier Card Kit The logiCVC ML automatically handles the full HD graphics background layer and the video overlay The logiFDT IP core is a template matching hardware accelerator that significantly off loads the Zynq SoC processing system and improves the face tracking speed The accelerator fetches a template image pattern and source images from the memory makes cross correlation between each corresponding pixel in the template and the source image and finds the most probable match between the source and the template image The matching is examined by stepping the template image in one pixel steps left right and top down over the whole source image Figure 5 Figure 5 Pattern Matching Principle Illustration Copyright Xylon d o o 2015 All Rights Reserved Page 12 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 5 SDSOC PLATFORM Xylon s evk_fdt platform see Fig 3 for the targeted hardware kit follows Xilinx s SDSoC platform design specifications REF 2 The following Zynq SoC resources are not used by the evk_fdt platform and can be used for other purposes within the SDSoC development environment Clocks Clock id 2 default 100 MHz Clock id 3 120 MHz PS PL ports M AAT GP1 S AAT GPO S AAT Gbi GG AAT Hi GG AAT Hi GG AAT AC over axi_acp interconnect see chapter 5 2 Interrupts Over xliconcat IP
42. onment follow instructions listed in the start html file from your installation root folder for this reference design Try demo compilation and develop your own applications Copyright Xylon d o o 2015 All Rights Reserved Page 9 of 40 logiREF SDS0C FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 4 LOGIREF SDSOC FACE EVK DESIGN Xilinx Zynq Z 7020 Programmable Logic GigE Flash UART SPI DISPLAY CAN I2C as Hiti GPIO Z 7020 Processing System logiCVC ML ADV7511 Display Controller logiCLK Clock Generator Out Y for logiFDT logiWIN_1 Video Frame Grabber Processing system 7 CAMERA VITA Receiver gg PYTHON 1 300 BEE Out YCrCb 4 2 2 for Display logiWIN_0 Video Frame Grabber RD DIGITAL MEMORY doen FPGA XILINX IP logiBRicks On Figure 3 logiREF SDSoC FACE EVK SoC Block Diagram Pre Defined Platform Figure 3 shows the simplified block diagram of the logiIREF SDSoC FACE EVK evk_fdt SDSoC platform without the logiFDT IP core accelerator instantiated Figure 4 shows the block diagram of the SoC design completed with the instantiated logiFDT IP core for face tracking acceleration which is used as a C callable function within the SDSoC design environment Copyright Xylon d o o 2015 All Rights Reserved Page 10 of 40 logiREF SDS0C FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual Y July 20 2015 Ve
43. our logicBRICKS password Quick Info cover if all Knowledge Base Access and search the knowledge base Request an evaluation version of logicBRICKS IP core and check if it a Request Eval IP Core fits to your needs prior to purchase Both pay for and evaluation IP lt www logicbricks com cores have the same licensing procedure Activate your purchased IP core s license key The key is valid for a IP Core Activation single PC or Sun workstation 1 development seat and indentified by unique MAC MS Windows or Linux or Sun HostiD Solaris Create a case for Xylon technical support if you have active IP core or HW platform development license Create Case Subscribe to Newsletter Subscribe or unsubscribe to Xylon s newsletters Figure 26 Step 1 My logicBRICKS Navigation Page Step 2 Select the evaluation logicBRICKS IP core and click on Obtain evaluation license key link Figure 27 If you are entitled to get the evaluation logicBRICKS IP core you will be immediately asked Figure 30 your Ethernet MAC ID number or Sun Host ID as described in the Step 3 If the evaluation logicBRICKS IP cores list looks differently from the one shown on Figure 27 for example as the list presented by the Figure 28 please fill in and submit the request form Figure 29 and allow us some time to process your request Scroll down to get to the request form Copyright Xylon d o o 2015 All Rights Reserved Page 33 of 40
44. rating how to use the API Itis recommended to start by running the samples described in the Samples section Optimized for Xilinx Zynq 7000 AP SoC Sourced by Technology Partner V Visage Technologies FACE TRACKING amp ANIMATION Figure 33 logiFDT SDK Software Documentation The Start Page 10 2logiFDT Tracking Configuration For the face the MPEG 4 specification defines 66 low level Face Animation Parameters FAPs and two high level FAPs The low level FAPs are based on the study of minimal facial actions and are closely related to muscle actions They represent a complete set of basic facial actions and therefore allow the representation of most natural facial expressions Exaggerated values permit the definition of actions that are normally not possible for humans but could be desirable for cartoon like characters Copyright Xylon d o o 2015 All Rights Reserved Page 36 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 To change the profile of the face tracker please exchange the head cfg in the SD card root directory file with one of the three provided Face Tracker configuration files and restart the kit The provided profile configuration files are head_high cfg high profile configuration file head_mid cfg mid profile configuration file head_low cfg low profile configuration file 3 10 e
45. rface Software support for Linux and Microsoft Windows Embedded Compact operating systems Available for Xilinx Vivado IP Integrator and ISE Platform Studio Depending on the used device s speed grade More info htto www logicbricks com Products logiCLK aspx Datasheet http www logicbricks com Documentation Datasheets IP logiCLK hds pdf 7 4 logicBRICKS IP Cores for Video Processing The logilSP Image Signal Processing Pipeline IP core is a full high definition ISP pipeline designed for digital processing and image quality enhancements of an input video stream in Smarter Vision embedded designs based on Xilinx Zyngq 7000 All Programmable SoC and 7 Series FPGA devices More info htto www logicbricks com Products logilSP asox Datasheet htto www logicbricks com Documentation Datasheets IP logilSP hds pdf The logilSP Image Signal Processing ISP Pipeline IP core can be combined with the logiFDT Face Detector and Tracker in order to enhance the video quality prior to the face tracking processing Copyright Xylon d o o 2015 All Rights Reserved Page 23 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 The logilSP IP core accepts diversely formatted video inputs generated by different sensors and removes defective pixels de mosaics Bayer encoded video makes image color and gamma corrections filters the noise from the video c
46. rks on a single channel YUV video Y luminance component used which can be recorded by color grayscale and infrared camera For thermal video info please contact Xylon Carefully hardware software partitioned to assure maximal performance and minimal resources utilization The tracking engine uses single ARM Cortex A9 CPU core supported by hardware acceleration of the most used computing intensive operations implemented in programmable logic The required Zyng 7000 AP SoC resources utilization and achievable performance allows for parallel execution of other real time vision applications on the same SoC Parametrical VHDL design that allows tuning of slice consumption and features set Prepackaged for Xilinx Vivado Design Suite and fully controllable through the IP Integrator GUI interface P deliverables include the software driver documentation and technical support More info http Awww logicbricks com Products logiFD I aspx Datasheet http www logicbricks com Documentation Datasheets IP logiFDT_hds pdf Copyright Xylon d o o 2015 All Rights Reserved Page 20 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 7 3 2 logiCVC ML Compact Multilayer Video Controller The logiCVC ML IP core is an advanced display graphics controller for LCD and CRT displays which enables an easy video and graphics integration into embedded systems with Xilinx Zynq 70
47. rsion v1 0 0 Xilinx Zynq Z 7020 Programmable Logic GigE Flash UART SPI Memo DISPLAY 07 V a yen D e Cont i 1080p GbRIO weg Z 7020 Processing System logiCVC ML ADV7511 Display Controller logiFDT HW Accelerator logiCLK Clock Generator Out Y for logiFDT logiWIN_1 Video Frame Grabber CAMERA VITA Receiver j SS PYTHON 1300 From Avnet a DGC CCE EE logiWIN_0 Video Frame Grabber MIXED 3RD PARTY Figure 4 logiREF SDSoC FACE EVK SoC Block Diagram Platform with the logiFDT IP Processing system 7 From the input to the output image from camera is processed using a number of IPs The VITA Receiver IP core from Avnet Electronics Marketing receives the video data from the ON Semiconductor PYTHON 1300 camera module LVDS data and provides raw Bayer video data and video sync signals at its outputs The logiBAYER IP core converts camera sensor video from Bayer color space to YUV color space The design utilizes two instances of Xylon logiWIN Versatile Video Input frame grabbing IP core One logiWIN IP core does a full resolution frame grabbing then formats and stores the video for the display The other logiWIN IP core scales the video input to the resolution required by the logiFDT face tracking engine and as it is requested by the face tracking software generates the single channel video containing only the Y luminance component of the YUV video input Xylon s logiCVC ML Compact Multilayer Vid
48. support from bare metal software drivers to standard software drivers for different operating systems OS Xylon assures skilled technical support E Project Summary X FI 20 Search A 1 ri Name AXI4 Status License VLNV Alliance Partners ES Xylon l 3 2D Graphics Accelerator Bit Block Transfer AXI4 Production Induded logicbricks com logicbricks logibitblt 0 0 e 3 Audio 12S Transmitter Receiver AXI4 Production Induded logicbricks com logicbricks logii2s 0 0 Bitmap 2 5D Graphics Accelerator AXI4 Production Included logicbricks com logicbricks logibmp 0 0 3 12C Bus Master Controller AXI4 Production Induded logicbricks com logicbricks logii2c 0 0 Multilayer Video Corporate Production _fnduded _flog 3 Perspective Transformation and Lens Correction Image Processor AXI4 AXI4 Stream Production Induded logicbricks com logicbricks logiview 0 0 3 Scalable 3D Graphics Accelerator AXI4 Production Induded logicbricks com logicbricks logi3d 0 0 3 SD Card Host Controller AXI4 Production Induded logicbricks com logicbricks logisdhc 0 0 HL Automotive amp Industrial 0 AXI Infrastructure H Basel gt Basic Elements H Communication amp Networking H Debug amp Verification 4 gt Digital Signal Processing H Embedded Processing H FPGA Features and Design 4 gt Math Functions 4 gt Memories amp Storage Elements H 6 Standard Bus Interfaces HL Video amp Image Processing OS wie
49. uests for support should be directed You can download the evaluation IP core deliverables here You will need your login email and password for access to Xylon web download area This email contains the license s for the core s you requested It enables you tg use the core s at the level authorized by the License Type indicated in the table at the bottom ofthis page A full license allows you to use the core in Full Access mode Eyal IP download link NOTE A full license means that purchased or evaluation IP core can be fully implemented into the Xilinx FPGA The IP core licenses are attached to this e mail 03512090617423596_ip_xap_349logicvcmi_eval_flexim lic NOTE You can alternatively download the license archive by clicking here You must access this downloads evaluation license by September 13 2012 After this date the license archive will be removed from the website Figure 32 Step 4 E mail with logicBRICKS License and Download Instructions Copyright Xylon d o o 2015 All Rights Reserved Page 35 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design dee Designed by XYLON User s Manual July 20 2015 Version v1 0 0 10 SOFTWARE DOCUMENTATION 10 1 logiFDT SDK Documentation User s Manuals and additional reference manuals that describe the operation of the logiFDT software part are provided in the convenient HTML format Please open the documentation in your install
50. us clock Camera link output format 4 data pairs plus clock DVI output format Supports synchronization to external parallel input Versatile and programmable sync signals timing Double triple buffering enables flicker free reproduction Display power on sequencing control signals Parametrical VHDL design that allows tuning of slice consumption and features set Available for Xilinx Vivado IP Integrator and ISE XPS implementation tools More info http Awww logicbricks com Products logiC VC ML aspx Datasheet htip www logicbricks com Documentation Datasheets IP logiC VC ML_hds pdf Copyright Xylon d o o 2015 All Rights Reserved Page 21 of 40 logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual VW July 20 2015 Version v1 0 0 7 3 3 logiWIN Versatile Video Input The logiWIN IP core enables easy implementation of video frame grabbers Input video can be decoded real time scaled de interlaced cropped anti aliased positioned on the screen Supports Xilinx Zyng 7000 AP SoC and FPGAs Maximum input and output resolutions 2048x2048 Supports different input interface standards TU656 and ITU1120 PAL and NTSC RGB YUV 4 2 2 Built in YCrCb to RGB YUV to RGB and RGB to YCrCb converters Real time scale up to 64x and scale down to 16x lossless scaling down to 2x or 4x in the cascade scaling mode Supports video de interlacing cropping positioning pixel alpha blending Emb
51. vated Already activated IP licenses logiWVIN EVAL 1M Activated logiBITBLT EVAL 1M Activated Figure 28 Step 2 A List of Already Activated logicBRICKS IP Licenses logiJART EVAL 1M Not Activated Obtain evaluation license key Your company can get one evaluation license per product per year If your company already used evaluation license in last year you cannot obtain evaluation license automatically In that case please fill form with request for additional evaluation license Subject logic CO C MLIPC Core Evaluatio maae IP Core togicve VC ML EV AL Message Text e would like to use your d core with the Lage gees kit Figure 29 Step 1 Licensing logicBRICKS Evaluation IP Cores Step 3 Evaluation logicBRICKS IP licenses are tied to your Ethernet MAC address or Sun Host ID Figure 30 and can be used on a single working station only Fill in this address and click on the Request License Key button You should get the confirmation message Figure 31 If you do not get the confirmation message please contact Xylon technical support support logicbricks com Copyright Xylon d o o 2015 All Rights Reserved Page 34 of 40 E logiREF SDSOC FACE EVK mm SDSoC FDT Ref Design Designed by XYLON User s Manual Y July 20 2015 Version v1 0 0 Home About us Products Markets Solutions logicBRICKS Downloads Documentation News amp E My logicBRICKS

User`s Manual

Contents

Download Pdf Manuals

Related Search

Related Contents