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Lark Board User Manual

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1. TS system Contents 5 Address Map 5S ITA use Connections Tane Description Export Clock Base End x resetl Reset Input e11 B a E coreclk_fanout Clock Source clkin Clock Input peie_ev clk_in reset Reset Input a aH ak Clock Output coreclk fen clk corec Ik oreclk f n reset z l CAREER mc tput 7 Dj refelk Clock Input o por Conduit nreset_status Reset Output hip_ctrl Conduit peie_ev_hip_avam_0 RP Master Avalon Memory Mapped Master peie_evh IRA 0 J remti Conduit TH Conduit _s reconfigfromxevr Conduit reconfiig clk locked Conduit peie_ev_hip_evam_0 7 Oj hip_serial Conduit pei i E hip pipe Conduit p iiss Tas Avalon Memory Mapped Slave peie_ev_h 0x0000_0000 oxi fe 866 t Cra Avalon Memory Mapped Slave Ipcie_evh a 0x0000 0x3 E Iransceiver Reconfiguration Controller onduit gt mgnt_ell_elle Clock Input peie_ev gt ment_rst_reset Reset Input ngnt_clk D4 reconfig mgnt Avalon Memory Mapped Slave alt_xevr_reconfig_ ment_clk reconfigtoxevr Conduit __ reconfig from xevr Conduit a E ceb_h2 50_to_125 Avalon WM Clock Crossi ing Bridge n0_clk Clock Input peie_ev mO reset Reset Input n0_e1k s0_clke Clock Input elk _50 c drt Reset Input s0_e1k s0 Avalon Memory Mappe
2. VGA Display CN1 7 GND 8 GND 9 VGA_VDD Power 5V 10 GND Ground 11 NC Other 12 I12C_SDA_VGA 12C 13 I12C_SCL_VGA 14 5V_HSYNC SYNC 15 5V_VSYNC e HDMI The HDMI interface on Lark Board is named as J5 which is a standard 19 pin HDMI connector The following table contains pin definitions of the interface including the fixed pins of the connector Table 2 7 HDMI interface HDMI Display J5 Pin Signal Name Device Signal Type 1 HDMI_TX2 CH7033B 2 GND CH7033B 3 HDMI_TX2 CH7033B 4 HDMI_TX1 CH7033B 5 GND CH7033B Differential 6 HDMI_TX1 CH7033B Data amp Clock GND as 7 HDMI_TX0O CH7033B reference for signal 8 GND CH7033B 9 HDMI_TXO CH7033B 10 HDMI_CLK CH7033B 11 GND CH7033B 12 HDMI_CLK CH7033B 13 NC Other 14 NC 15 HDMICONN_I2CSCL TXS0102DC Be 16 HDMICONN_I2CSDA TXS0102DC 17 GND Ground 18 5V_VDD Power 5V 19 HDMICONN_HPLG 5CSXFC6D Status 20 GND_SHELDS 21 GND_SHELDS Ground 22 GND_SHELDS Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 18 HDMI Display J5 23 GND_SHELDS 2 4 2 SDI The SDI interface on Lark Board is used to implement high resolution video input and output which means that it could be connected to a HD camera or display There are two SMB connectors on the board for connections to SDI devices t
3. for L m L gt 1 L le pow double 2 int L B le 2 for j 0 j lt B 1 j p pow double 2 int m L j ps TWOPI N p w real cos ps w imag sin ps for i j i lt N 1 i i le ip B t xin i Copyright 2014 Embest Technology 74 Lark Board User Manual a Embest Technology 75 xin i real xin i imag xin ip real xin ip imag xin ip change the address nm N 2 ESN for i 1 i lt nm i if i lt j t xin j xin j xin i xin i t k LH while j gt k int main int argc char argv int i 0 int val size_t write_len 0 FILE srcfp FILE resfp double freq if arge 3 exit 1 printf usages s src_file dest_file n argv 0 xin i real xin ip real xin i imag xin ip imag xin ip real t real xin ip imag t imag EE xin ip w Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 76 srcfp fopen argv 1 w if srcfp perror open the source data failed exit 1 resfp fopen argv 2 w if resfp perror open the target file failed exit 1 for i 0 i lt POINT i SAMPLE_FREQ s i imag 0 val int s i real if write_len 1 perror Save input sine wave to file has failed n goto error_out fft s POINT double max int max_
4. keycode is 106 value is 1 keycode is 106 value is 0 Note 4 Pressing Ctrl C can exit this example application The same way can be applied to exit the example applications in the following contents B Pushing and releasing buttons will trigger two input events B This application read events from dev input event0 by default If it is required to test a keypad or mouse the source code of the application should be modified accordingly 4 8 3 PCle Test A PCle to xHCl Host Controller module hereafter called PCle module in short will be used here to test PCle interface Please follow the steps listed below to implement test 1 Connect the PCle module to Lark board and power on the board 2 PuTTY terminal window prints the following identification information of PCle controller Table 4 12 Information of PCle controller pci_bus 0000 00 root bus resource mem Oxc0000000 Oxcfffffff pci_bus 0000 00 root bus resource mem 0xd0000000 0xdfffffff pref pci_bus 0000 00 root bus resource io 0x1000 Oxffff pci_bus 0000 00 No busn resource found for root bus will use bus 00 ff PCI bus0 Fast back to back transfers disabled pci 0000 00 00 0 bridge configuration invalid bus 00 00 reconfiguring PCI bus1 Fast back to back transfers disabled pci 0000 00 00 0 BAR 8 assigned mem Oxc0000000 0xcOOfffff pci 0000 01 00 0 BAR 0 assigned mem Oxc0000000 0xc0001 fff 64bit pci 0000 00
5. Please follow the steps listed below to recompile kernel and RBF file in order to enable the Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 71 support to the module 1 Please execute the following instructions to add cam8000 d supports export CROSS_COMPILE gcc linaro arm linux gnueabihf 4 7 2012 11 20121123_linux b in arm linux gnueabihf make ARCH arm larkboard_lw_defconfig make ARCH arm LOADADDR 0x8000 The zlmage kernel generated after compilation Note The new kernel image does not support PCle frame buffer and ADC function 2 Uncompress camera tar oz2 under Linux APP package to obtain an executable file camera_test and copy it together with soc_system_cv_cam_sdi rbf saved under prebuild sd_card to the FAT partitions of the TF card then rename the latter file to soc_system rbf 3 Connect a CAM8000 D module and a 7 LCD to Lark Board 4 Boot up Lark Board and execute the following instructions in PUTTY terminal window to implement test mount dev mmcblk0p1 mnt e cd mnt camera_test The images captured by the camera module now can be seen on LCD screen Note 4 The default output of the camera module is 7 LCD 800x480 If a 4 3 LCD is used the output resolution set in FPGA project lark_cv_cam_sdi should be changed to 480x272 If VGA or HDMI is used as video output the driver for CH7033 needs to be added to Linux kernel a
6. PCle supports serial P2P transmission under full duplex mode at high speed with high bandwidth A device connected to it has an exclusive channel and does not have to share the bus bandwidth PCle is mainly used for the function including active power management error reports end to end reliable transmission hot plugging and quality of service QoS PCI Express supports two types of interrupts One is the traditional PCI INTx which interrupts host s chip request with signal The other is MSI Message Signaled Interrupt which operates edge trigger and transmits through memory write processing Lark Board has a X4 PCle slot that supports X1 X2 and X4 adapter board Root complex mode is selected including MSI interrupt Avalon MM Cyclone V Hard IP for PCI Express is used to implement PCle function The Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 101 following figure shows PCle IP core interface of which the hip_serial is an input output port for external data pcie_cv_hip_avmm_0 clock conduit conduit interrupt conduit conduit conduit hip seria avalon conduit hip pipe avalon interrupt Crairg altera_pcie_cv_hip_avmm Figure 5 29 PCle IP interface The following figure shows the connections and configurations of PCle in QSYS 2 lark pde goys E 02coe ark 22 rk Be cK ga S R24 ar i File Edit System Generate View Tools Help
7. to a computer with a crossover cable 2 3 I O Voltages The following figure shows the number of valid I O on each I O bank of SoC and their voltages applied Table 2 3 I O and voltages O Bank Usage I O Bank Name PinNo vecio Voltage _ VREF Voltage _ VCCPD Voltage w ANN Sta a pu h Jb E ea ft 3A 3 3V 3B 1 5V A A e QP aa da aw O 1 8V 1 8V 14 14 14 42 49 81 33 17 6 45 34 22 12 14 80 10 uw o 7 3 3V 3 3V x y o el a ess Bo le z sa s o S jo a3 ja as 2 4 Details of Interfaces This section will introduce in detail the constructions principles interface definitions and considerations of use of peripherals on Lark Board so that users may have a deep understanding of the hardware circuitry of the board Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology 13 The peripheral interfaces and key on board chips are shown below User FPGA ADC Dip Switch Controller User Keys Reset tcp SMA x4 ADC Jumper select ADC1 DDR for HPS eMMC Flash Boot Device Select Jumper select ADC2 amp Clock Select HP aca DDR for FPGA Altera SCSXFC6D6F31 Power Switch PCle x4 SMB SDI RX amp TX Ethernet Phy FPGA Configuration Scheme CPLD Power JTAG Connector CH7033 FPGA Extended HDMI Enable disable USB Blaster II Net VGA HPS in JTAG chain USB Hub USB Host USB Phy Extend for EPCQ F
8. xa MRE D p PB Socket FPGA Extended UART HPS Extended switch switch eMMCorTF card socketin Board Figure 1 2 System block diagram Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 1 3 Product Dimensions mm ae a gE D 2638 7 p lt 0 21 g g ig al e mps g a fece fad eiO Din E EB omon Etema oo 20 209 oos 209 209 o0 120 Sor HO 000000 20000000 yy ess rs amn m Li Beg a 5 one ny Homma sex E oa ad a a Ae i gt 4 Cl O car O O a O i eal com lo oo O O E i YW Tl 5 i i amp Figure 1 3 Product Dimensions Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 6 Chapter 2 Introduction to Hardware System This chapter will introduce in detail the structure expansion and peripheral interfaces of Lark Board hardware system 2 1 Overview of CPU Cyclone SX SoC FPGAs is the new generation developed by Altera to satisfy the demand for products that require low power low cost and short time to market while need high speed and stable processing bandwidth It not only has the logic resources of traditional FPGAs but also integrates a dual core ARM Cortex A9 processor system and a high speed serial transceiver hard core making it suited for the areas such
9. 6 IO Control FPGA_H_SMBDAT H12 8A 7 IO Data FPGA_RX_H_PO R2 GXB_L1 8 IO Data FPGA_TX_H_PO P4 GXB_L1 9 IO Data FPGA_RX_H_NO R1 GXB_L1 10 10 Data FPGA_TX_H_NO P3 GXB_L1 11 10 Data FPGA_RX_H_P1 N2 GXB_L2 12 10 Data FPGA_TX_H_P1 M4 GXB_L2 13 10 Data FPGA_RX_H_N1 N1 GXB_L2 14 10 Data FPGA_TX_H_N1 M3 GXB_L2 15 10 Data FPGA_RX_H_P2 L2 GXB_L2 16 10 Data FPGA_TX_H_P2 K4 GXB_L2 17 10 Data FPGA_RX_H_N2 L1 GXB_L2 18 10 Data FPGA_TX_H_N2 K3 GXB_L2 19 10 Data FPGA_RX_H_P3 J2 GXB_L2 20 IO Data FPGA_TX_H_P3 H4 GXB_L2 21 IO Data FPGA_RX_H_N3 J1 GXB_L2 22 lO Data FPGA_TX_H_N3 H3 GXB_L2 23 G Ground GND 24 G Ground GND 25 lO Data FPGA_RX_D_PO K7 8A 26 IO Data FPGA_TX_D_PO C7 8A 27 10 Data FPGA_RX_D_NO K8 8A 28 IO Data FPGA_TX_D_NO B7 8A 29 10 Data FPGA_RX_D_P1 J10 8A 30 IO Data FPGA_TX_D_P1 AQ 8A 31 10 Data FPGA_RX_D_N1 J9 8A 32 lO Data FPGA_TX_D_N1 A8 8A 33 IO Data FPGA_RX_D_P2 F9 8A 34 IO Data FPGA_TX_D_P2 C12 8A 35 IO Data FPGA_RX_D_N2 F8 8A 36 IO Data FPGA_TX_D_N2 B11 8A 37 10 Data FPGA_RX_D_P3 G10 8A 38 IO Data FPGA_TX_D_P3 B13 8A 39 IO Data FPGA_RX_D_N3 F10 8A 40 10 Data FPGA_TX_D_N3 A13 8A Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 39 Chapter 3 Quick Use of Lark Board Lark Board eMMC Flash has been installed with Yocto image by default so that the board could be booting and running immediately This chapter will introduce how to r
10. file In the source code provided by Embest u boot can read RBF file and configure FPGA automatically when system is booting Only the method of making RBF file will be covered Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 50 here Please follow the steps below to learn how to generate a RBF file 1 Open the FPGA project that needs to be converted in Quartus and select Convert Programming Files in the File menu as shown below wll File Edit View Project Assignments Processing Tools Window Help New Ctrl4n system z D Open Ctrl 0 IEX Close Ctrl F4 Entity a New Project Wizard R Open Project Ctri J Save Project Close Project zi Save Ctrl s Save As Save all Ctrl Shift s File Properties Create Update gt sun X IP Components o 4 gt Convert Programming Files hax Page Setup a Customize Q Print Preview Time Print Ctrl P Recent Files gt Recent Projects gt files Exit Alt F4 Figure 4 2 Select Convert Programming Files 2 As shown in the following figure select Raw Binary File rbf in Programming file type drop down menu and Fast Passive Parallel x16 in Fast Passive Parallel x16 drop down menu and then enter a name in File name text box for the RBF file about to be generated iy Convert Progra g File D am p debug cv_soc_devkit_amp_re Specify th
11. 3 0 3 3 EEE TT JTAG based Disabled Disabled Use any valid MSEL pin configuration settings above 2 4 11 Jumpers Figure 2 10 FPGA configurations There are jumpers on Lark Board used for function selection and expansion The following table contains pin definitions of each jumper Table 2 5 Jumpers Jumper Function JP Name Signal Name Function JP7 JTAG_HPS_EN Enable disable HPS in JTAG chain JP5 HPS_WARM_RSTn HPS warm reset JP1 ADC1_MODE Analog CH1 SE Diff mode selection JP3 ADC2_MODE Analog CH2 SE Diff mode selection JP8 FPGA_DCLK JP9 FPGA_AS_DATA1 JP10 FPGA_AS_DATA2 D JP11 FPGA_AS_DATA3 2 4 12 Buttons Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 34 There are 6 buttons on Lark Board S1 button can reset the board The rest of the buttons are used as status input of FPGA or HPS and can be programmed by users The following table contains signal definitions and connections of these buttons Table 2 6 Buttons Button Switch Function Switch Name Signal Name Function S1 PB_COLD_RESETn HPS amp Peripheral Cold Reset S2 USER_FPGA_PBO Bank 3A AH3 function defined by FPGA 3 USER_HPS_PBO Bank 6B T30 function defined by HPS S4 USER_HPS_PB1 Bank 6B U28 function defined by HPS S5 USER_HPS_PB2 Bank 6B T21 function defined by HPS S6 USER_HPS_PB3 Bank 6B U20 function defined
12. B18 GND B19 PCIE_TX_PO 5CSX6D6F B20 PCIE_TX_P1 5CSX6D6F B21 GND B22 GND B23 PCIE_TX_PO 5CSX6D6F TX Differential data and B24 PCIE_TX_P1 5CSX6D6F reference ground B25 GND B26 GND B27 PCIE_TX_PO 5CSX6D6F B28 PCIE_TX_P1 5CSX6D6F B29 GND B30 NC Other B31 PCIE_PRSNT2_X4 5CSX6D6F Status B32 GND Ground 2 4 4 Camera The 30 pin FPC connector J12 on Lark Board is used to support 12 bit input of digital cameras It is currently compatible with Embest s CAM8000 D camera module The following table contains pin definitions of the FPC connector Table 2 10 FPC connector Camera J12 Pin Signal Name Device Signal Type 1 GND Ground 2 CAM_DO 5CSXFC6D Data Copyright 2014 Embest Technology Lark Board User Manual E Embest Technology 21 Camera J12 3 CAM_D1 4 CAM_D2 5 CAM_D3 6 CAM_D4 7 CAM_D5 8 CAM_D6 9 CAM_D7 10 CAM_D8 11 CAM_D9 12 CAM_D10 13 CAM_D11 14 GND Ground 15 PCLK 5CSXFC6D Clock 16 GND Ground 17 CAM_HS 5CSXFC6D SYNC 18 GND Ground 19 CAM_VS 5CSXFC6D SYNC 20 3 3V_CAMERA Power 3 3V 21 CAM_CLK Be CAM CLK 5CSXFC6D Clock 23 GND Ground 24 CAM_FLD 5CSXFC6D 25 CAM_WEN 5CSXFC6D Status 26 CAM_STROBE 5CSXFC6D 27 CAM_SDA 5 CAM SCL TXS0102D 12C 29 GND Ground 30 3 3V_CAMERA_IO Power 3 3V 31 GND E GND Power 2 4 5 ADC amp Pre Amp Since a long ti
13. DDR3_FPGA_DQ25 AJ24 4A IO DDR3_FPGA_DQ26 AK26 4A IO DDR3_FPGA_DQ27 AE23 4A IO DDR3_FPGA_DQ28 AE22 4A IO DDR3_FPGA_DQ29 Group 3 AG25 4A IO DDR3_FPGA_DQ30 AK27 4A IO DDR3_FPGA_DQ31 AJ27 4A IO DDR3_FPGA_DM3 AC20 4A IO DDR3_FPGA_DQS_P3 AD19 4A IO DDR3_FPGA_DQS_N3 2 2 2 eMMC Flash KE4CN2HBA is the eMMC Flash used on Lark Board with a memory space of 4GB 2 2 3 CH7033B CH7033B is a video encoder designed to drive high resolution displays through HDMI DVI YPbPr and VGA interfaces It is suited for mobile Internet devices laptops tablet computers portable e books and smart phones This chip possesses advanced scaling engine that supports 1080P HDTV The integrated frequency shifting engine can provide 60fps under 1080p mode Additionally CH7033B supports SPDIF and IIS digital audio output 2 2 4 AR8035 Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 12 AR8035 is a low power and low cost Ethernet PHY used on Lark Board and integrated with a 10 100 1000Mb transceiver It is a single port tri speed Ethernet PHY and supports MAC TM RGMII interfaces AR8035 is compliant with the IEEE 802 3az Energy Efficiency Ethernet Standard and the Atheros s proprietary SmartEEE standard which allows traditional MAC SoC devices incompatible with 802 3az to function as a complete 802 3az system Lark Board can be connected to a hub with a straight though network cable or connected
14. FPGA User LED A4 8A D31 USER_FPGA_LEDO A3 8A D32 USER_FPGA_LED1 D6 8A D33 USER_FPGA_LED2 C5 8A D34 USER_FPGA_LED3 The following table contains the connections of status LEDs Table 2 9 Status LEDs LED Ref Signal Name LED Function Power LED D64 12V_POWER_GOOD Bright indicate 12V fail D65 5V_POWER_GOOD Bright indicate 5V fail D66 1 1V_POWER_GOOD Bright indicate 1 1V fail D67 1 8V_POWER_GOOD Bright indicate 1 8V fail D68 VTT_POWER_GOOD Bright indicate 0 75V fail D69 1 5V_POWER_GOOD Bright indicate 1 5V fail D70 3 3V_POWER_GOOD Bright indicate 3 3V fail D71 2 5V_POWER_GOOD Bright indicate 2 5V fail D63 POWER_GOOD Bright indicate power OK PCle LED D35 PCIE_LED X1 Bright indicate PCle X1 work D36 PCIE_LED_ X4 Bright indicate PCle X4 work UART LED D15 HPS_UART_RX Blink indicate RX data active Copyright 2014 Embest Technology Lark Board User Manual WP mbesh Embest Technology 36 LED Ref Signal Name LED Function D16 HPS_UART_TX Blink indicate TX data active SDI LED D6 SDI_RX_CDn Bright indicate SDI input active 2 4 15 RTC There is a RTC circuitry on Lark Board When a battery is inserted in BT1 the board can keep a proper clock after power supply is turned off ACR1220 battery and a DS3221 chip are involved in the implementation of RTC circuitry Please refer to schematics and datasheet for its working princ
15. Fixed 15 NC 2 4 8 USB PHY amp HUB To satisfy diverse applications involving USB interfaces Lark Board provides 4 USB ports However there are only 2 USB controllers in HPS thus a PHY and a HUB are added to ensure 4 USB port can work at the same time The USB3320 on Lark Board is used to implement ULPI protocol between PHY and controller The USB2514 is used to expand the ports of PHY The following contents will introduce the implementation of USB in detail USB PHY USB3320 is an on board USB PHY chip which exchange data with the controller of HPS by using ULPI protocol The following table contains pin definitions of ULPI interface Table 2 16 ULPI interface ULPI between USB Controller and PHY Pin Bank Direction Signal Name Signal Type E16 7D IO USB1HS_DO G16 7D IO USB1HS_D1 D16 7D IO USB1HS_D2 D14 7D IO USB1HS_D3 Data A15 7D IO USB1HS_D4 C14 7D IO USB1HS_D5 D15 7D IO USB1HS_D6 M17 7D IO USB1HS_D7 N16 7D IO USB1HS_CLK Clock A14 7D In USB1HS_NXT E14 7D In USB1HS_DIR Control C15 7D Out USB1HS_STP USB HUB Copyright 2014 Embest Technology Lark Board User Manual beck Embest Technology 28 The USB2514 is a HUB chip used to expand more USB ports It expands a differential pair up to 4 pairs to accomplish connections to external USB devices CON1 CON2 are two USB connectors each of which provides two USB ports The following table
16. Lark Board User Manual PF abesk Embest Technology 47 Note Currently Lark Board only uses the cross compiler and root filesysetm of Yocto project While preloader uboot and kernel need to be compiled individually Please refer to 4 4 System Compilation 4 3 2 Installing Altera SoC Development Software The installation packages of Quartus II and SoC EDS are available for both Windows and Linux system The following contents are based on Windows system The operations under Windows are similar to that under Linux system Please visit https www altera com download sw dnl sw index jsp to download and install the latest versions of Quartus and Altera SoC EDS Let s assume the installation directory is Cr 4 3 3 Installing Linux Cross Compiler Optional Cif you have already installed Yocto package you don t have to install another cross compiler again Please ignore this section Please execute the following instructions to install a Linux cross compiler cd wget https launchpad net linaro toolchain binaries trunk 2012 11 download gcc linar o arm linux gnueabihf 4 7 2012 11 20121123_linux tar bz2 tar xjf gec linaro arm linux gnueabihf 4 7 2012 11 20121123 linux tar bz2 The default installation directory of cross compiler is gcc linaro arm linux gnueabihf 4 7 2012 11 20121123_linux 4 4 System Compilation This chapter will introduce how to compile u boot preloader and Linux kernel a
17. Out DDR3_FPGA_A14 AK21 4A Out DDR3_FPGA_RESETn AJ21 4A Out DDR3_FPGA_CKE AEi6 4A Out DDR3_FPGA_ODT AH10 3B Out DDR3_FPGA_BAO AJ11 3B Out DDR3_FPGA_BA1 AKi1 3B Out DDR3_FPGA_BA2 one AH7 3B Out DDR3_FPGA_CASn Ue AH8 3B Out DDR3_FPGA_RASn AB15 3B Out DDR3_FPGA_CSn AJ6 3B Out DDR3_FPGA_WEn AG17 4A In FPGA_RZQ AFi8 4A IO DDR3_FPGA_DQO AE17 4A IO DDR3_FPGA_DQ1 AG16 4A IO DDR3_FPGA_DQ2 AF16 4A IO DDR3_FPGA_DQ3 AH20 4A IO DDR3_FPGA_DQ4 AG21 4A IO DDR3_FPGA_DQ5 ua AJi6 4A IO DDR3_FPGA_DQ6 ARPS AH18 4A IO DDR3_FPGA_DQ7 AH17 4A IO DDR3_FPGA_DM0 V16 4A IO DDR3_FPGA_DQS_PO W16 4A IO DDR3_FPGA_DQS_NO AKi8 4A IO DDR3_FPGA_DQ8 AJ17 4A IO DDR3_FPGA_DQ9 AG18 4A IO DDR3_FPGA_DQ10 AK19 4A IO DDR3_FPGA_DQ11 AG20 4A IO DDR3_FPGA_DQ12 AF19 4A IO DDR3_FPGA_DQ13 la AJ20 4A IO DDR3_FPGA_DQ14 ARAN AH24 4A IO DDR3_FPGA_DQ15 AG23 4A IO DDR3_FPGA_DM1 V17 4A IO DDR3_FPGA_DQS P1 W17 4A IO DDR3_FPGA_DQS_N1 AE19 4A IO DDR3_FPGA_DQ16 Data Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 11 FPGA DDR3 AE18 4A IO DDR3_FPGA_DQ17 Group 2 AG22 4A IO DDR3_FPGA_DQ18 AK22 4A IO DDR3_FPGA_DQ19 AF21 4A IO DDR3_FPGA_DQ20 AF20 4A IO DDR3_FPGA_DQ21 AH23 4A IO DDR3_FPGA_DQ22 AK24 4A IO DDR3_FPGA_DQ23 AK23 4A IO DDR3_FPGA_DM2 Y17 4A IO DDR3_FPGA_DQS_P2 AA18 4A IO DDR3_FPGA_DQS_N2 AF24 4A IO DDR3_FPGA_DQ24 AF23 4A IO
18. Please follow the steps listed below to write Debian into a TF Card 1 Prepare a TF card with memory space bigger than 4G including 4G 2 Execute the following instruction to repartition the TF card sudo fdisk dev sdb repartition the TF card 3 Press p to display the partitions and then press d to delete all partitions 4 Press Enter key after each one of character strings n p 3 2048 1024K t 3a2 do not type commas is typed The same operations are required when typing n p 24096 3G t 283 and n p 1 lt enter gt lt enter gt t 1 b each lt enter gt means press Enter key for one time and then execute the following instructions w save changes and quit sudo mkdosfs dev sdb1 set sdb1 to FAT format sudo mkfs t ext3 dev sdb2 set sdb2 to EXT3 format sudo tar vxjf debian rootfs tar bz2 cd debian mount dev sdb2 mnt sd sudo cp rf mnt sd Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 56 Note L The use of fdisk could be different in different Linux distributions Despite that the first partition must be bigger than 20M in FAT the second one should be a Linux partition bigger than 2G and the third one should be bigger than 1M in RAW 5 6 7 Execute the following instructions to write preloader bin saved under prebuild sd_card into the TF card sudo dd if preloader bin of
19. R28 7A IO DDR3_HPS_DM2 R19 7A IO DDR3_HPS_DQS_P2 R18 7A IO DDR3_HPS_DQS_N2 P24 7A IO DDR3_HPS_DQ24 P25 7A IO DDR3_HPS_DQ25 T29 7A IO DDR3_HPS_DQ26 T28 7A IO DDR3_HPS_DQ27 R27 7A IO DDR3_HPS_DQ28 R26 7A IO DDR3_HPS_DQ29 R Group 3 V30 7A IO DDR3_HPS_DQ30 W29 7A IO DDR3_HPS_DQ31 W30 7A IO DDR3_HPS_DM3 R22 7A IO DDR3_HPS_DQS_P3 R21 7A IO DDR3_HPS_DQS_N3 FPGA DDR3 FPGA has the similar HMC which also enjoys an extended 1GB dynamic RAM the hardware design of FPGA DDR3 is almost the same as HPS DDR3 The following table contains interface definition and signal connection of FPGA DDR3 Table 2 2 FPGA DDR3 FPGA DDR3 Pin Bank Direction Signal Name Signal Type AA14 3B Out DDR3_FPGA_CLK_P ince AA15 3B Out DDR3_FPGA_CLK_N AJ14 3B Out DDR3_FPGA_AO AK14 3B Out DDR3_FPGA_A1 AH12 3B Out DDR3_FPGA_A2 AJ12 3B Out DDR3_FPGA_A3 Address AG15 3B Out DDR3_FPGA_A4 AH15 3B Out DDR3_FPGA_A5 AK12 3B Out DDR3_FPGA_A6 Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 10 FPGA DDR3 AK13 3B Out DDR3_FPGA_A7 AH13 3B Out DDR3_FPGA_A8 AH14 3B Out DDR3_FPGA_AQ AJ9 3B Out DDR3_FPGA_A10 AK9 3B Out DDR3_FPGA_A11 AK7 3B Out DDR3_FPGA_A12 AK8 3B Out DDR3_FPGA_A13 AGi2 3B
20. a Oe Type ID Message Figure 5 1 Open Programmer 5 Connect a CAM8000 D a 7 LCD a U Blaster cable either on board USB Blaster Il or an external USB Blaster II can be selected and a 19V power adapter to the board After board is powered on the information marked in a red box as shown in the following figure indicates the connection is OK Programmer E O2code File Edit View Processing Tools Window Help 5 Search altera com Zi Hardware Setup Lark Board Use 1 Mode TAG oes Cid Enable real time ISP to allow background programming for MAX II and MAX V devices File Device Checksum Usercode Program Verify Blank Examine Security Erdl re Chek d Stop output_files lark sof SCSXFC6D6F31I7ES 0C964BC7 0C9648C7 v I h save Fie 23 Add Device T up P Down Figure 5 2 Connection OK 6 Click Auto Detect in the left part of the window and select SCSXFCEDEES as shown below Copyright 2014 Embest Technology Lark Board User Manual not Embest Technology 82 ah aha W Programmer 02code lark v2 Bak bakJeam_sdi_lcd_ok lark lark output files lark cdf o S x e 5 3 Sei Ep Hardware Setups Lark Board USB 1 Mode ora E Enable real time ISP to allow background programming for MAX II and MAX V devices W Select Device File _ Verify Blank Exa
21. a complete chain of data flow Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 97 SDI RX IP interface SDI TX IP interface SDI to HDMI module Figure 5 24 Complete data flow The following configurations are required when generating SDI IP core in MegaWizard Plug In Manager Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology MegaWizard Plug In Manager SDI Sa a_i 98 SS Receiver Transmitter Options Device Selection Currently selected device family Cyclone V v Video Standard SD SDI 270Mbps HD SDI Supports 1 485 Gbps and 1 4835 Gbps HD SDI 3G HD SDI dual ink Dual standard Triple standard Interface Settings Bidirectional Receiver Transmitter Figure 5 25 Configurations of SDI IP core 1 amp ry 4 MegaWizardPlug InManager SDI 0O e e ate oscar er Transmi Transceiver and Protocol Generate transceiver and protocol blocks Generate transceiver only Generate protocol block only r Transceiver Type Use soft logic for transceiver Starting Channel Number Starting channel number 0 Transceiver Settings Use PLL reconfiguration for transceiver dynamic Enable TX PLL select for 1 1 000 and 1 1 00 001 data rate reconfi Figure 5 26 Configuration
22. as industrial control wireless and wired communication medical military and automotive electronics The SoC used on Lark Board is the most sophisticated FPGA chip in SX family 5CSXFC6D6F31 in FBGA 896 package It has three core resources FPGA up to 110K logic cells LE 5570 M10K memory blocks 621 MLABs 112 variable precision DSP blocks 224 18x18 multipliers 6 PLLs 288 lOs 72 72 LVDS transceiver and a memory controller HPS a dual core ARM Cortex A9 MPCore processor a memory controller DDR3 3 PLLs and 181 general IOs as well as a rich set of peripheral interfaces such as UART 12C USB SPI GPIO and EMAC Serdes 9 3Gbps transceivers and2 PCle hard IPs 2 2 Introduction to Peripheral Chips 2 2 1 DDR3 5CSXFC6D6F SoC has a hard memory controller separately for FPGA and HPS with a purpose to extend more external dynamic memory spaces Accordingly Lark Board Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 7 integrates two DDR3 SDRAM chips for FPGA and another two chips for HPS giving each of them 1GB external memory space HPS DDR3 The HMC of HPS is an effective expansion for the access space of ARM Cortex A9 processor It receives events come from AMBA AXI bus and Avalon MM bus and converts them into proper SDRAM instructions to manage the accesses to SDRAM As for hardware circuitry design there a 73 signal lines i
23. by HPS 2 4 13 UART J24 and J25 are two connectors in different types specially provided on Lark Board the connectors cannot be used simultaneously They are used to connect 3 3V serial debuggers for example the COM8000 DB9 to TTL or UART 8000U USB to TTL supplied by Embest Users can use Dupont wires to connect a RS232 to 3 3V level serial converter to conduct debugging The following table contains pin definitions of J24 and J25 Table 2 7 UART Pin Signal Name Device Signal Type J24 1 3 3V_VDD Power 3 3V 2 HPS_UARTO_TX 5CSX6D6F UART 3 HPS_UARTO_RX 5CSX6D6F 4 GND Ground J25 1 3 3V_VDD Power 3 3V 2 HPS _UARTO_TX 5CSX6D6F UART 3 HPS _UARTO_RX 5CSX6D6F 4 GND Ground 5 GND Ground Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 2 4 14 LED 35 The LEDs on Lark Board can be used for programming by users and indicating board status The users LEDs include 4 HPS LEDs 4 FPGA LEDs and 2 PCle LEDs The status LEDs are used to monitor or indicate operating state of circuitry and include 7 power indicators 2 UART LEDs 2 PCle LEDs and 1 SDI LED The following table contains the I O connections of HPS FPGA user LEDs Table 2 8 User LEDs FPGA Pin Bank LED Ref Signal Name HPS User LED A24 7A D27 USER_HPS_LEDO G21 7A D28 USER_HPS_LED1 E17 7A D29 USER_HPS_LED2 G22 7A D30 USER_HPS_LED3
24. com literature ug ug vip odf performance performance to learn more about these settings The following figure shows the data flowing out from frame buffer miiia miin niiin Figure 4 10 Data flow from Frame Buffer The display interface is controlled by FPGA In detail the input and output control are controlled respectively by Altera s Frame Reader and Clocked Video Output IP The data stream from FPGA is sent to two destinations one is LCD interface and the other is CH7033 a video encoder that converts data into VGA and HDMI signal The following table lists the addresses of reference files Table 4 9 Reference files for Frame Buffer linux 3 10 ltsi drivers video larkboardfb c Reference Files linux 3 10 Itsi include linux fb h linux 3 10 ltsi drivers video fomem c 4 6 3 ADC Driver The following figure shows how the ADC AD9628 works Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology 64 control result data result data Figure 4 11 ADC working principle The ADC AD9628 is initialized by ADC driver of Linux which emulates SPI time sequence by controlling the I O ports of FPGA to implement ADC initialization The default configurations of ADC includes 105MHz working frequency enabled dual channel 1 8V CMOS data output and 12 bit conversion results FPGA reads 1024 conversion results on the dual channels each time and write all of them into S
25. contains pin definitions of USB interface Table 2 17 USB interface USB Connector CON1 CON2 Pin Signal Name Device Signal Type 1 VBUS1_CN 2 DN1 USB2514 USB1 3 DP1 USB2514 4 GND 5 VBUS2_CN 6 DN2 USB2514 USB2 7 DP2 USB2514 8 GND 9 GND_SHIELDS 10 GND_SHIELDS FIX 11 GND_SHIELDS 12 GND_SHIELDS 2 4 9 USB Blaster amp JTAG JTAG is used to download firmware and obtain debugging information during FPGA development It is very important in product development stage The debugging function mainly depends on the four signals TCK TMS TDI and TDO The standard debugging interface for Altera FPGA is a 5Px2 connector used to connect debuggers such as USB Blaster There is an on board USB Blaster II debugger on Lark Board enabling the powerful debugging function of USB Blaster II by using just a mini USB cable without the need to purchase a separate debugger Moreover a separate USB Blaster could be supported by Lark Board by using an additional 5Px2 connector On Board USB Blaster Il The on board USB Blaster II is implemented with MAX II chip EPM570GF100 and a controller CY7C68013A The IP authorized by Altera needs to be programmed into MAX II Embest has obtained that authorization on Lark Board Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 29 The CONS on the board is used to connect to a computer install
26. dev sdx3 bs 64k seek 0 sudo sync Copy zlmage socfpga_cyclone5 dtb soc_system_cv_vga_pcie_adc rbf and u boot img under prebuild sd_card to the first partition of TF card and rename soc_system_cv_vga_pcie_adc rbf to soc_system rbf Insert the TF card onto Lard Board and power on the board After Lark Board boots up execute the following instructions in PuTTY terminal window or other terminal window to display Debian desktop on the screen root localhost startx amp 4 5 2 Updating Images in eMMC Flash There are three methods to update images in eMMC Flash writing the whole system into eMMC Flash under Linux system writing part of images into eMMC Flash under Linux system and writing part of images into eMMC Flash under u boot mode Note Because there is only one TF SD controller in HPS of Cyclone V SoC the TF card and eMMC need to share one channel which means TF card and eMMC Flash cannot be working simultaneously Writing Whole System into eMMC Flash under Linux A TF card that Linux system can boot from and a flash drive are required before Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 57 system images can be written into the card if your TF card has not been written with a Linux system please use the first method in 4 5 1 Writing Linux Images into TF Card to build partitions in TF card Please follow the steps listed below to upda
27. gt i 7 SCSXFCEDEFSIES SOCVHPS TDO L J Figure 5 6 Download completed 5 2 2 Elipse Debugging Please ensure that sof file has been downloaded to FPGA with the Programmer of Quartus or there might be errors when using Eclipse All the following operations are carried out in Quartus II Copyright 2014 Embest Technology Lark Board User Manual bot Embest Technology 1 Creation of an Eclipse project 84 Please refer to the operations illustrated in the following figures OGd d amp a er kas Project Nevagator D gt Cydore V SCSKFCEDGF SUITES 0 gt tok I a la T a By rersrcry Bees F oopus e Tass Flow Compiston Task sP ome gt Analyse b Synthese gt Fitter Pace S Raute 4 gt ascender Generate programming fies ga gt TmeQuest Trg Analyse gt EDA Netist varter amp Program Deuce Open Programmer MOA Wt 7 lt a F ltype ID Message WB Nios I sde_cmos hello_worlde Eclips J Sgnaitap Ti Loge Analyzer Run Smdaton Tool peo Tas Tap In System Memory Content Edtor Loge anayam Interface Editor In System Sources and Probes Editor Sgrabrobe Prs Pregame STAG Chain Debugger System Corese Megatiaard Pug in Manager Nos I Software Bud Toots for Edie ama Td Sots Customize Optors License Setup Iratall Devices Figure 5 7 Fie Edt Source Refactor Navigate Search Run Project Nios Il Window He
28. mre 6 2 2 2 12 Gell Fc be greene arene Aer nett Ar rtar eae enr rr ver recy reer trey fray tee heer er arr 11 2 2 3 GE 70SSBa tee heer eesaiteeeeeteasats 11 2 2 4 AR8035 E nee 11 2 3 Mele cc 12 2 4 Details of Intertaces 4 2c0eneiaen denn nneaiiinandd eevee 12 2 4 1 Ba gg 29 oee errr terre er 13 2 4 2 SDI S e 18 2 4 3 PCle e e AA a 18 2 4 4 02 gt ae ee a ee ROT RN E EE eT 20 2 4 5 i el AMD a ee dec ec we eee cee eee 21 2 4 6 Gigabit Ethernet erner eee Cee n ne ene eee Se 24 2 4 7 eMMC amp TF Card sc 25 2 4 8 USB PHY amp HUB at secerrccchetcnatadetnnetedehanatedacanatedataontedetonntadeiennaalotentens 27 2 4 9 USB Blaster amp JTAG aatos eee 28 2 4 10 DIP S suse seeveteestercudes teeters teseeesesteesuccssecseses 30 2 4 11 UUM IS eae cece 33 2 4 12 Buttons sanii na A a a A 33 2 4 13 VARI ea aaa E 34 2 4 14 LED err ERC errr ere errer er Terr erer Teer ere tererert Cer errere 35 2 4 15 MEG eene assent satcdatesatesetccsts ascctetstepatatetesstetteacesa 36 2 4 16 Extension Interfaces ecceeeseeeseeeeeneeeeeeeeeneeeeeaeeeeseeetseeeesaeeeas 36 Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology iv Chapter 3 Chapter 4 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 Quick Use of Lark Board aiciccisincicenccnisiccsnncsninnnwvsenceuniinncwnosnuannunvennencnsniue 39 NIX eae EEE EEE EE EE EEEE 44 Linux System Structure of Lark BOard ccecccecssceeeseeeeneeeeeeeeesseeessneees
29. of CAM8000 D The former one is field synchronization signal and the latter one is the data valid signal for line input This is slightly different from VESA standard so signal standards needs to be complied with each other before the interface conversion can be accomplished The video data of progressive scanning is controlled by line n and field synchronization signals The following figure shows the signal time sequence Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology 89 Horizontal Sync FO Active Picture Vertical Sync Figure 5 14 Signal time sequence 5 3 2 Output of Camera Video This section will show you how the video data flows from camera into FPGA and is finally displayed The following figure illustrates the whole process from input to output of video data Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 90 CAMERA YUV422 video data Clocked Video Input Avalon ST VGA HDMI YUV422 video data Color Plane Sequencer VGA HDMI data Avalon ST Paralell YUV422 1 0 CH7033Bi video data i LCD Chrome Resampler Avalon ST RGB444 video GB444 video Paralell YUV444 data data lt _ wideo data CSC Clocked Video Output Avalon ST PAvalon ST Paralell RGB44
30. other is Debian system The following contents will introduce how to write these systems into a TF card Writing Linux Images into TF Card There are three methods to write Linux system into a TF card The first is using the pre built image files provided by Embest to replace all the existing files the second is using image files compiled by yourself to replace all the existing files the third is using image files compiled by yourself to replace some of the existing files e Using the pre built image files provided by Embest to replace all the existing files 1 Please visit http Awww embest tech cn product pinggubanxilie lark board evaluation bo ard html to download the pre build Linux image provided by Embest 2 Uncompress the file lark_board_SD tar oz2 under prebuild sd_card to generate lark_board_SD img 3 Download the tool Win32Disklmager from http sourceforge net projects win32diskimager and install it Copyright 2014 Embest Technology Lark Board User Manual PF abosk Embest Technology 53 4 Run Win32Disklmager and click in the Image File block to select files that need to be write into TF card Click Device drop down menu to select the drive of the TF card and click Write at the bottom of the window to start writing Ga y Win32 Disk Imager oa Image File Device SLAE MDS Hash Progress Cancel Read Write Exit Waiting for a task Figure 4 6 Win32 Disk Imager 5 After images ar
31. stations and that this product accept harmful interference For evaluation only not FCC approved for resale Copyright 2014 Embest Technology Lark Board User Manual E Embest Technology ii European Union Notice This kit is a custom built evaluation kit destined for professionals to be used solely at research and development facilities for such purposes Revision History Version Date Description 1 0 2014 6 30 Original Version 1 1 2014 8 30 Revision Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology iii Table of Contents Chapter 1 Product Overvi W sicicscscsssssscsascsisactacssacsacastanataancaasnsanteaateasanananeaaceaaensaanenaceace 1 1 1 Brief Introduction 0 eee ceee cence tenet eeeaeeeeaeeeteaeeeeaeeeeaeeeseaeeeeaeeseaeeeseaeeenaaes 1 1 1 1 Packing Listi erea 1 1 1 2 Product Features eeeeeeeeeesneeeeeeeeeeneeeesaeeeeseeeesaeeessaeesseeessneeeeaes 2 1 2 System Block Diagram ccccccccccescceeeeeeeseceeeeneeecseeeeeeeeesseeeesaeessneeeseneeeseaes 4 1 3 Product Dimensions Mm cccccceeeeeeeeeeeeeeeeeeeeeeeeeeseeeeeeeeeeaeeeeeeeeeeeeeaas 5 Chapter 2 Introduction to Hardware System ccsesssesenseesseenseeeseeesseenseeeneeeseeees 6 241 OVENMIGWDICPU 112 0208 nknennnnennnakeknnnnknbnnnnuknannnd 6 2 2 Introduction to Peripheral Chips 2 ccnsesnsee 6 2 2 1 DDRS eprererererer ee Pree ere oe orc ein rereccee ene er ec ere ee rer eee nee eee
32. 00 0 PCI bridge to bus 01 pci 0000 00 00 0 bridge window mem 0xc0000000 0xcOOfffff PCI enabling device 0000 00 00 0 0140 gt 0143 3 The identification information of the PCle module is printed in PuTTY terminal window as shown below Table 4 13 Information of PCle module Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 69 xhci_hcd 0000 01 00 0 xHCI Host Controller xhci_hcd 0000 01 00 0 new USB bus registered assigned bus number 3 4 The identification information of the flash drive on PCle module is printed in 4 8 4 1 2 Copyright 2014 Embest Technology PuTTY terminal window as shown below a 8G flash drive has already been inserted to the module Table 4 14 Information of flash drive usb storage 2 1 1 0 USB Mass Storage device detected scsiO usb storage 2 1 1 0 scsi 0 0 0 0 Direct Access Kingston DataTraveler 2 0 1 00 PQ 0 ANSI 4 sd 0 0 0 0 sda 15131636 512 byte logical blocks 7 74 GB 7 21 GiB sd 0 0 0 0 sda Write Protect is off sd 0 0 0 0 sda Write cache disabled read cache enabled doesn t support DPO or FUA sda sda1 sd 0 0 0 0 sda Attached SCSI removable disk Network Interface Test Testing network interface under u boot Please execute the following instructions under u boot to implement test a TFTP server built on a PC is required the IP and MAC addresses below should be mo
33. 1 IO QSPI QSPI_I01 H18 7B 22 IO GPIO HPS_GPIO49 B25 7A 23 IO QSPI QSPI_lO2 A19 7B 24 IO GPIO HPS_GPIO50 C25 7A 25 IO QSPI QSPI_IO3 E19 7B 26 IO GPIO HPS_GPIO53 A24 7A 27 IN QSPI QSPI_SSO A18 7B 28 IO GPIO HPS_GPIO54 G21 7A 29 IN QSPI QSPI_CLK D19 7B 30 lO GPIO HPS_GPIO44 E17 7C 31 G Ground GND 32 IO GPIO HPS_GPIO62 G22 7A 33 IN 12C1 HPS_12C1_SCL H23 7A 34 G Ground GND 35 IN SPI HPS_SPIMO_MOSI C22 7A 36 IO 12C1 HPS_12C1_SDA A25 7A 37 IN SPI HPS_SPIMO_CLK A23 7A 38 OUT SPI HPS_SPIMO_MISO B23 7A 39 IN SPI HPS_SPIMO_CSO0n H20 7A 40 IO GPIO HPS_GPIO61 B22 7A FPGA Extension J19 is the I O extension interface for FPGA and transceiver It uses the same type of connector to connect Bank 8A GXB_L1 GXB_L2 The GXB can use the hard IP controller of FPGA such as PCle the I O of 8A works on 3 3V level and can use various resources of FPGA IO such as PLL and M4K The following table contains pin definition of J19 Table 2 11 FPGA extension interface Copyright 2014 Embest Technology Lark Board User Manual beck Embest Technology 38 FPGA Extend 40Pin IDC Connector J18 Pin Direction Signal Type Signal Name Pin_FPGA Bank FPGA 1 P Power 5V_EXP2 2 G Ground GND 3 IN Control nPERSTLO AJ1 3A 4 IN Control FPGA_H_SMBCLK E7 8A 5 G Ground GND
34. 1000M Ethernet linux 3 10 lItsi drivers net ethernet stm Drivers NET driver icro stmmac stmmac_platform c i linux 3 10 lItsi drivers spi spi cadence QSPI QSPI driver qspi c Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 61 linux 3 10 ltsi drivers spi spi dw mmio SPI SPI driver C linux 3 10 ltsi drivers i2c busses i2c d 12C 12C driver esignware platdrv c VGA HDMI output control PIDA CH7033 linux 3 10 ltsi drivers video ch7033 c driver Frame linux 3 10 ltsi drivers video larkboardf Kernel Frame Buffer driver Buffer b c linux 3 10 lItsi drivers mmc host dw_m MMC SD MMC SD controller driver mc socfpga c linux 3 10 ltsi drivers usb dwc2 platfo USB USB controller driver rm c linux 3 10 ltsi drivers pci nost pci alte PCle Altera PCle driver ra c linux 3 10 ltsi drivers input keyboard GPIO Key GPIO keypad driver gpio_keys_polled c GPIO GPIO driver linux 3 10 lItsi drivers gpio gpio dw c LED User LED driver linux 3 10 ltsi drivers leds leds gpio c ADC AD9628 driver linux 3 10 ltsi drivers char adc9628 c 4 6 1 MMC SD Driver The MMC SD card drivers under Linux system typically include four parts SD MMC core mmc_block mmc_queue and SD MMC driver MMC SD core implements the structure independent core code in operations related to MMC SD mmc_block implements driver structure us
35. 4 RGB444 video video data data Frame Buffer Frame Reader Avalon MM write Avalon MM read RGB444 video dat ee ae RGB444 video data DDR3 SDRAM Figure 5 15 Input and output of video data The figure above shows that the input data is converted from sequential YUV422 format into parallel YUV422 data then converted into parallel YUV444 data and finally converted into parallel RGB444 data that is aligned with LCD time sequence During the data conversion importance should be attached to the sequence of two adjacent 8 bit data because the sequence of chrominance and brightness signals will influence the display effect After the data is converted into RGB format it goes into frame buffer and then the DDR3 memory of FPGA Frame reader reads the data at the corresponding address and sends it to an appropriate display The main formats of video data are shown below Each format has been given a name Copyright 2014 Embest Technology Lark Board User Manual E Embest Technology 91 different from others B G R For RGB sequential data For RGB parallel data G For 4 4 4 sequential data For 4 2 2 sequential data Y E a For 4 2 0 sequential data For 4 2 2 parallel data y For 4 4 4 parallel data Cr For 4 2 0 parallel data Cb Figure 5 16 Video data formats The connections between control signal and data signal in QSYS design file are shown below For detailed configurations please refe
36. 5CSXFC6D 21 DSS_D18 5CSXFC6D 22 DSS_D19 5CSXFC6D a 23 DSS_D20 5CSXFC6D ia 24 DSS_D21 5CSXFC6D 25 DSS_D22 5CSXFC6D Copyright 2014 Embest Technology Lark Board User Manual beck Embest Technology 16 LCD Display J4 26 DSS_D23 5CSXFC6D 27 GND Ground 28 DSS_ACBIAS 5CSXFC6D 29 DSS_HSYNC 5CSXFC6D a 30 DSS_VSYNC 5CSXFC6D 31 GND Ground 32 DSS_CLK 5CSXFC6D Clock 33 GND Ground 34 TOUCH_X1 TSC2046 35 TOUCH_X1 TSC2046 Touch 36 TOUCH_X1 TSC2046 Panel 37 TOUCH_X1 TSC2046 38 SPIO_FPGA_CLK 5CSXFC6D 39 SPIO_FPGA_MOSI 5CSXFC6D 40 SPIO_FPGA_MISO 5CSXFC6D i 41 SPIO_FPGA_CSn1 5CSXFC6D 42 LCD_I2C1_SCL 5CSXFC6D 43 LCD_l2C1_SDA 5CSXFC6D S 44 GND Ground 45 3 3V_LCD_VDD 46 3 3V_LCD_VDD en 47 5V_LCD_VDD 48 5V_LCD_VDD a 49 RESET _HPS GLOBELn S1 Reset 50 LCD_PWM 5CSXFC6D Control 51 GND chp Ground VGA The VGA interface CN1 is realized by using a standard D SUB 15 pin connector The following table contains pin definitions of CN1 Table 2 6 VGA interface VGA Display CN1 Pin Signal Name Device Signal Type 1 VGA_REG 2 VGA_GRN CH7033B Data 3 VGA_BLU 4 NC Other 5 GND 7 CNG Ground Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 17
37. A10 C30 6A_ Out DDR3_HPS_A11 B30 6A Out DDR3_HPS_A12 C29 6A_ Out DDR3_HPS_A13 H25 6A Out DDR3_HPS_A14 P30 6A Out DDR3_HPS_RESETn L29 6A Out DDR3_HPS_CKE H28 6A Out DDR3_HPS_ODT E29 6A Out DDR3_HPS_BAO J24 6A Out DDR3_HPS_BA1 J23 6A Out DDR3_HPS_BA2 REE E27 6A Out DDR3_HPS_CASn en D30 6A Out DDR3_HPS_RASn H24 6A Out DDR3_HPS_CSn C28 6A Out DDR3_HPS_WEn D27 6A In HPS_RZQ K23 6A 10 DDR3_HPS_DQo K22 6A 10 DDR3_HPS_DQ1 H30 6A 10 DDR3_HPS_DQ2 G28 6A_ 10 DDR3_HPS_DQ3 L25 6A 10 DDR3_HPS_DQ4 L24 6A 10 DDR3_HPS_DQ5 a J30 6A 10 DDR3_HPS_DQ6 poe J29 6A 10 DDR3_HPS_DQ7 K28 6A 10 DDR3_HPS_DMOo N18 6A 10 DDR3_HPS _DQS_PO M19 6A_ 10 DDR3_HPS_DQS_NO k26 6A 10 DDR3_HPS_DQ8 L26 6A 10 DDR3_HPS_DQ9 K29 6A 10 DDR3_HPS_DQ10 K27 6A 10 DDR3_HPS_DQ11 M26 6A IO DDR3_HPS _DQ12 M27 6A_ 10 DDR3_HPS _DQ13 ae L23 6A 10 DDR3_HPS_DQ14 rene M30 6a IO DDR3_HPS_DQ15 M28 6A IO DDR3_HPS_DM1 N25 6A_ 10 DDR3_HPS_DQS P1 N24 6A 10 DDR3_HPS_DQS_N1 U26 7A 10 DDR3_HPS DQ16 Data T26 7A 10 DDR3_HPS_DQ17 Group 2 Copyright 2014 Embest Technology Lark Board User Manual Pe mbesk Embest Technology 9 HPS DDR3 N29 7A IO DDR3_HPS_DQ18 N28 7A IO DDR3_HPS_DQ19 P26 7A IO DDR3_HPS_DQ20 P27 7A IO DDR3_HPS_DQ21 N27 7A IO DDR3_HPS_DQ22 R29 7A IO DDR3_HPS_DQ23
38. AB25 5A In ADC_Dn4 W21 5A In ADC_Dp5 W22 5A In ADC_Dn5 Differential AD26 5A In ADC_Dp6 Data AC27 5A In ADC_Dn6 AA13 3B In ADC_Dp7 AB13 3B In ADC_Dn7 Y23 5A In ADC_Dp8 Y24 5A In ADC_Dn8 AD25 5A In ADC_Dp9 AC25 5A In ADC_Dn9 AF11 3B In ADC_Dp10 AG11 3B In ADC_Dn10 AB22 5A In ADC_Dp11 AB23 5A In ADC_Dn11 W20 5A Out ADC_ORp Differential Y21 5A Out ADC_ORn Status Copyright 2014 Embest Technology Lark Board User Manual ne Embest Technology 24 Interface between ADC amp FPGA AB30 5B In ADC_DCOp AA30 5B In ADC_DCOn AE13 3B In ADC_DOB AK4 3B In ADC_D1B Single Ended AJ4 3B In ADC_D2B Data AK3 3B In ADC_D3B AF30 5A Out FPGA_ADC_OEB AD24 4A Out FPGA_ADC_SPICSn AE24 4A Out FPGA_ADC_SPICLK a AC23 4A Out FPGA_ADC_SPIMOSI 2 4 6 Gigabit Ethernet Lark Board can provide a relatively high network performance of gigabit Ethernet The Ethernet is implemented by utilizing part of the EMAC controller integrated in HPS The AR8035 is added to realize connections between PHY and EMAC The RJ 45 interface is named as J14 to provide connection to network devices RGMII RGMII is the interfacing protocol applied on the connection between EMAC and AR8035 PHY It uses a 4 bit data port and operates at 125MHz It supports data transmission at both rising edge and fall edge providing a transmission rate up to 1000Mbps The following table contains pin definitions of RG
39. D5 8A Out DSS_D5 C4 8A Out DSS_D6 B1 8A Out DSS_D7 D7 8A Out DSS_D8 E8 8A Out DSS_D9 E2 8A Out DSS_D10 Data D2 8A Out DSS_D11 C2 8A Out DSS_D12 E3 8A Out DSS_D13 E6 8A Out DSS_D14 F6 8A Out DSS_D15 G12 8A Out DSS_D16 G11 8A Out DSS_D17 G7 8A Out DSS_D18 H8 8A Out DSS_D19 G8 8A Out DSS_D20 Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 15 Display Data Output J7 8A Out DSS_D21 H7 8A Out DSS_D22 H14 8A Out DSS_D23 e LCD The LCD interface J4 of Lark Board is implemented with a 50 pin FPC connector which connects LCD module to the board Currently LCD8000 43T 4 3 inch LCD8000 70T 7 inch and VGA8000 conversion module are supported by the board The following table contains pin definitions of LCD interface including the fixed pins of the connector Table 2 5 LCD interface LCD Display J4 Pin Signal Name Device Signal Type 1 DSS_DO 5CSXFC6D 2 DSS_D1 5CSXFC6D 3 DSS_D2 5CSXFC6D 4 DSS_D3 5CSXFC6D Data 5 DSS_D4 5CSXFC6D Blue 6 DSS_D5 5CSXFC6D 7 DSS_D6 5CSXFC6D 8 DSS_D7 5CSXFC6D 9 GND Ground 10 DSS_D8 5CSXFC6D 11 DSS_D9 5CSXFC6D 12 DSS_D10 5CSXFC6D 13 DSS_D11 5CSXFC6D Data 14 DSS_D12 5CSXFC6D Green 15 DSS_D13 5CSXFC6D 16 DSS_D14 5CSXFC6D 17 DSS_D15 5CSXFC6D 18 GND Ground 19 DSS_D16 5CSXFC6D 20 DSS_D17
40. Lark Board OE en sav User Manual Version 1 1 Aug 30 2014 PF abesk Embest Technology i Copyright Statement Lark Board and its related intellectual property are owned by Shenzhen Embest Technology Co Ltd Shenzhen Embest Technology has the copyright of this document and reserves all rights Any part of the document should not be modified distributed or duplicated in any approach and form with the written permission issued by Embest Technology Co Ltd Disclaimer Shenzhen Embest Technology does not take warranty of any kind either expressed or implied as to the program source code software and documents in the CD DVD ROMs provided along with the products and including but not limited to warranties of fitness for a particular purpose The entire risk as to the quality or performance of the program is with the user of products FCC NOTICE This kit is designed to allow 1 Product developers to evaluate electronic components circuitry or software associated with the kit to determine whether to incorporate such items in a finished product and 2 Software developers to write software applications for use with the end product This kit is not a finished product and when assembled may not be resold or otherwise marketed unless all required FCC equipment authorizations are first obtained Operation is subject to the condition that this product not cause harmful interference to licensed radio
41. M data width 64 bit X Avalon MM address width pee Peripheral mode Requester Completer E Single DW Completer V Control register access CRA Avalon MM slave port Enable multiple MSI MSI X support Auto enable PCIe interrupt enabled at power on Enable HIP Status Bus Enable HIP Status Extension Bus F Avalon to PCIe Address Translation Settings Number of address pages 2 Size of address pages 256 MBytes 28 bits Figure 5 32 PCle configurations in QSYS 2 According to the configurations shown above HPS is connected to IP interface and extend 4 sets of PCle transceiving ports to the top layer of FPGA through hip_serial and Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 103 then to the PCle slot on Lark Board to implement PCle communication Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 104 Technical Support and Warranty Technical Support J Embest Technology provides its product with one year free technical support including Providing software and hardware resources related to the embedded products of Embest Technology Helping customers properly compile and run the source code provided by Embest Technology Providing technical support service if the embedded hardware products do not function properly under the circumstances that customers operate according
42. MII interface on Lark Board Table 2 12 Interface between HPS MAC and PHY Interface between HPS MAC amp PHY Pin Bank Direction Signal Name Signal Type H19 7B Out MIl1_TX_CLK A20 7B Out MIl1_TX_EN F20 7B Out MIl1_TXDO J19 7B Out MIl1_TXD1 1 F21 7B Out MIl1_TXD2 F19 7B Out MIl1_TXD3 G20 7B In MIl1_RX_CLK K17 7B In MIl1_RX_DV Rx A21 7B In Mll1_RXDO Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 25 Interface between HPS MAC amp PHY B20 7B In MII1_RXD1 B18 7B In MII1_RXD2 D21 7B In MIl1_RXD3 B21 7B Out MII _MDC E21 7B IO MII_MDIO Manage C19 7B In MII_INT RJ 45 The following table contains pin definitions of RJ 45 J14 Ethernet interface Table 2 13 Ethernet interface RJ45 Ethernet J14 Pin Signal Name Device Signal Type 1 MIIA_TRPO 2 MIIA_TRNO AR8035 Data 3 MIIA_TRP1 4 MilA_TRN1 5 NC Shield 6 NC 7 MIIA_TRP2 8 MIIA_TRN2 AR8035 Data 9 MIIA_TRP3 10 MIIA_TRN3 11 MIIA_LED_LINK 12 Pull down LED Control LED 13 MIIA_LED_ACT 14 Pull up 15 GND GND 16 GND 17 NC Fix 18 NC 2 4 7 eMMC amp TF Card eMMC and TF card are used to provide solid storage of boot code and system Although there is only one MMC SD controller in HPS TF card and eMMC could work alternatively by the help of eMMC TF card po
43. NC A7 NC A8 NC Other A9 3 3V_EXP A10 3 3V_EXP Power 3 3V A11 PCIE_RSTn 5CSX6D6F Reset A12 GND A13 PCIE_REFCLK_SYN_P 100M_OSC A14 PCIE_REFCLK_SYN_N 100M_OSC A15 GND A16 PCIE_RX_PO 5SCSX6D6F A17 PCIE_RX_NO 5CSX6D6F A18 GND A19 NC A20 GND A21 PCIE_RX_P1 5CSX6D6F A22 PCIE_RX_N1 5CSX6D6F A23 GND A24 GND A25 PCIE_RX_P2 5CSX6D6F A26 PCIE_RX_N2 5CSX6D6F A27 GND A28 GND A29 PCIE_RX_P3 5CSX6D6F A30 PCIE_RX_N3 5CSX6D6F A31 GND Differential clock and reference ground RX differential data and reference ground A32 NC B1 12V_EXP B2 12V_EXP B3 12V_EXP B4 GND Power 12V B5 PCIE_SMBCLK 5CSX6D6F Control Copyright 2014 Embest Technology Lark Board User Manual nbe Embest Technology 20 PCle Connector J1 B6 PCIE_SMBDAT 5CSX6D6F B7 GND Ground B8 3 3V_EXP Power 3 3V B9 3 3V_EXP Pull up Status B10 3 3V_EXP Power 3 3V B11 PCIE_WAKEn 5CSX6D6F Control B12 NC Other B13 GND B14 PCIE_TX_PO 5CSX6D6F TX Differential data and B15 PCIE_TX_P1 5CSX6D6F reference ground B16 GND B17 PCIE_PRSNT2_X1 5CSX6D6F Status
44. RAM in one operation These results has a work length of 32 bits of which the lower 16 bits are the data from ADC channel 1 and the higher 16 bits are the data from ADC channel 2 The ADC driver of Linux obtains ADC conversion results by reading the SRAM of FPGA each channel has 12 valid bits and stores data in complement format the data needs to be processed before it can be used by users The following figure shown the process of reading ADC conversion results at Linux user space Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 65 open dev adc adc gt init the adc gt read p start adc ai d lay read data from fpga sram Figure 4 12 Reading conversion results The ADC driver in the kernel is implemented in a form of character device so users only need to read the device at Linux user space to obtain ADC conversion results The following table lists the addresses of reference files Table 4 10 Reference file for ADC driver Reference Files linux 3 10 Itsi drivers char adc9628 c 4 7 Configuring Display Modes The Linux system of Lark Board supports VGA and HDMI output as well as LCD displays with different screen size Users can modify display parameters under u boot mode 4 7 1 VGA HDMI Output CH7033 video encoder chip provides VGA and HDMI output simultaneously by default and u boot has default settings for VGA HDMI display mode Therefore there i
45. SOF File into FPGA 1 Download all the FPGA files at http Awww embest tech com product pinggubanxilie lark board evaluation board html and uncompress it 2 Double click lark_assignment_defaults qpf under FPGA demon lark_cv_cam_sdi to open the project file with Quartus II if the file cannot be opened successfully please check if Quartus II has been installed properly 3 Click on the tool bar at top of the software window to generate a SOF file 4 Open Programmer as shown below Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology 81 fie Et yew Project Asegrments Poong Toots Yndow Hep V OAS 628 EKI fe Saeed RO Ory OOUR SHAG F j 2 Launch Smdaton Library Compier Project Navigator S Launch Design Space Explorer Cydone V SCSKFCEDSFSII7ES TreQuest Timing Analyzer P here Adasors Pine A Desp Parution Planner Netist Viewers MA SignalTep I Loge Analyzer p System Memory Content Editor AN i Loge Analyzer interface Editor mq a In System Sources and Probes Editor ggralProbe Pr aneno Se Foni Comlaton TG han Debugger Tak System Coraole s Comoe Design A Megaidizard Plug in Manager bal Nos 1 Software Buld Tools for Edise v D Fitter Pisce A Route amp on v gt Assembler Gerevate prog ammang fiet v gt TeneQuest Tng Analyse I Tosap v D EDA Netst Writer Progam Device Open Programmer ay Optons wonna Fe uewe et e
46. T device in your system s Float2 GCC hardware i Float2 Performance Hello Freestanding For details click Finish to create the project and refer Hello MicroC OS II to the readme txt file in the project directory i E ad Se 5 The BSP for this template is based on the Altera HAL B Figure 5 9 Template configuration 2 Compilation Configure the relevant modules according to the addresses and buses provided by FPGA The entry of Main function is contained in hello_world c to which C code can be added for configuration When all the operations are finished you can start to compile the project Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology 86 ee ee file Edit Source Refactor Nevigate Search Run Project Nigs il Window Help ri a r G G O Q OG hello world lt iah E Sair 77t Ye val p P val p in New Window s Import 1 bpon Build Project Ceon Project Refresh 5 Cose Project P om s Cose Unrelated Projects Build Configurations Make Targets Index Show in Remote Systems view Convert To fun As se in your system s hardware Debug As gt feste the project and refer to the readme txt file in the project directory Profile As Team Compare With Restore from Local History Nios It Figure 5 10 Compile project 3 Run the project After compilation is done select Run configurat
47. Tel 86 755 25635626 872 875 897 Email support embest tech com Sales Information Tel 86 755 25635626 863 865 866 86 7 868 Fax 86 755 256 16057 Email globalsales embest tech com Company Information Website htto www embest tech com Address Tower B 4 F Shanshui Building Nanshan Yungu Innovation Industry Park Liuxian Ave No 1183 Nanshan District Shenzhen Guangdong China 518055 Copyright 2014 Embest Technology Lark Board User Manual
48. box and then click Save to save the configurations under the name you entered Copyright 2014 Embest Technology Lark Board User Manual not Embest Technology 41 Basic options for your PuTTY session Specify the destination you want to connect to Serial line Speed COM10 115200 Connection type Raw Iene Rlogin SSH Se al Load save or delete a stored session Saved Sessions serial com10 Default Senos E SSH Serial Close window on exit Aways Never Only on clean exit Open Cancel Figure 3 3 Enter port number 6 Click Window entry on the left part of configuration window and change the Lines of scrollback to 50000 on the right part as shown below This would prevent printed texts from being overlapped with each other because of inadequate printing lines allowed in PUTTY terminal window Copyright 2014 Embest Technology Lark Board User Manual bot Embest Technology 42 L Options controlling PuTTY s window Set the size of the window Rows 80 24 i When window is resized IS Window Change the number of rows and columns Appearance Change the size of the font Behaviour Change font size only when maximised Translation Forbid resizing completely Selection Control the scrollback in the window Colours Connection Lines of scrolback Data v Display scrollbar Proxy Display scrollbar in full screen mode Telnet Reset scro
49. converted 4 Select the file you added in Input files to convert box and click Properties jon the right to determine if the generated file needs to be compressed as shown below Click OK after you finish settings and click Generate to make a RBF file Input files to convert File Data area Properties Start Address 4 SOF Data Page_0 soc_system sof SCSXFC6D6F31ES _Addfie M SOF File Properties x Remove F does not enable Partial Reconfiguration Down o canci Properties Generate Close Help Figure 4 5 Compress RBF file or not Note The default configuration of the Lark Board is to support uncompressed rbf file if you want to use the compression rbf file please modify the dip switch S12 status according to 2 4 10 DIP Switch 4 If the system want to boot with the new rbf file it is needed to rename the new rbf file to Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 52 soc_system rbf and replace the old file with the same name in OS 4 5 System Update Lark Board can boot from a TF card or eMMC Flash This chapter will respectively introduce the update of system images in TF card and eMMC Flash 4 5 1 Updating Images in TF Card There are two operating systems available for Lark Board One of them is the original Linux system hereafter called Linux system in short which only has character interfaces but no graphics ones the
50. d Slave s0_clk 0x0000_0000 Ox3Eff_EEEE no Avalon Memory Mapped Master m0_e1k e E eccb_lw_50_to_125 Avalon WM Clock Crossing Bridge gt m0_elk Clock Input peie_ev gt nO_reset Reset Input m_e s0_clke Clock Input clk gt drt Reset Input s0_e1k gt o Avalon Memory Mapped Slave s0_e1k 0x0002_0000 ox0002_7Ee n Avalon Memory Mapped Master m0_e1k 7 E pio_rp_reset PIO Parallel 1 0 e E Clock Input elk 50 5 cy ct Reset Input elk see Figure 5 30 PCle connections in QSYS Copyright 2014 Embest Technology Lark Board User Manual mbes Embest Technology 102 System Settin Number of lanes land v Lane rate Geni 2 5 Gbps Port type Root port m RI buffer credit allocation performance for received requests peren x Reference clock frequency 100 MHz Use 62 5 MHz application clock Enable configuration via the PCIe link Device Identification M Vendor ID 0x00001172 Device ID 0x0000e000 Revision ID 0x00000001 Class Code 0x00060400 Subsystem Vendor ID 0x00001172 Subsystem Device ID 0x0000e000 PCI Express PCI Capabilities Device Error Reporting Link MSI MSI X Power Management Maximum payload size 256 Bytes il Completion timeout range ABCD w V Implement completion timeout disable Figure 5 31 PCle configurations in QSYS 1 Avalon MM enka T Avalon M
51. d User Manual PF abesk Embest Technology 59 Writing Part of Images into eMMC Flash under U boot 1 Create a TFTP server on your PC and use a network cable to connect Lark Board to the PC 2 Power on Lark Board to boot up the system from either a TF card or eMMC Flash and press any key on PC s keyboard before the Putty window starts countdown in seconds to enter u boot mode and then execute the following instructions to rescan eMMC Flash if a TF card is used to boot the system please remove it before execute the following instruction mmc rescan 3 Execute the following instructions to set Lark Board s IP address and TFTP server s IP and MAC addresses the addresses used below are examples please change them according to your network configurations setenv ipaddr 192 192 192 200 setenv serverip 192 192 192 100 setenv ethaddr fc 64 21 55 a4 11 4 Execute the following instructions to update preloader tftp 0x1000000 preloader bin mmc write 0x1000000 0x800 0x200 mmc read 0x2000000 0x800 0x200 e cmp b 0x1000000 0x2000000 0x40000 Note 4 The instruction mmc operates based on blocks 1 block 512byte The instructions used above write a 256KB file named preloader bin at offset Ox100000 Verification is required after writing in order to ensure that data has been written correctly 5 Execute the following instructions to update u boot e tftp 0x1000000 u boot img fatwri
52. dified based your network setenv ethaddr 08 20 30 23 45 10 setenv ipaddr 192 192 192 64 setenv serverip 192 192 192 201 tftp 0x1000000 zilmage ping 192 192 192 201 Testing network interface under Linux Execute the following instructions in PUTTY terminal window to implement test ifconfig ethO 192 192 192 64 ping 192 192 192 201 tftp g r zImage 192 192 192 201 Lark Board User Manual bos Embest Technology 70 4 8 5 ADC Test The ADC on Lark Board supports dual channel differential input If it is a single ended input please short the jumper JP1 channel A or JP3 channel B on the board as shown below If it is a differential input there is no need to short jumpers Figure 4 14 Jumper JP1 and JP3 Please execute the following instructions in PUTTY terminal window to implement test root socfpga_cyclone5 cd root socfpga_cyclone5 adc_test PuTTY will print the signal frequencies and amplitudes of both channels as shown below Table 4 15 Signal frequencies and amplitudes 289 chanelO frequency 29 633789 Mhz amplitude 1542 289 chanel1 frequency 29 633789 Mhz amplitude 2185 The source code of the example application adc_test is under Linux APP package which can be downloaded from http Awww embest tech com product pingqubanxilie lark board evaluation board html 4 8 6 CAM8000 D Camera Test By default the system of Lark Board does not support CAM8000 D camera module
53. dnl sw index jsp Tools http sourceforge net projects win32diskimager The following table lists all the contents of BSP package and the formats these contents are provided in Table 4 2 BSP contents Types Names Description Formats Preloader Primary bootstrap Source code BIOS U boot Secondary bootstrap Source code Kernel Linux 3 10 ltsi Source code Serial Serial interface driver Source code RTC Hardware clock driver Source code Net 10 100M 1000M Ethernet driver Source code QSPI QSPI driver Source code SPI SPI driver Source code l2cC 12C driver Source code CH7033 VGA HDMI controller driver Source code Device Drivers PCle Altera s PCle driver Source code MMC SD MMC SD controller driver Source code USB OTG USB OTG 2 0 driver Source code Frame buff Frame buff driver Source code GPIO GPIO driver Source code GPIO Key GPIO pushbutton driver Source code LED User LED driver Source code ADC ADC9628 driver Source code GPIO Key User of GPIO key driver Source code Demo RTC RTC user layer application Source code ADC ADC user layer application Source code Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 46 4 3 Building Development Environment The development environment can be built by installing cross compiling environment and two Altera SoC development tools Quartus II and Altera SoC EDS Qua
54. e input files to convert and the type of programming file to generate You can also import input file information from other files and save the conversion setup information created here for future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Raw Binary File rbf Options Configuration device EPCEI6 Mode File name output_file rbf ia Remote Local update difference file NONE Input files to convert File Data area Properties Start Address Add Hex Data SOF Data Page_0 Figure 4 3 Parameters Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 51 3 Click SOF Data in Input files to convert box and click Add ile on the right to add sof file take output_files soc_system sof of the current project as example as shown below future use Conversion setup files Open Conversion Setup Data Save Conversion Setup Output programming file Programming file type Raw Binary File rbf Z Configuration device EPCE16 Mode Fast Passive Parallel x16 gt File name output_file rbf aa Advanced Remote Local update difference file Input files to convert File Data area Properties Start Address 4 SOF Data Page_0 soc_system sof 5CSXFC6D6F31ES _Add Fie l Remove Properties Figure 4 4 Add file to be
55. e written into TF card insert the card into the TF card slot on Lark Board and power on the board Now the booting information can be seen in PuTTY terminal window or other terminal window e Using image files compiled by yourself to replace all the existing files After installation of Yocto is completed a script file named mk_sdimage sh can be found under opt altera linux bin This file can merge all the files including kernel DTB preloader u boot and rootfs into a single complete image file which can then be written into a TF card by Win32Disklmager Please visit http www rocketboards org foswiki Documentation GSRD131SdCard to learn how to use mk_sdimage sh to merge these images e Using image files compiled by yourself to replace some of the existing files Before getting start to update TF card partially let s take a look at the partitions of a TF card as shown below Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 54 Unused Partition 3 RAW Partition 2 EXT Linux Partition 1 FATS2 windows U boot Environment Figure 4 7 Partitions of TF card The following table lists all the files in these partitions and their descriptions Table 4 3 Files in partitions Partitions Formats File Names Descriptions socfpga_cyclone5 dtb Device Tree Blob file Partition 1 FAT soc_system rbf FPGA configuration file zlmage Com
56. ealize a quick use of Lark Board through simple hardware connections and software configurations Please follow the quick steps listed below 1 Set the DIP switches as shown in the following figure ttt tttt Figure 3 1 DIP switch settings 2 Connect a USB To TTL conversion cable for example UART8000 U needs to be purchased separately to the serial port of Lark Board as shown below Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 40 3 4 5 UART8000 U Lark Board Line Signal Pin Signal _ Black GND a GND Red TXD 3 RX Green RXD TX Figure 3 2 Hardware connections Connect the UART8000 U to the USB Host on PC and refer the UART8000 U user manual to install the driver then power on the board After Lark Board boots up it will obtain a port number for example com10 allocated automatically by PC to the board PuTTY will be taken as the example of serial communication software to explain how to configure parameters Firstly download PuTTY from http Awww chiark greenend org uk sgtatham putty download html then install and run it on a PC In the pop up configuration window please select Serial radio box under Connection type enter the serial port number COM10 for example allocated by the PC in Serial line text box and 115200 in Speed text box you can enter a name for example serial com10 for the current session in Saved Sessions text
57. ed when SD MMC cards work as block devices mmc_queue implements management of request queue MMC SD driver implements controller drivers The following figure illustrates how the four parts of MMC SD driver work in the whole system Copyright 2014 Embest Technology Lark Board User Manual bot Embest Technology 62 KERNEL Figure 4 9 MMC SD driver The following table lists the addresses of reference files for MMC SD driver Table 4 8 Reference files for MMC SD driver linux 3 10 lItsi drivers mmc host dw_mmc socfpga c linux 3 10 ltsi drivers mmc host dw_mmc pltfm c Reference Files linux 3 10 ltsi drivers mmc host dw_mmce h linux 3 10 ltsi drivers mmc host dw_mmc c 4 6 2 Frame Buffer Driver The frame buffer of Lark Board relies on the Virtual Frame Buffer Device driver please refer to vfb c file in kernel to fulfill its function The driver sets different display configurations based on the parameters provided by u boot There are three default display modes 4 3 LCD 480x272 7_CD 800x480 and VGA 1024x768 Additionally the driver needs to set a variety of parameters including operating clocks 10MHz for 4 3 LCD 30MHz for 7 LCD 65MHz for VGA frame reader and clocked video output IP for Copyright 2014 Embest Technology Lark Board User Manual not Embest Technology 63 FPGA display control interfaces based on the display modes Please visit htto www altera
58. ed with Quartus through a mini USB cable There is a jumper JP7 near CONS for selecting components involved in JTAG chain The following figures show the detection results of SoC chip when JP7 is shorted and opened Add JP7 TDI gt SCSXFC6D6 Figure 2 5 JP7 shorted Remove JP gt SCSXFC6D6 SOCVHPS Figure 2 6 JP7 opened JTAG J3 is used to connect the JTAG interface of an external USB Blaster debugger please note that the position and direction of pin 1 when connector an external USB Blaster wrong connection might damage the JTAG interface of SoC The following table contains pin definitions of JTAG interface Table 2 18 JTAG interface JTAG Connector J3 Pin Signal Name Device Signal Type 1 JTAG_TCK 5CSX6D6F JTAG 2 USB_DISABLEn Control 3 JTAG_TDI 5CSX6D6F JTAG Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 30 JTAG Connector J3 4 3 3V_VDD Power 5 JTAG_TMS 5CSX6D6F JTAG 6 HPS_WARM_RSTn JP5 Control 7 NC 8 NC 9 FPGA_TDI 5CSX6D6F JTAG 10 GND Ground 2 4 10 DIP Switch There are 5 DIP switches on Lark Board for power supply control HPS boot selection FPGA configuration mode selection and SDI rate selection The following contents will introduce the function connections and signal definitions of each DIP switch the DIP Switches location as show below Figure 2 7 DIP Switch
59. ed_ ok lark lark output_files lark cdf File Edit View Processing Tools Window Help Search altera con Hardware Setup E Enable real time ISP Lark Board USB 1 File to allow background programming for MAX II and MAX V devices Mode JTAG Z Device Checksum Usercode Program Verify Blank Examine Security Eral Configure Check Bit SCSXFC6D6F31I7ES 0C9648C7_ 0C964BC7 a al id a SOCVHPS 00000000 lt none gt Sa a output_files lark sof lt none gt gil Auto Detect aM De yada Fie EG change Fie m Figure 5 5 Download configuration files 9 Agreen bar will appear on the top right corner of the window as shown below when download is completed 100 r VO a y I Progranimer E O2cnde lark v2 bak bakjeam edi led ok lark lark output files lark caffe So ee File Edit View Processing Tools Window Help 5 Search altera con ee aa ees Enable real time ISP to allow background programming for MAX II and MAX V devices m File Device Checksum Usercode Program Verify Blank Examine Security Erase ISP Bu Start Configure Check Bit CLAMP 7s output_files lark sof SCSXFC6D6F31I7ES 0C9648C7 0C9648C7 l inas lt none gt SOCVHPS 00000000 lt none gt iy Auto Detect J Delete ja m zl Sa 2 2 Add Device fup Hy Lae H a J Down
60. eher C oe BV Shor quad Pitas memory 3 0 V SPI or quad SPI flash memory Figure 2 9 BSEL S12 is used to select FPGA configuration mode The default FPGA configuration mode on Lark Board is MSEL 4 0 00000 Table 2 4 DIP switch 4 Switch Pin Signal Name Function S12 FPGA Configuration Scheme 1 MSELO On MSELO 0 Off MSELO 1 2 MSEL1 On MSEL1 0 Off MSELO 1 3 MSEL2 On MSEL2 0 Off MSELO 1 4 MSEL3 On MSEL3 0 Off MSELO 1 MSEL4 Default MSEL4 0 The figure shown below can be found in Cyclone V datasheet It lists all the configuration modes supported by FPGA Copyright 2014 Embest Technology Lark Board User Manual beak Embest Technology 33 Configuration Scheme Compression Design Security Vccpgy V Power On Reset Valid MSEL 4 0 Feature Feature POR Delay Fast 10100 Disabled Disabled 1 8 2 5 3 0 3 3 Standard 11000 Fast 10101 FPP x8 Disabled Enabled 1 8 2 5 3 0 3 3 Standard 11001 Fast 10110 Enabled Enabled 1 8 2 5 3 0 3 3 Disabled Standard 11010 E Ea a O Fast ooo00 Disabled Disabled 1 8 2 5 3 0 3 3 Standard 00100 Fast 00001 FPP x16 Disabled Enabled 1 8 2 5 3 0 3 3 Standard 00101 Fast 00010 Enabled Enabled 1 8 2 5 3 0 3 3 __ Disabled Standard 00110 Enabled Enabled Fast 10000 PS Disabled Disabled 1 8 2 5 3 0 3 3 Standard ioi Enabled Enabled Fast 10010 AS x1 and x4 Disabled Disabled
61. es Location S8 is connected to the general I O of FPGA Bank 8A and cam be used as a typical status input switch Table 2 1 DIP switch 1 Switch Pin Signal Name Function Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology S8 User FPGA Dip Switch 1 USER_FPGA_DIPSWO C8 function defined by user USER_FPGA_DIPSW1 B8 function defined by user USER_FPGA_DIPSW2 C10 function defined by user 2 3 4 USER_FPGA_DIPSW3 C9 function defined by user S9 and S10 are used to enable and disable various voltages on the board When a voltage is disabled or unavailable a LED in the corresponding power supply area will be turned on indicating the voltage has been disabled or unavailable Table 2 2 DIP switch 2 Switch Pin Signal Name Function S9 Power on off for 5V 12V 3 3V 2 5V 1 5V_SHDNn On disable 5V Off enable 5V 2 12V_SHDNn On disable 12V Off enable 12V 3 3 3V_POWER_EN On disable 3 3V Off enable 3 3V 4 2 5V_POWER_EN On disable 2 5V Off enable 2 5V S10 Power on off for 1 8V 1 1V 1 5V VTT 1 1 8V_POWER_EN disable 1 8V Off enable 1 8V 1 1V_POWER_EN disable 1 1V Off enable 1 1V 1 5V_POWER_EN disable 1 5V Off enable 1 5V 2 3 4 VTT_POWER_EN disable 0 75V Off enable 0 75V 11 is used to select clock and booting of HPS the default co
62. guration files need to be loaded before the kernel starts running If the kernel image you are working with does not involve any FPGA resources only run ramboot needs to be executed 5 After entering Shell mode of Linux system run the script file nome root emmc sh to update the whole system in eMMC Flash 6 Reboot Lark Board to boot from eMMC Flash Writing Part of Images into eMMC Flash under Linux Note Q Please remove the TF card before booting Lark Board or the files would be written into the card instead L This method is not suited for filesysetm update in eMMC Flash After Lark Board successfully boots up from eMMC Flash the instructions contained in the following table can be used to replace the individual image in each partition of eMMC Flash Table 4 6 Replace individual image Files Operations and Instructions Copy images to your flash drive connect flash driver to the board and zImage then execute the following commands to mount it and copy files to eMMC assuming device name of the drive is dev sda1 soc_system rbf e sudo mkdir mnt udisk sudo mount dev sda1 mnt udisk socfpga_cyclone5 dtb sudo mkdir mnt sdcard G sudo mount dev mmclbokcp1 mnt sdcard u boot img G sudo cp mnt udisk lt file_name gt mnt sdcard preloader bin sudo dd if preloader bin of dev mmclbokcp3 bs 64k seek 0 Copyright 2014 Embest Technology Lark Boar
63. hows the format of audio data OLRCK Left Justified OSCLK Out Figure 5 22 Audio data format Please follow the steps listed below to implement I2S audio test Please refer to 4 5 System Update to update the system of Lark Board and then connect a HDMI display to the board Copy the test program I2S test that is contained in Linux APP camera tar bz2 of the development package to the FAT partition of a TF card Execute the following instructions after the board boots up successfully mount dev mmcbik0p1 mnt e cd mnt 12S_test Now y the HDMI display is making a continuous sound similar to hands free sound made by telephones 5 3 4 Input output of SDI Video SDI is an abbreviation of Serial Digital Interface It supports SD SDI HD SDI and 3G SDI at different data rates Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 96 Lark Board basically depends on SDI IP core to implement serial to parallel or parallel to serial conversion in both RX and TX directions The data between RX IP and TX IP is stored temporarily in FIFO so as to ensure clock domain crossing data synchronization on reception and transmission The following figure shows how SDI IP core works SDI_OUT rx_data_valid_out rx_dkh p pl relk si x gxb_tx_clkouti rx_serial refdk tx_serial_refdk Figure 5 23 Working principle of SDI IP core The following figure shows
64. hrough co axial cables J10 is an output interface which is the destination of the signal that travels from SoC s serial transmitter to LMH0303 driver J11 is an input interface that receives high resolution serial signal from external devices and passes it to LMH0384 equalizer which provides input to SoC s serial receiver The connections between SoC and LMH0303 LH0384 are shown in the following table Table 2 8 SDI input output SDI Input amp Output Pin Bank Direction Signal Name Signal Type T4 GXB_L1 Out SDI_TX_P L4 GXB_L1 Out SDI_TX_N C13 8A Out SDI_TX_SH_HDn E13 8A Out SDI_RSTIn F13 8A In SDI_FAULTn een F14 8A Out SDI_TX_EN F15 8A IO SDI_I2C_SDA B12 8A Out SDI_I2C_SCL U2 GXB_L1 In SDI_RX_P U1 GXB_L1 In SDI_RX_N E12 8A Out SDI_RX_BYPASS a D12 8A Out SDI_RX_EN 2 4 3 PCle 5CSXFC6D6F SoC integrates 2 PCle hard IPs and 9 pairs of 3Gbps serial transceiver Lark Board has a PCle X1 X4 J1 connector on board to make part of the SoC s IPs available for various PCle X1 X4 compliant expansion boards Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 19 The following table contains pin definitions of the PCle connector Table 2 9 PCle connector PCle Connector J1 Pin Signal Name Signal Type A1 12V_EXP A2 12V_EXP A3 12V_EXP A4 GND Power 12V A5 NC A6
65. igure 2 1 Top view of Lark Board TF card slot l Figure 2 2 Bottom view of Lark Board 2 4 1 LCD VGA HDMI The powerful video performance is one of the important features of Lark Board It supports multiple types of displays including 50 pin medium small sized LCD modules VGA HDMI and SDI monitors LCD VGA HDMI shares the same video data source Frame Buffer created in FPGA Now let s take a deep look at the hardware implementation of the Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 14 display function of LCD VGA HDMI interfaces Frame Buffer The video output of Lark Board comes from a frame buffer implemented by FPGA The buffer has 28 signal lines in which there are 24 data lines 3 control lines and 1 clock line A 50 pin LCD can be connected directly to them to display images while VGA HDMI displays need the on board chip CH7033B to convert the data before they can display any images SDI also receive data from the frame buffer but before that conversions by the logic resources of FPGA are required as well Table 2 4 Display output pins Display Data Output Pin Bank Direction Signal Name Signal Type K12 8A Out DSS_CLK Clock J12 8A Out DSS_VSYNC H13 8A Out DSS_HSYNC Control G13 8A Out DSS_ACBIAS E11 8A Out DSS_DO D9 8A Out DSS_D1 E9 8A Out DSS_D2 B6 8A Out DSS_D3 B5 8A Out DSS_D4
66. ilure external forces water animals or foreign materials Products malfunction caused by disassembly or alter of components by customers or products disassembled or repaired by persons or organizations unauthorized by Embest Technology or altered in factory specifications or configured or expanded with the components that are not provided or recognized by Embest Technology and the resulted damage in appearance or function Product failures caused by the software or system installed by customers or inappropriate settings of software or computer viruses Products purchased from unauthorized sales Warranty including verbal and written that is not made by Embest Technology and not included in the scope of our warranty should be fulfilled by the party who committed Embest Technology has no any responsibility Within the period of warranty the freight for sending products from customers to Embest Technology should be paid by customers the freight from Embest to customers should be paid by us The freight in any direction occurs after warranty period should be paid by customers 4 Please contact technical support if there is any repair request Note Embest Technology will not take any responsibility on the products sent back without the permission of the company Contact Information Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 106 Technical Support
67. includes two Quartus projects lark cv_pcie_rp and lark_cv_cam_sdi The former integrates LCD VGA HDMI output ADC and PCle function the latter integrates camera and SDI function 5 3 1 Input of Camera Video The clock and data pins of camera interface of FPGA are connected to the camera interface of Lark Board Camera interface is compliant with BT601 BT656 protocol and Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 88 needs the operating clock provided by FPGA Lark Board supports 640x480 input resolution and FPGA provides a clock frequency at 25MHz Camera module transmits video data depending on the pixel clock generate by itself CAM8000 D camera module will be taken as the example here The register configurations for CAM8000 D include resolution of 640x480 and YUV422 video format Each pixel of YUV422 format has 16 bits while the input has only 8 bit and therefore two adjacent bytes constitute a complete pixel The following figure shows four pixels YO UO VO Y1 U1 V1 Y2 U2 V2 Y3 U3 V3 The saved code stream is YO U0 Y1 V1 Y2 U2 Y3 V3 and the mapped pixel points are YO UO vo Y1 U1 V1 Y2 U2 V2 Y3 U3 V3 first second second DATA 9 2 pixel pixel pixel even Y 7 0 U 7 0 Y 7 0 V 7 0 Y 7 0 U 7 0 odd Y 7 0 U 7 0 Y 7 0 VI7 0 Y 7 0 U 7 0 Figure 5 13 9 YUV422 pixels There are two important control signals i_cam_vs AND i_cam_hs contained in the input
68. ing Linux Kernel Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 49 1 Please get the kernel source code from http Awww embest tech cn product pinggubanxilie lark board evaluation board h tml 2 Please execute the following instructions to compile it tar xvjf linux 3 10 Itsi tar bz2 cd linux 3 10 Itsi export CROSS_COMPILE gcc linaro arm linux gnueabihf 4 7 2012 11 20121123_linux b in arm linux gnueabihf make ARCH arm lark_board_defconfig make ARCH arm LOADADDR 0x8000 After all the instructions are executed a kernel image file zimage can be found under arch arm boot a device tree blob file socfoga_cyclone5 dtb can be found under arch arm boot dts Note Currently the uboot_v2013 01 01 from Altera does not support ulmage L The instruction used to compile dtb file separately is make ARCH arm dtbs 4 4 3 Generating FPGA RBF Configuration File FPGA needs to be configured first before Linux could access it There are two types of configuration files covered in this document One of them is SOF file generated by compiling Quartus projects FPGA configuration can be accomplished by writing this file directly into FPGA with the programmer integrated in Quartus please refer to 5 2 1 Building FPGA Project and Programming SOF File into FPGA for detailed information of the programming process The other is RBF file which is obtained by converting a SOF
69. ions as shown below and then you can run the project Nios 1 adc_cmasshello_world c Eclipse File Edit Source Refactor Navigate Search Broject Nigs I Window Help D g ig dh hn aieri ARAT E Figure 5 11 Run configurations The images captures by camera module will be displayed on LCD after the project running is finished 4 Update BSP bottom level software The steps above have accomplished a successful running If FPGA code is changed the BSP bottom level files in Eclipse need to be updated in order to synthesize a new sopc file To do so please right click lark_video_bsp in the left part of the window and select Generate BSP as shown below Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 87 Figure 5 12 Generate BSP 5 Recompilation and running Repeat the step 2 and 3 to accomplish running of the project The images captures by camera module will be displayed on LCD after the running is finished 5 3 FPGA Function Implementation on Lark Board The FPGA function implemented on Lark Board include input output of camera video input output of SDI high speed serial data data exchange on PCle interface and input of ADC data This chapter will introduce how these functions are implemented Note A The FPGA development package provided by Embest can be downloaded from http www embest tech com product pinggubanxilie lark board evaluation board html L The package
70. iple and detailed circuit 2 4 16 Extension Interfaces To facilitate users function expansion part of I O resources of FPGA and HPS has been extended by using two 40 pin connectors This section will introduce these interfaces in detail HPS Extension J21 is the I O extension interface for HPS It uses a 40 pin 2 54mm IDC connector to connect to Bank 7A 7B 7C 7D which are attached to some of the HPS s controllers such as QSPI UART I2C and SPI Certainly most of them can be set as GPIOs The following table contains pin definitions of J21 Table 2 10 HPS extension interface HPS Extend 40Pin IDC Connector J21 Pin Direction Signal Type Signal Name Pin_FPGA Bank FPGA 1 P Power 5V_EXP3 2 G Ground GND 3 N NC NC 4 N NC NC 5 P Power 3 3V_EXP3 6 N NC NC 7 G Ground GND 8 N NC NC 9 OUT UARTO HPS_UARTO_RX D24 7A Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 37 HPS Extend 40Pin IDC Connector J21 10 G NC GND 11 IO GPIO HPS_GPIOO F16 12 IN UARTO HPS_UARTO_TX E24 7A 13 IN 12C0 HPS_I2C0_SCL E23 7A 14 IO GPIO HPS_GPIO9 B15 7D 15 OUT UART1 HPS_UART1_RX D22 7A 16 lO 12C0 HPS_I2C0_SDA C24 7A 17 G Ground GND 18 IN UART1 HPS_UART1_TX C23 7A 19 lO QSPI QSPI_IO0 C20 7B 20 G Ground GND 2
71. l PF abesk Embest Technology 1 Chapter 1 Product Overview 1 1 Brief Introduction Lark Board is an evaluation board designed by Embest based on an Altera ARM Cortex A9 dual core FPGA processor for areas such as medical instruments video surveillance and industrial control The SoC named 5CSXFC6D6F31 that comes from Cyclone V SX family integrates not only the traditional FPGA fabric but also an ARM Cortex A9 based HPS operating at 800MHz and a high speed transceiver 8Gbps Serdes hard subsystem Lark Board provides 1GB DDR3 SDRAM separately for both ARM and FPGA and has 4 high speed USB2 0 Host interfaces a TF card slot for mass storage a 12 bit camera interface a VGA interface a 24 bit LCD interface PCle UART JTAG 3Gbps SDI input output and a HDMI interface Additionally two 2 200 pin connectors are mounted on the board in order to make the unused pins of HPS FPGA available for users Lark Board uses a switching power supply controller chip integrated with inductor that comes from Altera s Enpirion family to provide a stable and efficient output for each BANK of FPGA Meanwhile it has two on board DIP switches used to enable various voltage levels required by the different interfaces on the board with the purpose to facilitate power consumption evaluation conducted by users Lark Board comes with a lot of FPGA example applications and the corresponding source code Linux 3 10 and u boot source code and Debian 7 4
72. l introduce how there modes work as well as HDMI I2S audio output and FPGA register configurations 1 Output for LCD Images can be displayed on LCDs as long as the output is compliant with RGB444 video format The output resolution and parameter settings depend on the size of the LCD used The following two figures show the parameter settings for a 7 LCD with a resolution of 800x480 Image Data Format Image width Active pixels 800 pixels Image height Active lines 480 Taane Bits per pixel per color plane 8 bits Number of color planes 3 Color plane transmission format Sequence Parallel Allow output of channels in sequence Interlaced video ir Syncs Configuration Syncs signals Embedded in video On separate wires Active picture line 0 Frame Field 1 Parameters Ancillary packet insertion line 0 ie Embedded Syncs Only Frame Field 1 Horizontal blanking 0 pixels Vertical blanking 0 lines Figure 5 18 Settings for 7 LCD 1 Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 93 Separate Syncs Only Frame Field 1 Horizontal sync a7 pixels Horizontal front porch 39 pixels Horizontal back porch 39 pixels Vertical sync 2 lines Vertical front porch 13 lines Vertical back porch 29 lines F rising edge line 0 F falling edge line 0 Vertical blanking rising edge line 9 Ancillary packet insertion li
73. lifier ADL5562 to 6dB 12dB or 15 5dB For more details please refer to ADL5562 datasheet Li 15nH 1 GND Z Mp2 VCOM z 203 208 LAAN wrt OOnF iH rt ing vor R160 576 150 C827 69pF R578 Hi R164 3 826 330 RST 150 Zap L5 15n C828 68pF cB Ape is AA c24 RESO 23 AMP1_OUTN 4 100nF 100nF R579 33 AMP1 OUTP ADO GND ADC_GND 12 enal ep HZ 5 gece GND J 33v vDD 3 3V_AMP 7 weet 5 P H vec GND2 a FB30 VECS ADLSS62 c_GND 600R FB C202 T t00nF FB35 J 600R FB Figure 2 4 Amplification output circuit Copyright 2014 Embest Technology Lark Board User Manual Embest Technology 23 As shown in the figure above an optimized third order butterworth anti alias filter is placed between amplifier output end and ADC e ADC The ADC AD962 can provide a capability of 12 bit 105MSPS sampling performance and support quantified data output of CMOS or LVDS The following table contains pin definitions and signal connections between ADC and FPGA Table 2 11 Interface between ADC and FPGA Interface between ADC amp FPGA Pin Bank Direction Signal Name Signal Type AE29 5B Out ADC_CLK105_P AD29 5B Out ADC_CLK105_N ace W25 5B In ADC_Dp0 V25 5B In ADC_Dn0 Y26 5B In ADC_Dp1 Y27 5B In ADC_Dn1 V23 5A In ADC_Dp2 W24 5A In ADC_Dn2 AA26 5B In ADC_Dp3 AB27 5B In ADC_Dn3 AA24 5A In ADC_Dp4
74. llback on keypress iy Reset scrollback on display activity By Push erased text into scrollback Figure 3 4 Window configuration 7 Click Serial entry on the left part of the window and configure serial lines as shown below When configuration is done click Open to enter PuTTY terminal window Copyright 2014 Embest Technology Lark Board User Manual am Embest Technology 43 R PuTTY Configuratio ox Category E Session Options controlling local serial lines Logging Select a serial line Terminal Keyboard Serial line to connect to COM10 ad _ Configure the serial line Window Speed baud i i Appearance Behaviour Data bits Translation Stop bits Selection Colours Parity B Connection Flow control Data Proxy Telnet Rlogin H SSH Serial Figure 3 5 Serial configuration 8 Now the serial connection between PuTTY and Lark Board has been established PuTTY terminal window will print booting information when Lark Board is rebooting To implement operations on Lark Board you just need to type instructions in the window Copyright 2014 Embest Technology Lark Board User Manual mbesh Embest Technology 44 Chapter 4 Linux This chapter will briefly introduce the Linux system structure of Lark Board available software resources building of development environment system image compilation and update drivers paths a
75. lp New AlsShIREN ES Open File E Nios H AppScation men crew Nios Il Board Support Package Gate E Nics I Library Corwert Line Delimiters To Switch Workspace Restart s Import id Export Properties Lio ad CteleShitteW Alte Enter Tasks E Console C Properties 0 others 5s 18 items Figure 5 8 Nios Il Application and BSP from Template Sev eoOrKk evan leky a ortem is u ae8 i_fpoa_ Open Tools Resource Path Location Type Open template Please select SOPC file name the project and finally click Finish as shown below to create a BSP based on SOPC Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 85 r S Nios I Application and BSP from Template sd lh Nios II Software Examples Create a new application and board support package based on a software example template Target hardware information SOPC Information File named E 02code lark_v2 lark_camera new lark_cam sopcinfo CPU name nios2_qsys_0 I Application project E Use default locatign L Project location E 02code lark_v2 lark_camera software lark_camera 4 Project template Templates Template description i Blank Project Hello World prints Hello from Nios II to STDOUT Board Diagnostics Count Binary This example runs with or without the MicroC OS II Float2 Functionality RTOS and requires an STDOU
76. me ago FPGA is always involved in data acquisition especially in the high speed applications the data acquisition systems built up with FPGA and ADC can be often found Lark Board has a data acquisition system prototype which is made up of high bandwidth amplifier anti alias filter high speed ADC FPGA and ARM to support dual channel single ended analog signal based on SMA input or differential analog signal Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 22 Pre Amp The pre amp circuitry is used to receive and amplify analog input Lark Board provides two analog input channels that support single ended SMA input or differential input J SMA C211 100nF zip 100nF EX JP1 ADC_GND O PPH m 33V AMP I ADC GND f ll l EFA C198 C199 C200 ADC GND T iek T Rad cd ca Keep 75ohm Trace Impedance for Single Ended ADC_IN aun Addd Jumper JPL JP3 When Using Differential Signal Input Figure 2 3 Pre Amp circuitry As shown in the figure above pre amp circuitry is made up of a Balun T46 and a balanced filtering circuit The jumpers JP1 and JP3 are used to select working mode of Balun When JP1 and JP3 are both opened J6 and J7 constitute a differential channel A J8 and J9 constitute channel B When JP1 and JP3 are both shorted J6 input is a single ended channel A and J8 is a single ended channel B The resistors R159 R158 R166 and R168 are used to set the gains of amp
77. mine Security Erd p Start Check Bit Found devices with shared JTAG ID for device 1 Please select your device 5 5CSEBA6 5 5CSEBA6ES 5 SCSEMA6 5 SCSTFD6DS 5 SCSXFC6C6 5 SCSXFC6C6ES I J SCSXFC6D6 SE SCSXFC6D6ES pur wm og P Do gt aa SCSXFCEDEF31ES TDO Figure 5 3 Select device 7 then click Si Change File to select sof file and finally click Open as shown below Lasera use vos e id Enable real time ISP to allow background programming for MAX II and MAX V devices Fie Device Checksum Usercode Program Verify Blank Examine Security Er Pu Start Configure Check Bit Stop W Select New Programming File ib Auto Detect SS Lookin Jl E 02code Vark _v2 ak bak cam_sd_led_ok output_fles JOOOU 8 X Delete z A My Computer Name Size Type Date Modified Add File ull Add len R eh sofFile 2014 7 7 11 40 06 lark sof Programming Files sof pof jam jbc ekp jic Figure 5 4 Select file Program Configure 8 Make sure the check box in the line of the sof file is checked and click Start in the left part of the window as shown below to start downloading configuration files Copyright 2014 Embest Technology Lark Board User Manual 83 mbes Embest Technology E Programmer E 02code lark v2 bak bak eam_sdi_l
78. n total on DDR3 SDRAM interface which includes 44 data lines 82 DQ 4 DM 4 pairs of DQS 15 address lines 11 instruction lines 2 clock lines and 1 ZQ calibration resistive line Because DDR is source synchronous time sequence interface model the signals related to each other require same length traces on PCB layout to ensure timing closure In addition parameters such as time sequence driving capability and on chip match can be configured in Qsys and therefore being consistent with the physical design is required it would be wise to add a matching resistor in parallel on the board because the address and instruction signals are working under two driven by one mode The following table contains the interface definition and signal connections of HPS DDR3 Table 2 1 HPS DDR3 HPS DDR3 Pin Bank Direction Signal Name Signal Type M23 6A Out DDR3_HPS_CLK_P Clock L23 GA Out DDR3_HPS_CLK_N F26 6A Out DDR3_HPS_AO G30 6A Out DDR3_HPS_A1 F28 6A Out DDR3_HPS_A2 F30 6A Out DDR3_HPS_A3 Address J25 6A Out DDR3_HPS_A4 J27 6A Out DDR3_HPS_A5 F29 6A Out DDR3_HPS_A6 E28 6A Out DDR3_HPS_A7 Copyright 2014 Embest Technology Lark Board User Manual nbe Embest Technology 8 HPS DDR3 H27 6A Out DDR3_HPS_A8 G26 6A Out DDR3_HPS_AQ D29 6A Out DDR3_HPS_
79. nd generate FPGA RBF configuration files as well Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 48 4 4 1 1 2 Compiling U boot and Preloader Please get u boot source code from http Awww embest tech cn product pinggubanxilie lark board evaluation board h tml Please execute the following instructions to compile it tar xvjf u boot 2013 lark board tar bz2 cd u boot socfpga lark board export CROSS_COMPILE gcc linaro arm linux gnueabihf 4 7 2012 11 20121123_linux b in arm linux gnueabihf make mrproper make socfpga_cyclone5_config make After all the instructions are executed u boot img file can be found under u boot socfpga lark board and u boot spl bin file can be found under u boot socfpga lark board spl Note A gcc linaro arm linux gnueabihf 4 7 2012 11 20121123_linux bin arm linux gnueabihf is the directory where saves the default cross compiler If you are using the cross compiler provided by Yocto please modify the directory accordingly 3 Copy the u boot spl bin generated by the last step to C altera 13 1 embedded 4 4 2 and run the Embedded_Command_Shell bat file under the same directory and then execute the following instructions to generate a file Proloader bin cd cygdrive c altera 13 1 embedded mkpimage exe o preloader bin u boot spl bin u boot spl bin u boot spl bin u boot spl bin Compil
80. nd working principles function tests and application development 4 1 Linux System Structure of Lark Board The embedded Linux system of Lark Board is composed of four blocks Preloader U boot Kernel and Rootfs the following figure is an illustration of the structure followed with brief description for each block Figure 4 1 Embedded Linux system structure Preloader It is a primary bootstrap when system boots up it is copied from HPS boot ROM to on chip RAM to be executed It is responsible for initializing CPU copying u boot to SDRAM and then hand over control to u boot U boot It is secondary bootstrap of version 2013 01 01 responsible for interacting with users updating images and loading kernels Kernel Its version is Linux3 10 ltsi Altera will provide a long term support to it and Embest will also upload code combination and updates in time Rootfs It uses ext filesystem Debian filesystem image is also available for users 4 2 Software Resources You can download Demos operating system source code tools and pre built images by visiting the links in the following table Copyright 2014 Embest Technology Lark Board User Manual 45 beck Embest Technology Table 4 1 Software resources Categories URLs Demos Source Code http Awww embest tech com product pinggubanxilie lark board evaluation board html Pre built Images https www altera com download sw
81. ne 0 Embedded Syncs Only Field 0 Vertical blanking 0 lines Separate Syncs Only Field 0 Vertical sync 0 lines Vertical front porch 0 lines Vertical back porch 0 lines 7 General Parameters SCSCSCid Pixel fifo size 512 pixels Fifo level at which to start output 1 pixels i Video in and out use the same clock Use control port Figure 5 19 Settings for 7 LCD 2 By using a simple QSYS project the LCD output interface can be tested quickly to see if it is working properly For example Test Pattern Generator can be used to generate colored stripes or single color background in LCD data format as shown below E alt_vip_itc_0 Clocked Video Output F is_clk_rst Clock Input ipll Oo is_clk_rst_reset Reset Input is_clk_rst din Avalon Streaming Sink is_clk_rst clocked_video Conduit Eil E alt_vip_tpg 0 Test Pattern Generator clock Clock Input pll_0_o reset Reset Input clock dout Avalon Streaming Source clock Figure 5 20 Test LCD output interface 2 VGA HDMI Output Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 94 D 23 0 D 23 0 SPDIF Ds CK 25S WS Rs D 3 Copyright 2014 Embest Technology The video data is sent by FPGA to CH7033B chip which then configures the data based on software settings and sends it out Please refer to the source code of BSP for register configura
82. nes 44 Software AGSOUNC CS i e cesta 44 Building Development Environment ceeeceeeeeeeneeeeeneeeeneeeteneeersaeeeenaes 46 4 3 1 Building Linux Development Environment ceeeeeeeeeeeeeeeees 46 4 3 2 Installing Altera SoC Development Software cesses 47 4 3 3 Installing Linux Cross Compiler Optional ccccceeeee 47 System Compilati nan renia ts 47 4 4 1 Compiling U boot and Preloader 48 4 4 2 Compiling Linux Kernel 2 cc cc eee 48 4 4 3 Generating FPGA RBF Configuration File eeeeeeeeee 49 System Update cise 52 4 5 1 Updating Images in TF Card wcssscsisescced netcnet necccednzescneesteseneuesceeenee 52 4 5 2 Updating Images in eMMC Flash 56 INtFOGUCTION 1G Drivers sissies aaisa apiri Taaa 60 4 6 1 MMC SD Driven sirieni E ee ak aa 61 4 6 2 Frame Buffer Driver ssri i steadied sats fee 62 4 6 3 ABOADA E de atebetnwetabeterntetn nate 63 Configuring Display Modes 5 12404 65 4 7 1 VGA HDMI ka 65 4 7 2 Configuring tor LCD w 34 4048 ci ies 66 4 7 3 Configuring tor 4 3 LOD sssssrsssisise ae 66 Example Applications riseire EE EE e a T s 66 4 8 1 LED TESE e ee eae er ere meee ete eee bor freer eee e 66 4 8 2 Button Keypad TeSt oo eee eeeeeeeneeeeseeeeeneeeeeeeeeneeeteneeereaeeennaeees 67 4 8 3 PUle Testta2e 2625s eee eee 68 4 8 4 Network Interface TeSt cccescceesseeeesceeeeeeeeeseeeseeneeennenenanensenenes 69 4 8 5 ADG Test cucccicnte ieee 70 4 8 6 CAM8000 D Camera TS c
83. nfigurations on Lark Board are CLKSEL1 0 00 and BOOTSEL2 1 0 101 Table 2 3 DIP switch 3 Switch Pin Signal Name Function 11 Boot Device Select amp Clock Select HPS_UARTO_RX Default CLKSELO 0 1 HPS_GPIO62 Off CLKSEL1 1 On CLKSEL1 0 2 HPS_SPIMO_CSO0n Off BOOTSELO 1 On BOOTSELO 0 3 QSPI_SSO Off BOOTSEL1 1 On BOOTSEL1 0 4 HPS_GP1IO28 Off BOOTSEL2 1 On BOOTSEL2 0 The figure shown below is the configurations of CSEL and BSEL provided in Cyclone V datasheet Copyright 2014 Embest Technology Lark Board User Manual mbes Embest Technology 32 oscl_clk EOSC1 pin nand_x_clk 25 device frequency range 10 50 MHz oscl_clk 25 2 MHz max 10 12 5 MHz 9 6 MHz max oscl_clk 20 25 12 5 25 MHz 9 6 MHz max oscl_clk 10 25 25 50 MHz oscl_clk 5 25 9 6 MHz max mpu_clk PLL modes nand_x_clk controller clock oscl_clk 50 MHz max oscl_clk 20 240 MHz max oscl_clk 50 MHz max 400 MHz max Locked oscl_clk 32 osc1_clk 10 240 MHz max oscl_clk 16 400 MHz max Locked Figure 2 8 CSEL pin oscl_clk 5 240 MHz max oscl_clk 8 400 MHz max Locked a C on FPGA HSA FPGRBRG OOO C oe BV NANO Tash memory O oe eov C oa 18 SDMMG fash memory vith eternal vansceker C o6 80V SD MMC fash memory with intera transc
84. num 0 for i 0 i lt POINT i calculateamplitude result i sqrt s i real s i real s i imag s i imag 2 POINT val int result i if result i gt max amp amp i lt POINT 2 max result i max_num i s i real 4096 sin TWOPI SIMULATION_FREQ i write_len fwrite amp val sizeof int 1 resfp save to file Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 77 write_len fwrite amp val sizeof int 1 srcfp if write_len 1 perror Save input sine wave to file has failed n goto error_out printf 0x 8x val if i amp amp i 1 16 0 printf n freq SIMULATION_FREQ POINT max_num printf n d frequency f amplitude f n max_num freq max error_out fclose srcfp fclose resfp return 0 Please execute the following instruction to compile FFT application source code e arm linux gnueabihf gcc fft c Im o fft Then execute the following instruction to run the application fft in_data out_data 4 9 3 DS 5 Debugging ARM DS 5 is an integrated development environment that supports the development on all the ARM processor core based chips Altera s DS 5 only supports Altera SoC and features tracking system performance analyzer applications of real time system emulator and compiler and core space debugger DS 5 is included in SoC EDS and thus there i
85. part from change in resolution of FPGA project Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 72 4 9 Application Development and DS 5 Debugging This section will introduce application development under Linux system through two examples a LED application and a FFT application and also talk about debugging in DS 5 IDE at the end of this section 4 9 1 Development of LED Application This application realizes blinking of LED indicators by operating the file sys class leds hps_led d brightness The following table contains the source code of the application Table 4 16 LED application include lt stdio h gt include lt sys ioctl h gt include lt sys time h gt include lt sys types h gt include lt fentl h gt include lt unistd h gt include lt stdlib h gt include lt errno h gt void setLEDBrightness int ledno int brightness FILE fp char dir 100 char brightness_char 10 sprintf dir sys class leds hps_led d brightness brightness if fp fopen dir w NULL printf Failed to open the file s n dir else fwrite brightness_char 1 sizeof brightness_char fp fclose fp Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 73 int main int argc char argv while 1 setLEDBrightness setLEDBrightness setLEDBrightness setLEDBrightness sleep 1 setLEDBrightnes
86. pressed Linux kernel image Partition 2 EXT3 various Linux root filesystem Preloader bin Preloader image Partition 3 RAW U boot img U boot image After learning about the partitions and files of a TF card you are ready to update anyone of the partitions The following table contains instructions that used to do so Table 4 4 Instructions to update partition File to Be Updated Instructions to Be Used zlmage Use the following instructions to mount the first partition of TF card and replace the files with new ones one by one soc_system rbf i sudo mkdir mnt sdcard socfpga_cyclone5 dtb e sudo mount dev sdx1 mnt sdcard sudo cp lt file_name gt mnt sdcard u boot img Copyright 2014 Embest Technology Lark Board User Manual beck Embest Technology 55 File to Be Updated Instructions to Be Used preloader bin sudo dd if preloader bin of dev sdx3 bs 64k seek 0 root filesystem sudo dd if yocto_rootfs ext3 of dev sdx2 Note soc_system rbf is a configuration file for FPGA Please refer to 4 4 3 Generating FPGA RBP for the information of how to make the file Users can obtain the files listed in the table above from prebuild sd_card directory of the development package provided by Embest Writing Debian Images into TF Card A Debian filesysetm image has been included in Embest s development package
87. r to lark_cam sys of project source code aL Qsys lark_cam qsys E O2code lark_v2 lark_camera cam_sdi lark_cam qsys File Edit System Generate View Tools Help Clocked Video Input Clock Input Reset Input Conduit INi Lato clock reset ind Clock Input Reset Input Avalon Streaming Sink Avalon Streaming Source lsc Clock Input Reset Input Avalon Streaming Sink Avalon Streaming Source alt vip_csc_0 do1 Avalon Streaming Source avalon_streaming_source 13 1 Ox1004_1000 ox1004_107 Avalon Streaming Source Avalon Memory Mapped Master Clocked Video Output Clock Input Reset Input Avalon Streaming Sink Conduit Figure 5 17 Connections between control and data signals In addition there is an option named user control during the use of IP core This option allows access to IP core through HPS under Linux system By configuring the registers provided by IP core or reading the status of the registers software can implement operations and control over IP core Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 92 5 3 3 LCD VGA HDMI Video Output Lark Board provides LCD VGA and HDMI video output modes These modes share the same source the output from FPGA The following contents wil
88. rtus II is a comprehensive PLD FPGA development software tool from Altera with support to multiple design formats such as schematics VHDL VerilogHDL and AHDL Altera Hardware Description Language It has a built in synthesizer and emulator which can accomplish the whole PLD development process from design input to hardware configurations Altera SoC EDS contains development tools such as cygwin cross compiler DS 5 and mkpimage to help users quickly start the development of firmware and applications Note 4 There two versions for both Quartus II and SoC EDS Subscription and Web version The former version needs to be purchased for use with full functionalities the later one can be used for free but with limited functionalities A 30 day trial of Subscription version is available with full functionalities LQ Each instruction has been put a bullets before it to prevent confusion caused by the long instructions that occupy more than one line in the context L Please note that there are SPACES put in the following instructions Missing any SPACE will lead to failure when running an application 4 3 1 Building Linux Development Environment 1 Install a Linux system on your PC Ubuntu 12 04LTS or the latest officially released version is recommended 2 Visit http www rocketboards org foswiki Documentation GSRD131 GettingStartedYo cto to download and install Altera Yocto package Copyright 2014 Embest Technology
89. s no need to download it separately DSS 5 supports debugging of preloader and u boot as well as Linux kernel and applications For detailed information on debugging please refer to Altera s SoC EDS Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 78 manual at htto www altera com literature ug ug soc eds pdf Copyright 2014 Embest Technology Lark Board User Manual mbesh Embest Technology 79 Chapter 5 FPGA This chapter will briefly introduce the FPGA resources included in Altera Cyclone V SoC used on Lark Board and will show you the detailed information about the FPGA function implemented on Lark Board as well as the process of FPGA development introduced by using an example 5 1 FPGA Resources Lark Board uses a SoC from Cyclone V SX family with a code name 5CSXCE6 which possesses the richest resources among all the family members The following table shows a comparison among all the members of the family on their resources Table 5 1 Cyclone V SX SoC resources Resources 5CSXC2 5CSXC4 5CSXC5 5CSXC6 Core ARM Cortex A9 MPCore Dual core Dual core Dual core Dual core LE K 25 40 85 110 ALM 9 434 15 094 32 075 41 509 M10K memory blocks 140 270 397 557 M10K memory Kb 1 400 2 700 3 972 5 570 MLAB Kb 138 231 480 621 18x18 multipliers 72 116 174 224 Variable precision DSP blocks 36 58 87 112 Maximum transcei
90. s setLEDBrightness setLEDBrightness setLEDBrightness sleep 1 return 0 4 9 2 Development of FFT Application The following table contains the source code of a simple FFT application This application uses sampling points generated by sin library function as the input Of course the sampling output from ADC of Lark Board can be used for calculation too as long as the sin analog input is replaced with ADC s sampling data Table 4 17 FFT application include lt math h gt include lt stdio h gt include lt stdlib h gt include lt errno h gt define SIMULATION_ FREQ 30000000 0f define SAMPLE_FREQ 100000000 0f define PI 3 14159f define TWOPI 6 2831 853f define POINT_1024 1024 define POINT POINT_1024 struct complex double real double imag Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology complex float result POINT struct complex s POINT struct complex EE struct complex c1 struct complex c2 struct complex c3 c3 real c1 real c2 real c1 imag c2 imag c3 imag c1 real c2 imag c1 imag c2 real return c3 r fft function xin is input buff N is the number of fft dot z void fft structcomplex xin intN int f m LH nm i k j L int le B ip double p ps struct complex w t LH N 2 lefthand f N for m 1 f f 2 13m 24m N POINT_1024 m 10
91. s no need to modify the configurations under most circumstances The following instructions are used only if the default settings of u boot have been changed and need to be restored SOCFPGA_CYCLONES5 setenv dispmode VGA Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 66 SOCFPGA_CYCLONES5 saveenv 4 7 2 Configuring for 7 LCD Execute the following instructions under u boot to configure settings for 7 LCD SOCFPGA_CYCLONES5 setenv dispmode LCD7 SOCFPGA_CYCLONES5 saveenv 4 7 3 Configuring for 4 3 LCD Execute the following instructions under u boot to configure settings for 4 3 LCD SOCFPGA_CYCLONE5 setenv dispmode LCD4 _ 3 SOCFPGA_CYCLONES5 saveenv 4 8 Example Applications This chapter will introduce how to test the devices on Lark Board by using example applications included in the Linux system please note the following contents are based on the premise that Lark Board boots from a TF card hence it might be necessary for you to install Linux system on a TF card by using the first method in 4 5 1 Updating Images in TF Card 4 8 1 LED Test The HPS can control D27 D30 LED indicators on Lark Board Please execute the following instructions in PUTTY terminal window to implement LED test D27 is attached to hps_ledO D28 to hps_led1 D29 D30 are handled in a similar pattern root socfpga_cyclone5 echo 1 gt sys class leds hp
92. s of SDI IP core 2 Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 99 a 5 ies z MegaWizard Plug In Manager SDI el Lao ao pocumertaten Protocol Options Transceiver Options Receiver Transmitter Options Receiver Options O CRC error output O SDI synchronization output Tolerance to consecutive missed EAV SAV 10 E Transmitter Options Figure 5 27 Configurations of SDI IP core 3 5 3 5 Input Data from ADC Lark Board has two set of SMD hardware interfaces Since the hardware does not support LVDS differential input CMOS single ended input is adopted currently The data flowing to FPGA comes from the on board chip AD9628 which produce digital signal embedded with data clock Please refer to the source code in BSP linux 3 10 Itsi drivers char adc9628 c for the register configurations of AD9628 The data comes from a signal generator that is connected to SMA is sent to AD9628 and then FPGA and finally goes into SRAM There are two processing approaches for the stored data the first is a method applied inside FPGA the stored data will be processed with Digital Down Conversion DDC and then fetched at a variable rate by a Cascade Integrator Comb CIC the second is reading the data via HPS by software and then getting it under Fast Fourier Transformation FFT to see if the data frequency calculated is consistent with the anticipated Lark Board adopts the
93. s_led0 brightness root socfpga_cyclone5 echo 1 gt sys class leds hps_led1 brightness root socfpga_cyclone5 echo 1 gt sys class leds hps_led2 brightness root socfpga_cyclone5 echo 1 gt sys class leds hps_led3 brightness root socfpga_cyclone5 echo 0 gt sys class leds hps_led0 brightness Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 67 root socfpga_cyclone5 echo 0 gt sys class leds hps_led1 brightness root socfpga_cyclone5 echo 0 gt sys class leds hps_led2 brightness root socfpga_cyclone5 echo 0 gt sys class leds hps_led3 brightness Figure 4 13 D27 D30 on Lark Board 4 8 2 Button Keypad Test HPS can receive and process the input signals from buttons S3 S6 on Lark Board The buttons are driven by gpio_keys_polled driver of the kernel Please execute the following instructions in PUTTY terminal window to implement test root socfpga_cyclone5 cd root socfpga_cyclone5 key_test When pushing the buttons one by one the following information will be printed in PUTTY terminal window Table 4 11 Information returned when pushing buttons keycode is 103 value is 1 keycode is 103 value is 0 keycode is 104 value is 1 keycode is 104 value is 0 keycode is 105 value is 1 Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 68 keycode is 105 value is 0
94. second approach AD9628 uses SPI bus for configuration The bus has three signal lines clock signal chip selection signal and dual direction data signal It is not working with standard SPI protocol Lark Board utilizes GPIO output to emulate SPI time sequence so that register configurations for ADC can be accomplished The PIO IP core is used for dual direction Copyright 2014 Embest Technology Lark Board User Manual bos Embest Technology 100 input and output operations The following figure is a PIO configuration window Tk PIO Parallel 1 0 Megatore altera_avalon_pio i Block Diagram z 7 Basic Settings Sher cr opel Width 1 32 bits 4 Direction pio_rp_reset ee Input Indut Output Output Port Reset Value 0x0000000000000000 Output Register altera_avalon_pio Enable individual bit setting clearing Edge capture register Synchronously capture Edge Type RISING Enable bit clearing for edge capture register Interrupt E Generate IRQ IRQ Type LEVEL Level Interrupt CPU when any unmasked I O pin is logic true Edge Interrupt CPU when any unmasked bit in the edge capture register is logic true Available when synchronous capture is enabled Figure 5 28 PIO configurations Additionally AD9628 can be set to test mode under which FPGA receives test data without the need to connect SMA interface 5 3 6 PCle Function
95. system image as well as schematics and key chips datasheets to help users implement evaluation and secondary development fast 1 1 1 Packing List Lark Boardx1 USB cable for FPGA programming and controlx1 Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 2 19V DC power adapterx1 8GB TF cardx1 12V DC Fan 1 1 2 Product Features General Specifications Operating Temperature 0 C 70 C Power Supply 12 20V Operating Humidity 20 90 Dimensions 180mm x 120mm PCB Layers 10 layer PCB SoC Specifications FPGA up to 110K logic cells LE 5570 M10K 621 MLABs 112 variable precision DSP blocks 224 18x18 multipliers 6 PLLs 288 IOs 72 72 LVDS transceiver and a memory controller HPS a dual core ARM Cortex A9 MPCore processor a memory controller DDR3 3 PLLs and 181 general IOs as well as a rich set of peripheral interfaces such as UART 12C USB SPI GPIO and EMAC High speed transceiver includes 2 PCle hard IPs and 9 3Gbps transceivers On Board Memories 1GB DDR3 SDRAM for HPS 1GB DDR3 SDRAM for FPGA 4GB eMMC Flash Data Transfer Interfaces A SDI high resolution serial digital interface that supports SMD standard interface and provides a SDI TX and a SDI RX A 12 bit digital camera input Two 12 bit high speed ADC interfaces that support SMA input A PClex4 connector for PClex4 PClex2 and PClex1 adapter cards A RJ45 interface
96. te mmc 0 1 0x1000000 u boot img uboot_size Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 60 6 Execute the following instructions to update kernel and DTB file tftp 0x1000000 socfpga_cyclone5 dtb fatwrite mmc 0 1 0x1000000 socfpga_cyclone5 dtb dtb_size tftp 0x1000000 zlmage fatwrite mmc 0 1 0x1000000 zlmage zlmage_size Note When using fatwrite to update kernel and DTB file the uboot_size dtb_size and zlmage_size should be replaced with the actual bytes of the file represented in HEX for example zimage has a size of 1MB so zZilmage_size should be replaced with Ox100000 7 Execute the following instructions to update Yocto filesystem tftp 0x1000000 yocto_rootfs ext3 mmc write 0x1000000 0x3800 0x48bb4 4 6 Introduction to Drivers The 0x48bb4 above stands for file size with unit in blocks 1 block 512byte This chapter will introduce the main drivers contained in the system kernel of Lark board and their source code paths The working principle of MMC SD Frame Buffer and ADC drivers will be covered too The following table contains descriptions for the main drivers and the path to their source code Table 4 7 Drivers Names Descriptions Source Code Path linux 3 10 ltsi drivers tty serial 8250 8 Serial Serial interface driver 250_dw c RTC Hardware clock driver linux 3 10 ltsi drivers rtc rtc ds 1307 Device P 10 100M
97. te the whole system 1 Create a folder named emmc under the root directory of your flash drive and copy emmc_rootfs tar bz2 preloader bin u boot img socfpga_cyclone5 dtb and zlmage under prebuild emmc of Embest s development package or the images made by yourself into the folder as shown below tana emmc_rootfs tar bz2 preloader bin socfpga_cycioneS u boot img zimage dtb Figure 4 8 Files in flash drive The following table contains descriptions for these files Table 4 5 File descriptions Files Descriptions emmc_rootfs tar oz2 Packaged EXT filesystem preloader bin Preloader u boot img U boot image socfpga_cyclone5 dtb DTB file zlmage Kernel image 2 Copy ramdisk gz uboot under prebuild emmc to the FAT partition of the TF card 3 Connect your flash drive and the TF card to Lark Board and power on the board and then press any key on PC s keyboard before the Putty window starts countdown in seconds to enter u boot mode 4 Execute the following instructions under U boot mode run ramload run fpgaload run bridge_enable_handoff Remove the TF card if the TF card stays in the slot the files would be written Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 58 into the card instead and then execute the following command run ramboot Note 2 The pre built kernel will access FPGA resources by default so FPGA confi
98. that supports RGMII gigabit Ethernet Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 3 e Four high speed USB2 0 Host interfaces e ATF card slot TF card and eMMC flash cannot be used simultaneously e A 40 pin FPGA expansion interface for LVDS RSDS SLVS mini LVDS signals e A 40 pin HPS expansion IO for 12C SPI QSPI UART GPIO signals Debugging Interfaces e An on board USB Blaster II Mini USB Type B e A 10 pin JTAG interface can be used to connect an external USB Blaster e Support UART serial debugging Audio Video Interfaces e A 24 bit true color LCD interface supporting 4 wire touch screen e AVGA interface e AHDMI interface Other Interfaces amp Buttons e A power jack 12V 30V round DC power jack and ATX 4 pin standard power connector e Areset button and 5 user defined buttons e ARTC Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 4 UART Convert 4 3 LCD y Cable USB to TTL or7 LCD Digital Camera oe USB Blaster er WIFI Module USB Keyboard gt Flash Disk USB Mouse Figure 1 1 Interfaces and Buttons 1 2 System Block Diagram DDR3 512MB x2 24Bit RGB LCD LarK Board amp 4 wire res TP I F Digital Camera _12C SPI HDMI 24t reb FRAME VGA AMP M o ADC SMA f ave Cyclona V DDR3 ZX ANZTS YAA SMB spi Tx im ae 5CSXFC6D pom sp D a m Host2 0 x4 tcktdi tdo tms 2 XCVRx
99. tions The following figure shows the working flow inside CH7033B SDRAM RGB YCbCr Input format decoder Video Format 80 86 MPU interface DE SPDIF decoder ns decoder E TMDS TERC4 _ encoder Differential serializer Audio packet org Registers RC slave EDID MCL Working flow inside CH7033B EDID buffer Figure 5 21 FPGA Register Configurations DACO DAC DAG TLOWTLC THCOVIDCO TOCI VIDC TDC2 TDC2 DDC_SC DDC_sD IRQ SPCM SPDM In order to facilitate control and altering configurations by software for video output FPGA provides three configurable register interfaces The configurations include resolution clock selection and width of various synchronization signals please refer to the source code linux drivers video larkboardfb c for details The output clocks for different resolutions are listed below 1024x768 65Mhz output clock 800x480 7 inch 30Mhz output clock Lark Board User Manual PF abesk Embest Technology 95 480x272 4 3 inch 10Mhz output clock 4 HDMI 12S Audio Output Audio data from FPGA is processed by CH7033 which then sends it out to HDMI bus FPGA adopts 24 bit mono output that is the format supported by CH7033 The lower 16 bits of the output are the valid audio data The audio output is sinusoidal waveforms with 350Hz and 440Hz respectively for left and right channel The following figure s
100. to the instructions in the documents provided by Embest Technology Helping customers troubleshoot the products O The following conditions will not be covered by our technical support service We will take appropriate measures accordingly Customers encounter issues related to software or hardware during their development process Customers encounter issues caused by any unauthorized alter to the embedded operating system Customers encounter issues related to their own applications Customers encounter issues caused by any unauthorized alter to the source code provided by Embest Technology Warranty Conditions 1 12 month free warranty on the PCB under normal conditions of use since the sales of the product Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 105 2 The following conditions are not covered by free services Embest Technology will 3 charge accordingly Customers fail to provide valid purchase vouchers or the product identification tag is damaged unreadable altered or inconsistent with the products Products are damaged caused by operations inconsistent with the user manual Products are damaged in appearance or function caused by natural disasters flood fire earthquake lightning strike or typhoon or natural aging of components or other force majeure Products are damaged in appearance or function caused by power fa
101. ts acaninca fected cde cos ccucndaecece detains esecettdndas 70 Application Development and DS 5 Debugging eeeeeeeereeeeeeteeeeeeeeee 72 4 9 1 Development of LED Application 72 Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology v 4 9 2 Development of FFT Application eeeeesceesseeeeeeeeeeneeeeeneeeees 73 4 9 3 BES Sod 1 61 0 1a eee eee NDR INCE EE neem note a net Eee me in 77 Chapter 5 FPGA eiteseteceinantsanciisndnnndctdesstanadineninatanasenadenadinadenuseusdevasdacdacecanedeussinatinaienadenss 79 5i FPGA RESoUrcES ene ee EE 79 5 2 FPGAD v l pmeMt scese een i eee esaa 79 5 2 1 Building FPGA Project and Programming SOF File into FPGA 80 5 2 2 Elipse Debugging eeecceeseeeeseeeteeeceseeeeeeneneneseeessneneneneneneetenes 83 5 3 FPGA Function Implementation on Lark Board 87 5 3 1 inputot Camera VIGGO ci eae 87 5 3 2 Output of Camera VI oa ac ee ace loadsa en sn tna ees 89 5 3 3 LCD VGA HDMI Video Output ccceeceeeeeeeeeeeeeeeeeteeeneeeeeenees 92 5 3 4 Input output of SDI Video jem mem mene ine mee tn nne met nen arian seer near enr aa 95 5 3 5 Input Data from ADC Seen erm ere ee nr err eee tT eter e ee eene et ater see aterm acre 99 5 3 6 PUES FUN TO as eae ee 100 Technical Support and Warrannty sssscsssessessecsnesseseessessnessnssessessnersnssesseesnersnsees 104 Copyright 2014 Embest Technology Lark Board User Manua
102. vers 6 6 9 9 PCI Express PCle hard IP block 1 1 1 1 Maximum HPS I Os 181 181 181 181 Maximum FPGA user I Os 145 145 288 288 Maximum FPGA LVDS 66 66 144 144 HPS PLLs 3 3 3 3 FPGA PLLs 5 5 6 6 HPS hard memory controllers 1 1 1 1 FPGA hard memory controllers 1 1 1 1 5 2 FPGA Development FPGA development needs to be done on Quartus II platform This platform integrates a Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 80 series of tool chain including Qsys Nios Il Software Building Tools for Edipse MegaWizard Plug In Manager Programmer and SignalTap II Logic Analyzer supporting a complete PLD development process from design input to hardware configurations Quartus II can be downloaded from https www altera com download sw dnl sw index jsp There are two versions available for Quartus Il one is Web version and the other is Subscription version Please use the latter one to carry out FPGA development This document will not include the guide of using Quartus because Altera has provided a complete tutorial for the software at http www alteraforum com cn showtopic 75 aspx This section will take the project lark_cv_cam_sdi as the example to briefly introduce the development of FPGA camera Hardware required here includes a camera module and a 7 LCD CAM8000 D will be the camera module used in the following contents 5 2 1 Building FPGA Project and Programming
103. wer switch design on Lark Board Copyright 2014 Embest Technology Lark Board User Manual a Embest Technology 26 eMMC Interface eMMC and TF card share the MMC SD controller of HPS so they work on the same clock lower 4 bit data and control signal but the higher 4 bit data is reserved for eMMC The following table contains pin definitions of eMMC interface Table 2 14 eMMC interface eMMC between HPS amp Device Pin Bank Device Signal Name Signal Type G18 7C IO MMC_DATO C17 7C IO MMC_DAT1 D17 7C IO MMC_DAT2 B16 7C IO MMC_DAT3 H17 7C IO MMC_DAT4 maa C18 7C IO MMC_DAT5 G17 7C IO MMC_DAT6 E18 7C IO MMC_DAT7 A16 7C Out MMC_CLK Clock F18 7C Out MMC_CMD B17 7C Out MMC_CD ane TF Card Interface The TF1 interface on the back of Lark Board is a TF card slot The following table contains pin definitions of the interface Table 2 15 TF card interface TF card connector TF1 Pin Signal Name Device Signal Type 1 MMC_DAT2 5CSX6F6D Data 2 MMC_DAT3 5CSX6F6D 3 MMC_CMD 5CSX6F6D Command 4 3 3V_VDD Power 3 3V 5 MMC_CLK 5CSX6F6D Clock 6 GND Ground 7 MMC_DATO 5CSX6F6D Da ata 8 MMC_DAT1 5CSX6F6D 9 MMC_CD 5CSX6F6D Command 10 GND Ground 11 GND Copyright 2014 Embest Technology Lark Board User Manual PF abesk Embest Technology 27 TF card connector TF1 12 GND 13 GND 14 NC

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