XEM6110 User`s Manual
Contents
1. p e Clock Configuration Source Synchronous The DDR2 clocking is designed to be source synchronous from the FPGA This means that the FPGA sends the clock signal directly to the SDRAM along with control and data signals allowing very good synchronization between clock and data Memory Controller Blocks Spartan 6 has integrated memory control blocks to communicate with the external DDR2 mem ory on the XEM6110 This is instantiated using the Xilinx Core Generator memory interface generator or MIG to create a suitable memory controller for your design You should read and become familiar with the DDR2 SDRAM datasheet as well as MIG and the core datasheet Al though MIG can save a tremendous amount of development time understanding all this informa tion is critical to building a working DDR2 memory interface The XEM6110 provides 1 2v as Vccint According to the memory controller block documentation the Spartan 6 2 speed grade can operate memory to 312 5 MHz with this internal voltage 12 www opalkelly com XEMG6110 User s Manual MIG Settings JTAG The following are the settings used to generate the MIG core for our RAMTester sample using Xilinx Core Generator These settings were used with ISE 12 2 and MIG 2 3 Note that settings may be slightly different for different versions of ISE or MIG Frequency 312 5 MHz Memory Type Component Memory Part MT47H64M16XX 3 1Gb x16 Data Width 16 Enable DQS Enable2. T s memo bp wer jaa 7 ps pw s Joen e ue Oe os zz Jioni ee o Ier Josi Da ps oeo LL o Joen T o o Jo m Je Clock Signal FPGA Pin OSC P IO L32P GCLK29 2 OSC N IO L32N GCLK28 2 AB11 20 www opalkelly com XEM6110 User s Manual XEM6110 Quick Reference JP2 Length Pin Connection FPGA Pin mm DE A EE smt A 5 VDC 1 8VDD 3 3VDD 3 3VDD 3 3VDD W20 W22 U19 V20 N ojo E N p 7038 20 080 22 106 25 362 25374 25 971 N Kei 35 ets ES ES si 17036 20080 18 7 25 00 22706 25362 EN 23285 Ga 25 374 25971 18 067 ES 18 060 Eee E Pin Connection mm PAP a mawo s haw J s His l n 41328 pra pew O 32 ps hro 90242 a eo so 86 ipo Dien 12 356 IS ISE www opalkelly com 21
3. 17 USB 2 0 PCI EXpreSS suits beh Fe a 17 Cypress PLL FPGA based PLLs 17 C Connections FPGA based DC Controller 17 Four I O Banks Two I O BankS 17 DC Power Connector Expansion Connectors 17 32 MiB SDR SDRAM gt 128 MiB DDR2 SDRAM 17 XEM6110 Mechanical Drawing 18 BRK6110 Mechanical Drawing 19 XEM6110 Quick Reference 20 XEM6110 Quick Reference 21 Contents XEMG6110 User s Manual 4 www opalkelly com XEM6110 User s Manual Introducing the XEM6110 The XEM6110 is a compact FPGA board featuring the Xilinx Spartan 6 FPGA It is an external 1 lane PCI Express device capable of live reconfiguration without powering down the con nected host and high speed communication Designed as a full featured integration system the XEM6110 provides access to over 110 I O pins on its 484 pin Spartan 6 device and has a 128 MiByte DDR2 SDRAM available to the FPGA The XEM6110 is designed to work with medium sized FPGA designs with a wide variety of external interface requirements PCB Footprint A mechanical drawing of the XEM6110 is shown at the end of this manual The PCB is 75mm x 50mm with four mounting holes M2 metric screws spaced as shown in the figure These mounting holes are electrically isolated from all signals on the XEM6110 The PCI Express con nector Molex 74960 3018 is mounted flush to the
4. 66 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin mappings for JP2 are listed at the end of this document in the Quick Reference section For each JP2 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair I www opalkelly com 13 XEM6110 User s Manual 14 Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs Setting I O Voltages The Spartan 6 FPGA allows users to set I O bank voltages in order to support several different I O signalling standards This functionality is supported by the XEM6110 by allowing the user to connect independent supplies to the FRGA VCCO pins on two of the FPGA banks By default ferrite beads have been installed which attach each VCCO bank to the 3 3VDD supply If you intend to supply power to a particular I O bank you MUST remove the appropriate ferrite beads Power can then be supplied through the expansion connectors The table below lists details for user supplied I O bank voltages I O Bank Ferrite Bead o ue2as se Hi LE Considerations for Differential Signals The XEM6110 PCB layout and routing has been designed with several applications in mind including applications requiring the use of di
5. 8v To turn ON an LED the FPGA pin should be brought low To turn OFF an LED the FPGA pin should be at high impedance NOTE Because the bank voltage is 1 8v and the LEDs are connected to 3 3v it is important to tri state set to high impedance the FPGA outputs in order to turn off an LED Sending the FPGA output to logic 1 may damage the FPGA The example Verilog code provides proper signals to the LED outputs function 7 0 xem6110 led input 7 0 a integer i begin for i20 i 8 i i 1 begin u xem6110 led i a i 1 b1 1 b0 1 bz end end endfunction assign led xem6110_led count Output counter value to LEDs Low Jitter 100 MHz Crystal Oscillator A 100 MHz crystal oscillator with LVDS output is attached directly to the FPGA on pins Y11 and AB11 Bank 2 The oscillator is a Crystek CCLD 033 50 100 000 or equivalent and features 50ppm frequency stability and phase jitter of O 5ps typical 1ps RMS max over 12 kHz to 80 MHz The differential input can be converted to a single ended clock signal by instantiating an IBUF GDS component as shown in the Verilog below IBUFGDS IOSTANDARD LVDS_25 osc_clk OCclIO ICsys_clkp IBCsys_clkn www opalkelly com 11 XEM6110 User s Manual DDR2 SDRAM The Micron DDR2 SDRAM is connected exclusively to the 1 8 v I O on Bank 3 of the FPGA The tables below list these connections p NS 5 e p e
6. HIB which is inserted into the PC in a x1 PCI Express slot Both the XEM6110 and PCI1001 contain devices which equalize and retime the high speed se rial signals to improve signal integrity These devices can require different equalization settings depending on the cable length between the PCI100 and XEM6110 On the XEM6110 these settings are determined by jumpers on the header JP3 On the PCI1001 these settings are determined by jumpers on the header JP1 The jumper setting should be the same on both devices For a given cable length insert a jumper between the pins as indicated in the table below Insert the jumper where a solid circle is indicated Remove the jumper where a hollow circle is indicat ed By default all boards are shipped with all jumpers installed 3 meter cable selected www opalkelly com 15 XEM6110 User s Manual Cable Length MolexP N 1 2 3 4 5 6 meter 1745760001 o o o 3meters 745760003 e e e 5 meters 745760008 o e 0 7 meters 745760007 o eje 16 www opalkelly com XEMG6110 User s Manual Differences Between the XEM3010 and XEM6110 The XEM6110 was designed to be as compatible as possible with our XEM3010 in order to facilitate customer design migration with minimal changes The differences between these two products are highlighted below USB 2 0 PCI Express The most dramatic upgrade is the 1 lane PCI Express interface which replaces the USB 2 0 in
7. PCB edge The XEM6110 has two high density 80 pin connectors on the bottom side which provide access to many FPGA pins power and JTAG BRK6110 Breakout Board A simple breakout board the BRK6110 is provided as an optional accessory to the XEM6110 This breakout board provides DC power and easy access to the high density connectors on the XEM6110 by routing them to lower density 2mm spaced thru holes The breakout board also provides a convenient reference for building boards that will mate to the XEM6110 Opal Kelly reserves the right to change the form factor and possibly pinout of the BRK6110 Therefore unlike the XEM6110 it is not intended or recommended for production integration www opalkelly com 5 XEM6110 User s Manual Full schematics and Gerber artwork files for the BRK6110 are provided free of charge If your application depends on the existing form factor you may reproduce this board from these docu ments A mechanical drawing of the BRK6110 is also shown at the end of this document DDR2 SDRAM 128 MiB Spartan 6 FPGA Host Interface XC6SLX45 2FGG484 Bus ls 1 0 63 1 0 FL LEDs Low Jitter o gt Samtec Expansion Connector Samtec Expansion Connector Functional Block Diagram PCle 100 MHz Power Supply The XEM6110 is designed to be operated from a 5 volt power source supplied through the ex pansion connectors on the bottom of the device This provides power for the three high efficien cy
8. of a 2 Amp switching regulator on the XEM6110 VCCOO is the bank 0 I O voltage to the FPGA Factory default is 3 3v VCCO1 is the bank 1 I O voltage to the FPGA Factory default is 3 3v Power Budget The table below can help you determine your power budget for each supply rail on the XEM6110 All values are highly dependent on the application speed usage and so on Entries we have made are based on typical values presented in component datasheets or approximations based on Xilinx power estimator results Shaded boxes represent unconnected rails to a particular component Empty boxes represent data that the user must provide based on power estimates The user may also need to adjust parameters we have already estimated such as FPGA Vcco values where appropriate www opalkelly com 9 XEM6110 User s Manual Componenti iw pa 8 pma ETT fow EPGAW Ed ELECTO IO ow FPGA Vecos DDRZ es EE E FPGAVccoo PCle est s00mw FPGAVeo Cd Cd PT tote E Supply Heat Dissipation IMPORTANT Due to the limited area available on the small form factor of the XEM6110 and the density of logic provided heat dissipation may be a concern This depends entirely on the end application and cannot be predicted in advance by Opal Kelly Heat sinks may be required on any of the devices on the XEM6110 Of primary focus should be the FPGA U10 the two PCle interface devices U1 U2 and the SDRAM U
9. switching regulators on board to provide 3 3v 1 8v and 1 2v 0 9v is derived from the 3 3 volt supply using a small low dropout LDO regulator for use as a DDR2 termination voltage Each of the three switching regulators can provide up to 2A of current PCI Express 1 1 Interface The XEM6110 is an external 1 lane PCI Express device which connects to a supporting host computer using a standard PCI Express cable A repeater equalizer inside the host computer converts the backplane PCI Express into the cabled standard The Opal Kelly PCI1001 host interface board is used for this conversion As a PCI Express peripheral the XEM6110 is supported by the Opal Kelly PCI Express driver The Opal Kelly FrontPanel Application and FrontPanel API can be used to download configura tion bitfiles to the FPGA after the host computer has booted After FPGA configuration high speed communication between the host and XEM6110 is enabled The FPGA may be reconfig ured any number of times without rebooting the host computer 6 www opalkelly com XEMG6110 User s Manual XEM6110 FPGA Integration Module PCI1001 Host Interface Board On board Peripherals The XEM6110 is designed to compactly support a large number of applications with a small num ber of on board peripherals These peripherals are listed below Low Jitter Crystal Oscillator A fixed frequency 100 MHz low jitter crystal oscillator is include on board and outputs LVDS to the FPGA The S
10. 11 Although the switching supplies are high efficiency they are very compact and consume a small amount of PCB area for the current they can provide If you plan to put the XEM6110 in an enclosure be sure to consider heat dissipation in your de sign Host Interface 10 There are 57 signals 29 inputs and 28 outputs that connect the on board PCI Express bridge to the FPGA These signals comprise the host interface on the FPGA and connect to the host interface IP provided by Opal Kelly that you incorporate into your HDL design A number of synthesis and mapping constraints must be used to properly map the signals to pin locations I O standards and other timing requirements Each of the samples installed with FrontPanel includes a copy of a template constraints file that lists all the XEM6110 pins and maps them to the appropriate FPGA pins using LOC location constraints You can use this template to quickly get the pin locations correct on a new design PCI Express The XEM6110 is a PCI Express peripheral which connects to the PC using the external PCI Express cabling to a host interface board HIB which resides inside the PC The HIB plugs into one of the standard 1 lane PCI Express slots of a typical desktop motherboard Although the XEM6110 is an external device it should generally be treated as an internal device in some respects Notably external PCI Express devices must be powered up before booting the PC and must remain powe
11. 7 s Opal Kelly XEM6110 User s Manual A compact 75mm x 50mm integration board featuring the Xilinx Spartan 6 FPGA external PCI Express and on board SDRAM The XEM6110 is a compact external PCI Express FPGA integration module featuring the Xilinx Spar tan 6 FPGA 1 Gb 64 Mx16 bit DDR2 SDRAM high efficiency switching power supplies and two high density 0 8 mm expansion connectors The external PCI Express interface provides fast configuration downloads without requiring a PC reboot and PC FPGA communication as well as easy access with our popular FrontPanel application and SDK A low jitter 100 MHz oscillator is also on board Software documentation samples and related materials are Copyright 2010 2011 Opal Kelly Incorporated Opal Kelly Incorporated Portland Oregon http www opalkelly com All rights reserved Unauthorized duplication in whole or part of this document by any means except for brief excerpts in published reviews is prohibited without the express written permission of Opal Kelly Incorporated Opal Kelly the Opal Kelly Logo and FrontPanel are trademarks of Opal Kelly Incorporated Linux is a registered trademark of Linus Torvalds Microsoft and Windows are both registered trademarks of Microsoft Corporation All other trademarks referenced herein are the property of their respective owners and no trademark rights to the same are claimed Revision History Date Description J 20101201 Initial rele
12. CHECKED High temp self refresh DISABLED Output drive strength Reducedstrength RTT nominal 50 ohms default DCI for DQ DQS CHECKED DCI for address control CHECKED ZIO pin Y2 RZQ pin K7 Calibrated Input Selection Yes Class for address control Class Il Debug signals Your option System clock Differential The JTAG connections on the FPGA are wired directly to the expansion connector JP1 on the XEM6110 to facilitate FPGA configuration and ChipScope usage using a Xilinx JTAG cable The BRK6110 has these signals connected to a 2 mm header compatible with the Xilinx JTAG cable Expansion Connectors JP1 JP2 JP1 is an 80 pin high density connector providing access to FPGA Bank 1 Several pins 38 40 54 58 59 61 77 and 79 of this connector are wired to global clock inputs on the FPGA and can therefore be used as inputs to the global clock network Pin JP1 10 is connected to the Vrer pins of Bank 1 Pin mappings for JP1 are listed at the end of this document in the Quick Reference section For each JP1 pin the corresponding board connection is listed For pins connected to the FPGA the corresponding FPGA pin number is also shown Finally for pins routed to differential pair I Os on the FPGA the FPGA signal names and routed track lengths have been provided to help you equalize lengths on differential pairs JP2 is an 80 pin high density connector providing access to FPGA Banks 0 and 1 Several pins 42 44 59 61 64
13. PC based virtual instruments such as LEDs hex dis plays pushbuttons toggle buttons and so on Essentially this makes your PC a reconfigurable I O board and adds tremendous value to the XEM6110 as an experimentation or prototyping system Programmers Interface In addition to complete support within FrontPanel the XEM6110 is also fully supported by the FrontPanel programmer s interface API a powerful C class library available to Windows pro grammers allowing you to easily interface your own software to the XEM In addition to the C library wrappers have been written for C Java and Python making the API available under those languages as well Sample wrappers are also provided for Matlab and LabVIEW Complete documentation and several sample programs are installed with FrontPanel 8 www opalkelly com XEM6110 User s Manual Applying the XEM6110 Powering the XEM6110 The XEM6110 requires that this supply be clean filtered and within the range of 4 5v to 5 5v This supply must be delivered through the VDC pins on the two device s two expansion connec tors The expansion bus has several power supply pins described below VDC is provided by an external device to the XEM6110 It must be a clean filtered sup ply within the range of 4 5 volts and 5 5 volts 3 3v is the output of a 2 Amp switching regulator on the XEM6110 1 8v is the output of a 2 Amp switching regulator on the XEM6110 1 2v is the output
14. ase 20110406 Added note and reference regarding LVDS output restriction for Spartan 6 Introducing the XEM6110 scs chee ctor crane 5 PCB FOON has 104 7 dob p ridad dias 5 BRK6110 Breakout Board 5 Functional Block Diagram lisse 6 Power SUDDLY cuisse dosi a A Sov e UR CE p S a 6 PCI Express 1 1 Interface ioo simmer mre RP 6 On board Peripherals a T Low Jitter Crystal Oscillator 7 128 MByte Word Wide DDR2 Synchronous DRAM 7 RENE 7 Expansion Connectors aaa 7 FrontPanel Support zars made bb bb d vnk bande 8 Programmer s Interface 8 Applying the XEM6110 a 9 Powering the XEMOT110 asi erem meme deere 9 Power Budget ri da ser eet ista 9 Supply Heat Dissipation IMPORTANTID 10 Host IMO ACE Ss sonia ada d dedo dido 10 POL EXDEIGSS us ar a aia diode obe dr 10 A C RT ETE 11 Low Jitter 100 MHz Crystal Oscillator 11 DORZ SDRAM he diri ide 12 Clock Configuration Source Synchronous 12 Memory Controller Blocks veer cla e 12 MIG Settings ues ndr Eb ended Ss e e ines 13 SPa E E PE 13 Expansion COonhectOrs s ud ace sce Red dad 13 MPN 5 EIS Peet ee 13 APS ed tree Epis weed E es eens t 13 Setting VO Voltages abu ear tact tdg 14 Considerations for Differential Signals 14 BRKO110 Breakout Boatd 1 3 4 oes bn crt oben 15 PCI Express Cable Gelechon i 15 Differences Between the XEM3010 and XEM6110
15. er s Manual For Bank O the four VREF pins are routed to expansion connector JP1 on pins 48 51 62 and 65 Note that all four must be connected to the same voltage for proper application of input thresh olds Please see the Xilinx Spartan 6 documentation for more details For Bank 1 the four VrEF pins are connected to a single pin on expansion connector JP1 pin 10 BRK6110 Breakout Board The BRK6110 is a simple two layer breakout board which can be used to evaluate or transition to the XEM6110 It provides standard 2 mm thru hole connections to the 0 8 mm high density connectors on the XEM6110 and a DC power connector 2 1mm 5 5mm center positive for pro viding VDC to the XEM6110 The corresponding connections to the XEM6110 are labelled in silkscreen on the BRK6110 The BRK6110 connectors essentially mirror the connections on the XEM6110 For example the JP1 connector on the XEM6110 mates to JP1 on the BRK6110 and is electrically connected to JP1A and JP1B on the BRK6110 according to the table below Note that the pins on JP1 the Samtec connector are routed to two headers denoted as JP1A and JP1B JP1A pins are numbered 1 40 JP1B pins are numbered 41 80 This is to map them to the single Samtec connector rr A similar relationship holds for JP2 JP2A and JP2B PCI Express Cable Selection The XEM6110 is designed as an external PCI Express device The Opal Kelly PCI1001 is a x1 PCI Express host interface board
16. fferential LVDS pairs Please refer to the Xilinx Spartan 6 datasheet for details on using differential I O standards with the Spartan 6 FPGA Note LVDS output on the Spartan 6 is restricted to banks 0 and 2 LVDS input is available on all banks For more information please refer to the Spartan 6 FPGA SelectlO Resources User Guide from Xilinx FPGA I O Bank Voltages In order to use differential I O standards with the Spartan 6 you must set the VCCO voltages for the appropriate banks to 2 5v according to the Xilinx Spartan 6 datasheet Please see the sec tion above entitled Setting I O Voltages for details Characteristic Impedance The characteristic impedance of all routes from the FPGA to the expansion connector is approxi mately 50 0 Differential Pair Lengths In many cases it is desirable that the route lengths of a differential pair be matched within some specification Care has been taken to route differential pairs on the FPGA to adjacent pins on the expansion connectors whenever possible We have also included the lengths of the board routes for these connections to help you equalize lengths in your final application Due to space con straints some pairs are better matched than others Reference Voltage Pins VREF The Xilinx Spartan 6 supports externally applied input voltage thresholds for some input signal standards The XEM6110 supports these Vrer applications for banks O and 1 www opalkelly com XEM6110 Us
17. nnector 5 v DC power must be delivered to the device through the expansion connectors The BRK6110 provides such power with the same connector found on the XEM3010 32 MiB SDR SDRAM 128 MiB DDR2 SDRAM The XEM3010 has 32 MiB of on board single data rate SDRAM The XEM6110 replaces this with a faster higher capacity 128 MiB double data rate SDRAM The Spartan 6 also has an internal memory control block MCB which provides a DDR2 controller to designs without con suming significant FPGA fabric www opalkelly com 17 XEMG6110 User s Manual XEM6110 Mechanical Drawing 50 00 1 47 00 i 35 74 i 0 24 i 3 07 i O 000000000 y 000000000 All dimensions in mm 18 www opalkelly com XEMG6110 User s Manual BRK6110 Mechanical Drawing All dimensions in mm 120 00 117 00 112 71 111 00 108 56 106 41 28 00 92 73 73 00 65 00 58 26 29 00 27 00 3 00 O CODON VO Oe TR oO Oe O COD a ONOS Oo 0000 oO d oO mo oe NN ARADO e 00 TWO ONKO www opalkelly com 19 XEM6110 User s Manual XEM6110 Quick Reference JP1 Length Pin Connection FPGA Pin mm H pe CSC EE ELLE s merk gt mems M D m pw Y as eco ss voor gt 69 o2 fema aras JP1 Length Pin Connection mm 2 ewm IL ese s eso
18. partan 6 FPGA can produce a wide range of clock frequencies using the on chip DCM and PLL capabilities 128 MByte Word Wide DDR2 Synchronous DRAM The XEM also includes a 128 MByte DDR2 SDRAM with a full 16 bit word wide interface to the FPGA This SDRAM is attached exclusively to the FPGA and does not share any pins with the expansion connector The maximum clock rate of the SDRAM is 266 MHz The DDR2 SDRAM is a Micron MT47H64M16HR 3 G or compatible LEDs Eight LEDs and are available for general use as debug outputs Expansion Connectors Two high density 80 pin expansion connectors are available on the bottom side of the XEM6110 PCB These expansion connectors provide user access to several power rails on the XEM6110 the JTAG interface on the FPGA and 124 non shared I O pins on the FPGA including several GCLK inputs The connectors on the XEM6110 are Samtec part number BSE 040 01 F D A The table below lists the appropriate Samtec mating connectors along with the total mated height Samtec Part Number Mated Height BTE 040 01 F D A 5 00mm 0 197 www opalkelly com 7 XEM6110 User s Manual Samtec Part Number Mated Height BTE 040 02 F D A 8 00mm 0 315 BTE 040 03 F D A 11 00mm 0 433 BTE 040 04 F D A 16 10mm 0 634 BTE 040 05 F D A 19 10mm 0 752 FrontPanel Support The XEM6110 is fully supported by Opal Kelly s FrontPanel software FrontPanel augments the limited peripheral support with a host of
19. red until turning off the PC Unlike standards such as USB or Firewire the hot plugging is not supported by most operating systems The PCI Express implementation in the XEM6110 is a two part implementation The first part is dedicated silicon on the XEM6110 that is able to configure the FPGA at any time This silicon enumerates the XEM6110 as a PCI Express device even without any FPGA configuration The second part is IP provided by Opal Kelly that is built along with your FPGA application This www opalkelly com LEDs XEMG6110 User s Manual component resides inside the FPGA and serves as the host interface between the dedicated PCI Express silicon and your FPGA application Because part of the PCI Express implementation resides within the FPGA with your design it is possible that during development certain situations can occur that would crash the PC hard ware For this reason we highly recommend that development be done using a dedicated PC that is not mission critical and can tolerate the unexpected hardware crash For pin mappings to the PCI Express host interface please see our sample UCF files You can use these UCF files as a basis for your design There are eight LEDs on the XEM6110 Each is wired directly to the FPGA according to the pin mapping tables at the end of this document The LED anodes are connected to a pull up resistor to 3 3VDD and the cathodes wired directly to the FPGA on Bank 3 with a bank I O voltage of 1
20. terface PCI Express is significantly faster and still allows FPGA reconfiguration over the inter face without shutting down the computer However plug and play is not currently supported by most operating systems for PCI Express so the device must be turned on before the PC boots Cypress PLL FPGA based PLLs There is no on board PLL on the XEM6110 Spartan 6 adds on chip PLLs with similar function ality and the trade off is a lower jitter clock oscillator on the XEM6110 2C Connections FPGA based BC Controller The XEM6110 does not have the C connections on its expansion connectors These have been replaced with new routes to the FPGA so that existing designs may incorporate a user supplied IC controller into the FPGA fabric Four I O Banks Two I O Banks The Spartan 3 device used on the XEM3010 has 6 I O banks four of which are routed to the ex pansion connectors Each of these four has selectable I O bank voltages The Spartan 6 device on the XEM6110 only has four total I O banks two of which are routed to the expansion connec tors This is a consideration in designs where multiple I O bank voltages were used Note LVDS output on the Spartan 6 is restricted to banks 0 and 2 LVDS input is available on all banks For more information please refer to the Spartan 6 FPGA SelectlO Resources User Guide from Xilinx DC Power Connector Expansion Connectors Due to space constraints the XEM6110 no longer has a DC power co
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