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LPC4350 datasheet - NXP Semiconductors

1. Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Q 2 F 3 Description Te T 7 i S amp Sa o a a u p o S SEN RUE Ege PD 4 T2 l BN l R Function reserved PU lo CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 lO EMC D18 External memory data line 18 R Function reserved l O GPIO6 18 General purpose digital input output pin R Function reserved R Function reserved lO SGPIO8 General purpose digital input output pin PD 5 Pe l 2 N l R Function reserved PU lo CTOUT_9 SCTimer PWM output 9 Match output 3 of timer 3 O EMC D19 External memory data line 19 R Function reserved l O GPIO6 19 General purpose digital input output pin R Function reserved R Function reserved lO SGPIO9 General purpose digital input output pin PD 6 R6 l RI N l R Function reserved PU lo CTOUT_10 SCTimer PWM output 10 Match output 3 of timer 3 O EMC D20 External memory data line 20 R Function reserved l O GPIO6 20 General purpose digital input output pin R Function reserved R Function reserved lO SGPIO10 General purpose digital input output pin PD 7 T6 l R N l R Function reserved PU CTIN
2. values Symbol Parameter Conditions Min Max Unit folk clock frequency on pin SD_CLK data transfer mode 52 MHz tsu D data input set up time on pins SD_DATn as inputs 3 9 ns on pins SD_CMD as inputs 5 2 ns th D data input hold time on pins SD_DATn as inputs 0 4 ns on pins SD_CMD as inputs 0 ns tav data output valid delay on pins SD DATn as outputs 15 3 ns time on pins SD CMD as outputs 16 ns tha data output hold time on pins SD_DATn as outputs 4 ns on pins SD_CMD as outputs 4 ns lt Toy clk gt SD_CLK ta Qv th Q SD_CMD O SD DATn O tsu D fn D SD CMD I SD DATn I 002aag204 Fig 39 SD MMC timing 11 19 LCD Table 34 Dynamic characteristics LCD Tamp 40 C to 485 C 22V lt Vpp REG 3V3 8 6V 27Vx VppvI0 lt 3 6 V C 20 pF Simulated values Symbol Parameter Conditions Min Typ Max Unit folk clock frequency on pin LCD_DCLK 50 MHz ta av data output valid A 17 ns delay time tha data output hold time 85 ns LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 128 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 11 20 SPIFI Table 35 Dynamic characteristics SPIFI Tamb 40 C to 85 C 2 2 V lt Vpp REG 3V3 S3 6
3. Boot mode Pins Description P2 9 P2 8 P12 P1 1 USARTO LOW LOW LOW LOW Boot from device connected to USARTO using pins P2_0 and P2 1 SPIFI LOW LOW LOW HIGH Boot from Quad SPI flash connected to the SPIFI interface on P3 3 to P3 8 11 EMC 8 bit LOW LOW HIGH LOW Boot from external static memory such as NOR flash using CSO and an 8 bit data bus EMC 16 bit LOW LOW HIGH HIGH Boot from external static memory such as NOR flash using CSO and a 16 bit data bus EMC 32 bit LOW HIGH LOW LOW Boot from external static memory such as NOR flash using CSO and a 32 bit data bus USBO LOW HIGH LOW HIGH Boot from USBO USB1 LOW HIGH HIGH LOW Boot from USB1 SPI SSP LOW HIGH HIGH HIGH Boot from SPI flash connected to the SSPO interface on P3 3 function SSPO SCK P3 6 function SSPO_SSEL P3 7 function SSPO0 MISO and P3 8 function SSPO MOSI I USARTS3 HIGH LOW LOW LOW Boot from device connected to USARTS using pins P2 3 and P2 4 1 The boot loader programs the appropriate pin function at reset to boot using either SSPO or SPIFI Remark Pin functions for SPIFI and SSPO boot are different 7 13 Memory mapping The memory map shown in Figure 7 and Figure 8 is global to both the Cortex M4 and the Cortex MO processors and all SRAM is shared between both processors Each processor uses its own ARM private bus memory map for the NVIC and other system functions LPC4350 30 20 10 All information provided in th
4. Symbol o e 2 Description me fe IS leg 5 3 g 3 E sz e m Oo u D Hi a m a S Oo S I e 2 erie P3 4 A15 C14 B8 119 1 N O GPIO1 14 General purpose digital input output pin PU Du R Function reserved R Function reserved lO SPIFI SIOS3 I O lane 3 for SPIFI O U1 TXD Transmitter output for UART 1 lO I2S0 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the PS bus specification lO 12S1_RX_SDA I28S1 Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification O LCD VD13 LCD data P3 5 C12 C11 B7 121 B N lO GPIO1 15 General purpose digital input output pin PU R Function reserved R Function reserved lO SPIFI SIO2 I O lane 2 for SPIFI U1 RXD Receiver input for UART 1 V O 12S0_TX_SDA 2S transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification lO 12S1_RX_WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification O LCD_VD12 LCD data P3 6 B13 B12 C7 122 l IN l O GPIOO 6 General purpose digital input output pin PU yo SPI MISO Master In Slave Out for SPI l O SSPO SSEL Slave Select for SSPO l O SPIFI MISO Input
5. Vor V Conditions VDD REG 3V3 Vpp 0 3 3 V medium drive EHD 0x1 002aah044 40 C 25 C 85 C Vo V Conditions Vpp REq 3v3 Vpp o 3 3 V ultra high drive EHD 0x3 LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 103 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller 36 002aah047 VoH V 3 2 40 C 25 C 85 C 2 8 2 4 2 0 0 8 16 24 loH mA Conditions Vpp REG 3V3 Vpp 0 3 3 V normal drive EHD 0x0 a 002aah049 VoH V 3 2 40 C 25 C 85 C 2 8 2 4 2 0 0 32 64 96 loH mA Conditions Vpp REG 3V3 Vpp 0 3 3 V high drive EHD 0x2 ee 002aah048 VoH V 3 2 40 C 25 C 85 C 2 8 2 4 2 0 0 16 32 48 loH mA Conditions VpD REG 3V3 Vpp 0 3 3 V medium drive EHD 0x1 4 002aah050 VoH V 3 2 40 C 25 C 85 C 2 8 24 2 0 0 40 80 120 loH mA Conditions Vpp REG 3v3 Vpp o 3 3 V ultra high drive EHD 0x3 Fig 23 High drive pins typical HIGH level output vo
6. Table 9 Thermal resistance value BGA packages Symbol Parameter Conditions Thermal resistance in C W 15 LBGA256 TFBGA180 TFBGA100 Rina thermal resistance from JEDEC 4 5 in x 4 in still air 29 38 46 junction to ambient 8 layer 4 5 in x 3 in still air 24 30 37 Rth j c thermal resistance from 14 11 11 junction to case LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 87 of 158 NXP Semiconductors LPC4350 30 20 10 10 Static characteristics 32 bit ARM Cortex M4 M0 microcontroller Table 10 Static characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typi Max Unit Supply pins VDp 10 input output supply 2 2 3 6 V voltage Vpp REGyava regulator supply 2 12 2 3 6 V voltage 3 3 V VpDA 3V3 analog supply voltage on pin VDDA 2 2 3 6 V 3 3 V on pins 3 0 3 3 3 6 V USBO VDDA3V3 DRIVER and USBO_VDDA3V3 VBAT battery supply voltage 2 2 2 3 6 V Vprog pf polyfuse programming on pin VPP for OTP Bl 2 7 3 6 V voltage lorog pf polyfuse programming on pin VPP OTP z 30 mA current programming time lt 1 6 ms Ipp REG 3v3 regulator supply current Active mode MO core in
7. 000005 111 SSP interface 0 0 0 0 c cee eee 113 SPlinterface 0 0 0 nernet irei 116 SSP SPI timing diagrams 117 SGPIO TIMING ess ec eee pute 118 External memory interface 120 USB interface nnan nananana 125 Ethernet ireen ESRAR E EE RES 126 SD MMG ky xe REMER ERG ERS 128 LOD L2 RR VRBIS 128 SPIEL ce detente pic REPE EN E Aani 129 ADC DAC electrical characteristics 130 Application information 133 LCD panel signal usage 133 Crystal oscillator 0 000000 135 RTC oscillator 0 0 0 0 eee 137 XTAL and RTCX Printed Circuit Board PCB layout guidelines 22 137 Standard I O pin configuration 137 Reset pin configuration 138 Suggested USB interface solutions 138 Package outline seesee 141 Soldering 6 cede oorr rmm 145 Abbreviations lsleesssse 149 References seeei o RR 150 18 19 19 1 19 2 19 3 19 4 20 21 32 bit ARM Cortex M4 MO microcontroller Revision history lees 151 Legal information 155 Data sheet status 155 Definitions 0 0 0 0 155 Disclaimers 0 00 e eae 155 Trademarks 0 0 156 Contact information 156 Contents 2420600008 sive eevee m wee 157 Please be aware that important notices conce
8. Rysi LPC43xx oS SSS Se pS eS Pi 1 2 KQ analog pin ADCO n ADC1 n 1 2 2 KQ multiplexed pin Re E ADC co i COMPARATOR fo FE LLT SEE VEXT Vss H1 002aag704 Rs lt 1 7 x fakapo x Cia 2 KQ Fig 42 ADC interface to pins Table 37 DAC characteristics VppA ava Over specified ranges Tamb 0 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Ep differential linearity error 2 7 V lt VppA ava 3 6 V 1 0 8 LSB 2 2 V lt Vppa ava lt 2 7 V 1 0 LSB EL adi integral non linearity code 0 to 975 1 1 0 LSB 2 7 V lt Vppa ava 3 6 V 2 2 V Vppa ava lt 2 7 V 41 5 LSB Eo offset error 2 7 V Vppa ava 3 6 V 1 0 8 LSB 2 2 V Vppa ava lt 2 7 V 1 0 LSB Eg gain error 2 7 V Vppa ava 3 6 V 1 l 0 3 2 2 V Vppa ava lt 2 7 V 1 0 CL load capacitance 200 pF RL load resistance 1 kQ ts settling time 2 0 4 uo 1 In the DAC CR register bit BIAS 0 see the LPC43xx user manual 2 Settling time is calculated within 1 2 LSB of the final value LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 132 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 13 Application information 13 1 LCD panel signal usage
9. SOT740 2 occupied area solder resist DIMENSIONS in mm Ed solder land plus solder paste P SL SP SR Hx Hy 1 00 0 450 0 450 0 600 17 500 17 500 n pr v mere Meyeri i 1 0000O0Q0Q000 1 1 OQOO0O0C0O0CO0OCO POO OQ OO OT QW 1 DOS OOO l OOO O00 COG COO l OO OOO OOO l 1 OOO O DX QW TO m WOO D0 O COC Y SPEC ce say a NORD VICO RERO ARN LES Ore BR EUER eer Soe Generic footprint pattern Refer to the package outline drawing for actual layout P sullo 7 y KKR gt N e eese SS solder paste deposit N RES S ks Bee Boe KS gt 4 detail X sot740 2_fr Fig 55 Reflow soldering of the LBGA256 package LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 145 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Footprint information for reflow soldering of TFBGA180 package SOT570 3 QOOOOO0O0 O0000000 OO00000 I0000000 O00 o0o0 00000000 OO OOOO OO OO OOO QOOOO0O0O0O00001u020 see detail X Ry solder land SL SKB KK solder paste deposit SP a N N me ne e solder land plus solder paste EX oos eo Ss solder resist opening SR occupi
10. LCD panel power enable R Function reserved O TRACEDATA 3 Trace data bit 3 O ENET MDC Ethernet MIIM clock lO SGPIO7 General purpose digital input output pin Al ADC1 6 ADC1 and ADCO input channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P8 0 E5 E4 l BI IN lO GPIO4 0 General purpose digital input output pin PU USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition R Function reserved MCI2 Motor control PWM channel 2 input lO SGPIO8 General purpose digital input output pin R Function reserved R Function reserved O TO MATO Match output 0 of timer 0 P8 1 H5 G4 l Gl IN O GPIO4 1 General purpose digital input output pin PU Jo USBO IND1 USBO port indicator LED control output 1 R Function reserved MCI1 Motor control PWM channel 1 input lO SGPIO9 General purpose digital input output pin R Function reserved R Function reserved O TO_MAT1 Match output 1 of timer 0 P8 2 K4 J4 Gl IN l O GPIO4 2 General purpose digital input output pin PU Jo USBO INDO USBO port indicator LED control output 0 R Function reserved MCIO Motor
11. Master Out Slave in for SSPO l O SPIFI CS SPIFI serial flash chip select lO GPIO5 11 General purpose digital input output pin lO SSPO SSEL Slave Select for SSPO R Function reserved R Function reserved P4 0 D5 D4 l 1 Bl IN l O GPIO2 0 General purpose digital input output pin PU O MCOAO0 Motor control PWM channel 0 output A NMI External interrupt input to NMI R Function reserved R Function reserved O LCD VD13 LCD data lO U3 UCLK Serial clock input output for USARTS in synchronous mode R Function reserved P4 1 A1 D3 l 3 BI IN lO GPIO2 1 General purpose digital input output pin PU lo CTOUT_1 SCTimer PWM output 1 Match output 3 of timer 3 O LCD_VDO LCD data R Function reserved R Function reserved O LCD_VD19 LCD data O U3 TXD Transmitter output for USARTS ENET COL Ethernet Collision detect MII interface Al ADCO 1 ADCO and ADC1 input channel 1 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 22 of 158 NXP Semiconductors LPC
12. R Function reserved R Function reserved l O SGPIO13 General purpose digital input output pin PD_10 P11 l z BN R Function reserved PU CTIN 1 SCTimer PWM input 1 Capture input 1 of timer 0 Capture input 1 of timer 2 O EMC_BLS3 LOW active Byte Lane select signal 3 R Function reserved lO GPIO6 24 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PD 11 N9 M7 BN R Function reserved PU R Function reserved O EMC CS3 LOW active Chip Select 3 signal R Function reserved l O GPIO6 25 General purpose digital input output pin lO USB1 ULPI DO ULPI link bidirectional data line 0 O CTOUT 14 SCTimer PWM output 14 Match output 2 of timer 3 R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 46 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 TFBGA100 LQFP144 Type LBGA256
13. Symbol TFBGA180 TFBGA100 LQFP144 Reset state 1 Description PE 15 IT LBGA256 wo iN UZ c R Function reserved CTOUT 0 SCTimer PWM output 0 Match output 0 of timer 0 I2C1 SCL I C1 clock input output this pin does not use a specialized I2C pad EMC_CKEOUT3 SDRAM clock enable 3 GPIO7 15 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PF 0 D12 PU SSPO SCK Serial clock for SSPO GP CLKIN General purpose clock input to the CGU R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved I281 TX MCLK 12S1 transmit master clock PF 1 E11 PU R Function reserved R Function reserved O SSPO SSEL Slave Select for SSPO R Function reserved O GPIO7 16 General purpose digital input output pin R Function reserved O SGPIOO General purpose digital input output pin R Function reserved PF_2 D11 PU R Function reserved U3 TXD Transmitter output for USART3 O SSPO MISO Master In Slave Out for SSPO R Function reserved O GPIO7 17 General purpose digital input output pin R Function re
14. 1 12 0 4 Toy clk 0 3 Toy clk ns time 5 tcstBLsL_ CS LOW to BLS LOW PB 0 0 7 1 8 ns WAITWEN 1 WAITWEN 1 x Tcy cik x Toy clk LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 120 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 27 Dynamic characteristics Static asynchronous external memory interface continued C 22 pF for EMC Dn C 20 pF for all others Tamb 40 C to 85 C 2 2 V x Vppinea ava 3 6 V 2 7 V lt Vppio x 3 6 V values guaranteed by design the values in the table have been calculated with WAITTURN 0x0 in STATICWAITTURN register Timing parameters are given for single memory access cycles In a normal read operation the EMC changes the address while CS is asserted resulting in multiple memory accesses Symbol Parameter Conditions Min Typ Max Unit teLsLgeLsu BLS LOW to BLS HIGH time PB 0 2 0 9 0 1 ns WAITWR WAITWR WAITWEN 1 x WAITWEN 1 x Tey clk Toy cll tstsHeow BLS HIGH to end of write PB 0 2 1 9 Tey cik 0 5 Tey cik ns time 5 tgisupuv BLS HIGH to data invalid PB 0 1 2 5 Tey clk 1 4 Toyclk ns time 2 tcsuEow CS HIGH to end of write 5 2 0 0 ns
15. 11 11 SSP interface Table 24 Dynamic characteristics SSP pins in SPI mode Tamb 40 C to 85 C 2 2 V lt Vpp nea ava 3 6 V 2 7 V x Vopao 3 6 V C 20 pF Sampled at 10 and 90 of the signal level EHS 1 for all pins Simulated values Symbol Parameter Conditions Min Typ Max Unit SSP master Toy cik clock cycle time full duplex mode 1 1 25 5 x 106 S when only transmitting 1 51 x 109 S tps data set up time in SPI mode 13 6 ns tbH data hold time in SPI mode 3 8 ns tva data output valid in SPI mode 6 0 ns time tha data output hold in SPI mode 1 1 ns time tlead lead time continuous transfer mode Toy clk 3 2 Toy clk 6 1 ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 0 5 x Tey ck 3 2 0 5 x Tey cik 6 1 ns CPHA 1 SPI mode CPOL 1 Toy clk 13 2 Toy clk 6 1 ns CPHA 0 SPI mode CPOL 1 0 5 x Toy clk 3 2 0 5 x Toy clk 6 1 ns CPHA 1 synchronous serial 0 5 x Teyclk 3 2 0 5 x Teyck 6 1 ns frame mode microwire frame format Toy clk 3 2 Toy clk 6 1 ns tlag lag time continuous transfer mode 0 5 x Toy clIk z ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 Toy clk E ns CPHA 1 SPI mode CPOL 1 0 5 x Toy cli ns CPHA 0 SPI mode CPOL 1 Toy clk ns CPHA 1 synchronous serial Toy clk ns frame mode microwire f
16. 16 B Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit EIA 485 mode USARTS includes an IrDA mode to support infrared communication All USARTs have DMA support Support for synchronous mode at a data bit rate of up to 8 Mbit s e Smart card mode conforming to ISO7816 specification SPI serial I O controller The LPC4350 30 20 10 contain one SPI controller SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus Only a single master and a single slave can communicate on the interface during a given data transfer During a data transfer the master always sends 8 bits to 16 bits of data to the slave and the slave always sends 8 bits to 16 bits of data to the master Features Maximum SPI data bit rate 25 Mbit s Compliant with SPI specification e Synchronous serial full duplex communication Combined SPI master and slave Maximum data bit rate of one eighth of the input clock rate 8 bits to 16 bits per transfer SSP serial I O controller Remark The LPC4350 30 20 10 contain two SSP controllers The
17. 250 us after reset 250 us 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 Toga 1 CCLK with CCLK CPU clock frequency 11 2 External clock for oscillator in slave mode Remark The input voltage on the XTAL1 2 pins must be lt 1 2 V see Table 10 For connecting the oscillator to the XTAL pins also see Section 13 2 and Section 13 4 Table 15 Dynamic characteristic external clock Tamb 40 C to 85 C Vpp io over specified ranges Symbol Parameter Conditions Min Max Unit fosc oscillator frequency 1 25 MHz Toy cll clock cycle time 40 1000 ns tcucx clock HIGH time Toy clk x 0 4 Tey cik x 0 6 ns tcicx clock LOW time Toy ck x 0 4 Tey cik x 0 6 ns 1 Parameters are valid over operating temperature range unless otherwise specified Toy clk 002aag698 Fig 26 External clock timing with an amplitude of at least Viigus 200 mV LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 106 of 158 NXP Semiconductors LPC4350 30 20 1 0 11 3 11 4 11 5 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Crystal oscillator Table 16 Dynamic characteristic oscillator Tamb 40
18. All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 156 of 158 NXP Semiconductors LPC4350 30 20 10 21 Contents 32 bit ARM Cortex M4 M0 microcontroller 1 General description suus 1 7 17 6 High speed USB Host Device interface with ULPI 2 Features and benefits 4 1 USB eee eee eee ee ee cee ee 72 3 Applications sisse 4 7 17 6 1 Features nananana ee 72 4 Ordering information 5 7 17 7 LCD controller 2 200005 73 adc DERE QE TZ Feats 12e ew a Ped aoe ced voe 73 4 1 Ordering options se sees 5 7178 Ethernet 0 000 000 cece eee eae 74 5 Block diagram eese 6 747 81 BEBIGECcEceccrie eot o ado Rada 74 6 Pinning information Lees 7 7 18 Digital serial peripherals 74 6 1 PINNING Lise egies CE E deena ER 7 7 18 1 VARTI uec ones prb petet eh RA 74 6 2 Pin description 0 0 00 e eee eee 8 TAB A Features ceded ag heb ese 74 7 Functional description sss 61 7 18 2 USARTO 2 3 illu etu 75 74 Architectural overview 61 7 18 2 1 Features rOin a Ba see ree der eee le 75 72 ARM Cortex M4 processor 61 7 18 3 SPI serial I O controller 75 73 ARM Cortex MO co processor 61 7 18 3 1 Features
19. NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Q 2 F 3 Description Te T 7 3 o0 o amp nee g B B 5 j E d ec c PE 7 F15 z BN l R Function reserved PU lo CTOUT 5 SCTimer PWM output 5 Match output 3 of timer 3 U1_CTS Clear to Send input for UART1 O EMC D26 External memory data line 26 lO GPIO7 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 8 F14 z 2 N R Function reserved PU lo CTOUT_4 SCTimer PWM output 4 Match output 3 of timer 3 U1_DSR Data Set Ready input for UART 1 O EMC D27 External memory data line 27 lO GPIO7 8 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 9 E16 RI N l R Function reserved PU CTIN_4 SCTimer PWM input 4 Capture input 2 of timer 1 U1_DCD Data Carrier Detect input for UART 1 O EMC D28 External memory data line 28 lO GPIO7 9 General purpose digital input output pin R Function reserved R Function reserved R Function
20. Transmitter output for USART2 R Function reserved R Function reserved R Function reserved R Function reserved PA_2 K15 J13 Gl IN l O GPIO4 9 General purpose digital input output pin PU QEI PHB Quadrature Encoder Interface PHB input R Function reserved U2 RXD Receiver input for USART2 R Function reserved R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 37 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol ie Q 2 F 3 Description Te pm q a lt o0 S amp UE g B B5 j E FE ESE PA 3 H11 E10 Bl N O GPIO4 10 General purpose digital input output pin PU QEI PHA Quadrature Encoder Interface PHA input R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved R Function reserved PA 4 G13 E12 2 N R Function reserved PU lo CTOU
21. aaa LPC4350 30 20 10 Bus 32 bit ARM Cortex M4 MO flashless MCU up to 264 kB SRAM Ethernet two HS USBs advanced configurable peripherals Rev 4 5 26 November 2015 Product data sheet 1 General description The LPC4350 30 20 10 are ARM Cortex M4 based microcontrollers for embedded applications which include an ARM Cortex MO coprocessor up to 264 kB of SRAM advanced configurable peripherals such as the State Configurable Timer PWM SCTimer PWM and the Serial General Purpose I O SGPIO interface two high speed USB controllers Ethernet LCD an external memory controller and multiple digital and analog peripherals The LPC4350 30 20 10 operate at CPU frequencies of up to 204 MHz The ARM Cortex M4 is a 32 bit core that offers system enhancements such as low power consumption enhanced debug features and a high level of support block integration The ARM Cortex M4 CPU incorporates a 3 stage pipeline uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals and includes an internal prefetch unit that supports speculative branching The ARM Cortex M4 supports single cycle digital signal processing and SIMD instructions A hardware floating point processor is integrated in the core The ARM Cortex MO coprocessor is an energy efficient and easy to use 32 bit core which is code and tool compatible with the Cortex M4 core The Cortex MO coprocesso
22. o4000 8000 0x4000 7000 0x4000 6000 LCD MC 0x4000 5000 MA CT 0x4004 7000 0x4000 4000 0x4000 3000 0x4000 2000 0x4000 1000 0x4000 0000 002aaf775 J9 0u0590491UJ OIN TIN X910 WHV 1d c 40 9npuooliul9S dXN 0L 0c 0 0S trOd l NXP Semiconductors LPC4350 30 20 1 0 7 14 7 15 7 15 1 7 16 7 16 1 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller One Time Programmable OTP memory The OTP provides 64 bit 256 bit One Time Programmable OTP memory for general purpose use General Purpose I O GPIO The LPC4350 30 20 10 provide eight GPIO ports with up to 31 GPIO pins each Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers Pins may be dynamically configured as inputs or outputs Separate registers allow setting or clearing any number of outputs simultaneously The value of the output register may be read back as well as the current state of the port pins All GPIO pins default to inputs with pull up resistors enabled and input buffer disabled on reset The input buffer must be turned on in the system control block SFS register before the GPIO input can be read Features Accelerated GPIO functions GPIO registers are located on the AHB so that the fastest possible I O timing can be achieved Mask registers allow treating sets of port bits as a group leaving other bits unchanged All GPIO registers
23. 16 or 32 data bits per device Separate reset domains allow auto refresh through a chip reset if desired SDRAM clock can run at full or half the Cortex M4 core frequency Note Synchronous static memory devices synchronous burst mode are not supported High speed USB Host Device OTG interface USBO Remark The USBO controller is available on parts LPC4350 30 20 See Table 2 The USB OTG module allows the LPC4350 30 20 10 to connect directly to a USB Host such as a PC in device mode or to a USB Device in host mode Features On chip UTMI compliant high speed transceiver PHY Complies with Universal Serial Bus specification 2 0 Complies with USB On The Go supplement Complies with Enhanced Host Controller Interface Specification Supports auto USB 2 0 mode discovery Supports all high speed USB compliant peripherals Supports all full soeed USB compliant peripherals Supports software Host Negotiation Protocol HNP and Session Request Protocol SRP for OTG peripherals Supports interrupts This module has its own integrated DMA engine USB interface electrical test software included in ROM USB stack High speed USB Host Device interface with ULPI USB1 Remark The USB1 controller is available on parts LPC4350 30 See Table 2 The USB1 interface can operate as a full speed USB Host Device interface or can connect to an external ULPI PHY for High speed operation Features Complies
24. 3 3 V reset code while 1 executed from RAM all peripherals disabled PLL1 enabled CCLK 12 MHz 4 6 6 mA CCLK 60 MHz 4 25 3 mA CCLK 120 MHz 4 48 4 mA CCLK 180 MHz 4 72 0 mA CCLK 204 MHz i 81 5 mA Ipp REG 3v3 regulator supply current after WFE WFI instruction 3 3 V executed from RAM all peripherals disabled MO core in reset Sleep mode l5 5 0 mA deep sleep mode 4 30 uA power down mode 4 15 uA deep power down l6 0 03 uA mode deep power down 4 2 uA mode VBAT floating IBAT battery supply current active mode Vgar Ul 0 nA 3 2 V Vpp REG 3V3 3 6 V LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 88 of 158 NXP Semiconductors LPC4350 30 20 10 Table 10 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified 32 bit ARM Cortex M4 M0 microcontroller Symbol Parameter Conditions Min Typi Max Unit IBAT battery supply current Vpp REG ava 3 3 V 8 VBAT 3 6 V deep sleep mode 2 uA power down mode 8 uA deep power down 8 mode 2 uA IDD 10 I O supply current deep sleep mode 1 uA power down mode 1 uA d
25. 32 bit ARM Cortex M4 M0 microcontroller 6 2 Pin description LPC4350_30_20_10 On the LPC4350 30 20 10 digital pins are grouped into 16 ports named PO to P9 and PA to PF with up to 20 pins used per port Each digital pin can support up to eight different digital functions including General Purpose I O GPIO selectable through the System Configuration Unit SCU registers The pin name is not indicative of the GPIO port assigned to it Not all functions listed in Table 3 are available on all packages See Table 2 for availability of USBO USB1 Ethernet and LCD functions The parts contain two 10 bit ADCs ADCO and ADC1 The input channels of ADCO and ADC1 on dedicated pins and multiplexed pins are combined in such a way that all channel 0 inputs named ADCO 0 and ADC1_0 are tied together and connected to both channel 0 on ADCO and channel 0 on ADC1 channel 1 inputs named ADCO 1 and ADC1 1 are tied together and connected to channel 1 on ADCO and ADC1 and so forth There are eight ADC channels total for the two ADCs All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 8 of 158 NXP Semiconductors LPC4350 30 20 10 Table 3 Pin description 32 bit ARM Cortex M4 M0 microcontroller LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol LBGA256
26. A built in FIFO acts as a buffer for display data providing flexibility for system timing Hardware cursor support can further reduce the amount of CPU time required to operate the display Features AHB master interface to access frame buffer Setup and control via a separate AHB slave interface Dual 16 deep programmable 64 bit wide FIFOs for buffering incoming display data Supports single and dual panel monochrome Super Twisted Nematic STN displays with 4 bit or 8 bit interfaces Supports single and dual panel color STN displays e Supports Thin Film Transistor TFT color displays Programmable display resolution including but not limited to 320 x 200 320 x 240 640 x 200 640 x 240 640 x 480 800 x 600 and 1024 x 768 Hardware cursor support for single panel displays 15 gray level monochrome 3375 color STN and 32 K color palettized TFT support 1 2 0r 4 bits per pixel bpp palettized displays for monochrome STN e 1 2 4 or 8 bpp palettized color displays for color STN and TFT 16 bpp true color non palettized for color STN and TFT 24 bpp true color non palettized for color TFT Programmable timing for different display panels e 256 entry 16 bit palette RAM arranged as a 128 x 32 bit RAM Frame line and pixel clock signals AC bias signal for STN data enable signal for TFT panels Supports little and big endian and Windows CE data formats All information provided in this
27. Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 54 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description oO eo eo S d lt a cz o lt 0 oO ER E URL UR e E d EF J E PF 9 D6 BN S l R Function reserved PU JO UO DIR RS 485 EIA 485 output enable direction control for USARTO O CTOUT 1 SCTimer PWM output 1 Match output 3 of timer 3 R Function reserved l O GPIO7 23 General purpose digital input output pin R Function reserved lO SGPIOS3 General purpose digital input output pin R Function reserved Al ADC1 2 ADC1 and ADCO input channel 2 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 10 A3 l z BIN R Function reserved PU Jo UO TXD Transmitter output for USARTO R Function reserved R Function reserved lO GPIO7 24 General purpose digital input
28. Figure 25 and Figure 26 updated for full temperature range Section 7 23 Serial Wire Debug JTAG updated The following changes were made on the TFBGA180 pinout in Table 3 P1 18 moved from ball D6 to L8 P7 5 moved from ball C7 to A7 PF 4 moved from ball L8 to D6 RESET moved from ball B7 to C7 RTCX2 moved from ball A7 to B7 Ball G10 changed from VSS to VDDIO LPC4350 30 20 10 v 3 4 20120904 Preliminary data sheet LPC4350 30 20 10 v 3 3 Modifications e SSPO boot pin functions corrected in Table 5 and Table 4 Pin P3 3 SSPO SCK pin P3 6 SSPO SSEL pin P3 7 SSPO MISO pin P3 8 SSPO MOSI Minimum value for all supply voltages changed to 0 5 V in Table 6 LPC4350 30 20 10 v 3 3 20120821 Preliminary data sheet LPC4350 30 20 10 v 3 2 Modifications e Parameter twake updated in Table 13 for wake up from deep power down mode and reset Dynamic characteristics of the SD MMC controller updated in Table 28 Dynamic characteristics of the LCD controller updated in Table 29 Dynamic characteristics of the SSP controller updated in Table 21 e Minimum value of V for conditions USBO pins USBO DP USBO DM USBO VBUS USBO pins USBO ID USBO RREF and USB1 pins USB1 DP and USB1 DM changed to 0 3 V in Table 6 Parameters ly and lj renamed to lj and l in Table 10 AES removed AES is available on parts LPC43Sxx only Pin configuration diagrams corr
29. LCD panel connections for TFT panels External TFT 12 bit 4 4 4 TFT 16 bit 5 6 5 mode TFT 16 bit 1 5 5 5 mode TFT 24 bit pin mode LPC43xx LCD LPC43xx LCD LPC43xx pin LCD LPC43xx LCD pin used function pin used function used function pinused function LCD VD23 PB O0 BLUES PB 0 BLUE4 PB 0 BLUE4 PB 0 BLUE7 LCD_VD22 PB_1 BLUE2 PB 1 BLUES PB 1 BLUES PB 1 BLUE6 LCD VD21 PB2 BLUE1 PB 2 BLUE2 PB 2 BLUE2 PB 2 BLUE5 LCD VD20 PB 3 BLUEO PB 3 BLUE1 PB 3 BLUE1 PB 3 BLUE4 LCD_VD19 P7_1 BLUEO P7_1 BLUEO P7 1 BLUES LCD VD18 P7 2 intensity P7 2 BLUE2 LCD VD17 P7 3 BLUE1 LCD VD16 P7_4 BLUEO LCD_VD15 PB_4 GREEN3 PB_4 GREEN5 PB 4 GREEN4 PB 4 GREEN7 LCD VD14 PB_5 GREEN2 PB_5 GREEN4 PB 5 GREEN3 PB 5 GREEN6 LCD VD13 PB_6 GREEN1 PB 6 GREEN3 PB 6 GREEN2 PB 6 GREEN5 LCD VD12 P8 3 GREENO P8 3 GREEN2 P8 3 GREEN1 P8 3 GREEN4 LCD VD11 P4 9 GREEN1 P4 9 GREENO P49 GREEN3 LCD_VD10 P4 10 GREENO P4 10 intensity P4 10 GREEN2 LCD VD9 P4 8 GREEN 1 LCD VD8 l P7 5 GREENO LCD VD7 P8 4 RED3 P8 4 RED4 P8 4 RED4 P8 4 RED7 LCD VDe P8 5 RED2 P8 5 RED3 P8_5 RED3 P8_5 RED6 LCD VD5 P86 RED1 P8 6 RED2 P8 6 RED2 P8 6 RED5 LCD_VD4 P8 7 REDO P8 7 RED1 P8 7 RED1 P8 7 RED4 LCD VD3 P4 2 REDO P4 2 REDO P4 2 RED3 LCD VD2 P4 3 intensity P4 3 RED2 LCD VD1 P4 4 RED1 LPC4350 30 20 10 All inform
30. TFBGA180 TFBGA100 LQFP144 Reset state 1 Type Description Multiplexed digital pins PO 0 L3 K3 C2 n 2 Uz c GPIOO 0 General purpose digital input output pin SSP1 MISO Master In Slave Out for SSP1 ENET RXD1 Ethernet receive data 1 RMII MII interface SGPIOO General purpose digital input output pin R Function reserved R Function reserved I280 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification 1 0 12S1_TX_WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification G1 34 BON PU O GPIOO 1 General purpose digital input output pin O SSP1 MOSI Master Out Slave in for SSP1 ENET COL Ethernet Collision detect MII interface O SGPIO1 General purpose digital input output pin R Function reserved R Function reserved ENET TX EN Ethernet transmit enable RMII MII interface 1 0 12S1_TX_SDA 12S1 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification H1 38 PU O GPIOO 4 General purpose digital input output pin CTIN 3 SCTimer PWM input 3 Capture input
31. Table 38 LCD panel connections for STN single panel mode External pin 4 bit mono STN single panel 8 bit mono STN single panel Color STN single panel LPC43xx pin LCD function LPCA3xx pin LCD function LPC43xx pin LCD function used used used LCD VD 23 8 LCD VD7 P8 4 UD 7 P8 4 UD 7 LCD_VD6 P8 5 UD 6 P8 5 UD 6 LCD VD5 P8 6 UD 5 P8 6 UD 5 LCD VD4 P8 7 UD 4 P8_7 UD 4 LCD_VD3 P4 2 UD 3 P4 2 UD 3 P4 2 UD S3 LCD VD2 P4 3 UD 2 P4 3 UD 2 P4 3 UD 2 LCD VD1 P4 4 UD 1 P4 4 UD 1 P4 4 UD 1 LCD VDO P4 1 UD O P4 1 UD 0 P4_1 UD 0 LCD LP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP LCD ENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB LCDM LCDM LCDM LCDM LCD FP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP LCD DCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK LCD LE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE LCD PWR P7 7 CDPWR P7 7 LCDPWR P7 7 LCDPWR GP CLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN Table 39 LCD panel connections for STN dual panel mode External pin 4 bit mono STN dual panel 8 bit mono STN dual panel Color STN dual panel LPC43xx pin LCD function LPCA3xx pin LCD function LPCA3xx pin LCD function used used used LCD VD 23 16 LCD VD15 PB 4 LD 7 PB 4 LD 7 LCD VD14 PB 5 LD 6 PB 5 LD 6 LCD VD13 PB 6 LD 5 PB 6 LD 5 LCD VD12 P8 3 LD 4 P8 3
32. Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the 1 S bus specification O 2S0 TX MCLK 2S transmit master clock lO SSPO SCK Serial clock for SSPO R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 19 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description MEER nes g 3 g g hk os 8g B s jg E SRI P3 1 G11 D10 F7 114 B IN l O I2S0 TX WS Transmit Word Select It is driven by the PU master and received by the slave Corresponds to the signal WS in the 2S bus specification lO 1280 RX WS Receive Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the PS bus specification CANO RD CAN receiver input O USB IND1 USB1 Port indicator LED control output 1 l O GPIO5 8 General purpose digital input output pin R Function reserved O LCD VD15 LCD data R Function reserved P3 2 F11 D9 Ge 116 Bl OL W O I2S0 TX SDA 12S transmit data It is dr
33. both cores and all peripherals except for peripherals in the always on power domain are shut down Memories can remain powered for retaining memory contents as defined by the individual power down mode Either core in active mode can put the part into one of the three power down modes if the core is enabled to do so If both cores are enabled for putting the system into power down then the system enters power down only once both cores have received a WFI or WFE instruction Wake up from sleep mode is caused by an interrupt or event in the core s NVIC The interrupt is captured in the NVIC and an event is captured in the Event router Both cores can wake up from sleep mode independently of each other Wake up from the Power down modes Deep sleep Power down and Deep power down is caused by an event on the WAKEUP pins or an event from the RTC or alarm timer When waking up from Deep power down mode the part resets and attempts to boot Serial Wire Debug JTAG Debug and trace functions are integrated into the ARM Cortex M4 Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions The ARM Cortex M4 is configured to support up to eight breakpoints and four watch points Remark Serial Wire Debug is supported for the ARM Cortex M4 only The ARM Cortex MO coprocessor supports JTAG debug A standard ARM Cortex compliant debugger can debug the ARM Cortex M4 and the ARM Cortex MO
34. time tgisupuv BLS HIGH to data invalid PB 1 2 5 1 4 ns time tWEHANV WE HIGH to address invalid PB 1 0 9 Tey cik 2 4 Tey clk ns time 1 Parameters specified for 40 of Vpp oy for rising edges and 60 of Vppiio for falling edges 2 Tey 1 CCLK see LPC43xx User manual 3 End Of Read EOR longest of tesHoeH toEHANV tcsHBLSH 4 Start Of Read SOR longest of tcsi Av tcsLoEL tcsLBLsL 5 End Of Write EOW earliest of address not valid or EMC_BLSn HIGH EMC An toEHANV lt tcsHEOW EMC_CSn lt tCSLOEL 4 L toELOEH EMC_OE Jat sagen BLSHEOW tcsLBLSL tBLSLBLSH arja EMC_BLSn EMC_WE t tcsLDv am lt 4 CSHEOR tBLSHDNV tcsLsoR gt diii EMC Dn SOR EOR EOW Fig 34 External static memory read write access PB z 0 002aag699 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 121 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller tesa gt lt toEHANV Sl fsa eas EMC CSn 4 CcsLOEL Lt EMC OE 4 toELOEH lt tCSLBLSL tCSHOEH EMC An Sud lcsLAV EMC BLSn tCSHBLSH tesLWEL tWELWEH t
35. 0 1 0 2 0 3 0 4 0 5 0 6 VoL V Conditions Vpp REG 3V3 Vpb o 3 3 V Fig 20 Normal drive pins typical LOW level output current Io versus LOW level output voltage VoL 002aah039 3 6 36 loH mA Conditions Vpp REG 3V3 Vpp o 3 3 V Fig 21 Normal drive pins typical HIGH level output voltage Voi versus HGH level output current loH All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 102 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller 15 a 002aah040 loL Ud mA 25 12 85 C g 6 3 0 0 0 1 0 2 0 3 0 4 0 5 0 6 Vor V Conditions Vpp REG 3V3 Vpp 0 3 3 V normal drive EHD 0x0 40 002aah043 loL mA 32 40 C 25 C 24 85 C 16 8 0 0 0 1 0 2 0 3 0 4 0 5 0 6 Vor V Conditions Vpp REG 3V3 Vpp 0 3 3 V high drive EHD 0x2 25 lot mA 20 15 10 60 lot mA 45 30 15 Fig 22 High drive pins typical LOW level output current lo versus LOW level output voltage VoL 0 0 1 0 2 0 3 0 4 0 5 0 6 0 0 1 0 2 0 3 0 4 0 5 0 6 002aah041 40 C 25 C 85 C
36. 1 ADC1 2 ADCO 3 B5 B4 A3 139 8 IA ADC input channel 3 Shared between 10 bit ADCO 1 ADC1 3 ADCO 4 C6 A5 138 8 IIA ADC input channel 4 Shared between 10 bit ADCO 1 ADC1 4 ADCO 5 B3 C3 l 144 8l IIA ADC input channel 5 Shared between 10 bit ADCO 1 ADC1 5 ADCO 6 A5 A4 142 8 IIA ADC input channel 6 Shared between 10 bit ADCO 1 ADC1 6 ADCO 7 C5 B5 136 8 IIA ADC input channel 7 Shared between 10 bit ADCO 1 ADC1 7 RTC RTC ALARM A11 A10 C3 129 0O O RTC controlled output This pin has an internal pull up The reset state of this pin is LOW after POR For all other types of reset the reset state depends on the state of the RTC alarm interrupt RTCX1 A8 A8 A5 125 B Input to the RTC 32 kHz ultra low power oscillator circuit RTCX2 B8 B7 B5 4126 8 O Output from the RTC 32 kHz ultra low power oscillator circuit Crystal oscillator pins XTAL1 D1 C1 B1 12 8 l Input to the oscillator circuit and internal clock generator circuits XTAL2 E1 D1 Ci 13 B O Output from the oscillator amplifier Power and ground pins USBO VDDA F3 E3 D1 16 Separate analog 3 3 V power supply for driver 3V3 DRIVER LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 58 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontrol
37. 2 V lt Vgar 3 6 Vil typical CRTCX1 2 20 pF also see Section 13 3 Symbol Parameter Conditions Min TypPl Max Unit fiRTC RTC input frequency 32 768 kHz Ipp nrc RTC supply current 280 800 nA 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 107 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 11 6 GPCLKIN Table 19 Dynamic characteristic GPCLKIN Tamb 25 C 2 4 V lt Vpp REG 3V3 lt 3 6 V Symbol Parameter Min Typ Max Unit GP_CLKIN input frequency 25 MHz 11 7 l O pins Table 20 Dynamic characteristic I O pins Tamb 40 C to 85 C 2 7 V lt VppvI0 lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit Standard I O pins normal drive strength tr rise time pin configured as output EHS 1 28 4 0 25 ns tr fall time pin configured as output EHS 1 l8 0 9 25 jns tr rise time pin configured as output EHS 0 28 4 9 4 3 ns tr fall time pin configured as output
38. 20 10 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Table 41 Recommended values for Cx1 x2 in oscillation mode crystal and external components parameters low frequency mode continued Fundamental oscillation Maximum crystal series External load capacitors frequency resistance Rs Cx1 Cx2 12 MHz 160 0 18 pF 18 pF 1600 39 pF 39 pF 16 MHz 1200 18 pF 18 pF 800 33 pF 33 pF 20 MHz 100 Q 18 pF 18 pF 800 33 pF 33 pF Table 42 Recommended values for Cx1 x2 in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation frequency Maximum crystal series resistance Rs External load capacitors Cy Cyo 15 MHz 800 18 pF 18 pF 20 MHz 800 39 pF 39 pF 1000 47 pF 47 pF LPC43xx Cg 100 pF T 002aag379 Fig 43 Slave mode operation of the on chip oscillator LPC43xx CX1 Fig 44 Oscillator modes with external crystal model used for Cy4 Cx2 evaluation T Cx2 C CL CP Rs 002aag380 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 136 of 158 NXP Semiconductors LPC4350 30 20 1 0 13 3 13 4 13 5 LPC4350_30_20_10 32 bit ARM Cortex
39. 3 1 4 9 ns CLKn DELAY 7 l 2 5 3 6 5 8 ns 1 Program the EMC CLKn delay values in the EMCDELAYCLK register see the LPC43xx User manual The delay values must be the same for all SDRAM clocks EMC_CLKn CLKO DELAY CLK1 DELAY CLK2 DELAY CLK3 DELAY LPC4350 30 20 10 Product data sheet All information provided in this document is subject to legal disclaimers Rev 4 5 26 November 2015 NXP Semiconductors N V 2015 All rights reserved 123 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller EMC_CLKn gt EMC DYCSn EMC RAS EMC CAS EMC WE EMC_CKEOUTn EMC A 22 0 EMC_DQMOUTn EMC D 31 0 write register Fig 36 SDRAM timing delay 0 NF Ng XOU X c i EMC CLKn delay tg programmable CLKn DELAY EMC CLKn M Toy ck delay 0 ta xv ta th x ta pe ld xv ta qv ta suD thi i ay MEN 5 as read delay 0 a EMC D 31 0 read delay 0 002aag703 For the programmable EMC_CLK 3 0 clock delays CLKn DELAY see Table 29 Remark For SDRAM operation set CLKO DELAY CLK1 DELAY CLK2 DELAY CLK3_DELAY in the EMCDELAYCLK LPC4350 30 20 10 30 20 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 124
40. 3 of timer 3 1 0 EMC_DO0O External memory data line 0 USB0_PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts R Function reserved R Function reserved R Function reserved LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 11 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 I LBGA256 TFBGA180 TFBGA100 9 LQFP144 GPIO1 1 General purpose digital input output pin U1_DTR Data Terminal Ready output for UART1 O CTOUT 12 SCTimer PWM output 12 Match output 3 of timer 3 lO EMC D1 External memory data line 1 R Function reserved hg UZ es alls R Function reserved R Function reserved O SD_VOLTO SD MMC bus voltage select output 0 P1 9 T7 N5 J5 52 IN l O GPIO1 2 General purpose digital inp
41. 4 8 or 16 to produce the output clock Since the minimum output divider value is 2 it is insured that the PLL output has a 50 duty cycle The PLL is turned off and bypassed following a chip reset After reset software can enable the PLL The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is 100 ps Reset Generation Unit RGU The RGU allows generation of independent reset signals for individual blocks and peripherals on the LPC4350 30 20 10 Power control The LPC4350 30 20 0 feature several independent power domains to control power to the core and the peripherals see Figure 9 The RTC and its associated peripherals the alarm timer the CREG block the OTP controller the back up registers and the event router are located in the RTC power domain The main regulator or a battery supply can power the RTC A power selector switch ensures that the RTC block is always powered on All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 82 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller LPC43xx VDDIO to I O pads vss to cores REGULATOR to memories VDDREG peripherals oscillators MAIN POWER DOMAIN to RTC ULTRA LOW POWER domain I VBAT REGULATOR perip
42. 85 C unless otherwise specified 32 bit ARM Cortex M4 M0 microcontroller Symbol Parameter Conditions Min Typ Max Unit VoH HIGH level output lou 6 mA Vpp o 0 4 V voltage VoL LOW level output lo 6 mA 0 4 V voltage lou HIGH level output Vou Vppio 0 4 V 6 mA current lo LOW level output VoL 0 4 V 6 mA current lous HIGH level short circuit drive HIGH connected to 12 86 5 mA output current ground lots LOW level short circuit drive LOW connected to 12 76 5 mA output current Vpb 0 loa pull down current Vi 5V 4115 93 uA 16 lou pull up current Vi 0V 4115 62 uA 16 Vpp o lt Vis 5 V 10 uA Rs series resistance on I O pins with analog 200 Q function analog function enabled I O pins high drive strength Ci input capacitance 5 2 pF lu LOW level leakage Vi 0 V on chip pull up 3 nA current resistor disabled liu HIGH level leakage Vi Vpp oy on chip 3 nA current pull down resistor disabled Vi 5V 20 nA loz OFF state output Vo 0 Vto Vpp 0 3 nA current on chip pull up down resistors disabled absolute value Vi input voltage pin configured to provide a digital function Vpp o 2 2 2 V 0 5 5 V Vpb o 20V 0 z 3 6 V Vo output voltage output active 0 Vppuo V Vin HIGH level input 0 7 x Vpp o z 5 5 V voltage Vi LOW level input voltage 0 0 3 x V Vpb o Vhys hystere
43. BASE_SPI_CLK LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 116 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 11 13 SSP SPI timing diagrams Toy clk SCK CPOL 0 SCK CPOL 1 MOSI CPHA 0 in Q lt j tha DATA VALID MSB DATA VALID DATA VALID LSB IDLE DATA VALID MSB tps tbH MISO CPHA 0 MI DATA VALID MSB DATA VALID DATA VALID LSB LD DATA VALID MSB MOSI CPHA 1 twa je tha DATA VALID LSB DATA VALID DATA VALID MSB IDLE DATA VALID MSB MISO CPHA 1 ips tpH DATA VALID LSB DATA VALID DATA VALID MSB MEENEEN DATA VALID MSB aaa 013462 Fig 31 SSP master mode timing SPI mode LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 117 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Toy clk SCK CPOL 0 A SCK CPOL 1 co CA e XR d ce E tps tbH a MOSI DATA VALID DATA VALID twa tra CPHA 1 MISO DATA VALID DATA VALID tps tbH L MOSI D
44. C to 85 C Vppao over specified ranges 2 2 V lt Vpp ngay ava lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit Low frequency mode 1 MHz 20 MHz I5 ljt per period jitter time 5 MHz crystal BIA 13 2 ps 10 MHz crystal 6 6 ps 15 MHz crystal 4 8 ps High frequency mode 20 MHz 25 MHz I61 tit per period jitter time 20 MHz crystal BIA 4 3 ps 25 MHz crystal gt 3 7 ps 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 3 Indicates RMS period jitter 4 PLL induced jitter is not included 5 Select HF 0 in the XTAL_OSC_CTRL register 6 Select HF 1 in the XTAL_OSC_CTRL register IRC oscillator Table 17 Dynamic characteristic IRC oscillator Tamb 40 C to 85 C 2 2 V lt Vpp REG 3V3 8 6 VII Symbol Parameter Conditions Min TypPl Max Unit fosc RC internal RC oscillator 11 82 12 0 12 18 MHz frequency 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages RTC oscillator Table 18 Dynamic characteristic RTC oscillator Tamb 40 C to 85 C 2 2 V lt Vpp REG 3V3 3 6 V or 2
45. Dynamic characteristics Static asynchronous external memory interface e Parameter tcsi gi s with condition PB 0 corrected WAITWEN 1 x Tey cik added See Table 26 Dynamic characteristics Static asynchronous external memory interface LPC4350 30 20 10 v 4 1 20131211 Product data sheet LPC4350 30 20 10 v 4 Modifications Description of RESET pin updated in Table 3 Layout of local SRAM at address 0x1008 0000 clarified in Figure 7 LPC4350 30 20 10 Memory mapping overview e Maximum value for Viigus added in Section 13 3 RTC oscillator Vo for RTC ALARM pin added in Table 10 RTC ALARM and WAKEUPn pins added to Table 10 Table note 9 added in Table 10 Timing parameters in Table 31 Dynamic characteristics SD MMC corrected Band gap characteristics removed OTP memory size available for general purpose use corrected Part LPC4350FBD208 removed LPC4350 30 20 10 v 4 20130326 Product data sheet LPC4350 30 20 10 v 3 7 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 152 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 44 Revision history continued Document ID Release date Data sheet status Change notice Supersedes Parameter lj 4
46. EHS 0 Is 1 9 4 0 ins tr rise time pin configured as input A o3 1 3 ins ti fall time pin configured as input AH 02 1 2 ins I O pins high drive strength tr rise time pin configured as output standard 215 4 3 7 9 ns drive mode EHD 0x0 tr fall time pin configured as output standard IS 14 7 8 7 ins drive mode EHD 0x0 tr rise time pin configured as output medium IS 3 2 5 7 ins drive mode EHD 0x1 tr fall time pin configured as output medium 215 3 2 5 5 ins drive mode EHD 0x1 tr rise time pin configured as output high drive 25 2 9 4 9 ns mode EHD 0x2 tr fall time pin configured as output high drive BIS 2 5 3 9 ns mode EHD 0x2 tr rise time pin configured as output ultra high 215 2 8 4 7 ns drive mode EHD 0x3 tr fall time pin configured as output ultra high IS 2 4 3 4 ins drive mode EHD 0x3 tr rise time pin configured as input M 0 3 1 3 ins t fall time pin configured as input AH 02 1 2 ins I O pins high speed tr rise time pin configured as output EHS 1 l8 350 670 ips tr fall time pin configured as output EHS 1 28 450 730 ips tr rise time pin configured as output EHS 0 IS 1 0 1 9 ins tr fall time pin configured as output EHS 0 l8 1 0 2 0 ins tr rise time pin configured as input AH 03 1 3 ins ti fall time pin configured as input AH 02 1 2 ins 1 Simulated data LPC4350 30 20 10
47. GPIO4 5 General purpose digital input output pin PU yo USB1 ULPI DO ULP link bidirectional data line 0 R Function reserved O LCD VD6 LCD data O LCD VD8 LCD data R Function reserved R Function reserved TO_CAP1 Capture input 1 of timer 0 P8 6 K3 J3 BN l O GPIO4 6 General purpose digital input output pin PU UsSBi ULPI NXT ULPI link NXT signal Data flow control signal from the PHY R Function reserved O LCD VD5 LCD data O LCD LP Line synchronization pulse STN Horizontal synchronization pulse TFT R Function reserved R Function reserved TO CAP2 Capture input 2 of timer 0 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 34 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description Kel e S 8 x x lt 6 oO 8 B BP g e E a eNA P8 7 Ki J 2 N O GPIO4 7 General purpose digital input output pin PU USB1_ULPI_STP ULP link STP signal Asserted to end o
48. High level leakage current for condition V 5 V changed to 20 nA max See Table 10 e Parameter Vppa ava added for pins USBO VDDA3V3 DRIVER and USBO_VDDAS8V3 in Table 10 SPI timing data added See Table 22 SGPIO timing data added See Table 23 SPI and SGPIO peripheral power consumption added in Table 11 Data sheet status changed to Product data sheet Corrected max voltage on pins USBO DP USBO DM USBO VBUS USB1 DP and USB1 DM in Table 6 and Table 10 to be consistent with USB specifications LPC4350 30 20 10 v 3 7 20130131 Preliminary data sheet LPC4350 30 20 10 v 3 6 Modifications SGPIO and SPI location corrected in Figure 1 SGPIO to DMA connection corrected in Figure 7 e Power consumption in active mode corrected See parameter Ipp nEay ava In Table 10 and graphs Figure 12 Figure 13 and Figure 14 e Parameter name Ipp apc changed to Ippa in Table 10 Figure 21 Band gap voltage for different temperatures and process conditions and Table 13 Band gap characteristics corrected Added note to limit data in Table 24 Dynamic characteristics Static asynchronous external memory interface to single memory accesses e Value of parameter lpp ngG ava in deep power down increased to 0 03 pA in Table 10 e Value of parameter lpp o in deep power down increased to 0 05 pA in Table 10 LPC4350 30 20 10 v 3 6 20121119 Preliminary data sheet LPC4350 30 20 10 v 3
49. Internal RC IRC oscillator trimmed to 1 5 96 accuracy over temperature and voltage Ultra low power Real Time Clock RTC crystal oscillator Three PLLs allow CPU operation up to the maximum CPU rate without the need for a high frequency crystal The second PLL is dedicated to the High speed USB the third PLL can be used as audio PLL Clock output W Configurable digital peripherals Serial GPIO SGPIO interface State Configurable Timer SCTimer PWM subsystem on AHB Global Input Multiplexer Array GIMA allows to cross connect multiple inputs and outputs to event driven peripherals like the timers SCTimer PWM and ADCO 1 E Serial interfaces Quad SPI Flash Interface SPIFI with 1 2 or 4 bit data at rates of up to 52 MB per second 10 100T Ethernet MAC with RMII and MII interfaces and DMA support for high throughput at low CPU load Support for IEEE 1588 time stamping advanced time stamping IEEE 1588 2008 v2 One High speed USB 2 0 Host Device OTG interface with DMA support and on chip high speed PHY USBO One High speed USB 2 0 Host Device interface with DMA support on chip full speed PHY and ULPI interface to external high speed PHY USB1 USB interface electrical test software included in ROM USB stack Four 550 UARTs with DMA support one UART with full modem interface one UART with IrDA interface three USARTs support UART synchronous mode and a smart card interface
50. M4 M0 microcontroller 7 6 1 Features 7 6 2 LPC4350_30_20_10 7 7 7 8 7 9 Controls system exceptions and peripheral interrupts The Cortex M4 NVIC supports up to 53 vectored interrupts Eight programmable interrupt priority levels with hardware priority level masking e Relocatable vector table Non Maskable Interrupt NMI Software interrupt generation Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags Individual interrupt flags can represent more than one interrupt source System Tick timer SysTick The ARM Cortex M4 includes a system tick timer SysTick that is intended to generate a dedicated SYSTICK exception at a 10 ms interval Remark The SysTick is not included in the ARM Cortex MO core Event router The event router combines various internal signals interrupts and the external interrupt pins WAKEUPT 3 0 to create an interrupt in the NVIC if enabled In addition the event router creates a wake up signal to the ARM core and the CCU for waking up from Sleep Deep sleep Power down and Deep power down modes Individual events can be configured as edge or level sensitive and can be enabled or disabled in the event router The event router can be battery powered The following events if enabled in the event router can create a wake up signal from sleep deep sleep power down and deep power down modes and or create an i
51. M4 M0 microcontroller RTC oscillator In the RTC oscillator circuit only the crystal XTAL and the capacitances Crtcx and Crtcxe need to be connected externally Typical capacitance values for Cgrcx and Cnrcxe are Catcxt 2 20 typical 4 pF An external clock can be connected to RTCX1 if RTCX2 is left open The recommended amplitude of the clock signal is Viigus 100 mV to 200 mV with a coupling capacitance of 5 pF to 10 pF Virgus must be lower than 450 mV See Figure 43 for a similar slave mode set up that uses the crystal oscillator LPC43xx RTCX1 RTCX2 XTAL mli CRTCX1 CRTCX2 002aah148 Fig 45 RTC 32 kHz oscillator circuit XTAL and RTCX Printed Circuit Board PCB layout guidelines Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors C4 Cy and Cyg in case of third overtone crystal usage have a common ground plane Also connect the external components to the ground plain To keep the noise coupled in via the PCB as small as possible make loops and parasitics as small as possible Choose smaller values of C4 and C 2 if parasitics increase in the PCB layout Ensure that no high speed or high drive signals are near the RTCX1 2 signals Standard I O pin configuration Figure 46 shows the possible pin modes for standard I O pins with analog input function Digital output driver enabled disabled Digital
52. R Function reserved R Function reserved R Function reserved R Function reserved l O SGPIO12 General purpose digital input output pin P4 7 H4 F4 14 B 0 O LCD DCLK LCD panel clock PU GP_CLKIN General purpose clock input to the CGU R Function reserved R Function reserved R Function reserved R Function reserved VO 12S1_TX_SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I S bus specification lO 12S0_TX_SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the l2S bus specification P4 8 E2 D2 l 15 B N R Function reserved PU CTIN_5 SCTimer PWM input 5 Capture input 2 of timer 2 O LCD_VD9 LCD data R Function reserved lO GPIO5 12 General purpose digital input output pin O LCD VD22 LCD data O CAN1 TD CANT transmitter output lO SGPIO13 General purpose digital input output pin LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 24 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin descri
53. SSP controller can operate on a SPI 4 wire SSI or Microwire bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SSP supports full duplex All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 75 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 18 4 1 7 18 5 7 18 5 1 7 18 6 LPC4350 30 20 10 32 bit ARM Cortex M4 MO microcontroller transfers with frames of 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features Maximum SSP speed in full duplex mode of 25 Mbit s for transmit only 50 Mbit s master and 17 Mbit s slave Compatible with Motorola SPI 4 wire Texas Instruments SSI and National Semiconductor Microwire buses e Synchronous serial communication Master or slave operation 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame DMA transfers supported by GPDMA I2C bus interface Remark The LPC4350 30 20 10 contain two I2C bus interfaces The I C bus is bidirectional for inter IC control using only two wires a Serial Clock line SCL and a Serial Data line SDA Each device is recognized by a unique address and can ope
54. Timer SCTimer PWM 7 19 5 Windowed WatchDog Timer WWDT 79 S osoioosis Rei Die ghd 68 7 19 5 1 Features 000000 ess 79 7 16 1 1 Features eee eee eg 7 20 Analog peripherals 00005 80 7 16 2 Serial GPIO SGPIO esses e9 720 1 Analog to Digital Converter ADU e 7 46 24 JEBHIUIBS veiut caedi ia iHd Rid sciet ME C Ab MAR PEEL 39 747 AHB peripherals ssssse esee 70 7 20 2 Digital to Analog Converter DAC 80 7474 General Purpose DMA GPDMA 70 7 20 2 1 Features ce ees 80 TATAAN FOAtureS costae aer Reed n 70 7 21 Peripherals in the RTC power domain 80 7 47 2 SPI Flash Interface SPIFI 70 L214 RTC eee eee eee 80 7 47 24 no REPRE 7i ee FBAIUTES aaa gE iea eE doit peus tu 80 7 17 3 SD MNC card interface 71 7 21 2 Alami imet 3 3 Seed ened Le hee a E Roe 81 7 17 4 External Memory Controller EMC 71 7 22 System control E P AE DO EER LS 81 T4744 Features n o n a naraon bh ri 74 7221 Configuration registers CREG 81 7 17 5 High speed USB Host Device OTG interface 7 22 2 System Control Unit SCU 81 USB0 MRNA ANC DEOR EKNE 72 7 22 3 Clock Generation Unit CGU 81 ATE TU MEN 72 uec i htermal RO oscilator UPC ees ipinia pe 7 22 5 PLLOUSB for USBO 82 continued gt gt LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NX
55. and phase and can have different clock sources within the CGU One CGU base clock is routed to the CLKOUT pins The base clock that generates the CPU clock is referred to as CCLK Multiple branch clocks are derived from each base clock The branch clocks offer flexible control for power management purposes All branch clocks are outputs of one of two Clock Control Units CCUs and can be controlled independently Branch clocks derived from the same base clock are synchronous in frequency and phase All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 81 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 22 4 7 22 5 7 22 6 7 22 7 7 22 8 7 22 9 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Internal RC oscillator IRC The IRC is used as the clock source for the WWDT and or as the clock that drives the PLLs and the CPU The nominal IRC frequency is 12 MHz The IRC is trimmed to 1 5 accuracy over the entire voltage and temperature range Upon power up or any chip reset the LPC4350 30 20 10 use the IRC as the clock source The boot loader then configures the PLL1 to provide a 96 MHz clock for the core and the PLLOUSB or PLLOAUDIO as needed if an external boot source is selected PLLOUSB for USBO PLLO is a dedicated PLL for the USBO High speed controller PLLO accepts an input c
56. changes the address while CS is asserted resulting in multiple memory accesses Symbol Parameter Conditions Min Typ Max Unit Read cycle parameters tosav CS LOW to address valid 3 1 1 6 ns time CSLOEL CS LOW to OE LOW time 2 0 6 Tey clk x 1 34 Toy clk x ns WAITOEN WAITOEN tcsugis CS LOW to BLS LOW time PB 1 0 7 1 8 ns toeLoeH OE LOW to OE HIGH time 2 0 6 0 4 ns WAITRD WAITRD WAITOEN 1 x WAITOEN 1 x Tey clk Tey clk tam memory access time 16 ns WAITRD WAITOEN 1 x Tey clk th D data input hold time 16 5 ns tcsHBLsH CS HIGH to BLS HIGH time PB 1 0 4 1 9 ns tcsHoeH CS HIGH to OE HIGH time 0 4 1 4 ns toeHaANv OE HIGH to address invalid PB 1 2 0 2 6 ns tcsHEOR CS HIGH to end of read Bl 2 0 0 ns time icsison CS LOW to start of read A 0 1 8 ns time Write cycle parameters tesLav CS LOW to address valid 3 1 1 6 ns time tesLDV CS LOW to data valid time 3 1 1 5 ns tes iweL CS LOW to WE LOW time PB 1 1 5 0 2 ns WAITWEN 1 WAITWEN 1 X Tey clk X Tey clk tcstpsL CS LOW to BLS LOW time PB 1 0 7 1 8 ns twetweH WE LOW to WE HIGH time PB 1 2 0 6 0 4 ns WAITWR WAITWR WAITWEN 1 x WAITWEN 1 x Tey clk Toy cll tWEHDNV WE HIGH to data invalid PB 1 21 0 9 Toy clk 2 3 4 Toy clk ns time twEHEOW WE HIGH to end of write PB
57. conforming to ISO7816 specification Up to two C_CAN 2 0B controllers with one channel each Use of C_CAN controller excludes operation of all other peripherals connected to the same bus bridge See Figure 1 and Ref 2 Two SSP controllers with FIFO and multi protocol support Both SSPs with DMA support One SPI controller LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 2 of 158 NXP Semiconductors LPC4350 30 20 1 0 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller One Fast mode Plus I C bus interface with monitor mode and with open drain I O pins conforming to the full C bus specification Supports data rates of up to 1 Mbit s One standard I C bus interface with monitor mode and with standard I O pins Two I S interfaces each with DMA support and with one input and one output Digital peripherals External Memory Controller EMC supporting external SRAM ROM NOR flash and SDRAM devices LCD controller with DMA support and a programmable display resolution of up to 1024 H x 768 V Supports monochrome and color STN panels and TFT color panels supports 1 2 4 8 bpp Color Look Up Table CLUT and 16 24 bit direct pixel mapping Secure Digital Input Output SD MMC card interface Eight channel General Purpose DMA controller ca
58. control PWM channel 0 input l O SGPIO10 General purpose digital input output pin R Function reserved R Function reserved O TO MAT2 Match output 2 of timer 0 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 33 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description o 2 2 g E 3 is js kis 8g B P s jg E Er E a eae P8 3 J3 H3 l 2 N O GPIO4 3 General purpose digital input output pin PU VO USB1 ULPI D2 ULP link bidirectional data line 2 R Function reserved LCD VD12 LCD data LCD VD19 LCD data R Function reserved OO R Function reserved O TO MATS Match output 3 of timer 0 P8 4 J2 H2 Bl IN l O GPIO4 4 General purpose digital input output pin PU yo USB1 ULPI D1 ULP link bidirectional data line 1 R Function reserved O LCD VD7 LCD data O LCD VD16 LCD data R Function reserved R Function reserved TO CAPO0 Capture input 0 of timer 0 P8 5 J1 H1 Bl IN l O
59. cores separately or both cores simultaneously Remark In order to debug the ARM Cortex MO release the MO reset by software in the RGU block All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 84 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller LPC43xx TCK ARM Cortex MO TCK ARM Cortex M4 TMS TRST TDI TDO TDI TDO JTAG ID OxOBAO 1477 JTAG ID Ox4BAO 0477 TDO 4 DBGEN DBGEN HIGH RESET RESET HIGH 002aah448 Fig 10 Dual core debug configuration LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 85 of 158 LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller NXP Semiconductors 8 Limiting values Table 6 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 Symbol Parameter Conditions Min Max Unit Vpp REG 3v3 regulator supply voltage jon pin VDDREG 0 5 3 6 V 3 3 V VDpD O input output supply on pin VDDIO 0 5 3 6 V voltage VppA 3V3 analog supply voltage on pin VDDA 0 5 3 6 V 8 3 V VBAT battery supply voltage on pin VBA
60. local SRAM oio odn 0x1008 A000 LPC4350 30 32 MB AHB SRAM bit banding 32 kB 8 kB local SRAM 0x2200 0000 reserve TS 0x1008 0000 ee 0x2001 0000 16 kB AHB SRAM LPC4350 30 20 10 0x2000 C000 16 kB AHB SRAM LPC4350 30 20 0x2000 8000 16 kB AHB SRAM LPC4350 30 20 0x2000 4000 LPC4350 30 20 10 16 kB AHB SRAM LPC4350 30 20 10 0x2000 0000 0x1000 0000 Pd 4 do 0 local SRAM external static memory banks 0x1000 0000 0GB 256 MB shadow area 0x0000 0000 002aat774 e 32 kB local SRAM LPC4350 30 0x1001 8000 96 kB local SRAM Fig 7 LPC4350 30 20 10 Memory mapping overview LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 66 of 158 eeus ejep JONPOld SLOZ JequieAoN 92 G p 9H sieuirejosip ee 0 joefqns s jueuunoop S14 ui pepi oid uoneuuojul y 8S1 JO 79 Ol 02 0 OSEPOd 1 pamasa siuBu Ily GLOZ N N s1ojonpuooiuegs dXN 0x400F 0000 Ox400E 5000 Ox400E 4000 Ox400E 3000 Ox400E 2000 Ox400E 1000 Ox400E 0000 0x400C 8000 0x400C 7000 0x400C 6000 0x400C 5000 0x400C 4000 0x400C 3000 0x400C 2000 0x400C 1000 0x400C 0000 0x400B 0000 0x400A 5000 0x400A 4000 0x400A 3000 0x400A 2000 0x400A 1000 0x400A 0000 0x4008 A000 0x4008 9000 0x4008 8000 0x4008 7000 0x4008 6000 0x4008 5000 0x4008 4000 0x4008 3000 0x4008 20
61. nA current pull down resistor disabled Vi 5V 20 nA loz OFF state output Vo 0V to Vpp oy 3 nA current on chip pull up down resistors disabled absolute value Vi input voltage pin configured to provide a digital function Vpp o gt 2 2V 0 z 5 5 V Vppuo 0 V 0 3 6 V Vo output voltage output active 0 Vppuo V Vin HIGH level input 0 7 x Vpb o s 5 5 V voltage ViL LOW level input voltage 0 0 3 x V Vpb o Vhys hysteresis voltage 0 1 x Vppiio V Vou HIGH level output lou 8 mA Vpp o 0 4 V voltage VoL LOW level output lo 8 mA 0 4 V voltage lou HIGH level output Vou VbDD 10 0 4 V 8 mA current lot LOW level output VoL 0 4 V 8 mA current lous HIGH level short circuit drive HIGH connected to 12 86 mA output current ground lots LOW level short circuit drive LOW connected to 12 76 mA output current Vpp o lod pull down current Vi Vppio 141 15 62 uA 16 lou pull up current Vi 0V 4115 62 uA 16 Vpp o lt V lt 5V 0 uA Open drain I2C0 bus pins Vin HIGH level input 0 7 x VppiIo 7 5 V voltage ViL LOW level input voltage 0 0 14 0 3 x V Vpp 0 Vhys hysteresis voltage 0 1 x Vpp o V VoL LOW level output lois 3 mA 0 4 V voltage lu input leakage current Vi Vpp o 13 4 5 uA VI 5 V 10 uA LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserv
62. of 158 NXP Semiconductors LPC4350 30 20 10 11 Table 30 16 USB interface 32 bit ARM Cortex M4 MO microcontroller Dynamic characteristics USBO and USB1 pins full speed C 50 pF Rou 1 5 k2 on D to Vpb io 3 0 V lt VppvI0 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 to 90 4 20 ns tr fall time 10 to 90 96 4 20 ns tFRFM differential rise and fall time matching t t 90 111 11 96 Vcns output signal crossover voltage 1 3 2 0 V tFEOPT source SEO interval of EOP see Figure 37 160 175 ns teDEOP source jitter for differential transition see Figure 37 2 45 ns to SEO transition Uni receiver jitter to next transition 18 5 18 5 ns tJR2 receiver jitter for paired transitions 10 to 90 9 9 ns tEoPR1 EOP width at receiver must reject as 11 40 ns EOP see Figure 37 TEOPR2 EOP width at receiver must accept as 1 182 ns EOP see Figure 37 1 Characterized but not implemented as production test Guaranteed by design Remark If only USBO HS USB is used the pins VDDREG and VDDIO can be at different voltages within the operating range but should have the same ramp up time If USB1 FS USB is used the pins VDDREG and VDDIO should be a minimum of 3 0 V and be tied together differential data lines TPERIOD Desine differential data to crossover point
63. output pin R Function reserved SD WP SD MMC card write protect input R Function reserved Al ADCO 5 ADCO and ADC1 input channel 5 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 11 A2 l BI N R Function reserved PU Ug RXD Receiver input for USARTO R Function reserved R Function reserved l O GPIO7 25 General purpose digital input output pin R Function reserved O SD_VOLT2 SD MMC bus voltage select output 2 R Function reserved Al ADC1 5 ADC1 and ADCO input channel 5 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 55 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol g Q 2 F 3 Description 3 8 83 L is g B B5 j E T E a erie Clock pins CLKO N5 M4 K3 45
64. peripherals disabled all peripheral clocks disabled Fig 11 Typical supply current versus regulator supply voltage Vpp nEGysva in active mode 100 002aah612 IDD REG 3V3 mA MA 204 MHz 89 L r 35 180 MHz reme LM tl S 60 120 MHz KENNEN God NN ERN ee E 40 60 MHz 20 12 MHz 40 15 10 35 60 85 temperature C Conditions Vpp REa ava 3 3 V Active mode entered executing code while 1 from SRAM MO core in reset internal pull up resistors disabled PLL1 enabled IRC enabled all peripherals disabled all peripheral clocks disabled Fig 12 Typical supply current versus temperature in Active mode LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 95 of 158 NXP Semiconductors LPC4350 30 20 1 0 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller 450 ae IDD REG 3V3 25 C mA 40 C 80 60 40 20 0 12 36 60 84 108 132 156 180 204 CCLK frequency MHz Conditions Vpp REq 3v3 3 3 V Active mode entered executing code while 1 from SRAM MO core in reset internal pull up resistors disabled PLL1 enabled IRC enabled all peripherals disabled all peripheral clocks disa
65. the SPIFI interface using pins P3 3 to P3 8 EMC 8 bit 0 0 1 1 Boot from external static memory such as NOR flash using CSO and an 8 bit data bus LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 64 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 4 Boot mode when OTP BOOT_SRC bits are programmed continued Boot mode BOOT_SRC BOOT_SRC BOOT SRC BOOT_SRC Description bit 3 bit 2 bit 1 bit 0 EMC 16 bit 0 1 0 0 Boot from external static memory such as NOR flash using CSO and a 16 bit data bus EMC 32 bit 0 1 0 1 Boot from external static memory such as NOR flash using CSO and a 32 bit data bus USBO 0 1 1 0 Boot from USBO USB1 0 1 1 1 Boot from USB1 SPI SSP 1 0 0 0 Boot from SPI flash connected to the SSPO interface on P3_3 function SSPO SCK P3 6 function SSPO_SSEL P3 7 function SSPO0 MISO and P3 8 function SSPO MOSIJII USART3 1 0 0 1 Boot from device connected to USART3 using pins P2 3and P2 4 1 The boot loader programs the appropriate pin function at reset to boot using either SSPO or SPIFI Remark Pin functions for SPIFI and SSPO boot are different Table 5 Boot mode when OPT BOOT SRC bits are zero
66. with Universal Serial Bus specification 2 0 Complies with Enhanced Host Controller Interface Specification All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 72 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller e Supports auto USB 2 0 mode discovery Supports all high speed USB compliant peripherals if connected to external ULPI PHY e Supports all full speed USB compliant peripherals e Supports interrupts This module has its own integrated DMA engine USB interface electrical test software included in ROM USB stack 7 17 7 LCD controller 7 17 7 1 LPC4350 30 20 10 Remark The LCD controller is available on LPC4350 only See Table 2 The LCD controller provides all of the necessary control signals to interface directly to various color and monochrome LCD panels Both STN single and dual panel and TFT panels can be operated The display resolution is selectable and can be up to 1024 x 768 pixels Several color modes are provided up to a 24 bit true color non palettized mode An on chip 512 byte color palette allows reducing bus utilization that is memory size of the displayed data while still supporting many colors The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions
67. 00 0x4008 1000 0x4008 0000 Fig 8 GIMA a o reserved C CAN1 1281 1250 I2CO motor control PWM GPIO GROUP interrupt GPIO GROUPO interrupt GPIO interrupts external memory banks LPC4350 30 20 10 Memory mapping peripherals SRAM memories 0x4000 0000 0x0000 0000 LPC4350 30 20 10 D usen d OxFFFF FFFF ie us external memories and uo Peripnerals g ARM private bus 0x6000 0000 reserved 0x4400 0000 eripheral bit band alias region i pere 3 0x4200 0000 clocking reserved Su reset control 0x4010 2000 peripherals 0x4010 1000 0x4010 0000 APB2 reserved ue peripherals 0x400F 8000 L high speed GPIO 0x400F 4000 J reserved es I 0x400F 2000 reserved 0x400F 0000 peripherals APB3 peripherals ox400E 0000 reserved gt 0x400D 0000 Apes APB2 peripherals 0x400C 0000 peripherals un reserved 0x400B 0000 cod APB1 peripherals 0x400A 0000 reserved 0x4009 0000 APBO peripherals 0x4008 0000 x reserved ENS 0x4006 0000 clocking reset peripherals ox4005 0000 RTC domain peripherals 7 0x40040000 0000 AHB J APBO s reserved Au peripherals peripherals 0x4001 2000 Lo AHB peripherals gt 0x4006 0000 0x4005 4000 0x4005 3000 0x4005 2000 0x4005 1000 0x4005 0000 reserved RGU CCU2 CCU1 CGU RTC PRTC ox4004 6000 0x4004 3000 0x4004 2000 0x4004 0000 0x4001 2000 0x4001 0000 0x4000 9000 CD
68. 1 in SPIFI quad mode SPIFI output 101 R Function reserved l O SSPO MISO Master In Slave Out for SSPO R Function reserved R Function reserved P3 7 C11 C10 D7 123 B N R Function reserved PU yo SPI MOSI Master Out Slave In for SPI lO SSPO MISO Master In Slave Out for SSPO l O SPIFI MOSI Input IO in SPIFI quad mode SPIFI output IOO l O GPIOB5 10 General purpose digital input output pin lO SSPO MOSI Master Out Slave in for SSPO R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 21 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description oO eo eo S i y b t lt o amp z g Bg amp a2 d E J E P3 8 C10 C9 E7 124 B N R Function reserved PU SPI_SSEL Slave Select for SPI Note that this pin in an input pin only The SPI in master mode cannot drive the CS input on the slave Any GPIO pin can be used for SPI chip select in master mode l O SSPO MOSI
69. 1 of timer 1 O EMC A5 External memory address line 5 R Function reserved R Function reserved O SSPO SSEL Slave Select for SSPO 1 0 SGPIO7 General purpose digital input output pin R Function reserved LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 9 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol g o e m 3 Description 3 8 3 jz g g B B 5 j H 5 z c P11 R2 Ni K2 42 2 IN O GPIOO 8 General purpose digital input output pin Boot pin PU see Table 5 O CTOUT_7 SCTimer PWM output 7 Match output 3 of timer 1 l O EMC A6 External memory address line 6 l O SGPIO8 General purpose digital input output pin R Function reserved lO SSPO MISO Master In Slave Out for SSPO R Function reserved R Function reserved P1 2 R3 N2 Ki 43 B N l O GPIOO 9 General purpose digital input output pin Boot pin PU see Table 5 O CTOUT_6 SCTimer PW
70. 281 TX SDA 12S1 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification Al ADC1 3 ADC1 and ADCO input channel 3 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 7 B7 BN R Function reserved PU VO U3 BAUD Baud pin for USART3 O SSP1 MOSI Master Out Slave in for SSP1 O TRACEDATA Trace data bit 2 lO GPIO7 21 General purpose digital input output pin R Function reserved lO SGPIO6 General purpose digital input output pin V O 2S81 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the PS bus specification Al ADC1 7 ADC1 and ADCO input channel 7 or band gap O output Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PF 8 E6 l BN R Function reserved PU yo UO UCLK Serial clock input output for USARTO in synchronous mode CTIN 2 SCTimer PWM input 2 Capture input 2 of timer 0 O TRACEDATA 3 Trace data bit 3 lO GPIO7 22 General purpose digital input output pin R Function reserved lO SGPIO7 General purpose digital input output pin R Function reserved Al ADCO 2 ADCO and ADC1 input channel 2
71. 2S0 and I2S1 pins Simulated values Symbol Parameter Conditions Min Typ Max Unit common to input and output tr rise time 4 ns tr fall time ns twH pulse width HIGH on pins l2Sx_TX_SCK 36 5 ns and 12Sx_RX_SCK twL pulse width LOW on pins 12Sx_TX_SCK 36 ns and 28x RX SCK output twa data output valid time jon pinl2Sx_TX_SDA HO 4 4 ns on pin l2Sx_TX_WS 4 3 ns input tsu D data input set up time jon pin l25x RX SDA H 0 ns on pin l283x RX WS 0 20 ns thi data input hold time jonpinl2Sx_RX_SDA H 3 7 ns on pin l283x RX WS 3 9 ns 1 Clock to the I2S bus interface BASE APB1 CLK 150 MHz peripheral clock to the I2S bus interface PCLK BASE APB1 CLK 12 I S clock cycle time Tey cik 79 2 ns corresponds to the SCK signal in the S bus specification LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 110 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller 12Sx_TX_SCK 12Sx_TX_SDA 12Sx_TX_WS Toy clk twH tw tva I lt twa Fig 28 I S bus transmit 002aag497 12Sx_RX_SCK 12Sx_RX_SDA I2Sx RX WS Toy clk twH tw tsu D tn D
72. 4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol g Q 2 F 3 Description 3 8 3 g g B B 5 j m E ele P4 2 D3 A2 8 B N VO GPIO2 2 General purpose digital input output pin PU lo CTOUT 0 SCTimer PWM output 0 Match output 0 of timer 0 O LCD VD3 LCD data R Function reserved R Function reserved O LCD VD12 LCD data U3 RXD Receiver input for USART3 l O SGPIO8 General purpose digital input output pin P4 3 C2 B2 7 BI N VO GPIO2 3 General purpose digital input output pin PU lo CTOUT 3 SCTimer PWM output 3 Match output 3 of timer 0 O LCD VD2 LCD data R Function reserved R Function reserved O LCD VD21 LCD data VO U3 BAUD Baud pin for USARTS l O SGPIO9 General purpose digital input output pin Al ADCO 0 DAC output ADCO and ADC1 input channel 0 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P4 4 Bl Al 9 Bl N O GPIO2 4 General purpose digital input output pin PU g CTOUT 2 SCTimer PWM output 2 Match output 2 of timer 0 O LCD VD1 LCD data R Function reserved R Function reserved O LLCD VD20 L
73. 5 Modifications Table 13 Band gap characteristics added Power consumption for MO core added in Table 11 Peripheral power consumption Section 7 22 10 Power Management Controller PMC added Table 10 added Table note 2 Dynamic characteristics for peripherals are provided for Vpp REG ava 2 2 7 V Description of ADC pins on digital analog input pins changed Each input to the ADC is connected to ADCO and ADC1 See Table 3 Use of C CAN peripheral restricted in Section 2 ADC channels limited to a total of 8 channels shared between ADCO and ADC1 Minimum value for parameter Vi changed to 0 V in Table 10 Static characteristics LPC4350 30 20 10 v 3 5 20121011 Preliminary data sheet LPC4350 30 20 10 v 3 4 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 153 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 44 Revision history continued Document ID Release date Data sheet status Change notice Supersedes Modifications e Temperature range for simulated timing characteristics corrected to Tamb 40 C to 85 C in Section 11 Dynamic characteristics SPIFI timing added See Section 11 15 SPIFI maximum data rate changed to 52 MB per second Editorial updates
74. 6 V 4 0 15 LSB 2 2 V lt VppA ava lt 2 7 V 0 15 LSB Ec gain error 2 7 V lt Vppa ava 3 6 V ISI 0 3 2 2 V VppA ava lt 2 7 V 0 35 Er absolute error 2 7 V Vppa ava 3 6 V 6 3 LSB 2 2 V VppA ava lt 2 7 V 4 LSB Rysi voltage source interface see Figure 42 1 7 xfakapc KQ resistance x Cia Ri input resistance i8 1 2 MQ fakpc ADC clock frequency 4 5 MHz fs sampling frequency 10 bit resolution 11 clock 400 kSamples s cycles 2 bit resolution 3 clock 1 5 MSamples s cycles 1 The ADC is monotonic there are no missing codes 2 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 41 3 The integral non linearity E aq is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors See Figure 41 4 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 41 5 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 41 6 The absolute error Er is the maximum difference between the center of the steps of the actual transfe
75. ATA VALID DATA VALID twa gt 4 lt tha CPHA 0 MISO DATA VALID DATA VALID 002aae830 Fig 32 SSP slave mode timing SPI mode 11 14 SGPIO timing The following considerations apply to SGPIO timing e SGPIO input signals are synchronized by the internal clock SGPIO_CLOCK To guarantee that no samples are missed all input signals should have a duration of at least one SGPIO_CLOCK cycle plus the set up and hold times When an external clock input is used to generate output data synchronization causes a latency of at least one SGPIO_CLOCK cycle The maximum output data rate is one output every two SGPIO CLOCK cycles Synchronization also causes a latency of one SGPIO CLOCK cycle when sampling several inputs This may cause inputs with very similar timings to be sampled with a difference of one SGPIO CLOCK cycle LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 118 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 26 Dynamic characteristics SGPIO Tamb 40 C to 85 C 22V lt Vpp REG 3V3 S3 6V 2 7Vs VppiI0 lt 3 6 V Simulated values Symbol Parameter Conditions Min Typ Max Unit tsu D data input set up ti
76. All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 143 of 158 NXP Semiconductors LPC4350 30 20 10 LQFP144 plastic low profile quad flat package 144 leads body 20 x 20 x 1 4mm 32 bit ARM Cortex M4 M0 microcontroller SOT486 1 Pe pin 1 index DIMENSIONS mm are the original dimensions detail X UNIT Ai Ao A3 bp c 1 45 1 35 Note 1 Plastic or me al protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES VERSION IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE SOT486 1 136E23 MS 026 EQ on Fig 54 Package outline for the LQFP144 package LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 144 of 158 NXP Semiconductors LPC4350 30 20 10 15 Soldering 32 bit ARM Cortex M4 M0 microcontroller Footprint information for reflow soldering of LBGA256 package
77. All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 108 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 2 Simulated using 10 cm of 50 Q PCB trace with 5 pF receiver input Rise and fall times measured between 80 96 and 20 96 of the full output signal level 3 The slew rate is configured in the system control block in the SFSP registers using the EHS bit See the LPC43xx user manual 4 C 20 pF Rise and fall times measured between 90 and 10 of the full input signal level 5 The drive modes are configured in the system control block in the SFSP registers using the EHD bit See the LPC43xx user manual 11 8 12C bus Table 21 Dynamic characteristic I2C bus pins Tamb 40 C to 85 C 22V lt Vpop REG 3v3 lt 3 6 AUI Symbol Parameter Conditions Min Max Unit fscL SCL clock frequency Standard mode 0 100 kHz Fast mode 0 400 kHz Fast mode Plus 0 1 MHz tf fall time SII4ISII6l of both SDA and 300 ns SCL signals Standard mode Fast mode 20 0 1 x Og 300 ns Fast mode Plus 120 ns ti ow LOW period of the SCL clock Standard mode 4 7 us Fast mode 1 3 us Fast mode Plus 0 5 us tHIGH HIGH period of the SCL clock Standard mode 4 0 us Fast mode 0 6 us Fast mode Plu
78. C 12 Allowed as long as the current limit does not exceed the maximum current allowed by the device 13 To Vgs 14 The values specified are simulated and absolute values 15 The weak pull up resistor is connected to the Vpp oy rail and pulls up the I O pin to the Vpp oy level 16 The input cell disables the weak pull up resistor when the applied input voltage exceeds Vpp o 17 The parameter value specified is a simulated value excluding bond capacitance 18 For USB operation 3 0 V lt Vpp to lt 3 6 V Guaranteed by design 19 Vpp o present 20 Includes external resistors of 33 Q 1 96 on D and D LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 94 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 10 1 Power consumption 002aah611 100 IDD REG 3V3 mA mA 204 MHz LLL 80 180 MHz CT ee NNNM SN 60 120 MHz 40 60 MHz 20 12 MHz M 0 2 2 24 2 6 2 8 3 3 2 34 3 6 VDD REG 3V3 V Conditions Tamb 25 C active mode entered executing code while 1 from SRAM MO core in reset internal pull up resistors disabled PLL1 enabled IRC enabled all
79. C4350FET180 TFBGA180 Thin fine pitch ball grid array package 180 balls SOT570 3 LPC4330FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LPC4330FET180 TFBGA180 Thin fine pitch ball grid array package 180 balls SOT570 3 LPC4330FET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC4330FBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC4320FET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC4320FBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 LPC4310FET100 TFBGA100 Plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm SOT926 1 LPC4310FBD144 LQFP144 Plastic low profile quad flat package 144 leads body 20 x 20 x 1 4 mm SOT486 1 4 1 Ordering options Table 2 Ordering options Type number Total LCD Ethernet USBO USB1 ADC Motor QEI GPIO Package SRAM Host Host channels control Device Device PWM OTG ULPI interface LPC4350FET256 264kB yes yes yes yes yes 8 yes yes 164 LBGA256 LPC4350FET180 264kB yes yes yes yes yes 8 yes yes 118 TFBGA180 LPC4330FET256 264kB no yes yes yes yes 8 yes yes 164 LBGA256 LPC4330FET180 264kB no yes yes yes yes 8 yes yes 118 TFBGA180 LPC4330FE
80. CD data O US3 DIR RS 485 EIA 485 output enable direction control for USART3 lO SGPIO10 General purpose digital input output pin O DAC DAC output Shared between 10 bit ADCO 1 and DAC Configure the pin as GPIO input and use the analog function select register in the SCU to select the DAC LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 23 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 TFBGA100 LOFP144 O LBGA256 Q TFBGA180 P4 5 GPIO2 5 General purpose digital input output pin CTOUT 5 SCTimer PWM output 5 Match output 3 of timer 3 O LCD FP Frame pulse STN Vertical synchronization pulse TFT R Function reserved 5 UZ es 96 R Function reserved R Function reserved R Function reserved lO SGPIO11 General purpose digital input output pin P4 6 C1 B1 11 B IN l O GPIO2 6 General purpose digital input output pin PU lo CTOUT 4 SCTimer PWM output 4 Match output 3 of timer 3 O LCD_ENAB LCDM STN AC bias drive or TFT data enable input
81. CLK M4 LCD 0 85 1 72 ETHERNET CLK M4 ETHERNET 1 05 2 09 UARTO CLK M4 UARTO 0 3 0 38 CLK APBO UARTO UART1 CLK_M4_UART1 0 27 0 48 CLK APBO UART1 UART2 CLK M4 UART2 0 27 0 47 CLK APB2 UART2 UART3 CLK_M4_USARTS 0 29 0 49 CLK_APB2_UART3 TIMERO CLK_M4_TIMERO 0 07 0 14 TIMER1 CLK M4 TIMER1 0 07 0 14 TIMER2 CLK M4 TIMER2 0 07 0 15 TIMER3 CLK_M4_TIMER3 0 06 0 11 SDIO CLK_M4_SDIO 0 79 1 37 CLK_SDIO SCTimer PWM CLK_M4_SCT 0 52 1 05 SSPO CLK M4 SSPO 0 12 0 21 CLK APBO SSPO SSP1 CLK M4 SSP1 0 15 0 28 CLK APB2 SSP1 DMA CLK M4 DMA 1 88 3 71 WWDT CLK M4 WWDT 0 05 0 08 QEI CLK M4 QEI 0 33 0 68 USBO CLK M4 USBO 1 46 3 32 CLK_USBO USB1 CLK M4 USB1 2 83 5 03 CLK USB1 RITIMER CLK M4 RITIMER 0 04 0 08 EMC CLK M4 EMC 3 6 6 97 CLK M4 EMC DIV SCU CLK M4 SCU 0 09 0 23 CREG CLK M4 CREG 0 37 0 72 SGPIO CLK PERIPH SGPIO 0 1 0 17 SPI CLK SPI 0 07 0 11 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 100 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 10 3 BOD and band gap static characteristics Table 12 BOD static characteristics Tamb 25 C simulated values for nominal processing Symbol Parameter Conditions Min Typ Max Unit Vin threshold vo
82. CTimer PWM output 8 Match output 0 of timer 2 R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 47 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 TFBGA100 LQFP144 Type J LBGA256 Y TFBGA180 AR PD 16 R Function reserved Dv Nj Uz c R Function reserved O EMC A16 External memory address line 16 R Function reserved l O GPIO6 30 General purpose digital input output pin O SD_VOLT2 SD MMC bus voltage select output 2 O CTOUT 12 SCTimer PWM output 12 Match output 3 of timer 3 R Function reserved PE 0 P14 N12 l BN R Function reserved PU R Function reserved R Function reserved O EMC A18 External memory address line 18 lO GPIO7 0 General purpose digital input output pin O CAN1 TD CANT transmitter output R Function reserved R Function reserved PE 1 N14 M12 l 21 N l R Function reserved PU R Func
83. EDEC JEITA PROJECTION ISSUE DATE 08 07 09 SOT570 3 cto MOIS Fig 52 Package outline of the TFBGA180 package LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 142 of 158 NXP Semiconductors LPC4350 30 20 10 TFBGA100 plastic thin fine pitch ball grid array package 100 balls body 9 x 9 x 0 7 mm 32 bit ARM Cortex M4 MO microcontroller SOT926 1 A D T B A Pd ball A1 index area E detail X Y 1 Ov CI A B gt b n e 1 2 e 61 Sw K lOOOO i J OOOO H OOOO G OOOO F OOOO 4 E OOOO D OOOO c OOOO B lOO OO A OOOO 3 ball A1 index area X 0 2 5 mm scale DIMENSIONS mm are the original dimensions A UNIT max Ay A2 b D E e e1 e2 v w y y 0 4 0 8 0 5 9 1 9 1 mm 1 2 03 065 04 39 8 9 0 8 7 2 7 2 0 15 0 05 0 08 0 1 OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION Sane DATE 05 42 09 SOT926 1 de tx Q 05 12 22 Fig 53 Package outline of the TFBGA100 package LPC4350_30_20_10
84. EMC_WE tam gt tBLSHDNV 4 CSHEOR t SI gt CSLDV t tcs_son h D WEHDNV EMC Dn SOR EOR EOW 002aag700 Fig 35 External static memory read write access PB 1 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 122 of 158 NXP Semiconductors LPC4350 30 20 10 Table 28 Dynamic characteristics Dynamic external memory interface 32 bit ARM Cortex M4 M0 microcontroller Simulated data over temperature and process range C 10 pF for EMC_DYCSn EMC RAS EMC CAS EMC WE EMC An C 9 pF for EMC Dn C 5 pF for EMC DQMOUTn EMC CLKn EMC CKEOUTn Tamb 40 C to 85 C 2 2 V lt VppigEay ava lt 3 6 V Vppio 23 3 V 10 RD 1 see LPC43xx User manual EMC CLKn delays CLKO DELAY CLK1_DELAY CLK2 DELAY CLK3_DELAY 0 Symbol Parameter Min Typ Max Unit Toy cl clock cycle time 8 4 2 ns Common to read and write cycles ta pYcsv DYCS delay time 3 1 0 5 x Toa 5 1 0 5 x Tog NS th DYcs DYCS hold time 0 3 0 5 x Tog 0 9 0 5 x Toy ns ta RASV row address strobe valid delay time 3 1 0 5 x Te 4 9 0 5 x Tog NS th RAS row address strobe hold time 0 5 0 5 x Toy 11 1 0 5 x Toye ns ta casv col
85. GA256 package LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 141 of 158 NXP Semiconductors LPC4350 30 20 10 TFBGA180 thin fine pitch ball grid array package 180 balls 32 bit ARM Cortex M4 M0 microcontroller SOT570 3 ii D B JA A ball A1 index area DA E A 2 FA t detail X Y EI 4 gt MOvMICIAB j e gt 1 2e b gt lt SISWO C P oooo0o0oo0o000 O4 N OOOOOOOOOO00 M OOOOOOOOOOO i L OOOOOOOOOO00 e K OOOOOOOO0OOO J OOOOO OOo H OOOOO oo 1 BE a OOOOO OOo 7 F OOOOO OO T2 El ooooooo0oo0000 eg D O0000000000 Cc OOOOOOOOcOOO B OOOOOOOOOOOO A OOOOOOOOOOOOO r ball A1 1 3 5 7 9 _ 1 index area 2 754 26 7 807019 5 10mm scale DIMENSIONS mm are the original dimensions UNIT A A4 A2 b D E e e2 v w y y max 1 20 0 40 0 80 0 50 12 1 12 1 mm nom 1 06 0 35 0 71 0 45 12 0 12 0 0 8 10 4 10 4 0 15 0 05 0 12 0 1 min 0 95 0 30 0 65 0 40 11 9 11 9 OUTLINE REFERENCES EUROPEAN VERSION IEC J
86. ISP means programming or reprogramming the on chip SRAM memory using the boot loader software and the USARTO serial port ISP can be performed when the part resides in the end user board ISP loads data into on chip SRAM and execute code from on chip SRAM Boot ROM The internal ROM memory is used to store the boot code of the LPC4350 30 20 10 After a reset the ARM processor will start its code execution from this memory The boot ROM memory includes the following features The ROM memory size is 64 kB Supports booting from UART interfaces and external static memory such as NOR flash quad SPI flash and USBO and USB1 Includes API for OTP programming Includes a flexible USB device stack that supports Human Interface Device HID Mass Storage Class MSC and Device Firmware Upgrade DFU drivers Several boot modes are available depending on the values of the OTP bits BOOT_SRC If the OTP memory is not programmed or the BOOT_SRC bits are all zero the boot mode is determined by the states of the boot pins P2_9 P2_8 P1_2 and P1_1 Table 4 Boot mode when OTP BOOT SRC bits are programmed Boot mode BOOT SRC BOOT SRC BOOT_SRC BOOT_SRC Description bit 3 bit 2 bit 1 bit 0 Pin state 0 0 0 0 Boot source is defined by the reset state of P1 1 P1 2 P2 8 and P2 9 pins See Table 5 USARTO 0 0 0 1 Boot from device connected to USARTO using pins P2 Oand P2 1 SPIFI 0 0 1 0 Boot from Quad SPI flash connected to
87. KIN and Table 19 Dynamic characteristic GPCLKIN Updated SSP slave and SSP master values in Table 24 Dynamic characteristics SSP pins in SPI mode Updated footnote 2 to Tey cik 12 x Tey PCLk removed tyo data output valid time in SPI mode minimum value of 3 x 1 PCLK from SSP slave mode added units to ty delay time for SSP slave and master mode LPC4350_ 30 20 10 v 4 3 20150430 Product data sheet LPC4350_ 30 20 10 v 4 2 Modifications Updated Section 1 General description Table note 2 corrected in Table 10 Updated USART dynamic characteristics table See Table 23 Updated SD MMC dynamic characteristics table See Table 33 Updated SPIFI dynamic characteristics table See Table 35 Added SSP slave timing data See Table 24 e Updated USB dynamic characteristics table USBO and USB1 pins full speed t Min 4 ns Max 20 ns t Min 4 ns Max 20 ns terry Min 90 96 Max 111 11 96 See Table 30 Added band gap characteristics table See Table 13 Added motor control PWM instead of PWM to Table 2 Added remark to Table 30 LPC4350 30 20 10 v 4 2 20140818 Product data sheet 201408013F01 LPC4350 30 20 10 v4 1 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 151 of 158
88. LD 4 LCD VD11 P4 9 LD 3 P4 9 LD 3 P4 9 LD 3 LCD_VD10 P4_10 LD 2 P4_10 LD 2 P4 10 LD 2 LCD VD9 P4 8 LD 1 P4 8 LD 1 P4 8 LD 1 LCD VD8 P7 5 LD 0 P7 5 LD 0 P7_5 LD 0 LCD_VD7 UD 7 P8_4 UD 7 LCD_VD6 P8 5 UD 6 P8 5 UD 6 LCD VD5 P8 6 UD 5 P8 6 UD 5 LCD VD4 P8 7 UD 4 P8_7 UD 4 LCD_VD3 P4 2 UD 3 P4 2 UD 3 P4 2 UD S3 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 133 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 39 LCD panel connections for STN dual panel mode continued External pin 4 bit mono STN dual panel 8 bit mono STN dual panel Color STN dual panel LPC43xx pin LCD function LPCA3xx pin LCD function LPCA3xx pin LCD function used used used LCD_VD2 P4 3 UD 2 P4_3 UD 2 P4 3 UD 2 LCD_VD1 P4 4 UD 1 P4 4 UD 1 P4 4 UD 1 LCD_VDO P4 1 UD 0 P4_1 UD 0 P4_1 UD O LCD LP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP LCD ENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB LCDM LCDM LCDM LCDM LCD FP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP LCD DCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK LCD LE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE LCD PWR P7 7 LCDPWR P7 7 LCDPWR P7 7 LCDPWR GP CLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN Table 40
89. M O O EMC_CLKO SDRAM clock 0 PU O CLKOUTC Clock output pin R Function reserved R Function reserved lO SD CLK SD MMC card clock O EMC CLKO01 SDRAM clock 0 and clock 1 combined lO SSP1 SCK Serial clock for SSP1 ENET TX CLK ENET REF CLK Ethernet Transmit Clock MII interface or Ethernet Reference Clock RMII interface CLK1 T10 l 41 O O EMC CLK1 SDRAM clock 1 PU CLKOUTC Clock output pin R Function reserved R Function reserved R Function reserved O CGU OUTO CGU spare clock output 0 R Function reserved O 281 TX MCLK I281 transmit master clock CLK2 D14 P10 K6 99 4 O O EMC CLKS3 SDRAM clock 3 PU CLKOUT Clock output pin R Function reserved R Function reserved lO SD CLK SD MMC card clock O EMC CLK23 SDRAM clock 2 and clock 3 combined O 2S0 TX MCLK 12S transmit master clock VO I2S1 RX SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I S bus specification CLK3 P12 l 4 O O EMC_CLK2 SDRAM clock 2 PU O CLKOUTC Clock output pin R Function reserved R Function reserved R Function reserved O CGU OUT1 CGU spare clock output 1 R Function reserved lO 12S1_RX_SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the I S bus specificat
90. M output 6 Match output 2 of timer 1 l O EMC A7 External memory address line 7 l O SGPIO9 General purpose digital input output pin R Function reserved l O SSPO MOSI Master Out Slave in for SSPO R Function reserved R Function reserved P13 P5 M2 Ji 44 BIN lO GPIOO 10 General purpose digital input output pin PU lo CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 lO SGPIO10 General purpose digital input output pin O EMC OE LOW active Output Enable signal O USBO IND1 USBO port indicator LED control output 1 O SSP1 MISO Master In Slave Out for SSP1 R Function reserved O SD RST SD MNC reset signal for MMC4 4 card P14 TS P2 J2 47 B IN l O GPIOO 11 General purpose digital input output pin PU lo CTOUT 9 SCTimer PWM output 9 Match output 3 of timer 3 lO SGPIO11 General purpose digital input output pin O EMC_BLSO LOW active Byte Lane select signal 0 O USBO INDO USBO port indicator LED control output 0 O SSP1 MOSI Master Out Slave in for SSP1 R Function reserved O SD_VOLT1 SD MMC bus voltage select output 1 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 10 of 158 NXP Semiconductors LPC4350 30 20 10 Table 3 Pin description continued 32 b
91. M13 G7 81 2 IN l O SGPIO5 General purpose digital input output pin PU Ug RXD Receiver input for USARTO VO EMC A12 External memory address line 12 USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition l O GPIO5 1 General purpose digital input output pin R Function reserved T8 CAP1 Capture input 1 of timer 3 R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 15 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description o le 8 X 4 x x o o S E o g a m uL Om S E E qm erie P2 2 M15 L13 F5 84 I N I O SGPIO6 General purpose digital input output pin PU yo UO UCLK Serial clock input output for USARTO in synchronous mode I O EMC A11 External memory address line 11 O USBO IND1 USBO port indicator LED control output 1 lO GPIO5 2 General purpose digital input output pin CTIN_6 SCTimer PWM in
92. N lO USB1 ULPI D5 ULPI link bidirectional data line 5 PU R Function reserved O U1_RTS Request to Send output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 O ENET_TXD3 Ethernet transmit data 3 MII interface lO GPIO6 2 General purpose digital input output pin R Function reserved R Function reserved O SD_VOLT1 SD MMC bus voltage select output 1 Al ADC1 0 DAC output ADC1 and ADCO input channel 0 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PC 4 FA l BN R Function reserved PU l O USB1 ULPI D4 ULPI link bidirectional data line 4 R Function reserved ENET TX EN Ethernet transmit enable RMII MII interface l O GPIO6 3 General purpose digital input output pin R Function reserved T3_CAP1 Capture input 1 of timer 3 O SD DATO SD MMC data bus line 0 PC_5 G4 l BN R Function reserved PU Oo USB1 ULPI D3 ULP link bidirectional data line 3 R Function reserved O ENET TX ER Ethernet Transmit Error MII interface l O GPIO6 4 General purpose digital input output pin R Function reserved T3_CAP2 Capture input 2 of timer 3 O SD DAT1 SD MMC data bus line 1 PC 6 H6 z BN R Function reserve
93. NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 44 Revision history continued Document ID Release date Data sheet status Change notice Supersedes Modifications Parameter C corrected for high drive pins changed from 2 pF to 5 2 pF See Table 10 Table 19 Dynamic characteristic I O pins 1 added e IRC accuracy changed from 1 to 1 5 over the full temperature range See Table 17 Dynamic characteristic IRC oscillator Description of internal pull up resistor configuration added for RESET WAKEUPn and ALARM pins See Table 3 Description of DEBUG pin updated Input range for PLL1 corrected 1 MHz to 25 MHz See Section 7 22 7 System PLL1 Section 13 7 Suggested USB interface solutions added SSP master mode timing diagram updated with SSEL timing parameters See Figure 31 SSP master mode timing SPI mode e Parameters tjeag tlag and ty added in Table 23 Dynamic characteristics SSP pins in SPI mode Reset state of the RTC alarm pin RTC ALARM added See Table 3 SRAM location for parts LPC4320 corrected in Figure 7 EEE standard 802 3 compliance added to Section 11 16 Covers Ethernet dynamic characteristics of ENET MDIO and ENET_MDC signals Signal polarity of EMC CKEOUT and EMC_DQMOUT corrected Both signals are active HIGH e Parameter tcsi wg with condition PB 1 corrected WAITWEN 1 x Toyick added See Table 26
94. P Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 157 of 158 NXP Semiconductors LPC4350 30 20 10 7 22 6 7 22 7 7 22 8 7 22 9 7 22 10 7 23 8 9 10 10 1 10 2 10 3 10 4 11 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 10 11 11 11 12 11 13 11 14 11 15 11 16 11 17 11 18 11 19 11 20 12 13 13 1 13 2 13 3 13 4 13 5 13 6 13 7 14 15 16 17 PLLOAUDIO for audio 82 System PLET i crcr rscs i99 Res 82 Reset Generation Unit RGU 82 Power control 00 200000ee 82 Power Management Controller PMC 83 Serial Wire Debug JTAG llus 84 Limiting values leere 86 Thermal characteristics 87 Static characteristics L 88 Power consumption 04 95 Peripheral power consumption 99 BOD and band gap static characteristics 101 Electrical pin characteristics 102 Dynamic characteristics 106 Wake up times 0000 e ee 106 External clock for oscillator in slave mode 106 Crystal oscillator 00 107 IRC oscillator 0 0 0 0 eee 107 RTC oscillator 0 0 0 0 0 0 0 cece eee 107 GPGLEKIN ries eed Ge dee SEES 108 WO PINS itia eaaa oH bars YR S 108 CDUS ir b eee te eee at anes munis 109 I2S bus interface llle llus 110 USART interface
95. PWM input 3 Capture input 1 of timer 1 R Function reserved O LCD VD17 LCD data O LCD VD5 LCD data R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 31 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol TFBGA100 LQFP144 Type 1 Q LBGA256 Q TFBGA180 Z Reset state O P7_4 GPIO3 12 General purpose digital input output pin CTOUT_13 SCTimer PWM output 13 Match output 3 of timer 3 E N si UZ Rx O R Function reserved LCD_VD16 LCD data LCD_VD4 LCD data TRACEDATA 0 Trace data bit 0 R Function reserved OoOo R Function reserved Al ADCO 4 ADCO and ADC1 input channel 4 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P7_5 A7 A7 l 133 BI IN l O GPIO3 13 General purpose digital input output pin PU lo CTOUT 12 SCTimer PWM output 12 Match output 3 of timer 3 R Function reserved LCD VD8 LCD data LCD VD23 LCD data
96. Rev 4 5 26 November 2015 147 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Footprint information for reflow soldering of TFBGA100 package SOT926 1 Generic footprint pattern Refer to the package outline drawing for actual layout LO RSE RA S At SOSS FA solder land P S Y solder paste deposit SKO ZEEE JERS OA RNS Oe eet ES KKK S 222S 5 lS SS e ON ood 4 solder land plus solder paste Roe occupied area solder resist detail X DIMENSIONS in mm P SL SP SR Hx Hy 0 80 0 330 0 400 0 480 9 400 9 400 sot926 1 fr Fig 58 Reflow soldering of the TFBGA100 package LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 148 of 158 NXP Semiconductors LPC4350 30 20 10 16 Abbreviations 32 bit ARM Cortex M4 M0 microcontroller LPC4350_30_20_10 Table 43 Abbreviations Acronym Description ADC Analog to Digital Converter AHB Advanced High performance Bus APB Advanced Peripheral Bus API Application Programming Interface BOD BrownOut Detection CAN Controller Area Network CMAC Cipher based Message Aut
97. Rev 4 5 26 November 2015 6 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 6 Pinning information 6 1 Pinning LPC4350 30FET256 LPC4350 30FET180 ball A1 ball A1 indxarea 2 4 6 8 10 12 14 16 index area 2 4 6 8 10 12 14 1 3 5 7 9 11 13 15 O0O0O0OOOOOOOOOOO000 OOO OOOOOOOO OOOOOOOOOOOOOO000 OOo OOOOOOOOQ OOOOOOOOOOOOOO00 O0000000000000000 RUE Erde e OOOOOOOOOOO0O0O0000 OOOOOOOOOOO0O00000 OOO OO0OOOOOO OOOOOOOOOOOO00000 OOO OOOOO OO0OOOOOOOOOO0O0000 Oooo OOOOO OOOOOOOOOOOOOO000 ooo OOOOO OOOOOOOOOOOOOOO00 OOO OOOOOQ OOOOOOOOOOO0OO0000 ooo ooooo0oo0o0000000000 O00 OOOOOOOOOOOO0O0000 0000000000000000 ooo 000000000 OOOOOOOOOOOOO000 O00 OO0O0O0O00000 OOOOOOOOOOO0O0O0000 OOO OOOOOOOOO 002aaf813 002aag374 Transparent top view Transparent top view Fig 2 Pin configuration LBGA256 package Fig 3 Pin configuration TFBGA180 package Pallant LPC4330 20 10FET100 index area 12 3 4 b 6 7 8 9 10 QOOOOOOCUQOQO QOODUOOOOO Ud OOOOOOOOO0 LPC4330 20 10FBD144 XReronrmooeoaw sr 002aag375 Transparent top view 002aag377 Fig 4 Pin configuration TFBGA100 package Fig 5 Pin configuration LQFP144 package LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 7 of 158 NXP Semiconductors LPC4350 30 20 1 0
98. SPI mode CPOL 1 Toy clk 2 2 ns CPHA 0 SPI mode CPOL 1 0 5 x Toyick 2 2 ns CPHA 1 synchronous serial 0 5 x Toyick 2 2 3 ns frame mode microwire frame format Toy clk 2 2 ns LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 114 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 24 Dynamic characteristics SSP pins in SPI mode Tamb 40 C to 85 C 2 2 V lt Vpp REG 3V3 lt 3 6 V 2 7 V lt Vpp io lt 3 6 V C 20 pF Sampled at 10 and 90 of the signal level EHS 1 for all pins Simulated values Symbol Parameter Conditions Min Typ Max Unit tiag lag time continuous transfer mode 0 5Tey cik 0 2 ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 Tey cik 0 2 ns CPHA 1 SPI mode CPOL 1 0 5 x Took 0 2 z ns CPHA 0 SPI mode CPOL 1 Toy clk 0 2 ns CPHA 1 synchronous serial Tey cik 0 2 ns frame mode microwire frame format 0 5 x Toy clk ns ta delay time continuous transfer mode 0 5 x Toy ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 n a ns CPHA 1 SPI mode CPOL 1 0 5 x Tey clk ns CPHA 0 SPI mode CPOL 1 n a ns CPHA 1 synchronous serial Tey clk ns frame m
99. SSPO MISO Master In Slave Out for SSPO LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 35 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description o 2 2 g E 3 3 g i e m a le D Hi a uL uL Om S _ pa z e P9_2 N8 M6 Bl IN l O GPIO4 14 General purpose digital input output pin PU MCOB2C Motor control PWM channel 2 output B R Function reserved R Function reserved l O I2S0 TX SDA I28 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification ENET RXD3 Ethernet receive data 3 MII interface l O SGPIO2 General purpose digital input output pin l O SSPO MOSI Master Out Slave in for SSPO P9 3 M6 P5 Bl IN l O GPIO4 15 General purpose digital input output pin PU O MCOAO0 Motor control PWM channel 0 output A O USB1 IND1 USB1 Port indicator LED control output 1 R Function reserved R Function reserved ENET RXD2 Ethernet receive data 2 MII inte
100. T 0 5 3 6 V Vorog pf polyfuse programming on pin VPP 0 5 3 6 V voltage Vi input voltage only valid when Vpp o 2 2 2 V 2 5 V tolerant I O pins 0 5 5 5 V ADC DAC pins and digital I O 0 5 VpDA 3V3 V pins configured for an analog function USBO pins USBO DP 0 3 5 25 V USBO DM USBO VBUS USBO pins USBO ID 0 3 3 6 V USBO RREF USB1 pins USB1 DP and 0 3 5 25 V USB1 DM Ipp supply current per supply pin 3 100 mA Iss ground current per ground pin 3 100 mA llatch I O latch up current 0 5Vpp o Vi 1 5Vppio 100 mA Tj 125 C Tstg storage temperature 4 65 150 C Ptot pack total power dissipation based on package heat transfer 1 5 W per package not device power consumption Vesp electrostatic discharge human body model all pins 5 2000 2000 V voltage 1 The following applies to the limiting values a This product includes circuitry designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted 2 Including voltage on outputs in 3 state mode 3 The peak current is limited to 25 times the corresponding maximum current 4 Dependent on package type 5 Human body model equiva
101. T 9 SCTimer PWM output 9 Match output 3 of timer 3 R Function reserved VO EMC A23 External memory address line 23 l O GPIO5 19 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PB 0 B15 D1i4 2 N R Function reserved PU 6 CTOUT 10 SCTimer PWM output 10 Match output 3 of timer 3 O LCD VD23 LCD data R Function reserved l O GPIOB5 20 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PB 1 A14 A13 RI N l R Function reserved PU JUSBi ULPI DIR ULPI link DIR signal Controls the ULP data line direction O LCD VD22 LCD data R Function reserved lO GPIO5 21 General purpose digital input output pin O CTOUT 6 SCTimer PWM output 6 Match output 2 of timer 1 R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 38 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions ar
102. T1 includes a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz Features Maximum UART data bit rate of 8 MBit s 16 B Receive and Transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Auto baud capabilities and FIFO control mechanism that enables software flow control implementation Equipped with standard modem interface signals This module also provides full support for hardware flow control Support for RS 485 9 bit EIA 485 mode UART1 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 74 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 18 2 7 18 2 1 7 18 3 7 18 3 1 7 18 4 LPC4350 30 20 10 32 bit ARM Cortex M4 MO microcontroller DMA support USARTO 2 3 The LPC4350 30 20 10 contain three USARTs In addition to standard transmit and receive data lines the USARTs support a synchronous mode The USARTS include a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz Features Maximum UART data bit rate of 8 MBit s
103. T100 264kB no yes yes yes no 4 no no 49 TFBGA100 LPC4330FBD144 264kB no yes yes yes no 8 yes no 83 LQFP144 LPC4320FET100 200kB no no yes no 4 no no 49 TFBGA100 LPC4320FBD144 200kB no no yes no 8 yes no 83 LQFP144 LPC4310FET100 168kB no no no no 4 no no 49 TFBGA100 LPC4310FBD144 168kB no no no no 8 yes no 83 LQFP144 LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 5 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 5 Block diagram LPC4350 30 20 10 TEST DEBUG INTERFACE INTERFACE ARM CORTEX M4 d HIGH SPEED USBO 1 HOST DEVICE OTG HIGH SPEED usB1 1 1 SD LCD MMC HOST DEVICE iG O masters slaves snq epoo snq epoo q snq uiejs s AHB MULTILAYER MATRIX U U BRIDGE U ALARM TIMER BACKUP REGISTERS POWER MODE CONTROL CONFIGURATION REGISTERS EMC I I I I I I I I I EVENT ROUTER I HS GPIO SSP1 OTP MEMORY I SPIFI QEI 1 I RTC RTC OSC I I I I 1 12 MHz IRC RTC POWER DOMAIN connected to GPDMA 002aaf772 1 Not available on all parts see Table 2 Fig 1 LPC4350 30 20 10 Block diagram LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet
104. TEE 75 74 Interprocessor communication 61 7 18 4 SSP serial I O controller 75 75 AHB multilayer matrix sls 62 7 18 4 1 Faaturas rm 76 7 6 Nested Vectored Interrupt Controller NVIC 62 7 18 5 l C bus interface 000 76 7 64 Features ch cee ac kell cooks 63 7 18 5 4 Features 0 000000 ee 76 7 6 2 Interrupt sources lille elles 63 7 18 6 lS interface 2 6 eee essere eee ees 76 77 System Tick timer SysTick 63 7 18 6 1 Features 000000 77 7 8 Event router 2 0 0000000e 63 7 18 7 C CAN n n n 77 7 9 Global Input Multiplexer Array GIMA TAA 63 7 18 7 1 Features T 77 7 9 1 ur o A 64 719 Counter timers and motor control 78 7 10 On chip static RAM aoaaa aaao 64 7 19 1 General purpose 32 bit timers external event 711 In System Programming ISP 64 counters eoi a a nee eb bee bd 78 712 Boot ROM LL LLL 64 7 19 1 1 Features aana aanne 78 7 13 Memory mapping sisse 65 7 19 2 Motor control PWM 78 744 One Time Programmable OTP memory 68 7 19 3 Quadrature Encoder Interface QEI 78 7 15 General Purpose Vo GPIO M ee ee 68 7 19 3 1 Features iis i r itai aes dara t peraan OR 78 7 45 1 Features uoua 8 su Repetitive Interrupt RI UMer s zsir tie 7 16 Configurable digital peripherals 68 7 19 4 1 Features TI DEXDEEEEELUU 79 7 16 1 State Configurable
105. TRACEDATA 1 Trace data bit 1 R Function reserved OoOo R Function reserved Al ADCO 3 ADCO and ADC1 input channel 3 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC P7 6 C7 F5 134 BN l O GPIO3 14 General purpose digital input output pin PU lo CTOUT 11 SCTimer PWM output 1 Match output 3 of timer 2 R Function reserved O LCD LP Line synchronization pulse STN Horizontal synchronization pulse TFT R Function reserved O TRACEDATA 2 Trace data bit 2 R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 32 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description Pe ea IS i X 4 x x o o ia mg o g a m m So Oo Ss m m elie P7_7 B6 D5 140 S IN I O GPIO3 15 General purpose digital input output pin PU lo CTOUT 8 SCTimer PWM output 8 Match output 0 of timer 2 R Function reserved O LCD PWR
106. V 2 7V 8S Vpp io x 8 6 V C 20 pF Sampled at 90 and 10 of the signal level EHS 1 for all pins Simulated values Symbol Parameter Min Max Unit Tey clk clock cycle time 9 6 s ns tos data set up time 2 8 ns ipH data hold time 0 ns twa data output valid time 2 6 ns tha data output hold time 0 8 ns Toy elk SPIFI SCK SPIFI data out DATA VALID SPIFI data in DATA VALID DATA VALID 002aah409 Fig 40 SPIFI timing Mode 0 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 129 of 158 NXP Semiconductors LPC4350 30 20 10 12 ADC DAC electrical characteristics 32 bit ARM Cortex M4 M0 microcontroller Table 36 ADC characteristics VppA ava Over specified ranges Tamb 0 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Via analog input voltage 0 VpDA 3V3 V Cia analog input 2 pF capacitance Ep differential linearity error 2 7 V lt Vppa ava 3 6 V m2 0 8 LSB 2 2 V VppA ava lt 2 7 V 1 0 LSB Ei adj integral non linearity 2 7 V Vppa ava 3 6 V 3 0 8 LSB 2 2 V VppA ava lt 2 7 V 1 5 LSB Eo offset error 2 7 V Vppa ava 3
107. XP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol TFBGA100 Type 1 T LBGA256 S TFBGA180 Z Reset state n LQFP144 2 P9 6 GPIO4 11 General purpose digital input output pin MCOB1 Motor control PWM channel 1 output B USB1 PWR FAULT USB1 Port power fault signal indicating over current condition this signal monitors over current on the USB1 bus external circuitry required to detect over current condition TZ e a6 R Function reserved R Function reserved ENET COL Ethernet Collision detect MII interface lO SGPIO8 General purpose digital input output pin UO RXD Receiver input for USARTO PA 0 L12 L10 RI IN l R Function reserved PU R Function reserved R Function reserved R Function reserved R Function reserved 12S1_RX_MCLK 12S1 receive master clock CGU_OUT1 CGU spare clock output 1 R Function reserved PA 1 J14 H12 Bl IN l O GPIO4 8 General purpose digital input output pin OoOO PU QEI_IDX Quadrature Encoder Interface INDEX input R Function reserved O U2 TXD
108. _5 SCTimer PWM input 5 Capture input 2 of timer 2 lO EMC D21 External memory data line 21 R Function reserved lO GPIO6 21 General purpose digital input output pin R Function reserved R Function reserved lO SGPIO11 General purpose digital input output pin LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 45 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 TFBGA180 TFBGA100 LQFP144 Type d LBGA256 R Function reserved CTIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 lO EMC D22 External memory data line 22 R Function reserved l O GPIO6 22 General purpose digital input output pin PD 8 Ni UZ c R Function reserved R Function reserved l O SGPIO12 General purpose digital input output pin PD 9 TM BN l R Function reserved PU o CTOUT 13 SCTimer PWM output 13 Match output 3 of timer 3 lO EMC D23 External memory data line 23 R Function reserved lO GPIO6 23 General purpose digital input output pin
109. al purpose digital input output pin CTIN_7 SCTimer PWM input 7 T3_CAP3 Capture input 3 of timer 3 R Function reserved P2 7 H14 G12 C10 96 2 N JO GPIOO 7 General purpose digital input output pin If this pin PU is pulled LOW at reset the part enters ISP mode using USARTO O CTOUT 1 SCTimer PWM output 1 Match output 3 of timer 3 lO U3 UCLK Serial clock input output for USARTS in synchronous mode lO EMC A9 External memory address line 9 R Function reserved R Function reserved O T3 MATS Match output 3 of timer 3 R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 17 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Q 2 F 3 Description Te T 7 lt o0 o amp ee E g B B 5 j T E d ec c P2 8 J16 H14 C6 98 2 IN l O SGPIO15 General purpose digital input output pin Boot pin PU see Table 5 O CTOUT 0 SCTimer PWM output 0 Match output 0 of timer 0 lO US3 DIR RS 485 EIA 485 output enab
110. amp TFBGA180 k PD_12 R Function reserved D UZ c R Function reserved EMC CS2 LOW active Chip Select 2 signal R Function reserved l O GPIO6 26 General purpose digital input output pin R Function reserved O CTOUT 10 SCTimer PWM output 10 Match output 3 of timer 3 O R Function reserved PD_13 Ti4 BN R Function reserved PU QCTIN 0 SCTimer PWM input 0 Capture input 0 of timer 0 1 2 3 O EMC BLS2 LOW active Byte Lane select signal 2 R Function reserved lO GPIO6 27 General purpose digital input output pin R Function reserved O CTOUT 13 SCTimer PWM output 13 Match output 3 of timer 3 R Function reserved PD 14 R13 L11 BN l R Function reserved PU R Function reserved O EMC DYCS 2 SDRAM chip select 2 R Function reserved lO GPIO6 28 General purpose digital input output pin R Function reserved O CTOUT 11 SCTimer PWM output 11 Match output 3 of timer 2 R Function reserved PD 15 T15 P13 2 N R Function reserved PU R Function reserved VO EMC A17 External memory address line 17 R Function reserved l O GPIO6 29 General purpose digital input output pin SD WP SD MMC card write protect input O CTOUT 8 S
111. ansmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification l O SD DAT6 SD MMC data bus line 6 PC 14 Ni BN l R Function reserved PU il R Function reserved U1 RXD Receiver input for UART 1 R Function reserved l O GPIO6 13 General purpose digital input output pin lO SGPIO13 General purpose digital input output pin O ENET TX ER Ethernet Transmit Error MII interface O SD DAT7 SD MMC data bus line 7 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 43 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Q 2 F 3 Description Te T 7 3 o0 o amp nee g B B 5 j E d ec E PD 0 N2 R N l R Function reserved PU lo CTOUT_15 SCTimer PWM output 15 Match output 3 of timer 3 O EMC DQMOUT Data mask 2 used with SDRAM and static devices R Function reserved l O GPIO6 14 General purpose digital input output pin R Function
112. are byte and half word addressable Entire port value can be written in one instruction Bit level set and clear registers allow a single instruction set or clear of any number of bits in one port Direction control of individual bits Up to eight GPIO pins can be selected from all GPIO pins to create an edge or level sensitive GPIO interrupt request GPIO interrupts Two GPIO group interrupts can be triggered by any pin or pins in each port GPIO groupO and group1 interrupts Configurable digital peripherals State Configurable Timer SCTimer PWM subsystem The SCTimer PWM allows a wide variety of timing counting output modulation and input capture operations The inputs and outputs of the SCTimer PWM are shared with the capture and match inputs outputs of the 32 bit general purpose counter timers The SCTimer PWM can be configured as two 16 bit counters or a unified 32 bit counter In the two counter case in addition to the counter value the following operational elements are independent for each half State variable Limit halt stop and start conditions Values of Match Capture registers plus reload or capture control values All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 68 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller In t
113. ation provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 134 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 40 LCD panel connections for TFT panels continued External TFT 12 bit 4 4 4 TFT 16 bit 5 6 5 mode TFT 16 bit 1 5 5 5 mode TFT 24 bit pin mode LPC43xx LCD LPC43xx LCD LPC43xxpin LCD LPC43xx LCD pin used function pin used function used function pin used function LCD VDO l g P4 1 REDO LCD LP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP P7 6 LCDLP LCD ENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB P4 6 LCDENAB LCDM LCDM LCDM LCDM LCDM LCD_FP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP P4 5 LCDFP LCD DCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK P4 7 LCDDCLK LCD LE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE P7 0 LCDLE LCD PWR P7 7 LCDPWR P77 LCDPWR P7 7 LCDPWR P77 LCDPWR GP CLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN PF 4 LCDCLKIN 13 2 Crystal oscillator LPC4350_30_20_10 The crystal oscillator is controlled by the XTAL_OSC_CTRL register in the CGU see LPC43xx user manual The crystal oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the PLL The oscillator can operate in one of two modes slave mode and os
114. bled Fig 13 Typical supply current versus frequency in Active mode 002aah153 10 IDD REG 3V3 mA 8 HHHH 60 temperature C Conditions Vpp REq 3v3 3 3 V MO core in reset internal pull up resistors disabled PLL1 enabled IRC enabled all peripherals disabled all peripheral clocks disabled core clock CCLK 12 MHz Fig 14 Typical supply current versus temperature in Sleep mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 96 of 158 NXP Semiconductors LPC4350 30 20 1 0 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller 002aah154 300 IDD REG 3V3 uA 240 180 120 60 40 15 10 35 60 85 temperature C Conditions Vpp REG 3V3 3 3 V Veat floating Vpp I0 3 3 V Fig 15 Typical supply current versus temperature in Deep sleep mode 002aah155 50 IDD REG 3V3 pA 40 30 20 10 40 15 10 35 60 85 temperature C Conditions VDD REG 3V3 3 3 V Vgar floating VpD 0 9 3 V Fig 16 Typical supply current versus temperature in Power down mode All information provided in this docum
115. ce does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 8 tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 109 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller 9 A Fast mode I C bus device can be used in a Standard mode I C bus system but the requirement tgy par 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tymax tsu pAr 1000 250 1250 ns according to the Standard mode I C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time SDA SCL S 1 fscL tSU DAT 70 96 tHD DAT Fig 27 I C bus pins clock timing 002aa 425 11 9 Table 22 I2S bus interface Dynamic characteristics I S bus interface pins Tamp 40 C to 85 C 2 2 V lt Vpp REG 3V3 S3 6V 2 7VS VppvI0 8 6 V C 20 pF Conditions and data refer to I
116. cillation mode n slave mode couple the input clock signal with a capacitor of 100 pF Cc in Figure 43 with an amplitude of at least 200 mV RMS The XTAL2 pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 44 and in Table 41 and Table 42 Since the feedback resistance is integrated on chip only a crystal and the capacitances CX1 and CX2 need to be connected externally in case of fundamental mode oscillation L CL and RS represent the fundamental frequency The capacitance Cp in Figure 44 represents the parallel package capacitance and must not be larger than 7 pF Parameters FC CL RS and CP are supplied by the crystal manufacturer Table 41 components parameters low frequency mode Recommended values for Cx1 x2 in oscillation mode crystal and external Fundamental oscillation frequency Maximum crystal series resistance Rs External load capacitors Cx1 Cx2 2 MHz lt 2009 33 pF 33 pF lt 2009 39 pF 39 pF lt 200 Q 56 pF 56 pF 4 MHz lt 2009 18 pF 18 pF lt 2009 39 pF 39 pF lt 2009 56 pF 56 pF 8 MHz lt 2009 18 pF 18 pF lt 200 Q 39 pF 39 pF All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 135 of 158 NXP Semiconductors LPC4350 30
117. conductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warrant
118. control registers over the AHB slave interface Two AHB bus masters for transferring data These interfaces transfer data when a DMA request goes active Master 1 can access memories and peripherals master 0 can access memories only 32 bit AHB master bus width Incrementing or non incrementing addressing for source and destination Programmable DMA burst size The DMA burst size can be programmed to more efficiently transfer data Internal four word FIFO per channel Supports 8 16 and 32 bit wide transactions Big endian and little endian support The DMA Controller defaults to little endian mode on reset An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred Raw interrupt status The DMA error and DMA count raw interrupt status can be read prior to masking 7 17 2 SPI Flash Interface SPIFI The SPI Flash Interface allows low cost serial flash memories to be connected to the ARM Cortex M4 processor with little performance penalty compared to parallel flash devices with higher pin count LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 70 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 17 2 1 7 17 3 7 17 4 7 17 4 1 LPC4350 30 20 10 32 bit ARM Cortex M4 MO microcontroller After a few commands configure the
119. counter for revolution counting Index compare register with interrupts Can combine index and position interrupts to produce an interrupt for whole and partial revolution displacement Digital filter with programmable delays for encoder input signals Can accept decoded signal inputs clk and direction Repetitive Interrupt RI timer The repetitive interrupt timer provides a free running 32 bit counter which is compared to a selectable value generating an interrupt when a match occurs Any bits of the timer compare function can be masked such that they do not contribute to the match detection The repetitive interrupt timer can be used to create an interrupt that repeats at predetermined intervals Features e 32 bit counter Counter can be free running or be reset by a generated interrupt 32 bit compare value e 32 bit compare mask An interrupt is generated when the counter value equals the compare value after masking This mechanism allows for combinations not possible with a simple compare Windowed WatchDog Timer WWDT The purpose of the watchdog is to reset the controller if software fails to periodically service it within a programmable time window Features Internally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be g
120. ction reserved PU yo U3 UCLK Serial clock input output for USARTS3 in synchronous mode lO SSP1 SSEL Slave Select for SSP1 O TRACEDATA 0 Trace data bit 0 lO GPIO7 19 General purpose digital input output pin R Function reserved lO SGPIO4 General purpose digital input output pin R Function reserved Al ADC1 4 ADC1 and ADCO input channel 4 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 53 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description e 9 59 lz s x m m 2 8 B P s jg E E a enie PF 6 E7 l BI IN l R Function reserved PU JO U3 DIR RS 485 EIA 485 output enable direction control for USART3 O SSP1 MISO Master In Slave Out for SSP1 O TRACEDATA 1 Trace data bit 1 lO GPIO7 20 General purpose digital input output pin R Function reserved lO SGPIO5 General purpose digital input output pin VO
121. cycle 0 50 50 tsu set up time for ENET_TXDn ENET_TX_EN 2 4 ns ENET TX ER th hold time for ENET_TXDn ENET_TX_EN 12 ns ENET TX ER folk clock frequency for ENET RX CLK UM 25 MHz Oclk clock duty cycle O 50 50 96 tsu set up time for ENET_RXDn ENET_RX_ER 2 4 ns ENET RX DV th hold time for ENET_RXDn ENET RX ER 12 2 ns ENET RX DV 1 Output drivers can drive a load 25 pF accommodating over 12 inch of PCB trace and the input capacitance of the receiving device 2 Timing values are given from the point at which the clock signal waveform crosses 1 4 V to the valid input or output level ENET RX CLK ENET TX CLK ENET RXD n ENET RX DV ENET RX ER ENET TXD n ENET TX EN ENET TX ER Fig 38 Ethernet timing 002aag210 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 127 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 11 18 SD MMC Table 33 Dynamic characteristics SD MMC Tamb 40 C to 85 C 22V Vpp REG 3V3 S3 6V 2 7Vs VppvI0 8 6 V C 20 pF SAMPLE DELAY 0x9 DRV_DELAY 0xD in the SDDELAY register sampled at 90 and 10 96 of the signal level EHS 1 for SD CLK pin EHS 1 for SD DATn and SD CMD pins Simulated
122. d PU IVO USB1 ULPI D2 ULP link bidirectional data line 2 R Function reserved ENET RXD2 Ethernet receive data 2 MII interface l O GPIO6 5 General purpose digital input output pin R Function reserved T3_CAP3 Capture input 3 of timer 3 O SD DAT2 SD MMC data bus line 2 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 41 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description a3 l IS lg S 3 is fk s g B s jg E a eae PC_7 G5 l EN l R Function reserved PU JO USB1 ULPI D1 ULP link bidirectional data line 1 R Function reserved ENET_RXD3 Ethernet receive data 3 MII interface l O GPIO6 6 General purpose digital input output pin R Function reserved O T3_MATO Match output 0 of timer 3 O SD DAT3 SD MMC data bus line 3 PC_8 NA l BN l R Function reserved PU IO USBi1 ULPI DO ULP link bidirectional data line O R Function reserved ENET RX DV Ethernet Receive Data Valid RMII MII inte
123. d LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 39 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol g o e m 3 Description 3 8 8 amp is g B B5 j E i E d erie PB 6 A6 C5 l BI IN l R Function reserved PU 1 0 USB1_ULPI_D3 ULP link bidirectional data line 3 O LCD VD13 LCD data R Function reserved l O GPIO5 26 General purpose digital input output pin CTIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 O LCD_VD19 LCD data R Function reserved Al ADC0_6 ADCO and ADC1 input channel 6 Configure the pin as GPIO input and use the ADC function select register in the SCU to select the ADC PC 0 D4 l BN l R Function reserved PU USB1 ULPI CLK ULP link CLK signal 60 MHz clock generated by the PHY R Function reserved l O ENET RX CLK Ethernet Receive Clock MII interface O LCD DCLK LCD panel clock R Function reserved R Function reserved lO SD CLK SD MMC card c
124. disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 69 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 7 17 AHB peripherals 7 17 1 General Purpose DMA GPDMA The DMA controller allows peripheral to memory memory to peripheral peripheral to peripheral and memory to memory transactions Each DMA stream provides unidirectional serial DMA transfers for a single source and destination For example a bidirectional port requires one stream for transmit and one for receives The source and destination areas can each be either a memory region or a peripheral for master 1 but only memory for master 0 7 17 1 1 Features Eight DMA channels Each channel can support a unidirectional transfer 16 DMA request lines Single DMA and burst DMA request signals Each peripheral connected to the DMA Controller can assert either a burst DMA request or a single DMA request The DMA burst size is set by programming the DMA Controller Memory to memory memory to peripheral peripheral to memory and peripheral to peripheral transfers are supported Scatter or gather DMA is supported through the use of linked lists This means that the source and destination areas do not have to occupy contiguous areas of memory Hardware DMA channel priority AHB slave DMA programming interface The DMA Controller is programmed by writing to the DMA
125. document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 73 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller LCD panel clock may be generated from the peripheral clock or from a clock input pin 7 17 8 Ethernet Remark The Ethernet peripheral is available on parts LPC4350 30 See Table 2 7 17 8 1 7 18 7 18 1 7 18 1 1 LPC4350_30_20_10 Features 10 100 Mbit s DMA support Power management remote wake up frame and magic packet detection Supports both full duplex and half duplex operation Supports CSMA CD Protocol for half duplex operation Supports IEEE 802 3x flow control for full duplex operation Optional forwarding of received pause control frames to the user application in full duplex operation Back pressure support for half duplex operation Automatic transmission of zero quanta pause frame on deassertion of flow control input in full duplex operation Supports IEEE1588 time stamping and IEEE 1588 advanced time stamping IEEE 1588 2008 v2 Digital serial peripherals UART1 The LPC4350 30 20 10 contain one UART with standard transmit and receive data lines UARTI also provides a full modem control handshake interface and support for RS 485 9 bit mode allowing both software address detection and automatic address detection using 9 bit mode UAR
126. e LPC4350 30 20 10 contain two C CAN controllers Controller Area Network CAN is the definition of a high performance communication protocol for serial data communication The C CAN controller is designed to provide a full implementation of the CAN protocol according to the CAN Specification Version 2 0B The C CAN controller can create powerful local networks with low cost multiplex wiring by supporting distributed real time control with a high level of reliability 7 18 7 1 Features LPC4350 30 20 10 e Conforms to protocol version 2 0 parts A and B Supports bit rate of up to 1 Mbit s e Supports 32 Message Objects Each Message Object has its own identifier mask Provides programmable FIFO mode concatenation of Message Objects Provides maskable interrupts Supports Disabled Automatic Retransmission DAR mode for time triggered CAN applications Provides programmable loop back mode for self test operation All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 77 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 19 7 19 1 7 19 1 1 7 19 2 7 19 3 7 19 3 1 LPC4350 30 20 10 32 bit ARM Cortex M4 MO microcontroller Counter timers and motor control General purpose 32 bit timers external event counters The LPC4350 30 20 10 include four 32 bit timer counters The timer co
127. e not available on all parts See Table 2 Symbol g Q 2 F 3 Description 3 is g lle g B8 B5 2 FE ele PB 2 B12 B11 BN l R Function reserved PU VO USB1 ULPI D7 ULP link bidirectional data line 7 O LCD VD21 LCD data R Function reserved lO GPIO5 22 General purpose digital input output pin O CTOUT 7 SCTimer PWM output 7 Match output 3 of timer 1 R Function reserved R Function reserved PB 3 A13 A12 2 N R Function reserved PU yo USB1 ULPI D6 ULP link bidirectional data line 6 O LCD VD20 LCD data R Function reserved l O GPIOB 23 General purpose digital input output pin O CTOUT_8 SCTimer PWM output 8 Match output 0 of timer 2 R Function reserved R Function reserved PB 4 B11 B10 RI N l R Function reserved PU yo USB1_ULPI_D5 ULPI link bidirectional data line 5 O LCD_VD15 LCD data R Function reserved lO GPIO5 24 General purpose digital input output pin CTIN_5 SCTimer PWM input 5 Capture input 2 of timer 2 R Function reserved R Function reserved PB_5 A12 Ali 2 N R Function reserved PU yo USB1 ULPI D4 ULP link bidirectional data line 4 O LCD VD14 LCD data R Function reserved l O GPIOB5 25 General purpose digital input output pin CTIN 7 SCTimer PWM input 7 O LCD PWR LCD panel power enable R Function reserve
128. e qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automotive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 20 Contact information 32 bit ARM Cortex M4 M0 microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 19 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC4350_30_20_10
129. ect It is driven by the master and received by the slave Corresponds to the signal WS in the S bus specification R Function reserved T2 CAPO0 Capture input 2 of timer 2 R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 27 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description eg 8 i g 3 g S hk og 8 B P sg E e Z4 P6_2 L13 Kt J9 78 BI N I O GPIO8 1 General purpose digital input output pin PU O EMC_CKEOUT1 SDRAM clock enable 1 l O UO DIR RS 485 EIA 485 output enable direction control for USARTO V O 2S0 RX SDA 2S Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification R Function reserved l T2_CAP1 Capture input 1 of timer 2 R Function reserved R Function reserved P6_3 P15 N13 79 B IN lO GPIOS 2 General purpose digital input output pin PU Jo USBO PPWR VBUS drive signal towards exter
130. ected for LQFP packages Figure 5 and Figure 6 Figure 10 updated All power consumption data updated in Table 10 and Section 10 1 Power consumption BOD levels updated in Table 12 SWD debug option removed for Cortex MO core LPC4350 30 20 10 v 3 2 20120604 Preliminary data sheet LPC4350 30 20 10 v 3 1 LPC4350 30 20 10 v 3 1 20120105 Objective data sheet LPC4350 30 20 10 v 3 LPC4350 30 20 10 v 3 20111205 Objective data sheet LPC4350 30 20 10 v2 1 LPC4350 30 20 10 v2 1 20110923 Objective data sheet LPC4350 30 20 10 v2 LPC4350 30 20 10v 2 20110714 Objective data sheet LPC4350 30 20 10 v 1 LPC4350 30 20 10 v 1 20101029 Objective data sheet LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 154 of 158 NXP Semiconductors LPC4350 30 20 10 19 Legal information 32 bit ARM Cortex M4 M0 microcontroller 19 1 Data sheet status Document status 1l2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specificat
131. ed Product data sheet Rev 4 5 26 November 2015 92 of 158 NXP Semiconductors LPC4350 30 20 10 Table 10 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified 32 bit ARM Cortex M4 M0 microcontroller Symbol Parameter Conditions Min Typ Max Unit Oscillator pins Vi XTAL1 input voltage on pin 0 5 1 2 V XTAL1 Vo xTAL2 output voltage on pin 0 5 1 2 V XTAL2 Cio input output i 0 8 pF capacitance USBO pins Vi input voltage on pins USBO DP USBO DM USBO VBUS Vpp o gt 2 2V 5 25 V Vpp o 0 V 3 6 V Rpa pull down resistance on pin USBO_VBUS 48 64 80 kQ Vic common mode input high speed mode 50 200 500 mV voltage full speed low speed 800 E 2500 mV mode chirp mode 50 600 mV Vidit differential input voltage 100 400 1100 mV USB1 pins USB1 DP USB1 DM I8 loz OFF state output 0OV Vj 3 3V 10 uA current VBus bus supply voltage 5 25 V Vpi differential input D D 0 2 V sensitivity voltage VcM differential common includes Vp range 0 8 2 5 V mode voltage range Vith rs se single ended receiver 0 8 2 0 V switching threshold voltage VoL LOW level output R of 1 5 KQ to 3 6 V 0 18 V voltage for low full speed Vou HIGH level output R of 15 kQ to GND 2 8 3 5 V voltage driven for low full speed Cirans transceiver capacitance pin to GND 20 pF ZpRV drive
132. ed Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 155 of 158 NXP Semiconductors LPC4350 30 20 10 Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotiv
133. ed 3 6 V provides digital I O functions with TTL levels and hysteresis high drive strength 4 5 V tolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V provides high speed digital I O functions with TTL levels and hysteresis 5 5 V tolerant pad providing digital I O functions with TTL levels and hysteresis and analog input or output 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V When configured as an ADC input or DAC output the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull up resistor through the pin s SFSP register 6 5 V tolerant transparent analog pad 7 For maximum load C 6 5 pF and maximum pull down resistance Rpg 80 kO the VBUS signal takes about 2 s to fall from VBUS 5 V to VBUS 0 2 V when it is no longer driven 8 Transparent analog pad Not 5 V tolerant 9 Pad provides USB functions 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only 10 Open drain 5 V tolerant digital I O pad compatible with I2C bus Fast Mode Plus specification This pad requires an external pull up to provide output functionality When power is switched off this pin connected to the I2C bus is floating and does not disturb the 12C lin
134. ed area detail X Dimensions in mm P SL SP SR Hx Hy 0 80 0 40 0 40 0 50 12 30 12 30 44 64 30 15 08 27 Recommend stencil thickness 0 1 mm Issue date sot570 3_fr Fig 56 Reflow soldering of the TFBGA180 package Product data sheet Rev 4 5 26 November 2015 146 of 158 LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Footprint information for reflow soldering of LQFP144 package SOT486 1 4 I x Y Gx gt P2 j P1 Ad o 2L ane ee l Ua ZZ Z ZZ ZZ Za Z Hy Gy ZA ZZ By Ay pz Z7 a Zi za z Z ZA YE a FALLEALSFA EA SFALLEALSEA LEASSS uuuuddd Loos J Ls Bx gt I Ax gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 23 300 23 300 20 300 20 300 1 500 0 280 0 400 20 500 20 500 23 550 23 550 sot486 1_fr Fig 57 Reflow soldering of the LQFP144 package LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet
135. ed for a specific date time Alarm timer The alarm timer is a 16 bit timer and counts down at 1 kHz from a preset value generating alarms in intervals of up to 1 min The counter triggers a status bit when it reaches 0x00 and asserts an interrupt if enabled The alarm timer is part of the RTC power domain and can be battery powered System control Configuration registers CREG The following settings are controlled in the configuration register block BOD trip settings Oscillator output DMA to peripheral muxing e Ethernet mode Memory mapping Timer USART inputs Enabling the USB controllers In addition the CREG block contains the part identification and part configuration information System Control Unit SCU The system control unit determines the function and electrical mode of the digital pins By default function 0 is selected for all pins with pull up enabled For pins that support a digital and analog function the ADC function select registers in the SCU enable the analog function A separate set of analog I Os for the ADCs and the DAC as well as most USB pins are located on separate pads and are not controlled through the SCU In addition the clock delay register for the SDRAM EMC_CLK pins and the registers that select the pin interrupts are located in the SCU Clock Generation Unit CGU The Clock Generator Unit CGU generates several base clocks The base clocks can be unrelated in frequency
136. eep power down mode B9 0 05 uA IppA Analog supply current on pin VDDA n 0 4 deep sleep mode uA power down mode 11 0 4 pA deep power down ml 0 007 mode uA RESET RTC ALARM WAKEUPn pins Vin HIGH level input 10 10 8 x 5 5 V voltage Vps 0 35 Vib LOW level input voltage 10 o 0 3 x V Vps m 0 1 Vhys hysteresis voltage 10 0 05 x V Vps 0 35 Vo output voltage 10 Vo 0 2 V Standard I O pins normal drive strength Ci input capacitance 2 pF ILL LOW level leakage Vi 0 V on chip pull up 3 nA current resistor disabled liu HIGH level leakage Vi Vpp oy on chip 3 nA current pull down resistor disabled Vi 5V 20 nA loz OFF state output Vo 0 Vto Vpp oy 3 nA current on chip pull up down resistors disabled absolute value Vi input voltage pin configured to provide 0 5 5 V a digital function Vpp o gt 2 2V VppiIo 0 V 0 3 6 V Vo output voltage output active 0 Vppio V Vin HIGH level input 0 7 x Vpb o 5 5 V voltage ViL LOW level input voltage 0 0 3 x V Vpp O Vhys hysteresis voltage 0 1 x Vppiio V LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 89 of 158 NXP Semiconductors LPC4350 30 20 10 Table 10 Static characteristics continued Tamb 40 C to
137. elle P6 5 P16 L14 F9 82 2 NN O GPIO3 4 General purpose digital input output pin PU lo CTOUT 6 SCTimer PWM output 6 Match output 2 of timer 1 UO RXD Receiver input for USARTO O EMC RAS LOW active SDRAM Row Address Strobe R Function reserved R Function reserved R Function reserved R Function reserved P6 6 L14 K12 83 BI IN l O GPIOO 5 General purpose digital input output pin PU Jo EMC BLS1 LOW active Byte Lane select signal 1 lO SGPIO5 General purpose digital input output pin USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition R Function reserved T2 CAP3 Capture input 3 of timer 2 R Function reserved R Function reserved P6 7 J13 H1 85 Bl IN R Function reserved PU io EMC_A15 External memory address line 15 l O SGPIO6 General purpose digital input output pin O USBO IND1 USBO port indicator LED control output 1 l O GPIO5 15 General purpose digital input output pin O T2 MATO Match output 0 of timer 2 R Function reserved R Function reserved Pe 8 H13 F12 86 Bl IN R Function reserved PU yo EMC A14 External memory address line 14 lO SGPIO7 Ge
138. enerated at a programmable time prior to watchdog time out Enabled by software but requires a hardware reset or a watchdog reset interrupt to be disabled Incorrect feed sequence causes reset or interrupt if enabled e Flag to indicate watchdog reset Programmable 24 bit timer with internal prescaler All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 79 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Selectable time period from Tcy WDCLk x 256 x 4 to Tcy wDCLk x 224 x 4 in multiples of Tcy WDCLK x 4 The Watchdog Clock WDCLK uses the IRC as the clock source 7 20 Analog peripherals 7 20 1 Analog to Digital Converter ADCO 1 7 20 1 1 Features 10 bit successive approximation analog to digital converter Input multiplexing among 8 pins Power down mode Measurement range 0 to VDDA Sampling frequency up to 400 kSamples s Burst conversion mode for single or multiple inputs e Optional conversion on transition on ADCTRIGO or ADCTRIG1 pins combined timer outputs 8 or 15 or the PWM output MCOA2 Individual result registers for each A D channel to reduce interrupt overhead DMA support 7 20 2 Digital to Analog Converter DAC 7 20 2 1 Features 10 bit resolution Monotonic by design resistor string archi
139. ent is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 138 of 158 NXP Semiconductors LPC4350 30 20 1 0 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller On the LPC4350 30 20 10 USBn_VBUS pins are 5 V tolerant only when VDDIO is applied and at operating voltage level Therefore if the USBn_VBUS function is connected to the USB connector and the device is self powered the USBn_VBUS pins must be protected for situations when VDDIO 0 V If VDDIO is always at operating level while VBUS 5 V the USBn_VBUS pin can be connected directly to the VBUS pin on the USB connector For systems where VDDIO can be 0 V and VBUS is directly applied to the USBn VBUS pins precautions must be taken to reduce the voltage to below 3 6 V which is the maximum allowable voltage on the USBn VBUS pins in this case One method is to use a voltage divider to connect the USBn VBUS pins to VBUS on the USB connector The voltage divider ratio should be such that the USB VBUS pin will be greater than 0 7VDDIO to indicate a logic HIGH while below the 3 6 V allowable maximum voltage For the following operating conditions VBUS max 5 25 V VDDIO 3 6 V the voltage divider should provide a reduction of 3 6 V 5 25 V or 0 686 V For bus powered devices a regulator powered by USB can provide 3 3 V to VDDIO whenever bus power is present and ensure tha
140. ent is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 97 of 158 NXP Semiconductors LPC4350 30 20 1 0 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller 002aah156 10 IDD REG 3V3 uA 8 60 temperature C Conditions Vpp REG 3V3 3 3 V Vear floating VbDp 10 3 3 V Fig 17 Typical supply current versus temperature in Deep power down mode 2aah1 80 002aah150 IBAT uA 60 40 20 0 0 4 0 2 0 0 2 0 4 0 6 VBAT VDD REG 3V3 V Conditions VDD REG 3V3 3 0 V CCLK 12 MHz Fig 18 Typical battery supply current in Active mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 98 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller IBAT pA Conditions Vpb REG 3V3 Vpp 0 floating 002aah157 35 60 temperature C Fig 19 Typical battery supply versus temperature in Deep power down mode 85 10 2 Peripheral power consumption The typical power consumption at T 25 C for each individua
141. ent is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 59 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description a lt 8 lt 6 o amp z g 8 2s gg E 4 Sie VSSIO C4 cs 4 3 Ground D13 D4 40 L4 G6 D5 76 G7 G8 109 G8 J3 H8 J6 H9 J8 J9 K9 K10 M13 P7 P13 VSSA B2 A3 C2 135 Analog ground Not connected B9 B8 n C 1 N neutral input buffer disabled no extra VDDIO current consumption if the input is driven midway between supplies set the EZI bit in the SFS register to enable the input buffer input OL output driving LOW OH output driving HIGH AI O analog input output IA inactive PU pull up enabled weak pull up resistor pulls up pin to VDDIO F floating Reset state reflects the pin state at reset without boot code operation 2 5 V tolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exceed 3 6 V provides digital I O functions with TTL levels and hysteresis normal drive strength 3 5 V tolerant pad with 15 ns glitch filter 5 V tolerant if VDDIO present if VDDIO not present do not exce
142. ernal circuitry required to detect over current condition LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 16 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol g Q 2 F 3 Description 3 g 3E g B B 5 j E E d elie P2_5 K14 J12 D10 91 BI N I O SGPIO14 General purpose digital input output pin PU CTIN 2 SCTimer PWM input 2 Capture input 2 of timer 0 USB1 VBUS Monitors the presence of USB1 bus power Note This signal must be HIGH for USB reset to occur ADCTRIG1 ADC trigger input 1 l O GPIO5 5 General purpose digital input output pin R Function reserved O TS MAT2 Match output 2 of timer 3 O USBO INDO USBO port indicator LED control output 0 P2 6 Ki6 J14 G9 95 N I O SGPIO7 General purpose digital input output pin PU O UO DIR RS 485 EIA 485 output enable direction control for USARTO O EMC A10 External memory address line 10 O USBO INDO USBO port indicator LED control output 0 l O GPIO5 6 Gener
143. es 11 5 V tolerant pad with 20 ns glitch filter provides digital I O functions with open drain output and hysteresis 13 On the LQFP144 package VSSIO and VSS are connected to a common ground plane 12 VPP is internally connected to VDDIO for all packages with the exception of the LBGA256 package 14 On the TFBGA100 package VSS is internally connected to VSSIO LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 60 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 7 Functional description 7 1 7 2 7 3 7 4 LPC4350_30_20_10 Architectural overview The ARM Cortex M4 includes three AHB Lite buses the system bus the I CODE bus and the D code bus The I CODE and D code core buses allow for concurrent code and data accesses from different slave ports The LPC4350 30 20 10 use a multi layer AHB matrix to connect the ARM Cortex M4 buses and other bus masters to peripherals in a flexible manner that optimizes performance by allowing peripherals that are on different slaves ports of the matrix to be accessed simultaneously by different bus masters An ARM Cortex MO co processor is included in the LPC4350 30 20 10 capable of off loading the main ARM Cortex M4 application processor Most peripheral interrupts are connected to bot
144. escription continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 Type d LBGA256 TFBGA180 A TFBGA100 g LQFP144 P1 12 GPIO1 5 General purpose digital input output pin U1 DCD Data Carrier Detect input for UART1 R Function reserved lO EMC D5 External memory data line 5 TO_CAP1 Capture input 1 of timer 0 R Function reserved iN Uz c O lO SGPIO8 General purpose digital input output pin O SD DAT3 SD MMC data bus line 3 P1 13 R10 L8 Hs 60 2 IN lO GPIO1 6 General purpose digital input output pin PU o U1 TXD Transmitter output for UART1 R Function reserved lO EMC D6 External memory data line 6 TO_CAPO Capture input 0 of timer 0 R Function reserved lO SGPIO9 General purpose digital input output pin SD CD SD MMC card detect input P1 14 R11 K7 J8 61 IN l O GPIO1 7 General purpose digital input output pin PU U1 RXD Receiver input for UART1 R Function reserved lO EMC D7 External memory data line 7 O TO MAT2 Match output 2 of timer 0 R Function reserved lO SGPIO10 General purpose digital input output pin R Function reserved P1 15 T12 P11 K8 62 2 IN l O GPIOO 2 General purpose digital inpu
145. extended SEO EOP skew nx TPERIOD tFDEOP Fig 37 Differential data to EOP transition skew and EOP width ger eve source EOP width tFEOPT receiver EOP width teopri tEoPR2 002aab561 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 125 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 31 Static characteristics USBO PHY pins Symbol Parameter Conditions Min Typ Max Unit High speed mode Pons power consumption 2 68 mW IppA ava analog supply current 3 3 V on pin USBO VDDASVS3 DRIVER 3 total supply current 18 mA during transmit 31 mA during receive 14 mA with driver tri stated 14 mA Ippp digital supply current 7 mA Full speed low speed mode Poons power consumption 2 15 mW Ippa sva analog supply current 3 3 V on pin USBO_VDDA3V3_DRIVER total supply current 3 5 mA during transmit 5 mA during receive 3 mA with driver tri stated 3 mA Ippp digital supply current 3 mA Suspend mode IppA ava analog supply current 3 3 V 24 uA with driver tri stated 24 uA with OTG functionality enabled 3 mA Ippp digital supply current 30
146. h processors The processors communicate with each other via an interprocessor communication protocol ARM Cortex M4 processor The ARM Cortex M4 CPU incorporates a 3 stage pipeline uses a Harvard architecture with separate local instruction and data buses as well as a third bus for peripherals and includes an internal prefetch unit that supports speculative branching The ARM Cortex M4 supports single cycle digital signal processing and SIMD instructions A hardware floating point processor is integrated in the core The processor includes an NVIC with up to 53 interrupts ARM Cortex M0 co processor The ARM Cortex MO is a general purpose 32 bit microprocessor which offers high performance and very low power consumption The ARM Cortex MO co processor uses a 3 stage pipeline von Neumann architecture and a small but powerful instruction set providing high end processing hardware In LPC43x0 the Cortex MO coprocessor hardware multiply is implemented as a 32 cycle iterative multiplier The co processor incorporates an NVIC with 32 interrupts Interprocessor communication The ARM Cortex M4 and ARM Cortex MO interprocessor communication is based on using shared SRAM as mailbox and one processor raising an interrupt on the other processor s NVIC for example after it has delivered a new message in the mailbox The receiving processor can reply by raising an interrupt on the sending processor s NVIC to acknowledge the message All information
147. he two counter case the following operational elements are global to the SCTimer PWM but the last three can use match conditions from either counter Clock selection Inputs Events Outputs Interrupts 7 16 1 1 Features Two 16 bit counters or one 32 bit counter Counters clocked by bus clock or selected input Counters can be configured as up counters or up down counters State variable allows sequencing across multiple counter cycles Event combines input or output condition and or counter match in a specified state Events control outputs and interrupts Selected events can limit halt start or stop a counter Supports up to 8 inputs 16 outputs 16 match capture registers 16 events 32 states 7 16 2 Serial GPIO SGPIO The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate serial stream processing 7 16 2 1 Features LPC4350 30 20 10 Each SGPIO input output slice can be used to perform a serial to parallel or parallel to serial data conversion 16 SGPIO input output slices each with a 32 bit FIFO that can shift the input value from a pin or an output value to a pin with every cycle of a shift clock Each slice is double buffered Interrupt is generated on a full FIFO shift clock or pattern match Slices can be concatenated to increase buffer size Each slice has a 32 bit pattern match filter All information provided in this document is subject to legal
148. heet Rev 4 5 26 November 2015 18 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description e co eo S 8 Rx x a lt o oO a ER o aee ig aE E eNA P2_12 E15 D13 B9 106 2 IN O GPIO1 12 General purpose digital input output pin PU lo CTOUT_4 SCTimer PWM output 4 Match output 3 of timer 3 R Function reserved O EMC A3 External memory address line 3 R Function reserved R Function reserved R Function reserved lO U2 UCLK Serial clock input output for USART2 in synchronous mode P2 13 C16 E14 A10 108 Bl N l O GPIO1 13 General purpose digital input output pin PU CTIN_4 SCTimer PWM input 4 Capture input 2 of timer 1 R Function reserved l O EMC A4 External memory address line 4 R Function reserved R Function reserved R Function reserved l O U2 DIR RS 485 EIA 485 output enable direction control for USART2 P3_0 F13 D12 A8 112 B IN VO 1280 RX SCK 12S receive clock It is driven by the master PU and received by the slave Corresponds to the signal SCK in the 2S bus specification O 2S0 RX MCLK 12S receive master clock lO I280 TX SCK
149. hentication Code CSMA CD Carrier Sense Multiple Access with Collision Detection DAC Digital to Analog Converter DC DC Direct Current to Direct Current DMA Direct Memory Access GPIO General Purpose Input Output IRC Internal RC IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display LSB Least Significant Bit MAC Media Access Control MCU MicroController Unit MIIM Media Independent Interface Management n c not connected OHCI Open Host Controller Interface OTG On The Go PHY Physical Layer PLL Phase Locked Loop PMC Power Mode Control PWM Pulse Width Modulator RIT Repetitive Interrupt Timer RMII Reduced Media Independent Interface SDRAM Synchronous Dynamic Random Access Memory SIMD Single Instruction Multiple Data SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port UART Universal Asynchronous Receiver Transmitter ULPI UTMI Low Pin Interface USART Universal Synchronous Asynchronous Receiver Transmitter USB Universal Serial Bus UTMI USB2 0 Transceiver Macrocell Interface All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 149 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 17 References 1 LPC43xx User manual UM10503 http Avww nxp com documents user_
150. herals l RTC I O WAKE to WAKEUP0 1 2 3 pads Vps RTCX1 RTCX2 ind VDDA VSSA VPP USBO VDDA3V DRIVER USBO_VDDA3V3 i USB0 POWER DOMAIN 002aag378 Fig 9 Power domains 7 22 10 Power Management Controller PMC The PMC controls the power to the cores peripherals and memories The LPC4350 30 20 10 support the following power modes in order from highest to lowest power consumption 1 Active mode 2 Sleep mode 3 Power down modes a Deep sleep mode b Power down mode c Deep power down mode LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 83 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 23 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Active mode and sleep mode apply to the state of the core In a dual core system either core can be in active or sleep mode independently of the other core If the core is in Active mode it is fully operational and can access peripherals and memories as configured by software If the core is in Sleep mode it receives no clocks but peripherals and memories remain running Either core can enter sleep mode from active mode independently of the other core and while the other core remains in active mode or is in sleep mode Power down modes apply to the entire system In the Power down modes
151. input Pull up enabled disabled Digital input Pull down enabled disabled Digital input Repeater mode enabled disabled Digital input Input buffer enabled disabled Analog input The default configuration for standard I O pins is input buffer disabled and pull up enabled The weak MOS devices provide a drive capability equivalent to pull up and pull down resistors All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 137 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller VDDIO enable output driver data output from core 1 slew rate bit EHS input buffer enable bit EZI data input to core filter select bit ZIF pull up enable bit EPUN pull down enable bit EPD analog I O The glitch filter rejects pulses of typical 12 ns width Fig 46 Standard I O pin configuration with analog input ESD VSSIO 002aah028 13 6 Reset pin configuration ESD 20 ns RC reset auircH FILTER lt i Fig 47 Reset pin configuration 002aag702 13 7 Suggested USB interface solutions The USB device can be connected to the USB as self powered device see Figure 48 or bus powered device see Figure 49 LPC4350_30_20_10 All information provided in this docum
152. interface at startup the entire flash content is accessible as normal memory using byte halfword and word accesses by the processor and or DMA channels Simple sequences of commands handle erasing and programming Many serial flash devices use a half duplex command driven SPI protocol for device setup and initialization and then move to a half duplex command driven 4 bit protocol for normal operation Different serial flash vendors and devices accept or require different commands and command formats SPIFI provides sufficient flexibility to be compatible with common flash devices and includes extensions to help insure compatibility with future devices Features Interfaces to serial flash memory in the main memory map Supports classic and 4 bit bidirectional serial protocols Half duplex protocol compatible with various vendors and devices Quad SPI Flash Interface SPIFI with 1 2 or 4 bit data at rates of up to 52 MB per second Supports DMA access SD MMC card interface The SD MMC card interface supports the following modes to control Secure Digital memory SD version 3 0 e Secure Digital I O SDIO version 2 0 Consumer Electronics Advanced Transport Architecture CE ATA version 1 1 MultiMedia Cards MMC version 4 4 External Memory Controller EMC The LPC4350 30 20 10 EMC is a Memory Controller peripheral offering support for asynchronous static memory devices such as RAM ROM and NOR flash I
153. ion 1 Please consult the most recently issued document before initiating or completing a design 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 19 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as ag
154. ion LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 56 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description oM sau E 3 is g fk s 8 B 2 ie jg E j E SB Debug pins DBGEN L4 K4 A6 28 Zl I PU JTAG interface control signal Also used for boundary scan To use the part in functional mode connect this pin in one of the following ways Leave DBGEN open The DBGEN pin is pulled up internally by a 50 kO resistor Tie DBGEN to VDDIO Pull DBGEN up to VDDIO with an external pull up resistor TCK SWDCLK J5 G5 H2 27 2 HF Test Clock for JTAG interface default or Serial Wire SW clock TRST M4 L4 B4 29 B I PU I Test Reset for JTAG interface TMS SWDIO K6 K5 C4 30 Bl i PUI Test Mode Select for JTAG interface default or SW debug data input output TDO SWO K5 J5 H3 31 B o O Test Data Out for JTAG interface default or SW trace output TDI J4 H4 G3 26 Bl i PUJI Test Data In for JTAG interface USBO pins USBO_DP F2 E2 E1 18 El l O USBO bidirectional D line USBO DM G2 F2 E2 20 l l l O USBO bidirect
155. ional D line USBO VBUS F1 E1 E3 21 l l I O VBUS pin power on USB cable This pin includes an internal E pull down resistor of 64 kQ typical 16 KQ USBO ID H2 G2 F1 22 Bl l Indicates to the transceiver whether connected as an A device USBO ID LOW or B device USBO ID HIGH For OTG this pin has an internal pull up resistor USBO RREF H1 G1 F3 24 8 l 12 0 KQ accuracy 1 96 on board resistor to ground for current reference USB1 pins USB1 DP F12 Dii E9 89 l O USB1 bidirectional D line USB1_DM G12 E11 E10 90 E l O USB1 bidirectional D line I C bus pins l2C0_SCL L15 K13 D6 92 9 rF I O I C clock input output Open drain output for I2C bus compliance l2C0 SDA L16 Ki4 E6 93 09 LF I O I C data input output Open drain output for I2C bus compliance Reset and wake up pins RESET D9 C7 Be 428 lU JNIA External reset input A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 This pin does not have an internal pull up WAKEUPO A9 A9 A4 130 IA External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration gt 45 ns wakes up the part This pin does not have an internal pull up LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semic
156. is document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 65 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller LPC4350 30 20 10 FJ OxFFFF FFFF c reserved 4GB 0xE010 0000 0xE000 0000 0x8800 0000 SPIFI data 0x8000 0000 256 MB dynamic external memory DYCS3 0x7000 0000 256 MB dynamic external memory DYCS2 0x6000 0000 gt reserved x peripheral bit band alias region 0x4200 0000 0x4010 2000 SFO 0x4010 1000 0x4010 0000 ARM private bus reserved l 0x4400 0000 7E reseed 0x400F 8000 high speed GPIO 0x400F 4000 reserved ENG Ox400F 2000 Ox400F 1000 Ox400F 0000 APB peripherals 3 _ 0x400E 0000 z reserved y 0x400D 0000 0x2000 0000 YF 0x4008 0000 0x1F00 0000 eene 1 0x400A 0000 0x1E00 0000 B reserved J 0x4009 0000 seubenosee NUM 0x1C00 0000 16 MB static external memory CSO reserved ot 3 0x4006 0000 clocking reset peripherals 0x4005 0000 RTC domain peripherals 0x4004 0000 reserved x AHB peripherals 256 MB dynamic external memory DYCS1 SS reserved 0x1800 0000 SPIFI data 0x1400 0000 0x4001 2000 0x4000 0000 0x3000 0000 0x2800 0000 reserved Uu 1GB 0x1041 0000 64 kB ROM 0x1040 0000 128 MB dynamic external memory DYCSO 0x1009 2000 E reserved y i reserved EN 64 kB 8 kB
157. it ARM Cortex M4 MO microcontroller LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Reset state 1 Description d LBGA256 amp TFBGA180 S TFBGA100 amp LQFP144 GPIO1 8 General purpose digital input output pin hg UZ es ils CTOUT 10 SCTimer PWM output 10 Match output 3 of timer 3 R Function reserved EMC CS0 LOW active Chip Select 0 signal USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus external circuitry required to detect over current condition O SSP1 SSEL Slave Select for SSP1 O SGPIO15 General purpose digital input output pin SD POW SD MMC power monitor output P1 6 T4 P3 K4 49 BN Oo GPIO1 9 General purpose digital input output pin PU CTIN 5 SCTimer PWM input 5 Capture input 2 of timer 2 R Function reserved EMC WE LOW active Write Enable signal R Function reserved R Function reserved 1 0 SGPIO14 General purpose digital input output pin 1 0 SD_CMD SD MMC command signal P1_7 T5 N4 G4 50 BN 1 0 GPIO1 0 General purpose digital input output pin PU U1_DSR Data Set Ready input for UART1 CTOUT_13 SCTimer PWM output 13 Match output
158. iven by the PU transmitter and read by the receiver Corresponds to the signal SD in the S bus specification lO 12S0_RX_SDA 2S Receive data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification O CANO TD CAN transmitter output O USB INDO USB1 Port indicator LED control output 0 l O GPIO5 9 General purpose digital input output pin R Function reserved O LCD_VD14 LCD data R Function reserved P3 3 B14 B13 A7 118 IN R Function reserved PU yo SPI SCK Serial clock for SPI l O SSPO SCK Serial clock for SSPO O SPIFI SCK Serial clock for SPIFI O CGU OUT1 CGU spare clock output 1 R Function reserved O 2S0 TX MCLK 12S transmit master clock VO 2S81 TX SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the 1 S bus specification LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 20 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2
159. l peripheral is measured as LPC4350 30 20 10 follows 1 Enable all branch clocks and measure the current IDD REG 3V3 2 Disable the branch clock to the peripheral to be measured and keep all other branch clocks enabled 3 Calculate the difference between measurement 1 and 2 The result is the peripheral power consumption Table 11 Peripheral power consumption Peripheral Branch clock Ipp REGy 3v3 in mA Branch clock Branch clock frequency 48 MHz frequency 96 MHz MO core CLK M4 MOAPP 3 3 6 6 I2C1 CLK APBS l2C1 0 01 0 02 I2CO CLK APB1 Il2CO 0 02 0 01 DAC CLK APB3 DAC 0 01 0 02 ADCO CLK APB3 ADCO 0 05 0 05 ADC1 CLK_APB3_ADC1 0 04 0 04 CANO CLK_APB3_CANO 0 17 0 17 CAN1 CLK APB1 CAN1 0 17 0 17 MOTOCON CLK_APB1_MOTOCON 0 05 0 05 12S CLK_APB1_12S 0 11 0 11 SPIFI CLK_SPIFI 0 95 1 85 CLK_M4_SPIFI GPIO CLK_M4_GPIO 0 66 1 31 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 99 of 158 NXP Semiconductors LPC4350 30 20 10 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Table 11 Peripheral power consumption Peripheral Branch clock Ipp REGy 3v3 in mA Branch clock Branch clock frequency 48 MHz frequency 96 MHz LCD
160. le direction control for USART3 l O EMC A8 External memory address line 8 l O GPIO5 7 General purpose digital input output pin R Function reserved R Function reserved R Function reserved P2 9 H16 G14 B10 102 l JN O GPIO1 10 General purpose digital input output pin Boot PU pin see Table 5 O CTOUT_3 SCTimer PWM output 3 Match output 3 of timer 0 lO U3 BAUD Baud pin for USART3 O EMC A0 External memory address line 0 R Function reserved R Function reserved R Function reserved R Function reserved P2 10 G16 F14 E8 104 Bl IN lO GPIOO 14 General purpose digital input output pin PU Jo CTOUT 2 SCTimer PWM output 2 Match output 2 of timer 0 O U2 TXD Transmitter output for USART2 O EMC A1 External memory address line 1 R Function reserved R Function reserved R Function reserved R Function reserved P2 11 F16 13 A9 105 2 IN l O GPIO1 11 General purpose digital input output pin PU O CTOUT_5 SCTimer PWM output 5 Match output 3 of timer 3 U2_RXD Receiver input for USART2 O EMC A2 External memory address line 2 R Function reserved R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data s
161. lent to discharging a 100 pF capacitor through a 1 5 kQ series resistor LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers Rev 4 5 26 November 2015 NXP Semiconductors N V 2015 All rights reserved 86 of 158 Product data sheet NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller 9 Thermal characteristics The average chip junction temperature T C can be calculated using the following equation T Tamo Pp X Ra Tamb ambient temperature C Rina the package junction to ambient thermal resistance C W e Pp sum of internal and I O power dissipation The internal power dissipation is the product of Ipp and Vpp The I O power dissipation of the I O pins is often small and many times can be negligible However it can be significant in some applications Table 7 Thermal characteristics Vpp 2 2 V to 3 6 V Tamo 40 C to 85 C unless otherwise specified Symbol Parameter Min Typ Max Unit Tjmax maximum junction 125 C temperature Table 8 Thermal resistance LQFP packages Symbol Parameter Conditions Thermal resistance in C W x15 96 LQFP144 Rth a thermal resistance from KEDEC 4 5 in x 4 in still air 38 junction to ambient Single layer 4 5 in x 3 in 50 still air Rih c thermal resistance from 11 junction to case
162. ler Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description e eo S i S T c 7 i 60 9 amp z g 8 e ig 38 8 E a eae USBO G3 F3 D2 17 USB 3 3 V separate power supply voltage _VDDA3V3 USBO_VSSA H3 G3 D3 19 Dedicated analog ground for clean reference for termination _TERM resistors USBO VSSA Gi F1 F2 23 Dedicated clean analog ground for generation of reference REF currents and voltages VDDA B4 A6 B2 137 Analog power supply and ADC reference voltage VBAT B10 B9 C5 127 RTC power supply 3 3 V on this pin supplies power to the RTC VDDREG F10 D8 E4 94 Main regulator power supply Tie the VDDREG and VDDIO F9 E8 E5 131 pins to a common power supply to ensure the same ramp up L8 F4 59 time for both supply voltages L7 25 VPP E8 12 OTP programming voltage VDDIO D7 H5 F10 5 21 I O power supply Tie the VDDREG and VDDIO pins to a E12 H10 K5 36 common power supply to ensure the same ramp up time for F7 K8 41 both supply voltages F8 G10 71 G10 77 H10 107 J6 111 J7 141 K7 L9 L10 N7 N13 VDD Power supply for main regulator I O and OTP vss G9 F10 113 Ground H7 D7 14 J10 E6 J11 ET K8 ES9 K6 K9 LPC4350 30 20 10 All information provided in this docum
163. lock Al ADC1 1 ADC1 and ADCO input channel 1 Configure the pin as input USB ULPI CLK and use the ADC function select register in the SCU to select the ADC PC 1 E4 Bl IN l O USB1 ULPI D7 ULPI link bidirectional data line 7 PU R Function reserved U1 RI Ring Indicator input for UART 1 O ENET MDC Ethernet MIIM clock l O GPIO6 0 General purpose digital input output pin R Function reserved T3 CAPO0 Capture input 0 of timer 3 O SD VOLTO SD MMC bus voltage select output 0 PC 2 Fe l Bl IN O USB1 ULPI D6 ULPI link bidirectional data line 6 PU ds R Function reserved U1 CTS Clear to Send input for UART 1 O ENET_TXD2 Ethernet transmit data 2 MII interface lO GPIO6 1 General purpose digital input output pin R Function reserved R Function reserved O SD RST SD MNC reset signal for MMC4 4 card LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 40 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description a lt 8 2 6 S Ek z g jp j 5 8 amp d m E 4 erie PC 3 F5 S I
164. lock frequency from an external oscillator in the range of 14 kHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The CCO operates in the range of 4 3 MHz to 550 MHz PLLOAUDIO for audio The audio PLL PLLOAUDIO is a general purpose PLL with a small step size This PLL accepts an input clock frequency derived from an external oscillator or internal IRC The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO A sigma delta converter modulates the PLL divider ratios to obtain the desired output frequency The output frequency can be set as a multiple of the sampling frequency fs to 32 x fs 64 x fs 128 x fs 256 x fs 384 x fs 512 x fs and the sampling frequency fs can range from 16 kHz to 192 kHz 16 22 05 32 44 1 48 96 192 kHz Many other frequencies are possible as well using the integrated fractional divider System PLL1 The PLL1 accepts an input clock frequency from an external oscillator in the range of 1 MHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz This range is possible through an additional divider in the loop to keep the CCO within its frequency range while the PLL is providing the desired output frequency The output divider can be set to divide by 2
165. ltage Voy versus HGH level output current lop LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 104 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 002aah450 Vi V Conditions Vpp o 3 3 V Simulated values Fig 24 Typical pull up current ly versus input voltage Vj 120 002aah449 Ipd pA Vi V Conditions Vppiio 3 3 V Simulated values Fig 25 Typical pull down current ly versus input voltage Vj LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 105 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 11 Dynamic characteristics 11 1 Wake up times Table 14 Dynamic characteristic Wake up from Deep sleep Power down and Deep power down modes Tamb 40 C to 85 C Symbol Parameter X Conditions Min Typ Max Unit twake wake up time from Sleep mode 21 3 x 5 x Toy cl ns Tey clk from Deep sleep and 12 51 us Power down mode from Deep power down mode
166. ltage _ interrupt level 0 assertion 2 75 V de assertion 2 92 V interrupt level 1 assertion 2 85 V de assertion 3 00 V interrupt level 2 assertion 2 95 V de assertion 3 12 V interrupt level 3 assertion 3 05 V de assertion 3 19 V reset level 0 assertion 1 70 V de assertion 1 85 V reset level 1 assertion 1 80 V de assertion 1 95 V reset level 2 assertion 1 90 V de assertion 2 05 V reset level 3 assertion 2 00 V de assertion 2 15 V 1 Interrupt and reset levels are selected by writing to the BODLV1 2 bits in the control register CREGEO see the LPC43xx user manual Table 13 Band gap characteristics VppA ava Over specified ranges Tamb 40 C to 105 C unless otherwise specified Symbol Parameter Min Typ Max Unit 0 621 0 6425 0 664 mV Vret bg band gap reference voltage t 1 Based on characterization not tested in production LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 101 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 10 4 Electrical pin characteristics LPC4350 30 20 10 T 002aah030 lo 40 C mA 25 C 85 C 12 9 6 3 0 0
167. manual UM10503 pdf 2 LPC43X0 Errata sheet http Avww nxp com documents errata_shee ES_LPC43XX pdf LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 150 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 18 Revision history Table 44 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC4350 30 20 10 v 4 5 20151126 Product data sheet LPC4350 30 20 10 v 4 4 Modifications Fixed the revision number on the first page to v 4 5 In v 4 4 of the document the revision number of the first page was v 4 3 while the document was at v 4 4 Added a table note The values in the table have been calculated with WAITTURN 0x0 in STATICWAITTURN register See Table 27 Dynamic characteristics Static asynchronous external memory interface Changed footnote 12 in Table 3 Pin description with the text VPP is internally connected to VDDIO for all packages with the exception of the LFBGA256 package Updated Figure 29 I2S bus timing receive for signal I2Sx RX WS changed second half of the signal from tsu D to th D LPC4350 30 20 10 v 4 4 20151117 Product data sheet 2015110031 LPC4350 30 20 10 v 4 3 Modifications e Added GPCLKIN section and table See Section 11 6 GPCL
168. me 2 ns th D data input hold time IU Tscpio 2 ns tsu D data input set up time sampled by ol TscPio 2 ns SGPIO_CLOCK th D data input hold time sampled by Hu TscPio 2 ns SGPIO CLOCK twa data output valid time IU 2 x Tsqpio ns tha data output hold time TscPio ns tva data output valid time sampled by ol 3 3 ns SGPIO_CLOCK tha data output hold time sampled by IU 3 3 ns SGPIO CLOCK 1 SGPIO CLOCK is the internally generated SGPIO clock Tsapio 1 fsaPio cLock SGPIO CLOCK 4 4 4 4 4 CLKINext t LI NS sync CLKINext CLKINi DIN sync DIN CLKout Dout Fig 33 SGPIO timing 002aah668 LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 119 of 158 NXP Semiconductors LPC4350 30 20 10 Table 27 Dynamic characteristics Static asynchronous external memory interface 32 bit ARM Cortex M4 M0 microcontroller 11 15 External memory interface C 22 pF for EMC_Dn C 20 pF for all others Tamb 40 C to 85 C 2 2 V x VopireGy3v3 lt 3 6 V 2 7 V lt Vopii0 x 3 6 V values guaranteed by design the values in the table have been calculated with WAITTURN 0x0 in STATICWAITTURN register Timing parameters are given for single memory access cycles In a normal read operation the EMC
169. miconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 76 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller The I S bus provides a standard communication interface for digital audio applications The S bus specification defines a 3 wire serial bus using one data line one clock line and one word select signal The basic 2S bus connection has one master which is always the master and one slave The I S bus interface provides a separate transmit and receive channel each of which can operate as either a master or a slave 7 18 6 1 Features The I S interface has separate input output channels each of which can operate in master or slave mode Capable of handling 8 bit 16 bit and 32 bit word sizes Mono and stereo audio data supported The sampling frequency can range from 16 kHz to 192 kHz 16 22 05 32 44 1 48 96 192 kHz Support for an audio master clock e Configurable word select period in master mode separately for I2S bus input and output Two 8 word FIFO data buffers are provided one for transmit and one for receive Generates interrupt requests when buffer levels cross a programmable boundary Two DMA requests controlled by programmable buffer levels The DMA requests are connected to the GPDMA block Controls include reset stop and mute options separately for 1 S bus input and I2S bus output 7 18 7 C CAN Remark Th
170. mp is e g B B 5 j zi H E 4 gc c P7 0 B16 B14 110 Bl N O GPIO3 8 General purpose digital input output pin PU lo CTOUT_14 SCTimer PWM output 14 Match output 2 of timer 3 R Function reserved O LCD_LE Line end signal R Function reserved R Function reserved R Function reserved O SGPIO4 General purpose digital input output pin P7 1 C14 C13 113 BN lO GPIOS 9 General purpose digital input output pin PU CTOUT 15 SCTimer PWM output 15 Match output 3 of timer 3 l O 1280 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification O LCD VD19 LCD data O LCD VD7 LCD data R Function reserved O U2_TXD Transmitter output for USART2 l O SGPIO5 General purpose digital input output pin P7 2 A16 A14 115 Bl IN l O GPIO3 10 General purpose digital input output pin PU CTIN 4 SCTimer PWM input 4 Capture input 2 of timer 1 V O I2S0 TX SDA I28 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification O LCD VD18 LCD data O LCD VD6 LCD data R Function reserved U2 RXD Receiver input for USART2 l O SGPIO6 General purpose digital input output pin P7 3 C13 C12 117 B IN lO GPIO3 11 General purpose digital input output pin PU CTIN 3 SCTimer
171. n access all memories on the AHB and all DMA capable AHB slaves Up to 164 General Purpose Input Output GPIO pins with configurable pull up pull down resistors GPIO registers are located on the AHB for fast access GPIO ports have DMA support Up to eight GPIO pins can be selected from all GPIO pins as edge and level sensitive interrupt sources Two GPIO group interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins Four general purpose timer counters with capture and match capabilities One motor control Pulse Width Modulator PWM for three phase motor control One Quadrature Encoder Interface QEI Repetitive Interrupt timer RI timer Windowed watchdog timer WWDT Ultra low power Real Time Clock RTC on separate power domain with 256 bytes of battery powered backup registers Alarm timer can be battery powered W Analog peripherals One 10 bit DAC with DMA support and a data conversion rate of 400 kSamples s Two 10 bit ADCs with DMA support and a data conversion rate of 400 kSamples s Up to eight input channels per ADC Unique ID for each device Power Single 3 3 V 2 2 V to 3 6 V power supply with on chip internal voltage regulator for the core supply and the RTC power domain RTC power domain can be powered separately by a 3 V battery supply Four reduced power modes Sleep Deep sleep P
172. n addition it can be used as an interface with off chip memory mapped devices and peripherals Features Dynamic memory interface support including single data rate SDRAM Asynchronous static memory device support including RAM ROM and NOR flash with or without asynchronous page mode Low transaction latency Read and write buffers to reduce latency and to improve performance 8 16 32 data and 24 address lines wide static memory support 16 bit and 32 bit wide chip select SDRAM memory support e Static memory features include Asynchronous page mode read Programmable Wait States Bus turnaround delay All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 71 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 17 5 7 17 5 1 7 17 6 7 17 6 1 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Output enable and write enable delays Extended wait Four chip selects for synchronous memory and four chip selects for static memory devices e Power saving modes dynamically control EMC_CKEOUT and EMC CLK signals to SDRAMs Dynamic memory self refresh mode controlled by software Controller supports 2048 AO to A10 4096 AO to A11 and 8192 AO to A12 row address synchronous memory parts Those are typically 512 MB 256 MB and 128 MB parts with 4 8
173. nal charge pump or power management unit indicates that the VBUS signal must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts lO SGPIO4 General purpose digital input output pin O EMC CS1 LOW active Chip Select 1 signal R Function reserved T2_CAP2 Capture input 2 of timer 2 R Function reserved R Function reserved P6 4 R16 M14 F6 80 B N l O GPIO3 3 General purpose digital input output pin PU CTIN 6 SCTimer PWM input 6 Capture input 1 of timer 3 O UO TXD Transmitter output for USARTO O EMC CAS LOW active SDRAM Column Address Strobe R Function reserved R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 28 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Description Ao S IS lea 5 X 4 x x o o amp oa E o g a m uL S Oo S m m e
174. nchronous mode R Function reserved l O ENET MDIO Ethernet MIIM data input and output TO_CAP3 Capture input 3 of timer 0 O CAN1_TD CANI transmitter output lO SGPIO11 General purpose digital input output pin R Function reserved P1 18 N12 N10 J10 67 2l N l O GPIOO 13 General purpose digital input output pin PU O U2 DIR RS 485 EIA 485 output enable direction control for USART2 R Function reserved ENET TXDO Ethernet transmit data 0 RMII MII interface TO MATS Match output 3 of timer 0 CAN1 RD CAN receiver input lO SGPIO12 General purpose digital input output pin TOO R Function reserved P1_19 Mii N9 K9 68 2 IN ENET TX CLK ENET REF CLK Ethernet Transmit PU Clock MII interface or Ethernet Reference Clock RMII interface lO SSP1 SCK Serial clock for SSP1 R Function reserved R Function reserved O CLKOUT Clock output pin R Function reserved O 2S0 RX MCLK 12S receive master clock VO 281 TX SCK Transmit Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the 1 S bus specification LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Produc
175. neral purpose digital input output pin O USBO INDO USBO port indicator LED control output 0 l O GPIO5 16 General purpose digital input output pin O T2 MAT1 Match output 1 of timer 2 R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 29 of 158 NXP Semiconductors LPC4350 30 20 10 Table 3 Pin description continued 32 bit ARM Cortex M4 MO microcontroller LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Reset state 1 Type Description Pe 9 S LBGA256 c1 I TFBGA180 wo a TFBGA100 LQFP144 iN UZ c O GPIO3 5 General purpose digital input output pin R Function reserved R Function reserved EMC_DYCS0 SDRAM chip select 0 R Function reserved T2_MAT2 Match output 2 of timer 2 R Function reserved R Function reserved P6_10 H15 G13 100 PU GPIO3 6 General purpose digital input output pin MCABORT Motor control PWM LOW active fast abort R Function reserved EMC_DQMOUT1 Data mask 1 used with SDRAM and static devices R Function
176. ngth high drive mode lou HIGH level output Vou Vpp o 0 4 V 14 mA current lot LOW level output VoL 0 4 V 14 mA current lous HIGH level short circuit drive HIGH connected to nal 113 mA output current ground loLs LOW level short circuit drive LOW connected to nal 110 mA output current Vpp o I O pins high drive strength ultra high drive mode lou HIGH level output Vou Vpp o 0 4 V 20 mA current lo LOW level output Voi 0 4 V 20 mA current lous HIGH level short circuit drive HIGH connected to 12 165 mA output current ground lois LOW level short circuit drive LOW connected to 12 156 mA output current Vpp o l O pins high speed Ci input capacitance 2 pF lu LOW level leakage Vi 0 V on chip pull up 3 nA current resistor disabled LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 91 of 158 NXP Semiconductors LPC4350 30 20 10 Table 10 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified 32 bit ARM Cortex M4 M0 microcontroller Symbol Parameter Conditions Min Typi Max Unit liu HIGH level leakage Vi Vpp oy on chip 3
177. nterrupt e External pins WAKEUPO 1 2 3 and RESET Alarm timer RTC 32 kHz oscillator running The following events if enabled in the event router can create a wake up signal from sleep mode only and or create an interrupt WWDT BOD interrupts e C CANO 1 and QEI interrupts e Ethernet USBO USB1 signals e Selected outputs of combined timers SCTimer PWM and timer0 1 3 Remark Any interrupt can wake up the ARM Cortex M4 from sleep mode if enabled in the NVIC Global Input Multiplexer Array GIMA The GIMA routes signals to event driven peripheral targets like the SCTimer PWM timers event router or the ADCs All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 63 of 158 NXP Semiconductors LPC4350 30 20 10 7 9 1 7 10 7 11 7 12 32 bit ARM Cortex M4 M0 microcontroller Features Single selection of a source Signal inversion Can capture a pulse if the input event source is faster than the target clock Synchronization of input event and target clock Single cycle pulse generation for target On chip static RAM The LPC4350 30 20 10 support up to 200 kB local SRAM and an additional 64 kB AHB SRAM with separate bus master access for higher throughput and individual power control for low power operation In System Programming ISP In System Programming
178. ode microwire frame format z n a ns 1 Toy SSPCLKDIV x 1 SCR x CPSDVSR fmain The clock cycle time derived from the SPI bit rate Tey ck is a function of the main clock frequency fmain the SSP peripheral clock divider SSPCLKDIV the SSP SCR parameter specified in the SSPOCRO register and the SSP CPSDVSR parameter specified in the SSP clock prescale register 2 Tey eik 2 12 x Toy Pcug LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 115 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 11 12 SPI interface Table 25 Dynamic characteristics SPI Tamb 40 C to 85 C 22V Vpp REG 3V3 S38 6V 2 7V 8 VppiI0 lt 8 6 V Simulated values Symbol Parameter Conditions Min Typ Max Unit Toy pcLky PCLK cycle time 5 ns Toy clock cycle time pl 40 ns Master tps data set up time 7 2 ns tou data hold time 0 ns twa data output valid time 3 7 ns tha data output hold time 1 2 ns Slave tos data set up time 1 2 ns toy data hold time 3 x Toy pcLk 0 54 ns tva data output valid time 3 x Tey PcLkK 9 7 ns tha data output hold time 2 x Toy pcLk 7 1 ns H Toye 8 BASE_SPI_CLK Teypcik 1
179. on all parts See Table 2 Symbol o e 2 Description Bie Ie le S 3 E s o amp og E o g t m uL Om S 4 m E z c PC 11 L5 l 2l N l R Function reserved PU USB1_ULPI_DIR ULPI link DIR signal Controls the ULPI data line direction U1 DCD Data Carrier Detect input for UART 1 R Function reserved l O GPIO6 10 General purpose digital input output pin R Function reserved R Function reserved O SD DAT4 SD MMC data bus line 4 PC 12 L6 BN R Function reserved PU R Function reserved O U1_DTR Data Terminal Ready output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 R Function reserved l O GPIO6 11 General purpose digital input output pin lO SGPIO11 General purpose digital input output pin V O I2S0 TX SDA I28 transmit data It is driven by the transmitter and read by the receiver Corresponds to the signal SD in the S bus specification O SD DAT5 SD MMC data bus line 5 PC 13 Mi a BN l R Function reserved PU R Function reserved O U1_TXD Transmitter output for UART 1 R Function reserved l O GPIO6 12 General purpose digital input output pin lO SGPIO12 General purpose digital input output pin V O I2S0 TX WS Tr
180. onductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 57 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description ei e t S 3 is fk s Se es jeg E a eae WAKEUP1 A10 C8 OY EIA External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration gt 45 ns wakes up the part This pin does not have an internal pull up WAKEUP2 C9 E5 OY IA External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration gt 45 ns wakes up the part This pin does not have an internal pull up WAKEUPS3 D8 l OY A I External wake up input can raise an interrupt and can cause wake up from any of the low power modes A pulse with a duration gt 45 ns wakes up the part This pin does not have an internal pull up ADC pins ADCO 0 E3 B6 A2 6 8 LIA I ADC input channel 0 Shared between 10 bit ADCO 1 and ADC1_0 DAC DAC ADCO_1 C3 O4 AM 2 8 LIA I ADC input channel 1 Shared between 10 bit ADCO 1 ADC1 1 ADCO 2 A4 B3 B3 143 8 IIA ADC input channel 2 Shared between 10 bit ADCO
181. ower down and Deep power down Processor wake up from Sleep mode via wake up interrupts from various peripherals Wake up from Deep sleep Power down and Deep power down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 3 of 158 LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller NXP Semiconductors Brownout detect with four separate thresholds for interrupt and forced reset Power On Reset POR Available as LBGA256 TFBGA180 and TFBGA100 packages and as LQFP144 package 3 Applications E Embedded audio applications W Industrial automation Motor control Power management White goods B e metering RFID readers LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved 4 of 158 Product data sheet Rev 4 5 26 November 2015 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC4350FET256 LBGA256 Plastic low profile ball grid array package 256 balls body 17 x 17 x 1 mm SOT740 2 LP
182. provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 61 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 7 5 AHB multilayer matrix TEST DEBUG HIGH SPEED PHY INTERFACE ARM SD DMA ETHERNET USBO USB1 LCD masters 0 1 slaves N N N 64 kB ROM 128 kB LOCAL SRAM N N N N 72 kB LOCAL SRAM SPIFI W 7 N SGPIO 32 kB AHB SRAM K 16 KB 16 kB AHB SRAM EXTERNAL N IN N MEMORY CONTROLLER AHB PERIPHERALS S REGISTER INTERFACES APB RTC x DOMAIN PERIPHERALS master slave connection 002aaf873 Fig 6 AHB multilayer matrix master and slave connections 7 6 Nested Vectored Interrupt Controller NVIC The NVIC is an integral part of the Cortex M4 The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts The ARM Cortex MO co processor has its own NVIC with 32 vectored interrupts Most peripheral interrupts are shared between the Cortex MO and Cortex M4 NVICs LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 62 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex
183. ption continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol g o e m 3 Description 3 8 83 amp is g B5 j E Zi FE d elle P4 9 L2 J2 33 BRI N l R Function reserved PU CTIN_6 SCTimer PWM input 6 Capture input 1 of timer 3 O LCD VD11 LCD data R Function reserved l O GPIO5 13 General purpose digital input output pin O LCD_VD15 LCD data CAN1 RD CANT receiver input lO SGPIO14 General purpose digital input output pin P4 10 M3 L3 35 BI IN l R Function reserved PU CTIN 2 SCTimer PWM input 2 Capture input 2 of timer 0 O LCD VD10 LCD data R Function reserved l O GPIO5 14 General purpose digital input output pin O LCD VD14 LCD data R Function reserved lO SGPIO15 General purpose digital input output pin P5 0 N3 L2 37 BN lO GPIO2 9 General purpose digital input output pin PU O MCOB2C Motor control PWM channel 2 output B lO EMC D12 External memory data line 12 R Function reserved U1_DSR Data Set Ready input for UART 1 T1 CAPO0 Capture input 0 of timer 1 R Function reserved R Function reserved P5 1 P3 M1 39 Bl IN l O GPIO2 10 General purpose digital input output pin PU MCI2 Motor control PWM channel 2 input l O EMC D13 Ex
184. put 6 Capture input 1 of timer 3 T3_CAP2 Capture input 2 of timer 3 R Function reserved P2 3 J12 G11 D8 87 BI IN l O SGPIO12 General purpose digital input output pin PU lO 2C1 SDA 2C1 data input output this pin does not use a specialized I2C pad O U3_TXD Transmitter output for USARTS l CTIN_1 SCTimer PWM input 1 Capture input 1 of timer 0 Capture input 1 of timer 2 l O GPIO5 3 General purpose digital input output pin R Function reserved O T3 MATO Match output 0 of timer 3 O USBO_PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts P2 4 Kt1 L9 D9 88 BI IN l O SGPIO13 General purpose digital input output pin PU yo I2C1 SCL I C1 clock input output this pin does not use a specialized I2C pad U3 RXD Receiver input for USART3 CTIN 0 SCTimer PWM input 0 Capture input 0 of timer 0 1 2 3 l O GPIO5 4 General purpose digital input output pin R Function reserved O T3_MAT1 Match output 1 of timer 3 USBO PWR FAULT Port power fault signal indicating overcurrent condition this signal monitors over current on the USB bus ext
185. r interrupt transfers to the PHY R Function reserved O LCD VD4 LCD data O LCD PWR LCD panel power enable R Function reserved R Function reserved TO_CAP3 Capture input 3 of timer 0 P8 8 L1 K1 z BN R Function reserved PU JUSBi ULPI CLK ULP link CLK signal 60 MHz clock generated by the PHY R Function reserved R Function reserved R Function reserved R Function reserved O CGU OUTO CGU spare clock output 0 O I281 TX MCLK 12S1 transmit master clock P9 0 T1 P1 2I IN lO GPIO4 12 General purpose digital input output pin PU o MCABORT Motor control PWM LOW active fast abort R Function reserved R Function reserved R Function reserved ENET_CRS Ethernet Carrier Sense MII interface l O SGPIOO General purpose digital input output pin lO SSPO SSEL Slave Select for SSPO P9 1 N6 P4 BIN l O GPIO4 13 General purpose digital input output pin PU O MCOA2C Motor control PWM channel 2 output A R Function reserved R Function reserved l O 1280 TX WS Transmit Word Select It is driven by the master and received by the slave Corresponds to the signal WS in the 2S bus specification l ENET_RX_ER Ethernet receive error MII interface l O SGPIO1 General purpose digital input output pin l O
186. r curve of the non calibrated ADC and the ideal transfer curve See Figure 41 7 8 LPC4350 30 20 10 Tamb 25 C Input resistance R depends on the sampling frequency fs Ri 2 KQ 1 fs x Cia All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 130 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller 1023 offset error gain error Eo EG 1022 1021 1020 1019 1018 code out 1LSB ideal Lu 1 2 3 4 5 6 7 1018 1019 1020 1021 Via LSBideal offset error 1024 Example of an actual transfer curve The ideal transfer curve Integral non linearity Ei aqj 1 2 3 Differential linearity error Ep 4 5 Center of a step of the actual transfer curve 10 bit ADC characteristics E V V o fiis DDA 3V3 VSSA 1022 1023 1024 002aaf959 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 131 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller
187. r offers up to 204 MHz performance with a simple instruction set and reduced code size In LPC43x0 the Cortex MO coprocessor hardware multiply is implemented as a 32 cycle iterative multiplier See Section 17 References for additional documentation 2 Features and benefits E Cortex M4 Processor core ARM Cortex M4 processor running at frequencies of up to 204 MHz Built in Memory Protection Unit MPU supporting eight regions Built in Nested Vectored Interrupt Controller NVIC Hardware floating point unit Non maskable Interrupt NMI input JTAG and Serial Wire Debug SWD serial trace eight breakpoints and four watch points Enhanced Trace Module ETM and Enhanced Trace Buffer ETB support System tick timer NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller B Cortex MO Processor core ARM Cortex MO co processor capable of off loading the main ARM Cortex M4 application processor Running at frequencies of up to 204 MHz JTAG and built in NVIC E On chip memory Up to 264 kB SRAM for code and data use Multiple SRAM blocks with separate bus access Two SRAM blocks can be powered down individually 64 kB ROM containing boot code and on chip software drivers 64 bit 256 bit general purpose One Time Programmable OTP memory W Clock generation unit Crystal oscillator with an operating range of 1 MHz to 25 MHz 12 MHz
188. r output with 33 Q series resistor 36 44 1 Q impedance for driver which is not high speed capable steady state drive 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 The recommended operating condition for the battery supply is Vpp REG ava gt Vegar 0 2 V See Figure 18 3 Pin VPP should either be not connected when OTP does not need to be programmed or tied to pins VDDIO and VDDREG to ensure the same ramp up time for both supply voltages 4 Vpb nEGy 3va 3 3 V Vppio 3 3 V Tamb 25 C LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 93 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller 5 PLL1 disabled IRC running CCLK 12 MHz 6 Vaar 3 6 V 7 Vop 0 Vppa 3 6 V over entire frequency range CCLK 12 MHz to 180 MHz 8 On pin VBAT Tamb 25 C 9 Voppb REGy 3v3 3 3 V Vpp o 3 3 V Input leakage increases when Vppiio is floating or grounded It is recommended to keep Vpp REG 3v3 and Vpp io powered in deep power down mode 10 Vps corresponds to the output of the power switch see Figure 9 which is determined by the greater of Vaar and Vpp Reg 3v3 11 Vppa ava 3 3 V Tamo 25
189. rame format 0 5 x Toy clIk ns LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 113 of 158 LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller NXP Semiconductors Table 24 Dynamic characteristics SSP pins in SPI mode Tamb 40 C to 85 C 2 2 V lt Vpp nea ava 3 6 V 2 7 V x Vpp io 3 6 V C 20 pF Sampled at 10 and 90 of the signal level EHS 1 for all pins Simulated values Symbol Parameter Conditions Min Typ Max Unit ty delay time continuous transfer mode 0 5 x Toy ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 n a ns CPHA 1 SPI mode CPOL 1 0 5 x Toygk ns CPHA 0 SPI mode CPOL 1 n a ns CPHA 1 synchronous serial Tey clk ns frame mode microwire frame format n a ns SSP slave PCLK Peripheral clock 204 MHz frequency Toy clk clock cycle time 2 1 11 x 109 S tps data set up time in SPI mode 1 15 ns tou data hold time in SPI mode 0 5 ns twa data output valid in SPI mode 4 x 1 PCLK 3 ins time tha data output hold in SPI mode 5 1 ns time tlead lead time continuous transfer mode Toy clk 2 2 ns SPI mode CPOL 0 CPHA 0 SPI mode CPOL 0 0 5 x Tey ck 2 2 ns CPHA 1
190. rate as either a receiver only device for example an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C is a multi master bus and can be controlled by more than one bus master connected to it Features e C0 is a standard I2C compliant bus interface with open drain pins I CO also supports Fast mode plus with bit rates up to 1 Mbit s e C1 uses standard l O pins with bit rates of up to 400 kbit s Fast I C bus Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The l C bus can be used for test and diagnostic purposes All IC bus controllers support multiple address recognition and a bus monitor mode 12S interface Remark The LPC4350 30 20 10 contain two I S bus interfaces All information provided in this document is subject to legal disclaimers NXP Se
191. reed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitly agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 19 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and condition
192. reserved R Function reserved R Function reserved R Function reserved P6 11 H12 F11 C9 101 PU GPIO3 7 General purpose digital input output pin R Function reserved R Function reserved EMC CKEOUTO SDRAM clock enable 0 R Function reserved T2 MATS Match output 3 of timer 2 R Function reserved R Function reserved P6 12 G15 F13 103 PU GPIO2 8 General purpose digital input output pin CTOUT 7 SCTimer PWM output 7 Match output 3 of timer 1 R Function reserved EMC DQMOUTO Data mask 0 used with SDRAM and static devices R Function reserved R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 30 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol Q 2 F 3 Description 10 SE t 3 3 BS a
193. reserved R Function reserved lO SGPIO4 General purpose digital input output pin PD 1 P1 l R N l R Function reserved PU R Function reserved O EMC CKEOUT2 SDRAM clock enable 2 R Function reserved l O GPIO6 15 General purpose digital input output pin O SD POW SD MMC power monitor output R Function reserved O SGPIO5 General purpose digital input output pin PD 2 R1 2 N R Function reserved PU o CTOUT 7 SCTimer PWM output 7 Match output 3 of timer 1 lO EMC D16 External memory data line 16 R Function reserved l O GPIO6 16 General purpose digital input output pin R Function reserved R Function reserved lO SGPIO6 General purpose digital input output pin PD 3 P4 l 2 N l R Function reserved PU Jo CTOUT_6 SCTimer PWM output 7 Match output 2 of timer 1 O EMC D17 External memory data line 17 R Function reserved lO GPIO6 17 General purpose digital input output pin R Function reserved R Function reserved lO SGPIO7 General purpose digital input output pin LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 44 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller
194. reserved PE 10 E14 RI N l R Function reserved PU CTIN_3 SCTimer PWM input 3 Capture input 1 of timer 1 O U1_DTR Data Terminal Ready output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 l O EMC D29 External memory data line 29 l O GPIO7 10 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 50 of 158 NXP Semiconductors LPC4350 30 20 10 Table 3 Pin description continued 32 bit ARM Cortex M4 M0 microcontroller LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol TFBGA180 TFBGA100 LQFP144 Reset state 1 Type Description PE 11 C LBGA256 Oo Ni UZ c R Function reserved CTOUT 12 SCTimer PWM output 12 Match output 3 of timer 3 U1 TXD Transmitter output for UART 1 1 0 EMC_D30 External memory data line 30 1 0 GPIO7 11 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 12 D15 PU R Function reserved CTOUT 11 SCTimer PWM output 11 Match output 3 of
195. rface lO GPIO6 7 General purpose digital input output pin R Function reserved O T3_MAT1 Match output 1 of timer 3 SD CD SD MMC card detect input PC 9 K2 l BN R Function reserved PU USB1 ULPI NXT ULP link NXT signal Data flow control signal from the PHY R Function reserved ENET RX ER Ethernet receive error MII interface l O GPIO6 8 General purpose digital input output pin R Function reserved T3 MAT2 Match output 2 of timer 3 SD POW SD MMC power monitor output PC 10 M5 BN R Function reserved PU USBI ULPI STP ULP link STP signal Asserted to end or interrupt transfers to the PHY U1_DSR Data Set Ready input for UART 1 R Function reserved OoOo l O GPIO6 9 General purpose digital input output pin R Function reserved O T3 MATS Match output 3 of timer 3 O SD CMD SD MMC command signal LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 42 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available
196. rface lO SGPIO9 General purpose digital input output pin O U3 TXD Transmitter output for USARTS P9 4 N10 M8 BN R Function reserved PU MCOBOC Motor control PWM channel 0 output B O USB1 INDO USB1 Port indicator LED control output 0 R Function reserved lO GPIO5 17 General purpose digital input output pin O ENET_TXD2 Ethernet transmit data 2 MII interface lO SGPIO4 General purpose digital input output pin U3 RXD Receiver input for USART3 P9 5 M9 L7 69 B N l R Function reserved PU O MCOA1 Motor control PWM channel 1 output A O USB1 PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active high Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB_PPWR used on other NXP LPC parts R Function reserved l O GPIOB 18 General purpose digital input output pin O ENET TXD3 Ethernet transmit data 3 MII interface lO SGPIOS3 General purpose digital input output pin O UO TXD Transmitter output for USARTO LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 36 of 158 N
197. ription Se ee 8 3 g 3 E sz 8 B P s jg E Er E E gg eae P5 6 T13 Mii 63 Bl IN l O GPIO2 15 General purpose digital input output pin PU MCOBI1 Motor control PWM channel 1 output B O EMC D10 External memory data line 10 s R Function reserved U1 TXD Transmitter output for UART 1 T1 MAT2 Match output 2 of timer 1 R Function reserved R Function reserved P5 7 R12 Nii l 65 Bl N l O GPIO2 7 General purpose digital input output pin PU O MCOA2C Motor control PWM channel 2 output A O EMC D11 External memory data line 11 R Function reserved U1 RXD Receiver input for UART 1 O T1_MAT3 Match output 3 of timer 1 R Function reserved R Function reserved P6 0 M12 M10 H7 73 B IN R Function reserved PU O 2S0 RX MCLK 12S receive master clock R Function reserved R Function reserved lO 2S0 RX SCK Receive Clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification R Function reserved R Function reserved R Function reserved P6 1 R15 P14 G5 74 B IN l O GPIOS 0 General purpose digital input output pin PU EMC DYCS1 SDRAM chip select 1 l O UO UCLK Serial clock input output for USARTO in synchronous mode lO 1280 RX WS Receive Word Sel
198. rning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2015 All rights reserved For more information please visit http Awww nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 26 November 2015 Document identifier LPC4350 30 20 10
199. rved R Function reserved PE 4 K13 J11 PU R Function reserved NMI External interrupt input to NMI R Function reserved O EMC A22 External memory address line 22 O GPIO7 4 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 5 N16 PU R Function reserved CTOUT 3 SCTimer PWM output 3 Match output 3 of timer 0 U1 RTS Request to Send output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 O EMC D24 External memory data line 24 O GPIO7 5 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 6 M16 PU R Function reserved CTOUT 2 SCTimer PWM output 2 Match output 2 of timer 0 U1 RI Ring Indicator input for UART 1 O EMC D25 External memory data line 25 1 0 GPIO7 6 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 49 of 158
200. s 0 26 us tHD DAT data hold time BIBI Standard mode 0 us Fast mode 0 7 us Fast mode Plus 0 us tsu DAT data set up time 8119 Standard mode 250 ns Fast mode 100 ns Fast mode Plus 50 ns 1 Parameters are valid over operating temperature range unless otherwise specified See the I C bus specification UM10204 for details 2 tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 3 A device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the Viu min of the SCL signal to bridge the undefined region of the falling edge of SCL 4 Cp total capacitance of one bus line in pF If mixed with Hs mode devices faster fall times are allowed 5 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified t 6 In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing 7 The maximum tgup par could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ pAr or tvp ack by a transition time This maximum must only be met if the devi
201. s of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semi
202. served O SGPIO1 General purpose digital input output pin R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 52 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description EET E 3 is s 8 B s jg E d E SB PF 3 E10 EN l R Function reserved PU n U3 RXD Receiver input for USART3 l O SSPO MOSI Master Out Slave in for SSPO R Function reserved lO GPIO7 18 General purpose digital input output pin R Function reserved lO SGPIO2 General purpose digital input output pin R Function reserved PF 4 D10 D6 H4 120 J O O SSP1 SCK Serial clock for SSP1 PU GP CLKIN General purpose clock input to the CGU O TRACECLK Trace clock R Function reserved R Function reserved R Function reserved O 2S0 TX MCLK 12S transmit master clock lO 2S0 RX SCK I28 receive clock It is driven by the master and received by the slave Corresponds to the signal SCK in the S bus specification PF_5 E9 l z BN R Fun
203. sis voltage 0 1 x Vpp o V lod pull down current Vi Vpp io 4115 62 uA 16 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 90 of 158 NXP Semiconductors LPC4350 30 20 10 Table 10 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified 32 bit ARM Cortex M4 M0 microcontroller Symbol Parameter Conditions Min Typi Max Unit lou pull up current Vi 0V 4115 62 uA 16 Vpp I0 lt V lt 5V 10 uA I O pins high drive strength standard drive mode lou HIGH level output VoH Vpp o 0 4 V 4 z mA current loL LOW level output Vor 0 4 V 4 mA current lous HIGH level short circuit drive HIGH connected to a 32 mA output current ground lots LOW level short circuit drive LOW connected to 112 32 mA output current Vpp o I O pins high drive strength medium drive mode lou HIGH level output Vou Vpp o 0 4 V 8 mA current lo LOW level output Vor 0 4 V 8 mA current lous HIGH level short circuit drive HIGH connected to nal 65 mA output current ground loLs LOW level short circuit drive LOW connected to nal 63 mA output current Vpp o I O pins high drive stre
204. t data sheet Rev 4 5 26 November 2015 14 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description o amp 3 8 3 3 js fk s o amp 8 oa E a eg a Tm uL o Oo S E qu erie P1_20 M10 J10 K10 70 IN l O GPIOO 15 General purpose digital input output pin PU yo SSP1 SSEL Slave Select for SSP1 R Function reserved O ENET TXD1 Ethernet transmit data 1 RMII MII interface TO CAP2 Capture input 2 of timer 0 R Function reserved l O SGPIO13 General purpose digital input output pin R Function reserved P2 0 Ti6 N14 G10 75 2 IN l O SGPIOA General purpose digital input output pin PU Jo UO TXD Transmitter output for USARTO O EMC A13 External memory address line 13 O USBO0 PPWR VBUS drive signal towards external charge pump or power management unit indicates that VBUS must be driven active HIGH Add a pull down resistor to disable the power switch at reset This signal has opposite polarity compared to the USB PPWR used on other NXP LPC parts l O GPIOB 0 General purpose digital input output pin R Function reserved T3_CAPO Capture input 0 of timer 3 O ENET MDC Ethernet MIIM clock P2_1 N15
205. t output pin PU o U2 TXD Transmitter output for USART2 lO SGPIO2 General purpose digital input output pin ENET RXDO Ethernet receive data 0 RMII MII interface O TO MAT1 Match output 1 of timer 0 R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 13 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Description Symbol Reset state 1 Type LBGA256 5 TFBGA180 d TFBGA100 V LQFP144 P1 16 GPIOO 3 General purpose digital input output pin U2 RXD Receiver input for USART2 lO SGPIOS3 General purpose digital input output pin ENET CRS Ethernet Carrier Sense MII interface O TO MATO Match output 0 of timer 0 R Function reserved iN Uz c O R Function reserved ENET RX DV Ethernet Receive Data Valid RMII MII interface P1 17 M8 L6 H10 66 BI IN l O GPIOO 12 General purpose digital input output pin PU VO U2 UCLK Serial clock input output for USART2 in sy
206. t power to the USBn VBUS pins is always present when the 5 V VBUS signal is applied See Figure 49 Remark Applying 5 V to the USBn VBUS pins for a short time while the regulator ramps up might compromise the long term reliability of the part but does not affect its function LPC43xx VDDIO R2 R3 USBn VBUS VBUS USB B connector aaa 013458 Fig 48 USB interface on a self powered device where USBn VBUS 5 V All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 139 of 158 NXP Semiconductors LPC4350 30 20 10 LPC4350_30_20_10 Product data sheet 32 bit ARM Cortex M4 M0 microcontroller LPC43xx REGULATOR USBn_VBUS VBUS USB B connector aaa 013459 Fig 49 USB interface on a bus powered device Remark If the VBUS function of the USB1 interface is not connected configure the pin function for GPIO using the function control bits in the SYSCON block VDDIO R1 LPC43xx Exe USBn VBUS VBUS gt 1 4 USB B 24 connector gt gt aaa 013460 Fig 50 USB interface for USB operating in OTG mode Remark In OTG mode it is impor
207. tant to be able to detect the VBUS level and to charge and discharge VBUS This requires adding active devices that disconnect the link when VDDIO is not present All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Rev 4 5 26 November 2015 140 of 158 NXP Semiconductors LPC4350 30 20 10 14 Package outline 32 bit ARM Cortex M4 M0 microcontroller LBGA256 plastic low profile ball grid array package 256 balls body 17 x 17 x 1mm SOT740 2 lt D T B a ball A1 index area A2 A ti A1 i detail X zi 4 gt e 1 2 e b v WCIAIB H Yi 00000 OOOOO ne O000 OOOOO OoOooooO 100000 OOOOOOO0000000 00000000 00000 OOOOOOOO000000 OOOOO ooo0oo0oo0o ball A1 index area 2 4 6 8 10 12 14 16 0 5 10 mm SESSA scale DIMENSIONS mm are the original dimensions A UNIT max A1 A2 b D E e e1 e2 v w y y 0 45 1 1 0 55 17 2 17 2 mm 1 55 035 09 045 168 168 1 15 15 0 25 0 1 0 12 0 35 OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION ISSUE DATE 05 06 46 SOT740 2 MO 192 s E fee Gd Fig 51 Package outline LB
208. tecture Controllable conversion speed Low power consumption 7 21 Peripherals in the RTC power domain 7 21 1 RTC The Real Time Clock RTC is a set of counters for measuring time when system power is on and optionally when it is off It uses little power when the CPU does not access its registers especially in the reduced power modes A separate 32 kHz oscillator clocks the RTC The oscillator produces a 1 Hz internal time reference and is powered by its own power supply pin VBAT 7 21 1 1 Features Measures the passage of time to maintain a calendar and clock Provides seconds minutes hours day of month month year day of week and day of year Ultra low power design to support battery powered systems Uses power from the CPU power supply when it is present Dedicated battery power supply pin RTC power supply is isolated from the rest of the chip LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 80 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 21 2 7 22 7 22 1 7 22 2 7 22 3 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Calibration counter allows adjustment to better than 1 sec day with 1 sec resolution Periodic interrupts can be generated from increments of any field of the time registers Alarm interrupt can be generat
209. ternal memory data line 13 R Function reserved O U1_DTR Data Terminal Ready output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 T1 CAP1 Capture input 1 of timer 1 R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 25 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o o 2 Description o cf amp 3 8 3 6 g Ez 8g B B s jg E SB P5 2 RA M3 46 B N O GPIO2 11 General purpose digital input output pin PU MCI1 Motor control PWM channel 1 input lO EMC D14 External memory data line 14 R Function reserved O U1_RTS Request to Send output for UART 1 Can also be configured to be an RS 485 EIA 485 output enable signal for UART 1 T1_CAP2 Capture input 2 of timer 1 R Function reserved R Function reserved P5 3 T8 P6 54 Bl IN lO GPIO2 12 General purpose digital input output pin PU MCIO Motor control PWM channel 0 input VO EMC D15 Ex
210. ternal memory data line 15 R Function reserved U1 RI Ring Indicator input for UART 1 T1_CAP3 Capture input 3 of timer 1 R Function reserved R Function reserved P5 4 P9 N7 57 IN l O GPIO2 13 General purpose digital input output pin PU MCOBO Motor control PWM channel 0 output B lO EMC D8 External memory data line 8 R Function reserved U1_CTS Clear to Send input for UART 1 O T1_MATO Match output 0 of timer 1 R Function reserved R Function reserved P55 P10 N8 l 58 Bl IN lO GPIO2 14 General purpose digital input output pin PU O MCOA1 Motor control PWM channel 1 output A lO EMC D9 External memory data line 9 R Function reserved U1_DCD Data Carrier Detect input for UART 1 O T1_MAT1 Match output 1 of timer 1 R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 26 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin description continued LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol o e 2 Desc
211. timer 2 U1 RXD Receiver input for UART 1 O EMC D31 External memory data line 31 O GPIO7 12 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 13 G14 PU R Function reserved CTOUT 14 SCTimer PWM output 14 Match output 2 of timer 3 I2C1 SDA 2C1 data input output this pin does not use a specialized I2C pad EMC DQMOUTS Data mask 3 used with SDRAM and static devices GPIO7 13 General purpose digital input output pin R Function reserved R Function reserved R Function reserved PE 14 C15 PU R Function reserved R Function reserved R Function reserved EMC DYCS3 SDRAM chip select 3 GPIO7 14 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 51 of 158 NXP Semiconductors LPC4350 30 20 10 Table 3 Pin description continued 32 bit ARM Cortex M4 MO microcontroller LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2
212. tion reserved R Function reserved l O EMC A19 External memory address line 19 lO GPIO7 1 General purpose digital input output pin CAN1 RD CANT receiver input R Function reserved R Function reserved PE 2 M14 L12 2I IN ADCTRIGO ADC trigger input 0 PU CANO_RD CAN receiver input R Function reserved O EMC A20 External memory address line 20 lO GPIO7 2 General purpose digital input output pin R Function reserved R Function reserved R Function reserved LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 48 of 158 NXP Semiconductors LPC4350 30 20 10 Table 3 Pin description continued 32 bit ARM Cortex M4 MO microcontroller LCD Ethernet USBO and USB1 functions are not available on all parts See Table 2 Symbol TFBGA100 LQFP144 Reset state 1 Description PE 3 A LBGA256 M A TFBGA180 D UZ c R Function reserved CANO TD CAN transmitter output ADCTRIG1 ADC trigger input 1 EMC A21 External memory address line 21 GPIO7 3 General purpose digital input output pin R Function reserved R Function rese
213. tsu D gt t Y th D Fig 29 1 S bus timing receive 002aag498 11 10 USART interface Table 23 USART dynamic characteristics Tamb 40 C to 85 C 22V lt Vpb REG 3V3 lt 3 6 V 2 7 V lt VppvI0 3 6 V C 20 pF EHS 1 for all pins Simulated values Symbol Parameter Min Max Unit USART master in synchronous mode tsu D data input set up time 26 6 ns th D data input hold time 0 ns twa data output valid time 0 8 8 ns USART slave in synchronous mode tsu D data input set up time 1 2 ns th D data input hold time 0 4 i ns twa data output valid time 5 5 24 ns LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 111 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller lt _ Tey clk SCLK FES 1 SCLK FES 0 ty Q I lt tv Q TXD A START m BIT1 RXD aaa 016717 Fig 30 USART timing LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 112 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller
214. uA VBUS detector outputs Vin threshold voltage for VBUS valid 4 4 V for session end 0 2 0 8 V for A valid 0 8 2 V for B valid 2 4 V Vhys hysteresis voltage for session end 150 10 mV A valid 200 10 mV B valid 200 10 mV 1 2 3 Total average power consumption The driver is active only 20 of the time 11 17 Ethernet Characterized but not implemented as production test Remark The timing characteristics of the ENET_MDC and ENET_MDIO signals comply with the EEE standard 802 3 LPC4350_30_20_10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 126 of 158 NXP Semiconductors LPC4350 30 20 10 32 bit ARM Cortex M4 M0 microcontroller Table 32 Dynamic characteristics Ethernet Tamb 40 C to 85 C 2 2 V lt Vppinga ava 3 6 V 2 7 V lt Vopao 3 6 V Values guaranteed by design Symbol Parameter Conditions Min Max Unit RMII mode folk clock frequency for ENET RX CLK u 50 MHz Sclk clock duty cycle 0 50 50 96 tsu set up time for ENET_TXDn ENET_TX_EN lal 4 ns ENET_RXDn ENET RX ER ENET RX DV th hold time for ENET_TXDn ENET_TX_EN 12 p ns ENET RXDn ENET_RX_ER ENET RX DV MII mode folk clock frequency for ENET TX CLK U is 25 MHz Sclk clock duty
215. umn address strobe valid delay time 2 9 0 5 x Toyctk 4 6 0 5 x Toyo NS th cas column address strobe hold time 0 3 0 5 x Tog 0 9 0 5 x Tog ns ta wev WE valid delay time 3 24 0 5xTeyck 5 9 0 5 x Toyo ns thwe WE hold time 1 3 0 5 x Toa 1 4 0 5 Toyo ns ta pamoutv DQMOUT valid delay time 3 1 0 5 x Toye 5 0 0 5 x Toyck NS thipamout DQMOUT hold time 0 2 0 5 x Tog 10 8 0 5 x Toyck ns taav address valid delay time 3 8 0 5 x Toy 6 3 0 5 x Toy gy ns thia address hold time 0 3 0 5 x Toyo 10 9 0 5 x Toy ns taickEouTv CKEOUT valid delay time 3 1 0 5 x Toy 5 1 0 5 x Tog NS thickEouT CKEOUT hold time 0 5 x Tey cik 0 7 0 5 x Toc ns Read cycle parameters tsu D data input set up time 1 5 0 5 ns th D data input hold time E 0 8 2 2 ns Write cycle parameters taav data output valid delay time 3 8 0 5 x Toyo 6 2 0 5 x Toy gy NS tha data output hold time 0 5 x Tey cik 0 7 0 5 x Toc ns Table 29 Dynamic characteristics Dynamic external memory interface EMC_CLK 3 0 delay values Tamb 40 C to 85 C Vppio 3 3 V 10 2 2 V lt Vpp nEay ava lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit ta delay time delay value CLKn DELAY 0 0 0 0 0 0 0 ns CLKn DELAY 1 H 0 4 0 5 0 8 ns CLKn DELAY 2 11 0 7 1 0 1 7 ns CLKn_DELAY 3 l 1 1 1 6 2 5 ns CLKn DELAY 4 11 1 4 2 0 3 3 ns CLKn_DELAY 5 H 1 7 2 6 4 1 ns CLKn DELAY 26 2 1
216. unter is designed to count cycles of the system derived clock or an externally supplied clock It can optionally generate interrupts generate timed DMA requests or perform other actions at specified timer values based on four match registers Each timer counter also includes two capture inputs to trap the timer value when an input signal transitions optionally generating an interrupt Features A 32 bit timer counter with a programmable 32 bit prescaler Counter or timer operation Two 32 bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event can also generate an interrupt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match Up to two match registers can be used to generate timed DMA requests Motor control PWM The motor control PWM is a specialized PWM supporting 3 phase motors and other combinations Feedback inputs are provided to automatically sense rotor position and use that information to ramp speed up or down An abort input causes the PWM to release all motor drive outputs immediatel
217. ut output pin PU lo U1 RTS Request to Send output for UART1 O CTOUT 11 SCTimer PWM output 11 Match output 3 of timer 2 lO EMC D2 External memory data line 2 R Function reserved R Function reserved R Function reserved O SD DATO SD MMC data bus line 0 P1 10 R8 N6 H6 53 2 IN l O GPIO1 3 General purpose digital input output pin PU Ut RI Ring Indicator input for UART1 O CTOUT 14 SCTimer PWM output 14 Match output 2 of timer 3 lO EMC D3 External memory data line 3 R Function reserved R Function reserved R Function reserved O SD DAT1 SD MMC data bus line 1 P1 11 T9 PB J7 55 B IN lO GPIO1 4 General purpose digital input output pin PU U1 CTS Clear to Send input for UART1 O CTOUT 15 SCTimer PWM output 15 Match output 3 of timer 3 lO EMC DA External memory data line 4 R Function reserved R Function reserved R Function reserved O SD DAT2 SD MMC data bus line 2 LPC4350 30 20 10 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 12 of 158 NXP Semiconductors LPC4350 30 20 1 0 32 bit ARM Cortex M4 M0 microcontroller Table 3 Pin d
218. y At the same time the motor control PWM is highly configurable for other generalized timing counting capture and compare applications Quadrature Encoder Interface QEI A quadrature encoder also known as a 2 channel incremental encoder converts angular displacement into two pulse signals By monitoring both the number of pulses and the relative phase of the two signals the user code can track the position direction of rotation and velocity In addition a third channel or index signal can be used to reset the position counter The quadrature encoder interface decodes the digital pulses from a quadrature encoder wheel to integrate position over time and determine direction of rotation In addition the QEI can capture the velocity of the encoder wheel Features Tracks encoder position All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2015 All rights reserved Product data sheet Rev 4 5 26 November 2015 78 of 158 NXP Semiconductors LPC4350 30 20 1 0 7 19 4 7 19 4 1 7 19 5 7 19 5 1 LPC4350_30_20_10 32 bit ARM Cortex M4 M0 microcontroller Increments decrements depending on direction Programmable for 2x or 4x position counting Velocity capture using built in timer Velocity compare function with less than interrupt Uses 32 bit registers for position and velocity Three position compare registers with interrupts Index

LPC4350 datasheet - NXP Semiconductors

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