ADM User`s manual
Contents
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5. 0005 509 ior 50 6005 208 scs 79 600 JIA E08 13S34VSI 105 nds C AUdISH 208 Tanovsi senor ZY DOS OND 09 Tv TN03 VSI Figure A 10 ISA Connector T 2 c qo a t LO eo LO o a MOTOROLA 3 I H B j j 0 J g V 48053 SYOLDVAWI 9 710230 2079 veuqoy N4 ET 3 T L33HS UNS CONS 50 50 95950 Lo3roud I VIOHOLON ND 2 e 15 TD on StU444N9 NV YOLISNNOD VSI nro nro nro ml YOLIANNOI VSI SYRIA VSI e dra B de La wa HOLJ3JNNOJ nra arg e 8 583 z t2 t 5 fire MO nro nto nro aro nto nto nro e 8 20N0t LSTLOHTL k 3uvds Z SYCIOWTL E sost SNId 7915 0 1 DA e a 13 LEJ 913 82 62 TEJ 813 nro nro nro nro nro nro E davi CA 7 Nid JAV D EEA sud 5098450 e e e 55 m ma 97 ov 19 Se en 97 z n Ual 95 15 35 nro nro nro nro
6. N m un Nol 0000 5 m yl z S Bl E E Eh Sel Eel el 5 to Le LE S S gt B 2 e 5 si t i a Ly fe ES d z o 8 lt 2 8 EE EA E IRI m 5 3 8 P a lt Ble SS ES al T b lt disz a pm PAST 3AS BASt 179038 DY DOZIA YO IA lv I a mE zay 70 say env CDvH IVAN IVAH 90V MEET Ag e LY 0 2H 103829 SOM vH AS ADM 607 olay cm ia ziv RH Cm Tv EDO ETOW m 710v DOV ds te 2 139 3 TDI bavi stav S MAEE UVA pra a Vo DATA AE E 09S uu3d 3 00 3307 PAE E nq 4015 185 43 unn ONNOYD Wee Lo aS ARH Aut Qo 239 93 DIVA DOVH gor 1 ana Pannows 00 w ori ozay TDAH ceny EV ean y 39 7 d d 19901 bAEE TIR 720 520 qv GIAI 1207 I DIVA 9z v SaNNOYI szav sv on Dv 0 EV TE 6 PUN N3VH ae bannaws g ISUH xi AE AD ZINSHA DI DAE z h qAS ani uN E VINI 1AS 0 YINH DAS LL E ol z SWL dannosa g E 2 azt
7. 2 21 Expansion Connector P6 and P8 2 22 SSI AIB Goritiechor u u ur 3m me E PERDRE ELO DS LORD ED RBS 2 24 Dedicated SSI Connectors 2 25 SCI Dedicated 2 25 JTAG OnCE Connector 2 26 SRAM Memory Bank 0 A 4 DSP56305ADM User s Manual V Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 Figure A 10 Figure A 11 Figure A 12 Figure A 13 vi Fl sh MOmOb s t z lieta cq an rare ete eR Sa dire A 5 Optional SRAM Bank 1 A 6 DRAM Memory Bank s vehe E stag ed cin deen CERE as A 7 SA BUS 2 oe ot tere Lon oe Pre A E Dc Pure ilo A 8 PC ICONMGGCIOR TEPORE PN RN EN EN EV D una dud A 9 JTAG SCI SSI SSI AIB A 10 Interrupts Mode Control and Clock Supply A 11 CRU ione DIRE OE A 12 IS A QODDOCIOE 22 atrio ee ne Rese eee I EM SE eS A 13 Decoupling lt A 14 Expansions and Logic Analyzer Connectors A 15 5V 3 3V Power Regulator and Power up Reset Generator A 16 DSP56305ADM User s Manual MOTOROLA LIST OF TABLES Table 1 1 Table 2 1 Table 2 2 Table 2 3 Table 2 4 Table 2 5 Table 2 6 Table 2 7 Table 2 8 Table 2 9 Table
8. zz E 1190L E lt E 3 Bs a LI LI gt N un r MOTOROLA Figure A 6 PCI Connector DSP56305ADM User s Manual 9197530 SYOLIANNOI DS ONY SV ISS 33018 Juv DN3 ET 40 L 13348 ONS A38 SOVSOE9SdSQ LIIFOYd NN030E33 6d oE 9 9 ND e 06 SH 13534 OSH XUL 2005 2035 15 Eon ons DIS au 2005 ON 0015 1005 JN 1915 81 0005 0015 0035 560 ou 1025 0095 166 ENG 002 Das aloo 105 ON 0105 0095 8166 EOIdS Ws 1660 20199 0115 06 10139 1015 z 00199 Tous NN027124 Old Q AD 06 DIS T1166 6 2125 2125 8 L 1125 1125 100 5 0125 0725 7166 1015 1015 z I Tous 1985 NNO3924 Aeg 9 8 XUS SS 06 xs A z XIS 30 OSM H3IH3ANOJ QNVWRWOJ SWL gt 18538 H3lH3ANOJ NVINW03 Siu NNOITIS Td SRL 8 3 n EEN GGA 83183AN0J ONYWWOJ L V iji SAL 07 6 1453 QHVH H31H3ANO02 ONYWWOJ A3 7g 9 Lud S DL 00 OL 001 z 1 HL 01 Figure 7 JTAG SCI SSI
9. nro nro nro nro nro EEA e e e 9 DA en jon EEA YUOLVHAN39 5201 MY 87 WES 100090 827 lt 100090 j 215 WVHT Hed 3 I H B 3 3 J q V Figure A 11 Decoupling Capacitors DSP56305ADM User s Manual MOTOROLA A 14 I H j a J q 48534 382 SUO133NN02 NOISNYdX3 33019 9 Nyy 9N3 40 i 133HS A3H S0VS0E9SdS 1J3r0Ud Zd Sd 9d 8d Saati t3 0v3H u3av3aH U3avaH DOV 05 8 9 67 COVAVH 9 64 04 lt 05 9 9 67 we DV 05 67 DY 6 0VH 97 17 9 IVH EXIVH 87 17 00 0 DV 97 17 CIV DV 97 Li GN 40 2H 97 O O S7 60NH 97 6 Evi EEA 97 S7 EDY 97 O O S7 Vv DAVH E7 90YH ET 9
10. 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 2 DSP56305ADM Board 2 3 DSP56305ADM Features 2 3 Configuring the DSP56305 ADM 2 5 DSP56305ADM 2 8 DSP56305 Operating 5 2 12 Clock Sot IC uetus cdd DE E ERI Pa 2 14 Host Port Selection 2 17 COnle CIOES Lv ul 2 20 DSP56305ADM User s Manual MOTOROLA Technical Summary DSP56305ADM Board Architecture 2 1 DSP56305ADM BOARD ARCHITECTURE The DSP56305ADM is a versatile board that can be used as a stand alone board or as an expansion card in a host computer with ISA or PCI expansion slots and connected to other cards The DSP56305 signals power and ground connections are brought out to four 50 pin connectors for attaching additional boards or logic analyzers In addition separate connectors are provided for the on chip peripheral ports SCI SSI and JTAG OnCE A dedicated connector is provided for audio applications An overview description of the DSP56305 is also provided in the DSP56305 Product Information DSP56305P D included with this kit 2 2 DSP56305ADM FEATURES The DSP56305ADM provides the following features e DSP56305 running at 80 MHz on board socketed BGA package e 128K fast static memory one wait state access at 80 MHz 3 3V Option to add 128
11. m w c S S 1459 Figure 1 2 Jumper Configuration Back Side 1 3 2 Installing the DSP56305ADM Figure 1 3 shows the interconnection diagram for connecting a PC to the DSP56305ADM board Using the instructions in the ADS User s Manual connect the Command Converter to the DSP56305ADM board Power for the DSP56305ADM is supplied from the Command Converter module 1 8 DSP56305ADM User s Manual MOTOROLA Quick Start Guide Installation Procedure 37 pin 14 pin User Application Interface Ribbon Circuits Cable Cable Host Bus Interface Card Command Converter Host Computer E Motorola DSP DSP56305ADM Figure 1 3 Application Development 1 3 3 Installing the Software Refer to the Motorola Application Development System User s Manual for detailed instructions about installation and use of the ADS software 1 3 4 Testing the DSP56305ADM Installation Once the DSP56305ADM is installed it becomes a part of the Application Development System Refer to the Motorola Application Development System User s Manual for detailed information regarding evaluation and testing of an installed ADS system Ts MOTOROLA DSP56305ADM User s Manual 1 9 Quick Start Guide Installation Procedure 1 10 DSP56305ADM User s Manual MOTOROLA MOTOROLA SECTION 2 TECHNICAL SUMMARY Preliminary DSP56305ADM User s Manual 2 1 Technical Summary
12. 15 5 6 YIH 6 8100 nsu 16 6 6 IN JL 8 di 101 DIH 8 L SUH 02 8 L m NL 8 L svi 1095 9 S odis S DOVH 9 s EEA 9 S daa ovv 9 S 10011 Sa 7 29 lt EDQVH 4 E EOU 7 o ND EEA CND 1 ND ano 2 1 EEA MULINI 4 T wv 1 902 01 6ST SNId 9ST OL SOT SNId ZOT OL SS SNId ZS 01 SNId Figure A 12 Expansions and Logic Analyzer Connectors A 15 DSP56305ADM User s Manual MOTOROLA 1 diu3s30 AHI 4asay uo J MOd Ajddns JaMod Y20709 Jnuldv ET 0 El 133HS A38 SQV50E9 5dSQ 1930084 en 062 9 Ln Jnd C E YI m di Sta se i S0 Hi SG a n xo Wi 13539 NO Y3MOd _ ASZ 4NOL 4 u u Jon N Z NE SI Asz Jot S si LT NSU 30001 NII 9 U3MOd ET V us 990111 T SLANT BLANT SUDTND 1 4 N ZON N m ne 0 id 90 Ed 2 4nro E ELYO SIWST 7 za m Z DE a LIOZIOHA LOdNI BIMOd 1VNH31X3 ISNI DA MOTOROLA Figure A 13 5V 3 3V Power Regulat
13. Figure 2 10 Expansion Connectors P2 and P5 MOTOROLA DSP56305ADM User s Manual 2 21 Technical Summary Connectors INTRB INTRA BCLK 1 X X 2 AA1 D22 D23 V3 3 GND D21 V3 3 CLKOUT GND D20 CAS D18 D19 NMI RESET D16 D17 V3 3 V3 3 D15 V3 3 GND GND GND D14 BB BG D12 D13 BR V3 3 D10 D11 GND AA2 D9 V3 3 AAS WR GND V3 3 RD GND GND D8 V3 3 V3 3 D6 D7 GND BCLK D4 D5 AO A8 D3 V3 3 GND V3 3 GND D2 A1 A9 DO D1 A2 A10 A22 A23 GND V3 3 V3 3 V3 3 A3 A11 A20 A21 A4 A12 A18 A19 GND V3 3 A16 47g p 48 A17 A6 47pq 448 14 Figure 2 11 Expansion Connector P6 and P8 2 22 DSP56305ADM User s Manual MOTOROLA Technical Summary Connectors 2 8 2 5 V Power Connector The 5 V power connector to the DSP56305ADM is a 3 lead two part terminal block connector This two part connector provides these advantages It is easily detachable from the board and connecting wires to it does not affect the soldering quality of its receptacle to the PCB The power connector is used only when the DSP56305ADM is used in stand alone mode If it is used in stand alone mode the power switch SW1 is used to turn the DSP56305ADM on and off When installed in an ISA or PCI host this switch is bypassed and power is provided through the host interface connector 2 8 3 HI32 Connector Two HI32 connectors are provided on the DSP56305ADM a PCI edge connector configured as 32 bit universal 5 V and 3 3 V connector and an ISA edge c
14. aii SY uvdH gy bos TOUS TT TOYS TOLS Ta IUS 0995 Ed ie 98095 454 ms Tj DI 115 0115 Evi ave 2035 Ha X0E 0VH 1025 mp 6071 era 6D0YH 0025 ML LUN cm kima seh Laz DIVA SWL kaka oN DWH 00 s OVI ry OH TOL mn EVI rry EDUYH T kika MIL 30 ODIVH sg aj forg D0VH ua ups MEE DIVA 19 fay UDIVH d Da cip MM fay GD vH 89 mp SIVA pave ED VH Sw ive ML D VH uM DOVA if M IVH T EYY 9 0VH zv m PAM Ov SESS ASVII a PM VH 155 MHI WVUS oyy S IVH a TE ep ma Ma MI dot em mt wins ow ur ivi mus vt Dem IERI lt a ze jeu va sef su ulei pru TE 0 0VH 001 ONY SngstNu FEAT ELE S e Je ui Jio 9 lt 70 I H t j g V Figure A 9 CPU DSP56305ADM User s Manual A 12
15. connected to IROB IRQC and IROD lines Table 2 6 Operating Mode Selection Mode SW3 SW3 2 SW3 3 SW3 4 MODA MODB MODC MODD 0 Expanded mode ON ON ON ON 1 RTOS Mode OFF ON ON ON 2 RTOS Mode ON OFF ON ON 3 RTOS Mode OFF OFF ON ON 4 Reserved ON ON OFF ON 5 Reserved OFF ON OFF ON 6 Reserved ON OFF OFF ON 7 Reserved OFF OFF OFF ON 8 Expanded mode ON ON ON OFF 9 Bootstrap from byte wide memory OFF ON ON OFF A Bootstrap through SCI ON OFF ON OFF B Reserved OFF OFF ON OFF C Host Bootstrap PCI Mode 32 bit wide ON ON OFF OFF D Host Bootstrap 16 bit wide UB Mode OFF ON OFF OFF ISA E Host Bootstrap 8 bit wide UB Mode in ON OFF OFF OFF double strobe pin configuration F Host Bootstrap 8 bit wide UB Mode in OFF OFF OFF OFF single strobe pin configuration MOTOROLA DSP56305ADM User s Manual 2 13 Technical Summary Clock Source 2 6 CLOCK SOURCE There are three clock sources on the DSP56305ADS Low cost on board clock generator External BNC connector e Crystal oscillator Table 2 7 Clock Source Selection Jumper Settings Clock Source 8 Clock Generator 1 2 BNC Connector Crystal Oscillator fa The DSP56305ADM is configured for the on board clock generator with a DIP1
16. nsec The DRAM chips are M5M4V4800CTP 8 The maximum load capacitance of each bank is 3 x 5 15 pF address bus and 7 pF data bus The 512K DRAM is accessed by the DSP56305 with four wait states when the DSP56305 is operating with an 80 MHz clock The RAS signal to the 512K DRAM is generated using the DSP56305 AA2 RAS line The 512K DRAM connection is shown in Figure 2 5 M5M4V4800CTP M5M4V4800CTP M5M4V4800CTP AA2 RAS D 16 23 Figure 2 5 512K DRAM Connection The 512K words DRAM is enabled and disabled using jumper J1 When J1 is installed the DRAM bank is enabled When 1 is not installed the DRAM is disabled and AA2 line can be used for other purposes See Table 2 4 for DRAM jumper configuration Table 2 4 DRAM Configuration Jumper Settings DRAM Configuration JA DRAM Bank 0 Enabled 1 amp 2 DRAM Bank 0 Disabled 1 2 Note Because of increased capacitance on the data and address lines if the optional DRAM bank is mounted performance may be degraded 2 10 DSP56305ADM User s Manual MOTOROLA Technical Summary DSP56305ADM Memories 2 4 3 Flash PROM To facilitate stand alone operation of the DSP56305ADM a Flash PROM is provided The FPROM is on board programmable making it ideal for updates Use is done with a byte wide AT29LV512 3 3V only programmable eliminating the need for additional supply or a DC DC converter 200 nsec access time The low speed has no p
17. which loads executable code from the Host to the board When performed at 33 MHz the boot routine located in the Bootstrap ROM is unable to change the Multiplication Factor MF in the PLL Control Register The frequency relation of the PCI bus to the board is 3 3 and the DSP56305ADM cannot operate properly at this frequency ratio To allow operation using the PCI configure SW3 for the Flash Boot mode The code in Example 2 1 must be programmed into the Flash memory Following RESET the DSP56305 enters Flash Boot mode and loads this program from the Flash memory The program changes theDSP56305ADM s initial frequency to the desired frequency reconfigures the Operating Mode Register OMR for PCI configuration and jumps to start of the boot routine From this point the DSP56305ADM performs its usual PCI operation Example 2 1 PCI Boot Flash Program FEE EE E EE EE EE E EU E TE E E E FE EE FE EE EL GEL GG gl gg 08 g Boot from FLASH program setting Chip Frequency to 80MHz turning chip to PCI mode by jumping to PCI boot segment in bootstrap ROM receive SREC format do next gt gt gt asm56300 a b 1 bootpci asm gt gt gt srec b bootpci PLL INIT 80 EQU 750013 PLL Initialization Word 80 MHz M PCTL EQU SFFFFFD PLL Control Register PCI OP MODE EQU 00000B PCI mode configuration BOOT START EQU
18. 1 1 2 REQUIRED USER SUPPLIED EQUIPMENT 1 4 1 3 INSTALLATION PROCEDURE 1 4 1 3 1 Preparing the DSP56305ADM 1 5 1 3 2 Installing the DSP56305ADM 1 8 1 3 3 Installing the 1 9 1 3 4 Testing the DSP56305ADM Installation 1 9 SECTION 2 TECHNICAL 2 1 2 1 DSP56305ADM BOARD ARCHITECTURE 2 3 2 2 DSP56305ADM FEATURES 2 3 2 3 CONFIGURING THE DSP56305 ADM 2 5 2 4 DSP56305ADM MEMORIES 2 8 2 4 1 128K SRAM With Option for 128K SRAM 2 8 2 4 2 Optional 512K DRAM 2 10 2 4 3 Blas ila nese 2 11 2 5 DSP56305 OPERATING MODES 2 12 2 6 CLOCK SOURCE rd debi ER DR et E EROS 2 14 2 6 1 On Board Clock Generator 2 14 2 6 2 External Cook c uu sten LER LM ESSE BE 2 15 2 6 3 DSP56305 PLL Enable Disable on Reset 2 16 2 7 HOST PORT SELEGHION xx ee de gee kee RENS 2 17 2 7 1 ISA DMA and Interrupt Channel Configuration 2 17 2 7 2 PGI Operation sas os ve ot ore see bees ewe 2 19 2 8 CONNEGTORS iii ae eae REEUM es 2 20 2 8 1 Expansion and Logic Analyzer Connectors 2 20 2 8 2 5 V Power 2 23 2
19. 1 3 INSTALLATION 1 4 1 2 DSP56305ADM User s Manual MOTOROLA Quick Start Guide 1 1 OVERVIEW The Motorola Application Development System ADS is a tool used to design and test complex software applications and hardware products using a specific Motorola DSP chip The related Application Development Modules ADMs contain the DSP chip and related hardware used for bench development and test Detailed information about the content and use of the ADS is provided in the ADS User s Manual DSPADSUM AD This manual provides specific information about the DSP56305 Application Development Module DSP56305ADM This section provides a summary description of the DSP56305ADM additional requirements and quick installation information Detailed information about the DSP56305ADM design and operation is provided in the remaining sections of this manual Subsection 1 2 of this document gives a summary description of the equipment required to use the module with the Motorola ADS Subsection 1 3 describes installation instructions including Preparing the module for installation Installing the module Installing the software e Testing the installation Note Detailed information about the design and operation of the DSP56305ADM is provided in this manual in Section 2 and Appendices A and B MOTOROLA DSP56305ADM User s Manual 1 3 Quick Start Guide Required User Supplied Equipment 1 2 REQUI
20. 1 ISA DMA and Interrupt Channel Configuration The DSP56305ADM enables the user to configure one of four channels for DMA and one of four interrupt channels for the ISA bus interface Table 2 10 and Table 2 12 describe these configuration options Table 2 9 ISA Bus DMA Channel Configuration DMA Channel 5 0 80 0005 5 15 554 5 8 5 8 5 155544 6 8 eed 8 00065 1 elle4 100004 7 5 8 0 0005 1 254 100004 MOTOROLA DSP56305ADM User s Manual 2 17 Technical Summary Host Port Selection Table 2 10 ISA Bus DMA Channel Configuration 2 18 DMA Channel JA 5 0 1 8 2 7 5 3 6 4 5 6 3 6 4 5 7 1 8 2 7 Table 2 11 ISA Bus Interrupt Selection Interrupt J6 5 155052 6 7 10 Table 2 12 ISA Bus Interrupt Selection Interrupt Je 5 3 6 6 2 7 7 1 8 10 4 5 DSP56305ADM User s Manual MOTOROLA Technical Summary Host Port Selection 2 7 2 PCI Operation The PCI bus is designed to operate with boards at a 3 5 frequency relationship The standard PCI bus operates at 33 MHz so the DSP56305ADM is configured to operate at 55 MHz The DSP56305 begins its boot routine after reset
21. 2 10 Table 2 11 Table 2 12 Table A 1 Table B 1 MOTOROLA DSP56305ADM Default Switch Jumper Options 1 6 DSP56305 Card Default Switch Jumper Options 2 5 DSP56305ADM Memories 2 8 SRAM Configuration Jumper 5 5 2 9 DRAM Configuration Jumper 5 2 10 Flash PROM Configuration Jumper Settings 2 11 Operating Mode Selection 2 13 Clock Source Selection Jumper Settings 2 14 PLL Configuration Jumper 5 5 2 16 ISA Bus DMA Channel Configuration 2 17 ISA Bus DMA Channel Configuration 2 18 ISA Bus Interrupt 2 18 ISA Bus Interrupt 2 18 Listo Schematics vus eve Leod du aco eer pear nee qos A 3 Bilkor Materials sr safe 28 B 3 DSP56305ADM User s Manual vii viii DSP56305ADM User s Manual MOTOROLA Example 2 1 MOTOROLA LIST OF EXAMPLES PCI Boot Flash DSP56305ADM User s Manual DSP56305ADM User s Manual MOTOROLA MOTOROLA SECTION 1 QUICK START GUIDE DSP56305ADM User s Manual Quick Start Guide OVERVIEW TJ OVERVIEW A be 1 3 1 2 REQUIRED USER SUPPLIED EQUIPMENT 1 4
22. 4 package 33 0 MEZ 3 3 V clock generator and a jumper linking JP8 pins 1 8 It is recommended that when the on board clock generator is used or when an external clock is provided through the BNC connector the XTLD and COD bits in the PLL Control Register PCTL should be set This helps avoid unnecessary on board RFI 2 6 1 On Board Clock Generator The clock generator U17 is mounted in a socket allowing frequency selection by replacing the clock generator The user may replace the clock generator with a generator of a different frequency The PCB layout is designed such that it will accept both 14 pin and 8 pin DIP packages for the clock generator socket The DSP56305ADM supports both 8 pin and 14 pin 3 3 V clock generator modules Locate the clock generator in the socket as shown inFigure 2 8 2 14 DSP56305ADM User s Manual MOTOROLA Technical Summary Clock Source 14 13 12 11 10 9 8 8 7 6 5 U17 s 14 pin DIP package I 8 pin DIP package 1 2 3 4 1 2 3 4 5 6 7 Figure 2 8 U17 Socket Layout for 14 Pin and 8 Pin DIP Packages Note The clock generator must be 3 3 V type To select the on board clock generator JP8 should be jumpered from pin 1 to pin 8 The clock generator supplied with the DSP56305ADM is a 33 MHz oscillator in a 14 pin DIP package 2 6 2 External Clock To support non standard clock rates and frequency fine tuning an external clock input via a BNC connector is furnished Using this conn
23. 42 C50 C26 C41 C49 Co 025 35 C46 C56 R16 C19 C40 C4 C34 C45 C57 C23 C54 m 5 S lo FR2 a FRI 8 N C39 2g C29 C33 s u3 C38 ABCDEFGHJKLMNPR 5 C44 C18 3 4 5 5 s 7 8 E R15 s a 19 C47 x c53 x cie 13 a mm E c37 cag C32 C36 C13 F S ph 2 52 C15 E R13 8 im R11 C24 C14 C31 C55 R10 C22 R12 8 C30 us e ES ins 5 Figure 2 3 DSP56305ADM Bottom of Board DSP56305ADM User s Manual 2 7 Technical Summary DSP56305ADM Memories 2 4 DSP56305ADM MEMORIES Table 2 2 DSP56305ADM Memories Type Size Speed Voltage AA Line On Board SRAM 128K word 24 bit 10 ns 3 3V AAO Constant SRAM 128K word 24 bit 10 ns 3 3V AA3 Optional DRAM 512K word 24 bit 80 ns 39V AA2 Optional Flash 64K byte 200 ns 3 3V AAT On Socket Note The first bank of SRAM and the Flash PROM are supplied as standard with the DSP56305ADM The second SRAM bank and the DRAM are not included All circuitry and associated components decoupling capacitors jumpers etc are provided with solder pads for mounting the optional SRAM and DRAM chips if desired 2 4 1 128K SRAM With Option for 128K SRAM The SRAM on the DSP56305ADM is composed of a single bank of three chips of 128K x 8 SRAM providing 128K words of 24 bit memory These chips are MCM6926WJ10 a 3 3 v BiCMOS device with an access time of 10 nsec The maximum load c
24. 8 3 AISA CONMECIO a citi ad eed he ea e nati 2 23 2 8 4 SSI Port Connectors 2 23 2 8 5 SCI Port 2 25 2 8 6 JTAG OnCE 2 26 MOTOROLA DSP56305ADM User s Manual iii APPENDIX A DSP56305 SCHEMATICS A 1 SCHEMATICS APPENDIX B DSP56305 BILL OF MATERIALS B 1 BILL OF MATERIALS DSP56305ADM User s Manual MOTOROLA Figure 1 1 Figure 1 2 Figure 1 3 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure A 1 MOTOROLA LIST OF FIGURES Jumper Configuration Front Side 1 7 Jumper Configuration Back Side 1 8 Application Development 1 9 DSP56305ADM Block 2 4 DSP56305ADM Top of 2 6 DSP56305ADM Bottom of Board 2 7 128K SRAM Connection 2 9 512K DRAM Connection 2 10 Flash PROM Connection 2 11 DSP Mode Selection Block Diagram 2 12 U17 Socket Layout for 14 Pin and 8 Pin DIP Packages 2 15 BN Selection RP 2 16 Expansion Connectors and P5
25. AA Address Attribute lines are used There is a variety of jumpers options for various memories configuration to enable disable each of the memory types on the DSP56305ADM Expansion and Logic Analyzer Connectors 64K Byte Flash PROM 3 3V Mode select AT29LV512 128K word 24 DSP56305 Static RAM MCM6926WJ10 x 3 Port A HI32 Port _ 128 WORD 24 SCI Port RR Static RAM MCM6926WJ10 x 3 SSI Ports i Optional not included OnCE Port 512K WORD 24 Dynamic RAM M4V4800CTP 8 x 3 Optional not included 5V to 3 3V OnCE Port voltage and JTAG regulator ISA Edge Connector PCI Edge Connector SSIO SSI1 Ports and AIB Interface SCI Port Figure 2 1 DSP56305ADM Block Diagram 2 4 DSP56305ADM User s Manual MOTOROLA Technical Summary Configuring the DSP56305 ADM 2 3 CONFIGURING THE DSP56305 ADM Figure 1 1 and Figure 1 2 on page 1 8 show the physical locations of jumpers on the DSP56305ADM Table 2 1 describes the default factory configuration for the DSP56305ADM jumper groups Table 2 1 DSP56305 Card Default Switch Jumper Options Group Default Option Comment Removed Disables 512K words optional DRAM memory J2 Removed Disables 128K words optional SRAM memory J3 Mounted Enables 128K words SRAM memory J4 J5 J4 no jumpers Sets ISA DMA channel 5 selected J5 3 6 4 5 J6 4 5 Sets ISA Interrupt channel 10 JP7 Removed Disables Flash mem
26. DSP56305ADM User s Manual Motorola Incorporated Semiconductor Products Sector 6501 William Cannon Drive West Austin TX 78735 8598 This document and other documents can be viewed on the World Wide Web at http www motorola dsp com This manual is one of a set of three documents You need the following manuals to have complete product information Family Manual User s Manual and Technical Data OnCE is a trademark of Motorola Inc MOTOROLA INC 1998 Order this document by D56305ADMUM D Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not authorized for use as components in life support devices or systems intended for surgical implant into the body or intended to support or sustain life Buyer agrees to notify Motorola of any such intended end use whereupon Motorola shall determine availability and suitability of its product or products for the use intended Motorola and are registered trademarks of Motorola Inc Motorola Inc is an Equal Employment Opportunity Affirmative Action Employer ii DSP56305ADM User s Manual MOTOROLA TABLE OF CONTENTS SECTION 1 QUICK START 1
27. E connector is used both for JTAG testing during production and for OnCE functions for code debugging and software development The pinout of the JTAG OnCE dedicated connector is shown in Figure 2 15 on page 2 26 2 26 TDI GND TDO GND TCK GND N C KEY ORST TMS 3 3V N C DE TRES Figure 2 15 JTAG OnCE Connector DSP56305ADM User s Manual MOTOROLA MOTOROLA APPENDIX A DSP56305 SCHEMATICS DSP56305ADM User s Manual A 1 DSP56305 Schematics A 1 SGHEMATIGS 5 aiat eat es owe eee ee eed ae ace A 3 A 2 DSP56305ADM User s Manual MOTOROLA DSP56305 Schematics 1 SCHEMATICS Table A 1 provides a list of the schematics included in this appendix Table A 1 List of Schematics Figure Figure Name Page Figure A 1 SRAM Memory Bank 0 A 4 Figure A 2 Flash Memory A 5 Figure A 3 Optional SRAM Bank 1 A 6 Figure A 4 DRAM Memory Bank A 7 Figure A 5 ISA Bus Buffers A 8 Figure A 6 PCI Connector A 9 Figure A 7 JTAG SCI SSI SSI AIB Connectors A 10 Figure A 8 Interrupts Mode Control and Clock Supply A 11 Figure A 9 CPU A 12 Figure A 10 ISA Connector A 13 Figure A 11 Decoupling Capacitors A 14 Figure A 12 Expansions and Logic Analyzer Connectors A 15 Figure A 13 5V 3 3V Power Regulator and Power up Reset Generator A 16 MOTOROLA DSP56305ADM User s Manual A 3
28. K fast static memory 1 wait state access at 80 MHz 3 3V Option to add 512K dynamic memory 4 15 wait state access at 80 MHz 3 3V e 64K Byte Flash PROM on board 3 3V programmable e ISA EISA bus compatible edge connector slave only operation e PCI bus compatible edge connector master and slave operation e Stand alone or computer plug in card operation Integrated expansion and logic analyzer connectors e Dedicated SSI ports connectors e Dedicated SCI port connector JTAG OnCE port connector e 5V operation with on board 3 3 V voltage regulation Note Call your local Motorola sale office or distributor for additional information about the Motorola DSP Application Development System ADS kit The ADS kit includes two additional boards a Host Interface Card and an external Universal Command Converter The Host Interface Card plugs into the bus on an IBM PC compatible HP7xx workstation or Sun Sun compatible system in the computer case The Host Interface Card is connected via a 37 way ribbon cable to an external Universal Command Converter which is then connected via a 14 way ribbon cable and the JTAG OnCE port to the DSP56305ADM The ADS is compatible only with Motorola software tools MOTOROLA DSP56305ADM User s Manual 2 3 Technical Summary DSP56305ADM Features Figure 2 1 shows the DSP56305ADM architecture To achieve the best memory performance no memory decoding is performed outside the DSP56305 chip and the
29. Manual DSP56305UM D and the DSP56300 Family Manual DSP56300FM D During reset the DSP56305 interrupt signals IROA IROD are also used as the Mode Select signals MODA MODD The DSP56305ADMuses SW3 to select the mode entered on exit from reset Table 2 6 lists the available modes Multiplexor U13 selects the signals presented on the DSP signals IROA MODA IROD MODD During reset the RESET signal is asserted the values selected on SW3 are passed to the DSP56305 The MODx signals are pulled high closing a switch in SW3 pulls the corresponding MODx signal low These values are sampled by the DSP56305 on the rising edge of RESET and moved to the Operating Mode Register OMR This determines the mode in which the DSP56305 exits reset During normal operation RESET deasserted U13 passes the interrupt signals INTRA INTRD to the DSP56305 as IROA IROD To Interrupts of DSP56305 3 3 V Figure 2 7 DSP Mode Selection Block Diagram 2 12 DSP56305ADM User s Manual MOTOROLA Technical Summary DSP56305 Operating Modes Support is provided to enable DSP56305 to enter to all available modes via MODA MODD IRQD and NMI PINIT lines These lines are sampled by the DSP56305 on the rising edge of the RESET signal The sampled combination is moved to the Operating Mode Register OMR After RESET is deasserted the mode selection lines are released driven by pull up resistors and the IRQ signals are
30. QWH DV 17 EY Dv EEA E7 QNS zu DE ND lt SZ 0VH a 15 Gov zu 15 Ov 17 15 EEA 07 6 EXIVH 07 6E EOQVH EEA 07 6 SE DV 07 6E v YH Oo LE DOVH VOYH 9E lo LE OUVH EDY LE OW EEA 9E LE NS vH 9E SE 201 P 02 0 9 SE EEA Da JE SE od DV 3E 5E OV s 001 wo 16 t 600 o w o GL Li v oo OY Xus ZE 00 MIS XL DOVH 8DQVH EEA ZE Oo EEA CE TE ND EEA 0 00 62 ND 9DOVH DE 62 90 0E 6C eng Vv 62 OV WLNIH gz LZ EEA UH 82 LZ AQuiH gz LC Da xn gz 12 ND ND 9c 52 XIS 92 5e INS a 92 SZ N EEA 9c 52 EEA 0195 p 74 EZ TS 3AvudH C EZ EEA C EZ N NS EZ qu 1015 e 1 1025 EEA 44 M4 QNS EEA e 2 ex YM O EVV DIS 02 6T 0055 33SA30H oz 6T dvn apa 02 6T ona 97 61 QNS TOUS 81 LT DIS OH 9T LT MIO EDO 9r LT EEA 81 LT us EEA 91 E ND 4 9T ST DUIH 9r ST m DI 91 En 44 Saul T Oo T 0015 NS T EEA O ND QNS e TE 2035 uvdH e TE 1 0 ze EEA IL EEA 6 SRL wv
31. RED USER SUPPLIED EQUIPMENT The following section gives a brief summary of the equipment required to use the DSP56305 Application Development Module DSP56305ADM some of which will be supplied with the module and some of which must be supplied by the user For use with the Motorola ADS and the appropriate interface card the user must supply one of the following host computer systems e PC compatible computer 486 class or higher with MS DOS version 6 0 or later Windows 3 1 or later or Windows 95 Minimum 8 Mbytes RAM One open 16 bit ISA expansion slot One bank of free I O addresses in the range of 100 102 200 202 or 300 303 no IRQ is required CD ROM drive Hard drive with 4 Mbytes of free disk space Mouse e Sun Microsystems Sun 4 Workstation running Sun Operating System Release 4 1 1 or later or Solaris Release 2 5 or later one open SBus expansion slot a CD ROM drive and a mouse e Hewlett Packard HP7xx Workstation running HPUX Version 9 x Version 10 x is not supported one open EISA expansion slot a CD ROM drive and a mouse 1 3 INSTALLATION PROCEDURE Installation requires the following steps Preparing the DSP56305ADM board Installing the module Installing the software pee qe ms Testing the installation 1 4 DSP56305ADM User s Manual MOTOROLA Quick Start Guide Installation Procedure 1 3 1 Preparing the DSP56305ADM CAUTION Because all electronic components are s
32. SSI AIB Connectors DSP56305ADM User s Manual MOTOROLA A 10 dit2s30 123788 300A LINI NV 0070 30019 unu 40 8 133HS DONI Aad 50 50895951 LIarotd tos 4 YIOHOLOM sos INg BHF rer ct woe til 2 WIX siet Sar A S3D9V3DVd 10 NIdYT ONY did Nid8 SLAJDY unl MT 137005 HI RS 137005 Hl OWS TA M 4 Ld NUVIX 3508 HI RS 137005 WS ATX 10S Wl 045 en lt j zu 505191 o dA 51 OTH Tu TINIXIM EZ EEA 01 NJ z Ese SIE INF t CAE L zat 0012991 lt AINId 0 lt 6 VI e in 1145 m t issus 0012991 m s 13538 B 135394 5 9 MINX 7 SOSTHL dI oue P lt Fu LSTLIVYL 4 lt 19599 9 Na ML GOSTIL in t 1353 d 2s Tu VIT EEA EEA EMS A Es dn gm Ult EQ EN oL W Fo l SOUL a E 30H n 97v WI 2041 e YOON a 8 NW Sour A vs n 71595 v
33. Sff0000 Starting address of bootstrap code PRR RRR RRR k k k K k Yk k K K KOK KOK KOR KKK KEK KOK KK KKK KK ck kck ck kckck ck ckck ck kck ck ck ck k ck kckckckckck ck ck ck ckckckckckck kckck First two words in FLASH Program size and Load Run start address E RS RARER RRA AERA SE RS ARENAS RAE RRS RR RS ee org p 0 p 0 dc 120 The size of program dc 000 Address in internal p memory to load program from flash and start to run MOTOROLA DSP56305ADM User s Manual 2 19 Technical Summary Connectors Example 2 1 PCI Boot Flash Program FEAR oi ERK SR RRS RR AS RH dece de OR ge RN AR oe ee soe Main Program FR K k isk AER ESR AES RETE OK e X bo oo K KUK KC RON ROB ooo RE ERRATE ERA S RES e o ESE org p 0 p PERERA ERE SS ERE CONGR SRR SBR RE GAR are voe ee ovo ge eae wo vale deo COR KORR SON NOR ONU I QUON OR eR oce Initialize PLL LRA REAR SRLS eof b OO s Ge e KA So vob ovo oec X REKER KEE EEEE GRON SEG Ke Ao Oeo eoo ck Ck k k k ck k k k k ck k k x ck ck Ck k ck Ck ck ck ck ck x ck ck ck ck k k ck Ck ck ck k lt ck k k x ck Ck ck k k k lt ck ck k k lt K ck lt k x K lt ck k ck ko Sk ck k k k x ko ko ko movep PLL_INIT_80 x M PCTL Activate PLL move omr a and SFFFFFO a or PCI_OP_MODE a set PCI mode move a omr jmp START go to the bootstrap code beginning 2 8 CONNECTORS The DSP56305ADM prov
34. UNHLUY ONG EL 40 5 AY NOGNIMS 0 7 0 95450 LIArotid siu EEA sin Ldr E amp sad SW PIE qu TE un mie EN 8 IN DV E DY ey E 00 Z ow wl v wd W a oye n DA oc sa DV X S wE Vv ena deg wE ev Od ES v 01 si to wb DV DI TH og ov 00 ET TI V 331dZ1SA16z1V Figure A 2 Flash Memory DSP56305ADM User s Manual MOTOROLA 447530 MIZI WHS 33018 HINAVE 40 E 133HS ONS AY savsvessdsd 103 0 un lt l z00 57 THUS a a a 5 5 5 sn gz 87 87 qu n E 907 MA GDY a ri Gui RA pO GIV LO GIN x GV z CN wi EEA a Y XEDV ry V try CN DI Ld ong EN nd lo Gov 01081 Gov g EN gy SE DV e co Dy Hog gy Dy 000 ing QN Gul ogg OY OO ing gy 0 ov oar dea ye Gv ena o LE v py v LEN gy 8 T UN m 5099 OD ME GN Qu to ey SE GN un
35. a L LIE Ll WE OY mo OY DI 3 NENNT Gx 3 NES ev 9 Wi ev me OY il v a OY OV wi OY WE OY NE Dv owe Dv dt pv 7 Ov 7 7 IL6IMIN 9269094 IL6IMIW TOY Figure A 3 Optional SRAM Bank 1 MOTOROLA DSP56305ADM User s Manual 87530 YHJ SUq 3 UU03 33018 veugpy ny 1 ON v 13395 C A38 savsocssusad 130d Ezod SJANUO AAA sv p m en MOT M M L L L EEA 30 72 Um EEA sva sva soc VIE STE d 6 OY 6 V sa 6 n mE 9Y i v n 2d LZ 90 EV 6t NV Gnd 90 Iv 61 GN ux 14 90 sv 6L an 9t lt q sy LSE Qv P e Lo DY OM Z sy mat pa yy Lt GV Lil py Lt Ov ex Em Pm 000 Z cc cv t nv DI id ET env en Z ce ey 2E or aia zy LE v 27 zy l v I 5 27 zv 01 w OV ona 10 1 ov 20 iw LEE vu El oc ov DV 00 00 ov LEE v OT El og oy HE z oT Wy x oT OV x 2 or 0097 A 7WSIA 0084 A7WSW 0084A7WSW Figure A 4 DRAM Memory Bank DSP56305ADM User s Manual MOTOROLA
36. al SRAM disabled J3 Jumpered 128K words SRAM enabled J4 J5 J4 Removed ISA DMA channel 5 selected J5 3 6 4 5 J6 4 5 ISA Interrupt channel 10 selected JP1 1 2 ISA clamp protection is set JP2 Removed DSP PLL enabled JP3 JP4 JP5 JP6 Removed ISA host interface enabled 7 Removed Flash memory disabled JP8 located on 1 8 Sets clock source to clock generator bottom of board SW3 SW3 2 ON Bootstraps from Host ISA SW3 1 3 4 OFF 1 6 DSP56305ADM User s Manual MOTOROLA 321 P wi ERE Cm JP1 JP4 D m 5V GND ANI DSP56305 Quick Start Guide Installation Procedure Jumpered I Not jumpered MOTOROLA DSP56305ADM User s Manual Figure 1 1 Jumper Configuration Front Side 1 7 Quick Start Guide Installation Procedure IVI RNS 1 498 528 Cez amp C_ 809 3 9 3 gr p s D
37. anual B 3 DSP56305 Bill of Materials Table B 1 Bill of Materials Continued Reference Value Description MSIL Cat No Total P10 FC14CONN 028 00149 1 P11 remove pin 8 FC14CONN 028 00149 1 R1 R10 R11 1 VRES 006 00257 3 R2 68 Q VRES 006 00288 1 R3 2430 VRES 006 00215 1 R4 R12 IMQ VRES 006 00249 2 R5 R7 R8 RY R13 R16 10K VRES 006 00188 6 R6 510 VRES 006 00221 1 R15 3 9 10 VRES 006 00297 1 R14 200KQ 10 VRES 006 00298 1 RN1 10KQ RN8 VCC 051 00003 1 RN2 on socket 10K Q RN8 VCC 051 00003 1 009 00027 RN5 10K Q RN14BUS 051 00046 1 RN3 on socket 1KQ RN8 VCC 051 00014 1 009 00027 RN4 1K Q RN9 VCC 051 1 RN6 4700 RN14BUS 051 00036 1 SW1 Power On Off 040 00032 1 SW2 Reset push button 040 00034 1 SW3 SPST4 040 00026 1 U1 74HCT00 051 74HCTOOAD 1 U2 74LS05 051 74LS05D 1 U3 on 256 pin BGA DSP56305BGA 051 1 socket U4 U10 U13 M5M4V4800 3 U5 U11 U14 MCM6926 3 U6 U12 U15 MCM6926 3 U7 U19 74ACT157 051 74ACT157AD 2 U8 LT1086 051 LT1086CM 1 U9 MC1455 051 MC1455D 1 U16 on socket AT29LV512PLCC 051 009 00259 1 B 4 DSP56305ADM User s Manual MOTOROLA DSP56305 Bill of Materials Table B 1 Bill of Materials Continued Reference Value Description MSIL Cat No Total U17 on socket 33 MHz CLK GEN 3V 8 14 009 00262 1 pin U18 U20 U22 on soc
38. apacitance of each bank is 3 x 6 pF 18 pF address bus and 8 pF data bus The 128K SRAM is accessed by the DSP56305 with one wait state when the DSP operates with an 80 MHz clock Although devices with 12 ns access time are adequate for 80 MHz operation a 10 ns device is used to enable operation at 100 MHz The chip select to the onboard SRAM is generated using the DSP56305 AAO line The AA3 line selects the optional 128K block The 128K SRAM connection is shown in Figure 2 4 SRAM bank 0 comprises a single bank of 3 chips of 128k X 8 3 3 V devices providing 128k 24 bit words The chips used are Motorola MCM6926W 10 This is a BiCMOS SRAM 128k x 8 3 3 V only device with an access time of 10 nS The maximum load capacitance of each bank is 3 x 6 pf 18 pF address bus and 8 pF data bus The SRAM is accessed by the DSP56305 with 1 wait state when the DSP operates at 80 MHz clock Although devices with 12 nS access time are acceptable for 80 MHz operation the 10 nS device permits 1 wait state operation with 100 MHz versions of the DSP56305 The chip select to SRAM bank 0 is generated using the DSP56305 signal AAO The power supply to the MCM6926W 10 is 3 3 V SOJ packages are used Schematic detail of SRAM connections is shown in Figure 2 4 2 8 DSP56305ADM User s Manual MOTOROLA Technical Summary DSP56305ADM Memories Space is provided to mount an additional 128 k words of SRAM as bank 1 Specifications and connection are ident
39. ector an external 3 3 V clock generator 50 ohm impedance DC coupled may be connected to the DSP56305ADM To avoid damage to the DSP the external clock should be applied before the DSP56305ADM is powered on and should be removed after the DSP56305ADM is powered off CAUTION To avoid damage to the DSP56305 chip ensure the DSP56305ADM is powered off when connecting or removing the external clock To select the external clock generator JP8 should be jumpered from pin 3 to pin 6 MOTOROLA DSP56305ADM User s Manual 2 15 Technical Summary Clock Source 2 6 3 DSP56305 PLL Enable Disable on Reset The DSP56305 samples the PINIT NMI line on exit from the reset state to determine whether the PLL should be enabled or disabled To enable the PLL JP2 should not be jumpered To disable the PLL install a jumper on JP2 The principles of NMI Request and PLL INIT selection are shown in Figure 2 9 See Table 2 8 Table 2 8 PLL Configuration Jumper Settings Initial PLL Configuration JP2 PLL Enabled 1 2 PLL Disabled 16092 During reset RESET asserted the level selected by JP2 is passed to the DSP by multiplexor U7 This level on NMI PINIT is sampled by the DSP on the rising edge of RESET and latched into the PEN bit of the PLL control register During normal operation RESET deasserted multiplexor U7 passes the NMI signal to the DSP See Figure 2 9 NMI Req
40. ensitive to the effects of electrostatic discharge ESD damage correct procedures should be used when handling all components in this kit and inside the supporting personal computer Use the following procedures to minimize the likelihood of damage due to ESD Always handle all static sensitive components only in a protected area preferably a lab with conductive anti static flooring and bench surfaces Always use grounded wrist straps when handling sensitive components Never remove components from anti static packaging until required for installation Always transport sensitive components in anti static packaging This procedure describes configuring the DSP56305ADM board for use with its ISA bus interface The board is factory configured as plug in card for ISA bus operation Refer to Host Port Selection on page 2 17 for other configurations Locate the jumper blocks on the DSP56305ADM board as shown in Figure 1 1 and Figure 1 2 on page 1 8 Verify their settings as shown in Table 1 1 on page 1 6 See the technical summary in Section 2 of this manual for additional information about the DSP56305ADM board and its components MOTOROLA DSP56305ADM User s Manual 1 5 Quick Start Guide Installation Procedure Table 1 1 DSP56305ADM Default Switch Jumper Options Group Default Option Comment JA Removed 512K words optional DRAM disabled J2 Removed 128K words option
41. erformance implications here since the program is copied by the DSP56305 byte by byte to its internal memory and run from there The load capacitance of this chip is 6 pF on the address lines and 12 pF maximum on the data lines The flash memory can tolerate as many as 1000 program cycles per sector Each sector is 128 bytes for a total of 512 sectors The AT29LV512 has a low power write protect against inadvertent write during power transitions It also features data polling during programming to shorten programming cycles All actions to the device are controlled via a sequence of commands except Read state which the device enters after power up written to the device The Flash PROM is connected to Port A of the DSP56305 as shown in Figure 2 6 AT29LV512 Figure 2 6 Flash PROM Connection The Flash memory is enabled and disabled using jumper JP7 When JP7 is installed the Flash memory is enabled When JP7 is removed the Flash is disabled and the AA1 line can be used for other purposes Table 2 5 Flash PROM Configuration Jumper Settings Flash PROM Configuration JP7 Flash PROM Enabled 1 amp 2 Flash PROM Disabled 1 2 MOTOROLA DSP56305ADM User s Manual 2 11 Technical Summary DSP56305 Operating Modes 2 5 DSP56305 OPERATING MODES All of the operating modes provided on the DSP56305 can be accessed on the DSP56305ADM For detailed information on the se modes please see the DSP56305 User s
42. ical to bank 0 except AA3 provides chip select for bank 1 Jumper J3 controls SRAM bank 0 and jumper J2 controls optional SRAM bank 1 When the jumper is inserted the SRAM bank is enabled and the appropriate Address Attribute signal is used as Chip Select When the jumper is removed the SRAM bank is disabled and the Address Attribute signal can be used for other purposes MCM6926WJ10 MCM6926WJ10 MCM6926WJ10 AAO Bank 0 AA3 Bank 1 RD D 16 23 Figure 2 4 128K SRAM Connection The 128K SRAM is enabled and disabled using jumper J3 J2 is used to enable and disable the optional bank When the appropriate jumper is installed its corresponding bank of SRAM is enabled When the jumper is not installed the SRAM is disabled and the AA0 line or the AA3 line for the optional SRAM bank can be used for other purposes Note Because of increased capacitance on the data and address lines if the optional SRAM bank is mounted performance may be degraded Table 2 3 SRAM Configuration Jumper Settings SRAM Configuration Ja J2 SRAM Bank 0 Enabled 1 2 SRAM Bank 0 Disabled 10 2 SRAM Bank 1 Enabled 16392 SRAM Bank 1 Disabled 1 2 MOTOROLA DSP56305ADM User s Manual 2 9 Technical Summary DSP56305ADM Memories 2 4 2 Optional 512K DRAM The 512K DRAM on the DSP56305ADM is composed of a single bank of three chips of 512K x 8 3 3V withan access time of 80
43. ides the following connectors e Expansion and logic analyzer connectors 8 x 25 pin SMD pin rows Power 3 pin terminal block two part HI32 port ISA and PCI edge connectors e SSII F Two connectors 2 x 7 and 2 x 15 SMD pin rows JTAG OnCE port connector 2 x 7 SMD pin rows 2 8 1 Expansion and Logic Analyzer Connectors To support hardware expansion and logic analyzer connection to the DSP56305ADM a set of four dual in line 50 pin SMD connectors is provided All the DSP56305 pins are routed to these connector In addition contains 3 3 v and GND pins are provided to facilitate hardware expansions powered by the DSP56305ADM These connectors are connected to most of the pins of the DSP56305 chip The signals that are not provided on these connectors are PCAP XTAL EXTAL MODA MODB MODC MODD and PINIT The pinout of these four connectors is shown in Figure 2 10 on page 2 21 and Figure 2 11 on page 2 22 2 20 DSP56305ADM User s Manual MOTOROLA Technical Summary Connectors GND V3 3 GND BL HAD12 HAD13 STDO HAD14 HAD15 THI HRST HC1 TMS HCLK HAEN ee HREQ HPAR SC00 V3 3 GND GND HIRQ HWR SCKO HLOCK HDRQ SRDO CLAMP HDEVSEL SC21 GND V3 3 SC11 HTRDY HFRAME STX GND V3 3 V3 3 HIRDY HRD one HC2 HAD16 SCLK HAD18 HAD17 TIO0 HAD19 GND TIO2 V3 3 HAD20 HADI HAD21 HAD22 HAD HAD23 HC3 GND HAD24 41 442 HAD25 HADS HAD26 43 444 HAD27 HAD HAD28 4554 46 HAD29 HAD8 HAD30 4704 X 48 HAD31 P5
44. ket 7AHCT244 051 74HCT244 3 009 00290 U21 U23 on socket 74HCT245 051 74HCT245 2 009 00290 Y1 32 768 kHz Crystal Oscillator 051 1 Note not solder ES MOTOROLA DSP56305ADM User s Manual B 5 DSP56305 Bill of Materials B 6 DSP56305ADM User s Manual MOTOROLA
45. od D n QN TNT wu JUIN SUINI SUINI z ein ETH qup TH 6H 84 LY 9H su rH EH ZH SnaviNu EEA ah SN Figure A 8 Interrupts Mode Control and Clock Supply A 11 DSP56305ADM User s Manual MOTOROLA H 99530 MHI SNOLLJ3NNO2 33019 vaugoy JnujJv INI MOTOROLA 13348 AJH S0VS0E9SdSU LIAFOHd i 2 00 2929292922292 INI V IOuOLOW SISISISISISISIRIGIRIGISIEISISISISISISISIE RIES NH 6 En wel de Hone 169040 SURSEEZEEZEZEEE2 s OTH 64 8H PETERET TUUS IH TRE DAS zi dVJd Iu EE Tig Id sg Mia 7717 13534 MIX eap voe NON 3g norm PURE VINH Dd 9 Lum ISH 39 D 1548 YE gm 7 Sim INYA VOS ims 5 3g qui Xus mo AUH ku YMH XIS ery OHH 034 57 TH 201 nl NaVH TOLL mpm SEEN 001 kuka
46. onnector These connectors are located on opposite sides of the DSP56305ADM enabling its operation in ISA EISA and PCI systems The PCI edge connector is keyed with both 5 v and 3 3 v keys to allow operation in both 5 V and 3 3 V PCI systems 2 8 4 SSI Port Connectors The SSI port pins are provided on three different connectors The Expansion and Logic Analyzer connectors Two dedicated SSI ports connectors e DSP56004AIB compatible connector The pins multiplication is to ease the connection of the SSI pins to various applications The dedicated connectors are for general purpose use to be connected via a flat cable to another board To avoid cross talk and to supply a constant impedance path for the ongoing signals GND lines are inserted between the signal lines To avoid incorrect insertion of the receptacle connector keying is provided as one of the pins is cut and its corresponding hole in the receptacle connector is filled MOTOROLA DSP56305ADM User s Manual 2 23 Technical Summary Connectors The AIB interface connector supports the DSP56004AIB Audio Interface Board which is a high quality audio board with 2 stereo 18 bit ADCs and 3 stereo 18 bit DACs originated for the DSP56004 The pinout of the independent SSI connectors and the AIB connector is shown in Figure 2 13 on page 2 25 and in Figure 2 12 on page 2 24 On the last figure the most left column contains the AIB connector signals names while the second to the lef
47. or and Power up Reset Generator DSP56305ADM User s Manual A 16 APPENDIX B DSP56305 BILL OF MATERIALS MOTOROLA DSP56305ADM User s Manual B 1 DSP56305 Bill of Materials B 1 BILL OP MATERIALS su retention ici cei B 3 B 2 DSP56305ADM User s Manual MOTOROLA DSP56305 Bill of Materials B 1 BILL OF MATERIALS Table B 1 Bill of Materials Reference Value Description MSIL Cat No Total C1 C2 C4 C6 C8 C10 0 1 uF VCAP 021 00064 51 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C24 C35 C36 C37 C38 C40 C41 C42 C43 C45 C46 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C3 100 uF 10 v DPCAP 023 00038 1 C5 C39 10 uF 20 v DPCAP 023 00027 2 C7 0 47 uF VCAP 021 00102 1 C9 390 pF VCAP 021 00089 1 C44 C47 22 pF 2096 VCAP 021 00077 2 D1 D4 D5 D6 D7 1N4148 048 LL1N4148 5 D2 MBRD640CT 048 MBRD640CT 1 D3 1SMC5 0AT3 R1SDIO 048 1SMC5 0AT3 1 F1 on socket 5A Fuse 065 00025 1 015 00014 FR1 FR2 Ferrite 024 00013 2 J1 J2 J3 JP2 JP3 JP4 JMP2P 009 00165 JP5 JP6 JP7 JA J5 J6 JH8 028 00148 3 JP8 JH8 009 00297 1 JP1 JMP3P 009 00165 1 LD1 yellow LED 048 01003 1 LD2 green LED 048 01001 1 P2 P5 P6 P8 Header long FC50CONN 028 00136 4 pins P3 PWR3 009 00213 1 P4 FC6CONN 028 00147 1 P7 BNC 009 00287 1 P9 FC30CONN 028 00143 1 MOTOROLA DSP56305ADM User s M
48. ory JP3 JP4 JP5 JP6 Mounted Enables ISA host interface 1 2 Sets ISA clamp protection JP2 Removed Enables DSP PLL to run 8 located on back 1 8 Selects clock source to clock generator SW3 SW3 2 ON Bootstraps from host ISA bus SW3 1 3 4 OFF Figure 2 2 on page 2 6 shows the component placement on the front of the DSP56305ADM Figure 2 3 on page 2 7 shows the component placement on the back of the DSP56305ADM Note The board is factory configured as plug in card for ISA bus operation Refer to Host Port Selection on page 2 17 for other configurations MOTOROLA DSP56305ADM User s Manual 2 5 Zh k 2 ds 39019 1X3 d ar aw 8 83 Su zhs 42 id 6n zar 4n 3 Z NY zn p 8 Configuring the DSP56305 ADM Technical Summary J 38
49. su vu Eu Zu tH NU yor 1300S NO Q31Nn04 494205 ug ozn TNY 910 AZ E e zNa VSL a yOVSH SAH E ni OND s EAZ EVI wN S que JOD Bo SE EL if VIH 6 g 4 4 4 BE INT YSI 4 F 7 DEN Z T su deli IS 505151 50519 IAE N oud L to IW N3VH NavH 8 z Nav zh Nav topos wo 811 T o 5 p 4 SUN AUdISU 26 INI YSI 505191 ISH ISH E He LL TSUN uvdH SIE oye LSE nva H Qu q E Em 2901 6 o JMOL IJMOL ELE TN VSI UH ZL m s 8 3uss 3uss L 9 vs I EE OND WH 8L z vs T Jaos us 2 DE ae a INI VSI HUYS Cn vH 11 vs EAZ EVZ xot 6002 ve SL UWS eui af CET lE OWS Ne o VS 135005 NO CILNNON IHY OZN 611 911 Lin 911 agli INI VSI QXVH Zt 8 CVS EAT EVE TT ae E cm st Wet avs XH S9 EH lt 03H Figure A 5 ISA Bus Buffers MOTOROLA DSP56305ADM User s Manual
50. t column contains the DSP56305 signal names When connected to the AIB card the DSP56305ADM supports one stereo output channel and one stereo input channel 2 24 AIB Function SSI Function GPIOO GPIO1 GPIO2 GPIO3 SDIO SDI1 RBICK RLRCK SDOO 5001 5002 TLRCK RESET GND Figure 2 12 SSI AIB Connector DSP56305ADM User s Manual GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND MOTOROLA Technical Summary Connectors SCOO 1 R2 GND SCO1 GND SC10 5 X 6 GND SC11 GND SRDO 9 X X10 GND SRD1 1104 12 GND KEY 13 GND Figure 2 13 Dedicated SSI Connectors 2 8 5 SCI Port Connector The SCI port pins are routed to two connectors e Expansion and logic analyzer connectors e Dedicated SCI port connector Routing to the expansion Logic Analyzer connectors is done to support expansion boards and application debug while the dedicated connector enables connection to an application board via a flat cable To avoid incorrect insertion of the receptacle connector keying is provided as one of the pins is cut while its corresponding hole in the receptacle connector is filled The pinout of the SCI dedicated connector is shown in Figure 2 14 on page 2 25 TXD 1 4 2 GND SCLK 3 X X 4 GND RXD 5R 6 KEY Figure 2 14 SCI Dedicated Connector MOTOROLA DSP56305ADM User s Manual 2 25 Technical Summary Connectors 2 8 6 JTAG OnCE Connector The JTAG OnC
51. uest To DSP56305 PINIT NMI pin PLL INIT jumper Figure 2 9 PLL Selection After the RESET line is deasserted the PINIT NMI signal is connected to the NMI signal The DSP56305ADM is factory configured for PLL enabled JP2 removed 2 16 DSP56305ADM User s Manual MOTOROLA Technical Summary Host Port Selection 2 7 HOST PORT SELECTION The DSP56305 s HI32 port supports the PCI bus with no n additional logic while the ISA bus interface is supported with the addition of external buffers To support application development on both platforms DSP56305ADM supports both ISA and PCI environments That is the DSP56305ADM has edge connectors for both ISA and PCI so the board can be plugged into any EISA ISA or PCI host The DSP56305ADM is factory configured for use with an ISA host When the DSP56305ADM is used in an ISA host the default setting is used and JP3 JP4 JP5 and JP6 are jumpered U18 U20 U21 U22 U23 RN2 and RN3 are mounted in their sockets See Table 1 1 on page 1 6 for more information on jumper configuration When the DSP56305ADM is used as a stand alone device JP3 4 JP5 and JP6 should be jumpered U18 U20 U21 U22 U23 RN2 and RN3 should be mounted in their sockets The same configuration should be used for an ISA host When the DSP56305ADM is used in a PCI host the jumpers on JP3 4 JP5 and JP6 should be removed U18 U20 21 U22 U23 RN2 and RN3 should be removed from their sockets 2 7
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