Errata - STMicroelectronics
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1. C7 STM32F302x6 STM32F302x8 A oum Errata sheet STM32F302x6 and STM32F302x8 Rev Z device limitations Silicon identification This errata sheet applies to revision Z of STMicroelectronics STM32F302x6 x8 products These products feature an ARM 32 bit 4 CPU with FPU core for which an errata notice is also available see Section 1 for details Section 2 gives a detailed description of the product silicon limitations The products are identifiable as shown in Table 1 e Bythe revision code marked below the order code on the device package e By the last three digits of the Internal order code printed on the box label Table 1 Device identification 2 Sales type Revision code marked on device STM32F302x6 x8 Z 1 The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device see the STM32F302x6 x8 reference manual for details on how to find the revision code 2 Refer to STM32F302x6 x8 product datasheet for details on the device marking The full list of part numbers is shown in Table 2 Table 2 Device summary Reference Part number STM32F302x6 STM32F302C6 STM32F302K6 STM32F302R6 STM32F302x8 STM32F302C8 STM32F302K8 STM32F302R8 September 2015 DoclD025990 Rev 6 1 21 www st com STM32F302x6 STM32F302x8 Contents Contents 1 ARM Cortex M4 core with FPU core limitations 5 1 1 Cortex M4 core with FPU interrupted l2. 2 7 3 2 1 and OA2MSK and OA1 7 4 OA2 7 4 J OA2EN 1 and OA2MSK 4 and OA1 7 5 OA2 7 5 J OA2EN 1 and OA2MSK 5 and OA1 7 6 OA2 7 6 J OA2EN 1 OA2MSK 6 and OA1 7 OA2 T OA2EN 1 and OA2MSK 7 GCEN 1 and 1 7 1 000000000 ALERTEN 1 and 1 7 1 060001100 SMBDEN 1 and OA1 7 1 0b1100001 SMBHEN 1 and OA1 7 1 060001000 e The master starts a transfer addressed to the 10 bit slave address OA1 As a result after the address reception the ADDCODE value is OA1 7 1 equal to the 7 bit slave address instead of 0b11110 amp OA1 9 8 Workaround None If several slave addresses are enabled mixing 10 bit and 7 bit addresses the 10 bit Slave address OA1 7 1 must not be equal to the 7 bit slave address Wakeup frames may not wakeup the MCU mode when STOP mode entry follows 2 enabling Description If the IC is enabled PE 1 and wakeup from STOP enabled in 2 WUPEN 1 while a transfer occurs on the I C bus and STOP mode is entered during the same transfer while SCL 0 the IC is not able to detect the following START condition This means that if the 2 is addressed it will not wake up the MCU and this address is not acknowledged Workaround After enabling the 2 is set to 1 wait for a temporization before entering STOP mode to ensure that the eventual on going frame is finished DoclD025990 Rev 6 Ly STM32F302x6 STM32F302x8 STM
3. DoclD025990 Rev 6 20 21 STM32F302x6 STM32F302x8 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved 21 21 DoclD025990 Rev 6 9
4. Load multiple instruction are not supported The following sequence read of JDR1 JDR2 and JDR3 injected data registers will only cause the R1 register to be loaded with JDR1 value and registers R2 and R3 will be zeroed LDR RO 0x50000080 LDMIA RO R1 R2 R3 Workaround Load multiple instruction LDMxx must be replaced by multiple single load LD instructions ADEN bit cannot be set immediately after the ADC calibration is done Description At the end of the ADC calibration there is an internal reset of ADEN bit 4 ADC clock cycle after the ADCAL bit cleared by hardware Due to that if ADEN bit is set within those four ADC clock cycles it will be reset by the calibration logic and the ADC will stay disabled Workarounds Continue to set the ADEN bit until ADRDY bit become 1 e After ADCAL is cleared wait for a minimum of four ADC clock cycles before setting the ADEN bit DoclD025990 Rev 6 10 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 3 2 3 1 2 3 2 Note 11 21 SPI peripheral limitations SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 1 Description SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 1 In the following conditions e SPl
5. these limitations and their implications on the behavior of STM32F30xxx devices Table 3 Cortex M4 core with FPU limitations and impact on microcontroller behavior ARM ID 752770 ARM category ARM summary of errata Impact on STM32F3xxxx Interrupted loads to SP can cause erroneous behavior MINOR Cat B 776924 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Minor Cat B 1 1 5 21 Cortex M4 core with FPU interrupted loads to stack pointer can cause erroneous behavior Description An interrupt occurring during the data phase of a single word load to the stack pointer SP R13 can cause an erroneous behavior of the device In addition returning from the interrupt results in the load instruction being executed with an additional time For all the instructions performing an update of the base register the base register is erroneously updated on each execution resulting in the stack pointer being loaded from an incorrect memory location The instructions affected by this limitation are the following e LDR SP e LDR SP Rn imm e LDR SP Rn imm e LDR SP Rn e LDR SP Rn Rm Workaround As of today no compiler generates these particular instructions This limitation can only occur with hand written assembly code Both issues can be solved by replacing the direct load to the stack pointer by an intermediate load to a gene
6. 32F302x6 x8 silicon limitations 2 4 4 3 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by 12 peripheral is disabled Description When wakeup from Stop mode by 12C peripheral is disabled 0 and the MCU enters Stop mode while a transaction is on going on the I C bus the following wrong operation may occur 1 BUSY flag may be wrongly set when the MCU exits Stop mode This prevents from initiating a transfer in master mode as the START condition cannot be sent when BUSY is set This failure may occur in master mode of the I2C peripheral used in multi master l C bus environment If 2C bus clock stretching is enabled I2C peripheral NOSTRETCH 0 the I2C peripheral may pull SCL low as long as the MCU remains in Stop mode suspending all I C bus activity during that time This may occur when the MCU enters Stop mode during the address phase of an I C bus transaction in low period of SCL This failure may occur in slave mode of the 12C peripheral or in master mode of the I2C peripheral used in multi master I C bus environment Its probability depends on the timing configuration operating clock frequency of I2C peripheral and the I C bus timing Workaround Disable the 12C peripheral PE 0 before entering Stop mode and re enable it in Run mode DoclD025990 Rev 6 14 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 4 5 Note 15 21 Wakeup frame may not wa
7. TXE flag till it becomes high to make sure the data transfer has started C Disable the SPI interface by clearing SPE bit while the last data transfer is on going d Poll the BSY bit till it becomes low The second workaround can be used only when the CPU is fast enough to disable the SPI interface after a TXE event is detected while the data frame transfer is ongoing It cannot be implemented when the ratio between CPU and SPI clock is low and the data frame is particularly short At this specific case the timeout can be measured from the TXE event DoclD025990 Rev 6 Ly STM32F302x6 STM32F302x8 STM32F302x6 x8 silicon limitations 2 4 2 4 1 9 instead by calculating fixed number of CPU clock cycles corresponding to the time necessary to complete the data frame transaction 2 peripheral limitations 10 bit slave mode wrong direction bit value after Read header reception Description Under specific conditions the transfer direction bit DIR bit 16 of status register 2 ISR is low instead of high after reception of the 10 bit addressing Read header Nevertheless the 2 operates correctly in slave transmission mode and data can be sent using the TXIS flag To see the limitation all the following conditions have to be fulfilled e l Chasto be configured in 10 bit addressing mode OA1MODE is set in the I2C OAR1 register e high LSBs of the 2 slave address are equal to the 10 bit addressing Read hea
8. active while RE OorUE 0 18 2 6 5 Receiver timeout counter starting in case of a 2 stop bit configuration 19 2 7 Comparator peripheral limitation 19 2 7 1 VREFINT scaler startup time from power down parameter degradation 19 2 8 GPIO peripheral limitation 19 2 8 1 GPIOx locking mechanism is not working properly for GPIOx_OTYPE register ulcus OD RD D ga E gH P UE rk 19 Revision history 20 9 DoclD025990 Rev 6 STM32F302x6 STM32F302x8 List of tables List of tables Table 1 Device identification 0 00 eee 1 Table 2 eae ee Bere nates Rees has a Ru ae al Eee we 1 Table 3 Cortex M4 core with FPU limitations and impact on microcontroller behavior 5 Table 4 Summary of silicon limitations 7 Table 5 Document revision history 20 3 DocID025990 Rev 6 4 21 ARM Cortex M4 core with FPU core limitations STM32F302x6 STM32F302x8 ARM Cortex M4 core with FPU core limitations An errata notice of the STM32F302x6 x8 core is available from the following web address http infocenter arm com All the described limitations are minor and related to the revision rOp1 v1 of the Cortex M4 core with FPU Table 3 summarizes
9. d as a GPIO Only the 4 wire JTAG port configuration is impacted Workaround Use the SWD debug port instead of the full 4 wire JTAG port ADC limitations Sampling time shortened in JAUTO auto delayed mode Description When the ADC is configured in JAUTO single conversion mode CONT 0 with auto delayed mode enabled AUTDLY 1 if the last regular conversion is read and a new regular trigger arrives before the JEOS bit is cleared the first regular conversion sampling time is shortened by 1 cycle This does not apply for configuration where SMP 000 1 5 cycle sampling time or if the interval between triggers is always above the auto injected sequence conversion period Workaround The sampling time can be increased by 1 clock cycle if the situation is foreseen Injected queue of context is not available in case of JOM 0 Description The queue mechanism is not functional when JQM 0 The effective queue length is equal to 1 stage a new context written before the previous context s consumption will lead to a queue overflow and will be ignored Consequently the ADC must be stopped before programming the JSQR register Workaround None 9 DoclD025990 Rev 6 STM32F302x6 STM32F302x8 STM32F302x6 x8 silicon limitations 2 2 3 2 2 4 d Load multiple not supported by ADC interface Description The ADC interface only supports non sequential read accesses Read accesses on AHB3 port ADC interface using
10. de ADDCODE may indicate wrong slave address detection 13 2 4 3 Wakeup frames may not wakeup the MCU mode when STOP mode entry follows 2 enabling 2 cc eee 13 2 4 4 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by I2C peripheral is disabled 14 2 4 5 Wakeup frame may not wakeup from STOP if typysta is close to in Fast mode and Fast mode 15 2 4 6 Wrong data sampling when data set up time tsy pat is smaller than I2CCLK period 16 2 4 7 Spurious Bus Error detection in master mode 16 2 5 125 peripheral limitations 17 Ly 00 10025990 Rev 6 2 21 Contents STM32F302x6 STM32F302x8 3 21 2 5 1 In 125 slave mode WS level must be set by the external master when enabling the 25 17 2 6 USART peripheral limitations 17 2 6 1 When PCLK is selected as clock source for USART1 PCLK1 is used instead Of PCLK2 1 eee eens 17 2 6 2 Start bit detected too soon when sampling for NACK signal from the SIMANG AIG cece cc sear ea We ed ese R uk Bake Oe 18 2 6 3 A break request can prevent the Transmission Complete flag TC from being Set essere ye e ne ard XO Rn etie 18 2 6 4 nRTS is
11. der value i e OA1 7 3 11110 OA1 2 OA1 9 OA1 1 OA1 8 and OA1 0 1 in the 12C_OAR1 register e I C receives the 10 bit addressing Read header Ox 1111 OXX1 after the repeated start condition to enter slave transmission mode As a result the DIR bit is incorrect in slave mode under specific conditions Workaround If possible do not use these four values as 10 bit addresses in slave mode e OA1 9 0 0011110001 e OA1 9 0 0111110011 e OA1 9 0 1011110101 e 1 9 0 1111110111 If one of these addresses is the I C slave address the DIR bit must not be used in the FW DoclD025990 Rev 6 12 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 4 2 2 4 3 13 21 10 bit combined with 7 bit slave mode ADDCODE may indicate wrong slave address detection Description Under specific conditions the ADDCODE Address match code in the I2C_ISR register indicates a wrong slave address To see the limitation all the following conditions have to be fulfilled e 12 slave address OA1 is enabled and configured in 10 bit mode OA1EN 1 and OA1MODE 1 e Another 7 bit slave address is enabled and the bits 1 to 7 of the 10 bit slave address OA1 are equal to the 7 bit slave address i e one of the configurations below is set J OA2EN 1 and OA2MSK 0 and OA1 7 1 OA2 7 1 J OA2EN 1 and OA2MSK 1 and OA1 7 2 OA2 7 2 2 1 and OA2MSK 2 OA1 7 3
12. e address reception is case it is not the slave address If one of the conditions above is met and if the SCL falling edge following the START condition occurs on the first cycle of the I2CCLK clock HSI the address reception is not correctly done and the address match wakeup interrupt is not generated Workaround None at MCU level To ensure the correct behavior in a multi slave network the master should use a START condition hold time lower than 1 us or greater than 2 us If the wakeup frame is not acknowledged by the 2 e fthe master can program the duration of the START hold time the master should decrease or increase the START condition hold time for more than one HSI period and resend the wakeup frame e master can change the I C transfer mode the master should switch to Standard mode and resend the wakeup frame 9 DoclD025990 Rev 6 STM32F302x6 STM32F302x8 STM32F302x6 x8 silicon limitations 2 4 6 2 4 7 d Wrong data sampling when data set up time tsy pAr is smaller than one I2CCLK period Description The I2C bus specification and user manual specifies a minimum data set up time at e 250 Standard mode e 100 ns in Fast mode e 50 ns in Fast mode Plus The I2C SDA line is not correctly sampled when tgy pat is smaller than one I2CCLK I2C clock period the previous SDA value is sampled instead of the current one This can result in a wrong slave address recep
13. es may not wakeup the MCU mode when A STOP mode entry follows enabling pon ieee oie Section 2 4 4 Wrong behavior related with MCU Stop mode when wakeup A PON from Stop mode by I2C peripheral is disabled Section 2 4 5 Wakeup frame may not wakeup from STOP if typysta is P close to 1 5 in Fast mode and Fast mode Plus Section 2 4 6 Wrong data sampling when data set up time tsy par is p smaller than one I2CCLK period Section 2 4 7 Spurious Bus Error detection in master mode A Section 2 5 125 Section 2 5 1 In 125 slave mode WS level must be set by the external A 7 21 DoclD025990 Rev 6 9 STM32F302x6 STM32F302x8 STM32F302x6 x8 silicon limitations Table 4 Summary of silicon limitations continued Links to silicon limitations Revision Z Section 2 6 1 When PCLK is selected as clock source for USART1 A PCLK1 is used instead of PCLK2 Section 2 6 2 Start bit detected too soon when sampling for NACK signal N from the SmartCard 2 eid Section 2 6 3 A break request can prevent the Transmission Complete flag peripheral limitations A TC from being set Section 2 6 4 nRTS is active while RE 0 or UE 0 A Section 2 6 5 Receiver timeout counter starting in case of a 2 stop bit A configuration Section 2 7 Comparator Section 2 7 1 VREFINT scaler startup time from power down parameter N peripheral limitation degradation Section 2 8 GPIO Section 2 8 1 GPIOx lock
14. hole communication Workaround The 125 peripheral must be enabled when the external master sets the WS line at High level when the 125 protocol is selected Low level when the LSB or MSB justified mode is selected USART peripheral limitations When PCLK is selected as clock source for USART1 PCLK1 is used instead of PCLK2 Description USART1 is mapped on the fast APB2 and its clock can be selected among four different sources using the USART1SW 1 0 bits in the RCC_CFGR3 register The default configuration selects PCLK1 APB1 clock as USART1 clock source instead of PCLK2 APB2 clock Workaround There is no workaround To reach 9 Mbaud System Clock SYSCLK should be selected as USART1 clock source d DoclD025990 Rev 6 STM32F302x6 STM32F302x8 STM32F302x6 x8 silicon limitations 2 6 2 2 6 3 2 6 4 9 Start bit detected too soon when sampling for signal from the SmartCard Description In the 1507816 when a character parity error is incorrect the SmartCard receiver shall transmit a NACK error signal at 10 5 0 2 etu after the character START bit falling edge In this case the USART transmitter should be able to detect correctly the NACK signal by sampling at 11 0 0 2 etu after the character START bit falling edge The USART peripheral used in SmartCard mode does not respect the 11 0 2 etu timing and when the NACK falling edge reaches 10 68 etu or more the USART mi
15. ing mechanism is not working properly for A peripheral limitation GPIOx OTYPE register 2 1 Note 9 System limitations Wakeup sequence from Standby mode when using more than one wakeup source Description The various wakeup sources are logically OR ed in front of the rising edge detector that generates the wakeup flag WUF The WUF flag needs to be cleared prior to the Standby mode entry otherwise the MCU wakes up immediately If one of the configured wakeup sources is kept high during the clearing of WUF flag by setting the CWUF bit it may mask further wakeup events on the input of the edge detector As a consequence the MCU may not be able to wake up from Standby mode Workaround To avoid this limitation the following sequence should be applied before entering the Standby mode e Disable all used wakeup sources e Clear all related wakeup flags e Re enable all used wakeup sources e Enter Standby mode when applying this workaround if one of the wakeup sources is still kept high the MCU will enter the Standby mode but then it will wake up immediately and generate the power reset DoclD025990 Rev 6 8 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 1 2 2 2 2 2 1 2 2 2 9 21 Full JTAG configuration without NJTRST pin cannot be used Description When using the JTAG debug port in debug mode the connection with the debugger is lost if the NJTRST pin PB4 is use
16. ions Table 4 gives quick references to all documented limitations The legend for Table 4 is as follows A workaround available N no workaround available P partial workaround available and grayed fixed Table 4 Summary of silicon limitations peripheral limitations master when enabling the I2S Links to silicon limitations Revision 2 Section 2 1 1 Wakeup sequence from Standby mode when using more A Section 2 1 System than one wakeup source limitations Section 2 1 2 Full JTAG configuration without NJTRST pin cannot be used A Section 2 2 1 Sampling time shortened in JAUTO auto delayed mode A Section 2 2 2 Injected queue of context is not available in case of JQM 0 N Section 2 2 ADC limitations Section 2 2 3 Load multiple not supported by ADC interface A Section 2 2 4 ADEN bit cannot be set immediately after the ADC A calibration is done Section 2 3 1 SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end P Section 2 3 SPI of transfer or end of transfer 1 peripheral limitations Section 2 3 2 BSY bit may stay high at the end of a SPI data transfer in A slave mode Section 2 4 1 10 bit slave mode wrong direction bit value after Read header reception Section 2 4 2 10 bit combined with 7 bit slave mode ADDCODE may N indicate wrong slave address detection Section 2 4 3 Wakeup fram
17. is slave or master e Full duplex or simplex mode is used e CRC feature is enabled e configured to manage data transfers by software interrupt or polling e a peripheral mapped on the same DMA channel as the SPI is doing DMA transfers the CRC may be frozen before the CRCNEXT bit is written resulting in a CRC error Workaround If the application allows it use the DMA for SPI transfers BSY bit may stay high at the end of a SPI data transfer in slave mode Description In slave mode BSY bit is not reliable to handle the end of data frame transaction due to some bad synchronization between the CPU clock and external SCK clock provided by master Sporadically the BSY bit is not cleared at the end of a data frame transfer As a consequence it is not recommended to rely on BSY bit before entering low power mode or modifying the SPI configuration e g direction of the bidirectional mode Workaround e When the SPI interface is in receive mode the end of a transaction with the master can be detected by the corresponding RXNE event when this flag is set after the last bit of that transaction is sampled and the received data are stored e When the following sequence is used the synchronization issue does not occur The BSY bit works correctly and can be used to recognize the end of any transmission transaction including when RXNE is not raised in bidirectional mode a Write the last data into data register b Poll
18. keup from STOP if typysta is close to tsu Hsi in Fast mode and Fast mode Plus Description Under specific conditions and if the START condition hold time duration is very close to the HSI start up time duration tgyysi the 2 is not able to detect the address match and to wake up the MCU from STOP The tguys is between 1 us and 2 us refer to product datasheet therefore this issue cannot occur in Standard mode To see the limitation one of the conditions listed below has to be met e Timeout detection is enabled TIMOUTEN 1 or TEXTEN 1 and the frame before the wakeup frame is abnormally finished due to a 12 Timeout detection TIMOUT 1 e slave arbitration is lost during the frame before the wakeup frame ARLO 1 According to standards the slave arbitration is not applicable 1 C and used only in SMBus for which the transfer is done in Standard mode Therefore when the standards are respected this condition does not lead to the limitation e The MCU enters STOP mode while another slave is addressed after the address phase and before the STOP condition BUSY 1 e MCU is in STOP mode and another slave is addressed before the I C is addressed The last three conditions can occur only in a multi slave network In STOP mode the HSI is powered on by the when a START condition is detected SDA falling edge while SCL is high The HSI is used to receive the address and it is powered off after th
19. oads to stack pointer can cause erroneous behavior 5 1 2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used 6 2 STM32F302x6 x8 silicon limitations 7 2 1 System limitations 8 2 1 1 Wakeup sequence from Standby mode when using more than one wakeup SOUICE sireci aa eee 8 2 1 2 Full JTAG configuration without NJTRST pin cannot be used 9 2 2 ADC limitations 3 22333 xo ence a Ra e RR aR dO e d Ca a CR RR ae 9 2 2 1 Sampling time shortened JAUTO auto delayed mode 9 2 2 2 Injected queue of context is not available in case of JQM 20 9 2 2 3 Load multiple not supported by ADC interface 10 2 2 4 ADEN bit cannot be set immediately after the ADC calibration is done 10 2 3 SPI peripheral limitations 11 2 3 1 SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 1 11 2 3 2 BSY bit may stay high at the end of a SPI data transfer in slave mode 11 24 I C peripheral limitations gren 12 2 4 1 10 bit slave mode wrong direction bit value after Read header ESEE RES EE eee al ee aR E 12 2 4 2 10 bit combined with 7 bit slave mo
20. ral purpose register followed by a move to the stack pointer Example Replace LDR SP RO by LDR R2 R0 MOV SP R2 d DoclD025990 Rev 6 STM32F302x6 STM32F302x8 ARM Cortex M4 core with FPU core limitations 1 2 d VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Description On ARM Cortex M4 with FPU core 14 cycles are required to execute a VDIV or VSQRT instruction This limitation is present when the following conditions are met e AVDIV or VSQRT is executed e destination register for VDIV or VSQRT is one of s0 s15 e An interrupt occurs and is taken e The ISR being executed does not contain a floating point instruction e 14 cycles after the VDIV or VSQRT is executed an interrupt return is executed In this case if there are only one or two instructions inside the interrupt service routine then the VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated meaning that these registers hold incorrect out of date data Workaround Two workarounds are applicable e Disable lazy context save of floating point state by clearing LSPEN to 0 bit 30 of the FPCCR at address OxEOO0EF34 e Ensure that every ISR contains more than 2 instructions in addition to the exception return instruction DoclD025990 Rev 6 6 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 STM32F302x6 x8 silicon limitat
21. rking information Added the following limitations Section 2 1 1 Wakeup sequence from Standby mode when using 01 Oct 2014 3 more than one wakeup source Section 2 2 3 Load multiple not supported by ADC interface Section 2 3 1 SPI CRC may be corrupted when a peripheral connected to the same DMA channel of the SPI is under DMA transaction near the end of transfer or end of transfer 1 Added the following limitation 21 Nov 2014 4 Section 2 2 4 ADEN bit cannot be set immediately after the ADC calibration is done Added the following limitations Section 2 6 2 Start bit detected too soon when sampling for NACK signal from the SmartCard Section 2 6 3 A break request can prevent the Transmission Complete flag TC from being set Section 2 6 4 nRTS is active while RE 0 or UE 0 Section 2 7 1 VREFINT scaler startup time from power down parameter degradation Updated Section 2 4 4 Wrong behavior related with MCU Stop mode when wakeup from Stop mode by I2C peripheral is disabled Added the following limitations Section 2 1 2 Full JTAG configuration without NJTRST pin cannot 14 Sep 2015 6 be used Section 2 3 2 BSY bit may stay high at the end of a SPI data transfer in slave mode Section 2 6 5 Receiver timeout counter starting in case of a 2 stop bit configuration Section 2 4 7 Spurious Bus Error detection in master mode 19 Feb 2015 5 d
22. sinterprets this transition as a START bit even if the NACK is correctly detected Workaround None A break request can prevent the Transmission Complete flag TC from being set Description After the end of transmission of data D1 the Transmission Complete TC flag will not be set in the following conditions e CTS hardware flow control is enabled e Diis being transmitted e A break transfer is requested before the end of D1 transfer e nCTS is de asserted before the end of transfer of D1 Workaround If the application needs to detect the end of the data transfer the break request should occur after making sure that the TC flag is set nRTS is active while RE 0 or UE 0 Description The nRTS line is driven low as soon as RTSE bit is set even if the USART is disabled UE 0 or the receiver is disabled RE 0 that is not ready to receive data Workaround Configure the I O used for nRTS as alternate function after setting the UE and RE bits DoclD025990 Rev 6 18 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 6 5 2 7 2 7 1 2 8 2 8 1 19 21 Receiver timeout counter starting in case of a 2 stop bit configuration Description In the case of a 2 stop bit configuration the receiver timeout counter starts counting from the end of the second stop bit of the last character instead of the end of the first stop bit Workaround Change the RTO value in the USARTx_RTOR regi
23. ster with subtracting 1 bit duration Comparator peripheral limitation VREFINT scaler startup time from power down parameter degradation Description The VREFINT scaler is an embedded voltage follower providing the VREFINT or its fractions 1 2 1 4 or 3 4 to the comparator input The maximum VREFINT scaler startup time ts is not as expected for the first activation of the VREFINT scaler after powering on the device and it can be up to 1s in worse case conditions This maximum value depends mainly on the voltage and temperature see the device datasheet for more details Workaround None GPIO peripheral limitation GPIOx locking mechanism is not working properly for GPIOx_OTYPE register Description Locking of GPIOx OTYPER i with i 15 8 depends on the setting of GPIOx LCKR i 8 and not from the setting of GPIOx LCKR i GPIOx LCKR i 8 locks GPIOx OTYPER i together with GPIOx_OTYPERIi 8 It is not possible to lock GPIOx OTYPER i with i 15 8 without locking also GPIOx OTYPER i 8 Workaround The only way to lock GPIOx OTYPER i with i215 8 is to lock also GPIOx OTYPER i 8 9 DoclD025990 Rev 6 STM32F302x6 STM32F302x8 Revision history 3 Revision history Table 5 Document revision history Date Revision Changes 21 Mar 2014 1 Initial release 09 Apr 2014 2 Removed all part numbers with 16KByte Flash size Added note 2 in Table 1 Device identification Removed the package ma
24. tion a wrong received data byte or a wrong received acknowledge bit Workaround Increase the I2CCLK frequency to get I2CCLK period smaller than the transmitter minimum data set up time Or if it is possible increase the transmitter minimum data set up time Spurious Bus Error detection in master mode Description In master mode a bus error can be detected by mistake so the BERR flag can be wrongly raised in the status register This will generate a spurious Bus Error interrupt if the interrupt is enabled A bus error detection has no effect on the transfer in master mode therefore the I2C transfer can continue normally Workaround If a bus error interrupt is generated in master mode the BERR flag must be cleared by software No other action is required and the on going transfer can be handled normally DoclD025990 Rev 6 16 21 STM32F302x6 x8 silicon limitations STM32F302x6 STM32F302x8 2 5 2 5 1 2 6 2 6 1 17 21 I2S peripheral limitations In 125 slave mode WS level must be set by the external master when enabling the I2S Description In slave mode the WS signal level is used only to start the communication If the 125 in slave mode is enabled while the master is already sending the clock and the WS signal level is low for 125 protocol or high for the LSB or MSB justified mode the slave starts communicating data immediately In this case the master and slave will be desynchronized throughout the w
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