Home

CAEN V1740 64ch/12bit@65Msps rev13

1. pes wama x x _ _ jew x x x vme conteos eue xe x wesmus __ 5 Je m x x _ MULTICAST BASE ADDRESS CONTROL nem x ReLocationanoress pero xe x rmauTSTUSD x NUMBER X x _ pureventnumecn overs o x x _ __ _ _ ero xe x x _ _____ pem ww px w pasena enc e x 5 jo ow x xe w jormosschuo loge 5 2 Configuration ROM 0xF000 0xF084 r The following registers contain some module s information they are D32 accessible read only OUI manufacturer identifier IEEE OUI Version purchased version Board ID Board identifier Revision hardware revision identifier Serial MSB serial number MSB Serial LSB serial number LSB NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 40 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Table 5
2. 16 3 FUNCTIONAL DESCRIPTION 17 ANALOG INPUT 17 CLOT DISPPRIBEEION 18 3 2 FH Drect Dre uiuos DN E oe best E QD 19 9 2 2 DESTINO TR mE 19 3 2 3 bu TT 19 3 2 4 Quan Ee anes Rese 19 129 FDL POG 19 3 2 6 20 Sp vA Direct Drive BYPASS P10 G7 Gite ue dut ie aquas a EA RAE 20 3 2 6 IE seca s dina Cesta 20 3 2 9 VITIS TATRAWIOIITITI TIT 20 5 MODE E E 21 roo opo TUS OD MER 21 3 3 2 Dala Qcguisttion and S OYGBE sis cotsctisvaclueunciclnacrdesandverdeisndecsanstetuacuunacidussadeseslevsdessandlssenenexiacesatet 22 3 3 3 Acquisition Triggering Samples and Events 22 205 Custom S126 CY CNS Nm 23 3 3 4 E VOD 23 ERN 23 TE o Nomcn 24 3 3 4 3 Event format
3. ae here 24 3 3 5 Memory FULL EE 25 3 4 TRIGGER MANAGEMENT cccsccsssesccsssesccecussesccessssceessescceccesccesssecsccestesccussesceesssseeessesuseeessesceeeesees 26 NPO 00118 07 V1740x MUTx 13 Filename V1740_REV13 DOC Number of pages Page 55 3 CAEN 0 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 3 4 1 lb ro a ITUR a A A PRO 26 3 4 2 I ERN ET 26 3 4 3 Local channel group eese nennen 26 THSSSESOIBOIdOEBCE re eee 21 3 4 4 26 RON WISIS T r 20 3 5 TEST PATTERN GENERATOR e EEEE 30 OV MEME MONTOR Mur 30 3 7 1 Trigger Majority Mode Monitor Mode 0 30 272 Tor Model TIS TI Mode CNET 31 3 7 3 Buffer Occupancy Mode Monitor Mode 3 31 3 7 4 Voltage Level Mode Monitor Mode 4 esses eene nnne sese nennen nns 31 3 8 RESET CLEAR AND DEFAULT 31 3 8 1 TOTEM 31 3 8 2 DUAL PUER 32 3 6 3 IB U
4. 51 227 BLT EVENT NUMBER ksr n taba rd E Eau rasuras Ur MER PEE OM 51 5 36 SRAT 51 5 39 SOFTWARE RESET XEP24 W ER veau 51 5 40 SOBTWARBCLEAR UXBEP2S W 51 5 41 FLASH ENABLE 52 5 42 Ig UV NP AT 0 4 5 18 i c 32 5 43 CONFIGURATION RELOAD n He eene ne nne seres 32 INSTALLATION 53 Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 5 CAEN 0 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 EEB Esdr 53 CS OLEI VU Scc 53 PIRMWARE UPGRADE 2 12 24 9 95 09 99 8 0M MOON OMM URS 53 6 3 1 VIMO Uporade files desCriDHlOl niseecseaso 54 LIST OF FIGURES AO BLOCR EIAGRANL c quu questio i ai ommum 9 EI 2 EMOD y uas metre nimii uo diu
5. p 0 V1740 5 28 Monitor Mode 0x8144 r w This register allows to encode the Analog Monitor see 6 3 7 operation 000 majority 001 waveform generator saw tooth ramp 010 reserved 011 buffer occupancy 100 voltage level 5 29 Event Size 0x814C r B 31 0 Nr of 32 bit words in the next event 5 30 VME Control r w 1 7 0 Release On Register Access RORA Interrupt mode default 1 Release On AcKnowledge ROAK Interrupt mode 0 RELOC Disabled BA is selected via Rotary Switch see S 2 6 1 RELOC Enabled BA is selected via RELOC register see 5 34 5 0 ALIGN64 Disabled NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 49 uds for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 1 ALIGN64 Enabled see 5 3 11 1 2 0 BERR Not Enabled the module sends a DTACK signal until the CPU inquires the module 1 BERR Enabled the module is enabled either to generate a Bus error to finish a block transfer or during the empty buffer read out in D32 3 0 Optical Link interrupt disabled 1 Optical Link interrupt enabled Bit 7 this setting is valid only for interrupts broadcasted on VMEbus interrupts broadcasted optical link feature RORA mode only In RORA mode interrupt status be remo
6. vk FREUE QU OR VAY GO Ma GU SR PER S ci eU 42 5 6 GROUP N BUFFER OCCUPANCY OXINQA 42 521 OROUPNDAC IOXIMOS BIW ad 42 5 8 GROUP N ADC CONFIGURATION O0X1N9C HI men ne nenne ense re nennen 42 5 9 GROUP N CHANNEL TRIGGER MASK 8 42 NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 4 CAEN 0 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 10 GROUP CONFIGURATION 43 5 11 GROUP CONFIGURATION SET OX8004 9 43 S 1X GROUP CONFIGURATION BIT CLEAR 0X8008 43 5 13 BUFFER ORGANIZATION 0 800 20 42 420000000000 43 5 14 CUSTOM SIZE 44 5 15 ACQUISITION CONTROL 0X8100 44 5 16 ACQUISITION STATUS 0 8104 2 11 1 66 6 45 5 17 SOFTWARE TRIGGER 0X8 W 45 5 18 TRIGGER SOURCE ENABLE MASK 0X810C 0 0000 0
7. 46 5 19 FRONT PANEL TRIGGER OUT ENABLE MASK 0X81 10 46 5 20 POST TRIGGER SETTING 0X81 14 0200000000 0 eH e nen mH nn nenne nnne ne ese renes 47 5 21 FRONT PANEL I O DATA 0 8118 Hee e n nmn emn nnne sensn renes 47 5 22 FRONT PANEL VO CONTROL TIC R W 47 5 23 GROUP ENABLE MASK 0X8120 48 5 24 ROC FPGA FIRMWARE REVISION 0X8124 8 0000 48 5 25 HVENT STORED OXGO 2C REQUE RA RU BOR EON ISDEM Ep 49 5 26 SLT MONITOR DAC ORS LIG PIW 49 3 27 BOARD INFO 0 8 140 n n menn nem nennen nennen e ne se se nere esee neun 49 5 28 MONITOR MODE 0X8144 2 02202000000 0 0 0 ehe nne ne nne nennen sense rene n eres esee suns 49 5 29 EVENT SIZE 0X814C R M Ri 49 5 30 VME CONTROLO EFON B W ETENE I 49 5 31 VME STATUS R 50 0 22 BOARD OS R W 50 5 33 MCST BASE ADDRESS AND CONTROL OXEFOC 50 5 34 RELOCATION ADDRESS R W 1 51 5 35 INTERRUPT STATUS ID n nne nenne enhn 51 5 36 INTERRUPT EVENT NUMBER OXEF18
8. lt O 5 S ev gt gt ROC FPGA Readout control VME interface control Optical link control Trigger control External interface control Fig 1 1 Mod V1740 Block Diagram The function of each block will be explained in detail in the subsequent sections NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 9 le far Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 2 Technical specifications 2 1 Packaging and Compliancy The module is housed in a 6U high 1U wide VME unit The board hosts the VME P1 and P2 connectors and fits into both VME VME64 standard and V430 backplanes VX1740 versions fit VME64X compliant crates In all cases only well ventilated crates must be used The V1740 cannot be operated with CAEN crates VME8001 8002 8004 8004A 2 2 Power requirements The power requirements of the module are as follows Table 2 1 Model V1740 power requirements NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 10 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 2 3 Front Panel Mod V1740 EXTERNAL _ 5 CLOCK IN INTERNAL __ CLOCK OUT LOCAL TRIGGER OUT
9. e sesta ense eene 10 EEE c 14 TABLE 2 3 MOD 1 740 TECHNICAL 8 12 00000000000000000 0 000000020 0000000 10 TABLE 3 1 FRONT PANEL VOS DEFAULT SETTING 30 TABLES L ADDBESS MAP FOR THE MODEL VU 740 epis cue En TEN 39 TABLE 5 2 ROM ADDRESS MAP FOR THE MODEL V 1740 esses 4 TABLE 5 3 OUTPUT BUFFER MEMORY BLOCK DIVISION 44 NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 7 F1 Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 1 General description 1 1 NPO Overview The Mod V1740 is a 1 unit wide VME 6U module housing a 64 Channel 12 bit 65 MS s Flash ADC Waveform Digitizer with threshold Auto Trigger capabilities Maximum sampling frequency is 65 MS s using an external clock and 62 5 MS s using the internal source The high channel density is allowed by the AD9222 Octal 12 bit 65 MSPS Analog to Digital Converter therefore most channel settings are performed over groups of 8 channels one group per ADC chip The single ended analog input signal has a dynamic range of 2 Vpp 10 Vpp available on request The DC of
10. NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 50 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 34 Relocation Address OxEF10 r w Bt 1 13 31 Function X 2 These bits contains the A31 A16 bits of the address of the module 15 0 it can be set via VME for a relocation of the Base Address of the module 5 35 Interrupt Status ID OxEF14 r w Bit 31 0 This register contains the STATUS ID that the module places on the data bus during the Interrupt Acknowledge cycle 5 36 Interrupt Event Number OxEF18 r w Bit 9 0 INTERRUPT EVENT NUMBER If interrupts are enabled the module generates a request whenever it has stored in memory a Number of events INTERRUPT EVENT NUMBER 5 37 BLT Event Number OxEF1C r w 2 Funcdion This register contains the number of complete events which has to 7 0 be transferred via BLT CBLT see 3 11 1 2 5 38 Scratch OxEF20 r w E 0 Scratch to be used to write read words for VME test purposes 5 39 Software Reset OxEF24 w B 0 A write access to this location allows to perform software reset 5 40 Software Clear OxEF28 w 31 0 A write access to this location clears all the memories NPO Filename Number of pages gt Page 00118 07 V174
11. 19 of CR CSR space indicating the slot number in the crate the recognized Address Modifier for this cycle is 2F SAE 15 implemented only on versions with 160pin connectors 2423 19118 16115 0 77 OFFSET Fig 3 14 CR CSR addressing 3 9 1 3 Address relocation Relocation Address register see 5 34 allows to set via software the board Base Address valid values 0 Such register allows to overwrite the rotary switches settings its setting is enabled VME Control Register see 5 di The used addresses are 31 24 23 1615 OFFSET ce I software ADERH ADERL lt relocation 31 2423 1615 0 OFFSET A24 software relocation ADERL Fig 3 15 Software relocation of base address 3 10 Data transfer capabilities The board supports D32 single data readout Block Transfer BLT32 and MBLT64 2eVME and 2eSST cycles Sustained readout rate is up to 60 MB s with MBLT64 up to 100 MB s with 2eVME and up to 160 MB s with 2eSST 3 11 Events readout 3 11 1 Sequential readout The events once written in the SRAMs Memory Event Buffers become available for readout via VME During the memory readout the board can continue to store more events independently from the readout on the free buffers The acquisition process is therefore deadtimeless until the memory becomes full Although the memories
12. BLOCK TRANSFER D32 D64 2eVME BLT32 allows via a single channel access to read N events in sequence N is set via the BLT Event Number register see S 5 37 The event size depends on the Buffer Organization Register setting S 5 13 namely Event Size 8 Block Size 16 bytes Smaller event size can be achieved via Custom Size setting see 5 14 Then it is necessary to perform as many cycles as required in order to readout the programmed number of events We suggest to enable BERR signal during BLT32 cycles in order to end the cycle avoiding filler readout The last BLT32 cycle will not be completed it will be ended by BERR after the N event in memory is transferred see example in the figure below READOUT DATA BUFFERS Block size 1024 bytes BERR enabled BLT size 16384 bytes N 4 Fig 3 16 Example of BLT readout Since some 64 bit CPU s cut off the last 32 bit word of a transferred block if the number of words composing such block is odd it is necessary to add a dummy word which has then to be removed via software in order to avoid data loss This can be achieved by setting the ALIGN64 bit in the VME Control register see 5 5 26 MBLT64 cycle is similar to the BLT32 cycle except that the address and data lines are multiplexed to form 64 bit address and data buses The 2eVME allows to achieve higher transfer rates thanks to the requirement of only two edges of the two control signals
13. EXTERNAL 3 TRIGGER IN SYNC SAMPLE START ANALOG INPUT ANALOG MONITOR OUTPUT L 5 DIGITAL I O s 64 CH 12 BIT 65 MS s DIGITIZER Fig 2 1 Mod V1740 front panel NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 11 for Discoven Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 2 4 External connectors 2 4 f ANALOG INPUT connectors GND GND LEFT ROW LEFT ROW CH3in CH2in CHOin GND Fig 2 2 ERNI SMC Connectors Function Analog input single ended input dynamics 2Vpp Zin 50Q on request 10Vpp Zin 1KQ Mechanical specifications Two ERNI SMC 114805 Dual Row 68pin connectors N B absolute max analog input voltage 6Vpp with Vrail max to 6V or 6V for any DAC offset value Ensure that alignment is correct during insertion extraction operations incorrect alignment may lead to connector damage 2 4 2 CONTROL connectors Function e TRG OUT Local trigger output NIM TTL on Rt 50Q TRG IN External trigger input NIM TTL Zin 500 SYNC SAMPLE START S IN Sample front panel input NIM TTL Zin 50Q MON DAC output 1Vpp on 500 Mechanical specifications 00 type LEMO connectors NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 33
14. Registers address map Table 5 1 Address Map for the Model V1740 Beaster name avoress move resis EVENTREADOUTeUFFER 0 werd a x X x X x _ Bw em owing e x x _ Group nAMCFPGAFIRMWAREREVISION crupnaurrenoccurancy m x x x GepnbC 5 pee x x _ croupnancconricunarion X x _ Group n CHANNEL TRIGGER ENABLE MASK etwa Juno xe x x _ Group 0400 x x _ E FRONT PANEL TAUGGEROUT ENABLE MASK Juno pa x x _ Posrrmiccensermnc x x _ _ Juno pe x x _ FronTPaneLuoconrac peno umae x x _ roupenaatemask beo x x _ a NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 39 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Beaster name omes move resis peis Eventstore 5 pec _ Jew x x x sermonronoac umae x x _
15. User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 3 3 In order to keep all dividers outputs aligned the AD9510 is provided with a SYNCB input see 3 2 all dividers are put in phase on a SYNCB edge This is done automatically within a board at any board reset therefore it is guaranteed that one board has the same sampling clock for all channels However if it is necessary to synchronize sampling clock on more V1740s then SYNCB signals have to be synchronized in their turn as well On modules with printed board Rev 2 or greater synchronization is achieved by piloting SYNCB through a D Edge Triggered Flip Flop receiving EXT CLK as clock input In this way it is ensured that the SYNCBs of all modules have the same phase On modules with printed board Rev 1 however the synchronization SYNCB can be obtained through the S IN signal In fact on S IN leading edge when the board is properly programmed see 3 3 1 the ROC FPGA sends a pulse on SYNCB In order to avoid uncertainty it is necessary S IN is sent to all the modules in phase with EXT CLK this will allow all V1740s to receive it with the same clock period After the synchronization of sampling clock signals the modules will be also in phase with each other and all samples will be written into memory all at the same time However in order to ensure that the windows of acquisition related to the external trigger signal are also perfectly
16. 1 Group enabled 0 Group 2 disabled 1 Group 2 enabled 0 Group 1 disabled 1 Group 1 enabled 0 Group 0 disabled 1 Group 0 enabled Enabled groups provide the samples which are stored into the events and not erased The mask cannot be changed while acquisition is running 5 4 1 5 24 ROC FPGA Firmware Revision 0x8124 r Bt 1 Funcdion 31 16 Revision date in Y M DD format Firmware Revision X Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y format NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 48 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 25 Event Stored 0x812C r Bit This register contains the number of events currently stored in the 31 0 Output Buffer This register value cannot exceed the maximum number of available buffers according to setting of buffer size register 5 26 Set Monitor DAC 0x8138 r w Bit This register allows to set the DAC value 12bit This register allows to set the DAC value in Voltage level mode see 2 7 LSB 0 244 mV terminated on 50 Ohm 5 27 Board Info 0x8140 r Bit 1 A Funcion AJ 9 15 8 Memory size Mbyte Group
17. 12 ols for Discove Document type F1 Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 2 4 3 ADC REFERENCE CLOCK connectors GND CLK CLK m Fig 2 3 AMP CLK IN OUT Connector CLK IN Function CLK IN External clock Reference input AC coupled diff LVDS ECL PECL VPECL CML Zdiff2 1100 Mechanical specifications AMP 3 102203 4 connector CLK OUT Function CLOCK OUT Clock output DC coupled diff LVDS Zdiff 1100 Mechanical specifications AMP 3 102203 4 connector 2 4 4 Digital l O connectors NPO 9 amp 6 9 Fig 2 4 Programmable IN OUT Connector Function N 16 programmable differential LVDS I O signals Zdiff_in 110 Ohm Four Independent signal group 0 3 4 7 8 11 12 15 In Out direction control Lowest couple 0 highest couple not connected See also 6 3 5 Mechanical specifications 3M 7634 5002 34 pin Header Connector Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 13 uds for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 2 4 5 Optical LINK connector LINK TX red wrap black wrap Fig 2 5 LC Optical Connector Mechanical specifications LC ty
18. 7 0 FF all groups enabled and Local trigger coincidence level 1 whenever at least one channel in a group exceeds the threshold the trigger will be generated only if at least another enabled channel in another group is over threshold at that moment Local trigger coincidence level must be smaller than the number of groups enabled via bit 7 0 mask EXTERNAL TRIGGER ENABLE bit30 enables the board to sense TRG IN signals SW TRIGGER ENABLE bit 31 enables the board to sense software trigger see S 5 17 5 19 Front Panel Trigger Out Enable Mask 0x8110 r w Bt 1 1 Fundin 0 Software Trigger Disabled 1 Software Trigger Enabled 1 External Trigger Enabled 7 1 Group 7 trigger enabled ENR 1 1 Group 6 trigger enabled 1 Group 5 trigger enabled 1 Group 4 trigger enabled NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 46 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Bit 0 Group 3 trigger disabled 1 Group 3 trigger enabled 3 2 0 Group 2 trigger disabled 1 Group 2 trigger enabled 0 Group 1 trigger disabled 1 Group 1 trigger enabled 0 Group 0 trigger disabled 1 Group 0 trigger enabled This register bits 0 7 enable the groups to generate a TRG OUT front panel signal as the digitized signal of one
19. DS and DTACK to complete data cycle Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 34 for Discaove F1 Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 3 1 3 12 3 11 1 3 CHAINED BLOCK TRANSFER D32 D64 The V1740 allows to readout events from more daisy chained boards Chained Block Transfer mode The technique which handles the CBLT is based on the passing of a token between the boards it is necessary to verify that the used VME crate supports such cycles Several contiguous boards in order to be daisy chained must be configured as first intermediate or last via MCST Base Address and Control Register see 5 33 A common Base Address is then defined via the same register when a BLT cycle is executed at the address CBLT Base 0x0000 OxOFFC the first board starts to transfer its data driving DTACK properly once the transfer is completed the token is passed to the second board via the IACKIN IACKOUT lines of the crate and so on until the last board which completes the data transfer and asserts BERR which has to be enabled the Master then ends the cycle and the slave boards are rearmed for a new acquisition If the size of the BLT cycle is smaller than the events size the board which has the token waits for another BLT cycle to begin from the point
20. Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 54 ols for Discove Document type F1 Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 NPO backup copy of the firmware the FPGAs must be upgraded and the revisions kept aligned it is not guaranteed that the latest revision of one FPGA is compatible with an older revision Upgrade examples 1 Upgrade to Rev 1 0 main FPGA Rev 0 2 channel group FPGA of the standard page of the V1740 CVUpgrade 1740 1 0 0 2 rbf 32100000 standard 2 Upgrade to Rev 1 0 main FPGA Rev 0 2 channel group FPGA of the backup page of the V1740 CVUpgrade 1740 1 0 0 2 rbf 32100000 backup 3 Upgrade to Rev 1 0 main FPGA Rev 1 1 channel group FPGA of the standard page of the V1740 CVUpgrade v1740 1 0 1 1 rbf 32100000 standard Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 55
21. Input Input dynamic is 2Vpp Zin 50 10Vpp Zin 1KQ dynamic is available on request 16bit DAC allow to add up to 1V 5V with high range input DC offset in order to preserve the full dynamic range also with uni polar positive or negative input signals The input bandwidth ranges from DC to 30 MHz with 2nd order linear phase anti aliasing low pass filter L Input Dynamic Range 1 Vpp Input AW UB 2 AN d ANNV 5 Vref FPGA 0 T 16 bit 2 Positive Unipolar DAC FSR Negative Unipolar DAC 0 Bipolar DAC FSR 2 Fig 3 1 Input diagram Number of pages gt Page NPO Filename 55 17 00118 07 V1740x MUTx 13 V1740 REVI3 DOC CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 3 2 Clock Distribution MEZZANINES wmm Local Acquisition Memory Lombera Logis Fig 3 2 Clock distribution diagram The module clock distribution takes place on two domains OSC CLK and REF CLK the former is a fixed 50MHz clock provided by an on board oscillator the latter provides the ADC sampling clock OSC CLK handles both VME and Local Bus communication between motherboard and mezzanine boards see red traces in the figure above REF CLK handles ADC sampli
22. Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 CAENUpgrader requires the installation of 2 CAEN libraries CAENComm CAENVMELib and Java 5 6 or later CAENComm allows CAENUpgrader to access target boards via USB or via CAEN proprietary CONET optical link CAEN Upgrader GUI Upgrade CAEN Front End Hardware 225 n Electronic Instrumentation Bridge Upgrade Available actions Connection Type Upgrade Firmware USB Config Options Standard Q Backup Page T2 Board Model Lon LINK number 0r 88 Skip Verify Firmware binary file J VME Base Address Upgrade 0 cvUparade Ready Fig 4 4 CAENUpgrader Graphical User Interface DPP Control Software is an application that manages the acquisition in the digitizers which have DPP firmware installed on it The program is made of different parts there is a GUI whose purpose is to set all the parameters for the DPP and for the acquisition the GUI generates a textual configuration file that contains all the parameters This file is read by the Acquisition Engine DPPrunner which is a C console application that programs the digitizer according to the parameters starts the acquisition and manage the data readout The data that can be waveforms time stamps energies or other quantities of interest can be saved to output files or plotted using gnuplo
23. Mode Monitor Mode 0 It is possible to generate a Majority signal with the DAC the MON output provides a signal whose amplitude is proportional to the number of triggering groups the groups enabled to generate the local trigger where at least one of the enabled channels in the NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 30 EIE for Discoven Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 group has exceeded the programmed threshold see 5 5 3 5 5 9 and S 5 18 1 step 1 25mV This allows via an external discriminator to produce a global trigger signal as the resulting majority has exceeded a particular threshold THRESHOLD KO GROIN THRESHOLD GR1IN 2 5mV 1 25 MAJ ORITY Fig 3 11 Majority logic 2 triggering groups polarity bit 6 of Gr Config Reg 0 3 7 2 Test Mode Monitor Mode 1 In this mode the MON output provides a sawtooth signal with 1 V amplitude and 30 518 Hz frequency 3 7 3 Buffer Occupancy Mode Monitor Mode 3 In this mode MON out provides a voltage value proportional to the number of buffers filled with events step 1 buffer 0 976 mV This mode allows to test the readout efficiency in fact if the average event readout throughput is as fast as trigger rate then MON out value remains constant
24. aligned it is also necessary that the TRG IN signal is sent to all modules synchronously with EXT CLK and in accordance with the setup time related to its leading edge In fact if EXT TRG is not correlated with EXT CLK a board might sense the trigger in a certain period of the clock while another might sense it in the subsequent Therefore an uncertainty of 1 EXT CLK period would occur and then 1 SAMP CLK hit on the position of the acquired stored buffer with respect to the trigger arrival time The distribution of trigger can be simplified through the use of a daisy chain the external trigger signal is sent to the first board in the chain and this in coincidence with the TRG IN received gets triggered and generates a TRG OUT which is in turn fed to the adjacent board TRG IN and so on There is a fixed latency of few clock hits between TRG IN and TRG OUT the value of this latency depends on the loaded firmware version this latency which spreads from board to board can be easily rejected by acting on the value of the Post Trigger see S 3 3 3 in order to have acquisition windows of all modules perfectly aligned If the external trigger entering the first board is asynchronous then a one sample uncertainty occurs as described above when this uncertainty is resolved on the first board all the other ones will be aligned to it If a precise temporal relationship between trigger and samples is required such as repeated acquisitions where a j
25. example of C code that demonstrates the use of libraries and methods for an efficient readout and data analysis The users who intend to write the software on their own are suggested to start with this demo and modify it according to their needs For more details please see the WaveDump User Manual and Quick Start Guide Doc nr UM2091 GD2084 Fig 4 2 WaveDump output waveforms CAENScope is a fully graphical program that implements a simple oscilloscope it allows to see the waveforms set the trigger thresholds change the scales of time and amplitude perform simple mathematical operations between the channels save data to file and other operations CAENscope is provided as an executable file the source codes are not distributed NOTE CAENScope does not work with digitizers running DPP firmware For more details please see the CAENScope Quick Start Guide GD2484 CAEN AUTO TRIG RISING EDGE NIM Fig 4 3 CAENScope oscilloscope tab CAENUpgrader is a software composed of command line tools together with a Java Graphical User Interface for Windows and Linux OS CAENUpgrader allows in few easy steps to upload different firmware versions on CAEN boards to upgrade the VME digitizers PLL to get board information and to manage the firmware license Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 25 37 CAEN Q fools for Discovery Document type Title Revision date Revision User s Manual MUT
26. is the status of 16 LVDS Front Panel Inputs latched with board internal trigger if a post trigger NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 47 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 value is set the internal trigger is delayed respect to external one 1 PATTERN field into event headers is the status of 16 LVDS Front Panel Inputs latched with external trigger rising edge 00 General Purpose 01 Programmed I O 10 Pattern mode LVDS signals are input and their value is written into header PATTERN field see 3 3 4 1 LVDS I O 15 12 are inputs 1 LVDS I O 15 12 are outputs 0 2 LVDS I O 11 8 are inputs 1 LVDS I O 11 8 are outputs 0 LVDS I O 7 4 are inputs 1 LVDS 1 0 7 4 are outputs LVDS 1 0 3 0 are inputs 1 LVDS I O 3 0 are outputs 0 panel output signals TRG OUT CLKOUT enabled 1 panel output signals TRG OUT CLKOUT enabled in high impedance 0 TRG CLK are NIM I O Levels 1 TRG CLK are TTL I O Levels Bits 5 2 are meaningful for General Purpose I O use only 5 23 Group Enable Mask 0x8120 r w Bit 7 0 Group 7 disabled 1 Group 7 enabled 0 Group 6 disabled 1 Group 6 enabled 0 Group 5 disabled 1 Group 5 enabled 0 Group 4 disabled 1 Group 4 enabled 3 0 Group 3 disabled
27. nover where FileName is RBF BaseAdd 15 the Base Address Hex 32 bit of the V1740 image is standard default fast enables fast programming MultiRead Write with CAEN Bridge disables programming check N B it is strongly suggested to upgrade ONLY one of the stored firmware revisions generally the STD one if both revision are simultaneously updated and a failure occurs it will not be possible to upload the firmware via VME again 6 3 1 V1740 Upgrade files description The board hosts one FPGA on the mainboard and one FPGA for each of the eight channel groups The channel group FPGAs firmware is identical A unique file is provided that will updated all the FPGA at the same time ROC FPGA MAINBOARD FPGA Readout Controller VME interface FPGA Altera Cyclone EP1C20 AMC FPGA GROUP FPGA ADC readout Memory Controller FPGA Altera Cyclone EP3C16 All FPGAs can be upgraded via VMEBUS CVUpgrade utility program must be used for this purpose The programming file has the extension RBF and its name follows this general scheme v1740 revX Y W Z RBF where XY is the major minor revision number of the mainboard FPGA W Z is major minor revision number of the channel group FPGA WARNING the previous FW revision can be restored in case there is a failure when the upgrading program runs There is a jumper on the mainboard that allows to select the NPO
28. otherwise if MON out value grows in time this means that readout rate is slower than trigger rate 3 7 4 Voltage Level Mode Monitor Mode 4 In this mode MON out provides a voltage value programmable via the N parameter written in the SET MONITOR DAC register with Vmon 1 4096 N Volt 3 8 Reset Clear and Default Configuration 3 8 1 Global Reset Global Reset is performed at Power ON of the module or a VME RESET SYS RES see 5 39 It allows to clear the data off the Output Buffer the event counter and NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 31 for Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 performs a FPGAs global reset which restores the FPGAs to the default configuration It initializes all counters to their initial state and clears all detected error conditions 3 8 2 Memory Reset The Memory Reset clears the data off the Output Buffer The Memory Reset can be forwarded via either a write access to Software Clear Register see 5 5 40 or with a pulse sent to the front panel Memory Clear input see 6 3 5 3 8 3 Timer Reset The Timer Reset allows to initialize the timer which allows to tag an event The Timer Reset can be forwarded with a pulse sent to Trigger Time Tag Reset input see S 3 5 3 9 VMEBus interface The module is provided
29. range positive or negative 30MHz Bandwidth 2nd order linear phase anti aliasing low pass filter Analog Input ADC sampling clock generator PLL MODE internal reference 50MHz local oscillator PLL MODE external reference on CLK IN 100ppm tolerance Connector ERNI SMC for high density flat cable conductor spacing 0 635 mm 0 025 Programmable DAC for Offset Adjust one for 8 channels Resolution 12 bit Sampling rate up to 65 MS s simultaneously on each channel Digital Conversion Multi board synchronization one board can act as clock master External Gate Clock capability NIM TTL by S_IN input connector for burst or single sampling mode sampling clock generation supports three operating modes PLL mode internal reference 62 5 MHz local oscillator cue PLL mode external reference on Jitter lt 100ppm PLL Bypass mode External clock on CLK_IN drives directly ADC clocks External clock Frequency from 10 to 65 MHz CLK IN AC coupled differential input clock LVDS ECL PECL LVPECL CML single ended NIM TTL available using CAEN A654 cable CLK_OUT DC coupled differential LVDS output clock locked to ADC sampling clock Freq 10 50MHz generation Memory Buffer 192K sample ch or 1 5M sample ch Multi Event Buffer with independent read and write access y Programmable event size and pre post trigger Divisible into 1 1024 buffers Common External TRGIN NIM or TTL and
30. with a fully compliant VME64 VME64X interface see S 1 1 whose main features are EUROCARD 90 Format J1 P1 and J2 P2 with either 160 pins 5 rows or 96 3 rows connectors A24 A32 and CR CSR address modes D32 BLT MBLT 2eVME 2eSST data modes MGST write capability CBLT data transfers interrupter Configuration ROM 3 9 1 Addressing capabilities 3 9 1 1 Base address The module works in A24 A32 mode The Base Address of the module can be fixed through four rotary switches see S 2 6 and is written into a word of 24 or 32 bit The Base Address can be selected in the range 0x000000 gt 0xFF0000 A24 mode 31 24 23 1615 0 OFFSET Fig 3 12 A24 addressing 0x00000000 0xFFFF0000 A32 mode 31 2423 1615 0 lA SW2 SW3 1 SW4 SW5 7 0 Fig 3 13 A32 addressing NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 32 CAEN Q fools for Disi Document ine Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 The Base Address of the module is selected through four rotary switches see 6 2 6 then it is validated only with either a Power ON cycle or a System Reset see 3 6 3 9 1 2 CR CSR address GEO address is picked up from relevant backplane lines and written onto bit 23
31. 0x MUTx 13 V1740_REV13 DOC 55 51 wig far Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 41 Flash Enable OxEF2C r w 1 Flash write DISABLED This register is handled by the Firmware upgrade tool Bit 0 Flash write ENABLED 5 42 Flash Data OxEF30 r w Bit 7 0 Data to be serialized towards the SPI On board Flash This register is handled by the Firmware upgrade tool 5 43 Configuration Reload OxEF34 w Bit 0 A write access to this register causes a software reset see 5 3 6 a 31 0 reload of Configuration ROM parameters and PLL reconfiguration NPO Filename Number of pages 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 Page 52 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 6 Installation Mod V1740 fits into GU VME crates The V1740 cannot be operated with CAEN crates VME8001 8002 8004 8004A VX1740 versions require VME64X compliant crates A Use only crates with forced cooling air flow Tum the crate OFF before board insertion removal Remove all cables connected to the front panel before board insertion removal CAUTION USE ONLY CRATES WITH FORCED COOLING AIR FLOW SINCE OVERHEAT MAY DAMAGE THE MODULE CAUTION ALL CABLES MU
32. 2 ROM Address Map for the Model V1740 checksum OxA4 checksum length 0x00 checksum length1 0x00 checksum lengthO 0x20 ouid V1740 VX1740 0x11 V1740 0x00 revisO 0 01 0 00 sernumO 0x16 These data are written into one Flash page at Power ON the Flash content is loaded into the Configuration RAM where it is available for readout 5 3 Group n Threshold 0x1n80 r w 11 0 Threshold Value for Trigger Generation Each Group of channels Group 0 7 Group 1 Ch8 15 etc can generate local trigger as the digitized signal exceeds the Vth threshold This register allows to set Vth LSB input range 12bit see also 3 4 3 5 4 Group n Status 0x1n88 Bt 1 1 Function 5 Buffer free error 1 trying to free a number of buffers too large GROUPn 1 enabled GROUPn enabled GROUPn DAC see 6 5 7 Busy 2 1 Busy 0 DC offset updated 1 Memory empty 0 Memory full NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 33 41 CAEN Q Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 5 Group n AMC FPGA Firmware 0x1n8C 31 16 Revision date in Y M DD format 15 8 Firmware Revision X 0 Firmware Revision Y Bits 31 16 contain the Revision date in Y M DD format Bits 15 0 contain the firmware revision number coded on 16 bit X Y
33. AM MERETTTN 32 5 NMEBUS 2nstieceteumro o trino IMEEM aieea En MEINEN PIENO 32 3 9 1 Address rrr 32 3 9 1 1 Base e 32 LRC SR AUTES ERN 33 39 13 Address 33 3 10 DATA TRANSFER CAPABILITIES 33 3 11 RSET RTA OW od T c MI 33 RET Cound TITRE TEE 33 3 11 1 1 LEE DA B Un 34 3 11 1 2 BLOCK TRANSFER 032 064 2e VME ccsscccsssscccssscccesesccensscsessceeenscecesscsensscenenesesensscsenesces 34 3 11 1 3 CHAINED BLOCK TRANSFER 032 064 35 NS NEED UT ON O 33 3 12 M Eni P 35 23 4 08900 8 P 36 EB LUE DE NOIL QE 39 Dl REGISTERS ADDRESS PAP E A NNUS 39 5 2 CONFIGURATION OXFOOO OXFO84 966 40 5 3 GROUP N THRESHOLD OX1N80 R W 4 5 4 GROUP N STATUS Ni UR PE VE Qd Ur ME 4 3 9 GROUPN AMC FPGA FIRMWARE OXINGG
34. BLT 2eVME 2eSST and 32 64 bit Chained Block Transfer CBLT The built in daisy chainable Optical Link is able to transfer data at 80 MB s thus it is possible to connect up to eight ADC boards 512 ADC channels to a single Optical Link Controller Mod A2818 Optical Link and VME access are internally arbitrated The board is available with different input range memory and connector configuration as summarized by the following table Filename Number of pages gt Page 8 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 CAEN Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Table 1 1 Mod V1740 versions Model Inputtype SRAM Memory Optical link FPGA Form factor V1740 Single ended 192Ksamples ch EP3C16 6U VME64 V1740 V1740B Single ended 1 5Msamples ch EP3C16 6U VME64 VX1740 Single ended 192 Ksamples ch EP3C16 6U VME64X VX1740B Single ended 1 5Msamples ch EP3C16 6U VME64X 1 2 Block Diagram FRONT PANEL x64 channels FPGA ADC 6 CONTROLLER BUFFERS
35. OCK SOURCE Type Dip Switch Function Select clock source External or Internal NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 14 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 SW1 FW Type Dip Switch Function it allows to select whether the Standard STD or the Back up BKP firmware must be loaded at power on default position STD iu ER 74 1145 i T eI i E acd 2 tr E 02 DE GE j 1 111 D eeeekl er y BE 3 gi i Xi Sg gm HE TTA ua E 5 BE D Bs 1 BET 1 Hm E zu E ES S BH p EIE f i i s TEN np TER tt oh T BRE tte it i Fig 2 6 Rotary and dip switches location Number of pages gt Page 15 NPO Filename 35 00118 07 V1740x MUTx 13 V1740 REVI3 DOC Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 2 7 Technical specifications table Table 2 3 Mod V1740 technical specifications 1 unit wide VME 6U module 64 channels single ended 2 Vpp 10Vpp on request input
36. OR of all the enabled trigger sources after being synchronized with the internal clock becomes the global trigger of the board and is fed in parallel to all the channels which store an event A Trigger Out is also generated on the relevant front panel TRG OUT connector or TTL and allows to extend the trigger signal to other boards For example in order to start the acquisition on all the channels in the crate as one of the channels ramps over threshold the Local Trigger must be enabled as Trigger Out the Trigger Out must then be fed to a Fan Out unit the obtained signal has to be fed to the External Trigger Input of all the boards in the crate including the board which generated the Trigger Out signal see also the following figure NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 28 CAEN Q Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 CLOCK REF CLOCK DISTRIB SYNC S IN TRIGGER External of generated Progr Phase shift Simultaneous start of run Common to all by a master board and time reference channels OPTICAL LINK Readout and or control 80MB s up to 8 boards TRIGGER LOGIC fan out ANALOG OUTPUT Linear Sum Majority TRIGGER BUS Trigger Tagging Digital Majority Over Threshold Coincidence matrix ADCs data stream Fig 3 10
37. Organization 0x800C r w Bit 3 0 BUFFER CODE The BUFFER CODE allows to divide the available Output Buffer Memory into a certain number of blocks according to the following table NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 43 uds for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Table 5 3 Output Buffer Memory block division CODE Samples per Block 1 ch 011 8 write access to this register causes Software Clear see 3 7 This register must not be written while acquisition is running In order to obtain a number of Samples per Block from one channel different from the Table above it is necessary to use the Custom Size register 0x8020 in this case the CODE must be set larger than the Custom Size corresponding to the smallest possible value for example set 0111 code if the desired number of Samples per Block is 900 5 14 Custom Size 0x8020 r w Bit 02 Custom Size disabled Nous 40 Allows to set a Custom Number of Samples per Block from one channel relationship is Nous NSAMPLES 2 3 therefore if the desired number of Samples per Block is 900 this register must be set to 0x258 only values multiple of 3 are allowed This register must not be written while acquisition is running see 3 3 3 1 5 15 A
38. Page 24 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 28 27 26 25 24 23 22 21 2o t9 18 17 1615 14131211110 9 7 6 5 4 3 2 1 o 1010 Event size Board ID Res Pattern Group mask Trigger Time Tag HEADER 0 HEADER 1 HEADER 2 HEADER 3 DATA WORD 0 Hin m DATA WORD 1 on o NES DATA WORD 2 DATA_WORD_3 5202 DATA WORD 4 5203 8103 DATA 51 4 DATA WORD 5 e 5006 8205 5105 DATA WORD 6 10 110 50 7 52 6 51 6 50 6 7 3 0 11 0 11 0 11 8 DATA WORD 8 5207 S1C7 50 7 DATA WORD 1 DATA WORD 0 PERENNE 61 8 135 s2c1 S1C1 50 1 5260 8200 51 0 80 0 A 3 0 11 0 prey po rto stern 131 111 1 144bit Fig 3 6 Event Organization 3 3 5 Memory FULL management Bitb of Acquisition Control register see 6 5 14 allows to select Memory FULL management mode In Normal Mode the board becomes full whenever all buffers are full see 6 5 13 otherwise Always one buffer free mode it is possible to always keep one buffer free board becomes full whenever N 1buffers are full with N 2 nr of blocks see S 5 13 In Normal Mode th
39. RITY BIT 6 OF GR CONFIG REG 0 3l 5 D ADDRESSING tuns dua A UM 32 WS NIE e PNIS CNET 32 EN R ADORE eere S 33 FIG 3 15 SOFTWARE RELOCATION OF BASE ADDRESS 1 20 44 4 02 0 na rnt esee rese nere annee nnns 33 FIG 3 16 EXAMPLE OF BLT READOUT cananea ra 34 FIG 4 1 BLOCK DIAGRAM OF THE 425 36 FGA WANBDUMPOUTPUEW A VEEOBRNMS 37 FIG 4 0 CABNSCOBPE OSCILLOSCOPE TAB oue icxedutogedaptitereduvtan tesa E 27 Fic 4 4 CAENUPGRADER GRAPHICAL USER INTERFACE 38 FIG 4 5 DPP CONTROL SOFTWARE GRAPHICAL USER INTERFACE AND ENERGY PLOT 1 2 22 38 NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 6 CAEN 0 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 LIST OF TABLES MOD 9 TABLE 2 1 MODEL 1740 POWER 2 01 e sse ee esse
40. RUN ACQUISITION command see 8 3 3 1 or with respect to a buffer emptying after a MEMORY FULL status the trigger overlaps the previous one and the board is not enabled for accepting overlapped triggers As a trigger is refused the current buffer is not frozen and the acquisition continues writing on it The Event Counter can be programmed in order to be either incremented or not If this function is enabled the Event Counter value identifies the number of the triggers sent but the event number sequence is lost if the function is not enabled the Event Counter value coincides with the sequence of buffers saved and readout 3 3 3 1 Custom size events It is possible to make events with a number of Samples per block which depends on Buffer Organization register setting see 5 13 smaller than the default value Such Custom Size events can be programmed through Custom Size 0x8020 register 5 14 3 3 4 Event structure An event is structured as follows Header four 32 bit words Data variable size and format The event can be readout either via VME or Optical Link data format is 32 bit word 3 3 4 1 Header 15 composed by four words namely Size of the event number of 32 bit words NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 23 uds lor Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Chan
41. ST BE REMOVED FROM THE FRONT PANEL BEFORE EXTRACTING THE BOARD FROM THE CRATE 6 1 Power ON sequence To power ON the board follow this procedure 1 insert the V1740 board into the crate 2 power up the crate 6 2 Power ON status At power ON the module is in the following status e Output Buffer is cleared e registers are set to their default configuration see S 3 12 6 3 Firmware upgrade The board can store two firmware versions called STD and BKP respectively at Power On a microcontroller reads the Flash Memory and programs the module with the firmware version selected the JP2 jumper see 2 6 which can be placed either the STD position left or in the BKP position right It is possible to upgrade the board NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 53 ools for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 firmware via VME by writing the Flash for this purpose download the software package available at www caen it website The package includes the new firmware release file 1740 revX Y W Z rbf and the V1740 firmware upgrade tool CVUpgrade exe windows executable e CVUpgrade tool source code and VC project For upgrading the firmware utilizing CVUpgrade exe open a DOS shell then launch CVUpgrade FileName BaseAdd image fast
42. T echnical Information M anual Revision n 13 20 September 2011 MOD V1740 64 CHANNEL 12 BIT 65 M S S DIGITIZER MANUAL REV 13 NPO 00118 07 V 1740x M UT x 13 CAEN will repair or replace any product within the guarantee period if the Guarantor declares that the product is defective due to workmanship or materials and has not been caused by mishandling negligence on behalf of the User accident or any abnormal conditions or operations CAEN declines all responsibility for damages or injuries caused by an improper use of the Modules due to negligence on behalf of the User It is strongly recommended to read thoroughly the CAEN User s Manual before any kind of operation 4 CAEN reserves the right to change partially or entirely the contents of this Manual at any and without giving any notice Disposal of the Product The product must never be dumped in the Municipal Waste Please check your local regulations for disposal of electronics products MADE IN ITALY We stress the fact that all the boards are made in Italy because in this globalized world where getting the lowest possible price for products sometimes translates into poor pay and working conditions for the people who make them at least you know that who made your board was reasonably paid and worked in a safe environment this obviously applies only to the boards marked MADE IN ITALY we can not attest to the manufacturing process of third party boa
43. Trigger integration 3 5 Front Panel l Os The V1740 is provided with 16 programmable general purpose LVDS I O signals Signals can be programmed via VME see 6 5 21 and 5 5 22 Default configuration is NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740 REV13 DOC 55 29 uds for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Table 3 1 Front Panel I Os default setting RESERVED SSS E SSS 3 6 Test pattern generator The FPGA AMC can emulate the ADC and write into memory a ramp 0 1 2 3 3FFF 3FFF 3FFE 0 for test purposes It can be enabled via Channel Configuration register see 5 5 9 3 7 Analog Monitor The board houses a 12bit 100MHz DAC with 0 1 V dynamics on a 50 Ohm load see Fig 1 1 whose input is controlled by the ROC FPGA and the signal output driving 50 Ohm is available on the MON 2 output connector MON output of more boards can be summed by an external Linear Fan In This output is delivered by a 12 bit DAC The DAC control logic implements four operating modes Trigger Majority Mode Monitor Mode 0 Test Mode Monitor Mode 1 Buffer Occupancy Mode Monitor Mode 3 Voltage Level Mode Monitor Mode 4 Operating mode is selected via Monitor Mode register see 5 28 Monitor Mode 2 is reserved for future implementation 3 7 1 Trigger Majority
44. VME Command Trigger Individual channel auto trigger time over under threshold TRGOUT NIM or TTL for the trigger propagation to other V1740 boards Trigger Time Stamp 320 LSB 8ns FSR 17s Sync input for Time Stamp alignment ADC and Memory controller FPGA Altera Cyclone EP3C16 for 16 channels Optical Link Data readout and slow control with transfer rate up to 80 MB s to be used instead of VME bus Daisy chainable one A2818 PCI card can control and read eight V1740 boards in a chain VME64X compliant D32 BLT32 MBLT64 CBLT32 64 2eVME 2eSST Multi Cast Cycles VME interface Transfer rate 60 5 MBLT64 100MB s 2eVME 160MB s 2eSST Sequential access to the data of the Multi Event Buffer The Chained readout allows to read one event from all the boards in a VME crate with a BLT access Upgrade V1740 firmware can be upgraded via VME Software General purpose C Libraries and Demo Programs CAENScope 16 general purpose LVDS controlled by the FPGA LVDS I O Busy Data Ready Memory full Trig Out flag and other function can be programmed An Input Pattern from the LVDS I O can be associated to each trigger as an event marker NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 16 uds for Discover Revision date Revision Document type Title 13 User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 3 Functional description 3 1 Analog
45. are SRAMs VMEBus does not handle directly the addresses but takes them from a FIFO Therefore data are read from the memories sequentially according to the selected Readout Logic from a memory space mapped on 4Kbytes 0 0000 0 The events readout sequentially and completely starting from the Header of the first available event followed by the Trigger Time Tag the Event Counter and all the samples of the channels from 0 to 7 Once an event is completed the relevant memory buffer NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 33 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 NPO becomes free and ready to be written again old data are lost After the last word in an event the first word Header of the subsequent event is readout It is not possible to readout an event partially 3 11 1 1 SINGLE D32 This mode allows to readout a word per time from the header actually 4 words of the first available event followed by all the words until the end of the event then the second event is transferred The exact sequence of the transferred words is shown in S 3 3 4 We suggest after the 1 word is transferred to check the Event Size information and then do as many D32 cycles as necessary actually Event Size 1 in order to read completely the event 3 11 1 2
46. channels within Group n to generate a local trigger as the digitized signal of one enabled channel in the group exceeds the Vth threshold see 5 3 4 3 10 enables to generate the trigger biti enables Ch1 to generate the trigger and so on In order to generate the trigger the Group n itself must be enabled via Group Trigger Source Enable Mask see 6 5 18 5 10 Group Configuration 0x8000 r w y 0 Trigger Output on Input Over Threshold 1 Trigger Output on Input Under Threshold allows to generate local trigger either on channel over or under threshold see 5 3 and 5 3 4 reserved MUST ALWAYS BE SET TO 1 3 0 Test Pattern Generation Disabled 1 Test Pattern Generation Enabled 0 Trigger Overlapping Not Enabled 1 1 Trigger Overlapping Enabled Allows to handle trigger overlap see S 3 3 3 0 Window Gate 1 Single Shot Gate Allows to handle samples validation see S 3 3 1 This register allows to perform settings which apply to all groups It is possible to perform selective set clear of the Group Configuration register bits writing to 1 the corresponding set and clear bit at address 0x8004 set or 0x8008 clear see the following 6 5 11 and 6 5 12 Default value is 0 10 5 11 Group Configuration Bit Set 0x8004 w ra Configuration register are to 1 5 12 Group Configuration Bit Clear 0x8008 w Es T Configuration register are set to 0 5 13 Buffer
47. cquisition Control 0x8100 r w Bit 0 Normal Mode default board becomes full whenever all buffers 5 are full see S 5 13 1 Always keep one buffer free board becomes full whenever N 1buffers are full N 2 nr of blocks see S 5 13 0 COUNT ACCEPTED TRIGGERS 1 COUNT ALL TRIGGERS allows to reject overlapping triggers see 5 3 3 3 0 Acquisition STOP 1 Acquisition RUN allows to RUN STOP Acquisition 00 REGISTER CONTROLLED RUN MODE 01 2 S IN CONTROLLED RUN MODE 10 S IN GATE MODE 11 MULTI BOARD SYNC MODE Bit 2 allows to Run and Stop data acquisition when such bit is set to 1 the board enters Run mode and a Memory Reset see 5 3 8 2 is automatically performed When bit 2 is reset to O the stored data are kept available for readout In Stop Mode all triggers are neglected Bits 1 0 descritpion NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 33 44 uds for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 00 REGISTER CONTROLLED RUN MODE multiboard synchronization via S IN front panel signal RUN control start stop via set clear of bit 2 GATE always active Continuous Gate Mode Continuous Gate Mode can be used only if Gate mode see 5 9 is set in Window Mode 01 S IN CONTROLLED RUN MODE Multiboard synchronization via S IN fro
48. d as gate to enable samples storage The samples produced by the 65MHz ADC are stored in memory only if they are validated by the S IN signal otherwise they are rejected one sample per channel is stored at each clock hit in coincidence with S IN see data format at 3 3 4 The values sampled as the S IN signal is active high are stored SxCy means Sample x of Channel y etc 52 0 52 7 53 0 53 7 S1CO S1C7 SOCO SOC7 ADC DATA X D X D2 X D3 X na X Ds X X D7 X X D 10 D 11 D12 S IN D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D2 D3 D3 D3 D3 D3 D3 D3 D3 D3 D3 04 04 04 04 04 04 04 04 04 D5 D5 D5 D5 D5 D5 D5 D5 BUFFER 06 06 06 06 06 06 06 09 09 D9 D9 Fig 3 4 Data Storage underscored stored 3 3 3 Acquisition Triggering Samples and Events When the acquisition is running a trigger signal allows to storea Trigger Time Tag TTT the value of a 32 bit counter which steps with 125 MHz frequency and represents a time reference increment the EVENT COUNTER see 5 25 fill the active buffer with the pre post trigger samples whose number is programmable Acquisition window width S 5 20 freezing then the buffer for readout purposes while acquisition continues on another buffer buffer siz
49. d jitter Occurs 3 4 2 Software trigger ooftware trigger are generated via VME bus write access in the relevant register see 5 17 3 4 3 Local channel group auto trigger Each channel group 0 7 8 15 56 63 can generate local trigger as the digitized signal on one of the enabled channels see 5 9 exceeds the Vth threshold ramping up or down depending on VME settings The Vth digital threshold is programmable via VME register accesses see 6 5 3 the trigger is produced on the leading edge of the OR of the Over or Under depending on Trigger Output bit setting of Group Configuration see 5 10 Threshold signal of the enabled channels therefore in case of Trigger Output bit of Group Configuration set to Trigger Output on Input Over Threshold if a NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REV13 DOC 55 26 TIE lor Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 NPO channel is always over threshold its over threshold flag is always set to 1 and does not produce the trigger N B the local trigger signal does not start directly the event acquisition on the group that generated it such signal is propagated to the central logic which produces the global trigger which is distributed to all groups see 3 4 4 THRESHOLD GRO Local Trigger Grou
50. e board waits until one buffer is filled since FULL status is exited whether the trigger is overlapped or not The board exits FULL status at the moment which the last datum from the last channel participating to the event is read In Always one buffer free mode one buffer cannot be used therefore it is NOT POSSIBLE with this mode to set Buffer Code to 0000 see 5 13 but this allows to eliminate dead time when FULL status is exited NPO Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 25 CAEN Tools for Discovery Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 3 4 Trigger management All the channels in a board share the same trigger this means that all the channels store an event at the same time and in the same way same number of samples and same position with respect to the trigger several trigger sources are available Mother Board Mezzanines Memory Buffers TRG OUT Acquisition Logic zs Local Bus Interface Interface Fig 3 7 Block diagram of Trigger management 3 4 f External trigger External trigger can be NIM TTL signal on LEMO front panel connector 50 Ohm impedance The external trigger is synchronized with the internal clock see 3 2 3 if External trigger is not synchronized with the internal clock a one clock perio
51. e is programmable see Buffer Organization Ox800C register 8 5 13 An event is therefore composed by the trigger time tag pre and post trigger samples and the event counter Overlap between acquisition windows may occur a new trigger occurs while the board is still storing the samples related to the previous trigger this overlap can be either rejected or accepted programmable via VME If the board is programmed to accept the overlapped triggers as the overlapping trigger arrives the current active buffer is filled up then the samples storage continues on the subsequent one In this case events will not have all the same size see figure below Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 53 22 wis for D Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 EVENT n EVENT 1 EVENT n 2 Hecorded Not Recorded TRIGGER PRE POST ACQUISITION WINDOW Overlapping Triggers Fig 3 5 Trigger Overlap A can be refused for the following causes acquisition is not active memory is FULL and therefore there are no available buffers the required number of samples for building the pre trigger of the event is not reached yet this happens typically as the trigger occurs too early either with respect to the
52. ecessary to use the external clock For such purpose two solutions are possible a daisy chain where the clock is propagated from one board to another with the first board used as a clock master whose source could be either the internal clock or an external reference managed by the User tree structure with an equalized clock distributor fan out unit with low skew outputs and constant cables length In both cases the goal is to have all REF CLK signals with the same phase Since the PLL aligns the phase of VCXO output signal to REF CLK the result of synchronization is that all V1740s have the 500MHz VCXO output signals perfectly aligned in phase However despite the V1740s having all the same 500MHz reference it is not guaranteed that the sampling clock is in its turn aligned In fact the use of clock dividers to produce the sampling clock may lead such signals to have different phases as shown in the following picture where two 250MHz divider 2 see 5 3 2 2 are obtained from a 500MHz VCXO output 5 1 5 2 Fig 3 3 Sampling clock phase shift Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 53 20 F1 Document type Title Revision date Revision
53. format Example revision 1 3 of 12 June 2007 is 0x760C0103 5 6 Group n Buffer Occupancy 0x1n94 r 0 0 Occupied buffers 0 1024 5 7 Group n DAC 0x1m98 r w 15 0 DAC Data Bits 15 0 allow to define a DC offset to be added the input signal in the 1 range low range or in the 5V range high range see also 3 1 There is a DAC serving eight 8 channel groups Group 0 ChO 7 Group 1 Ch8 15 etc When Group n Status bit 2 is set to 0 DC offset is updated see 6 5 4 5 8 Group n ADC Configuration 0x1n9C r w 31 0 Reserved 5 9 Group n Channel Trigger Mask 0x1nA8 r w 0 Channel 7 trigger disabled 1 Channel 7 trigger enabled 0 Channel 6 trigger disabled 1 Channel 6 trigger enabled m 0 Channel 5 trigger disabled 1 Channel 5 trigger enabled 0 Channel 4 trigger disabled 1 Channel 4 trigger enabled 0 Channel 3 trigger disabled 1 Channel 3 trigger enabled 0 Channel 2 trigger disabled 1 Channel 2 trigger enabled 1 0 Channel 1 trigger disabled 1 Channel 1 trigger enabled 0 Channel 0 trigger disabled 1 Channel 0 trigger enabled 7 5 4 3 2 NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 42 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 This register bits 0 7 enable the
54. fset of the input signal can be adjusted for group of 8 channels by a programmable 16bit DAC The modules feature a front panel clock reference In Out and a PLL for clock synthesis from internal external references This allows multi board phase synchronizations to an external clock reference or to a clock Digitizer master board The data stream is continuously written in a circular memory buffer When the trigger occurs the FPGA writes further N samples for the post trigger and freezes the buffer that can be read either via VME or via Optical Link The acquisition can continue without dead time in a new buffer VME and Optical Link accesses take place on independent paths and are handled by the on board controller therefore when accessed through Optical Link the board can be operated outside the VME Crate see 2 1 Each Group has a SRAM memory see Table below with independent read write access divided in buffers 1 1024 of programmable size The trigger signal can be provided via the front panel input as well as via the VMEbus but it can also be generated internally The trigger from one board can be propagated to the other boards through the front panel Trigger Output An Analog Output allows to reproduce the sum of the input signals as well as the majority of the buffer occupancy The Modules VME interface is VME64X compliant and the data readout can be performed in Single Data Transfer D32 32 64 bit Block Transfer BLT M
55. ge 00118 07 V1740x MUTx 13 V1740_REV13 DOC 55 45 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 18 Trigger Source Enable Mask 0x810C r w Bit 31 0 Software Trigger Disabled 1 Software Trigger Enabled 0 External Trigger Disabled 1 External Trigger Enabled 29 27 27 Local trigger coincidence level default 0 reserved 7 0 Group 7 trigger disabled 1 Group 7 trigger enabled 0 Group 6 trigger disabled 1 Group 6 trigger enabled 0 Group 5 trigger disabled 1 Group 5 trigger enabled 0 Group 4 trigger disabled 1 Group 4 trigger enabled 0 Group 3 trigger disabled 1 Group 3 trigger enabled 0 Group 2 trigger disabled 1 Group 2 trigger enabled 0 Group 1 trigger disabled 1 Group 1 trigger enabled 0 Group 0 trigger disabled 1 Group 0 trigger enabled This register bits 0 7 enable the groups generate a local trigger as the digitized signal of the channels enabled via Group n Channel Trigger Mask see 6 5 9 exceeds the Vth threshold see 3 4 3 enables GroupO to generate the trigger bit enables Group1 to generate the trigger and so on Bits 26 24 allows to set minimum number of groups with at least one enabled channel over threshold beyond the triggering group in order to actually generate the local trigger signal for example if bit
56. gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 19 for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 NPO VCXO Out 3 2 6 PLL programming In PLL mode the User has to enter the divider for input clock frequency input clock PLL mode via CAENupgrader since the VCXO frequency is 500 MHz in order to use for example a 50MHz ExtCIk the divider to be entered is 20 Then it is necessary to set the parameters for sampling clock and CLK OUT enable frequency and delay in Output Clock field via CAENupgrader the tool refuses wrong settings for such parameters 3 2 7 Direct Drive BYPASS programming In BYPASS mode the User can directly set the input frequency Input Clock field real values are allowed Given an input frequency it is possible to set the parameters in order to provide the required signals 3 2 8 Configuration file Once all parameters are set the tool allows to save the configuration file which includes all the AD9510 device settings see CAENupgrader documentation It is also possible to browse and load into the AD9510 device a pre existing configuration file see CAENupgrader documentation For this purpose it is not necessary the board power cycle 3 2 9 Multi board synchronization In order to allow several 1 7405 to work synchronously same sampling clock for all channels it is n
57. itter on the position of the signal in the acquisition window is a major issue it is suggested to use one input channel among all the V1740s in the chain to sample the trigger signal itself this will allow to reconstruct off line the trigger edge position in the acquisition window with a resolution smaller than the sampling period through interpolation Acquisition Modes 9 9 1 Acquisition run stop NPO The acquisition can be started in two ways according to Acquisition Control register Bits 1 0 setting see S 5 14 setting the RUN STOP bit bit 2 in the Acquisition Control register bits 1 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE or S IN CONTROLLED RUN MODE driving S IN signal high bits 1 0 of Acquisition Control must be set to 01 Therefore acquisition is stopped either Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 53 21 PERTE CAEN for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 NPO SAMPLING CLOCK resetting the RUN STOP bit bit 2 in the Acquisition Control register bits 1 0 of Acquisition Control must be set to REGISTER CONTROLLED RUN MODE or S IN CONTROLLED RUN MODE driving S IN signal low bits 1 0 of Acquisition Control set to 01 3 3 2 Data acquisition and storage The S IN signal see 5 2 4 2 can be use
58. nel 12bit 65MS s Digitizer 20 09 2011 13 NPO 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 Board ID GEO 16 bit pattern latched on the LVDS I O as one trigger arrives Group Mask 21 Groups participating to event ex GR5 and participating Gr Mask OxAQ this information must be used by the software to acknowledge what Group the samples are coming from the first event contains the samples from the Group with the lowest number Event Counter It is the trigger counter it can count either accepted triggers only or all triggers see S 5 14 Trigger Time Tag is a 32 bit counter 31 bit count 1 overflow bit which is reset either as acquisition starts or front panel Reset signal see S 3 6 and is incremented at each sampling clock hit It is the trigger time reference 3 3 4 2 Samples otored samples data from masked channels are not read 3 3 4 3 Event format examples An event is structured as follows identifier Trigger Time Tag Event Counter samples caught in the acquisition windows The event can be stored in the board memories and can be readout via VME Optical Link data format is 32 bit word SxCy means Sample x of Channel y etc The event format is therefore the following N B data transfer starts from Channel 0 of Group 0 once all the data from one Group are transferred data transfer from the subsequent Group from 0 to 7 begins Filename Number of pages
59. ng trigger logic acquisition logic samples storage into RAM buffer freezing on trigger through a clock chain Such domain can use either external via front panel signal or an internal via local oscillator source selection is performed via dip switch SW1 see 2 6 in the latter case OSC CLK and REF CLK will be synchronous the operation mode remains the same anyway NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REV13 DOC 55 18 for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 NPO HEF CLK is processed by AD9510 device which delivers 6 clock out signals 4 signals are sent to ADCs one to the trigger logic and one to drive CLK OUT output refer to AD9510 data sheet for more details http www analog com UploadedFiles Data Sheets AD9510 pdf two operating modes are foreseen Direct Drive Mode and PLL Mode 3 2 1 Direct Drive Mode The aim of this mode is to drive externally the ADCs Sampling Clock generally this is necessary when the required sampling frequency is not a VCXO frequency submultiple The only requirement over the SAMP CLK is to remain within the ADCs range It is important to say that Direct Drive is the only way to achieve the full ADC 65 MS s sampling frequency since PLL dividers allow a maximum 62 5 MS s one 3 2 2 PLL Mode The AD9510 features an in
60. nt panel signal S IN works both as SYNC RUN START command GATE always active Continuous Gate Mode Continuous Gate Mode Gate always active to be used only if Gate Mode GROUP Configuration Register is set to Window Mode 10 S IN GATE MODE Multiboard synchronization is disabled J S IN works as Gate signal set clear of RUN STOP bit 11 MULTI BOARD SYNC MODE A Used only for Multiboard synchronization 5 16 Acquisition Status 0x8104 Bit Board ready for acquisition PLL and ADCs are synchronized correctly 0 not ready 1 ready This bit should be checked after software reset to ensure that the board will enter immediatly run mode after RUN mode setting otherwise a latency between RUN mode setting and Acquisition start might occur PLL Status Flag see 2 5 1 0 PLL loss of lock 1 no PLL loss of lock NOTE flag can be restored to 1 via read access to Status Register see S 5 31 PLL Bypass mode see 5 2 5 1 0 No bypass mode 1 Bypass mode Clock source see 2 6 5 0 Internal 1 External EVENT FULL itis setto 1 as the maximum nr of events to be read is reached 3 EVENT READY it is set to 1 as atleast one event is available to readout 0 RUN off 21 1 RUNon 1 0 reserved 5 17 Software Trigger 0x8108 w Bit 31 0 A write access to this location generates a trigger via software NPO Filename Number of pages gt Pa
61. of the channel in the enabled group exceeds the Vth threshold see S 3 4 3 enables GroupO to generate the OUT bit enables Group to generate the OUT and so on EXTERNAL TRIGGER ENABLE bit30 enables the board to generate the OUT SW TRIGGER ENABLE bit 31 enables the board to generate OUT see 5 17 5 20 Post Trigger Setting 0x8114 r w 31 0 Post trigger value The register value sets the number of post trigger samples The number of post trigger samples is Npost PostTriggerValue ConstantLatency where Npost number of post trigger samples PostTriggerValue Content of this register this is NOT the actual number of post trigger samples ConstantLatency constant number of samples added due to the latency associated to the trigger processing logic in the ROC FPGA This value is constant but the exact value may change between different firmware revisions 5 21 Front Panel 1 0 Data 0x8118 r w Bit Front Panel Data Allows to Readout the logic level of LVDS I Os and set the logic level of LVDS Outputs 5 22 Front Panel I O Control 0x811C r w Bit 0 Normal operations TRG OUT signals outside trigger presence trigger are generated according to Front Panel Trigger Out Enable Mask setting see S 5 19 12 I O Test Mode TRG OUT is a logic level set via bit 14 0 2 TRG OUT Test Mode set to 0 PATTERN LATCH MODE 0 PATTERN field into event headers
62. pO Group Configuration register 6 0 Local Trigger GroupO Group Configuration register 6 1 Fig 3 8 Local trigger generation 3 4 3 1 Trigger coincidence level It is possible to set the minimum number of groups with at least one channel that must be over threshold beyond the triggering group in order to actually generate the Local channel group auto trigger signal If for example Trigger Source Enable Mask see 5 5 18 bits 7 0 FF all groups enabled and Local trigger coincidence level 1 bits 26 24 whenever an enabled channel exceeds the threshold the trigger will be generated only if at least another enabled channel in another group is over threshold at that moment Local trigger coincidence level must be smaller than the number of channels enabled bit 7 0 mask The following figure shows examples with Local trigger coincidence level 1 and 0 Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 21 TIE lor Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 GRO THRESHOLD GRO CHx enabled IN N GR1_CHx THRESHOLD GR1 CHx enabled IN LOCAL TRG groupo TRIGGER Coinc lev 1 TRIGGER Coinc lev 0 Fig 3 9 Local trigger relationship with Coincidence level 3 4 4 Trigger distribution The
63. pe connector to be used with Multimode 62 5 125um cable with LC connectors on both sides see also 5 3 12 CAEN provides optical fiber cables with a duplex connector on the A2818 side and two simplex connectors on the board side the simplex connector with the black wrap is for the RX line lower and the one with the red wrap is for the TX higher Electrical specifications Optical link for data readout and slow control with transfer rate up to 80MB s TX RX daisy chainable 2 5 Other front panel components 2 5 1 Displays The front panel hosts the following LEDs Table 2 2 Front panel LEDs Name Colour Function DTACK VME read write access to the board CLK IN External clock enabled INIM Standard selection for CLK I O TRG OUT TRG IN S IN Standard selection for CLK TRG OUT TRG IN S IN LINK green yellow Network present Data transfer activity PLL LOCK The PLL is locked to the reference clock PLL BYPS green The reference clock drives directly ADC clocks the PLL circuit is switched off and the PLL LOCK LED is turned off green RUNbBitset see 5 16 green Trigger accepted DRDY green Event data depending on acquisition mode are present in the Output Buffer All the buffers are full OUT LVDS Signal group OUT direction enabled 2 6 Internal components SW2 4 5 6 Base Addr 31 16 Type 4 rotary switches Function Set the VME base address of the module SW3 CL
64. rds ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 TABLE OF CONTENTS L GENERAL DESCRIPHON 8 Me VT Wass HHPP 9 M BITE T Nm 9 2 TECHNICAL SPECIFIC XT IONS eesocesvezsassdepeuso eue ue eee OU aeo er v apo aaa ooa ao 10 2 1 PACKAGING AND COMPLIANCY ERA EE rana hestinun apa beard pU b Er EVO ri 10 22 POWERREQUIREMENI S 10 22 11 9r EXTERNAL CONNECTORS NU mmm 12 2 4 I ANALOG INPUT connectors UM 12 2 4 2 CONTROL GOMBOCIOPS ee ee CE aC eT D MM M LIE ere ya eee re 12 2 4 3 ADC REFERENCE CLOCK 00 sente eeeete sete sese e sese sese se ese se esee seen 13 2 4 4 DIUI O RIEN 13 2 4 5 ODDCOEDNR ION rete 14 2 5 OTHER FRONT PANEL 2 0 0 14 2 3 1 14 20 JJINTERNADCOMPONEN ES 14 2 7 TECHNICAL SPECIFICATIONS
65. t as an external plotting tool exactly like in WaveDump NOTE so far DPP Control Software is developed for Mod x724 and Mod x720 digitizer series Control Software n Electronic Settings Mode Channel Channel 0 IT Basic Advanced gnuplot graph Energy Histogram e c Settings Channel Enabled Copy Settings DC Offset Input Digital Gain 1 Decimation 1 M Pulse Polarity POSITIVE Trigger and Timing Filter Energy Filter Decay Time Threshold Rise Time Smoothing Factor Delay b y 0 Baseline Mean Holdoff Trapezoid Gain Peaking Delay RT Discrimination Window Peak Mean m z si Enabled Width 025 Baseline Holdoff AES us Peak Holdaff E us 4000 ADC channels 8165 49 7022 17 Fig 4 5 DPP Control Software Graphical User Interface and Energy plot NPO Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740 REV13 DOC 55 38 ols for Discover Document type Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 5 VME Interface The following sections will describe in detail the board s VME accessible registers content N B bit fields that are not described in the register bit map are reserved and must not be over written by the User 5 1
66. ternal Phase Detector which allows to couple REF CLK with VCXO 500 MHz frequency for this purpose it is necessary that REF CLK is a sub multiple of 500 MHz AD9510 default setting foresees the board internal clock 50MHz as clock source of REF CLK This configuration leads to 100 thus obtaining 10MHz at the Phase Detector input and CLK INT 500 MHz The required Sampling Clock 62 5MHz max is obtained by processing CLK INT through Sdiv dividers When an external clock source is used if it has 62 5MHz frequency then AD9510 programming is not necessary otherwise Ndiv and have to be modified in order to achieve PLL lock A REF CLK frequency stability better than 100ppm is mandatory 3 2 3 Trigger Clock TRG CLK signal has a frequency equal to of SAMP CLK therefore 2 samples uncertainty occurs over the acquisition window 3 2 4 Output Clock Front panel Clock Output is User programmable Odiv and Odel parameters allows to obtain a signal with the desired frequency and phase shift in order to recover cable line delay and therefore to synchronize daisy chained boards CLK OUT default setting is OFF it is necessary to enable the AD9510 output buffer to enable it 3 2 5 AD9510 programming CAEN has developed a software tool which allows to handle easily the clock parameters the CAENupgrader see www caen it path Products Front End VME Controller VME Filename Number of pages
67. ual MUT Mod V1740 64 Channel 12bit 65MS s Digitizer 20 09 2011 13 Title Revision date Revision 4 Software tools NPO CONET2 Optical Link Fig 4 1 Block diagram of the software layers CAEN provides drivers for both the physical communication channels the proprietary CONET Optical Link managed by the A2818 PCI card or A3818 PCle cards and the VME bus accessed by the V1718 and V2718 bridges a set of and LabView libraries demo applications and utilities Windows and Linux are both supported The available software is the following CAENComm library contains the basic functions for access to hardware the aim of this library is to provide a unique interface to the higher layers regardless the type of physical communication channel Note for VME access CAENcomm is based on CAEN s VME bridges V1718 USB to VME and V2718 PCI PCle to VME In the case of third part bridges or SBCs the user must provide the functions contained in the CAENcomm library for the relevant platform The CAENComm requires the CAENVMELib library to be installed even in the cases where the VME is not used CAENDigitizer is a library of functions designed specifically for the digitizer family and it supports also the boards running special DPP Digital Pulse Processing firmware The purpose of this library is to allow the user to open the digitizer program it and manage the data acquisition in an easy way with few lines of code the
68. user can make a simple readout program without the necessity to know the details of the registers and the event data format The CAENDigitizer library implements a common interface to the higher software layers masking the details of the physical channel and its protocol thus making the libraries and applications that rely on the CAENDigitizer independent from the physical layer The library is based on the CAENComm library that manages the communication at low level read and write access CAENVMELib and CAENComm libraries must be already installed on the host PC before installing the CAENDigitizer however both CAENVMELib and CAENComm libraries are completely transparent to the user WaveDump is a Console application that allows to program the digitizer according to a text configuration file that contains a list of parameters and instructions to start the acquisition read the data display the readout and trigger rate apply some post processing such as FFT and amplitude histogram save data to a file and also plot Filename Number of pages gt Page 00118 07 V1740x MUTx 13 V1740_REV13 DOC 25 36 Tools for Discever Document type n Title Revision date Revision User s Manual MUT Mod V1740 64 Channel 12bit 65 5 5 Digitizer 20 09 2011 13 NPO the waveforms using the external plotting tool gnuplot available on internet for free This program is quite basic and has no graphics but it is an excellent
69. ved by accessing VME Control register see 5 30 and disabling the active interrupt level In ROAK mode interrupt status is automatically removed via an interrupt acknowledge cycle Interrupt generation is restored by setting an Interrupt level 0 via VME Control register 5 31 VME Status OxEF04 Bit 3 0 VME FIFO not empty 1 VME FIFO empty 0 BERR FLAG no Bus Error has occurred 2 1 BERR FLAG Bus Error has occurred this bit is re set after status register read out 1 0 No Data Ready 1 5 32 Board ID 0 08 4 0 GEO VME64X versions this register be accessed in read mode only and contains the GEO address of the module picked from the backplane connectors when CBLT is performed the GEO address will be contained in the EVENT HEADER Board ID field see 3 3 4 1 Other versions this register can be accessed both in read and write mode it allows to write the correct GEO address default setting 0 of the module before CBLT operation GEO address will be contained in the EVENT HEADER Board ID field 5 33 MCST Base Address and Control OxEFOC r w These bits contain the most significant bits of the MCST CBLT address of the module set via VME i e the address used in MCST CBLT operations Allows to set up the board for daisy chaining 00 disabled board 01 last board 10 first board 11 intermediate
70. where the previous cycle has ended 1 2 Event Polling A read access to Event Size register see 5 28 allows polling the number of 32 bit words composing the next event to be read this permits to perform a properly sized according to the Event Size information BLT readout from the Memory Event Buffer Optical Link The board houses a daisy chainable Optical Link communication path which uses optical fiber cables as physical transmission line able to transfer data at 80 MB s therefore it is possible to connect up to eight V1740 to a single Optical Link Controller for more information see www caen it path Products Front End PCI PCle Optical Controller The parameters for read write accesses via optical link are the same used by VME cycles Address Modifier Base Address data Width etc wrong parameter settings cause Bus Error VME Control Register bit 3 allows to enable the module to broadcast an interrupt request on the Optical Link the enabled Optical Link Controllers propagate the interrupt on the PCI bus as a request from the Optical Link is sensed VME and Optical Link accesses take place on independent paths and are handled by board internal controller with VME having higher priority anyway it is better to avoid accessing the board via VME and Optical Link simultaneously Filename Number of pages Page 00118 07 V1740x MUTx 13 V1740 REVI3 DOC 55 35 CAEN Tools for Discovery Document type User s Man
71. xp EUR s nese 11 FiG 2 2 ERNISMC CONNECTORS E aN na a anr Ea in Ei a a a iaia 12 2 3 AMP CLR IN OUT CONNECTOR oE EE E NE 13 FIG 2 4 PROGRAMMABLE IN OUT CONNECTOR 13 OPPHOADLCONUNBOTOR 14 FIG 2 6 ROTARY AND DIP SWITCHES ee ee nenne nu sesso s sese aseo ees orte ee eret 15 MeN oe Sosa cease c 17 CLOCK DISTRIBUTION DEA GRAIG ae ie 18 PHASE Troer cet 20 FIG 3 4 DATA STORAGE UNDERSCORED STORED cccceeccscceecesceceseceseceseuceeceuceseseuceeseecseeeeseecesecenceseeees 22 Ig Eee IY neie EEEE E E EE EEE 23 Pa EVE TOR ATT ATION c E A EE E E EEEE E E AE E ET 22 FIG 3 7 BLOCK DIAGRAM OF TRIGGER MANAGEMENT 26 FIG 3 8 LOCAL TRIGGER GENERATION MATIN ET 21 FIG 3 9 LOCAL TRIGGER RELATIONSHIP WITH COINCIDENCE nnne nnne nene 28 DIG S DIOE TRIGGERHINTEGRATION RUD Uode P E 20 3 11 MAJORITY LOGIC 2 TRIGGERING GROUPS POLA

CAEN V1740 64ch/12bit@65Msps rev13

Contents

Download Pdf Manuals

Related Search

Related Contents