CORELIS
Contents
1. TCK range MHz Rate Resolution MHz 25 to 80 1 12 5 to 25 0 5 6 25 to 12 5 0 25 5 to 6 25 0 125 2 5to5 0 10 1 25 to 2 5 0 05 0 62 to 1 25 0 025 0 39 to 0 62 0 0156 0 05 to 0 39 0 05 Table 1 1 Programmable TCK Frequencies Features of the ScanTAP 4 The Corelis ScanTAP 4 Multiple TAP Intelligent pod connects to the PCI 1149 1 Turbo boundary scan controller via the 68 pin SCSI II type HOST connector No external power supply is tequited the PCI 1149 1 Turbo card supplies it Differential signal driving supports cables of up to 30 feet Automatic delay mechanisms compensate for transport delays through the cable The four TAPs are individually configurable for interface voltages from 1 25 to 3 3 V On board voltage translation logic allows a host to chain these TAPs together or to configure them for gang programming During gang programming each TAP drives the same data out to up to four targets and simultaneously programs and verifies them Optional Slow Slew rate Voltages limited to 1 8 V to 3 3 V for slow slew is provided Each TAP can detect power shorts to ground for up to 2 voltages per TAP with user provided test software allowing the ScanTAP 4 to detect potentially damaging conditions before the target system s is powered up Refer to Chapter 4 for further explanation on how to configure the ScanTAP 4 when using ScanPlus Runner software Product Overview 1 5 PCI 1149 1 Turbo Spe2. Table 1 3 ScanTAP 4 SPI Interface DC Characteristics 1 8 Product Overview I2C Interface Scan TAP 4 with Blue LED Only The ScanTAP 4 I2C interface has open drain outputs and the SDA SCL signals must be pulled up to 3 3V Vpp by the target SCL frequency Signal DC Characteristics 100 kHz See Table 1 4 Symbol Test Conditions Limit Min Limit Max Units Vop 3 0 3 6 V Vig Vpp gt 3 3 V 2 0 3 6 V Vi Vbp gt F 3 3 V 0 5 0 8 V Io 16 mA Vo 0 0 0 4 V Iot Vix 3 3 V 16 mA Table 1 4 ScanTAP 4 12C Interface DC Characteristics Product Overview Power Short Test Pins Power Vcc Sense Pins Two per TAP Vcc1 Vcc2 8 total Vcc Measurement Type Short to GND detect Target un Powered Voltage sense measurement of 50 VDC Voltage Sense Resolution 12 bit ADC Voltage Sense Accuracy 50 mV Physical Box Outline Dimensions 4 00 in X 4 60 in X 0 75 in Power Requirements No external supply needed Power is provided by the host controller Operating Environment Temperature 0 C to 55 C Relative Humidity 10 to 90 non condensing Storage Environment Temperature 40 C to 85 C 1 10 Product Overview Chapter 2 PCI 1149 1 Turbo Installation The PCI 1149 1 Turbo product typically consists of the following components e PCI 1149 1 Turbo PCI based boundaty scan controller card e PCI 1149 1 Turbo User s Manual Ensure all materials listed ate p
3. 10 Pin Straight header 10 pin 4 wall with center 3M 3473 6610 Target TAP notch Table A 2 Standard 10 Pin TAP Connector A 2 Recommended Target Connectors Figure A 2 shows a typical schematic of the target TAP connector with the recommended termination resistors The 1K pull up resistors should connect to the target Vcc supply cotresponding to the interface voltage programmable on the PCI 1149 1 Tutbo from 1 25 to 3 3 V Recommended resistor values ate 5 Voc Ves Voc Vice Target Board To all Boundary Scan Devices To TDI of 1st Device in the chain From TDO of last Device in chain To all Boundary Scan Devices To all Boundary Scan Devices Figure A 2 TAP Connector Schematic Recommended Target Connectors A 3 Flash Programming TAP Connector To build in support for in circuit programming of flash or microprocessor devices Corelis recommends including supplemental control signals in the TAP interface The ScanPlus Flash Programmer can use a 16 pin TAP similar to Figure A 3 to improve programming time This interface adds Write_Strobe Ready Busy and ground signals to the standard 5 signal interface Terminating resistors see Table can improve signal quality TRST XxX K GND TDI x K GND TDO X K GND TMS x K GND TCK x K GND Write_Strobe KX NX GND Reserved K WN Do Not Connect Ready Busy KM HR Do Not Connect Figure A 3 Boundary scan Flash Programming 16 Pin TAP
4. Dialog Box 4 16 Using PCI 1149 1 Turbo with ScanPlus Click the Use the following ScanTAP configuration check box and select the desired programming topology configuration from the drop down list Figure 4 13 shows the selections available from the configuration drop down list ScanPlus Runner Untitled tsp Dj x File Setup Diagnostics View Help Test Steps dt Test Step Name Results infrastructure inf cvf Not Tested infrastructure F infrastructui Infrastructure Test Step Options xl infrastructui Program_U1 Program_U I Skip Pre test Reset Sequence Set Pre test Parallel I 0s Hex Value to 0000 IT Use the following TCK MHz 50 000 y I Loop on Test Step fi Status Use the following ScanTAP configuration z Results KLI Sn 4 0 mE Test Status Figure 4 13 Available ScanTAP 4 TAP Configuration Using PCI 1149 1 Turbo with ScanPlus 4 17 Note that the same drop down options list contains additional configuration options for the fpi programming test steps These additional configuration options are only available for Gang Flash programming of fpi files and is not shown for regular test steps cvf files See Figure 4 14 Flash Programming Test Step Options 0000 50 000 y CIC M ni M mi mi LI mi mi LI Figure 4 14 Available ScanTAP 4 TAP Configuration for fpi files 4 18 Using PCI 1149 1 Turbo with ScanPlus Table 4 4 su
5. PCI slot e Use a screw to firmly attach the PCI 1149 1 Turbo card bracket to the PC chassis e Close the PC enclosure apply power and verify that the PC boots up correctly Preserve the original packing material for future shipment or storage of the PCI 1149 1 Turbo In the event that you installed the PCI 1149 1 Turbo controller before installing the software cancel the Add Remove Hardware Wizard and install the ScanPlus Applications from the CD The next time you start the PC Windows will automatically recognize and configure the PCI 1149 1 Turbo Once the PCI 1149 1 Tutbo is installed in the PC connect the ScanTAP 4 to the PCI 1149 1 Turbo card using the 68 pin SCSI type host cable e Power down shutdown the PC e Plug the 68 pin host cable to the mating connector on the PCI 1149 1 Turbo that should not protrude from the back of your PC enclosure e Plug the other side of the 68 pin host cable to the HOST connector of the ScanTAP 4 box e Apply power and verify that the PC boots up correctly The ON LED should be constantly illuminated when the PC is powered up PCI 1149 1 Turbo Installation 2 3 2 4 PCI 1149 1 Turbo Installation Chapter 3 Connecting to the Target Connecting to the Target The connection to the user target UUT board system is done from the Scan TAP 4 Intelligent Pod TAP connectors to mating connectors on the target The ScanTAP 4 connects to the target via the supplied 1 1 TAP flat
6. Passed Runs 0 Run Test Close Figure 4 10 ScanPlus Runner Test Plan for Gang Programming 4 14 Using PCI 1149 1 Turbo with ScanPlus The Options dialog provides an alternate way to specify gang programming from ScanPlus Runner Right click on the test step name to bring up a pop up menu and select Options as shown in Figure 4 11 o ScanPlus Runner Untitled l loj x File Setup Diagnostics View Help Test Steps Test Step Name Results infrastructure inf cvF infrastructure inf cv Enable All infrastructure inf cvf Disable All infrastructure_inf cwf Enable Selected Program_U12_Altera svf Program_U7 fpi Disable Selected Edit Test Steps View Diagnostics Test Status Debug Status TO Clear Statistics Run Test Figure 4 11 ScanPlus Runner Pop up Menu Using PCI 1149 1 Turbo with ScanPlus 4 15 An Options dialog box similar to Figure 4 12 will appear The appearance of the dialog box varies with the type of test step selected Figure 4 12 illustrates an options dialog for an infrastructure test step Consult the ScanPlus Runner User s Manual for more information on the Options dialog boxes Infrastructure Test Step Options ac Skip Pre test Reset Sequence 0000 Use the following TCK MHz 50 000 y TT Loop on Test Step fi I Use the following ScanTAP configuration 1 Cancel Defaults Figure 4 12 Infrastructure Test Options
7. ScanPlus Runner ScanTAP 4 Configuration NOTE Additional selection options are available for Flash Programming fpi test steps as described later in this chapter Using PCI 1149 1 Turbo with ScanPlus 4 7 TAP Configuration Method 2 This method is primarily provided for upwards compatibility with legacy tools and is not recommended for new applications It works by embedding the TAP selection text as patt of the test step file name This method will override any TAP configuration selected in Method 1 This feature is available in all relevant ScanPlus Tools including ScanPlus Runner ScanPlus Debugger and ScanPlus Flash Programmet File Name ID Meaning TAP s Enabled TAP1 Enable TAP1 only TAPI only _TAP2 Enable TAP2 only TAP2 only TAP3 Enable TAP3 only TAP3 only _TAP4 Enable TAP4 only TAP4 only _TAP1 2 Serialize TAPs 1 through 2 TAPs 1 and 2 in series _TAP1 2 3 Serialize TAPs 1 through 3 TAPs 1 2 and 3 in series _TAP1 2 3 4 Serialize TAPs 1 through 4 TAPs 1 2 3 and 4 in series For example to execute a test ot programming file on a target board that contains 3 TAPs using the file myboard_inf cvf change the file name to myboard_TAP1 2 3_inf cvf The ScanTAP 4 is configurable on the fly and adding a filename suffix from Table 4 2 to a test file name will configure the system to run that test Note that since in most cases the file name already contains a suffix the file n
8. TURBO INSTALLATION ee ee ee ee 2 1 Software Installation Fitstta cina td cl lt ie 2 2 Hardware Installationen A A O ci 2 3 CHAPTER 3 CONNECTING TO THE TARGET eens ee ese ee ee ee EE EE see ee ee ee ee ee EE EE 3 1 Connectino to the Target vase EE EA EA N NE Ed 3 1 20 Pin Scan LAP Connector iese ee Are EE ee tt ets 3 3 68 pin Host Connector OR OE N ER N EG 3 4 PCI 1149 1 Turbo Parallel I O Connectors esse nena 3 5 CHAPTER 4 USING PCI 1149 1 TURBO WITH SCANPLUS 4 1 EE N RO EA DE ORR NAGAR AAS ATEN AE N e OU TUE 4 1 Using PCI 1149 1 Turbo with ScanPlus Tools 4 1 ScanT AP 4 TAP Configuratio eso assessor iaia ahah aaah 4 5 FAP Configuration Method diia a lente er hues ees aad ones 4 6 TAP Configur tion Method 2 ses Eis insects bua eh iin eb paste bbs seg BEN page SE See ee oog Eb gee ke isc 4 8 TAP Configuration Method Finlandia 4 9 Gang Programming with ScanPlus Runner 4 13 Gang Programming with ScanPlus Flash Programmer nena 4 20 CHAPTER 5 THIRD PARTY APPLICATION INTERFACE 5 1 Using PCI 1149 1 Turbo with ScanPlus Runner Command line nono nonnnonnnrna conan 5 1 APPENDIX A RECOMMENDED TARGET CONNECTORS A 1 10 pin TAP Conector sinusitis A 1 Flash Programming TAP Connector nana A 4 20 pin TAP Comi ie A 7 APPENDIX B SELF TEST UTILITY SO
9. increment 211 625 MHz 212 609MHz 0 0156 MHz increment 226 391 MHz 227 350 MHz 0 05 MHz increment 233 050 MHz Table 5 1 PCI 1149 1 Turbo Controller Parameters 5 2 Third Party Application Interface Position Parameter Value Setting 3 Delay 1 Automatic Compensation 2 No Delay 3 0 5 Clock Delay 4 1 0 Clock Delay 5 1 5 Clock Delay 6 2 0 Clock Delay 7 2 5 Clock Delay the following are for PCI 1149 1 Turbo without ScanT AP only 8 3 0 Clock Delay 0 5 clock increment 31 14 5 Clock Delay 32 15 0 Clock Delay 4 Input Threshold 1 Automatic 2 Use advanced input threshold settings in position 11 through 14 5 Slew Rate 1 Automatic 2 Slow slew tate 3 Normal slew rate 6 TAPs 1 Use TAP1 Configuration 2 Use TAP2 3 Use TAP3 4 Use TAP4 5 Use TAPs 1 and 2 in series 5 Use TAPs 1 2 and 3 in series 7 Use TAPs 1 2 3 and 4 in series Third Party Application Interface 5 3 Position Parameter Value Setting 7 TAP1 Voltage 1 1 25 V 2 1 30 V 3 1 35 V beg 0 05 V per step 40 3 20 V 41 3 25 V 42 3 30 V 8 TAP2 Voltage 1 1 25 V 2 1 30 V 3 1 35 V Neg 0 05 V per step 40 3 20 V 41 3 25 V 42 3 30 V 9 TAP3 Voltage 1 1 25 V 2 1 30 V 3 1 35 V ni 0 05 V per step 40 3 20 V 41 3 25 V 42 3 30 V 10 TAP4 Voltage 1 1 25 V 2 1 30 V 3 1 35 V mi 0 05 V per step 40 3 20 V 41 3 25 V 42 3 30 V 11 TAP1 1 Automati
10. scan test path by generating the proper signals under software control to interface with the target device It also supports remote operation of multiple boundary scan JTAG Test Access Ports TAPs using any of the Corelis ScanTAP family of Multiple TAP Intelligent pods such as the ScanTAP 4 The ScanTAP 4 provides up to 4 independent TAP connectors with a programmable low voltage compatible interface It also supports simultaneous programming and verification of Flash memory devices at continuous scan clock TCK speeds of up to 80 MHz The PCI 1149 1 Turbo facilitates software controlled boundary scan operations per IEEE Standard 1149 1 It provides command access to the target s Test Access Port TAP to verify PCB interconnects perform functional testing and debug without manual probing Furthermore the JTAG interface gives access to internal device functions that are not accessible via external probing enabling fault isolation within the device itself The JTAG interface also enables programming target Flash and CPLD devices as well as general down and uploading of data blocks to and from various storage devices What Is IEEE Standard 1149 1 The IEEE Standard 1149 1 test bus and boundary scan architecture enable control of an IC board or system via a standard four signal interface Each IEEE Standard 1149 1 compliant IC incorporates a feature known as boundary scan which ensures that a JTAG controller can control and observe each
11. the left mouse button The test step is now highlighted Right click on the test step name to bring up a pop up menu and select Options as shown in Figure 4 7 o ScanPlus Runner TARGET 1149 1 tsp iol x File Setup Diagnostics Yiew Help Test Steps Test Step Name Rests infrastructure inf cvf Not Tested interconnect ic cvf Enable All Not Tested buswire_bus cwf Disable All Not Tested fifo met cvf Enable Selected Not Tested dram met cyf Not Tested Program U12 LEDs Of Papas Not Tested Program U18 LEDs OF Edit Test Steps Not Tested Demo Board UIQ Ex Not Tested View Diagnostics on O Il A Ww mi Test Status Debug Status MONTY Figure 4 7 ScanPlus Runner Pop up Menu 4 10 Using PCI 1149 1 Turbo with ScanPlus An Options dialog box similar to Figure 4 8 will appear The appearance of the dialog box varies with the type of test step selected Figure 4 8 illustrates an options dialog for an infrastructure test step Consult the ScanPlus Runner User s Manual for more information on the Options dialog boxes Infrastructure Test Step Options ad Skip Pre test Reset Sequence i 0000 TT Use the following TEK MHz 50 000 y I Loop on Test Step fi Use the following ScanTAP configuration 1 ba Cancel Defaults Figure 4 8 Infrastructure Test Options Dialog Box Using PCI 1149 1 Turbo with ScanPlus 4 11 Click the Use th
12. 3 3 Connector P2 Parallel Output Pin Assignment Note All even pins of the connector 2 4 6 8 34 are connected to ground P2 33 is not connected Connecting to the Target 3 5 The parallel input pott connector P1 on the PCI 1149 1 Turbo is a 34 pin connector that includes all of the signals for the parallel input port The connector is located near the top of the card The pin out of the P1 connector is shown in Table 3 4 Note 1 Note 2 PCI Bus Data Ee Signal Name Input Connector PORTA INO P1 1 i man ea pr porra ms DI roman mr PORTB IN7 P1 31 Table 3 4 Connector P1 Parallel Input Pin Assignment All even pins of the connector 2 4 6 8 connected 34 are connected to ground P1 33 is not All input signals have a 4 7 K pull up resistor to the programmed interface voltage 1 25 to 3 30 V When the ScanTAP 4 is used the 16 inputs and outputs interface at 3 3V 3 6 Connecting to the Target Chapter 4 Using PCI 1149 1 Turbo with ScanPlus Hardware Setup You must configure the PCI 1149 1 Turbo controller in a ScanPlus application before the application can use it This chapter uses ScanPlus Runner as an example to illustrate the configuration process Using PCI 1149 1 Turbo with ScanPlus Tools The PCI 1149 1 Turbo card is compatible with ScanPlus Runner ScanPlus Debugger and ScanPlus Flash Programmer The following steps are
13. 4 18 Figure 4 15 ScanPlus Flash Programmer Gang Programming Window iii 4 20 Figure A 1 Standard TAP connector top View nana A 1 Figure A 2 TAP Connector Schematic iii A 3 Figure A 3 Boundary scan Flash Programming 16 Pin TAP Connector top vieW ii A 4 Figure A 4 Flash Programming TAP Connector SchematiCS esse esse see se se Se Ged Ge SA Ge Ge ee ee Ge ee ee ee A 6 Figure A 5 Boundary scan Flash Programming 20 Pin TAP Connector top view iii A 7 Figure A 6 20 pin TAP Connector Schematic for SPI A 10 Figure A 7 20 pin TAP Connector Schematic for I2C iii A 11 Figure B 1 Self Test Result for the PCI 1149 1 Turbo when the ScanTAP 4 is NOT connected se se se B 2 Figure B 2 Self Test Results for the PCI 1149 1 Turbo with the ScanTAP 4 Connected iii B 3 Table of Tables Table 1 1 Table 1 2 Table 1 3 Table 1 4 Table 3 1 Table 3 2 Table 3 3 Table 3 4 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 5 1 Table A 1 Table A 2 Table A 3 Table A 4 Table A 5 Table A 6 Programmable TCK Frequencies v iu iii ala 1 5 ScanTAP 4 DC Characteristics sesse Ed kg seg sg ee isni ee gee ke Ee seats eg GEE DR Ge ed e ba EDGE he Deeg Reg AE De ski 1 7 ScanTAP 4 SPI Interface DC Characteristics iii 1 8 ScanTAP 4 I2C Interface DC Characteristics iii 1 9 ScanTAP 4 TAP Pin Assignm tit csc n
14. CORELIS PCI 1149 1 Turbo PCI 1149 1 Turbo High Speed PCI Bus Boundary Scan Controller User s Manual Document Part Number P N 70318 REV I Copyright 2002 2007 Corelis Inc boje ndra Blvd Suite 102 s CA 90703 2262 Telephone 926 6727 Fax 562 404 6196 Preface PRINTING HISTORY New editions are complete revisions of the manual Update packages which are issued between editions contain additional and replacement pages to be merged into the manual by the customer The dates on the title page change only when a new edition is published A software code may be printed before the date this indicates the version of the software product at the time the manual or update was issued Many product updates and fixes do not require manual changes and conversely manual corrections may be done without accompanying product changes Therefore do not expect a one to one correspondence between product updates and manual updates Revision E January 2004 Revision F June 2004 Revision G January 2006 Revision H November 2007 Revision I February 2011 GENERAL NOTICE Information contained in this document is subject to change without notice CORELIS shall not be liable for errors contained herein for incidental or consequential damages in connection with the furnishing performance or use of material contained in this manual This document contains proprietary information which is protected by copyright All rights reserved
15. Connector top view Cotelis Flash Programming software supports the external signals Write_Strobe and Ready Busy in addition to the standard but slowet scanned out in signals approach The Write_Strobe signal is active low and should be pulled up with a 1K resistor on the target board It needs to be logically ORed with the flash Write Enable WE signal so that either the flash Write Enable WE signal or the external Write_Strobe going low will assert the flash WE input The active low Ready Busy signal is typically an open collector open drain signal that ties directly to the same signal s on the Flash device s This enables multiple devices to drive it toward the PCI 1149 1 Turbo A 4 Recommended Target Connectors Table A 3 summarizes the specifications for a 16 pin TAP connector without latch ejector Equivalent connectors are available from other manufacturers Reference Description Manufacturer Part Number Flash TAP Straight header 16 pin 4 wall with center notch 3M 2516 6002UG Table A 3 Flash Programming TAP 16 Pin Connector Table A 4 describes the signals and Corelis recommended values of terminating resistors Note Some target Pin Signal Direction Termination boards may require a pull down resistor on 1 TRST Input to the UUT 1K pull up or 1 5K pull down 1 the TRST signal to 2 GND assure normal device operations when not 3 TDI Inp
16. FTWARE nena Self Test Table of Figures Figure 1 1 The Corelis PCI 1149 1 Turbo Boundary Scan Controller iii 1 2 Figure 1 2 Test Access Port TAP caida hasta een 1 2 Figure 1 3 PCI 1149 1 Turbo Block Diagram 1 3 Figure 2 1 Picture of the PCI 1149 1 Turbo and ScanTAP 4 Hardware 2 1 Figure 3 1 ScanTAP 4 20 pin TAP Header Connectors top view 3 1 Figure 4 1 Controller Configuration Screen 4 1 Figure 4 2 PCI 1149 1 Turbo Setup Screen but ScanTAP 4 not connected 4 2 Figure 4 3 Successful PCI 1149 1 Turbo With ScanTAP Setup Screen iii 4 3 Figure 4 4 Advanced Configuration Setup Screen iese see see se ee ee ee ee Se Se GR Se SA Ge SR SA GRA Ge ee ee ee ee 4 4 Figure 4 5 Controller Configuration TAP Configuration Options 4 6 Figure 4 6 Typical ScanPlus Runner Test Plan ui 4 9 Figure 4 7 ScanPlus Runner Pop up MENU 4 10 Figure 4 8 Infrastructure Test Options Dialog BOX 4 11 Figure 4 9 Available ScanTAP 4 Configuration nena 4 12 Figure 4 10 ScanPlus Runner Test Plan for Gang Programming iii 4 14 Figure 4 11 ScanPlus Runner Pop up Menu 4 15 Figure 4 12 Infrastructure Test Options Dialog Box iii 4 16 Figure 4 13 Available ScanTAP 4 TAP Configuration sesse se esse se esse se se ee Ge ee Ge ee Ge Ge Ge ee Ge ee GR Ge ee ee 4 17 Figure 4 14 Available ScanTAP 4 TAP Configuration for fpi fileS iii
17. No part of this document may be reproduced or translated to other languages without the prior written consent of CORELIS CORELIS assumes no responsibility for the use of or reliability of its software on equipment that is not furnished by CORELIS ENVIRONMENTAL NOTICE EI This product must be disposed of in accordance with the WEEE directive TRADEMARK NOTICE Windows is a registered trademark of Microsoft Corporation Other products and services named in this book are trademarks or registered trademarks of their respective companies All trademarks and registered trademarks in this book are the property of their respective holders PRODUCT WARRANTY For product warranty and software maintenance information see the PRODUCT WARRANTY AND SOFTWARE MAINTENANCE POLICY statement included with your product shipment EXCLUSIVE REMEDIES THE REMEDIES CONTAINED HEREIN ARE THE CUSTOMER S SOLE AND EXCLUSIVE REMEDIES CORELIS SHALL NOT BE LIABLE FOR ANY DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES WHETHER BASED ON CONTRACT TORT OR ANY OTHER LEGAL THEORY Product maintenance agreements and other customer assistance agreements are available for Corelis products For assistance contact your nearest Corelis Sales and Service Office RETURN POLICY No items returned to CORELIS for warranty service or any other reason shall be accepted unless first authorized by CORELIS either direct or through its authorized sales repr
18. O and TAP interfaces can be set to any voltage between 1 25 V and 3 30 V in increments of 0 05V minimum Parallel Input Output Ports The PCI 1149 1 Turbo contains 16 parallel inputs and 16 parallel outputs The board groups these digital I O into two 8 bit parallel input ports and two 8 bit parallel output ports Port A and Port B The host computer can access the output ports via the Corelis ScanPlus Runner software The input ports are for future use and are not currently available to the user The output ports are useful for providing discrete signals that control functions on the user target system such as reset power control and disable enable signals for operating non boundary scan devices on target boards that include some non IEEE 1149 1 compliant components PCI Bus Interface The PCI 1149 1 Turbo is a single slot universal 3 3 V or 5 V signaling level 32 bit 33 MHz PCI device compliant with Revision 2 2 of the PCI Bus Specification It is mapped to 132 MB of memory space of the host system as established during system initialization 1 4 Product Overview Programmable Clocks The PCI 1149 1 Turbo s programmable TCK outputs to the IEEE Standard 1149 1 compatible target system can generate a wide range of TCK frequencies with onboard TCK generation circuitry A programmable Phase Locked Loop PLL and counter dividers provide both a wide range and fine selection resolution See Table 1 1 for the set of programmable values
19. Programmer can use a 16 pin TAP similar to Figure A 5 to improve programming time This interface adds Write_Strobe Ready Busy and ground signals to the standard 5 signal interface Terminating resistors see Table can improve signal quality TRST 1 X X 2 GND TDI 3 x X 4 GND TDO 5 x X 6 GND TMS 7 x X 8 GND TCK 9 x DM 10 GND Write Strobe GPIO1 SPI CS2 11 x X 12 GND SPI SCK GPIO2 13 x X 14 GND Ready Busy SPI SDO GPIO3 15 x X 16 SPI_SDI UUT Power Test Point 17 X YN 18 2C SCL UUT Power Test Point 19 xX X 20 SPI CS1 I2C SDA Figure A 5 Boundary scan Flash Programming 20 Pin TAP Connector top view Corelis Flash Programming software supports the external signals Write Strobe and Ready Busy in addition to the standard but slower scanned out in signals approach The Write_Strobe signal is active low and should be pulled up with a 1K resistor on the target board It needs to be logically ORed with the flash Write Enable WE signal so that either the flash Write Enable WE signal or the external Write_Strobe going low will assert the flash WE input The active low Ready Busy signal is typically an open collector open drain signal that ties directly to the same signal s on the Flash device s This enables multiple devices to drive it toward the PCI 1149 1 Turbo Recommended Target Connectors A 7 Table A 3 summarizes the specifications for a 16 pin TAP connector without latch ejector Equivalen
20. ame ID is inserted between the suffix and the rest of the file name For example infrastructure_inf cvf becomes infrastructure_TAP1 2 3 4_inf cvf Table 4 2 ScanPlus Runner Naming Conventions NOTE Additional selection options are available for Flash Programming fpi test steps as described later in this chapter Using PCI 1149 1 Turbo with ScanPlus TAP Configuration Method 3 This method is only available for ScanPlus Runner Itis available in the ScanPlus Runner Options menu Use this method only when specific test step s require TAP configuration settings different from the global settings selected in Method 1 A typical ScanPlus Runner main screen with multiple test steps is shown in Figure 4 6 o ScanPlus Runner TARGET 1149 1 tsp oj x File Setup Diagnostics View Help Test Steps Test Step Name Resuts infrastructure inf cvf Not Tested interconnect ic cvf Not Tested buswire bus cvf Not Tested fifo_mct cwf Not Tested dram_mct cwf Not Tested Program U12 LEDs ON Altera svf Not Tested Program U18 LEDs OFF Xilinx svf Not Tested Demo Board U10 Ext HEX Fpi Not Tested 1 2 3 4 5 6 7 3 Test Status Test Statistics Status Ready _ Total Runs 0 Passed Runs 0 Run Test Close Figure 4 6 Typical ScanPlus Runner Test Plan Using PCI 1149 1 Turbo with ScanPlus 4 9 Highlight a test step by pointing to it with the mouse and then clicking once with
21. and TAP 3 _TAP1 4 Enable TAPs 1 through 4 Gang Programming of TAPs 1 2 3 and 4 Table 4 3 ScanPlus Runner Naming Conventions for Gang Programming For example to gang program all four target boards using the file program U7 fpi change the file name to program U7_TAP1 4 fpi The ScanTAP 4 is configurable on the fly and adding a filename suffix from Table 4 3 to a test file name will configure the system to run that test Using PCI 1149 1 Turbo with ScanPlus 4 13 In the test plan shown in Figure 4 10 below the system first tests target TAPs 1 through 4 for infrastructure then it programs the Altera CPLD on target TAPs 1 through 4 then it programs the Flash memory in parallel on all four targets Note that for files that already contain a suffix the file name ID is inserted between the suffix and the rest of the file name For example infrastructure inf cvf becomes infrastructure TAP1 4 inf cvf ScanPlus Runner Untitled zla x File Setup Diagnostics View Help Test Steps infrastructure TAP1 inf cvf Not Tested infrastructure TAP2 inf cvf Not Tested infrastructure TAP3 inf cvf Not Tested infrastructure TAP4 inf cvf Not Tested Program U12 TAP1 Altera svf Not Tested Program U12 TAP2 Altera svf Not Tested Program U12 TAP3 Altera svf Not Tested Program U12 TAP4 Altera svf Not Tested Program U7 TAP1 4 fpi Not Tested 1 2 3 4 5 6 ri 8 9 Test Status Test Statistics Status Ready Total Runs 0
22. atching 10 pin header on the target system 68 pin Host Connector The PCI 1149 1 Turbo connects to the ScanTAP 4 using a 68 wite one to one twisted pair ribbon cable P N 15314 Other HOST cables of longer lengths are also available Table 3 2 shows the part numbers for making custom length HOST flat cable Note that this table is provided for reference only and Corelis recommends using only approved HOST cables that are provided with the product Description Manufacturer Part Number 68 pin 100 x 100 SCSI IDC Socket Circuit Assembly CA 68MDP F SCSI Strain Relief Circuit Assembly CA LSR68MDP 0 25 Spectra Strip twisted pair 34 pair cable Amphenol 125 3099 999 Table 3 2 68 Pin SCSI type Cable Parts 3 4 Connecting to the Target PCI 1149 1 Turbo Parallel VO Connectors The parallel output port connector P2 on the PCI 1149 1 Tutbo is a 34 pin connector that includes all of the signals for the parallel output ports and B The connector is located near the top of the card The pin out of the P2 connector is shown in Table 3 3 PCI Bus Data Signal Name Output Connector Alignment PORTA OUTO P2 1 DI roe oen a pr rorracoura ms ps rorracours BT DI rorracoure ms Ds rorracours en pe rorracours rats DI roe oen er pr omom ea ps roe oes ms DI roma oen es ps roe oes em pe roe oes es pr row oer ea Table
23. c Input Threshold 12 TAP2 1 Automatic Input Threshold 13 TAP3 1 Automatic Input Threshold 14 TAP4 1 Automatic Input Threshold Table 5 1 PCI 1149 1 Turbo Controller Parameters continued Third Party Application Interface Example To select a PCI 1149 1 Turbo controller card with a TAP1 voltage of 3 30 V TCK frequency of 1 MHz and automatic delay compensation use this controller specification string controller PCI 1149 1 Turbo 42 196 1 To select a PCI 1149 1 Turbo ScanTAP4 controller card with all TAP voltages of 3 30 V TCK frequency of 1 MHz automatic delay compensation automatic input threshold slow slew rate and TAPI use this controller specification string controller PCI 1149 1 Turbo ScanTAP4 42 196 1 1 1 1 42 42 42 42 1 1 1 1 Third Party Application Interface 5 5 Appendix A Recommended Target Connectors 10 pin TAP Connector The Boundary Scan TAP is a well defined IEEE 1149 1 compatible electrical interface between boundary scan test equipment and the boundary scan compatible devices in the user s target board Boundary scan based test equipment such as the Corelis ScanPlus family of products utilize a single TAP to interface to the UUT This section explains how to implement a TAP connector that is compatible with most standard test equipment The TAP contains 5 signals TCK TMS TDO TDI and optionally TRST It also contains ground signal s Corelis recomm
24. cables P N 15310 15311 or 15312 Figure 3 1 shows the top view of the ScanTAP 4 box including the four TAP connectors which are cleatly marked TAP 1 TAP 2 TAP 3 and TAP 4 ScanTAP 4 Pin 19 Pin I Pin I Pin 2 Pin 20 Pin I Pin I Figure 3 1 ScanTAP 4 20 pin TAP Header Connectors top view Connecting to the Target 3 1 While most targets use only a single TAP connector it is not uncommon that targets contain multiple TAP connectors Although the 4 connector ScanTAP 4 will accommodate the vast majority of multiple TAP targets a target board with more than 4 TAPs requires a different interface Please contact Corelis for other available products The following ScanTAP 4 TAP connectors ate connected to the target board TAP1 when the target has a single TAP connector TAP1 and TAP2 when the target has 2 TAP interface connectors TAP1 TAP2 and TAP3 when the target has 3 TAP interface connectors TAP1 TAP2 TAP3 and TAP4 when the target has 4 TAP interface connectors To connect the TAP connector s to the target UUT e Make sure that the target power is OFF e Make sure that the ON LED on top of the ScanTAP 4 is illuminated e Install the TAP cable s on the Scan TAP 4 TAP connectors e Install the other side of the TAP cable s on the matching target TAP connectors e Now you can turn the target power ON Appendix A contains general recommendation for implementing compatible target TAP connector s Followi
25. cca iaia lana RE OR EE OE ON N 3 3 68 Pin SCSI type Cable Parts panacea iaia Ra N see Bes rekken 3 4 Connector P2 Parallel Output Pin Assignment iii 3 5 Connector P1 Parallel Input Pin Assignment iii 3 6 ScanPlus Runner ScanTAP 4 Configuration iii 4 7 ScanPlus Runner Naming Conventions sonervnnrnrnnnrnnnnnnnnnnnnnnnnrnvvrnnvenanenarvrvenasenarvrarvrnsnensvensnvssnsvsvassvaseree 4 8 ScanPlus Runner Naming Conventions for Gang Programming iii 4 13 ScanPlus Runner ScanTAP 4 Configuration ii 4 19 PCI 1149 1 Turbo Controller Parameters iii 5 2 Signal Description and TerminatiOn ene A 2 Standard 10 Pin TAP ed OE N ORE in ED di A 2 Flash Programming TAP 16 Pin Connector iii A 5 Signal Description and TerminatiOn ena A 5 Flash Programming TAP 16 Pin Connector iii A 8 Signal Description and Terminato sesyen E E a E ER EERE A 9 vi Chapter 1 Product Overview Introduction The PCI 1149 1 Turbo High Speed PCI Bus boundary scan controller is a member of the Corelis ScanPlus family of scan based test analysis and diagnostic tools The PCI 1149 1 Turbo High Speed PCI Bus Boundary Scan Controller card with memory behind the pin architecture interfaces between a PC and any IEEE Standard 1149 1 compatible target The PCI 1149 1 Turbo is designed to control the operation of an IEEE Standard 1149 boundary
26. cifications Host Computer CPU Pentium II Q 266 MHz or better Operating System Windows 95 98 NT ME 2000 XP PCI Interface Bus Width 32 bit Memory Space Size 132 MB ScanTAP Interface Maximum TCK frequency 80 MHz TCK frequency steps 1 00 MHz increments between 25 and 80 MHz TCK frequency steps cont d 0 80 MHz increments between 12 5 and 25 MHz TCK frequency steps cont d 0 25 MHz increments or less below 12 5 MHz Maximum scanning data length unlimited Physical Card Outline Dimensions PCB 3 875 in X 6 75 in I O Connectors P4 Boundary Scan Connector 68 pin SCSI II type AMP P N 787171 7 or equivalent P1 Input Port Connector 34 pin header 3M part no 2534 6002UB or equivalent P2 Output Port Connector 34 pin header 3M part no 2534 6002UB or equivalent Power Requirements from host expansion bus 5V 1 5 Amps maximum On board Fuse feeds power from PCI 1149 1 Turbo to external pod 1 5 Amp SLO BLO Littelfuse part number 045401 5 Operating Environment Temperature 0 C to 55 C Relative Humidity 10 to 90 non condensing Storage Environment Temperature 40 C to 85 C 1 6 Product Overview ScanTAP 4 Specifications PCI 1149 1 Turbo Interface Host Connector Host Cable Length TAP Interface Connectors Number of TAPs Maximum TCK frequency Maximum scanning data length Programmable Interface Voltage Programmable TAPs Signals DC characteristics 68 pin SCSI type AMP pa
27. e following ScanTAP configuration check box and select the desired programming topology configuration from the drop down list Figute 4 9 shows the selections available from the configuration drop down list o ScanPlus Runner TARGET 1149 1 tsp lol x File Setup Diagnostics View Help Test Steps Test Step Name infrastructure inf cvf Not Tested interconnect buswire_bus Infrastructure Test Step Options q xj fifo_mct cwf dram mct cyl Program UI Skip Pre test Reset Seguence id Set Pre test Parallel Os Hex Value to 0000 I Use the following TCK MHz 50 000 y Test Status I Loop on Test Step fi Staus INEEN J Use the following ScanTAP configuration fi z Results NQ 1 2 3 4 5 6 7 8 Figure 4 9 Available ScanTAP 4 Configuration 4 12 Using PCI 1149 1 Turbo with ScanPlus Gang Programming with ScanPlus Runner Special TAP configuration features are provided for parallel Gang programming of Flash memories using fpi files ScanPlus Runner also supports gang programming determining the configuration of the Flash programming topology from the fpi file name This is in addition to the TAP configuration options listed Table 4 3 lists suffixes to add to the file name for various cases File Name ID Meaning TAP s Enabled _TAP1 2 Enable TAPs 1 through 2 Gang Programming of TAP1 and TAP2 _TAP1 3 Enable TAPs 1 through 3 Gang Programming of TAP1 TAP2
28. ends the standard TAP connector shown in Figure A 1 which is widely regarded as the industry standard Note that each signal is terminated with a resistor discussed below in order to improve noise immunity The connector on the user s target should have a standard flat cable compatible pinout to match the TAP connector described in Table A 1 Figure A 1 shows the top view of the basic target 10 pin connector header 0 100 x 0 100 in spacing TRST 1 mM M 2 GND TDI 3 R WM 4 GND TO 5 R K 6 GND TMS 7 m K 8 GND TCK 9 m M 10 GND Figure A 1 Standard TAP connector top view Recommended Target Connectors A 1 Table A 1 describes the 10 pin TAP connector signals and Corelis recommended values of terminating resistors Pin Signal Direction Termination 1 TRST Input to the UUT 1K pull up or 1 5K pull down gt Note Some target 2 GND boards may require a pull down resistor on 3 TDI Input to the UUT 1K pull up the TROT signal to 4 GND assure normal device 5 TDO Output of the UUT 33 ohm series EE in boundary scan test 6 GND mode T TMS Input to the UUT 1K pull up 8 GND 9 TCK Input to the UUT 1K pull up 10 GND Table A 1 Signal Description and Termination Table A 2 summarizes the specifications for the 10 pin TAP connector Equivalent connectors are available from other manufacturers Reference Description Manufacturer Part Number
29. es the requirements related to the PCI 1149 1 Turbo card and to the ScanTAP 4 Refer to the ScanPlus Runner manual for further information Using PCI 1149 1 Turbo with ScanPlus Runner Command line You can invoke ScanPlus Runner with special command line parameters to execute a Test Step file provide test results and diagnostic messages in a log file if you have the ScanPlus Runner ADO and then terminate The following table shows the controller identifiers and associated parameters Consult the ScanPlus Runner User s Manual for more detail The PCI 1149 1 Turbo controller without ScanTAP4 uses three parameters and it uses up to fourteen parameters with ScanTAP4 The parameters are described in the table below Controller keyword PCI 1149 1 Turbo PCI 1149 1 Turbo ScanTAP4 Position Parameter Value Setting 1 TAPs Voltage 1 1 25 V 1 30 V dai 0 05 volts per step 41 3 25 V 42 3 30 V 43 Use advanced voltage settings in position 7 through 10 2 Clock Frequency 51 80 MHz 1 MHz increment 76 25 MHz TT 24 5 MHz 0 5 MHz increment 101 12 5 MHz Third Party Application Interface 5 1 Position Parameter Value Setting 102 12 25 MHz 0 25 MHz increment 126 6 25 MHz 127 6 125 MHz 0 125 MHz increment 136 5 MHz 137 4 9 MHz 0 1 MHz increment 161 2 5 MHz 162 2 45 MHz 0 05 MHz increment 186 1 25 MHz 187 1 225 MHz 0 025 MHz
30. esentatives All returned items must be shipped pre paid and clearly display a Returned Merchandise Authorization RMA number on the shipping carton Freight collect items will NOT be accepted Customers or authorized sales representatives must first contact CORELIS with notice of request for return of merchandise RMA s can only originate from CORELIS If authorization is granted an RMA number will be forwarded to the customer either directly or through its authorized sales representative CONTACT INFORMATION For sales inquiries please contact sales corelis com For any support related questions please enter a support request at www corelis com support or email support Qcorelis com For more information about other products and services that Corelis offers please visit www corelis com Table of Contents CHAPTER T PRODUCT OVER ME Museene dd 1 1 Introduccion ale 1 1 What Is IEEE Standard 1149 1 s n is OE ET EE AE daje 1 1 Features of the PCI 1149 1 TUrbo espinillas 1 3 Adjustable Voltage Interfaces cc asi Ge dai 1 4 Parallel Input Output Ports 4 EG OER EO EE OE OE EO EE 1 4 PCI B s Interface n ER N OE Aia EG 1 4 Programmable Clocks AE EE OR ER ER OE AE EE EE OE OE EEN 1 5 Features of the Scan KAPA tio ierit ei Ge ee SE seder Ee ee ee be Ese ke dat leeds 1 5 PCI 1149 1 Turbo Specifications ie esel asa SE AE ie ee ee Ee Ee es GEES biv Ee stints 1 6 Scan TAP 4 Specifications scr EE karse 1 7 CHAPTER 2 PCI 1149 1
31. f the PCI 1149 1 Turbo The Corelis PCI 1149 1 Tutbo is a sophisticated test controller that can access devices boards or systems compliant with IEEE Standard 1149 1 The PCI bus compatible card supports one JTAG boundary scan chain TAP Two general purpose 8 bit parallel I O ports can test or control non boundary scan areas of the unit under test UUT With its software controlled voltage translating logic the PCI 1149 1 Tutbo can test low voltage systems It supports signals including high speed differential pairs that can operate external Corelis ScanTAP gang products such as the ScanTAP 4 to remotely scan multiple Test Access Ports TAP The PCI 1149 1 Turbo contains several performance enhancing functional sections aimed at increasing test vector throughput A functional block diagram of the PCI 1149 1 Turbo is shown in Figure 1 3 Key functional elements include the TAP controller and the memory resources that support it The on board memory provides scan data storage and can store the entire scan data for maximum performance real time scan operations A test system accesses the TAP controller and its associated memory through the host PCI bus memory mapped I O This supports the high data rate of the PCI bus regardless of actual test clock speeds The ability to download information into these memory elements further decouples the scan operations from the host software A state machine that contains status and control registers acces
32. functional pin of the IC via the four wire interface A controller can load test debug or initialization patterns serially into the appropriate IC s via the IEEE Standard 1149 1 test bus Thus even with limited physical access a user can observe or control IC board or system functions Two main elements comprise the IEEE Standard 1149 1 test bus a Test Access Port TAP which interfaces internal IC logic with the external world via a four signal optionally five signal bus as shown in Figure 1 2 and a boundary scan architecture which defines standard boundary cells that drive and receive data at the IC pins IEEE Standard 1149 1 also defines both mandatory and optional opcodes and test features The test bus signals are Test Clock TCK Test Mode Select TMS Test Data In TDI Test Data Out IDO and the optional Test Logic Reset TRST Product Overview 1 1 KDI y E R ED o lt x i vo po le no O Ol o o un lt un 111191447 A22 v ry sped z s xaz RINK 427 aos ROOT i et al aa SRSA A RTO Figure 1 1 The Corelis PCI 1149 1 Turbo Boundary Scan Controller The IEEE 1149 1 Test Access Port Interface TAP consists of four TMS required signals Test Mode Select TMS TOK Test Clock TCK TDI Test Data In TDI se Test Data Out TDO A fifth signal is defined as optional TRST Test Reset TRST Figure 1 2 Test Access Port TAP Product Overview Features o
33. ith ScanPlus 4 5 TAP Configuration Method 1 The TAP Configuration select box in the Controller Configuration screen provides TAP selection options as shown in Figure 4 5 This is the preferred and most straightforward method for selecting which of the 4 ScanTAP 4 TAPs to use for connecting to the target This feature is available in all relevant ScanPlus Tools including ScanPlus Runner ScanPlus Debugger and ScanPlus Flash Programmer Controller Configuration E Controller Configuration Controllers Controller Settings A TAPs Voltage 1 80 i ey Ba faamai Nul Device PCI41491 pa Tea n le TEK Frequency 50 000MHz y B l pd Delay Compensation Automatic z PCI 1149 1 Net 1149 1 Slew Rate Automatic z zj TAPs Configuration 1 z Current Controller j PCI 1149 1 Turbo ScanTAP4 Cancel Apply Figure 4 5 Controller Configuration TAP Configuration Options 4 6 Using PCI 1149 1 Turbo with ScanPlus Table 4 1 summarizes the different configuration options available in the TAP Configuration drop down list Configuration Meaning TAP s Enabled 1 Enable TAP1 only TAP1 only 2 Enable TAP2 only TAP2 only 3 Enable TAP3 only TAP3 only 4 Enable TAP4 only TAP4 only 1 2 Serialize TAPs 1 through 2 TAPs 1 and 2 in series 1 2 3 Serialize TAPs 1 through 3 TAPs 1 2 and 3 in series 1 2 3 4 Serialize TAPs 1 through 4 TAPs 1 2 3 and 4 in series Table 4 1
34. ller The PCI 1149 1 Turbo controller is a plug and play device and its drivers are installed with the ScanPlus Application Software Windows will automatically recognize and configure the PCI 1149 1 Tutbo the first time it is detected in your system WARNING You MUST install the software first before installing the card Do not install the PCI 1149 1 Turbo card until you have successfully installed the application software ScanPlus CodeRunner etc Installing the software provides the plug and play driver for the card so that the operating system is able to properly detect and configure the card Installing the card before the software may result in improper card configuration and operation 2 2 PCI 1149 1 Turbo Installation Hardware Installation Again make sure to install the ScanPlus Application Software before installing the PCI 1149 1 Turbo controller The PCI 1149 1 Turbo controller is a plug and play device and its drivers are installed with the ScanPlus Application Software Windows will automatically recognize and configure the PCI 1149 1 Turbo the first time it is detected in your system To install the PCI 1149 1 Turbo on a PC e Install ScanPlus Applications from the CD and shut down the PC e Remove the PCI 1149 1 Turbo from its package e Disconnect the PC power cord from the power source and then remove the enclosure cover from the PC e Plug the PCI 1149 1 Turbo board into the PC in an available
35. mmarizes the additional fpi file specific configuration options available in the drop down list Configuration Meaning TAP s Enabled 1 2 Enable TAPs 1 through TAP2 in parallel Gang TAPs 1 and 2 are active 1 3 Enable TAPs 1 through TAP3 in parallel Gang TAPS 1 2 and 3 active 1 4 Enable TAPs 1 through TAP4 in parallel Gang All 4 TAPs are active Table 4 4 ScanPlus Runner ScanTAP 4 Configuration Using PCI 1149 1 Turbo with ScanPlus 4 19 Gang Programming with ScanPlus Flash Programmer Version 1 73 or newer of the ScanPlus Flash Programmer software supports gang programming of multiple target boards using ScanTAP 4 Gang programming with the ScanTAP 4 requires an fpi file that the ScanPlus Flash Generator generates Gang programming applies the same fpi file to identical targets concurrently via separate TAP connections Invoke ScanPlus Flash Programmer select the Setup menu item and the Gang Programming entry Then check off the TAPs on which you are programming the Flash Devices Figure 4 15 below shows the setup for programming four targets in parallel Gang Programming Figure 4 15 ScanPlus Flash Programmer Gang Programming Window 4 20 Using PCI 1149 1 Turbo with ScanPlus Chapter 5 Third Party Application Interface ScanPlus Runner provides a general purpose third party application interface that includes specifying the correct controller card and settings This section clarifi
36. n Parallel Outputs Controllers Controller Settings TAP Voltage 3 30 et TEK Frequency fi 000 MHz Delay Compensation Automatic y PCI 1149 1 Turbo ap We PCI 1149 1 Net 1149 1 Null Device Current Controller Fo 1149 1 Turbo vi OK Cancel Apply Help Cane Her Figure 4 2 PCI 1149 1 Turbo Setup Screen but ScanTAP 4 not connected 4 2 Using PCI 1149 1 Turbo with ScanPlus 6 Once ScanPlus Runner finds the PCI 1149 1 Turbo controller with the ScanTAP 4 connected to it it displays a screen similar to Figure 4 3 Note that saving the test plan tsp file in ScanPlus Runner FILE menu also saves the settings in the system registry The next time the tsp file is loaded into ScanPlus Runner it will use these settings to initialize the controller Controller Configuration x Controller Configuration Controllers Controller Settings F TAPs Voltage 3 304 m ae N Input Threshold Automatic z Turbo TCK Frequency 53 000 MHz z B l ped Delay Compensation Automatic z PCI 11491 Net11491 kovi Fl te Automatic z e zi TAP Configuration 1 z Current Controller Fans Tabo Gra Advanced Cancel Apply Figure 4 3 Successful PCI 1149 1 Turbo With ScanTAP Setup Screen Using PCI 1149 1 Turbo with ScanPlus 4 3 7 The Advanced button can be used for selecting different voltage settings for each individual TAP While most targets with multi
37. ng these recommendations makes the connection to the target easy and straightforward To accommodate target boards with TAP connectors other than this standard Corelis offers short custom adapter cables for connectors such as the Altera ByteBlaster connector the Xilinx 9 pin header the Lattice TAP connector or the TI 14 pin DSP connector 3 2 Connecting to the Target 20 Pin ScanTAP Connector The ScanTAP 4 contains four 20 pin TAP connectors All four connectors have the same signals and the same pinout Each connector is a shrouded header 0 100 X 0 100 in spacing with long ejectors that are compatible with standard 20 pin IDC flat cable connectors with strain relief The pin assignment is shown in Table 3 1 Pin Signal Direction Termination 1 TRST Input to the UUT 1K pull up 2 GND 3 TDI Input to the UUT 1K pull up 4 GND 5 TDO Output of the UUT 33 ohm series 6 GND 7 TMS Input to the UUT 1K pull up 8 GND 9 TCK Input to the UUT 1K pull up 10 GND Write_Strobe 11 GPIO1 SPI CS2 Input to the UUT 1K pull up 12 GND 13 1 Input to the UUT 1K pull up 14 GND Ready Busy 15 SPI SDO MISO Output of the UUT 1K pull up GPIO3 16 SPI_SDI MOSI Input to the UUT 1K pull up 17 VCCI UUT Power Test Point 1 None 18 I2C SCL Input to the UUT 1K pull up 19 VCC2 UUT Power Test Point 2 None 20 SPI_CS1 I2C SDA Input t
38. o the UUT 1K pull up Table 3 1 ScanTAP 4 TAP Pin Assignment Connecting to the Target 3 3 Note that only the first 10 pins are required For Flash Programming with external write or the Ready Busy signal use the first 16 pins of the TAP To build in support for power to ground short checking use all 20 pins of the TAP Pins 17 and 19 of each ScanTAP 4 connector can be used to sense that the target power pin is not shorted to GND Up to 2 different power pins can be checked on each of the four 20 pin connectors of the ScanTAP 4 box The 3 GPIO signals are general purpose output signals that are directly controlled by the Parallel I O menu of ScanPlus Runner Refer to the ScanPlus Runner manual for further information The dual purpose External Write GPIO1 signal is used for Flash programming and if used will override the Parallel Output GPIO1 function Refer to the ScanPlus Flash Programmer manual for further information about this function The dual purpose Read Busy GPIO3 signal is used for Flash programming and if used will override the Parallel Output GPIO3 function Refer to the ScanPlus Flash Programmer manual for further information about this function The ScanTAP 4 comes standard with 4 short cables that connect it to a target system with up to 4 TAP connectors These 20 pin to 10 pin cables Corelis P N 15310 are standard flat cables and can easily be made from off the shelf connectors Each cable mates with a m
39. onding to the interface voltage programmable on the PCI 1149 1 Tutbo from 1 25 to 3 3 V Recommended resistor values are 5 Vec Vee Vee Vee Vee Vee Vee 3 3V 3 3V i JE IL TRST to all bounday scan devices 7 to TDI of first device TDI in the chain Ki from TDO of last device in TDO chain TMS to all bounday scan devices TCK to all bounday scan devices i Write_Strobe GPIO1 to Flash Write_Strobe pin s lt GPIO2 lt a i Ready Busy GPIO3 from Flash Ready Busy pin s for voltage measurement UUT Power Test Point 1 I2C SCL l to 12C short testing i devices for voltage measurement UUT Power Test Point 2 120 SDA to 12C short testing devices Figure A 7 20 pin TAP Connector Schematic for I2C Recommended Target Connectors A 11 Appendix B Self Test Utility Software The PCI 1149 1 Turbo has a self test utility that can be used to test the card and make sure that it is fully functional Logic at the TAP connectors can read back data shifted out on TMS and TDO synchronously with the TCK Using these signal paths a host can test the TAP signals all the way to the connectors verifying the overall functionality of the system Self Test The self test utility is provided for off line confidence test only and under normal circumstances there is no need to run the self test utility software However if you
40. p 19 vce2 UUT Power Test Point SPI CS1 20 I2C SDA Input to the UUT 1K pull up Table A 6 Signal Description and Termination Recommended Target Connectors Figure A 6 shows a typical schematic of the target TAP connector with termination resistors The 1K pull up resistors should connect to the target Vec supply corresponding to the interface voltage programmable on the PCI 1149 1 Tutbo from 1 25 to 3 3 V Recommended resistor values are 5 Vcc Voc Voc Voc Vcc Vcc Vec Vcc Vec to all bounday scan devices lt to TDI of first device in the chain from TDO of last device in the chain to all bounday scan devices lt s TCK to all bounday scan devices to SPI device Write Strobe SPI CS2 GPIO1 Flash Write Strobe pin s si SPI_SCK GPIO2 to SPI device s lt from SPI device s Ready Busy SPI SDO GPIO3 Flash Ready Busy pin s i for voltage measurement UUT Power Test Point 1 voltage short testing i for voltage measurement UUT Power Test Point 2 voltage short testing SPI SDI gt to SPI device s SPI CS1 V gt to SPI device Figure A 6 20 pin TAP Connector Schematic for SPI A 10 Recommended Target Connectors Figure A 7 shows a typical schematic of the target TAP connector with termination resistors The 1K pull up resistors should connect to the target Vec supply corresp
41. ple TAPs use the same voltage settings for all the TAPs it is not uncommon to find targets that use for example the 3 3 V setting for one TAP 2 5 V for another and 1 8 V for one or two additional TAPs The Advanced Configuration screen is shown in Figure 4 4 ScanTAP Advanced Configuration 4 x Output Voltage gt Input Threshold 7 TAPI Voltage 330v y TAP1Theshold automatic TAP2Voltage 330v y TAP2Theshold automatic TAP3 Voltage 330v y TAP3Theshold Automatic y TAPA Voltage 330v v TAP4Threshold BEE Cancel Figure 4 4 Advanced Configuration Setup Screen 4 4 Using PCI 1149 1 Turbo with ScanPlus ScanTAP 4 TAP Configuration The ScanPlus Tools provide 3 different methods to specify the TAP s that connect the ScanTAP 4 to the target system Method 1 The TAP Configuration select box in the Controller Configuration screen see Figure 4 3 This is the preferred and most straightforward method for selecting which of the 4 ScanTAP 4 TAPs to use for connecting to the target Method 2 Embedding the TAP selection text as part of the test step file name This method is explained below and is primarily supported for upwards compatibility with legacy tools Method 3 Using the ScanPlus Runner tool Options menu Use this method only when specific test step s require TAP configuration settings different from the global settings selected in Method 1 above Using PCI 1149 1 Turbo w
42. provided for ScanPlus Runner Selecting the card in ScanPlus Debugger or ScanPlus Flash Programmer is done in a similar fashion 1 Invoke the ScanPlus Runner application 2 Click the Setup menu item and then select the Controller entry to display the Controller Configuration screen shown in Figure 4 1 Configuration x Test Plan Generation User Settings Controller Configuration Parallel Outputs Controllers Controller Settings PCI 1149 1 Turbo smo no PCI 1149 1 Net 1149 1 Null Device m Current Controller Null Device Cancel Apply Help Figure 4 1 Controller Configuration Screen Using PCI 1149 1 Turbo with ScanPlus 4 1 3 Select the PCI 1149 1 Turbo controller from the icons on the left Adjust the settings to the desired values 4 After you have made your selections click on the Apply button to test and save the settings When the program saves the settings successfully it displays the controller in the Current Controller box If ScanPlus Runner cannot find the controller it displays an error dialog 5 Once ScanPlus Runner finds the PCI 1149 1 Turbo controller if for some reason the Scan TAP 4 is not connected to it it displays a screen similar to Figure 4 2 If the ScanTAP 4 is connected after seeing this screen you must exit this program and re statt at step 1 Configuration xj Test Plan Generation User Settings Controller Configuratio
43. resent and free from visible damage or defects before proceeding If anything appears to be missing or damaged contact Corelis at the number listed on the front cover immediately The ScanTAP 4 typically consists of the following components and is shown in Figure 2 1 e ScanTAP 4 box e Host Cable 6 foot 68 pin SCSI type one to one Cable Corelis P N 15314 e Asset of four 20 pin to 10 pin TAP cables Corelis P N 15310 PCI 1149 1 Turbo 68 Wire Cable Cables P N 15310 ScanTAP 4 Figure 2 1 Picture of the PCI 1149 1 Turbo and ScanTAP 4 Hardware PCI 1149 1 Turbo Installation 2 1 NOTE The actual hardware shipped to the customer may vary depending on the customer order When this manual was published the following optional target interface TAP cables were available from Corelis e Bag of 4 TAP cables 20 pin to 16 pin TAP Corelis P N 15311 e Bag of 4 TAP cables 20 pin to 20 pin TAP Corelis P N 15312 e Host Cable 15 foot 68 pin SCSI type one to one cable Corelis P N 15328 e Host Cable 30 foot 68 pin SCSI type one to one cable Corelis P N 15329 Software Installation First The installation procedure requires the use of software that contains the driver for the PCI 1149 1 Turbo card Obtain the ScanPlus CD ROM or any other Corelis application that supports the PCI 1149 1 Turbo card in order to proceed with installation Install the ScanPlus Application Software before installing the PCI 1149 1 Turbo contro
44. rget paces the sequence by indicating a non ready completion of data transfer requiring a re scan of the target s status When not in this special mode the scan stream bursts at the programmed TCK rate as paced by the flow of vector bits from the host Another performance enhancement provides hardware expected value verification of scanned back data at programmable chain positions Thus the target output stream is evaluated without host intervention and accompanying process delays This further supports the above autonomous operation enabling the scanning sequence to loop and rescan until the desired feedback is supplied also without host intervention A programmable time delay skew compensation mechanism supports the PCI 1149 1 Turbo s high clock rates This accommodates the returned target scan stream delays due to signal travel time down and up the cables It can also adjust for a target s on board TCK to TDO response delay An auxiliary feature of the PCI 1149 1 Turbo is the target power shorted detector for two voltages With the target un powered this mechanism effectively measures the impedance of the target load for each of two possible connected voltages determining if a short exists some unacceptably low impedance If this impedance is less than about 1 ohm about an 11 watt target or greater at 3 3V for example it is deemed shorted Adjustable Voltage Interfaces The softwate programmable voltage level of the parallel I
45. rt no 787171 7 or equivalent 6 foot standard Corelis P N 15314 15 foot optional Corelis P N 15328 30 foot optional Corelis P N 15329 Four 20 pin shrouded headers 0 1 in X 0 1 in spacing 4 80 MHz Concurrent scanning at all TAPs occurs at up to the full TCK rate capability of the PCI 1149 1 Turbo unlimited 1 25 to 3 3 V in 0 05 V increments 4 each TAP can have its own programmable voltage settings See Table 1 2 Symbol Test Conditions Limit Min Limit Max Units Vin Vdd Adjust gt 2 5 V 2 Vdd 0 5 V Vdd Adjust lt 2 50 V 0 65 x Vdd Vdd 0 5 V Vy Vdd Adjust gt 2 00 0 7 V Vdd Adjust lt 2 0 0 35 x Vdd V Von Ion 2 mA Vdd 0 35 V Vor lo 2 mA 0 45 V Vdd 1 65 V Ion Vdd 1 65 1 95 V 4 mA Ior Vdd 1 65 1 95 V 4 mA Table 1 2 ScanTAP 4 DC Characteristics Note Also refer to Low Voltage CMOS LVC family signal characteristics data available from TI Product Overview SPI Interface ScanTAP 4 with Blue LED Only SCK frequency 1 MHz Signal DC Characteristics See Table 1 3 Symbol Test Conditions Limit Min Limit Max Units Vi Vdd Adjust gt 2 5 V 2 Vdd 0 5 V Vdd Adjust lt 2 50 V 0 65 x Vdd Vdd 0 5 V Vir Vdd Adjust gt 2 00 0 7 V Vdd Adjust lt 2 0 0 35 x Vdd V Von Ion 2 mA Vdd 0 35 V Ip 2 mA VoL 0 45 V Vdd 1 65 V Tou Vdd 1 65 1 95 V 4 mA doi Vdd 1 65 1 95 V 4 mA
46. sible through the PCI bus controls all functions of the PCI 1149 1 Turbo Parallel Ports Input Connector Parallel Ports Output Connector ER y PORT A PORT B PORT A PORT B Low Voltage Low Voltage Low Voltage Low Voltage 6 INPUTS INPUTS OUTPUTS OUTPUTS y 8 k w Pe ug MEMORY 8 2x TAP D 2 EU gt gt S Interface Ru Cc v SO lt O sli an MEMORY 5 ScanTAP ah Er 2 om 9 Programmable i CLOCK GENERATOR CONTROL STATUS Registers PA PCI INTERFACE Lo WI III Figure 1 3 PCI 1149 1 Turbo Block Diagram Product Overview 1 3 The PCI 1149 1 Turbo TAP controller contains special autonomous hardware accelerator mechanisms to greatly increase performance where scan patterns repeat numerous times This applies to target download upload sequences conveying large data blocks As a result time consuming tasks such as flash programming and emulator data transfers are more efficient for a given clock rate This mechanism off loads the host interaction requirements by generating repeated vectors internally using host pre loaded memory information After host initialization this mode of operation results in continuous maximal scanning rates at all clock frequencies The only exception occurs when the ta
47. suspect that the board is damaged you can tun the self test on the PCI 1149 1 Turbo card The self test utility is installed on your computer in the same folder where ScanPlus Applications ScanPlus Runner ScanPlus Debugger and ScanPlus Flash Programmer ate installed Make sure to disconnect any ScanTAP 4 TAP cables before running the test Using the Windows Explorer select and run the pcilld9 t test exe file A small pop up should appear The program checks for the presence of a ScanTAP 4 and runs the appropriate test Make sure that there is no target connected to the controller or to the ScanTAP 4 before running the self test as they can cause the test to fail Click on Test to run the self test The program should respond with results similar to the screens shown in Figure B 1 and Figure B 2 Self Test Utility Software B 1 PCI 1149 1 Turbo Self Test val rd Vv M val val Management Bus Test ADC DAC on ScanTAP J_ POD Event Test GAO Test Figure B 1 Self Test Result for the PCI 1149 1 Turbo when the ScanTAP 4 is NOT connected B 2 Self Test Utility Software PCI 1149 1 Turbo Self Test PASSED KUL DAL Programmable Voltage PASSED Vv El Vv Vv val val Vv Vv Vv Vv Figure B 2 Self Test Results for the PCI 1149 1 Turbo with the ScanTAP 4 Connected Self Test Utility Software
48. t connectors are available from other manufacturers Reference Description Manufacturer Part Number Flash TAP Straight header 16 pin 4 wall with center notch 3M 2516 6002UG Table A 5 Flash Programming TAP 16 Pin Connector Table A 4 describes the signals and Corelis recommended values of terminating resistors Pin Signal Direction Termination 1 TRST Input to the UUT 1K pull up or 1 5K pull down S 2 GND 3 TDI Input to the UUT 1K pull up 4 5 Output from UUT 33 ohm series 6 GND 7 Input to the UUT 1K pull up 8 GND 9 TCK Input to the UUT 1K pull up O Write_Strobe Note Some target boards may require a pull down resistor on the TRST signal to assure normal device operations when not in boundary scan test mode Note The target TDI signal is driven by the TDO signal of the boundary scan controller 11 GPIO1 Input to the UUT 1K pull up SPI CS2 12 GND Note The target SPI SCK TDO signal drives 13 GPIO2 Input to the UUT 1K pull up the boundary scan controllers TDI 14 GND signal Ready_Busy SPI_SDO Output from the 15 MISO UUT 1K pull up GPIO3 SPI_SDI 16 MOST Input to the UUT 1K pull up A 8 Recommended Target Connectors UUT Power Test 17 VCC1 Point 18 I2C SCL Input to the UUT 1K pull u
49. ut to the UUT 1K pull up di 4 GND mode 5 TDO Output from UUT 33 ohm series 6 GND Note The target 7 TMS Input to the UUT 1K pull up TDI signal is driven 8 GND by the TDO signal of the boundary scan 9 TCK Input to the UUT 1K pull up Sole O Write Strobe Input to the UUT 1K pull up 12 GND Note The target 13 Resetyed TDO signal drives ETE ER EI a the boundary scan 14 Reserved controller s TDI 15 Ready Busy Output from UUT 1K pull up signal 16 Reserved Table A 4 Signal Description and Termination Recommended Target Connectors A 5 Figure A 4 shows a typical schematic of the target TAP connector with termination resistors The 1K pull up resistors should connect to the target Vcc supply corresponding to the interface voltage programmable on the PCI 1149 1 Tutbo from 1 25 to 3 3 V Recommended resistor values are 5 Target Board To all Boundary Scan Devices To TDI of 1st Device in the chain From TDO of last Device in chain To all Boundary Scan Devices To all Boundary Scan Devices To flash device s WE control From flash Read Busy pin s Figure A 4 Flash Programming TAP Connector Schematics A 6 Recommended Target Connectors 20 pin TAP Connector To build in support for in circuit programming of flash or microprocessor devices Corelis recommends including supplemental control signals in the TAP interface The ScanPlus Flash
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