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UM1556 - STMicroelectronics

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1. 72 6 1 Paralleling of CS DIS current sense disable and IN input 72 6 1 1 Monolithic HSDs supplied from different supply lines 72 6 1 2 Hybrid HSDs supplied from different supply lines 73 6 1 3 Mix of monolithic and hybrid HSDs 74 6 2 Paralleling of CS pins current sense 75 6 2 1 Monolithic HSDs supplied from different supply lines 76 6 2 2 Hybrid HSDs supplied from different supply lines 77 6 2 3 Mix of monolithic and hybrid HSDs supplied from different supply lines 78 7 ESD protection asada sz ek Rok ados Cd UR e 80 7 1 ESD protection of HSD calculations 80 7 2 ESD protection ECU level layout consideration 84 8 Robust design 85 8 1 Design suggestions for HSDs and relays on the same PCB 85 9 REVISION history 86 Doc ID 023520 Rev 2 3 87 List of tables UM1556 List of tables Table 1 Datasheet values Table 2 Reverse battery protection of monolithic HSDs only comparison Table 3 CS pin levels in 5 Table 4 Analogue driver truth table OFF state Table 5 Anal
2. 29 2 7 3 K factor calibration method 30 2 8 Analogue current sense diagnostics 32 2 9 Open load detection in off state external circuitry for analogue M0 5 HSD Sd ede Si iu d 35 2 10 Open Load detection off state M0 5Enhanced HSD 36 3 Digital status output 37 2 87 Doc ID 023520 Rev 2 ky UM1556 Contents 3 1 Digital HSD diagnostics 37 4 Switching inductive loads 39 4 1 Turn on phase behaviour 39 4 2 Turn off phase behavior 40 4 2 1 Calculation of energy dissipated inthe HSD 41 4 2 2 Calculation example 42 4 3 Proper HSD lt 44 4 3 1 Example of VND5E160AJ driving relays 44 4 4 External clamping selection 47 4 4 1 Clamping circuitry examples 48 4 4 2 Component selection guide for external transil diode clamping 52 4 4 3 Examples of VN5E025AJ for DC motor driving with external clamp 56 5 High Side Driver selection for lamploads 66 6 Paralleling of HSDS
3. GND GND GND GND Doc ID 023520 Rev 2 65 87 High Side Driver selection for lamp loads UM1556 5 High Side Driver selection for lamp loads This chapter proposes drivers that can be used for typical automotive lamp loads or typical combinations of lamps A properly selected driver should allow the safe turning on of the bulb without any restrictions under normal conditions Under worst case conditions the driver should still be able to turn on the bulb even if some protection of the driver may be triggered temporarily However the driver s long term integrity should not be jeopardized In order to decide which driver is suitable to turn on a lamp three conditions are first defined see a b and c below Afterwards a simulation is performed with the pre selected bulb driver combination in order to verify the driver matches the requirements under the defined conditions The tool used for this simulation is based on Matlab Simulink Figure 54 Principle of the setup used for the simulations Line in A 10 m 16V A lt VN5E0104H Remance Z FootP Hpak I GAPGMS00128 The prerequisite to appear in Table 12 Table 13 Table 14 Table 15 is that the driver has to fulfill all of the following three requirements a Normal condition 13 5 V Te 25 C Tpulb 25 G Requirement none of the protection functions must be triggered 66 87 Doc ID 023520 Rev
4. ae ls I lee 2 o 2 c 1 H a H I i d tus ts 1 US 10 100us ims 10ms Wave S 20ug 8 20 4 Wave 10 1000us 10 1000 t Pulse Time seconds GAPGMS00120 Figure 45 Equivalent pulses giving the same power dissipation 1 1l Exponential Rectangular 0 5 Lz1 LR 1 41 t 1 1 Sawtooth Sinusoidal 0 5 t t Ly 1 4L Ls 2 2L GAPGMS00121 Figure 46 Maximum peak power as a function of initial temperature of the transil P Tj 25 C 125 100 75 50 25 0 0 50 100 150 200 Tj initial GAPGMS00122 e Repetitive pulse energy capability Depending on the application PWM HSD thermal cycling the transil should be able to withstand repetitive operation and the most important parameter is the average power dissipation 54 87 Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads Equation 16 Pava f E valid when 4 TpEMAG S f f switching frequency E energy dissipated in transil at each demag pulse Equation 17 eu at n tv PS VoL transil clamping voltage R load resistance L load inductance lo load current at turn off event The junction temperature Tj calculated from Payg should never exceed the maximum specified junction temperature Equation 18 Tj TAmp Rin j a Pave TAmp ambient temperature Rth j a therma
5. UM1556 ST User manual M0 5 and MO 5Enhanced high side drivers Introduction The aim of this document is to give the design engineer a comprehensive tool kit to better understand the behavior of high side switches allowing easier design and saving time and money Today s VIPower high side switches represent the 5th generation of smart power drivers the so called MO 5 In this latest generation of drivers all the experience and know how derived from previous generations have been implemented in order to improve robustness increase functionality and raise package density while maintaining lower prices The complexity of a modern High Side Driver HSD is still relatively low compared to many other logic ICs However the combination of digital logic functions with analog power structures supplied by an unstabilized automotive battery system across a wide temperature range is very challenging for such a device The M0 5 components today meet all the above criteria providing an optimal price performance ratio by offering the highest performance and robustness at excellent prices September 2013 Doc ID 023520 Rev 2 1 87 www st com Contents UM1556 Contents 1 General UN SIN Sa in nn eb ag ar UC aei Da nm an hr tr Sec om 7 1 1 Application schematic monolithic digital monolithic and hybrid analogue icr MP 7 1 2 Reverse battery protection 9 1
6. Hard short to GND 3 Short to GND Short to GND 7 feedback Trip time to thermal shutdown y z Figure 18 M0 5Enhanced Hard short to GND lu Short to GND Current sense switches to VsenseH as soon as Power Limitation is triggered 1 4 5 Indication of power limitation example for digital driver Figure 19 M0 5 Soft short to GND Figure 20 M0 5 Hard short to GND E 100 B 500v 100V B 200A 6000 20008 Stop 20 nwaa va Short to GND Short to GND STATI ae S Time to diagnostics i feedback Trip time 20 87 Doc ID 023520 Rev 2 ky UM1556 General items Figure 21 MO 5Enhanced Soft short to GND GND Figure 22 MO0 5Enhanced Hard short to Short to GND pes Switches tO logical 0 as soon as Power Limitation is triggered Short to GND 1 4 6 Table 4 M0 5Enhanced analogue current sense truth table Analogue driver truth table OFF state Operation mode Normal operation Short to Vbat Open load Short to GND Overtemperature Input level Output level Current sense L 0v Vbat VSENSEH V with external pull up SENSEH L L without external pull up OV L oV L 0v Doc ID
7. or Vbat2 e Positive voltage surge either on Vbat1 or Vbat2 while Device GND pin disconnected not used resistor protection only Positive pulse energy higher than HSD or Dona capability all paralleled devices can be damaged Doc ID 023520 Rev 2 ky UM1556 Paralleling of HSDs 6 1 2 A negative voltage surge ISO7637 2 pulse 1 either on Vbat1 or Vbat2 is directly coupled to the HSD GND pin through the involved Vcc GND clamp structure As soon as this occurs and the negative voltage on GND pin is large enough to activate all involved clamp structures there may be an unlimited current flow through both CS_DIS pins supported by current from Vcc through the associated parasitic bipolar structure This current can lead to malfunction or even failure of one or both of the HSDs A positive voltage surge ISO7637 2 pulse 2a 3b either on Vbat1 or Vbat2 may lead to the HSD GND pin to rise in voltage in case of missing Dgnd Dgnd failure or GND pin disconnected As soon as this occurs the voltage on CS_DIS pin also rises the CS_DIS pin clamp structure is linked with the GND If the voltage on the CS_DIS line reaches 6 3 V clamp voltage on CS_DIS pin there may be an unlimited current flow through both CS_DIS pins supported by current from Vcc through the associated parasitic bipolar structure This current can lead to malfunction or even failure of one or both of the HSDs In order to avoi
8. Vbatl Vbat2 A A 100nF 50V 100nF 50V GND U2 Vcc G Vcc Pwr Clamp Pwr Clamp USE h t CS_DIS CS_DIS OUT OUT NY pe Suma cs GND 5 ADC IN GND GND de GND Rsense p GND GND Direct connection of CS pins is not safe in following cases e Loss of Vbat or Vbat2 e Loss of GND connection Loss of either Vbat1 or Vbat2 leads to an incorrect current sense signal If Vbat2 is lost U2 logic part is supplied by U1 current sense signal through the internal Vcc CS clamp structure Therefore the voltage on CS bus drops and we no longer have an accurate VSENSE reading If the GND connection of one device is lost positive as well as negative ISO pulses on the associated supply line are no longer clamped considering no other devices connected on this supply line If the transient voltage is high enough to activate involved clamp structures there may be an unlimited current flow between both supply lines through the CS pins This current can lead to malfunction or even failure of one or both of the HSDs In order to ensure a valid current sense signal and to protect devices in all previously described cases we can add a diode in series to each CS pin
9. A positive ESD pulse the output is transferred through the body diode of the power MOSFET to the Vcc pin of the HSD so the same requirements to dimension the external capacitor apply as the negative ESD pulses on the output Clamping structure in HSD ESD protection ECU level layout consideration An ESD pulse on a powered ECU output connector is an expected event during the life of a Car Typically contact and air discharge tests are performed during module qualification Ref IEC61000 4 2 The possible risk at application level is an early failure of the HSD with a following resistive short circuit between Vcc and OUT The ESD pulse destruction value strongly depends on the module layout To make the module pass the required stress level add a 100 V ceramic capacitor with a value in the order of tens of nF to the output close to the connector This capacitor decreases both the applied dv dt and the maximum output voltage seen by the HSD ESD strike Battery output capacitor Doc ID 023520 Rev 2 ky UM1556 Robust design 8 Robust design 8 1 Design suggestions for HSDs and relays on the same PCB A typical ECU today still employs along with the smart power HSDs and LSDs a certain number of electromechanical relays The activation of these relays being on the same PCB and supplied by the same battery line as the HSDs may lead to fast dv dt on the battery line due to boun
10. GND Optional See Note 2 C3 10nF 100V GND GND GND GAPGMS00083 If status disable function is not required ST DIS pin should be left open or connected to ground through a resistor 10 Direct connection to ground is not safe ISO pulses clamped through ST DIS pin can damage the device Pull up R5 is optional for open load detection in off state No pull down resistors are necessary on IN and ST DIS pins due to the internal pull down structure Doc ID 023520 Rev 2 7 87 q General items UM1556 Figure 2 Monolithic analogue HSD application schematic 5V Vbat Vbat_switched R5 10k Optional for MO 5Enhanced See Note 5 U3 C3 10nF 100V Dgnd GND GND GND GND GND GAPGMS00085 Figure 3 Hybrid analogue HSD application schematic Vbat Vbat switched Loonk Sov RS 10k Optional for M0 5Enhanced See Note 5 U3 C3 10nF 100V GND GND GND GND GND GAPGMS00086 4 If current sense disable function is not required CS DIS pin should be left open or connected to ground through a resistor 10 kQ Direct connection to ground is not safe ISO pulses clamped through CS_DIS pin can damage the device ISO pulses refered to ISO 7637 2 2004 E 5 Pull up R5 is optional open load detection in off state capability in case of MO 5Enhanced Q 8 87 Doc ID 023520 Rev 2 UM1556 General items 1 2 Reverse
11. 10 pA IGND DC reverse GND current max 200 mA Is oN On state supply current max 3 mA Vstat Low level status voltage max 0 5 V at 1 6 mA ST72F561 Vou Output high level voltage min 4 3 V at 2 mA Vit Input low level voltage max 0 3 Vpp Doc ID 023520 Rev 2 ky UM1556 General items The maximum acceptable ground shift level is the maximum drop voltage on Renp that does not influence the communication between HSD and UC e STATUS signal level check as seen in Table 1 the microcontroller can safely recognize log L when the input voltage is below V 0 3 Vpp 0 3 x 5 1 5 V The maximum low level voltage on the HSD status pin 0 5 V This means there is a 1 5 V 0 5 V 1 V safety margin for voltage drop Rawp e INPUT signal level check as seen in Table f the microcontroller output high level 4 3 V is clearly above the HSD minimum input high level 2 1 V The voltage drop on the protection serial resistor is relatively small Rppor 10 k x 10 pA 0 1 V Hence there is a 4 3 V 0 1 V 2 1 V 2 2 1 V safety margin e Result the maximum acceptable drop voltage on Renp is 1 V For safety reasons we consider Venp 0 8 V for the following calculations 2 Calculate resistor value VaND _ 0 8V Is on max 9mA VBAT 14V 7 R gt 2700 200mA 3 Check power dissipation in reverse mode gt select resistor package 2 _ 14v 0 89
12. 3 37 ms lo TpEMAG e Average power dissipation repetitive turn off Assuming that the HSD is in a thermal shutdown condition with autorestart frequency assumed to be 500 Hz and lg lj gt 15 A Doc ID 023520 Rev 2 61 87 Switching inductive loads UM1556 62 87 Energy dissipated in the freewheeling diode Equation 17 HSD turn off lg li 15 A 0 L lo lg Vou 1 _ 1 15 0 6 sug 000073 0 6 15 1 100 1 15 0 8 5 13 6mJ Demagnetization time for lg lj 15 A Equation 12 _ L IVbEMAG tlo R 0 00073 1 15 0 6 _ TpEMAG g og ge t l 06 2 8ms The demagnetization time 2 8 ms is higher than the assumed HSD cycling frequency period 2 ms Therefore the average power dissipation on the freewheeling diode cannot be easily calculated using Equation 16 Payg f E 500 x 0 0136 6 8 W real value is significantly lower As a rough estimation we can use the average power dissipation during one demagnetization pulse E _ 0 0136 _ Paya 4 9W AVG TpEMAG _ 0 0028 1N5401 Varm 1 00 V lesm 200 A 8 3 ms Pp 6 25 W Step 6 Measurement confirmation of theoretical analysis e Transil diode protection circuitry SMBJ16A 1N4002 The measurement was done at room temperature on VND5E025AK loaded with a blocked DC motor as specified in the beginning and with external protection regarding Choice 1 SMBJ16A 1N4002 Doc ID 023520
13. Diagnostics Symbol Value Value H H VSENSE LoL L st i ini sample aiter viri wira minimum Delay response time from rising Condition delay of 600us and wait to t1 see SC to edqe of INPUT pin must be considered for 2 sample to distinguish g ass between SC to GND see minimum 300 ps Open load without pull Vi u up w Fe A 27 O P E A sg Waveform Vsense Vse ot inmates tosensem t VIN H H L VsENSE LL VSENSEH Open load Condition N A with pull up Same as open load without pull up Vin Waveform No diagnostics in off state VSENSEH t tosTKON VIN H H L VsENSE Nominal Nominal VSENSEH Condition N A N A Short circuit to VBAT V VN Waveform VsENSEH Vsense lt Nominal Vas tosTKON X Doc ID 023520 Rev 2 33 87 Analogue current sense UM1556 Table 8 Analogue HSD diagnostics continued M0 5 M0 5Enhanced Diagnostics Symbol Value Value VIN H H V VsENSE L gt VSENSEH V Poner or VSENSEH thermal shutdown shutdown 1st sample after ViN H with a minimum delay of 600 us and wait until thermal shutdown t1 for 2nd sample to A distinguish between open load Condition t1 depends on package cooling area SC resistance ambient temperature etc SC to GND range of 50 1000 ms see 1 Tj gt Trsp Typ 175 C tr SSS wo JU Waveform e r Vsense li VsENS
14. Figure 47 ky Monolithic digital HSD application schematic 7 Monolithic analogue HSD application schematic 8 Hybrid analogue HSD application schematic 8 Voltage levels during reverse battery resistor protection 9 Logical levels 10 Voltage levels during reverse battery using diode resistor protection network 12 Positive ISO pulse sc iaaiiai a i aa hh 13 Negative ISO 13 Voltage levels during reverse battery MOSFET protection 14 Hybrid HSD reverse battery protection with self switch on of the MOSFET 16 Example Self switch on of MOSFET eliminated by Dgnd 16 ISO pulse transfer to 17 Open load short to Vcc condition 18 Open load short to Vcc condition 19 MO0 5 Soft short to GND 0 20 5 short to GND 20 MO 5Enhanced Soft short to GND 20 MO 5Enhanced Hard short to GND 20
15. Maximum turn off current versus inductance VND5E160AJ datasheet I FEF r A Tistart 150 C single pulse B T stan 100 C repetitive pulse 4 C 125 C sed GAPGMS00116 Therefore it is convenient to translate I L chart to chart This can be easily done using Equation 15 for the calculation of energy on the HSD considering Ri 0 Vgar 13 5 V see Figure 40 Figure 40 Maximum demagnetization energy VND5E160A Maximum demagnetization energy VND5E160AJ calculated from I L curve in datasheet 1920 99 1 2 1354 325 Eux 11 2 32 5 10 00 X Relay 9 9mJ 260mH e A Tjstart 150 C single pulse B Tjstart 100 C repetitive pulse C Tjstart 125 C repetitive pulse 1 00 0 1 1 10 100 1000 L mH GAPGMS00117 46 87 Doc ID 023520 Rev 2 UM1556 Switching inductive loads Waveform A represents the max energy the device can withstand in a single pulse A second pulse with the same energy can destroy the part Waveforms B and C represent the max energy
16. The transil T clamps the demagnetization voltage to a safe level The clamping voltage of the transil should be selected in a way that the voltage across the HSD channel is below the minimum specified clamping voltage of the HSD 41 V The diode D is included to protect the transil during normal operation positive output voltage 2 Transil protection circuitry in parallel with the HSD Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads Vbat A Clamp et eet d F OUT i out GND L Vout Rend SZ Dgnd R GND GND The HSD channel is protected directly by the parallel transil The clamping voltage of the transil should be below the minimum clamping voltage of the HSD 41 V Such transils VoL lt 41 V usually start conducting at 30 V therefore there is a high probability that it is damaged during the clamped load dump pulse 36 V For that reason it is usually better to use the previously described solution 1 3 Freewheeling diode and reverse battery diode Vout GND GND GND A general purpose diode connected in parallel with the load provides a conductive path for proper demagnetization Relatively small demagnetization voltage 1 diode voltage drop in forward direction leads to a very slow demagnetization This can have a negative influence when driving the relay for example A slow movement of the armatu
17. Vbat 0 7 V leads to the activation of both CS_DIS clamp structures when Vpar is below 7 5 V and two diode voltage drop The resulting current can lead to malfunction or even failure of one or both of the HSDs In order to avoid such failure add a 10 KQ resistor in series to each CS_DIS pin as already described in case of paralleling of monolithic devices see Figure 6 1 1 Monolithic HSDs supplied from different supply lines on page 72 In principle the same applies to the input pins the clamp structure is the same as on CS_DIS pin Paralleling of CS pins current sense The following chapters describe the paralleling of CS pins of HSDs taking into account device technology monolithic HSDs or hybrid HSDs and supply line configuration either the same or separate supply line for each HSD Direct connection of CS pins is generally allowed when the devices are supplied from one supply line In case of separated supply lines we should use additional components to ensure a safe operation under conditions in automotive environments ISO pulses reverse battery Doc ID 023520 Rev 2 75 87 Paralleling of HSDs UM1556 6 2 1 76 87 Monolithic HSDs supplied from different supply lines Paralleling CS pins of monolithic HSDs is possible however some precautions in schematics should be applied if the HSDs are supplied from different supply lines Direct connection of CS pins as shown in the next picture
18. and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION OR INFRINGEMENT OF ANY PATENT COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN A SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCT
19. is not safe Figure 59 Direct connection of CS pins not recommended Monolithic HSD Vbatl Vbat2 loss of Vbat2 i00psov 10QnF SOV ADC IN Vanna nane Vsense mfluenced T GND GND GND GND GAPGMS00136 Direct connection of CS pins is not safe in following cases e Negative voltage surge on either on Vbat1 or Vbat2 e Positive voltage surge either on Vbat1 or Vbat2 while Device GND pin disconnected not used resistor protection only Positive pulse energy higher than the HSD or Dgnd capability all paralleled devices can be damaged e Loss of Vbat1 or Vbat2 A negative voltage surge ISO7637 2 pulse 1 either on Vbat1 or Vbat2 is directly coupled to the CS pin through the internal Vcc CS clamp structure If the negative voltage on the CS line is high enough to activate the Vcc CS clamp structure there may be an unlimited current flow through both CS pins This current can lead to malfunction or even failure of one or both of the HSDs A positive voltage surge ISO7637 2 pulse 2a 3b either on Vbat1 or Vbat2 together with missing Dgnd Dgnd not used Dgnd failure or GND pin disconnected can activate the Vcc CS clamp structure clamp voltage similar to Vcc GND clamp As soon as this occurs there may be an unlimited current flow through both CS pins This current can lead to malfunction or even failure of one or both of the HSDs Loss of either Vbat1 or Vbat2 l
20. simplified for R 0 Substituting the Tpemac and iour t by the formulas above we can calculate the energy dissipated in the HSD TpEMAG TpEMAG FHsD J VcLAMNP lour t dt f Vaar Vpeuagp lourltat then Equation 14 _ VBAT VpEMad ay y iol lo P oto ow Plo loe 90 Woemaal Equation 15 Vaar VpEMAGI 1 lim gt L 12 Hog SD 2 0 IVbEMac simplified for R0 Calculation example This example shows how to use above equations to calculate the demagnetization time and energy dissipated in the HSD Conditions Battery voltage Vgar 13 5 V HSD VNQ5EO050AK E Clamping voltage Vcr AMP 46 V typical for M0 5 MO 5E Load resistence R 81Q Load inductance L 260 mH Load current before turn off event l Vgar R 167 mA Step 1 Demagnetization voltage calculation using Equation 11 VpEMAG Vgar VcLANP 135 46 325V Step 2 Demagnetization time calculation using Equation 12 Doc ID 023520 Rev 2 ky Switching inductive loads UM1556 L IVbEMAG lo 0 260 32 5 0 167 81 T log log J 1 12ms DEMAG R VpEMAG 81 32 5 Step 3 Calculation of energy dissipated in the HSD using Equation 14 V 1 BAT DEMAG 0 E Oe EL I R l V log HSD R2 0 DEMAG VDEMAG 13513250260 81 0 467 325 06 229 e 4 04mJ 81 32 5 Step 4 Measurement compari
21. 2 1 Reverse battery protection of monolithic HSDs 9 1 2 2 Reverse battery protection of hybrid HSDs 15 1 3 Microcontroller protection 16 1 4 Introduction of MO 5Enhanced products 17 1 4 1 New features overview 18 1 4 2 Open load in off state short to Vbat 18 1 4 3 Indication of power limitation 19 1 4 4 Indication of power limitation example for analogue driver 19 1 4 5 Indication of power limitation example for digital driver 20 1 4 6 MO 5Enhanced analogue current sense truth table 21 1 4 7 Indication of power limitation the advantages 22 2 Analogue current sense 23 2 1 Introduction D EE 23 2 2 Simplified principle of operation 23 2 3 Normal operation channel ON CS DIS low 24 2 4 X Overtemperature indication channel ON CS DIS low 27 2 5 Current sense ESD and spikes protection 27 2 6 Current sense resistor calculation 28 2 7 Diagnostics with different load configurations 29 2 7 1 Diagnostics with paralleled loads 29 2 7 2 Diagnostics with different load options
22. 2 ky UM1556 High Side Driver selection for lamp loads SubPiott T Time s b Cold condition 16 V T 25 C 40 C Requirement power limitation allowed for durations of less than 20 ms SubPlot1 12 Time s c Hot condition Voatt 16 V Tc 105 G Tbulb 25 Requirement driver must not run into thermal shutdown Doc ID 023520 Rev 2 67 87 High Side Driver selection for lamp loads UM1556 SubPlot1 Time s Note The mentioned criteria only refer to the inrush current at turn on of a cold bulb The steady state power dissipation and in case PWM is applied the additional switching losses of the driver also have to be considered in order not to exceed the maximum possible power dissipation This obviously becomes more important with a larger number of channels per package i e dual or quad channel drivers and high power loads applied to more than one channel Table 12 List of suggested bulb driver combinations 1 4 Bulb load W 65 Driver ron 10 Single channel part VN5010AK VN5E010AH VN5012AK VN5016AJ VN5E016AH Dual channel part VND5012AK VND5E012AY Quad channel part 68 87 Doc ID 023520 Rev 2 UM1556 High Side Driver selection for lamp loads Table 12 List of suggested bulb driver combination
23. External clamping circuitry examples 2 2 External clamping circuitry 4 Freewheeling diode and reverse battery FET Vbat Load is reverse battery protected High number of ext Low peak power components cost dissipation on D during demag phase suitable for high current inductive loads such as DC motors Slow demagnetization GND GND GND GND 4 4 2 Component selection guide for external transil diode clamping This chapter shows how to select proper a diode D and transil T for external clamping circuitry 1 Figure 42 External clamping transil and diode Vbat Vout GND GND GND Transil selection e Clamping voltage V A characteristic 52 87 Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads Figure 43 Transil V A characteristic Stand off voltage Breakdown voltage Vc Clamping voltage Leakage current Vay le lpp Peak pulse current lg Breakdown current aT Voltage temperature coefficient Ve Forward voltage drop Rp Dynamic impedance Unidirectional GAPGMS00119 Considering the worst case values 16 V Vuspciampwin 41 V the demagnetization voltage should be limited at least to 16 41 25 V Assuming 1 V voltage drop on the protection diode D we need a transil with Vc lt 24 V at the given current level load current at switch off event The clamping voltage is usually sp
24. HSD Negative ISO pulses still pass GND and logic terminals The diode should withstand clamped ISO currents in case of positive ISO pulses and reverse voltages in case of negative ISO pulses Dimensioning of the diode 8 The most severe positive ISO pulse to consider is test pulse 2 at level IV 50 V 9 50 us This voltage is considered on top of the nominal supply voltage of 13 5 V so total voltage is 63 5 V The VIPower has a clamping voltage of typ 46 V minimum 41 V maximum 52 V In a typical device the remaining voltage is 63 5 V 46 V 0 7 V 16 8 V The ISO pulse generator interior resistance is given with 2 O Hence the resulting peak current through the diode is 8 4 A for a duration of 50 us a Result maximum peak forward current 8 4 A 50 us maximum reverse voltage 100 V Doc ID 023520 Rev 2 ky UM1556 General items Note Note Note Figure 7 Positive ISO pulse GND GND GAPGMS00093 The most severe negative ISO pulse to consider is test pulse 1 at level IV 100 V 2 ms This pulse is directly transferred to the GND pin The maximum peak reverse voltage of the diode should therefore be at least 100 V The diode works in avalanche mode if pulse level is above the rated reverse voltage Figure 8 Negative ISO pulse GND GND GAPGMS00094 As seen from the above explanation the HSD with diode protection in the GND pin doesn t clamp negative ISO pulses at
25. Philippines Singapore Spain Sweden Switzerland United Kingdom United States of America www st com Doc ID 023520 Rev 2 87 87 X
26. Rev 2 ky UM1556 Switching inductive loads Figure 51 Demagnetization energy measurement VND5E025AK Motor SMBJ16A and 1N4002 Vusp 39V gt No HSD clamp activated 41V lt 46 typ lt 52V 24V I 3e E 200m3 HSD power dissipation Vsar Vour our HSD energy E P d f Measure P1 rise N C1 P2 fall v C1 P3 duty C1 P4 duty C2 P5 freq C2 P6 value 27 74400 us 40 27 20 071 MHz status x w 10 0 Vidiv 10 0 Vidiv 10 0 A div 400 Widiv 20 00 V ofst 10 00 V ofst 0 00 A offset 200 psidiv R Trigger i 200 psidivi Stop 70V 1 00MS SOOMS sfEdge Negative GAPGMS00125 The measured energy is significantly lower than the calculated one 200 mJ measured versus 260 mJ calculated while the demagnetization time fits well This difference can be explained by measurement at ambient temperature when coil resistance is 25 higher than the resistance at 40 C used in the calculations Measured stall current was 19 A versus 25 A specification at 40 C As seen from the screenshot the external clamping circuitry SMBJ16A 1N4002 limits the demagnetization voltage to 24 V so the voltage across the HSD is maximum 39 V below internal clamp activation Reverse battery test The measured break down voltage of the external clamping circuitry is 19 V 1 mA gt fitting the 16 V 60 s reverse battery requirement The transil diode failed
27. Ri 0 60hm 4 T3 r C 125 C wee e jstart 7 Vear 13 5V R 0 ohm Emax AT 132mJ a Emax 74mJ y Emax p 62 5mJ 13 5V Ri 0 073 1 L mH 10 100 GAPGMS00123 The demagnetization energy is by a factor of 2 higher than the device is able to withstand therefore additional protection clamping is necessary The evaluation of an appropriate protection clamping is described in the following Step 5 Step 5 External clamping selection transil and diode The external circuitry is selected according to Table 10 We start with the evaluation of the circuitry with transil and diode as shown in Figure 48 Doc ID 023520 Rev 2 57 87 Switching inductive loads UM1556 Figure 48 External clamping circuitry border conditions 58 87 Vbat Vbat A A 16V Reverse battery ext clamping inactive 16V Demagnetization ext clamping active Jav Clamp OUT 15 5V OUT 25V Vout Vout GND GND GND GND GND GND GAPGMS00124 The diode D selection e Reverse voltage gt 52 V Must not conduct during positive voltage on the output maximum possible output voltage is limited by 92 V e Peak forward current gt 25 A 0 49 ms lo 1N4002 VRRM 100 V ESM 30A 8 3 ms The transil T selection e Stand off voltage gt 15 V Must not conduct dur
28. We should also consider the voltage drop on Rppor because the current required by the HSD input is typically 10 A The following condition must be fulfilled VPEAK VoH Viu R lt ltuC LATCHUP PROT Example 100V cp 43 21V 1V 20mA PROT lt lt 120kO Recommended value is 10 safe value for most automotive microcontrollers 1 4 Introduction of MO 5Enhanced products In addition to the established MO 5 drivers STMicroelectronics has introduced a new set of products called MO 5Enhanced As the name indicates these new drivers are based on the ST proprietary MO 5 technology but have some more sophisticated features The new features of the MO 5Enhanced family are aimed at improving the load handling as well as the overload diagnostics capabilities ky Doc ID 023520 Rev 2 17 87 General items UM1556 1 4 1 1 4 2 18 87 New features overview Improved diagnostics on analogue current sense devices Open load short to Vbat indication in off state Improved compatibility with higher variety of loads Optimized current limitation range Faster detection of overload and short to GND through Indication of power limitation Analogue stable indication by pulling the CS pin to Vsensen as for TSD Digital stable indication by pulling low the status pin as for TSD Open load in off state short to Vbat Now also featured on analo
29. as previously described in the case of monolithic devices see Section 6 2 1 Monolithic HSDs supplied from different supply lines Mix of monolithic and hybrid HSDs supplied from different supply lines Paralleling CS pins of monolithic and hybrid HSDs is possible however some precautions in schematics should be applied if the HSDs are supplied from different supply lines Direct connection of CS pins as shown in Figure 62 is not safe Doc ID 023520 Rev 2 ky UM1556 Paralleling of HSDs Figure 62 Direct connection of CS pins not recommended Mix of monolithic and hybrid HSD Vbatl Vbat2 A A Loss of Vbat2 100nF 50V 100nF 50V Isense GND GND GND GND GAPGMS00139 Direct connection of CS pins is not safe in following cases e Negative ISO pulse on Vbat2 e Loss of Vbat1 or Vbat2 e Loss of GND connection A negative voltage surge 1507637 2 pulse 1 on Vbat2 is directly coupled to the CS pin through the internal Vcc CS clamp structure If the negative voltage on the CS line is high enough to activate the Vcc CS clamp structure there may be an unlimited current flow through both CS pins This current can lead to malfunction or even failure of one or both of the HSDs Loss of either Vbat1 or Vbat2 leads to an incorrect current sense signal If Vbat2 is lost U2 logic part is supplied by U1 current sense signal through the internal Vcc CS clamp structure Therefore the voltage on CS bus drops resu
30. overheating during HSD thermal shutdown cycling as expected in theoretical calculation e Freewheeling diode protection circuitry 1N5401 The measurement was done at room temperature on VND5E025AK loaded with a blocked DC motor as specified in the beginning and with external freewheeling diode 1N5401 Doc ID 023520 Rev 2 63 87 Switching inductive loads UM1556 Figure 52 Demagnetization phase VND5E025AK DC motor blocked freewheeling diode 1N5401 ct H Tpemac 3bms vay a Measure P1 rise lv C1 P2 fall lw C1 P3 freq C1 P4 mean F3 P5 P amp mean F3 value _ 92 2 W status amp v 5 00 Vidiv 10 0 Vidiv Stop 3 60 V 10 000 V 20 000 V 0 mA offset 250 kS 25 MSisfEdge Negative GAPGMS00126 64 87 The measured demagnetization time of 3 2 ms is very close to the calculated value 3 37 ms Due to the measurement at room temperature the stall current was only 20 A versus 25 A specified at 40 C Figure 53 Repetitive demagnetization VND5E025AK TSD cycling DC motor 1N5401 i V OUT _ a Idiode c4 i ci Ppiove Average power dissipation on freewheeling diode Measure P1 rise lIv C1 P2 fall lv C1 P3freq C1 value 188 29783 Hz status amp 5 00 Vidiv 10 0 Vidiv 10 0 Aldiv 20 0 Widiv 5 000 V ofst 10 000 V mA offset 5 0
31. the novel 5 technology important improvements have been introduced to the analog current sense operation The block diagram of a MO 5 High Side Drive with analog current sense is reported in Figure 24 In line with the previous generations the current sense block has a double function e Current mirror of the load current in normal operation This delivers a current proportional to the load current according to a known ratio named K e Diagnostics flag in fault conditions This delivers a fixed voltage with a certain current capability in case of overtemperature conditions The current delivered by the current sense circuit can be easily converted to a voltage by means of an external sense resistor thus allowing continuous load monitoring and abnormal condition detection Figure 24 MO0 5 High Side Driver with analogue current sense block diagram Vec Signal Clamp e a Undervoltage Control amp Diagnostic Power Clamp i A IN DRIVER e Von Limitation Over Current temp Limitation cs CS DIS OUT la OVERLOAD PROTECTION LOGIC ACTIVE POWER LIMITATION L GND GAPGMS00101 2 2 Simplified principle of operation The simplified block diagram of the M0 5 analog current sen
32. 0 P4 mean F3 P5 3 2W P6 mean F3 5 00 ms div Stop 3 50 V 250 kS S OMSisfEdge Negativel GAPGMS00127 Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads The average power dissipation measured on the freewheeling diode is 3 2 W while the HSD thermal shutdown cycling frequency was 188 Hz These values are below theoretical calculations Real HSD cycling frequency is much lower than the frequency assumed in the calculation 500 Hz based on simulation with resistive load Conclusion The demagnetization energy is two times higher than the device is able to withstand therefore additional protection clamping is necessary Two different external protection circuits were analyzed Clamp OUT 25V Tout 2 Vout T G 8 e Transiland diode SMBJ16A or SMCJ18A 1N4002 The transil is not able to withstand the repetitive energy when the HSD is in a thermal cycling condition Therefore this protection can by used only if no PWM control is used and proper diagnostics is implemented to switch off the HSD in case of overload e Freewheeling diode 1N5401 and reverse battery protection circuitry with MOSFET With this external protection circuitry the repetitive energy capability requirement is also fulfilled Demag phase Starting conditions Clamp PMOS OUT 0V 1V Ta Tout 15V D 4 Dgnd d
33. 00 us with a more flat Vc Ipp characteristics SMCJ18A in 1 2 Ver IR min 10 1000 ps 8 20 us Gr Type max min max max max 10 4 SMCJ18A CA 1 18 20 0 1 29 2 53 39 3 254 9 2 1 Pulse test 15 50 ms 2 To calculate Vgg or Vc versus junction temperature use the following formulas 25 C 1 aT x 7 25 VCL Tj Vco_ 25 Ox 1 aT x Tj 25 60 87 VoL 23 V 25 A estimated from Vc Ipp diagram As seen in the datasheet the selected device is able to fulfill the 24 V 25 A clamping requirement together with a safe stand off voltage of 18 V no conduction at reverse battery condition It means that the HSD is fully protected and does not see any demagnetization energy In addition to single pulse energy considerations the repetitive energy capability also needs to be checked e Repetitive energy capability check HSD cycling Assuming that the HSD is in a thermal shutdown condition with autorestart frequency assumed to be 500 Hz and l lj gt 15 A One pulse energy according to Equation 17 Vor lg R gt L R lo Vou log Var 23 28 0 00073 06 15 23 E 0 62 E F 65 5mJ Demagnetization time check Equation 12 _ L VbEMAG lo P _ 0 00073 25 15 0 6 _ TDEMAG u T 06 l cores 0 4ms Average power dissipation on trans
34. 023520 Rev 2 21 87 General items UM1556 1 4 7 22 87 Table 5 Analogue driver truth table ON state Operation mode Input level Output level Current sense Normal operation Vbat lout K Short to Vbat Vbat lt lout K Open load Vbat OV Short to GND L VSENSEH PWM V Power limitation SENSEH Overload Vbat n gt nominal No power limitation Overtemperature L VSENSEH e Overtemperature overload and short to GND can be distinguished from an open load condition without the need of offstate diagnostics no switchable pull up resistor is required e Detailed diagnostics without external components is possible Indication of power limitation the advantages e The system reaction time on overload short circuit events depends on various aspects The most important one is the first link in the chain the diagnostics feedback of the smart power device Figure 23 System reaction time comparison Overload Event System Protection HSD turnoff Without Power Limitation indication t ms HSD turnoff With Power Limitation indication System Protection GAPGMS00100 e Indication of power limitation as diagnostics feedback allows almost instantaneous overload short circuit detection as soon as the deltaT exceeds 60 K Doc ID 023520 Rev 2 ky UM1556 Analogue current sense 2 Analogue current sense 2 1 Introduction With the introduction of
35. 1 VND5025AK with Rsgwsg selected to have Vgense 1 5 V lour Considering for sake of simplicity Ko 3 A 2790 typical value gt Isense 1 mA Assuming a typical Vsenge saturation of 7 5 V gt maximum Iggysg 5 mA to maintain linearity gt maximum lour 14 A In other words with the selected Rsense any load current greater than 14 A produces the same Vcense see Figure 26 Figure 26 VsENSE vs lout Vsense vs lout Vsense V O N Q O 0 5 10 15 20 25 30 lout A GAPGMS00103 On the other hand care must be taken to prevent the P channel MOSFET M1 from saturation causing the Isense to again be disproportional with lour This normally happens when the maximum current that M1 is able to supply is reached 11 mA typ This value is consistent with the current sense operating range and current limitation value Example 2 VND5025AK with Rsense selected in order to have 1 5 V lout 10A Considering for sake of simplicity 10 A 2760 typical value gt Isense 3 6 mA gt RsENSE 414 Q Assuming K to remain approx 2760 for lour gt 10 A the maximum load current which can be detected is ky Doc ID 023520 Rev 2 25 87 Analogue current sense UM1556 lout Isense max K 29A still compatible with the minimum l iH With the selected Rsense the maximum Vgense which can be developed to
36. 5 A estimated from Vc Ipp diagram Then we check the Vc Ipp parameters As seen from the Vc Ipp characteristics this transil does not fit with our 24 V 25 A requirement Nevertheless we can decide to use this device given that the HSD can also go in clamp to safely dissipate the remaining energy see Figure 49 Figure 49 Energy sharing between HSD and external clamping circuitry Vbat A Demagnetization 16V ext clamping active HSD clamping active Clamp EAT 41V Vclamp min lt aA TA OUT IN GND tisa 1 18 ZS N4002 24V Rgnd Dgnd 24 18 xz Laren GND GND GND The output voltage during the demagnetization phase is 25 V considering a worst case HSD Vciampmin 41 V Vgar 16 V Under these conditions the external clamping circuitry provides 18 A according to the transil characteristics at 24 V 1 V drop on the protection diode so the HSD is loaded by the remaining current 25 18 7 A Looking at the I L diagram we are clearly in the safe area In addition to single pulse energy considerations the repetitive energy capability also needs to be checked see Choice 2 Single pulse consideration Doc ID 023520 Rev 2 59 87 Switching inductive loads UM1556 Choice 2 Single pulse consideration In the second choice we select a more powerful transil from the SMCJ series ST devices 1500 W 10 10
37. AK 16 VN5016AJ VN5E016AH 2 21 5 25 VN5025AJ VND5025AK VN5E025AJ VND5E025AK 27 VNQ5027AK 70 87 Doc ID 023520 Rev 2 ky UM1556 High Side Driver selection for lamp loads Table 14 List of suggested bulb driver combinations 3 4 continued Bulb load Driver ron Single channel Dual channel Quad channel W mQ part part part VND5025AK 25 VN5025AJ DE c AK VN5E025AJ ds 27 VNQ5027AK VND5E050J AJ VNQ5E050K AK 50 VN5E050J AJ VND5E050K AK Q5E050K VND5025AK 25 VN5E025AJ VNQ5027AK 21 27 VND5050J AJ VNQ5050K AK 50 VND5050K AK VND5E050J AJ VNQ5E050K AK VN5E050J AJ VNDS5E050K AK Table 15 List of suggested bulb driver combinations 4 4 Bulb load Driver ron Single channel Dual channel Quad channel W mQ part part part 50 VN5050J AJ VND5050J AJ VNQ5050K AK VND5050K AK 10 VN5E050J AJ VND5E050J AJ VNQ5E050K AK VND5E050K AK 160 VN5E160S AS VND5E160J AJ VNQ5E160K AK 7 160 VN5160S VND5160J AJ VNQ5160K AK VN5E160S AS VND5E160J AJ VNQ5E160K AK 5 160 VN5160S VND5160J AJ VNQ5160K AK VN5E160S AS VND5E160J AJ VNQ5E160K AK Doc ID 023520 Rev 2 71 87 Paralleling of HSDs UM1556 6 6 1 6 1 1 Paralleling of HSDs Paralleling of CS_DIS current sense disable and IN input The following chapters describe the paralleling of CS_DIS and IN pins of HSDs taking into account device technology monolithic HSDs or hybrid HSDs and supply line confi
38. C which can be calculated as Hg 1 0 0039 40 20 2 Notevery relay datasheet specifies the coil inductance In this case it can be determined by measurement The inductance value is different with armature seated relay powered than when unseated relay not powered The inductance measurement should be done with relay powered armature seated because this better represents the application conditions The inductance of a typical 12 V automotive relay is in the range of 200 800 mH Step 1 Demagnetization voltage calculation using Equation 11 VpEMaG Vgar VoLANP 16 46 30V Step 2 Demagnetization time calculation using Equation 12 V ly R VpEMAgG lo J 0260 30 0 258 62 L TDEMAG 7 R lo MEAS 62 30 18ms Step 3 Calculation of energy dissipated in HSD using Equation 14 Vaar VpEMAG Vpemac 10 R Eysp sar Moemag P te Voewac os VDEMAG 16 30 30 0 258 62 25 0 260 62 0 258 30 log 299 228 82 9 9mJ Step 4 HSD datasheet analysis The maximum demagnetization energy is specified by I L diagram in the datasheet This diagram shows the maximum turn off current versus inductance for R 0 Q and Vpat 13 5 V see Figure 39 These conditions are different from conditions considered in our example 62 16 V and inductance 260 mH is not covered by the diagram Doc ID 023520 Rev 2 45 87 Switching inductive loads UM1556 Figure 39
39. EH Vsa t1 mM gt 1 Vsense 0 V condition explanation MO 5 only Under normal conditions the is a mirror of the HSD output current therefore just one sample gives us information about the HSD However we Should consider the status signal delay response time from the rising edge of the INPUT pin tpsENSE2H max 600 us see datasheet If the device is in a thermal shutdown condition the is pulled to Vgensen If Vsense 0 V we have to be careful because there are two possible states a OpenLoad b Hard short to GND the device is still not in thermal shutdown If a hard short to GND occurs the Vsenge first goes to 0 V the internal current mirror is not working because Vour is close to OV After the device reaches thermal shutdown the Vgenge is pulled to The time between SC to thermal shutdown depends on the package cooling area resistance ambient temperature etc Normally this time is in the range of 50 1000 ms See Figure 31 34 87 Doc ID 023520 Rev 2 UM1556 Analogue current sense 2 9 Figure 31 VND5012A current sense voltage behavior hard short to GND occurred 20 mQ thermal shutdown was reached 344 ms after short circuit to GND Short to GND Power Thermal Limitation shutdown ENSE wai eee 3 MOI 22 sl 20mV A V GAPGMS00108 Open load detection in off state external
40. IONAL SAFETY REQUIREMENTS B AERONAUTIC APPLICATIONS C AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS AND OR D AEROSPACE APPLICATIONS OR ENVIRONMENTS WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS PRODUCTS FORMALLY ESCC QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY Resale of ST products with provisions different from the statements and or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever any liability of ST ST and the ST logo are trademarks or registered trademarks of ST in various countries Information in this document supersedes and replaces all information previously supplied The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners 2013 STMicroelectronics All rights reserved STMicroelectronics group of companies Australia Belgium Brazil Canada China Czech Republic Finland France Germany Hong Kong India Israel Italy Japan Malaysia Malta Morocco
41. L 260 mH R 81Q 40 Inductive load HSD turn off phase 40 Inductive load turn off example VNQ5E050AK L 260 mH R 81Q 43 Maximum turn off current versus inductance VND5E160AJ datasheet 46 Maximum demagnetization energy VND5E160A 46 Demagnetization energy measurement VND5E160AJ relay 260 mH 47 External clamping transil and 52 Transil V A characteristic 53 Peak pulse power vs pulse time for transil 600 W 10 1000 us series 54 Equivalent pulses giving the same power dissipation 54 Maximum peak power as a function of initial temperature of the transil 54 Maximum turn off current versus inductance VN5E025AJ datasheet 57 Doc ID 023520 Rev 2 5 87 List of figures UM1556 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Figure 62 6 87 External clamping circuitry border conditions 58 Energy sharing between HSD and external clamping circuitry 59 Appropriate protection circuitry for VNBEO25A with DC motor 61 Demagnetizati
42. MO0 5 Soft short to GND 0 20 5 short to GND 20 MO 5Enhanced Soft short to GND 21 MO 5Enhanced Hard short to GND 21 System reaction time comparison 22 MO 5 High Side Driver with analogue current sense block diagram 23 M0 5 current sense simplified block diagram 24 VSENSE vs lout diosa eto ope OC alae A ata aL Bom TELE 25 VSENSE vs Vout lour LiMH TIT Ra eee ea RR T0707 Be a Ra ee 26 Current sense resistor _ 28 Switchable current sense resistor example 30 Vsense Measurement 2 ee 31 VND5012A current sense voltage behavior hard short to GND occurred 20 mQ thermal shutdown was reached 344 ms after short circuit to GND 35 Analogue HSD Circuit for open load detection in off state 36 Analogue HSD Open load detection in off state MO 5Enhanced 36 Digital HSD diagnostics timing 38 Inductive load HSD turn on phase 39 Inductive load turn on example VNQ5E050AK
43. Rend the Renp 71 W during reverse conditions higher price of the resistor Device turns off in case of positive ISO pulses Diode HSD GND Fixed voltage drop Resistive load only i Negative ISO pulse transfer to input Positive ISO pulse clamping i and diagnostics pin serial gt 50 V s D protection resistors necessary GND 14 87 Doc ID 023520 Rev 2 ky UM1556 General items Table 2 Reverse battery protection of monolithic HSDs only comparison continued Protection type monolithic HSD Resistor and diode HSD GND Ik D GND MOSFET HSD GND zp Vbat R GND Fixed voltage drop Positive ISO pulse clamping 50 V Any type of load Any type of load No voltage drop No ISO pulse transfer to input and diagnostics pin Negative ISO pulse transfer to input and diagnostics pin serial protection resistors necessary Higher cost more external components needed 1 2 2 Reverse battery protection of hybrid HSDs In contrast to monolithic devices all hybrid VIPower HSD do not need any external components to protect the internal logic in case of a reverse battery condition The protection is provided by internal structures see Reverse Battery Protection in the block diagram of Figure 10 In addition due to the fact that the output MOSFET turns on even in reverse battery mode thus providin
44. S_DIS pin as already described in case of monolithic devices see Figure 6 1 1 Monolithic HSDs supplied from different supply lines on page 72 In principle the same applies to the input pins the clamp structure is the same as on the CS_DIS pin Mix of monolithic and hybrid HSDs Paralleling of CS_DIS pins of monolithic and hybrid HSD is possible however some precautions in schematics must be applied The direct connection of CS_DIS pins as shown in Figure 58 is not safe even if we consider the same power supply for both devices Doc ID 023520 Rev 2 ky UM1556 Paralleling of HSDs Figure 58 Direct connection of CS_DIS pins not recommended Mix of monolithic and hybrid HSD 100nF 50V Vbat A Reverse battery condition or negative ISO pulse 100nF 50V GND GND GAPGMS00135 6 2 Direct connection of CS pins is not safe in the following cases single supply line considered e Reverse battery e Negative ISO pulse Due to the different concepts of reverse battery protection of hybrid and monolithic devices there is a way for unlimited current flow between both devices in case of reverse battery conditions The hybrid device has an integrated reverse battery protection in the Vcc line while the monolithic device needs an external diode resistor in series with the GND pin refer to Section 1 2 Reverse battery protection The different potential on each GND pin hybrid 0 V monolithic
45. TUS signal behavior and recommendations for diagnostics sampling for MO 5 in comparison with MO 5Enhanced Table 9 Digital HSD diagnostics MO 5 MO 5Enhanced Diagnostics Symbol Value Value VIN H L H L VsTAT L L lour lt lop see datasheet lout lt lo see datasheet Condition Vout gt VoL Typ 3 V Vout gt VoL Typ 3 V Without external pull up Without external pull up Open load without pull up VIN lout lt lot ViN lout lt lo Waveform ya 31 Ver tDOL on DOL on VIN H L H L VsTAT L L L L lour lt lop see datasheet lout lor see datasheet Condition Vout gt VoL Typ 3 V Vout gt VoL Typ 3 V Opeii load With external pull up With external pull up with Vis lout lt lot VIN lout lt lo 7 7 MENGE 1 Waveform Vstat__ tooL on Doc ID 023520 Rev 2 37 87 Digital status output UM1556 Table 9 Digital HSD diagnostics continued M0 5 M0 5Enhanced Diagnostics Symbol Value Value Vin H L H VsTAT H L H Active Power Limitation Condition Tj Typ 175 C Tj gt Trsp 175 C Thermal shutdown Thermal shutdown Overtemp Overload T gt Trsp Ti Fren VIN A ViN Waveform VSTAT VSTAT VIN H L VsTAT H L Condition lout gt lo see datasheet lout gt lo see datasheet Vout gt VoL Typ 3 V Vout gt VoL
46. Typ 3 V Short circuit to EE T k _ Jr JT wr Waveform V STAT tpot onj toSTKON We lt Figure 34 Digital HSD diagnostics timing overview w fo Vsrar I J OPEN LOAD no ext pull up I tpor on tror Vswr _ J OPEN LOAD ext pull up tsp u OVER TEMP M0 5 M0 5Enhanced STAT POWER LIMITATION M0 5Enhanced only Vsrar __ i SHORT to Vy DSTKON t tT ON state OPL OT OFF state GAPGMS00111 Q 38 87 Doc ID 023520 Rev 2 UM1556 Switching inductive loads 4 4 1 Switching inductive loads Switching inductive loads such as relays solenoids motors etc can generate transient voltages of many times the steady state value For example turning off a 12 volt relay coil can easily create a negative spike of several hundred volts The MO 5 MO 5E high side drivers are well designed to drive such loads in most cases without any external protection Nevertheless there are physical limits for each component that have to be respected in order to decide whether external protection is necessary or not An attractive feature of the MO 5 MO0 5E drivers is that a relatively high output voltage clamping leads to a fast demagnetization of the inductive load The purpose of this chapter is to provide a simple guide on how to check the conditions during demagnetization and how to select a proper HSD and the external clamping if
47. VBar VcLAMP 16 46 30V Step 2 Demagnetization time calculation using Equation 12 Le T 2000 8 L Torme ox ea 56 29 06 0 49ms Step 3 Calculation of energy dissipated in HSD using Equation 14 VpaT VpEMAG Voemaa o R a Rta vorn eo mh 16 90 06 25 30 log 0 62 30 25 0 6 _ 127 061 264 5mJ Step 4 HSD datasheet analysis Looking at the I L diagram in the datasheet the maximum turn off current specified for 0 73 mH inductance is 16 A single pulse 13 5 V RI 0 The worst case current in Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads our example a motor stall condition 25 A 16 V 40 C is much higher For better comparison of the calculated energy 264 5 mJ with the device limits it is useful to translate the current values at 0 73 mH Imax 16 Imax B 12 Imax c 11 A to energy values using Equation 15 i i 1 Veatt Ypemac _ 13 5 32 5 Euay a Lb MAX L 0 00073 162 2 79 132mJ a VDEMAGI 5 2 5 EMAX B 74 mJ EMAX C 62 5 mJ single pulse Tis 150 C repetitive pulse 100 C repetitive pulse Tjstart 125 G Figure 47 Maximum turn off current versus inductance VN5E025AJ datasheet 100 TI T w rp s I DC motor A Tistart 150 C single pulse Eusp 264 5mJ B Tistart 100 C repetitive pulse Vear 16V
48. W gt Package 2512 D Renn 2200 Power rating 70 C of 2512 is 1 W Note The device with only a resistor at the GND terminal doesn t clamp ISO pulses on the supply line Positive ISO pulses gt 50 V and negative ISO pulses pass the GND and logic terminals Therefore a serial protection resistor should be used between the uC and HSD Resistor values should be calculated according to the maximum injected current to the I O pin of the microcontroller used Doc ID 023520 Rev 2 11 87 General items UM1556 12 87 Reverse battery protection using diode plus resistor Figure 6 Voltage levels during reverse battery using diode resistor protection network Microcontroller OUT GND GND GND GND GAPGMS00092 A diode at the GND terminal prevents a short circuit through the internal substrate diode of the HSD during reverse mode A resistor 1 package 0805 should be inserted in parallel to the diode if the device drives an inductive load to clean up negative voltage peaks at GND terminal in case of inductive load switch off This ground network can be safely shared amongst several different HSDs The presence of the ground networkalso produces a shift 600 mV in the input threshold and in the status output values This shift does not vary if more than one HSD share the same diode resistor A diode at the GND terminal allows the HSD to clamp positive ISO pulses above 50 V clamping voltage of the
49. battery protection 1 2 1 Reverse battery protection of monolithic HSDs The reverse battery protection is inserted to the GND terminal of the driver There are three possible solutions resistor only resistor plus diode and MOSFET There is a relatively low current in the GND path and therefore no high power components are needed However this protection circuit still must be able to handle the clamped ISO pulse current as well as the ISO pulse voltage We also have to consider the fact that this simple ground circuitry doesn t provide any protection to the connected load If a reverse battery condition occurs the load is supplied in reverse polarity through internal body diode of the HSD and the power dissipation on the HSD can become critical depending on connected load and thermal connection of the HSD With a typical voltage drop on the internal body diode of about 0 7 V the resulting power dissipation 0 7 W Reverse battery protection using resistor Figure 4 Voltage levels during reverse battery resistor protection Microcontroller v qq OUT GND GND GND GND GAPGMS00090 A resistor Rgng in the GND line prevents a short circuit through the internal substrate diode of the HSD during a reverse battery condition The minimum resistor value is limited by the DC reverse ground pin current of the HSD The maximum resistor value is limited by the drop voltage caused by the on state supply
50. case of a thermal shutdown M0 5 MO 5Enhanced or a Power Limitation MO 5Enhanced the Csgwsg pin is switched to a voltage source Vsensen VsENsEH 9 V typ IsENSEHmax 8 for as long as the device remains in the thermal shutdown Power Limitation mode The voltage from the current sense resistor is usually connected through a 10 protection resistor to the ADC input of the uC For the Vsensen level the voltage is limited by the uC internal ESD protection 5 6 V and the ADC shows maximum value OxFF in case of 8 bit resolution The capacitor CF is used to improve the accuracy of the ADC This capacitor plus a 10 kQ serial resistor function as a low pass filter 210 kHz for potential HF noise on the Csgysg line especially if there is a long wire route to the microcontroller Figure 28 Current sense resistor GND GND GND GND GAPGMS00105 The Rgense_value definition example Consider the VN5016AJ 16 with a nominal load current ly 5A Vsense 2 typ K 5000 datasheet VSENSE Rsense OUT 5000 2 2 1 023520 2 ky UM1556 Analogue current sense 2 7 2 7 1 2 7 2 Diagnostics with different load configurations Diagnostics with paralleled loads AHSD with current sensing allows the detection of individual bulb failures when in a parallel arrangement However if we consider the bulb wattage spread the HSD K factor tolerance variati
51. cing of the contacts when inductive loads are driven Even a standard high frequency capacitor typ value 100 nF across the local battery and ground is not enough to smoothen these pulses The possible risk at application level is an early failure of the HSD with a following resistive short between Vcc and OUT In order to avoid this add a free wheeling diode across the inductive load terminals see below diagram in order to minimize the effects of the relay bouncing Some suggestions above those already mentioned to help render the HSDs less sensitive when used with relays on the same board are a the usage of four layer PCBs where the inner layers are used as low resistance shields one should be connected to module GND the other to the battery connector b the CS pin circuitry as recommended in the datasheet c the use of separate connectors to supply the HSDs GND GND GHD GHD GND GND GND GND ky Doc ID 023520 Rev 2 85 87 Revision history UM1556 9 86 87 Revision history Table 16 Document revision history Date Revision Changes 01 Aug 2012 1 Initial release 18 Sep 2013 2 Updated disclaimer Doc ID 023520 Rev 2 UM1556 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document
52. circuitry for analogue M0 5 HSD The following schematic shows a simple way to perform an open load diagnostics in off state for analogue HSDs In case of a missing load in off state the Rsense resistor is supplied through R5 R6 and D1 Then the voltage increase on Rgenge is about 2 V divider R5 R6 Rsense which be recognized by a uC as open load in off state In on state conditions or if current sense disable signal is high the influence of R5 R6 is suppressed by the conducting transistor T1 anode of D1 is shorted to GND Doc ID 023520 Rev 2 35 87 Analogue current sense UM1556 2 10 36 87 Figure 32 Analogue HSD Circuit for open load detection in off state 5V Vbat Vbat_switched A A cj 100nF 50V U3 TELL Losi as CS DIS 5x Lj us cs C3 10nF 100V GND GND GND GND GND GAPGMS00109 Open Load detection in off state M0 5Enhanced HSD Figure 33 Analogue HSD Open load detection in off state M0 5Enhanced Vbat Vbat_switched A A 5V A U3 Microcontroller Rsense C3 1k 10nF 100V Dgnd GND GND GND GND GND GAPGMS00110 4 Doc ID 023520 Rev 2 UM1556 Digital status output 3 Digital status output 3 1 Digital HSD diagnostics The diagnostics of digital MO 5 devices is based on a logical level on the status pin The table below summarizes all failure conditions the STA
53. current Ia of the HSD The voltage drop across this resistor elevates the minimum input High threshold and normally should not exceed 1 V depending on microcontroller I O levels Equation 1 R lt GND S on max Equation 2 V BAT RaNp 7 GND reverse max Doc ID 023520 Rev 2 9 87 General items UM1556 10 87 Equation 3 _ This resistor be shared amongst several different HSDs In this case Equation 1 IS onymax becomes the sum of the maximum on state currents of the different devices When the microprocessor ground is not common with the device ground the Renp produces a Shift Isionymax x Ranp in the input thresholds and in case of a digital HSD also the status output values This shift varies depending on how many devices are ON in the case of several HSDs sharing the same Renp This can lead to a very low value of Rayp needed to comply with Equation 1 and Equation 2 not being fulfilled To overcome this problem ST suggests the use of another solution with diode or MOSFET Resistor calculation example reverse battery requirement 14 V 260 s 1 Define maximum acceptable safe ground shift level Venp Figure 5 Logical levels check uC HSD ST72F561 VN5050 GND GAPGMS00091 Table 1 Datasheet values Symbol Parameter Value VN5050J Vin Input high side voltage min 2 1V li High level input current max
54. d such failures add a 10 KQ resistor in series to each CS_DIS pin see Figure 56 In principle the same applies to the input pins the clamp structure is the same as on the CS_DIS pin Figure 56 Proper connection of CS_DIS pins Vbat1 HSO pulse Vbat2 loomrisov GAPGMS00133 Hybrid HSDs supplied from different supply lines Paralleling of CS_DIS pins of hybrid HSDs is possible however some precautions in schematic should be applied if the HSDs are supplied from different supply lines Direct connection of CS_DIS pins as shown in Figure 57 is not safe Doc ID 023520 Rev 2 73 87 Paralleling of HSDs UM1556 Figure 57 Direct connection of CS_DIS pins not recommended Hybrid HSD Vbatl Vbat2 Positive ISO pulse gt Veramp Vcsct T 100nF 50V 100nF 50V GAPGMS00134 74 87 Direct connection of CS pins is not safe in the following cases e Loss of GND connection If the GND connection of one device is lost positive as well as negative ISO pulses on the associated supply line are no longer clamped considering no other devices are connected to this supply line If the transient voltage is large enough to activate involved clamp structures there may be unlimited current flow between both supply lines through the CS_DIS pins This current can lead to malfunction or even failure of one or both of the HSDs In order to avoid such failures add a 10 KQ resistor in series to each C
55. e maximum current capability of the HSD Equation 31 104 li IMHmax And therefore Equation 32 esp Resp LimHmax _ gt G ESD VbEMAG Example 1 Contact discharge 8 kV 330 pF 2 kW li max 14 A VNx5E160 HSD battery not supplied Vcc 0 V according to Equation 30 gt 46 nF according to Equation 32 gt 143 nF gt Cext gt 46 nF fulfils both requirements Example 2 Contact discharge 6 kV 150 pF 330 Q battery not supplied Vcc 0 V according to Equation 30 Cgyr gt 9 nF according to Equation 32 Cgxr gt 4 4 nF Ogxr1 gt 9 nF fulfils both requirements Positive ESD pulses without external protection ESD discharge resistance Body Diode of Power MOSEFT ESD discharge capacitor A positive ESD pulse on the output is transferred through the body diode of the power MOSFET to the Vcc pin of the HSD stressing the Vcc GND clamping structure The ESD ratings of the Vcc GND clamping structure is the same for the output clamping structure Clamping structure in HSD Doc ID 023520 Rev 2 83 87 ESD protection UM1556 7 2 84 87 Therefore the same considerations and calculations apply for negative ESD pulses on the output Positive ESD pulses with external protection ESD discharge resistance Body Diode of Power V MOSEFT Vcc H ESD discharge capacitor
56. eads to an incorrect current sense signal If Vbat2 is lost U2 and other components connected to Vbat2 is supplied by U1 current sense signal through the internal Vcc CS clamp structure Therefore the voltage on CS bus drops to almost OV resulting in an invalid Vsense reading Doc ID 023520 Rev 2 ky UM1556 Paralleling of HSDs 6 2 2 In order to protect the devices during ISO pulses and to ensure a valid current sense signal we can add a diode in series to each CS pin as shown in the following schematics In order to suppress the rectification of noise injected to the sense line add a ceramic filter capacitor between each CS pin and ground However the voltage drop on diodes in series with the CS pin can have an influence on the dynamic range of current sense temperature and current sense accuracy Figure 60 Safe solution for paralleling CS pins Vbatl Vbat2 A A 100nF 50V 100nF 50V 100 470pF GND Rgnd Ik Dgnd Rsense GND GND Hybrid HSDs supplied from different supply lines Paralleling CS pins of hybrid HSDs is possible however some precautions in schematics should be applied if the HSDs are supplied from different supply lines Direct connection of CS pins as shown in the next picture is not safe Doc ID 023520 Rev 2 77 87 Paralleling of HSDs UM1556 6 2 3 78 87 Figure 61 Direct connection of CS pins not recommended Hybrid HSD
57. ecified only at the maximum peak power limit of the device To determine the voltage at a given current level apply a linear approximation using Vgp lg and Vc Ipp data or estimate the value using Vc Ipp diagram in the datasheet The transil must not conduct during a reverse battery condition Assuming 16 V a 0 5 V drop on the HSD channel and a 0 5 V drop on the protection diode we have 15 V across the transil We can find the parameter Vg Stand off voltage in the transil specification Van is the maximum operation voltage with low leakage current valid in the whole temperature range gt 1 5V VCL lt 24 V at given lo e Single pulse energy capability The maximum nonrepetitive transient power and current capability of transils is specified mostly for 10 1000 us exponential pulse at 25 C A real application condition is usually different In our case the pulse length is given by the demagnetization time while the current waveform is close to the sawtooth shape depending on L R ratio of the load To check if the transil can safely operate under the desired conditions we can use the translation diagrams in Figure 44 Figure 45 and Figure 46 Doc ID 023520 Rev 2 53 87 Switching inductive loads UM1556 Figure 44 Peak pulse power vs pulse time for transil 600 W 10 1000 ys series
58. ense device is used different sense resistors have to be used in order to have the current sense band in the appropriate range matching the different load currents An example of a current sense resistor switching circuit can be seen in the Figure 29 The measured scale can be extended by Rsgwsg switched in parallel to Rgense2 by MOSFET Q1 Doc ID 023520 Rev 2 29 87 Analogue current sense UM1556 Figure 29 Switchable current sense resistor example 5V Vbat A A 100nF 50V U2 Microcontroller 21W LED OUT CLUSTER 10nF 100V GND GND GND GND GND GND GND GND GAPGMS00106 2 7 3 K factor calibration method In order to reduce the Vsense spread it is possible to reduce the K spread and eliminate the Rsense Variation by adding a simple test calibration test at the end of the module production line How the calibration works To calibrate on a specific device soldered in a module signifies measuring the K ratio ata given output current by a Vsense reading Since the relation Isense x K is known itis straightforward to calculate the K ratio However even if the K ratio measured at a single point eliminates the parametric spread it doesn t eliminate the Vsgysg variation due to the variation produced by the output current variation This variation can be eliminated given the following considerations Table 7 and Figure 30 show measurement in a random VND5E025AK wi
59. g the same low ohmic path as in regular operating conditions no additional power dissipation has to be considered Furthermore if for example a diode is connected to the GND of a hybrid HSD the output MOSFET is unable to turn on and thus the unique feature of the driver is disabled see Figure 11 Doc ID 023520 Rev 2 15 87 General items UM1556 Figure 10 Hybrid HSD reverse battery protection with self switch on of the MOSFET 13V OV U3 10nF 100V GND GND GND GND GND GND GND GAPGMS00096 Figure 11 Example Self switch on of MOSFET eliminated by Dgnd 13V OV 100nF 50V Ds 790mV U3 i Microcontroller qq body Diode MOSFET switched OFF 10nF 100V GND GND GND GND GND GND GND GAPGMS00097 1 3 Microcontroller protection If ISO pulses or reverse battery conditions appear the HSD control pins are pulled to dangerous voltage levels due to the internal HSD structure and ground protection network see Section 1 2 Reverse battery protection for further details z 16 87 Doc ID 023520 Rev 2 UM1556 General items Figure 12 ISO pulse transfer to I O pin GAPGMS00098 Therefore each microcontroller I O pin connected HSD must be protected by a serial resistor to limit the injected current The value of must be high enough to ensure that injected current is always below the latch up limit of the microcontroller I O
60. gue MO 5Enhanced high side drivers already implemented for digital high side drivers Open load detection in off state through external pull up resistor Differentiation between open load and short to Vbat by disconnecting the optional pull up resistor Figure 13 Open load short to Vcc condition Vcc line Vpu Logic Driver GAPGMS00099 Doc ID 023520 Rev 2 ky UM1556 General items Figure 14 Open load short to Vcc condition Vin VSENSE Pull up connected VsENsEH Open load j Vsense 0 Pull up H disconnected V SENSE Short to Vec VSENSEH GAPGCFTO00597 Table 3 CS pin levels in off state Pull up CS Yes VsenseH Open load No 0 Yes VsenseH Short to Vcc No VsenseH Yes 0 Nominal No 0 1 4 3 Indication of power limitation The principle e Diagnostics reacts as soon as power limitation is reached without waiting for thermal shut down in digital as well as in analogue HSDs e Noambiguity of diagnostics between open load and overload e Fastand secure detection of short circuit overload also for intermittent loads for example turn indicator lamps or loads driven with PWM e Intermittent short circuit detection covered as well 1 4 4 Indication of power limitation example for analogue driver ky Doc ID 023520 Rev 2 19 87 General items UM1556 Figure 15 M0 5 Soft short to GND Figure 16 M0 5
61. guration either the same or separate supply lines for each HSD Direct connection of CS_DIS or IN pins is generally allowed with devices designed with the same technology monolithic or hybrid supplied from one supply line In all other cases like the combination of monolithic with hybrid technology or different supply lines or both we should use additional components to ensure safe operation under conditions in automotive environments ISO pulses reverse battery The clamp structure on the CS DIS pin is the same as on the IN pin therefore all the explanations related to the paralleling of the CS DIS pins are also applicable to paralleling of IN pins Monolithic HSDs supplied from different supply lines Paralleling CS DIS pins of monolithic HSDs is possible however some precautions in schematics should be applied if the HSDs are supplied from different supply lines In this case the direct connection of CS DIS pins as shown in Figure 55 is not safe Figure 55 Direct connection of CS DIS pins not recommended Monolithic HSD 72 87 Vbati HSO pulse Vbat2 T Negative ISO pulse lt Vbat2 Vcrawp Vcscr 100mF 50V v Ul U2 OND es Het mre sellos a p 1a E e Roens Ta s re Dend T uC LO GND GND GND GND GND GND GAPGMS00132 Direct connection of CS_DIS pins is not safe in following cases e Negative voltage surge on either
62. hout additional protection The worst case demagnetization energy is clearly below the device limit 4 4 External clamping selection The main function of external clamping circuitry is to clamp the demagnetization voltage and dissipate the demagnetization energy in order to protect the HSD It can be used as a cost ky Doc ID 023520 Rev 2 47 87 Switching inductive loads UM1556 4 4 1 48 87 effective alternative in case the demagnetization energy exceeds the energy capability of a given HSD A typical example is driving DC motors high currents in combination with high inductance During the selection of a suitable HSD for such an application we usually end up in the situation that a given HSD fits perfectly in terms of current profile but the worst case demagnetization energy is too high turn off from stall condition at 16 V 40 C Rather than selecting a larger HSD the use of an external clamp can be the more economical choice External clamping circuitry requirements summary e Proper negative output voltage clamping to protect the HSD e Noconduction at Normal operation 0 16 V Reverse battery condition 16 V 260 s Jump start 27 V 60 s dump 36 V 400 ms e Proper energy capability Single demagnetization pulse Repetitive demagnetization pulse Clamping circuitry examples 1 Transil and diode protection circuitry in parallel with the load GND GND GND
63. ibution on the power surface can cause the presence of a hot spot causing the device failure with a single shot 2 Asin normal operation the life time of the device is affected by the fast thermal variation as described by the Coffin Manson law Repetitive demagnetization energy causing temperature variations above 60 K causes a shorter life time These considerations lead to two simple design rules 1 The energy has to be below the energy the device can withstand at a given inductance 2 Incase of a repetitive pulse the average temperature variation of the device should not exceed 60 K at turn off To fulfill these rules the designer has to calculate the energy dissipated in the HSD at turn off and then compare this number with the datasheet values as shown in the following examples Example of VND5E160AJ driving relays The purpose of this example is to evaluate if a VNDB5E160AJ device can safely drive a relay under following conditions Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads Battery voltage Vgat 16 V HSD VND5E160AJ Clamping voltage VcLAMP 46 V typical for M0 5 M0 5E Relay NVF4 4C Z60a Resistance R 62 2 40 C Inductance coil not powered L 260 mH Load current before turn off event lo 258 mA 1 The relay datasheet usually specifies a coil resistance at 20 C For the worst case evaluation we should consider the resistance at 40
64. il during HSD cycling Equation 16 Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads Pava f E 500 0 0655 32 8 W The calculated average power dissipation of 32 8 W is very high clearly above the capability of standard transil diodes Therefore this protection can be used only if no PWM control is used and proper diagnostics is implemented to switch off the HSD in case of overload Step 5 continued External clamping selection freewheeling diode The following evaluation is conducted on circuitry with a freewheeling diode as shown in Figure 50 In this case the average power dissipation on the freewheeling diode is not so high The demagnetization voltage is about 1 V therefore most of the energy stored in the load inductance is dissipated in the load resistance 0 6 2 Relatively slow demagnetization does not cause any problems when driving motors Figure 50 Appropriate protection circuitry for VN5E025A with DC motor Vbat Demag phase Starting conditions PMOS GND GND GND GND Demagnetization time Equation 12 Assuming 1 V news F _ 0 00073 1 25 05 L T oo 3 37ms DEMAG VpEMAG 0 6 1 The freewheeling diode selection e Reverse voltage gt 52 V Must not conduct during positive voltage on the output maximum possible output voltage is limited by 92 V e Peak forward current gt 25 A
65. ing the reverse battery condition at 16 V Veatreverse V HSDdrop VDdrop 16 V 0 5 V 0 5 V 15 V e Clamping voltage 24 V 25A To be sure that the HSD clamp is not activated VuspciampMin VBAT V Darop 41 V 16 V 1 V 24 V e Energy capability requirement single pulse Peak power 600 W considering Vc 24 V gt 24 V 25A 600 W Pulse duration 0 49 ms considering Vc 24 V Pulse waveform sawtooth demag current considered Equivalent exponential pulse duration 0 175 ms 0 49ms 1 4 0 5 0 175ms see Figure 45 Choice 1 Single pulse consideration According to required energy capability 600 W 0 175 ms we can find a suitable transil in the SMBJ series ST devices 600 W 10 1000 us Maximum peak power of these devices is 825 W 0 175 ms considering 105 C initial temperature see Figure 44 and Figure 46 Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads The first device closest to the reverse battery requirement stand off voltage Vpn gt 15 V is SMBJ16A Inu VRM Vgg IR min is EC max m ae HA V mA V A V A 10 4 C SMBJ16A CA 1 16 17 8 1 26 23 1 34 4 116 8 8 1 Pulse test 15 50 ms 2 To calculate Vgg or Vc versus junction temperature use the following formulas VBR Tj VgR 25 C x 1 aT x Tj 25 VCLGTj Vc 25 Cx 1 aT x T 25 24 V 18 A estimated from Vc Ipp diagram 27 V 2
66. itive turn on off cycles the HSD usually goes in thermal cycling when the motor is blocked so there are a lot of demagnetization cycles in a short time Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads External clamping circuitry examples Table 10 External clamping circuitry 1 Transil and diode in parallel with the load Vbat Vout GND External clamping circuitry examples 1 2 Fast demagnetization The peak voltage across the HSD channel depends also on maximum Vgar should be considered 2 Transil in parallel with the HSD Vbat A E Clamp ty a E a OUT E out GND L Vout Rgnd Dgnd GND GND Fast demagnetization Direct parallel protection of the HSD independent from Vpar Load dump pulse The transil with Ve lt 41 V is starting to conduct already at 30 V transil can be damaged during the load dump pulse Higher peak power dissipation on transil in comparison with circuitry 1 contribution of power supply 3 Freewheeling diode and reverse battery diode Vbat GND GND GND q Low cost Load is reverse battery protected Doc ID 023520 Rev 2 Only for small loads voltage drop and power dissipation on reverse battery protection diode Dr Slow demagnetization 51 87 Switching inductive loads UM1556 Table 11
67. l resistance between the junction and ambient Pavc average power dissipation Transil selection summary 1 Determine the length of equivalent exponential pulse TpEMAG 1 4 see Figure 45 considering sawtooth demagnetization current 2 Determine maximum peak power Pp for Tp using Figure 44 3 Correct Pp value according to worst case T using Figure 46 4 Check if corrected Tp 0 5 5 Check Payg and Ty in repetitive operation Equation 16 Equation 18 Doc ID 023520 Rev 2 55 87 Switching inductive loads UM1556 4 4 3 56 87 Diode selection e Reverse voltage gt 52 V Must not conduct during positive voltage on the HSD output maximum possible output voltage is limited by VuspclampMax 52 V e Peak forward current gt lo 9 TpgMAG 10 load current at switch off event Toemac demagnetization time Examples of VN5E025AJ for DC motor driving with external clamp The purpose of this example is to evaluate if a VN5E025AJ can safely drive a specific DC motor in terms of demagnetization energy and to determine a suitable external clamping circuitry if needed Battery voltage Vpgar 16 V HSD VN5E025AJ Clamping voltage Vcr AMP 46 V typical for 5 0 5 DC Motor Nominal current 1 5 A Resistance R 0 600 40 L 0 73 mH Inductance lo 25 40 16V Stall current Step 1 Demagnetization voltage calculation using Equation 11 VpEMaG
68. lting in an inaccurate Vsense reading If the GND connection of one device is lost positive as well as negative ISO pulses on the associated supply line are no longer clamped considering no other devices connected to this supply line If the transient voltage is high enough to activate the involved clamp structures there can be an unlimited current flow between both supply lines through the CS pins This current can lead to malfunction or even failure of one or both of the HSDs In order to ensure a valid current sense signal and to protect devices in all previously described cases we can add a diode in series to each CS pin as previously described in the case of monolithic devices see previous Section 6 2 1 Monolithic HSDs supplied from different supply lines ky Doc ID 023520 Rev 2 79 87 ESD protection UM1556 7 7 1 80 87 ESD protection ESD protection of HSD calculations The ESD robustness of a typical M0 5 HSD is rated at 5000 V on the output as well as Vcc pin according to the Human Body Model 100 pF 1 5 This applies to positive as well as negative ESD pulses For any ESD pulse beyond these values external protection is required Calculation of the energy capability of the HSD output without external protection negative ESD pulse ESD discharge resistance Clamping structure in HSD ERES VI 1 The energy content of the ESD pulse is Equatio
69. lue monotonic function of the lour as long as the maximum Isense 1 example or the current sense saturation 2 9 example are reached i e there s no chance of having the same Isenge for different lout within the given range The current sense may still work above the current limited region depending on the Voyr In this latter case however the intervention of protection mechanisms such as power limitation and saturation of the circuit depending the Rgense choice might cause the information provided by the current sense to not be processable Finally the CS switch off in case of a hard short circuit renders this latter condition indistinguishable from an open load triggered switch off Overtemperature indication channel ON CS DIS low In case of overtemperature the fault is indicated by the CS pin which is switched to a current limited voltage souce Indeed with reference to Figure 25 whenever an overtemperature condition is reached the branch circuit on the left side is activated The P channel MOSFET 2 is controlled in such a way as to develop 9 V typ Vsenseu the datasheet across the external sense resistor In any case the current sourced by the CS in this condition is limited to 8 mA typ Isense in the datasheet Example 4 VND5025AK and minimum sense resistance for vsENsEHr gt 5 V Considering typical ISENSEH 8 mA gt RSENSE_MIN 6250 Current sense ESD and spikes protection An additional im
70. maintain linearity is approx 4 3 V However the current sense operation for load current approaching the current limitation is neither guaranteed nor predictable Indeed because of the intervention of the current limiter the output voltage can drop significantly up to approximately 0 V in the extreme case of a hard short circuit As the whole circuit is referred to Vor ambiguous and unreliable current values can derive from the CS under such conditions In order to bring the CS into a well defined state a dedicated circuit section shuts down the current sense circuitry when Vour drops below a certain threshold 6 V typ see Figure 27 Figure 27 Vsense VS Vout lour li in VOUT vs VSENSE IOUT ILIMH oM 8 x VSENSE V 0 2 4 6 8 10 12 VOUT V GAPGMS00104 Once again this value is consistent with the current sense operating range and current limitation value Example 3 VND5025AK At the edge of current limitation lout 29 A the maximum drop on the output MOSFET is Vos Ros max 1 49 V Therefore at Vcc 8 V Vour is still sufficient to ensure correct CS function up to the current limited region 26 87 Doc ID 023520 Rev 2 ky UM1556 Analogue current sense 2 4 2 5 In conclusion in normal operation the current sense works properly within the described border conditions For a given device the Isense is a single va
71. n 19 1 2 VEps 5 Cesp V ESD The energy dissipated by the resistance is Equation 20 1 2 Wr 5 Cesp Vesp VpEMAG The energy dissipated by the HSD is Equation 21 Wusp esp VpEMAG Volamp CESD The maximum ESD pulse energy capability of the HSD can be calculated using Equation 21 and the data sheet parameters typical example Doc ID 023520 Rev 2 ky UM1556 ESD protection Calculation of external protection negative ESD pulse When the ESD pulse amplitude or the ESD capacitance is increased or the discharging resistance is decreased the HSD needs external protection because the energy discharged in the HSD exceeds the limit calculated in Equation 21 If we add a ceramic capacitor on the output the ESD pulse initially only charges the capacitor without impacting the HSD until the voltage reaches the HSD active clamping voltage Then the voltage stays constant without further impact on the capacitor and excessive energy is absorbed by the ESD discharge resistance and by the HSD ESD discharge resistance ESD discharge cap ESD capacitor on HSD pu pd output ESD discharge resistance Clamping structure in HSD wl If in the first step we neglect the HSD the final voltage becomes Equation 22 Cesp J T T Final ESD Cesp with Vesp 8 KV Cesp 330 pF and Frinaj 50 V should be gt 53 nF Si
72. nce the HSD can absorb some ESD energy on its own the external capacitor can actually be smaller The time t4 defines the point in time when the external capacitor reaches the demagnetisation voltage of the HSD and does not charge further The time constant for discharging the ESD capacitor is Equation 23 ET C CExT PEsD VESD 3 with CExT gt gt gt t Resp Cesp Doc ID 023520 Rev 2 81 87 ESD protection UM1556 Equation 24 ESD I t Resp Equation 25 a zt Vesp Veinal e d Equation 26 Yon Vrinar e7 Equation 27 V t oo Final The residual voltage at the ESD capacitor when the external capacitor is charged to the HSD clamping voltage becomes Equation 28 VEsp VpENAG r Therefore the energy absorbed by the HSD becomes Equation 29 ExT V C Cesp clamp ESD Wusp eso Voeuac 1 Once we know the maximum ESD energy capability of the HSD calculated with Equation 21 we can calculate the necessary external capacitor Equation 30 VESD VDEMAG WuspMAx C gt ESD VDEMAG SD VpEMAG Velamp 82 87 Doc ID 023520 Rev 2 ky UM1556 ESD protection Of course the external capacitor needs a voltage capability larger than the maximum clamping voltage of the HSD In addition it must be ensured that the ESD discharge current cannot exceed th
73. necessary according to the given load Turn on phase behaviour Figure 35 Inductive load HSD turn on phase GAPGMS00112 When an HSD turns on an inductive load the current increases with a time constant given by L R values so the nominal load current is not reached immediately This fact should be considered in diagnostics software i e to avoid false open load detection Doc ID 023520 Rev 2 39 87 Switching inductive loads UM1556 Figure 36 Inductive load turn on example VNQ5E050AK L 260 mH R 81 Q Measure P1 freq C1 2 1 P3 duty C1 P4fall C2 P5 P6 vals a a a Gf fe 10 0 Vidiv 10 0 50 0 mA div 5 00 msidivi Stop 11 0 00 V offset 10 00 V ofst 150 00 ma 100 5 20MS sfEdge Positive GAPGMS00113 4 2 Turn off phase behavior Figure 37 Inductive load HSD turn off phase Vin qoo t Vbat 7 Egar gt t VcLAMP Eusp Egar Eroan L Ero E Er L qp Vout R R V 0 Sy gt t GND GND AN N LN V nema G x i ce PE gt Tpemac T GAPGMS00114 The HSD turn off phase with inductive load is explained in Figure 37 The inductance reverses the output voltage in order to be able to continue driving the current in the same 40 87 Doc ID 023520 Rev 2 ky UM1556 Switching inductive loads 4 2 1 direction This voltage so called demagnetization voltage is limited to the
74. ogue driver truth table ON state Table 6 Paralleling bulbs Table 7 VsEguse Table 8 Analogue HSD diagnostics Table 9 Digital HSD diagnostics Table 10 External clamping circuitry examples 1 2 Table 11 External clamping circuitry examples 2 2 Table 12 List of suggested bulb driver combinations 1 4 Table 13 List of suggested bulb driver combinations 2 4 Table 14 List of suggested bulb driver combinations 3 4 Table 15 List of suggested bulb driver combinations 4 4 Table 16 Document revision history 4 87 Doc ID 023520 Rev 2 UM1556 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46
75. on energy measurement VND5E025AK Motor SMBJ16A and 1N4002 63 Demagnetization phase VND5E025AK DC motor blocked freewheeling diode 1N5401 punendgu mI E MEI LM LE uL LUN EPUM RE NEN 64 Repetitive demagnetization VND5E025AK TSD cycling DC motor 1N5401 64 Principle of the setup used for the 5 lt 66 Direct connection of CS DIS pins not recommended Monolithic HSD 72 Proper connection of 5_ 5 5 73 Direct connection of CS DIS pins not recommended Hybrid HSD 74 Direct connection of CS DIS pins not recommended Mix of monolithic and hybrid HSD 75 Direct connection of CS pins not recommended Monolithic HSD 76 Safe solution for paralleling CS lt 77 Direct connection of CS pins not recommended HybridHSD 78 Direct connection of CS pins not recommended Mix of monolithic and hybrid HSD 79 Doc ID 023520 Rev 2 ky General items UM1556 1 General items 1 1 Application schematic monolithic digital monolithic and hybrid analogue HSD Figure 1 Monolithic digital HSD application schematic Vbat Vbat_switched 5V 5V C5 100nF U4 1oone sov Microcontroller vqq
76. ons of bulb currents vs and ADC resolution it is clear that accurate failure determination can be difficult in some cases For example if there is a largeand small bulb on the output the detection limit for the lowest power bulb is lost in the tolerances In order to achieve better current sense accuracy one or both of the strategies listed below can be adopted 1 Current sense calibration K factor measurement of each HSD 2 Vegar measurement bulb current compensation by appropriate software Table 6 Paralleling bulbs overview 5 5W 7 7W 21421W 27427W 2145W 2747W 2142145W 27 27 7W OK without calibration Calibration and monitoring recommended Calibration and Vga monitoring necessary Diagnostics with different load options In some cases the requirement profile asks for alternative loads to be driven with one and the same High Side Driver These load alternatives may be a bulb lamp alternating with an LED cluster In this case the driver e must handle the high inrush current of the bulb load e must provide sufficiently low power dissipation during continuous operation e must not indicate an open load in case an LED cluster is applied instead of a bulb MO 5 drivers today offer an open load threshold in case of drivers with digital status output that is usually low enough to prevent an open load detection in case an LED is connected If an analog current s
77. provement brought to the current sense circuit with the MO 5 is related to the ESD and voltage transient protection of the CS pin With reference to Figure 25 this protection is now obtained thanks to the active clamping structure connected between Vcc and the CS pad represented in a simplified way by a zener Consequently the absolute maximum rating on Vosense now ranges from Vcc 41 V to Vcc This novel solution has removed the inaccuracy at very low Vsgwsg experienced by the MO 3 drivers due to the offset caused by some leakage in the previous ESD protection structure This offset increases when Vsgwsg is lower than Venp because of the ground network which protects against reverse battery With MO 5 the current sense is able to function correctly with the accuracy given by the K factor spread for Vsenge up to 1 V with reference to the device GND Doc ID 023520 Rev 2 27 87 Analogue current sense UM1556 2 6 28 87 Current sense resistor calculation The analogue M0 5 HSDs integrate a current sense which under normal circumstances provides a voltage across an external shunt resistor Rgeyge which is proportional to the load current with an N n ratio the so called K factor OUT Vsense Rsense sense Rsense K LV This allows monitoring of the current which flows through the load and the detection of fault conditions such as open load overload and short circuit to GND leading to a thermal shutdown In
78. re slow opening of contacts can have a negative influence on the lifetime of the relay contacts depending on the switching current In order to protect the freewheeling diode against the reverse battery condition there is an additional diode Dr required in series with the output This circuitry is suitable only for small loads because of permanent voltage drop power dissipation on Dr during normal operation 4 Freewheeling diode and reverse battery P channel MOS circuitry Doc ID 023520 Rev 2 49 87 Switching inductive loads UM1556 50 87 Vbat GND GND GND GND This circuitry is an improvement of the previous example The reverse battery protection of the freewheeling diode and load is solved by a PMOS circuitry with negligible voltage drop at nominal current to avoid undesired power dissipation in on state The peak power dissipation of the freewheeling diode during the demagnetization phase is very low in comparison with the transil protection because of low demagnetization voltage 1 diode voltage drop Furthermore the average power dissipation is much lower assuming non zero load resistance the part of demagnetization energy dissipated in the load resistance is higher at lower demagnetization voltage Therefore this circuitry is suitable for high current inductive loads such as DC motors where the transil protection is usually not able to handle the average power dissipation caused by repet
79. s 1 4 continued Bulb load Driver ron Single channel Dual channel Quad channel W mQ part part part 10 VN5010AK VN5E010AH 60 12 VN5012AK VND5012AK VND5E012AY 16 VN5016AJ VN5E016AH 10 VN5010AK VN5E010AH 12 VN5012AK 55 VND5012AK 16 VN5016AJ VND5E012AY VN5E016AH Table 13 List of suggested bulb driver combinations 2 4 Bulb load Driver ron Single channel Dual channel Quad channel W mQ part part part 10 VN5010AK VN5E010AH 3x27 7 12 VN5012AK VND5012AK 16 VN5016AJ VND5E012AY VN5E016AH 12 VN5012AK VND5012AK VND5E012AY 16 VN5016AJ EIER VNS5E016AH 25 VN5025AJ VND5025AK VN5E025AJ VND5E025AK 27 VNQ5027AK Doc ID 023520 Rev 2 69 87 High Side Driver selection for lamp loads UM1556 Table 13 List of suggested bulb driver combinations 2 4 continued Bulb load Driver ron Single channel Dual channel Quad channel W part part part 25 2747 VN5025AJ VND5025AK i VN5E025AJ VND5E025AK 27 VNQ5027AK VND5025AK 25 VN5025AJ E a AK VN5E025AJ 27 27 VNQ5027AK VND5E050J AJ VNQ5E050K AK 50 VN5E050AJ VNDS5E050K AK Q5E050K Table 14 List of suggested bulb driver combinations 3 4 Bulb load Driver ron Single channel Dual channel Quad channel W part 10 VN5010AK VN5E010AH 12 VN5012AK VND5012AK VND5E012AY 3 21 5 16 VN5016AJ VN5E016AH 25 VN5025AJ VND5025AK VN5E025AJ VND5E025AK 27 VNQ5027
80. se is shown in Figure 25 ky Doc ID 023520 Rev 2 23 87 Analogue current sense UM1556 Figure 25 5 current sense simplified block diagram 2 3 24 87 INPUT Main MOS Sense MOS lsenseH OMA typ Overtemp Cursense Amplified lsense lt 11MA Vour lt 6V gt BY To uC ADC GAPGMS00102 The SenseMOS is scaled down copy of the MainMOS according to a defined geometric ratio driven by the same gate control circuit as the MainMOS Normal operation channel ON CS_DIS low The current flowing through the MainMOS is mirrored by the SenseMOS The current delivered by the current sense pin is regulated by the current sense amplifier through the P channel MOSFET M1 so that Equation 4 VDs Main VDs sense gt Rus sense Isense Main lout and consequently Equation 5 V sense l ZK sense out where Doc ID 023520 Rev 2 ky UM1556 Analogue current sense K IR _ sense DS _ Main encloses the geometric ratio the current sense amplifier offset and various process parameter spreads Care must be taken in order to ensure the Isense is proportional to lour Indeed the maximum drop across the Rsgwse is internally limited to approx 7 5 V as specified in the datasheet by the parameter Maximum analog sense output voltage 5 V minimum 8 V lt lt 16 V 40 lt Tj lt 150 Example
81. son with theory see Figure 38 Figure 38 Inductive load turn off example VNQ5E050AK L 260 mH R 81 Q Tour Vout Vout Vpemac 32 5 TpeMac 12ms i A D Vec Vout gt gt HSD energy E P d f P1 freq C1 P2 period C1 P3 duty C1 P4fall C2 P5 P5 value status R R ES 20 0 MVidiv 10 0 Vidiv 100 m div 5 00 wid 2 00 1 00 msidiv Stop A 40 00 V ofst 20 00 V ofst 0 0 mA ofst 1 00 ms di 1 00 msidiv 1 00MS 100MS sfEdge Negative GAPGMS00115 The demagnetization energy dissipated in the HSD was measured by an oscilloscope with mathematical functions The first function F1 shows the actual power dissipation on the HSD Vgat Vout x lout the second function F4 shows the HSD energy integral of F1 As seen from the oscillogram the measured values are very close to the theoretical calculations Doc ID 023520 Rev 2 43 87 Switching inductive loads UM1556 4 3 4 3 1 44 87 Proper HSD selection Even if the device is internally protected against break down during the demagnetization phase the energy capability is limited and has to be taken into account during the design of the application It is possible to identify two main mechanisms that can lead to the device failure 1 temperature during the demagnetization rises quickly depending on the inductance and the uneven energy distr
82. supply line Therefore an appropriate serial protection resistor should be used between the uC and HSD The resistor value should be calculated according to maximum injected current to the I O pin of the used microcontroller Diode parameters can be lower if an external clamping circuitry is used e g HSD module is supplied from a protected power supply line Doc ID 023520 Rev 2 13 87 General items UM1556 Reverse battery protection using MOSFET Figure 9 OV Voltage levels during reverse battery MOSFET protection Microcontroller E GND GAPGMS00095 The HSD is protected by a MOSFET which is switched off during reverse battery conditions This MOSFET circuitry also provides full ISO pulse clamping at supply line and causes no ground level shift A capacitor between gate and source keeps the gate charged during negative ISO pulses as well The time constant given by RC values should be longer than 2 ms duration of reverse battery protection monolithic HSDs only comparison of negative 1507637 pulse 1 Table 2 Reverse battery protection of monolithic HSDs only comparison Protection type monolithic HSD Voltage drop fluctuation Resistor Calculation of R value necessary BSD Positive and negative ISO pulse 4 transfer to input and diagnostics pin 01 serial protection resistors Any type of load necessary Relatively high power dissipation on
83. th Table 7 VsENSE measurement VsenselV 1 0 64 2 1 29 3 1 99 4 2 69 5 3 39 30 87 Doc ID 023520 Rev 2 ky UM1556 Analogue current sense Figure 30 Vsense measurement Vsense Vs lout Vsense V N c SS SaaS lout A GAPGMS00107 The trend is almost linear in the application range and so we can approximate the Vsense trend with the following equation Equation 6 mE Vsense cn lout a Where m ohm is the rectangular coefficient and a is a constant The output current can be calculated by inverting this equation Equation 7 lout M Vsenset b Instead of loyt Isense x K once M S and b are known it is possible to evaluate the lout with a high accuracy leaving only the spread due to temperature variation The current sense fluctuation due temperature variation is expressed in the datasheet with the parameter dK K How to calculate M and b To calculate M and b two simple measurements performed at the end of the production line are required Chose two reference output currents and 1 and measure the respective and Vgensez These four values must thenbe stored in an EEPROM order to let the uC use this information to calculate K and b using the simple formulas reported below Since we defined lout M V b sense i
84. tis also true that Doc ID 023520 Rev 2 31 87 Analogue current sense UM1556 Equation 8 1 M Veenseit b and ref2 M V sense2t b Solving these two equations we get the following formulas Equation 9 M lret2 Vsenset Vsense2 b ligro V aay V V _ sense1 ref1 sense2 sense sense2 Example for the chosen device Setting 2 A and 4 A according to Table 7 we get 1 29 V and VsENSE2 2 69 V then M 1 43 S b 0 16 A lout is then Equation 10 lout 1 43 Vense t 0 16 After calibration the current sense variation is still affected by the device temperature Equation 10 remains affected by an error proportional to the sense current thermal drift This drift is reported in the datasheet as dK K lour 2 Currente VsENsE 4 V sense drift Vcsp 0 V Tj 40 C to 150 C dK4 K 0 1 The drift decreases when increasing the output current e g in the VND5E025AK datasheet the drift is 13 at 2 A and it decreases down to 6 when the output current is 10 A 2 8 Analogue current sense diagnostics Table 8 summarizes all failure conditions the signal behavior and recommendations for diagnostics sampling for M0 5 in comparison with MO 5Enhanced 32 87 Doc ID 023520 Rev 2 ky UM1556 Analogue current sense Table 8 Analogue HSD diagnostics M0 5 M0 5Enhanced
85. to ensure the junction temperature variation to stay below 60 K Putting the energy value of 9 9 mJ 260 mH calculated in Step 3 to this diagram we can see that we are clearly in the safe area Although the energy curve is introduced only up to 100 mH inductance the calculated energy is below the limit even at 100 mH Step 5 Measurement calculation check see Figure 41 Figure 41 Demagnetization energy measurement VND5E160AJ relay 260 mH ybat EE e a e e e ds Vout Inductivity change effect ME VE I moving of mechanical part with relay contact VpeMac 30V Vee VoutO gt gt HSD enetgy JH E P d t Measure P1 freq C1 P2 period C1 P3 duty C1 P4 fall C2 ga value status 20 0 Vidiv 10 0 Vidiv 100 mA div 5 00 widiv 40 00 V ofst 20 00 V ofst 0 0 mA ofst 1 00 ms div The measured energy is lower by a factor of two than calculated 4 6 mJ measured versus 9 9 mJ calculated This difference can be explained by measurement at ambient temperature when the coil resistance is 25 higher than the resistance at 40 C used in the calculations Another factor is the coil inductance decrease due to the magnetic saturation the inductance value used for calculation was measured at a low current Thase 2 00 9 Trigger Gp 1 00 ms div Stop 5 6 V 25WS sl Edge Negative GAPGMS00118 Conclusion the device can safely drive the load wit
86. value given by the clamping voltage of the HSD and the battery voltage Equation 11 VpEMAG VBAT VcLamp 13V 46V typ The load current decays exponentially linearly if R 0 and reaches zero when all energy stored in the inductor is dissipated in the HSD and the load resistance Since the HSD output clamp is related to the Vpar pin the energy absorbed by the HSD increases with increasing battery voltage the battery is in series with the high side switch and load so the energy contribution of the battery increases with the battery voltage Calculation of energy dissipated in the HSD The energy dissipated in the High Side Driver is given by the integral of the actual power on the MOSFET through the demagnetization time integrate the above formula we need to know the current response iour t and the demagnetization time Tpemag The Iour t can be obtained from the well known formula R L circuit current response using the initial current l and the final current Vpemac R considering iour gt 0 condition see Figure 37 VpEMAG ai out l EMAS 1 e 0 lt t lt TpEMAG2 lout 2 9 Inserting i t 0 we can calculate the demagnetization time Equation 12 t lo T Llo DEMAG Wpemac Equation 13 lo lim T zc c DEMAG R20 VDEMAG Doc ID 023520 Rev 2 41 87 Switching inductive loads UM1556 4 2 2 42 87

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