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Manual - Western Avionics Ltd

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1. BASE REGISTER RT Simulation DATA BUFFERS RTO LS LUT An DDB IRP Op k Illegalization Word 4 tions mas RX Address pU v P Queues Address Data buffer Address HI RT30 TX Data buffer Address LO RTSTAD RT31 Broadcast DATA BUFFERS RTO HS LUT DDB Illegalization Word gs Options mask RX Address P Low High Data buffer Address HI Priority Priority TX Data buffer Address LO Interrupt Interrupt BUFFER RTO LS Mode DDB VETERS Code LUT Options mask Message Message rx legalization Word Data buffer Address Interrupt Status DDB Address Report TX BC MRT Figure 5 1 Multiple Remote Terminal Organisation Diagram UMI 10862 Rew C 45 52 LOOK UP TABLES For each RT the Western Avionics IIB 3910 PMC board manages three different look up tables the address of these tables are obtained from the RT simulation tables These tables are as follows LS Look up Table giving a descriptor for each LS sub address HS Look up Table giving a descriptor for each HS message identifier LS Mode Command Look up Table giving a descriptor for each 3838 mode code NOTE The T R bit of the Command word or Action word is used as an offset to point to the RX or TX block of the look up tables Each desc
2. BASE REGISTER Control Register Message Descriptor Block M Numb Background Program VW Seay Area IRP ana Address LUT gt To LUT aan a gt SMB Queues Address 4 Insertion Program RTSTAD RT Simulation Table DDB 0 Address LS LUT Options mask from lt Time Tag HI MDB Data buffer Address HI Data BDD Address Data buffer Address LO High DDB ig n HS LUT lt Options mask BDD Address Low Priority Priority Interrupt Interrupt Address DATA Data buffer Address HI BUFFERS Data buffer Address LO Time Tag HI Time Tag LO from MDB Message Messages Interrupt Status Report BEB BBB MRT Figure 4 1 Bus Controller Organisation Diagram UMI 10862 Rew C 30 42 MESSAGE DESCRIPTOR BLOCK MDB Each bus message is defined by a message descriptor block as shown in table 4 1 Table 4 1 Message Descriptor Block MBD ADDRESS MESSAGE NUMBER 02H LS Event Mask 04H Message Type Word 06H LS Message Error Phase Definition 08H LS Message Error Description Word 0AH Address in Look up Table 0CH Command Word 1 0EH Command Word 2 10H Action Word 1 12H Action Word 2 14H Retry Subroutine Absolute Address 16H HS e
3. E m 909 41 20 9 gt rui lee gt ULEN 1 lolo 9 TTTTT oe 219 o 6 2 ala ESN P ie 2 1111165 Electrical settings Optical settings 23 INSTALLATION OF THE 3910 Prior to installing the Western Avionics 3910 ensure that all power has been removed from the host computer 24 TURN ON Set mains power on host computer to ON The Western Avionics IIB 3910 PMC will perform system self test on the BC MRT and CM lasting approximately four seconds 25 RESET The Western Avionics IIB 3910 PMC hardware and firmware are reset as follows Reset e Signal ZRES from the PMC bus Power up and power down Bit location in control register accessible by the PMC interface UM 10862 Rev C 12 2 6 SPECIFIC FEATURES 2 6 1 Control Register Features This is a 16 bit write only register accessible from the PMC bus This register is mapped into the memory field The features are as follows Hardware reset Three prioritised interrupts to the local on board processor for indication and control Acknowledge PMC Interrupt 2 6 2 Counter Features This 32 bit counter is a free running counter with a 0 55 or 10 LSB and can be read from a memory mapped location via the PMC bus interface The counter should be read in a single 32
4. 006 DOS 004 D03 D02 DOI DOO 1 0 0 LS 0 0 LC 5 4 M2 1 0 0 0 LS 1 3838 Interface Test Failed FR 1 Frame Counter Test Failed LC 1 Local Clock Test Failed 5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed MI 1 Memory Test 1 Failed If no selftest errors are detected the Status Register will be 8008H 6 2 4 Transformer Direct Coupling Select Register If the LSB of this register is set to 1 the module will be configured for 3838 transformer coupling If the LSB of this register is set to 0 the module will be configured for 3838 direct coupling 6 2 5 HS Subaddress Register The least significant five bits of this register will define the RT Subaddress used by the system for HS transfers 6 2 6 IRQ Selection Register 34H DIS Dl4 12 DIO D04 DOI 0 0 0 0 Trigger Post Trigger Full Stack Half Stack 0 0 0 0 0 0 0 0 H T Ifset a physical INTA interrupt will be generated when the trigger condition is met P Ifset a physical INTA interrupt will be generated when all the post trigger data is captured F Ifset a physical INTA interrupt will be generated when the stack is full If set a physical INTA interrupt will be generated when the stack is half full UMI 10962 Rev C 54 6
5. 1 4 2 11 22 2 2 00000000000000000 10 110 LIST OF FURNISHED ITEMS sese 11 111 LIST OF RELATED PUBLICATIONS esee nennen etre etre ennt 11 112 STORAGE DATA p 11 1 13 TOOLS AND TEST 11 1214 SAFETY PRECAUTIONS 6 Di Er 11 2 INSTALLATION AND PREPARATION FOR 5 0 2 12 2 1 Sis mE 12 2 2 CONFIGURATION SETTINGS teen sete enne trennen 12 2 3 INSTALLATION OF THE 3910 12 24 TURNON M 12 2 5 URINE DIRE DRE dt ES 12 2 6 rte poenae tee ted rdi 13 2 6 1 Control Register Feat res ue ete et ete e doe Ue Ret pas een been en hae 13 2 6 2 Counter T 13 2 6 3 IrigpersIn Features eoo 13 2 6 4 Irigger Out Features E E 13 Dele DOSE Ee DUE RESTS 14 2 7 1 Intvoductioni i o eR ERE ORE CURRERE VEREOR OUR 14 2 7 2 Electrical Chardcteristies eee ei ies e is oe 14 2 7 3 Capabilili esseere nece cc EU MM I EI TM 14 28 3839 INTERFACE
6. 2 8 LAYOUT J1 VIEWED ON FRONT PANEL FACE 15 BUS CONTROLLER ORGANISATION DIAGRAM eene nennen nnne enne nnns inneren 30 DATA BUFFERS SIMULATION AND MONITORING 2 244204442 eene enne ener 36 MULTIPLE REMOTE TERMINAL ORGANISATION DIAGRAM 45 LIST OF TABLES BASE REGISTER NAMES AND LOCATIONS eese emen 18 COMMAND REGISTER 1 00224 eene nennen enne een enne 20 STATUS REGIS LER Lec ML IN TEE 21 REMOTE TERMINAL SIMULATION TABLE ccccessseceessssecessaeeecessceceesaececeesseceeseesecseaaeescessaeens 28 MESSAGE DESCRIPTOR BLOCK esses enne eth nnnn ntes eet nete nnns 31 DATA DESCRIPTOR 2 4 24 1 37 DATA BUFFER o eo remitte ient 42 BASE REGISTERS 52 COMMAND 8 6 1 2 2 200 0000 00000000 53 STATUS 8 8 0 21101 0 10 00 00000 Nenia E Tre A eini 54 STACK I ATAIFORNDAT 66 STACK MESSAGES hi Re 68 1 GENERAL INFORMATION 11 INTRODUCTION This manual app
7. 5 M4 M3 M2 MI I 0 0 0 LS 1 3838 Interface Test Failed HS 1 3910 Interface Test Failed 1 Local Clock Test Failed 5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed MI 1 Memory Test 1 Failed Several bits can be set simultaneously If no self test errors are detected the code in the status register will be 8008H UMI 10862 Rev C 21 3 4 3 5 Background Running Pointer BRP 08H In the BC mode the Background Running Pointer BRP directs the firmware to the location of a background program which can be used to organise the message sequencing Before sending a BC start the user must initialise the BRP BRP is updated by the on board processor after executing a BC STOP command Table 3 4 is a list of the possible instructions with descriptions and examples Table 3 4 Instruction Set Background Program DELAY 0000H XXXXH XXXX Delay LSB of 10us NOPI 000 PC NOP2 0002 PC PC 2 NOP3 0003H PC PC 3 BSR 0004H XXXXH XXXX 16 bit signed branch to subroutine BRA 0006H XXXXH XXXX 16 bit signed branch JMP 0007H XXXXH XXXX 16 bit absolute address for jump RTS 0008H Return from subroutine RTI 0009H Return from insertion routine ENI 000 Enable program insertion DSI 000 Disable program insertion LOOP 000CH XXXXH Load loop counter with value XXXX DBNE 000DH XXXXH LOOP LOOP I branch s
8. sse 50 5 6 2 Message Interrupts or set of messages interrupt eene 50 5 6 3 Status Report Queue two words per report 50 297 SPECIFIC FUNGIIONS 55 per hene cepe 51 5 7 1 Data Message Reception nennen een en eee ee ren 51 2 72 Reception of Mode Commands Data Words 51 5 7 3 Mode Command Synchronise with Data seen 5l 5 7 4 Frequency Toggle d pede eodem abt be EE prep 51 5 7 5 Programmable HS RI TI Time 020020 0 1 0100000000000 51 UMI 10962 Rev C 23 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION 2 0 0 004 20 52 6 INTRODUC HON ceti area E DD 52 6 2 BASE REGISTERS oett ORE 52 6 2 1 Control Register Write 00 53 6 2 2 Command Register CR CURE 53 6 2 3 AIDE TK AGAT 54 6 2 4 Transformer Direct Coupling Select Register esee 54 6 2 5 HS Subaddress Register crits inesi ae re da 54 6 2 6 IR Selection Register Gad ra aeta 54 6 2 7 Load Clock HI LO Registers
9. HR Clear gt Hardware RESET If IEN is set and IRQ is set then interrupt line will be cleared If is set and IRQ is clear then the interrupt line will be asserted for test purposes only If is clear the value of IRQ is unaffected Note This register must be accessed to clear the interrupt during an interrupt service routine 1 0102H generates a command request 2 0163H clears the interrupt line 3 4 2 2 Clock HI Word Read 00H Clock LO Word Read 02H UM 10962 Rev C e Local Clock Reading CK HI LO Read a 32 bit word Update Local Clock by User Write new value in registers LOAD Clock HI LO Registers Write LOAD code 000 in command register Write 0 in the control register After executing the command the on board processor sets CO to 1 See Command Register below Synchronise Clock If the above procedure is carried out using synchronise clock command 0010H the contents of LOAD Clock HI will be added to the current clock value as a 32 bit signal offset 19 3 4 2 3 Command Register CR 04H Prior to clearing the command request bit CO in the control register the user must first test that the command register is clear When the command register is clear the user can insert the next command to be executed After the command is loaded bit CO in the control register can be cleared When the command register
10. The VXI 2800 module can inject errors on the LS status words in response to an action word receive command when simulating the RT The error injection is defined in the look up table in the word pointed by the HS sub address so it is common for the HS message identifiers In the HS look up table For an HS message identifier the error description word can take only two values Word 0000H for normal Word 0000 to illegalize the corresponding HS message identifier Illegalization is managed corresponding to the STANAG 3910 by the setting of the HS message frame error bit in the HS status word Ifa HS TX message is illegalized the RT will not transmit the HD data Error injections on the HS lines are defined in the DDB TX mode codes and all HS messages have fixed response times and will not be affected by the global or look up table response time error option All other messages have a minimum response time of 8 us The individual response time facility in the error injection word is a value that is added to the minimum response time Therefore a unique response time value of three in the error word will result in of response time of 11 uS 49 5 6 INTERRUPTS CODING 5 6 1 Low and High Priority Interrupts two word code On data messages without error 0800 DDB address On data messages with error 0 DDB address On mode commands without error 0900 DDB address On mode commands with error 0D00H DDB a
11. 38 1 55 6 2 8 Current Address Register CAR 42 55 6 2 9 Trigger Occurrence Register TOR 44 eene eren 55 6 2 10 Trigger Set up Pointer TSP 46H 55 6 3 DETAILED TRIGGER DESCRIPTION 56 642 STACK netto ette pretextu 66 6 4 1 Previous Address Pointer e aeea ei eo e 66 6 4 2 Time Stamp HILO aeo oed 66 6 4 3 Jpn 66 6 4 4 Next Address Pointer eese eene nennen retener entren ener enn 67 6 4 5 RI Response Time 1 2 tei tertie itid tene eene reste dta 67 6 5 3910 DATA iiie terrere bine Ree danas LER ERR EE LL 68 6 5 1 Flow Diagram REN 66 UM 10962 Rev C FIGURE 1 1 FIGURE 2 1 FIGURE 4 1 FIGURE 4 2 FIGURE 5 1 3 1 TABLE 3 2 TABLE 3 3 3 4 TABLE 4 1 TABLE 4 2 TABLE 4 3 6 1 6 2 6 3 6 4 6 5 UM 10962 Rev C LIST OF FIGURES IIB 3910 PMC FUNCTIONAL BLOCK
12. WESTERN AVIONICS STANAG 3910 PMC INTELLIGENT INTERFACE BOARD P N 1U10962G01 RevA User Manual UM 10962 Rev C Western Avionics Ltd 13 14 Shannon Free Zone Co Clare Ireland 9th July 2003 Table of Contents 1 GENERAL INFORMATION ississcssssccsisssecscsuscsceusecsosassescnstsaecsecescacbasncanssicnusadcess condeases 6 1 1 INTRODUCTION RISE IH EIE ERE ee ede et EEE 6 12 MANUAL DESCRIPTION 6 L3 CAPABILITIES ettet mri epi tested epe 6 1 3 1 0 2 12 1 6 1 3 2 Bus Controller BC Features With MRT Simulation and Data 7 1 3 3 Multiple Remote Terminal MRT Features sse eene 7 1 3 4 Chronological Bus Monitor CM Features eene eene 7 14 IIB 3910 PMC ARCHITECTURE piece remet ere pe 8 1 55 PROTOCOL MANAGEMENT 8 L6 3838 INTERFACE circe erit adit teen entere orte 8 1 7 en 9 1 8 10 1 9 SYSTEM CHARACTERISTICS AND 5
13. 40H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 D10 D08 D07 DOS D04 D03 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 2 Bus ID Word Type Register Base Address 42H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 D10 D08 007 DOS D04 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 2 Error Word Mask Register Base Address 44H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 D10 D08 D07 DOS 004 D03 D02 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Error condition disabled UMI 10962 Rew C 60 Trigger Data 2 Error Word Register Base Address 46H This register will define the Errors req
14. LSB lus For some modes this global response time register 15 not programmable fixed at 405 e 3838Mode without data If the value is less than 4 the on board processor selects 415 3 4 2 22 RT No Response Time Out Register 2AH programmable no response time out defines maximum RT response time allowed by the board to an RT before detecting NO RESPONSE LSB lus 3 4 2 23 HS Sub Address 2CH Indication for the on board processor of the sub address value used to define HS messages Set to 0Ox001A for EFA Set to 0x0001 for RAFALE Set to OXFFFF for 1553B operation only UM 10962 Rew C 25 3 4 2 24 IRQ Selection Register 34H D15 014 012 D11 D09 D08 007 D05 004 D02 DOI 0 0 0 0 Cycling Message HI Queue LO Queue 0 0 gue 0 M 0 0 0 0 L Ifset a physical INTA interrupt will be generated when a Broadcast Synchronise With Data mode code occurs If set a physical INTA interrupt will be generated when a push to the Message Queue occurs H Ifset a physical INTA interrupt will be generated when a push to the High Priority Queue occurs L If set a ph
15. 2 7 Load Clock HI LO Registers 38H1 3AH If a LOAD CLOCK command is executed these two registers define a 32 bit value to be loaded into the counter If a SYNCHRONIZE CLOCK command is executed the two registers define a 32 bit signed number to be added to the current clock value 6 2 8 Current Address Register CAR 42H This register contains the PAGE address of the current message being stored 6 2 9 Trigger Occurrence Register TOR 44H This register contains the PAGE address of the message that met the pre programmed trigger condition 6 2 10 Trigger Set up Pointer TSP 46H This register contains the absolute address of the trigger set up data NOTE This value is only 16 bits All trigger set up data must reside in the first 64Kbytes of the board 6 2 10 1 Trigger Set up Data TSP Address 00H Post Trigger Count Register PTCR This register will contain the number of messages to be stored after the trigger condition is met This value will be in the range 0000H to 8000H 0000H Stop immediately after trigger message 8000H Capture Forever 02H Selective Capture Count Register SCCR This register will contain the number of messages to be stored when the monitor is in the Selective Capture Mode This value will be in the range 0000H 8000H 20000H 1 message 8000H Selective Capture Forever 04H Start Page Register SPR This register will contain the desired PAGE address for the start of the monitor
16. 3 Bus ID Word Type Register Base Address 4EH This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D10 009 D08 DOS 004 D02 DOI DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Date 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 3 Error Word Mask Register Base Address 50H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D10 009 D08 DOS D04 D02 DO DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled UMI 10962 Rew C 61 Trigger Data 3 Error Word Register This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors Base Address 52H D15 D14 D13 D12 D10 009 D08 DOS D04 D02 DOI DOO 0 0 0 16 Sh 0 0 WC 0 0 NR TA Sy 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA
17. 33 NOTES 1 Word Number For the first word of the message command or status WWWWWwW 000000 2 Synchro Pattern Error Defines a specific synchro bit each Si defines the level for 500ns duration at least 1 bit of S5 SO must be set 55 54 53 52 51 50 right synchro bit example false synchro bit example 55 50 011001 3 Manchester Bit Error B4 BO defines the bit position in the word for the error 4 Word Length Error L4 L0 defines the number of bits in the word NOTE This count has an offset of 1 such that a value of 01111 will result on a valid word with a data bit count of 16 Wrong bus error RT response on wrong bus Both busses error RT response on both busses e Response time error RRRRR replaces the global RT response time LSB 1uS Illegal command Reserved for MRT only 4 2 6 Address in Look Up Table OAH This will contain the address in the look up table for the DDB pointer See figure 4 1 4 0 7 Command Word 1 0CH First Command Word 4 2 8 Command Word 2 0EH Second Command Word RT RT 3838 4 2 9 Action Word 1 10H First Action Word to be transmitted 3910 message 4 2 10 Action Word 2 12H Second Action Word to be transmitted RT RT 3910 4 2 11 Retry Subroutine Absolute Address 14H On completion of a message if an Event defined by the Mask has occurred and the Retry Event is enabled the Subroutine defined by this absolute address will be called
18. NOTES 1 The retry subroutine must be terminated by the RTS instruction to return execution back to the main background or insertion program 2 This feature can be used for immediate insertion of Acyclic messages or retry of the same message on the alternate bus UMI 10962 Rev C 34 4 2 12 HS Event Mask 16H 15 07 0 06 HS Data Overlap Error BIT 05 3910 Word Count Error BIT 04 FCS Error BIT 03 Invalid No End Delimiter BIT 02 Invalid NO Start Delimiter BIT 01 3910 No Response BIT 00 3910 Frame Word Timeout NOTE HS Data Overlap error bit Indicates that the HS data words of the previous message have been overlapped by the HS data words of the new image Data Message 1 Data Message 2 Overlap 4 3910 4 2 13 Inter message Gap Time 18H Gap between the end of this message and the LS line and the beginning of the next one next LSB 0 1 uS For 3910 message this inter message gap time must take account of the HS message 4 2 14 HS RT RT Inter message Gap Time Gap between the two 3838 messages initiating a HS RT RT message e LSB lys Intermessage Gap 9 HS Data Message 3910 4 2 15 Status Word 1 ICH First RX Status Word in the message If the BC detects no response error this value will be updated with FFFFH 42 16 Status Word 2 IEH Second RX Status Word in the message RT RT If the BC detects a no response error from the
19. Set of Message Number Message Indicator in Set of Message HS Frame Time out RI TI Register HS Errors High HS Errors Low Reserved Data Buffers Simulation and Monitoring 36 LS DATA BUFFERS Time Tag High Time Tag Low Data Data Data Data Data HS DATA BUFFERS Time Tag High Time Tag Low FC PA DA WC Data Data Data Data FCS 4 3 1 Look Up Table The sixth word of a message descriptor block points to a double word in the look up table that one contains the address of a LS or HS data descriptor block An identical architecture is defined in MRT mode but using LS sub addresses or HS message identifiers to point into the look up table Look up Table Address Error Injection Word MRT only 02H DDB Address Ext Subaddress look up table address 4 3 2 Data Descriptor Block A data descriptor block is associated with each data message this 16 word set defines the data buffering and associated queue control information Interrupt selection is defined in the option mask word Interrupt on correct or erroneous message or after a set of different messages and priority of interrupt three different available one interrupt only per message The data word count contains the data word count expected by the user The Western Avionics 3910 processor c
20. When unpacking remove all protective covering and store covering and packing container as unit may need to be reshipped at a later date CAUTION The 3910 card contains Electrostatic Sensitive Devices ESD s Observe ESD handling requirements and do not ship or store near electro static electromagnetic magnetic or radioactive fields 22 CONFIGURATION SETTINGS There are several headers used on the 3910 to allow it s use on either electrical or optical implementations of Stanag 3910 these headers are fitted to 3 way link blocks and are supplied fitted to match the customer selected application Optical settings are as shown below diagram on the left electrical settings on the right Linker L1 located top LH corner provides 5V feed to optical interface unit only Linkers L2 to L9 inclusive located in centre of unit configure HS routings for either electrical implementation when fitted to top of block or optical when fitted to bottom of block as indicated Header fitted at PP2 bottom LH of unit is used for user upgrades to firmware only and is supplied fitted to bottom of block as standard This header should only be placed in the upper position for firmware up grades details of which are supplied with any firmware up grades provided EEEIEI 99999 900006 a
21. clears the board is ready for a new command Refer to table 3 2 Table 3 2 Command Register CR CODE COMMAND 0000H Illegal 0001H GO TO BC MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H BC COLD Start 0005H BC WARM Start 0006H BC STOP 0007H MRT COLD Start 0008H MRT WARM Start 0009H MRT STOP 000AH PAUSE 000BH UNPAUSE 000CH LOAD CLOCK 000DH SELFTEST 000 RUN MONITOR 000 STOP MONITOR 0010H Synchronise CLOCK NOTE PAUSE Stop the Local clock UNPAUSE Restart the Local Clock UM 10962 Rev C 20 3 4 2 4 The status register will contain a word reflecting the status of the board as shown in table 3 3 Status Register SR 06H Table 3 3 Status Register CODE STATUS 0001H BC IDLE 0002H MRT IDLE 0003H MON IDLE 0004H BC RUNNING 0005H BC INSERTION RUNNING 8004H BC PAUSED Background 8005H BC PAUSED Insertion 9004H EXECUTING SOFTWARE PAUSE SWPSE A004H EXECUTING HARDWARE PAUSE HWPSE 0006H MRT RUNNING 8006H MRT PAUSED 0007H MON RUNNING 0008H MON RUNNING XXX8H EXECUTING SELFTEST FINISHED SELFTEST The status register will contain the following information after completion of self test D15 D14 D12 DII DIO D08 DOS D04 D02 DO 1 0 0 LS HS 0 LC
22. in a different buffer from the following data words The header option and the number of header words are defined in the option mask Header Address Header Message K Data Message K Header Message 2 Data Message 2 Header Message 1 Header Word Data Message 1 Time Tag High L Time Tag Low Data Data Data Buffer Address Data Data 10962 Rew C 41 DB ADDRESS 3838 BUFFER 3910 BUFFER 00H Time Tag HI Time Tag 3 02H Time Tag LO Time Tag 4 04H Data FC PA Automatically Updated 06H Data DA 08H Data WC 0AH Data Data 0CH 4 Data with or without Data Data 1 FCS In Receive Message only Table 4 3 Data Buffers 44 MODE COMMANDS In Bus Controller mode the Western Avionics IIB 3910 PMC board can transmit all mode command messages LS or HS For each mode command message data descriptor blocks pointed through the look up table allow the definition of interrupt requests or associated data word address storage If such a command is directed to an on board simulated RT the corresponding actions are made on the RT simulation table e Transmit RT status word last command word LS bit word e Inhibit or override inhibit LS or HS transmitters Examples a Synchronise with Data Word The data is obtained from the data buffer point
23. of the next message This value will be set to FFFFH for the last message after the post trigger count has expired and capturing has stopped 6 4 5 Response Time 1 2 These two locations will define the RT response times if any of the Status words in the message The second Response time is only applicable for 3838 RT RT transfers UMI 10962 Rev C 67 6 5 3910 DATA FORMAT If a 3838 message results in the transfer of 3910 data this message will be stored at the first new page after the 3838 message The NEXT ADDRESS value in the 3838 data will account for this and point to the first page after the expected 3910 data The first word in the 3910 data will describe the validity of the message as follows 015 D14 D13 D12 D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 001 V 0 0 0 0 0 0 0 0 S W F 0 E R B V W S F E R B If set this indicates that the 3910 message is ready to be interrogated If set this indicates that the 3910 message had wordcount error If W is set then this shall indicate if the error was ve or ve 1 ve If set this indicates that the 3910 message had a FCS error If set this indicates that the 3910 message had a manchester encoding error If set this indicates that the 3910 message had a RI timeout no HS response If set this indicates th
24. per report l 3838 Messages Message Number MSB 0 EVENTS with EVENTS BIT 15 Wrong Both Buses Error BIT 14 NO RESPONSE Error BIT 13 RT ADDRESS Error BIT 12 Error Mn LG SH WC Late Response BIT 11 SYNC Type Error Bit 09 0 Ist Status 1 2nd Status 10 BITS 08t000 RX Status Bits 2 3910 Messages Message Number MSB 1 EVENTS with EVENTS BIT 15 to 08 0 07 HS Data Overlap Error BIT 06 HS wordcount error polarity 1 Too many words BIT 05 HS Word Count Error BIT 04 2 HS FCS Error BIT 03 HS preamble count error BIT 02 HS manchester encoding error BIT 01 HS RI timeout BIT 00 HS Bit count error UM 10962 Rew C 44 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION 51 INTRODUCTION In Multiple Remote Terminal mode the Western Avionics IIB 3910 PMC board can simulate up to 31 RTs After initialisation by the host the board is ready to listen to the bus activity and to respond to command words for the simulated RTs The description of the mode of operation uses tables similar to those defining the bus controller mode providing the same associated features multiple data buffering signalisation etc Refer to figure 5 1 the Multiple Remote Terminal Organisation Diagram The specifics of the MRT mode of operation mainly concern the following e The logical path to point into the look up tables e The errors injection capabilities
25. processor after executing BC stop command 3 4 3 7 Reserved 0CH 3 4 2 8 LPIQAP Low priority interrupt queue start address 3 4 2 9 Reserved 10H 3 4 2 10 HPIQAP 12H High priority interrupt queue start address 3 4 2 11 Reserved 14H 3 4 2 12 MIQAP 16H Message interrupt queue start address 3 4 2 13 Reserved 18H 3 4 2 14 SRQAP Status report queue start address 3 4 2 15 Reserved ICH 3 4 2 16 RTSTAD RT simulation table start address Contains the address of the RT Simulation Tables which defines the RT status when they are simulated 3 4 2 17 Reserved 20H 3 4 2 18 Reserved 22H UMI 10862 Rev C 24 3 4 2 19 Toggle Buffer Address Offset 24H e MSB 1 global toggle enable 0 toggle offset 15 bits MSB offset 15 14 0 For data buffer if the toggle feature is selected bit 15 1 address of toggle buffer is Buffer Address High Toggle Buffer Offset Buffer Address Low 15 bits For further details refer to paragraph 4 3 3 3 3 4 2 20 Set of Messages Start Address 26H This is the pointer of a 256 word table reserved to the on board processor to compute the registers Set of Messages For further details refer to paragraph 4 5 2 3 4 2 21 Global RT Response Time Register 28H This is the response time for all the simulated RT s Different RT response time be defined in the error description words
26. second RT this value will be updated with FFFFH UM 10862 Rev C 35 43 DATA BUFFERS SIMULATION AND MONITORING The Western Avionics IIB 3910 PMC board processes all the data buffers running on the LS and HS lines Data buffers to be issued by the BC or the simulated RTs are transmitted by the IIB 3910 PMC board all others can be monitored A multiple data buffering structure is implemented Identical paths are used to access the data buffers whether they are transmitted received LS or HS These paths use a look up table and data descriptor block Refer to figure 4 2 Data Buffers Simulation and Monitoring LOOK UP TABLE LS TYPE DATA DESCRIPTOR BLOCK Option mask Header Address Reserved MRT Data Word Count Data descriptor Block Address Data Status Report Toggle Freq Buffer Addr High Buffer Address Low Link Pointer to another DDB Reserved Reserved Message Interrupt Code Set of Message Number Reserved HS Reserved MRT Reserved HS Data descriptor Block Address Reserved HS Reserved Figure 4 2 UM 10962 Rev HS TYPE DATA DESCRIPTOR BLOCK Option Mask Reserved LS Data Word Count Data Status Report Toggle Freq Buffer Addr High Buffer Address Low Link Pointer to another DDB Address of Modify Word Value to Write Message Interrupt Code
27. stack area 06H Finish Page Register FPR This register will contain the desired PAGE address for the end of the monitor stack area This value must be greater than the Start Page Register value 08H Window Word Count Register This register will contain the word number in the specified message on which the window trigger test is to be carried out If this value 15 zero the test will be carried out on any word within the specified message UM 10962 Rev C 55 0 3910 Trigger Error Register This register will define the error s in a 3910 message required for a trigger condition to occur If more than one error is defined the condition will be a logical OR of these errors This register is only relevant when the monitor trigger is in 3910 mode D15 DIA D12 D11 D10 D09 DOS D04 D02 DOL DOO D 0 0 0 0 0 0 0 0 W F P E R B W Trigger on Word Count Error F Trigger on FCS Error P Preamble bit count error E Manchester encoding error R RI timeout no HS response B Bit count error 0CH Hardware Trigger Register D15 D14 D13 D12 D10 D09 DO8 DOS 004 D02 DO DOO 0 0 0 0 0 0 0 0 0 0 0 The Monitor will wait for LO HI transition on TRIG IN input before storing messages and searc
28. 000 Figure 2 2 UMI 10862 Rev C Layout of J1 viewed on Front Panel face 15 3 OPERATION 31 INTRODUCTION The Western Avionics IIB 3910 PMC Intelligent Interface Board provides Bus Controller BC Multi Remote Terminal MRT functions which may be run either independently or simultaneously An independent Chronological Bus Monitor CM is also provided In order to run any of these functions information must be loaded into specific fixed register locations Base Registers Some of these registers contain pointers to other areas of memory registers The selection of these pointers is left up to the discretion of the user Therefore memory blocks can be positioned in the on board memory to suit user requirements This set up means that fixed position registers are minimal 32 CONVENTIONS 1 BASE PCI Base Address of this board 2 The memory range 10000 to End of Memory is reserved for the 3838 and 3910 data blocks All other data must reside in the first 64Kbytes After a Power On On board processor doing its power on initialisation Then executing Self Test Then waiting for a user command DSI default insertion program is disabled 33 ORGANISATION DIAGRAM The organisation diagram figure 3 1 shows how the functional areas of the Western Avionics 3910 board can be controlled 34 BASE REGISTERS The only fixed position registers are the Base Registers The Base Reg
29. 11 gt Inject Error in 1st RT SIM Ist RT response XXX 100 gt Inject Error on 2nd RT SIM 2nd RT RT response 4 0 5 LS Message Error Description Word 08H The following word defines the errors that can be injected into the 3838 message DI5 014 DI2 DIl DIO D09 105 104 002 DOI T T X X X X xX X X X X IX X X X TIT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 0 0 0 1 1 Parity error 55 54 53 52 51 SO Synchro Pattern Error 0 B4 B3 B2 BO Manchester Bit Error 1 L4 L3 L2 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TIT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TIT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS TTT 101 gt Illegal Command XXXXXXXXXXXXX 0000000000000 Not applicable for Mode TTT 110 gt Extended Subaddress XXXXXXXXXXXXX 0000000000000 Not applicable for BC Mode TTT 111 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 Not applicable for Mode UM 10962 Rev C
30. 910 BC RT BROADCAST 1 1 0 1 RECEIVE CLOCK BROADCAST 1 1 1 0 3910 RT RT BROADCAST 1 1 1 1 3910 MODE COMMAND BROADCAST 1 Extended Subaddress 1 Retry on EVENT 1 Interrupt on EVENT enabled 1 Interrupt on EVENT priority queue 0 LO priority 0 3910 Bus A 1 3910 Bus 0 0 0 If RETRY is enabled and IRQ on EVENT is disabled the RETRY will still take place Broadcast Receive Clock is a special message used for transmitting the 32 bit clock as data This message type only requires an MBD to define the command word and the inter message gap No queue interrupt or buffer control is carried out The transmitted message will be the command word defined by the MDB followed by two data words Clock Value HI and Clock Value LO clock value at the end message on the bus The transmission of a Broadcast Synchronise with Data mode code using the 3838 mode with data broadcast message type will cause cycling interrupt to be generated if enabled and the associated data word defined in the data buffer will be stored in the cycling interrupt base register 40H 32 4 2 4 LS Message Error Phase Definition 06H The following word defines the location of errors that can be injected into the LS message DIS D14 D12 DIO 0081007 006 005 D04 002 001 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X XXX 000 Error Injection Disabled XXX 001 gt Inject Error in 1st BC TX Initial BC message XXX 0
31. Cycle 1 SWPE SWPSE BRA xxxx with Minor cycle X SMB xxxx SMB xxxx RTS P LOOP 8 JSR Minor cycle SWPSE DBNE xxxx SITH BRA xxxx e Insertion Commands can be executed during SWPSE state HALT Oncompletion of this instruction the board will return to the BC idle state re start the board BC Cold Warm Start command register e SITH SITL The on board processor puts the value code in the cycling FIFO s gt High Priority L gt Low Priority HWPSE Hardware Pause e Restart by the external Trig In external CK All the registers are not initialised e Used to synchronise messages of minor frames on external Trig In Example See SWPSE above UM 10962 Rev C 23 3 4 2 6 Insertion Running Pointer OAH The Insertion Running Pointer IRP has the same set of instructions as Instruction Set Background Program To initiate an insertion the user must first load the IRP with the address of the insertion program Then bit Cl can be cleared in the control register background program be interrupted by an insertion command The insertion program cannot be interrupted by any other insertion command In this case the second insertion request will be delayed until the end of the first one Insertion program starting just before a minor cycle start will delay this one is updated by the on board
32. E 2 8 1 Introduction The 3838 interface matches the STANAG 3838 Standard 2 8 2 Electrical Characteristics The 3838 interface provides one dual redundant bus e Primary bus e Secondary bus The 3838 interface can be programmed to be e Transformer coupled Direct coupled 10962 Rev C 14 2 9 Input Output Connector J1 The 25 way connector M83513 13 D0OINP at J1 is a Micro D metal shell 0 050 contact spring type and is used for the supply of trigger in trigger out and all PMC bus signals Front panel connector pin out as follows Connector Signal Comments Pin Number designation 1 5 5 volt feed for external box 2 PRI 3838 Primary positive 3 GND 4 SEC 3838 Secondary positive 5 WNRDMA Write not read DMA FOFE control 6 GND 7 NTXDI HS TX secondary negative 8 EXTTRIG A2 External trigger Anode 9 NRXDI HS RX secondary negative 10 GND 11 TXDO HS TX primary negative 12 TRIGOUT El Trigger Out Emitter 13 RX0 HS RX primary negative 14 5V 5 volt feed for external FOFE box 15 PRI 3838 Primary negative 16 GND 17 SEC 3838 Secondary negative 18 GND 19 TXDI HS TX secondary positive 20 EXTTRIG K2 External trigger Cathode 21 RXDI HS RX secondary positive 22 GND 23 HS primary positive 24 TRIGOUT Trigger Out Collector 25 RX0 HS RX primary positive 0000000000000 000000000
33. N DEFINITION Error injection on status word and 3838 data words transmitted can be defined message by message using the message error descriptor word in the look up table or globally for all messages transmitted by an RT using global RT error injection word in each RT simulation table UM 10962 Rev C 46 5 5 1 Global RT Error Description Word RT Simulation Table The following word defines the errors that can be injected into the message D15 014 D12 Dil DIO 009 D07 106 005 004 D02 x x x x X X X X X X X TIT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y 0 0 0 S5 1 0 1 1 Y Y Y Y Y ERROR TYPE 0 0 0 00 Parity error S4 53 52 51 SO Synchro Pattern Error B4 B3 B2 Bl BO Manchester Bit Error L4 L3 L2 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TIT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TIT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P 2 3 Word Count Error Polarity Word Count Error VE Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR NOTE UM 10962 Rev C Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 Global error injection is enabled disabled by the LSB bit of the simulation type
34. Note This register must be accessed to clear the interrupt during an interrupt service routine Examples 1 0102H generates a command request 2 0163H clears the interrupt line 6 2 2 Command Register CR Prior to clearing the Command Request bit in the Control Register the user must first test that the CR is clear When the CR is clear the user can insert the next command to be executed Refer to table 6 2 Table 6 2 Command Registers CODE COMMAND 0000H Illegal 0001H GO TO BCT MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H Reserved 0005H Reserved 0006H Reserved 0007H Reserved 0008H Reserved 0009H Reserved 000AH Reserved 000BH Reserved 000CH LOAD CLOCK 000DH SELFTEST 000EH RUN MONITOR 000FH STOP MONITOR 0010H SYNCHRONISE CLOCK After the command is loaded bit CO in the Command register can be cleared When the CR clears the board is ready for a new command UM 10962 Rev C 53 6 2 3 Status Register SR This register contains a code reflecting the status of the board as shown in table 6 3 Table 6 3 Status Registers CODE COMMAND 0001H Reserved 0002H Reserved 0003H MONITOR IDLE 0004H Reserved 0005H Reserved 0006H Reserved 0007H MONITOR RUNNING 0008H Reserved The Status Register will contain the following information after completion of selftest D15 D14 D13 D12 D10 D09
35. Register is to be included in the trigger condition D15 D14 D13 D12 D10 D09 DO8 DOS 004 D02 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled UMI 10962 Rew C 62 Trigger Data 4 Error Word Register This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors Base Address 5EH D15 D14 D13 D12 D10 009 D08 DOS D04 D02 DOO 0 0 0 16 Sh 0 0 WC 0 0 NR TA Sy 10 Sy 1 Sync Type Error Sh 1 Short Word Error TA Terminal Address Error Lg 1 Long Word Error NR No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Start Register Base Address 60H This register defines the first trigger to be used in the trigger sequence This will be in the range to 5 Examples The first trigger used in the sequence is defined by the contents of the Trigger Start Register For these examples assume that the Trigger Start Register points to Trigger 1 value 1 Find the word defined by Trigger Data 1 then save the number of messages defined by the PTC register Key TTR Trigger Type Register TDP Trigger Data Pointer TPP Trigger Pass Pointer TFP Trigger Fail Pointer Trigger Stop Register Ex
36. TRUE for a word within the incoming message the Window Trigger will branch to the trigger defined in the Pass Register If the value of the Window Word Count Register is non zero the Window Trigger will use this value to specify the word number within the message for the Trigger test to be carried out If this value is zero all words within the message will be tested The Window Trigger would normally be preceded by a Single Trigger The Single Trigger would define the specific 3838 command word then pass to the Window Trigger to define a specific bit pattern of a particular word within this message If the Window Trigger Fail Register points back to the Single Trigger requirements then the monitor will start again with the next 3838 message UM 10962 Rev C 56 3 3910 Message Trigger Mode The 3910 Message Trigger will act the same as the Window Trigger with the following exceptions a There is no associated word count register This trigger should only be used for 3838 messages that will initiate a 3910 data transfer b If the specified 3838 word within the message is found this trigger does not automatically pass to the next trigger The resulting 3910 message is interrogated and compared with the 3910 Trigger Error Register Only if this condition is met will it branch to the trigger defined by the Pass Register If this condition is not met the next trigger will be defined by the Fail Pointer Register Value 4 Selectiv
37. Terminal Address Error Lg 1 Long Word Error NR No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Data 4 Trigger Data 4 Bit Mask Register Base Address 54H This register will define the bits to be ignored in the trigger bit pattern for trigger data 4 Any bit set in this register will be masked from the trigger test condition Trigger Data 4 Bit Pattern Register Base Address 56H This register will define the bit pattern required for trigger data Trigger Data 4 Bus ID Word Type Mask Base Address 58H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D10 D09 DO8 DOS 004 D02 DO DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits Ignore Bus ID in trigger condition Trigger Data 4 Bus Word Type Register Base Address 5AH This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D10 D09 D08 DOS D04 D02 DO DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Wmsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 4 Error Word Mask Register Base Address 5CH This register will define if the Error Word
38. able Broadcast HS Look up Table Broadcast LS Mode Commands Look up Table Address Table 3 4 Remote Terminal Simulation Table 3 5 1 Simulation Type Word BIT 15 Bits BIT 14 14 to 0 BIT 13 are for 12 MRT BIT 7 only BIT 6 BIT 0 other bits Bits 7 and 6 UM 10962 Rev 1 RT simulated Reserved 1 Inhibit transmitter LS on primary bus 1 Inhibit transmitter LS on secondary bus 1 Errors enabled on primary bus status word and data 1 Errors enabled on secondary bus Status word and data 1 Enable global error injection 0 Enable global RT errors defined in the RT simulation table as message per message errors defined in the look up tables 28 3 5 2 Status Word Broadcast and message error bits are dynamically updated Service request bit automatically set by the request files and cleared by the TX vector word mode code command Busy bit can be set by user to disable data transmission 3 5 3 LS Last Command Word Automatically updated including broadcast so the TX last command mode code is correctly simulated 3 5 4 LS Bit Word For user purposes 3 5 5 HS Status Word Automatically updated for frame error RX ready busy TX ready busy bits including broadcast So the 3910 TX command is correctly simulated This word in the simulation table is used by the on board processor as a flag to record FRAME errors However the user can force a HS Status word with the FRAME bit set by writ
39. ample 1 TTRI 000 TDP 000 0005H 0001H TSR 0006H Example 2 Find the message with word defined by the Trigger Data 2 followed by the Nth word within the message defined by the Trigger Data 4 Then save the number of messages defined by the PTC register TTRI TTR2 TDP2 TPP2 m P2 TSR UM 10962 Rev C 0001H 0002H 0002H 0001H 0002H 0004H 0005H 0001H 0006H 63 3 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 by Trigger Data3 i e Trigger on a specific 32 bit word TTRI 000 TDPI 0004H TPP 0002H TFPI 0001 TTR2 0002H TDP2 0001H TPP2 0003H 2 0001H gt TTR3 0001H TDP3 0003H TPP3 0005H 0001H TTRA 0006H Example 4 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 Then selectively capture all messages with word defined by Trigger Data 3 followed by word within the message defined by Trigger Data 2 TTRI 0001H TDPI 0004H 0002H 0001H TTR2 0002H TDP2 000 TPP2 0003H TFP2 000 PTTR3 0004H TDP3 0003H TPP3 0004H TFP3 0003H gt 4 0005H TDR4 0002H TPP4 0005H 0003H LTSR 0006 UM 10962 Rev C 64 5 Find
40. at the 3910 message had a bit count error The following word in the stack will be 0000 for 3910 message with no Word Count error W bit clear If W bit is set this word will be a signed number defining the polarity 1 ve 1 ve The following words in the stack will be the received 3910 message as shown in table 6 5 Table 6 5 Stack Messages WORD No NAME 1 Frame Control Physical Address 2 Destination Address 3 Word Count 4 Data 5 Data 6 Data N 2 Data N 1 Data N FCS 6 5 1 Flow Diagram TRIGGER SETUP Base 46H Trigger STACK Set up Register PTCR SCCR SPR FPR etc UMI 10962 Rev C 68
41. bit access The counter can be updated and used by the on board processor as follows Used Data buffers time tagging Frame cycles control Bus Monitoring Updated User request 3838 command 2 6 3 Trigger In Features Trigger In enters the board logic through the front panel connector J1 and then an opto coupler Inputs to this feature can be used for hardware starts of the major and or minor frames or external trigger for the bus monitor See Figure 2 1 for details 2 6 4 Trigger Out Features Trigger Out is in fact a bit in a register accessible by the on board processor to indicate to the external world that an event has been detected This event can be as follows Beginning of major and or minor frames Beginning of a message Bus Monitor trigger detected Trigger Out exits the board through an opto coupler on the front panel connector J1 See Figure 2 1 UM 10862 Rev C 13 27 PCI INTERFACE 2 7 1 Introduction The PCI interface on the Western Avionics IIB 3910 PMC board conforms to PCI LOCAL BUS specification Rev 2 2 and supports 3 3V and 5V VCCIO signalling 2 7 2 Electrical Characteristics 5 and 12V only All driving and loading rules are respected 2 73 Capabilities The Western Avionics IIB 3910 PMC board is used as a 2Mbyte field R W Static RAM 2Mbyte Read only 32 bit counter one 32 bit access Write only 16 bit register one 16 bit access 2 8 3838 INTERFAC
42. ddress On HS mode commands without error Action word On HS mode commands with error OEXXH Action word XX RT number 5 6 2 Message Interrupts or set of messages interrupt One word code equals message interrupt code in data descriptor block The code is pushed in queue only if the message is correct Sets of Messages Same feature as for BC mode 5 6 3 Status Report Queue two words per report Code pushed into queue only if error on message and Interrupt on erroneous message not set in the DDB 1st Word 2nd Word BIT 15 IT 14 IT 13 IT 12 BIT 11 BIT 10 to BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 Pointer to the double word in look up table look up table address index Events Wrong Both Buses Error No Response Error RT Address Error TX Error Mn Lg Sh Py WC Late Response SYNC Type Error Not Used HS wordcount error polarity 1 Too many words HS Word Count Error HS FCS Error HS preamble bit count error HS manchester encoding error HS RI timeout HS bit count error The bits 15 to 11 are used for e Status Word and data if it s an LS message e Status Word if it s a transmitted HS message NOTE If an error is detected on an action word data following a receive command with HS sub address a report is pushed in the queue 1st Word 2nd Word UM 10962 Rev C Pointer to the LS look up table with index HS sub address LS error code on bits 15
43. ddress pointers for the Bus Monitor are 16 bit words defining a PAGE address Each page is 32 bytes Example If a message pointer contains the value 2301H this indicates an absolute address of BASE 2301H x 20H BASE 46020H 62 BASE REGISTERS Table 6 1 Base Registers BASE REGISTER 00H Control Register Write Clock HI Word Read 02H Clock LO Word Read LSB of clock 0 5 uS 04H Command Register CR 06H Status Register SR 08H to 20H Reserved 22H Transformer Direct Coupling Select Register 24H to 2AH Reserved 2CH HS Subaddress Register 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Reserved 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Reserved 3EH Reserved 40H Reserved 42H Current Address Register CAR 44H Trigger Occurrence Register TOR 46H Trigger Set up Pointer TSP UM 10862 Rew 52 6 2 1 Control Register Write 00H DIS 04 D12 DIO D08 D07 006 005 D04 002 DOI 0 0 0 0 0 0 0 HR 0 IRQ 0 0 0 1 C0 CO Clear gt Command Request Cl Clear gt Insertion Request HR Clear gt Hardware RESET If is set and IRQ is set then interrupt line will be cleared If is set and IRQ is clear then the interrupt line will be asserted for test purposes only If is clear the value of IRQ is unaffected
44. e 1 Trigger Mode The Selective 1 Trigger searches for a particular word as with the Single Trigger type However if the last word of a message is encountered before this trigger condition is met the message is not saved on the stack If this trigger condition is met it will branch to the trigger defined by the Pass Register Value 5 Selective 2 Trigger Mode This trigger type is the same as the Window Trigger with the following exceptions a If the specific word within the message is not found the message will not be stored on the stack and the next trigger is defined by the contents of the Fail Pointer Register b When the trigger condition is found the message is stored on the stack If the number of selective messages defined by the Selective Capture Count Register have not been stored the next trigger is defined by the contents of the Fail Pointer Register When the programmed number of messages have been stored the next trigger is defined by the Pass register Therefore the two selective capture triggers allow the storage of a specific message or messages Value 6 Post Trigger Count Mode This mode is used as a terminator to the trigger sequence This mode simply stores the number of messages defined by the Post Trigger Count Register on the stack and then stops activity If the PTC is set to H8000 storage will continue until the board is commanded to halt NOTES This trigger mode always resides in Trigger Stop Registe
45. e value 6 This register is the STOP trigger sequence register Trigger Data 1 Trigger Data 1 Bit Mask Register Base Address 2EH Base Address 30H This register will define the bits to be ignored in the trigger bit pattern for trigger data 1 Any bit set in this register will be masked from the trigger test condition Trigger Data 1 Bit Pattern Register This register will define the bit pattern required for trigger data 1 Trigger Data 1 Bus ID Word Type Mask This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Base Address 32H Base Address 34H Register D15 D14 D13 D12 D10 009 DO8 DOS D04 D02 DOI DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 1 Bus ID Word Type Register Base Address 36H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D10 009 DO8 DOS 004 D02 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Bot
46. ection Response time out selection Bus events detection mask storage and reporting bus errors status word bits Simultaneous MRT Simulation up to 31 Data Words Transfers Data buffer simulation for BC and simulated RT s Sub address based data buffer access with data descriptor blocks defining each message Multi buffering linked buffers frequency toggled buffers Interrupt queues Data status report Data buffer time tagging 32 bits time tag Simultaneous monitoring of all data buffers 1 3 3 Multiple Remote Terminal MRT Features Simulation Up to 31 3838 3910 RT simulations Mode and Broadcast commands handling Comprehensive Error Injection Data Words Transfers e Data buffer simulation for simulated RTs Sub address based data buffer access offering same powerful data buffering as in the bus controller mode e All non transmitted data messages are monitored 1 3 4 Chronological Bus Monitor CM Features UMI 10962 Rev C Capture of all bus activity in chronological stack with time tagging of each message Comprehensive multi trigger facilities allowing selective capture and interrupts to be performed on complex data sequence Cyclical stack up to 2Mbyte with interrupt on completion of capture 3838 3910 errors detected 14 3910 ARCHITECTURE The Western Avionics IIB 3910 PMC board is a memory mapped PMC 3838 3910 int
47. ed by the DDB b Transmit Last Command A DDB is analysed the data word transmitted is stored in the data buffer If the RT is simulated the last command word from the RT simulation table is transmitted c Transmit Bit Word Similar to transmit last command d Transmit Vector Word Similar the transmit last command and then if the RT is simulated service request bit in the RT status word is reset and the vector word is reset or updated with the next vector word in FIFO s if any UMI 10862 Rev C 249 45 INTERRUPT REQUESTS Three types of interrupt requests IRQ be generated by the Western Avionics IIB 3910 PMC board RQ L and IRQ H low priority and high priority are synchronisation interrupts defined as follows By instructions in the BC instruction list message descriptor block to report bus events detection In data descriptor block to signal the transmission of a message e IRQ M is a data message interrupt and occurs only when the transmission of a data buffer is correct and the requesting bit is set in the data descriptor block It can also be programmed to occur with the last message of a set of 2 to 16 messages set of messages option When setting an IRQ the Western Avionics IIB 3910 PMC board pushes a vector code into queues each code defines the event origin of the IRQ Each queue must start at an address multiple of 200H user must manage the reading poi
48. ene een renes 36 4 3 1 VEL IUIS wean OQ 37 4 3 2 Data Descriptor Block uuu in enina 37 4 3 3 Data Bul CUS eet Tt A 41 44 55 42 45 INTERRUPT REQUBESTS 43 4 5 1 Inierrupt Coding x dds Gusta PETRO ORI rae 43 4 5 2 Set Message INIerTUPtS RR 43 4 5 3 Message Status Report QUEM seit ect E E neun 44 5 MULTIPLE REMOTE TERMINAL MODE OF 44 44 5 nennen 45 INTRODUCTION 45 52 8 555 esine ieni e Eee eR ps 46 53 MODE COMMANDS 46 54 DATA WORDS STORAGE gt 9 exer tee e rte ED 46 5 5 LS ERROR INJECTION 46 5 5 1 Global RT Error Description Word RT Simulation 47 5 5 2 Message Error Injection Word Look up Table sse 48 36 INTERRUPTS CODING 55 50 5 6 1 Low High Priority Interrupts two word code
49. er error injection bit position in the data stream UM 10962 Rev C 40 4 3 2 10 Extended Sub Address To enable the extended sub address feature see the MDB type word When enabled the value of the DDB address in the look up table is in fact a pointer for a further look up table called the extended look up table The on board processor uses the 3838 byte of the first data word received multiplied by four to calculate an offset in the extended look up table to find the true DDB address word Therefore the DDB and data buffer used is defined by the value of the first 3838 RX data word Offset Reserved MRT 02H DDB address 4 3 3 Data Buffers Data buffers are pointed to by the buffer address word contained in the data descriptor blocks The address of the toggled buffer is calculated by adding the global toggle offset to the data buffer address value in the DDB The first two words of a data buffer are updated with the value of the local clock at the beginning of the message HS data buffers contain e The Time Tag e The three protocol words of the HS frame FC PA DA WC e The HS data words e The frame check sequence FCS for received data buffers For transmitting data buffers the FC and PA bytes are automatically updated by the micro controller LS data buffers can be stored as follows e The standard way data words behind the time tag words e A particular way allowing the user to store header words of the data message
50. erface with high performance architecture and complex features Plugged into a 3 3V or 5 PMC universal the IIB 3910 PMC card provides enhanced test and simulation functions for all modes of operation of a 3838 3910 bus The host equipment using the on board RAM defines all configuration and data structures Protocol UNIVERSAL Management 3838 1553B PCI INTERFACE 1553B Lines in out INTERFACE Unit ELECRICAL 3910 INTERFACE INTERFACE INTERRUPT Figure 1 1 IIB 3910 PMC Functional Block Diagram 15 PROTOCOL MANAGEMENT UNIT A micro controller based structure running at 40Mhz handles the management of the 3838 and 3910 protocol for each of the operating modes BC MRT BM The micro controller works each of the 3838 command status and data words functions of its operating mode and the configuration tables in RAM The micro controller directly drives word by word the 3838 interface and initiates the HS 3910 interface depending on the HS action word messages running on the 3838 lines micro controller management unit allows flexibility and expandability as well as for the bus control tasks as for the user interface 16 3838 INTERFACE The 3838 interface is a dual redundant interface which includes a standard dual redundant transceiver and a Manchester encoder decoder with full error detection and error injection capabilities which include Manchester bit error Synch bit error Parity error Word len
51. fset 15 bits MSB OFFSET 15 14 0 The 5th word in a DDB enables the toggle feature for the corresponding data buffer and the toggle frequency BIT 15 BIT 14 to 11 BIT 10 to 08 BIT 07 to 00 1 Enable toggle local 0 Frequency indicator gt 000 FHz 001 F 2Hz 011 F 4Hz 111 F 8Hz Buffer Address When global toggle is enabled for a data buffer if the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset 15 bits Buffer Address Low UM 10962 Rew C 38 DDB Buffer Bank A bit15 1 Buffer Address Offset Buffer Bank B The toggle 1s synchronised on the minor frame counter register which is incremented on each minor cycle restart The on board processor stores the data buffer in bank A or B depending on the number of the running minor cycle and the frequency indicator of the message Minor Cycle 0 1 2 3 4 5 6 7 8 9 B frequency F Hz B A A F 2 Hz B A F 4 Hz A B B F 8 Hz A A 4 3 2 4 Link Pointer to New DDB 0CH If the message is good or bit 10 of the option mask is clear and bit 9 of the option mask is set the value in this location will replace the origina
52. gth error Wrong bus error Both bus error Response time error UMI 10962 Rev C zR 17 HS3910 INTERFACE The HS 3910 interface includes clock recovery encoder decoder and HS frame control functions with error detection and error injection capabilities Preamble bit count error Word count error or Start End delimiter pattern error Bit count error Frame check sequence FCS error Manchester bit error HS transmitter initialisation time TI and HS receiver initialisation timeout RIout are programmable This 3910 interface drives either an on board non redundant HS electrical transceiver or external dual redundant HS fibre optic transceivers This interface is controlled by the micro controller but is directly connected by DMA to the RAM transfer the HS data words UM 10962 Rev C 9 18 FEATURES The features of the Western Avionics 3910 are listed as follows Universal PMC card Can be used in 3 3V or 5V slot Memory mapped real time PCI interface 2MByte of RAM Multiple interrupt queues for various events 3838 and 3910 data protocol managed by a micro controller providing complete flexibility and extension capability prEN 3715 compatible HS transceivers interface for either fibre optic or electrical transceivers Error Injection and detection External Triggers Internal Self tests 1 9 SYSTEM CHARACTERISTICS AND SPECIFICATIONS The characteristics and specifications of the Western Avionic
53. h Buses Trigger Data 1 Error Word Mask Register Base Address 38H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D10 009 DO8 DOS 004 D02 DO DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled UMI 10962 Rev C 59 Trigger Data 1 Error Word Register Base Address 3AH This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 D10 D08 D07 DOS 004 D02 DOO 0 o o Mn Lg sh o o 0 0 INR Sy 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Data 2 Trigger Data 2 Bit Mask Register Base Address 3CH This register will define the bits to be ignored in the trigger bit pattern for trigger data 2 Any bit set in this register will be masked from the trigger test condition Trigger Data 2 Bit Pattern Register Base Address 3EH This register will define the bit pattern required for trigger data 2 Trigger Data 2 Bus ID Word Type Mask Base Address
54. hing for the software trigger condition N 1 The Monitor will wait for a HI LO transition on the TRIG IN input before storing messages and searching for the software trigger condition 1 Monitor will generate a gt 1 5uS pulse on the TRIG OUT when the software trigger condition has been detected 1 The Monitor will generate a gt 1 5uS pulse the TRIG OUT when the post trigger message count has been reached 6 3 DETAILED TRIGGER DESCRIPTION The Bus Monitor has four triggers that can be set up to trigger on a wide variety of complex conditions Each trigger can be allocated one of four different data and error conditions Ifa trigger passes this condition it then moves on to the trigger defined by the Pass register If a trigger fails this condition it then moves on to the trigger defined by the Fail Register Each trigger is allocated a trigger type value from one to six and these are as follows Value 1 Value 2 Single Trigger Mode The Single Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register If this condition is TRUE for the incoming 3838 word the Single Trigger will branch to the trigger defined in the Pass Register If it fails it will branch to the trigger defined by the Fail Trigger Register Window Trigger The Window Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register within the first 3838 message it encounters If this condition is
55. ics 3910 and operating procedures necessary to run the card Section 4 Bus Controller Mode of Operation contains information on the mode of operation for the Bus Controller function of the Western Avionics IIB 3910 PMC card Section 5 Multiple Remote Terminal Mode of Operation contains information on the mode of operation for the Multiple Remote Terminal function of the Western Avionics 3910 PMC card Section 6 Chronological Bus Monitor Mode of Operation contains information on the mode of operation for the Chronological Bus Monitor function of the Western Avionics 3910 PMC card 13 CAPABILITIES The Western Avionics IIB 3910 PMC provides the following capabilities and functions 1 3 1 General Memory mapped real time universal PCI interface 2MByte of RAM INTA interrupt 3838 and 3910 data protocol managed by a micro controller providing flexibility extensibility Comprehensive Error Injection HS transceivers interface for either fibre optic or electrical transceivers External Triggers Internal Self tests Standard single PMC format UM 10962 Rew C 6 1 3 2 Bus Controller BC Features With MRT Simulation and Data Monitoring Bus Control Autonomous frame control using comprehensive set of instructions and message descriptor blocks Acyclic message insertion Error injection Frame frequency selection Inter message gap sel
56. igned offset XXXX INITF 000 XXXXH Initialise frame duration to XX XX LSB 1005 SWPSE 000 Wait for new on board start of frame HALT 0010H End of BC program SITL 0 XXXXH Set low priority IRQ Push XXXX on LO queue SITH 0012H XXXXH Set high priority IRQ Push XXXX on HI queue HWPSE 0013H wait for external Trig LO HI for new frame SMB 0014H XXXXH Send message XXXXH absolute address of MDB TRGOUT 0015H XXXXH Trig out to the XXXXH level e Instructions e 1 2 3 e By a NOPx the user can replace one two or three instruction words BSR BRA DNBE The offset is defined in bytes count always even offset BSR e 15 levels of subroutines available TRGOUT e Instructions to put TRIGOUT at 0 if xxxx 0000H or 1 if xxxx 0001 On power on the output is on 0 level per default e LOOP xxxx e Load loop counter with value XXXX Only one level of loop UMI 10962 Rev C 22 INITF Minor frame duration minor cycle time e 10 us for the LSB the value for 20ms is 7 e It must be initialised at the beginning of the background program e This instruction resets the minor frame counter register e SWPSE Software Pause e To be put at the end of each minor cycle instruction list with the minor frame duration utility to have automatic minor frame restart Examples INITF xxxx HWSPE waiting an external trig SWPSE JSR Minor
57. ill be the range 1 to 5 Trigger 3 Trigger 3 Type Register Base Address This register will define the trigger type allocated to trigger 3 This value will be the range 1 to 6 Trigger 3 Data Pointer Base Address 20H This register will define the trigger data allocated to trigger 3 This value will be the range 1 to 4 Trigger 3 Pass Pointer Base Address 22H This register will define the new trigger to be activated 1f this trigger condition passes This value will be the range 1 to 5 Trigger 3 Fail Pointer Base Address 24H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 4 Trigger 4 Type Register Base Address 26H This register will define the trigger type allocated to trigger 4 This value will be the range 1 to 6 Trigger 4 Data Pointer Base Address 28H This register will define the trigger data allocated to trigger 4 This value will be the range 1 to 4 Trigger 4 Pass Pointer Base Address 2AH This register will define the new trigger to be activated 1f this trigger condition passes This value will be the range 1 to 5 Trigger 4 Fail Pointer Base Address 2CH This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM 10962 Rev C 58 Trigger Stop Register This register will always be programmed to th
58. ing a zero value into this location 3 5 6 HS Last Action Automatically updated including broadcast So the 3910 TX command is correctly simulated 3 57 HS Bit Word For user purposes NOTES 1 3838 Mode Commands TX shutdown override TX shutdown fully simulated The status of the transmitters are available to the user in the Base Registers 2 3910 Mode Commands TX shutdown and override TX shutdown are fully simulated The status of the transmitters are available to the user in the Base Registers 3 The user modify the RTs simulation state in real time UM 10962 Rev C 29 4 BUS CONTROLLER MODE OPERATION 41 INTRODUCTION In the Bus Controller mode the Western Avionics IIB 3910 PMC board runs a list of instruction pointed to by the Background Running Pointer defining the bus frame Each bus message is defined by a Message Descriptor Block MDD and the associated data is accessed through a Look Up Table LUT and Data Descriptor Blocks DDB the same way as in the Multi Remote mode Remote Terminals can simultaneously be simulated All non simulated data buffers can be monitored An internal minor frame duration counter allows autonomous control of cycling frames Acrylic messages can be inserted on the host request Insertion instruction lists define sequences of messages to be inserted Refer to figure 4 1 the Bus Controller Organisation Diagram
59. isters are the starting points for a description of operation of any of the three modes of operation BC MRT and CM They are located starting at the board Base Address UM 10862 Rev C 16 115 3 29601 WIN jdnuoeju 1dnuojug MOT wejbeig b eunBi4 1ognq eq 0 Ssouppy eq suondo gt 11 i Pd t 511975 ad OT oOELA 1 eur T ssexppy aad s LLY Saadan VLVd sseuppy Jang eje q s t IH Ssoppy Jang eq uonoefur LIH t 3dnuoju 8 KA 1111 0166 t PH e LOT 0166 eye OT r n aee SSOIppV i teer T 11118686 Se uoroofur 2 4 suddind VLVd ee LA IH Ssouppy Ins qvlsru eed suondo 0 1 OT Sel out DIN ponoso 0 Sso1p
60. l DDB address in the look up table This feature defines a different DDB for the next occurrence of the same message 4 3 2 5 Address of Modify Word Value to Write QEH 10H After the message is complete and bit 8 of the option mask is set the Value to Write is written in the address defined by the contents of OEH Action is limited to the first 64K bytes of the memory 4 3 2 6 3910 Frame Timeout and RI TI Time Register 18H BIT 15 to 13 Set to 0 BIT 12 If this bit is set the HS data stream will have a ve word count error BIT 11 If this bit is set the HS data stream will have a ve word count error BIT 10 If this bit is set the HS data stream will not be transmitted HS no response BIT 09 to 08 Set to 0 BIT 07 to 00 TI time for 3910 TX gt time for 3910 data to start from end of BC action word LSB 108 RI time for 3910 RX gt time for RX timeout after end of BC action word LSB lus 10962 Rev C 39 4 3 2 7 3910 Errors Injection 1 1 This word defines the desired start and end delimiter patterns for transmissions as follows D15 014 D12 DIO 007 D06 005 004 002 DOI ED7 EDS EDA ED3 ED2 EDI EDO 507 506 505 SD4 SD3 8 2 SDI SDO SD7 0 defines the start delimiter pattern Each bit is a 50nS segment of the start delimiter starting with SD7 and ending with SDO ED7 0 defines the end delimiter pattern Each bit is a 50nS segment of the end delimi
61. lies to 3910 PMC units to top assembly number 1U10962G01 using PCB to P N 1U10963H03 and schematic drawing no 1U10964 Rev F The Western Avionics IIB 3910 PMC Intelligent Interface Board is a standard PMC card designed to meet the requirements of STANAG 3910 The Western Avionics IIB 3910 PMC provides a powerful and intelligent interface between PMC based host equipment and the STANAG 3910 high speed data bus Bus Controller and Multi Remote Terminal functions can operate both independently or simultaneously An additional independent Chronological Bus Monitor function is provided The Western Avionics IIB 3910 PMC provides complete and comprehensive test and simulation functions for both STANAG 3910 and STANAG 3838 MIL STD 1553B systems 12 MANUAL DESCRIPTION The following paragraphs provide a general description of the manual layout and content Section 1 General Information contains brief description of the manual and a general description of the Western Avionics IIB 3910 PMC This section also contains the architecture protocol management 3910 3838 interface information instrument specifications information concerning accessories furnished items and also safety precautions Section 2 Installation and Preparation for Use contains instructions installation preparation for use self test and reset of the Western Avionics IIB 3910 PMC card Section 3 Operation contains a functional description of the Western Avion
62. m 14 2 6 1 OUT DE 14 2 8 2 Electrical Characteristies se bere ee o d EH e E EE dad 14 29 INPUT OUTPUT CONNECTOR L iiti recette retener ebbe nite Rp enhn a 15 OPERATION rr H 16 3 1 INTRODUCTION 16 32 CONVENTIONS 16 3 3 ORGANISATION 16 34 ea ER eee e IRURE THE RIBUS OPE Ope reese 16 3 4 1 Base Register Names and Location sse eene 18 3 4 2 Base Resister DESCHIPLONS s ose e rece teo bestias ee eue been 19 3 5 REMOTE TERMINAL SIMULATION TABLE 1 ethernet nennen enne 28 3 5 1 Simulation Type Word siiis Ee deer E AEE RAEE 28 3 3 2 Slalu WOTA aie E EEEN NA 29 3 5 3 LS Last Command Word 29 3 5 4 LS Bit Word sesoto o d Ee 29 3 5 5 HS Status Word iure epe die do aede eps e La S 29 3 5 6 TIS LASA CHON ostiis ertet C dee E A Res 29 3 5 7 HS areae 29 10962 Rev C zd 4 BUS CONTROLLER MODE OF 004 0001 ennt 30 4l INTRODUCTION crit oe te Ce
63. nter and erase with a 0000H value the codes after reading 4 5 1 Interrupt Coding 1 LO and HI priority interrupts two words Messages without error 0800H DDB Address Messages with error 0 DDB Address BC Event without RETRY 1000H Status Queue Address BC Event with RETRY 4000H Status Queue Address Send Interrupt SITL SITH 2000 SITL SITH Vector 2 Message Interrupts one word Message Interrupt Code from DDB Only if Message is Good 4 5 2 Message Interrupts When in a DDB bit 12 of the option mask word is set e The 10th word gives a set of message numbers 00H to e The 12th word gives a message indicator e For each set the on board processor manages a set word register It makes OR with the message indicator in set word register Then if the set word register is equal to FFFFH on board processor sends message interrupt code defined in the 9th word of the DDB and resets the set word register It is possible to define sets from 2 to 16 messages The user initialises at 0 set of messages table The 256 word set of messages table is pointed to by the set of Messages Start Address 26H in Base registers UM 10962 Rev C 43 4 5 3 Message Status Report Queue At the end of a message if an event is detected and matches with the 3838 or 3910 Event Masks of the MDB a Message Status Report is pushed in to the Message Status Report queue 2 words
64. o Address of another DDB 0EH Address of Modify Word 10H Value to Write 12H Message Interrupt Code 14H Set of Message Number 16H Message Indicator in the Set of Messages 18H RT TI Time Register 1AH 3910 Error Injection 1 1CH 3910 Error Injection 2 1EH 3910 Error Injection 3 UMI 10962 Rev C 2375 4 3 2 1 Option Mask 00H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 09 BIT 08 BIT 07 BIT 06 BIT 05 BIT 04 to 00 1 Interrupt on Correct Message 1 Interrupt on Error Message 1 HI LO Priority Queue 0 LO 1 HI 1 Interrupt on Set of Messages 1 Message Interrupt If Message Correct 1 Link only on Correct Message 1 Link to New DDB Enabled 1 Modify Word Enabled 0 0 0 Header Word Count 4 3 2 2 Data Status Report 06H BIT 15 to 14 BIT 13 to 00 NOTE 00 Good Message 01 Message Running 10 Error Message Signed Wordcount Error 0 No Wordcount Error The wordcount error is calculated as follows 3838 TX Wordcount Command Wordcount DDB Count Header Count 3838 RX Wordcount Wordcount Received DDB Count Header Count 3910 TX Wordcount Action Wordcount DDB Count 3910 RX Wordcount Action Wordcount DDB Count 4 3 2 3 Toggle Frequency and Buffer Address HI 08H The word 24H in Base Registers defines if the data buffer toggle feature is enabled and also the toggle offset MSB 1 global toggle enabled 0 no toggle of
65. ompares this word count with real data word count transmitted on the bus and writes the difference if any in the data status report word This last word also contains the status flag of the transmission message received correct or with error message running The most significant byte of data buffer address can be used to enable toggled buffer control toggle on beginning of each minor frame or on multiple cycles of this minor frame This allows user software synchronised on the frame cycle to always access the correct buffer The set of message interrupt features provides the possibility to send an interrupt after the last message of the set of messages It is to be used when the frame sequence is not purely repetitive Up to 128 different sets of messages from 2 to 16 messages each can be defined Refer to table 4 2 A HS type data descriptor block also defines HS transmission characteristics HS frame time out LSB 100 nS RI or TI values LSB 115 HS error injection no response preamble bit count error word count error FCS error encoding error Bit count error start end delimiter pattern error Error injection on LS data words is defined in the message descriptor blocks Table 4 2 Data Descriptor Block DDB ADDRES OPTION MASK 02H Header Address 04H Data Word Count 06H Data Status Report 08H Toggle Frequency and Buffer Address HI 0AH Buffer Address LO 0CH Link Pointer t
66. option works in the same manner as the BC mode except that the minor cycle number is given by the data word associated to the mode command synchronise with data word This mode command is due to circulate on the bus at the beginning of each minor cycle and toggles bank A or B are managed when this message occurs Minor Cyc 0 1 2 3 4 5 6 7 8 9 frequency 1 2 A B A B 2 2 B 4 2 A 8 2 5 7 5 Programmable HS RI TI Time DDB When MRT mode these values have an offset of 18us For example if the user requires a TI time of 30us a value of 12 must be stored in the DDB word UM 10962 Rev C 51 6 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION 6 1 INTRODUCTION When acting in BC or MRT mode a comprehensive window monitor facility is provided However the Western Avionics 3910 can also act as a chronological monitor for bus event detection and message recording In this mode the Western Avionics 3910 can be set to trigger on specific events and sequentially record precise time stamped messages on a stack The size and position of this stack can be defined by the user NOTE When the Western Avionics IIB 3910 PMC is in this mode the BC MRT facility is not available All a
67. py sonond IH LNT 016 ne 5 aul dud OT Jayng 91901 f o aa UM ans WHISIOdH 107 8 1 t O T8 ou seul suond 4 IH Se oun 20 LAN 2 Joquinw 111 4551 3 4 1 Base Register Names and Location The names and locations of the Base Registers are contained in table 3 1 Table 3 1 Base Register Names and Locations BASE Control Register Write Clock HI Word Read 02H Clock LO Word Read only 04H Command Register CR 06H Status Register SR 08H Background Running Pointer BRP Address of Program 0AH Insertion Running Pointer IRP Address of Program 0CH Reserved 0EH Low Priority Interrupt Queue Start Address Pointer 10H Reserved 12H High Priority Interrupt Queue Start Address Pointer 14H Reserved 16H Message Interrupt Queue Start Address Pointer 18H Reserved Status Report Queue Start Address Pointer 1 Reserved 1EH RT Simulation Table Address Register RTSTAD 20H Amplitude Register 22H Coupling Register 24H Toggle Buffer Address Offset MSB 1 Global Enable 26H SET OF MESSAGES S
68. r CROP RO REN ERES ERI E 30 42 MESSAGE DESCRIPTOR BLOCK enne nennen nennen nenne 31 4 2 1 Message Number teet ere ee te the ph ngang sedia 31 4 2 2 LS Event Mask 02 H iia EOS euge Mu 31 4 2 3 Message Type Word 4H iei e o HERE 32 4 2 4 LS Message Error Phase Definition 06H sse eene 33 4 2 5 LS Message Error Description Word 6 290 eene 33 4 2 6 Addressin Look Up Table UAE aed eroe re er erint da ope ret eid ed 34 4 2 7 Command Word 1 OCB Lio iet qu d oed oni ete 34 4 2 8 Command Word 2 0 0 0 0000000000000000000000 34 4 2 9 Action Word I iude ttti itte 34 4 240 Action Word 2 12 34 4 2 11 Retry Subroutine Absolute Address 14H eene eene 34 4 212 nnne trennen nen E 35 4 2 15 Jntermmessage Gap Time 18H ete erre 35 4 214 HS RT RT Inter message Gap Time essere eene nennen 35 42 15 Status Word 1 ICH sie enden Iron Oen Ee REO D TORIO EO PEE T i 35 4216 Status Word 2 IEH e eet eret en ehe nce acetate deter Dae 35 43 DATA BUFFERS SIMULATION AND e
69. r and never in any other register This is trigger 5 and must always be pointed at as last part of the trigger sequence Trigger 1 Trigger 1 type Register Base Address 0 This register will define the trigger type allocated to trigger 1 This value will be in the range to 6 Trigger 1 Data Pointer Base Address This register will define the trigger data allocated to trigger 1 This value will be the range 1 to 4 Trigger 1 Pass Pointer Base Address 12H This register will define the new trigger to be activated 1f this trigger condition passes This value will be the range 1 to 5 Trigger 1 Fail Pointer Base Address 14H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM 10962 Rev C 57 Trigger 2 Trigger 2 Type Register Base Address 16H This register will define the trigger type allocated to trigger 2 This value will be the range 1 to 6 Trigger 2 Data Pointer Base Address 1 8H This register will define the trigger data allocated to trigger 2 This value will be the range 1 to 4 Trigger 2 Pass Pointer Base Address This register will define the new trigger to be activated 1f this trigger condition passes This value will be the range 1 to 5 Trigger 2 Fail Pointer Base Address HCH This register will define the new trigger to be activated if this trigger condition fails This value w
70. riptor includes A Message Error Description or Illegalization word A Data Descriptor Block Address or Extended sub address look up table address as for BC mode 53 MODE COMMANDS SPECIFICATIONS All illegal mode codes defined in the 3838 standard are automatically illegalized The error descriptor word allows illegalization of complementary mode codes Associated data words which are not obtained from the RT Simulation Tables can be obtained from or stored in memory using Data Descriptor Blocks For each mode code DDB can be used to define IRQ s HS mode commands are processed in accordance with STANAG 3910 The message identifier points 00 and 80H T R l in the HS look up table define two illegalization and DDB address word pairs for all HS mode commands This allows one of the mode types T R 0 or T R l to be illegalized if required The DDB allows the definition of common interrupt requests for all the HS mode commands 5 4 DATA WORDS STORAGE To avoid data buffers overwriting in memory when receiving a data message the IIB 3910 PMC board does not store more data words than the number defined by e Data Word Count if no header option or Data Word Count Header Word Count 1 if header option e Data Word Count for HS message Data Word Count is defined in DDB extra word for LS messages will be the last received word of a message in excess of the DDB data word count 55 LS ERROR INJECTIO
71. s IIB 3910 PMC are listed as follows UM 10962 Rew C Size Standard PMC card 148 by 74 mm Power 5Vdc 600 mAmps 12Vdc 160 mAmps Temperature Operating 0 C to 50 Non operating 20 to 70 C MTBF e 106 295 Hrs Ground Benign 25 10 110 LIST 0F FURNISHED ITEMS The following is a list of furnished items Bus Analyser Simulator Model IIB 3910 PMC 2 Users Manual UM 10962 This document 111 LIST 0F RELATED PUBLICATIONS The following is a list of related publications 1 MIL STD 1553 2 PCI LOCAL BUS specification 3 STANAG 3838 4 STANAG 3910 112 STORAGE DATA As the PC card contains electrostatic sensitive devices ESD s special storage and handling is required Do not store near electrostatic electromagnetic magnetic or radiation fields 113 TOOLS AND TEST EQUIPMENT No special tools or test equipment is required to test the Western Avionics IIB 3910 PMC 1 14 SAFETY PRECAUTIONS WARNING Potentially hazardous voltages exist on the host computer power supply Do not attempt to install or remove the Western Avionics ITB 3910 PMC without first removing mains power Improper handling can cause injury or death 10962 Rev C 11 2 INSTALLATION AND PREPARATION FOR USE 21 GENERAL On delivery inspect the unit for possible damage If it is damaged notify the shipping company and contact your distributor or Western Avionics for details of return procedure
72. sociated errors as follows UM 10962 Rev C 66 D15 D14 D13 D12 D11 DIO DOS 004 D02 DOO ED HS OV Py 15 156 70 BO NR TA 0 ED 1 Indicates last 3838 word in message HS 1 Indicates message has associated 3910 data Only set for last word OV 1 3910 DATA overlap Decoder still active for previous 3910 message Py 1 3838 data word had a Parity error Mn 1 3838 data word had a Manchester error Lg 1 3838 data word had too many bits Long Sh 1 3838 data word had too few bits Short T1 TO describe the 3838 word type as follows TO WORD TYPE 0 0 Command Word 0 1 Status Word 1 0 Data Word 1 1 RT RT Command Word WC 1 Indicates 3838 message had a word count error Only set for last word BO Describe the bus the 3838 word was captured on as follows BO BUSID 0 0 Illegal 0 1 Secondary 1 0 Primary 1 1 Both Buses NR 1 Indicates that a RT failed to respond to a command No Response Only set for last word 1 Indicates that the RT status word did not match the address of command word Terminal Address Error 1 Indicates that the 3838 word did not the correct SYNC type 6 4 4 Next Address Pointer This word will define the page address
73. tart Address 28H Global RT Response Time Register us 2AH RT No Response Timeout Register us 2CH HS Subaddress Register 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Minor Frame Counter Register 38H Load Clock Register 3AH Load Clock LO Register 3CH Test and Set register TASR 3EH Service Request Queue Address Pointer SRQADSP 40H Cycling Interrupt Update Register 42H Monitor Current Address Register CAR 44H Monitor Trigger Occurrence Register TOR 46H Monitor Trigger Set up Pointer TSP 48H PRI Bus 3838 RT TX inhibit bits 4AH PRI Bus 3838 RT TX inhibit bits LO 4CH SEC Bus 3838 RT TX inhibit bits 4EH SEC Bus 3838 RT TX inhibit bits LO 50H PRI Bus 3910 RT TX inhibit bits 52H PRI Bus 3910 RT TX inhibit bits LO 54H SEC Bus 3910 RT TX inhibit bits 56H SEC Bus 3910 RT TX inhibit bits LO UM 10862 Rev 18 3 4 0 Base Register Descriptions The Base Register functions are defined in the following paragraphs 3 4 2 1 Control Register Write 00H D15 014 D12 DIO D09 008 D07 D06 D05 004 002 DOI 0 0 0 0 0 0 0 HR 10 IEN IRQ 0 0 0 CO Clear gt Command Request Cl Clear gt Insertion Request
74. ter starting with ED7 and ending with EDO LIL J LI 1000 1 110 01 11 0001 SD ED As can be seen above for a good start and end delimiter this register should be set to 1000111001110001 0 8 71 Any other value will inject start end delimiter pattern errors 4 3 2 8 3910 Errors Injection 2 1CH This word defines further error injection features as follows D15 014 D12 DIO 007 D06 005 004 002 DOI 0 0 PRS PR4 PR2 PRI PRO 2 FCS ML 5 0 The value of this defines the number of preamble bits to transmit 1 63 BT3 0 The value if this defines the bit count error for the HS data stream Values 0001 1111 define the number of bits to remove from the data stream Hence 1111 will result in the data stream being short by 15 bits For no bit error this value should be set to 0000 FCS Ifthis bit is set an FCS error will be injected into the data stream the FCS word will be incorrect ML If a manchester encoding error is required in the data stream this bit will define the level for the bit ME If this bit is set a manchester error will be injected into the data stream of level ML The position of the manchester error is defined by a 17 bit count This bit is the MSB of this count The remainder of the count is defined in the following register 4 3 2 9 3910 Errors Injection 3 1EH This word is the remaining 16 bits of the manchest
75. the message with word defined by Trigger Data followed by the Nth word within that message which does not meet the conditions of Trigger Data 2 TTRI 000 TDP 000 0002H 000 PTTR2 0002H TDP2 0002H TPP2 000 n P2 0004H TSR 0006H UM 10962 Rev C 65 6 4 STACK DATA FORMAT When the Bus Monitor is commanded to start all messages will be stored before the trigger condition is met Therefore all pre trigger data is captured The first captured message will start at the address defined by the The STACK data will wraparound after the Finish Page Register value has been exceeded The format of the messages are shown in Start Page Register All following messages will start on an even PAGE boundary table 6 4 6 4 1 Table 6 4 Stack Data Format WORD No NAME 1 Previous Address Pointer 2 Time Stamp HI 3 Time Stamp LO 4 Data 5 Errors N 4 Data N 3 Errors N 2 RT Response Time 1 LSB 0 5 uS N 1 RT Response Time 2 LSB 0 5 uS N Next Address Pointer Previous Address Pointer The first word of each message will define the page address of the previous message The first message stored will set this pointer to 0000 6 4 2 These two locations are a 32 bit word defining the value of the 32 bit 0 5uS clock when the message started 6 4 3 Time Stamp HI LO Data These words describe the previous DATA word TYPE BUS ID and as
76. to 11 50 5 7 SPECIFIC FUNCTIONS 5 7 1 Data Message Reception Each data message not transmitted by the Western Avionics IIB 3910 PMC board may be stored The path to access the data buffer is given by the RT look up table for messages BC lt gt RT Except for RT gt RT messages even if the RTs are simulated or not the path to point to the data buffer is always given by the transmitting RT look up table but the receiving RT look up table must point to a false DDB Received status words from RTs not simulated on board are stored in the associated disabled RT SIM table If an external RT fails to respond a value of FFFFH will be stored in the SIM table 5 7 2 Reception of Mode Commands Data Words For each mode command with data word message if the data word is not transmitted by the board it must be stored RT simulated or not The path for storing the data word is given by the RT mode command look up table 573 Mode Command Synchronise with Data Word When receiving a broadcast mode command Synchronise with Data word the on board processor e Stores the data word value in the Cycling Interrupt Update Register in base registers and set the cycling IRQ e Accesses to DDB to store the data word in a buffer and time tag the data buffer e Uses the value of the data word which is for example the minor cycle number 0 to 7 to manage frequency toggling of the data buffers 5 7 4 Frequency Toggle The frequency toggle
77. ts the TASR b e Jfnot free waits until free 3 4 2 26 Reserved 46H 3 4 2 27 PRI SEC 3838 3910 RT TX Inhibit HI LO 48H 56H RT 30 RT17 6 LO RT15 RT14 0 enable the transmitter 1 disable the transmitter A bit set defines specific RT transmitter as inhibited e Initialisation by the user before cold start Disable enable by corresponding mode command messages The user modify the inhibit bits in real time The receive function of the simulated is never disabled UM 10862 Rev C 27 35 REMOTE TERMINAL SIMULATION TABLE For each RT 16 words are used to define and store information concerning RTs The pointer to this table RTSTAD must be a multiple of 20H RTSTAD RT30 m RT31 Broadcast Refer to table 4 4 00H Simulation Type word 02H RT Status Word 04H LS Last Command Word 06H LS Look up Table Address MRT Only 08H HS Look up Table Address MRT Only 0AH LS Mode Commands Look up table Address MRT Only 0CH Vector Word 0EH LS BIT Word 10H HS Status Word 12H HS Last Action Word 14H HS BIT Word 16H Global RT Error Descriptor Word MRT Only 18H Not Used 1AH Not Used 1CH Not Used 1EH Not Used 20H 1222 3COH 3E0H Only 3 words used Set all others to 0 Broadcast LS Look up T
78. ty the on board processor resets the service request bit and the vector word e Otherwise the on board processor reads the FIFO s and writes this next value the RT vector word High priority vector words are processed before low priority vector words UM 10962 Rev C 26 The following 4Kbyte block after the service request queue is reserved for the individual RT requesting FIFO s managed by the on board processor SRQADP aa UNE ELE SERVICE REQUEST QUEUE 003EH eee gt 0040H gt WEEEERERERERERERERERERERERERERERERERERERERENER FREE To enter a request the User Requesting Queue the user must manage the current writing pointer SRQADP Base Registers and control the words pointed at are clear if these words are non zero the queue is full Reaching the end of the queue the user must restart at the beginning of the queue If several user CPUs can enter requests at the same time it is necessary to share control of SRQADP using for example the TASR flag with a test and set instruction To enter a request a CPU must carry out the following procedure Test and set the TASR word MSB bit and a e I ffree the SRQADP is read to define the entry address in the queue e Ifthe entry location defined by the SRQADP are clear the two words may be entered in the queue If these words are non zero the queue is full e Increments the SRQADP if the end is reached reinitialise it to the beginning Rese
79. uired in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D10 009 D08 DOS D04 D02 DOI DOO 0 0 0 16 Sh 0 0 WC 0 0 NR TA Sy 0 Sy 1 Sync Type Error Sh 1 Short Word Error TA Terminal Address Error Lg 1 Long Word Error NR No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Data 3 Trigger Data 3 Bit Mask Register Base Address 48H This register will define the bits to be ignored in the trigger bit pattern for trigger data 3 Any bit set in this register will be masked from the trigger test condition Trigger Data 3 Bit Pattern Register Base Address 4AH This register will define the bit pattern required for trigger data 3 Trigger Data 3 Bus ID Word Type Mask Base Address 4CH This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D10 D09 DO8 DOS 004 D02 DO DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data
80. vent Mask HS Overlap 18H Inter message Gap Time 1AH HS RT RT Inter message Gap Time 1CH Status Word 1 received 1EH Status Word 2 for RT RT received 4 2 1 Message Number 00H The number of the message is used in Message Status Report to identify messages 4 2 2 15 Event Mask 02H A logical AND is carried out with the LS event mask and the detected bus events If the result is lt gt 0 a message status report will occur and a retry if selected BIT 15 Wrong Both bus error BIT 14 No response error BIT 13 RT address error BIT 12 Transmission error BIT 11 Wrong sync error Bit 10 to 00 Status bits of RX status word not including address bits NOTE Transmission error includes Manchester error Long or Short word error Parity error Word Count error and Late Response error UMI 10962 Rew C 31 423 Message Word 04H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 to 8 BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 NOTES 1 UM 10962 Rev C 1 3838 TX on PRI bus 1 3838 TX on SEC bus 0 0 11 10 09 08 0 0 0 0 3838 MODE WITHOUT DATA 0 0 O0 1 3838 MODE WITH DATA 0 0 1 0 3838 RT RT 0 0 1 1 3838 BC RT RT BC 0 3910 BC RT 0 1 0 3910 RT BC 0 1 1 0 3910 RT RT 0 1 1 1 3910 TX MESSAGE MODE CODE 0 0 0 0 3838 MODE WITHOUT DATA BROADCAST 1 0 0 1 3838 MODE WITH DATA BROADCAST 1 0 1 0 3838 RT RT BROADCAST 1 0 1 3838 BC RT BROADCAST 1 1 0 0 3
81. word 47 01 X D00 X 5 5 Message Error Injection Word Look up Table The following word defines the errors that can be injected into the message D15 014 D12 DIO 009 D07 106 005 004 002 DO T T T x x x x X X X X X 0 X X X TIT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error 0 status word I data word Y Y Y Y Y Y Y 0 0 0 0 0 00 Parity error 0 1 1 5 54 S3 52 51 SO Synchro Pattern Error B4 B3 B2 Bl BO Manchester Bit Error L4 L2 LI LO Word Length Error ODN TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TIT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 101 gt Illegal Command XXXXXXXXXXXXX 0000000000000 TIT 110 gt Extended Subaddress XXXXXXXXXXXXX 0000000000000 111 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 10962 Rev C 48 NOTES 1 UMI 10962 Rev C No error 5 000 WWWWWW 111111 LS errors injection on HS action words commands
82. ysical INTA interrupt will be generated when a push to the Low Priority Queue occurs 3 4 2 25 Test and Set Register and SRQADP 3CH These two words are used to automatically manage FIFO s of vector words for each simulated RT For simulated RTs the Service Request bit in the status word can be set and reset by the user The vector word can be initialised by the user After a Transmit Vector Word mode command message the on board processor automatically resets the service request bit and the vector word On the other hand a service request queue is defined to automatically queue words representing successive requests for the simulated RTs This service request queue is 3 words long starting at the initial address in the service request queue address pointer SRQADP For a request two words are set in the queue as follows l RT number 000000000RRRRRIX RT address X Priority BIT 1 1 2 Vector word Two different priorities are available X High priority X 1 Low priority Reading this FIFO the on board processor manages each RT two 32 word vector words FIFO s one per priority These vector words are then used by the RT simulation If an RT FIFO 15 not empty the on board processor reads it then writes the value in RT vector words RT Simulation Table and sets the service request bit in the status word If a Transmit Vector Word mode command message occurs the on board processor reads the RT FIFO s Ifemp

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