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ANI sr2, byte - Renesas Electronics

1. 6 3 3 Frequency measurement 634 Pulse width Measurement MOUS bacs 6 3 5 Programmable rectangular wave output 06 2 7 6 3 Timer event counter program examples 1 0 00 00000000000 CHAPTER 7 SERIAL INTERFACE 65 020000 0 40 7 1 Serial Interface Configuration 00 2 440 188 7 2 Serial Mode RegisSters to Ru XE s CERA EE ROO RR XR 7 2 1 Serial mode high register SMB eot re ve 4212 Seral mod low register SMU Ed low A ERR otv aa RR Td 7 2 3 Serial mode register 2 2 3202 7 3 Serial Interface 7 3 1 ASynchirongus Tode con apre cu need it lake hayden feum ended 7452 Synichronous iode mi ter ned a E e vus Rede ecd deut ae be a eed 7 3 3 VO interface ModE Jtr patcr iet gr atre eig ere anges 7 3 4 Example of serial interface program 22422 2 00002 0000000000100 eene CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS 2 2222 8 1 Analog Digital Converter Configuration eese
2. 91 6 8 Timer Event Counter Mode Register Setting Event Counter Mode 92 6 9 Event Counter Mode Operation Em 92 6 10 Timer Event Counter Mode Register Setting Frequency Measurement Mode 93 6 11 Frequency Measurement Mode Operation 2 2 12 2 2 2022222 222001010112 93 6 12 Timer Event Counter Mode Register Setting Pulse Width Measurement Mode 94 6 13 Pulse Width Measurement Mode Operation 222 22 99555 95 6 14 Timer Event Counter Output Mode Register Setting 2 222 22 9 95 6 15 Timer Event Counter Mode Register Setting Programmable Rectangular Wave Output n 96 6 16 Programmable Rectangular Wave Output Mode 96 6 17 Timer Event Counter Mode Register Setting Programmable Rectangular Wave Output ECNT Clear COO Output Reset 98 6 18 Port C Setting Programmable Rectangular Wave 98 6 19 Timer Event Counter Mode Register Setting Programmable Rectangular Wave Output EGNT Operation Setting 99 6 20 SINGIS PUSS att te tendente qued ulster 100 6 21 Port C Setting Single Pulse 101 6 22 Interrupt Mask
3. NN Serial clock Internal clock TO output 128 CHAPTER 7 SERIAL INTERFACE FUNCTIONS b Since the timer TO output is being used as the serial clock SCK setting of the timer count value and timer operation is performed As an oscillator frequency of 11 0592 MHz data transfer rate of 110 bps and clock rate of 16 are used here the count value is found from Table 7 1 or the following expression to be 262 _ fxx 24 fx Oscillator frequency Clock rate Data transfer rate 00 C Count value Since the count value is greater than 255 TIMERO and TIMER are cascaded 131 83H is set in timer register 2 02H in TM1 Since TIMERO and TIMER 1 are cascaded the timer mode register settings are as shown in Figure 7 12 Figure 7 12 Timer Mode Register Setting 7 6 5 4 3 2 1 0 TIMER1 match signal as timer F F input TIMERO count input 12 TIMERO count up TIMERO match signal as TIMER1 count input TIMER count up c Port C settings are performed as follows PCO as TxD pin PC1 as RxD pin PC7 as output port and PC7 set to output a high level signal 129 CHAPTER 7 SERIAL INTERFACE FUNCTIONS Figure 7 13 Port C Setting Serial Interface PCO set as TxD pin PC1 set as RxD pin PC7 set as input output port PC7 output latch 1
4. timer event counter To serial interface eu Remark 76 Internal bus fxxx 1 3 bxx 1 12 384 1 384 fxx Oscillator frequency MHz CHAPTER 5 TIMER FUNCTIONS 5 2 Timer Mode Register This is an 8 bit register which specifies the operating mode of the two interval timers TIMERO and TIMER1 and the timer F F Its configuration is shown in Figure 5 2 1 amp bits 0 amp 1 These bits perform timer F F reset specification and input clock specification The internal clock is obtained by dividing the oscillator frequency by 3 2 CK00 amp bits 2 amp 3 These bits specify the TIMERO input clock Internal clocks 12 and s84 are obtained by dividing the oscillator frequency by 12 and 384 respectively 3 TSO bit 4 TSO controls the operation of the TIMERO upcounter When TSO is 1 the upcounter is cleared to and the count up is stopped when changed from 1 to 0 the upcounter starts counting up from However if after this bit is set to and the count has begun 0 is written to the bit again the upcounter is not cleared and the count continues 4 CK10 amp CK11 bits 5 amp 6 These bits specify the TIMER input clock 5 TS1 bit 7 TS1 controls the operation of the 1 upcounter and operates in the same way as the 150 bit RESET input sets the timer mode
5. In this programming example the A D converter is set to the scan mode First four A D conversion operations are performed on pins ANO to AN3 and the ANO to AN3 conversion results are stored in areas 4000H to 4003H 4008H to 400BH 4010H to 4013H and 4018H to 401BH respectively Next four A D conversion operations are performed on pins AN4 to AN7 and the AN4 to conversion results are stored in areas 4020H to 4023H 4028H to 402BH 4030H to 4033H and 4038H to 403BH respectively Then conversion is performed again on pins ANO to AN3 and the ANO to AN3 conversion results are stored in areas 4004H to 4007H 400CH to 400FH 4014H to 4017H and 401CH to 401FH respectively Finally conversion is performed on pins AN4 to AN7 and the 4 to AN7 conversion results are stored in areas 4024H to 4027H 402CH to 402FH 4034H to 4037H and 403CH to 403FH respectively An example of a program which repeats the above operations show below First the operation flow for initialization is shown in the following flowchart 146 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNC lt a gt Set counter Be 3 Ce 1 lt b gt De Ee Set A D channel mode register sem Reset INTFAD d Set interrupt mask register ser a memory address for storing the A D conversion results is set in the HL register pair Here the setting is for storage of the conversion results in address 4000H onward b
6. 61 4 2 20200 65 7 to PCO cc 66 44 Port D IPD7 to PDO niet ete es 70 45 Port F PF7 to 222 2 2 1 1 2 4444 4 41 1 ADDED DR PR RR RR Passa saa P Da ses a asas 4s 71 4 6 Operation of Arithmetic and Logical Operation Instruction Involving a Port and immediate 2 2 Eines RENE RR YR RR YR scenes 73 CHAPTER 5 TIMER F NCGCTIONJS eee eraan parie Fio resa avete 75 5 1 Timer Config ratlOn errori rentre ruere PE 75 5 2 Timer Mode Register 0 00 0 77 5 3 Timer noe HE RR AR ANARA 79 CHAPTER 6 TIMER EVENT COUNTER 81 6 1 Timer Event Counter Configuration 4 4 81 62 Mode Registers oe Eee Ee 85 6 2 1 Timer event counter mode register 85 622 Timer event counter output mode register 88 6 3 Counter Operation 4 4 6 3 1 Interval timer mode 6 3 2 Event COWUMECK IMO utut
7. input count Free running cleared after full count External pulses input to the pin are synchronized with the internal clock and ECNT counts up on their falling edge The pulse width of the pulses input to the CI pin must be at least 500 ns at 12 MHz operation pulses of 250 ns or less in width are regarded as noise signals and are not counted The count value can be read at any time by software When the timer event counter mode register is set as shown in Figure 6 8 if ECNT counts up to FFFFH the OV Overflow flag is set and the count starts again from 0000H The OV flag does not have an interrupt function but can be tested in the program by means of a skip instruction SKIT or SKNIT When the external event count reaches the value set in 1 and internal interrupt INTEO INTE1 is generated Figure 6 9 Event Counter Mode Operation Internal clock Cl input Internal signal A ECNT input 92 CHAPTER 6 TIMER EVENT COUNTER FUNCTIO 6 3 3 Frequency measurement mode In this mode the frequency of the external pulses input to the pin is measured Since the external pulses in the period basic time during which the timer output TO is high are counted in this mode the timer needs to be started beforehand After first clearing ECNT the operation is started by setting the data shown in Figure 6 10 in the timer event counter mode registe
8. gooo 0000H On chip ROM 0004H 8192 x 8 bit 0008H INTTO INTT1 1FFFH 2000H 0010H INT1 INT2 External memory 57088 x 8 bit 0018H INTEO INTE1 0020H INTEIN INTAD FEFFH FFOOH ise e Note EA 5 0028H INTSR INTST E 0060H SOFT 0080H LOW ADRS 0081H HIGH ADRS 7 a 0082H LOW ADRS 2 t 1 S 0083H HIGH ADRS T LOW ADRS HIGH ADRS User s area 1FFFH Note Can only be used when the RAE bit of the MM register is 1 49 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 50 Figure 3 7 Memory Map uPD78C11A 0000H 0000H On chip ROM 0004H 4096 x 8 bit 0008H OFFFH 1000H 0010H External memory 61184 x 8 bit 0018H 0020H FEFFH FFOOH On chip 256 x 8 bit 0028H Standby area FFFFH 0060H 0080H 0081H 0082H 0083H Call table OOBEH OOBFH Note Can only be used when the RAE bit of the MM register is 1 1 2 INTEO INTE1 INTEIN INTAD INTSR INTST SOFTI LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS LOW ADRS t 31 HIGH ADRS User s area CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3 8 Memory Map uPD78C10A 0000H 0000H ss 0004H 0008
9. 3 INTERNAL BLOCK FUNCTIONS 3 2 Mode Registers Mode registers are provided see Table 3 1 to control the ports timers timer event counters serial interface A D converter and interrupt control blocks Table 3 1 Mode Register Functions Mode Register Name Function Mode A register Per orms bit wise input output speci ication for port A Mode B register Per orms bit wise input output speci ication for port B Mode control C register Per orms bit wise port control mode specification for port C Mode C register Per in p orms bit wise input output speci ort mode ication for port C when Memory mapping register Per orms port expansion mode spec ification for port D and port F Performs bit wise input output specification for port F when in port mode Mode F register Timer mode register Specifies timer operating mode Timer event counter mode Specifies timer event counter operating mode register Timer event counter output Controls COO and CO1 output level mode register Serial mode register Specifies serial interface operating mode Specifies interrupt request enable disable Interrupt mask register A D channel mode register Specifies A D converter operating mode Zero cross mode register Specifies zero cross detector operation 41 3 INTERNAL BLOCK FU
10. gt 2 Number of bytes 4 3 Number of states 20 14 4 Function word lt SPL word 1 lt SPH Stores the low order 8 bits SPL of the stack pointer in the memory addressed by the 3rd byte lower address and 4th byte upper address and stores the high order 8 bits in the next memory address 5 Flags affected gt SK 0 L1 0 10 0 244 CHAPTER 14 INSTRUCTION SET STEAX rpa3 Store EA to Memory addressed by Register Pair 1 Operation code O 1 0 0 1 0 0 0 1 0 01 63 C Ci Co 2 Number of bytes states The number of bytes and number of states are as shown below depending on the rpa3 specification Lm Her petu Hye Number of bytes Number of states 3 Function rpa3 lt EAL 1 lt Stores the contents of the low order 8 bits EAL of the extended accumulator the memory addressed by the register pair rpa3 DE HL DE HL DE byte HL A HL B HL EA HL byte specified by C3C2CiCo 2 to 5 B to F and stores the contents of the high order 8 bits EAH in the memory addressed by rpa3 1 If DE byte HL byte is specified as rpa3 memory is addressed by the result of adding the 3rd byte Data of the instruction to the contents of DE HL If HL A HL B or HL EA is specified the memory is addressed by the result of adding the contents of the register A B EA to t
11. LIST FIGURES 1 3 Figure No Title Page 3 1 Register Configuration 2 102220000060002 39 3 2 PSW ConfigulatiOH xao Bd 42 3 3 Memory Map 8 Cr 46 3 4 Memory iso tei eoa at e e oc 47 3 b Memory Map 78 14 78 144 2 1 100000000000 48 3 6 Memory IMap UPD78CT2A eaeque 49 3 7 Memory 50 3 8 Memory 978 2 51 3 9 Memory uPD78C18 Mode 2 42 1220 00000 000 53 3 10 Memory M p UPD78CT A Mode sr tette Hes 54 3 11 Memory Map uPD78C12A tapa eta eene et excede pe deno 55 3 12 Memory uPD786114A Mode ier etate etai nere Y Er cl eue A SERRE 56 3 13 Zero CrosS 58 3 14 Zero Cross Detection Signal i eei te eene ed i tus rale Pe tage 58 3 15 Zero Cross Mode Register oct nete Re pese UE tnn Pop evene EUR 59 4 61 4 2 Mode A REGISTER FOR
12. m N w VAREF 31 2 PIN FUNCTIONS 32 1 1 2 2 3 Type 4 Output data F Output disable CHAPTER 2 FUNCTIONS 4 4 tput dat Output data E P ch Mask option Output disable 4 N ch 77 5 5 Output data Type 4 O IN OUT Output disable Type 1 6 Type 5 A Output data Type 4 A O IN OUT Output disable Type 1 7 Type 7 AVop P ch 1 INO N ch Sampling 777 ANss AVss Reference voltage From voltage tap of series 1 resistance string 33 2 PIN FUNCTIONS 8 8 Output data Output disable Type 5 OIN OUT N ch N ch Type 2 MCC 9 Type 8 A Output data Output disable Type 5 A IN OUT N ch N ch Type 2 MCC 10 Type 9 Self bias circuit enable INO Type 1 Data 34 2 PIN FUNCTIONS 11 10 Output data Output disable Type 5 O IN OUT Self bias circuit enable 9 A MCC 12 Type 10 A Output data Output disable Type 5 A O IN OUT N ch Self bias circuit enable Type 9 t A MCC 35
13. ven Heb Number of bytes Number of states 3 Function EAL lt rpa3 lt rpa3 1 Loads the contents of the memory addressed by the register pairrpa3 DE HL DE DE byte HL A HL B HL EA HL byte specified by C3C2C1Co 2 to 5 B to F into the low order 8 bits EAL of the extended accumulator and loads the contents of the memory addressed by rpa3 1 into the high order 8 bits f DE byte or HL byte is specified as rpa3 the memory is addressed by the result of adding the 3rd byte Data of the instruction to the contents of DE HL f HL A HL B or HL EA is specified the memory is addressed by the result of adding the contents of the register A B EA to the contents of HL 4 Flags affected SK lt 0 11 lt 0 LO lt 0 248 CHAPTER 14 INSTRUCTION SET PUSH rp1 Push Register Pair on Stack lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt lt 6 gt Operation code 1 0 1 1 0 Q Qo Number of bytes 1 Number of states 13 4 Function SP 1 lt 1 SP 2 rptu SP lt 5 2 Saves the upper half V B D H EAH of the register pair rp1 VA BC DE HL or extended accumulator specified by Q201Qo 0 to 4 to the stack memory addressed by SP 1 and saves the lower half A L EAL to the stack memory addressed by SP 2 Flags affected i SK 0 L1 0 10 0 Example PROGRAM START LXI SP OE000H INTERRU
14. 2 FUNCTIONS 36 13 11 OIN OUT Output data N ch Type 1 IN O Type 7 Type 2 Edge detector 14 Type 12 15 Type 13 INO 1 NEN STOP mode P ch 77 77 CHAPTER 2 FUNCTIONS 2 4 Pin Mask Options uPD78C18 78C14A 78C12A 78C11A Only The following mask options are available for pins and these can be selected bit wise to suit the purpose PA7 to PAO 1 Pull up resistor incorporated PB7 to PBO 2 Pull up resistor not incorporated PC7 to PCO Caution If a pull up resistor is incorporated in the zero cross function cannot be operated correctly 2 5 Processing of Unused Pins Recommended Connection PAO to PA7 Connect to Vss or Vpp via a resistor PBO to PB7 PCO to PC7 PDO to PD7 PFO to PF7 RD Leave open WR ALE STOP INT1 Connect to Vss or Connect to VAREF Connect to Vss AVss ANO to AN7 Connect to AVss or 37 38 CHAPTER 3 INTERNAL BLOCK FUNCTIONS 3 1 Registers The central registers are the sixteen 8 bit registers four 16 bit registers and special registers shown in Figure 3 1 Figure 3 1 Register Configuration SP 15 0 7 07 0 V A es B H L 15 0 EA 7 07 0 ALT 1 Accumulator A 2 Sin
15. PA PB PC PD PF MK MB MC MF TXB TMO PA PB PC PD PF MK PA PB PC PD PF MK MKL ANM SMH SML EOM MM MCC MA TM1 ZCM MKL ANM SM MKL ANM SM EOM RXB CRO CR1 CR2 EOM ETMO ETM1 ECNT ECPT SP B D H V B D H EA SP B D EA H H D H D H H D H D H D H D byte H A H B H EA H byte D H D H D byte H A H B H EA H byte 8 bit immediate data 16 bit immediate data 8 bit immediate data 3 bit immediate data CY HC Z NMINote FTO FT1 F1 F2 FEO FEIN FAD FSR FST ER OV AN5 AN6 AN7 SB Note NMI can also be written as FNMI Remark 1 sr sr4 special register 2 rp rp3 register pair 4 f flag CARRY HALF CARRY STACK POINTER CY BC HC DE Z VA 5 EXTENDED ACCUMULATOR PORTA PORT B PORT C PORT D PORT F MODE A MODE B MODE C MODE CONTROL C MODE F MEMORY MAPPING MER REGO MER REG MER MODE TIMER EVENT OUNTER REGO MER EVENT OUNTER MER EVENT OUNTER UPCOUNTER MER EVENT COUNTER CAPTURE TIMER EVENT COUNTER MODE TIMER EVENT COUNTER OUTPUT MOD CHANNEL MOD A D CONVERSION RESULTO 3 Tx BUFFER Rx BUFFER SERIAL MODE High SERIAL MODE Low MASK High MASK Low ZERO CROSS
16. Instruction A byte r byte sr2 byte wa byte rp2 word r1 A r1 sr A sr r word word r2 r byte sr2 byte wa byte 1 byte Instruction sr2 byte wa byte A r wa rpa A byte r byte sr2 byte wa byte A byte r byte sr2 byte wa byte Instruction S SBB SBB SBBW wa SBBX rpa SBCD word SBI A byte SBI r byte SBI sr2 byte SDED word SHLD word SK SKIT SKN SKNIT SLL SLLC SLR SLRC SOFTI SSPD STAW STAX STEAX SIC STOP SUB SUB SUBNB SUBNB SUBNBW SUBNBX SUBW wa SUBX rpa SUI A byte SUI r byte SUI sr2 byte A byte r byte sr2 byte APPENDIX INDEX OF INSTRUCTIONS ALPHABETICA Instruction 355
17. 14 6 13 Call instructions CALL word Call subroutine direct 1 Operation code O 1 0 0 0 0 0 0 High address 2 Number of bytes 3 3 Number of states 16 10 4 Function 5 1 lt PC 315 8 5 2 lt PC 37 0 SP lt SP 2 lt word Stores the high order 8 bits the start address of the next instruction in the stack memory indicated by SP 1 and stores the low order 8 bits in the stack memory indicated by SP 2 then loads the immediate data in the 2nd byte into the low order 8 bits PC7 0 of the program counter and loads the immediate data in the 3rd byte into the high order 8 bits 15 and jumps to the address indicated by the immediate data 5 Flags affected lt 0 11 lt 0 10 lt 0 CALB Call subroutine BC indirect 1 Operation code O 1 1 0 0 0 2 Number of bytes 2 3 Number of states 17 8 4 Function SP 1 lt 215 SP 2 lt PC 27 0 SP lt 2 lt B PC7 0 lt Stores the high order 8 bits of the start address of the next instruction in the stack memory indicated by 5 1 and stores the low order 8 bits in the stack memory indicated by SP 2 then loads the B register into the high order 8 bits 15 of the program counter and loads the contents of the C register into the low order 8 bits PC7 0 and jumps to the address indicated by the BC register lt 5 gt Flags affected SK 0 L
18. port mode 256 bytes PD7 to PDO bytes to PFO PF7 to PF4 port mode expansion mode Expansion mode PD7 to PDO 16K bytes PF5 to PFO amp port mode expansion mode 48K 56K PD7 to PDO expansion mode 60K bytes PF7 to PFO Note Depending on setting of bits MM7 amp MM6 On chip RAM access Disable Enable Piggyback memory access Access to addresses 0000H to 3FFFH of EPROM located in upper pin section UPD78C14 mode Access to addresses 0000H to 1FFFH of above EPROM uPD78C12A mode Access to addresses 0000H to OFFFH of above EPROM u PD78C11A mode Setting prohibited 347 APPENDIX INTRODUCTION PIGGYBACK PRODUCT A 4 Interface with Figure 5 Connection to 27C256A u PD78CG14 27C256A Vop 1 Vop 28 Ao A13 Vss 27 Vss 22 CE 20 Vss 14 Caution When the uPD2764 27C64 27128 is used a high level signal must be input to pin 27 For this reason pin 27 only should not be inserted in the socket but should receive a high level input externally 348 APPENDIX DEVELOPMENT TOOLS The following development tools are available for system development using 87AD series products Language Processor 87AD series This program converts a program written in mnemonics into object code which can be relocatable assembler executed by
19. 106 CHAPTER 7 SERIAL INTERFACE FUNCTIONS The uPD78C18 is equipped with a serial interface which allows distributed processing and the connection of various kinds of terminals This serial interface has three operation modes asynchronous mode synchronous mode and O interface mode 7 1 Serial Interface Configuration As shown in Figure 7 1 the serial interface consists of three pins the serial data input RxD serial data output TxD and serial clock input output SCK a transmission unit and reception unit each equipped with an 8 bit serial register a buffer register and transmission reception control and a mode register which specifies the operation mode Figure 7 1 Serial Interface Configuration Internal bus Receive INTSR register Serial register S P Reception control PC1 RxD O Transmit buffer register TXB Serial mode register Serial register gt 5 Transmission control PC2 SCK 0 4 PCO TxD O 8 24 384 TO output INTST lt Remark 24 fxx x al 24 384 xx fc Oscillator frequency MHz 107 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 1 Transmission unit 2 3 a b Serial register P gt S This register converts parallel data transferred from the transmit buffer register into serial data and transmits it from
20. PC7 output port When SCK of the LPD78C18 is output off chip SCK is input from off chip the PC2 pin can be used as the SCK input output pin by setting the MCC register d The bit of the serial mode high register SMH is set 1 enabling transmission Figure 7 14 Serial Mode High Register SMH Setting Serial Interface Transmission Enable 7 6 5 4 3 2 1 0 qp Previous status Transmission enable Previous status 130 CHAPTER 7 SERIAL INTERFACE FUNCTIONS The initialization program is shown below INTERFACE INITIALIZATION SINIT MV SMH 00H MV A OFEH MOV SML A MV A 83 MOV TMO A MV A 02 MOV 1 MV TMM 61H MV A 07H MOV MCC A ORI PC 80H MVI A 00H MOV A ORI SMH 04H 2 uPD78C18 data transmission D Internal serial clock TO x 16 even parity 8 bit character 2 stop bit a Set serial mode Set timer register Baud rate 110 bps Set timer mode amp start Set port C mode control TxD RxD SCK available PC7 output latch 1 Initialize port C Port C output mode Transmit enable T 5 lt b gt JD lt c gt d The following example shows a subroutine which performs on byte transmission of the accumulator A contents as serial data In this example operation by means of an interrupt INTST is not used and serial data transmission is per
21. lt Skip if no carry Adds the immediate data in the 2nd byte to the contents of the accumulator and stores the result in the accumulator Skips if no carry is generated as a result of the addition lt 5 gt Flags affected Z SK L1 lt 0 LO lt 0 CY 6 Example ADINC A lt ADINC byte Add Immediate to Register Skip if No Carry 1 Operation code O 1 1 1 O 1 0 0 0 0 1 0 0 R2 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function lt r byte Skip if no carry Adds the immediate data in the 3rd byte to the contents of the register r V A B C D E H L specified by R2R Ro 0 to 7 and stores the result in the specified register Skips if no carry is generated as a result of the addition lt 5 gt Flags affected Z SK HC L1 lt 0 LO lt 0 CY lt 6 gt Example To add immediate data to the HL register pair ADINC L IMM L L IMM SKIP IF NO CARRY ADI H 01H He H 1 ADINC sr2 byte Add Immediate with Special Register Skip if No Carry 1 Operation code O 1 1 O 1 0 0 Ss 0 1 0 0 52 Si So 2 Number of bytes 3 3 Number of states 20 11 4 Function sr2 lt sr2 byte Skip if no carry Adds the immediate data in the 3rd byte to the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and stores the result
22. 1 Operation code O 1 1 0 0 0 0 1 1 0 1 1 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if zero Obtains the logical product of the contents of the accumulator and the contents of the register r V A B C D E L specified by R2RiRo 0 to 7 Skips if the logical product is zero 5 Flags affected 5 1 lt 0 0 0 262 CHAPTER 14 INSTRUCTION SET 14 6 4 8 bit operation instructions Memory ADDX rpa Add Memory addressed by Register Pair to A 1 Operation code O 1 1 1 0 0 0 0 1 1 0 0 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function A Adds the contents of the memory addressed by the register pair DE HL DE HL DE specified by A2A 1Ao 1 to 7 to the contents of the accumulator and stores the result in the accumulator 5 Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY lt 6 gt MOV 4000 amp 4000H LXI H 4200H HL lt 4200H ADDX H A lt A HL This example adds together the contents of address 4000H and address 4200H ADCX rpa Add Memory addressed by Register Pair to A with Carry 1 Operation code O 1 1 1 0 0 0 0 1 1 0 1 0 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function lt A rpa CY Adds the contents of the memory addressed by th
23. 3 Number of states 8 8 4 Function lt Obtains the logical product of the contents of the register V A B C D E H L specified by R2RiRo 0 to 7 and the contents of the accumulator and stores the result in the specified register 5 Flags affected Z 5 lt 0 1 lt 0 10 0 6 Example HAA Or Register with 1 Operation code O 1 1 0 0 0 0 1 0 O 1 1 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function lt Avr Obtains the logical sum of the contents of the accumulator and the contents of the register V A B D E H L specified by R2R1Ro 0 to 7 and stores the result in the accumulator 5 Flags affected ZSK 0 L1 0 L0 0 6 Example A 257 CHAPTER 14 INSTRUCTION SET ORA r A Or A with Register 1 Operation code 0 1 1 0 0 0 0 0 0 0 1 1 R2 Ri Ro lt 2 gt Number of bytes 2 lt 3 gt Number of states 8 8 lt 4 gt Function B lt Obtains the logical sum of the contents of the register V A B C D H L specified by R2R 1Ro 0 to 7 and the contents of the accumulator and stores the result in the specified register 5 Flags affected 2 5 lt 0 1 lt 0 10 0 6 Example ORA lt Exclusive Or Register with 1 Operation code
24. 4 gt 5 gt 6 gt and the A D conversion value of each input is stored in the order gt 1 gt 2 gt When the conversion values have been stored in all four CR registers CRO to CR3 an INTAD internal interrupt is generated 142 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNC The A D converter continues A D conversion again from ANO or AN4 irrespective of whether or not an interrupt request has been acknowledged and stores the A D conversion results in order starting with CRO This operation continues until the A D channel mode register is changed This mode allows A D conversion of four analog inputs with a minimum of software Internal interrupts are disabled by setting 1 the MKAD bit of the interrupt mask register MKH Figure 8 4 Outline of A D Converter Operation Timing in Scan Mode ANO or AN4 AN1 or AN2 AN3 or ANO or AN4 conversion conversion conversion conversion operation operation operation operation Nem y 4 Sampling Sampling Sampling Y ANM register Conversion Conversion Conversion Conversion write result write result write result write result write to CRO register to CR1 register to CR3 register to CRO register Y INTFAD flag setting 8 3 2 Select mode In the select mode as shown in Figure 8 5 the A D channel mode register ANM specifies one of the analog inputs ANO to AN7 Figure 8 5 A D Channel Mode Regist
25. 4K byte mode Access to addresses 0000H to OFFFH uPD78C11A mode e 8K byte mode Access to addresses 0000H to 1FFFH uPD78C12A mode e 16K byte mode Access to addresses 0000H to 3FFFH uPD78C14 mode 32K byte modeNete Access to addresses 0000H to 7FFFH uPD78C18 mode Note The 32K byte mode applies to the uPD78CP18 only The configuration of the uPD78CP18 78C14 memory mapping registers is shown in Figures 12 1 and 12 2 1 Bits MMO to MM2 These bits control the PD7 to PDO port expansion mode and input output specification and the PF7 to PFO address output specification See 11 1 1 Memory mapping register MM for details 2 MM3 bit RAE This bit controls enabling RAE 1 and disabling RAE 0 of on chip RAM accesses See 11 1 1 Memory mapping register MM for details 3 Bits MM5 to MM7 These bits used to specify the on chip EPROM access range When STOP or RESET is input these bits are reset The uPD78CP18 is set to the 32K byte mode and the 78 14 to the 16K byte mode These bits valid only in the uPD78CP18 78CP14 78CG14Nete f data is written to these bits in the uPD78C14 78C12A 78C114 it is ignored by the CPU Therefore programs developed on the uPD78CP18 78CP14 78CG14 can be transferred directly to mask ROM Note The uPD78CG14 is described in APPENDIX A INTRODUCTION TO PIGGYBACK PRODUCT 203 CHAPTER 12 PROM ACCESSES uPD78CP18 78CP14 ONLY Figure 12 1 Memory Mapping
26. OE PB7 Vit 209 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS uPD78CP18 78 13 3 PROM Reading Procedure PROM contents can be read onto the external data bus O7 to OO using the following procedure EN Connect unused pins to GND with a pull down resistor N Supply 5 V to the Vpp and VPP pins Input address of data to be read to pins A14 through AO Read mode Output data to pins O7 to OO gi The timing for 2 to 5 above is shown in Figure 13 2 Figure 13 2 PROM Read Timing A14 10 PF6 2 A8 PFO CE PB6 OE PB7 210 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS uPD78CI 13 4 Erasure Procedure Ceramic Package Products Only The programmed data contents of the uPD78CP18DW 78CP18KB 78CP14DW 78CP14KB 78CP14R can be erased by exposure to ultraviolet radiation through the window in the top of the package Erasure is possible using ultraviolet light with a wavelength of approximately 250 nm The exposure required for complete erasure is 15 W s cm UV intensity x erasure time Using a commercially available UV lamp 254 nm wavelength 12 mW cm intensity erasure takes approximately 15 to 20 minutes Cautions 1 Program contents may also be erased by extended exposure to direct sunlight or fluorescent light The contents should therefore be protected by masking the window in the top of the package with light shielding cover film 2 Erasure should normally be carried
27. On chip 1024 x 8 bit 0028H INTSR INTST Standby area FFFFH 0060H SOFT 0080H LOW ADRS 0081H HIGH ADRS 7 a 0082 LOW ADRS t 1 0083H HIGH ADRS 55 O OOBEH LOW ADRS OOBFH HIGH ADRS User s area 7FFFH Note Can only be used when the RAE bit of the MM register is 1 53 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 54 Figure 3 10 Memory Map uPD78C14 Mode 0000H 0000H On chip EPROM 0004H 16384 x 8 bit 0008H 4000H 0010H External memory 48896 x 8 bit 0018H 0020H FEFFH FFOOH On chip 256 x 8 bit 8 0028H S WY FFFFH 0060H 0080H 0081H 0082H 0083H Call table OOBEH OOBFH Note only be used when the RAE bit of the MM register is 1 INTTO INTT1 INT1 INT2 INTEO INTE1 INTEIN INTAD INTSR INTST SOFTI LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS LOW ADRS 31 HIGH ADRS User s area CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3 11 Memory Map uPD78C12A Mode 0000H 0000H On chip EPROM 0004H 8192 x 8 bit 0008H INTTO INTT1 1FFFH 2000H 0010H 2 External memory 57088 x 8 bit 0018H INTEO INTE1 002
28. Table 6 3 ECNT Clearing ECNT Input No relation ECNT Clearing Stop after clearing Free running not cleared Internal clock 12 CI input falling edge 12 while Cl input is high TO falling edgeNete input while TO is high No relation Match of ECNT ETM1 Note The TO signal cannot be used when timer F F input is used as internal clock see Figure 5 1 Timer Block Diagram When iv is specified in the clear mode the clear operation is performed after the capture operation 7 Interrupt control circuit This circuit controls timer event counter interrupts Interrupt sources are shown below an interrupt request flag is set 1 by each source i ECNT ETMO match signal INTEO ii ECNT ETM1 match signal INTE1 iii Cl input falling edge or TO falling edge INTEIN In case iii the setting is as shown in Table 6 4 according to the ECNT input as in case ii of item 6 Clear control circuit Table 6 4 INTEIN Interrupt Request Flag Setting ECNT Input Internal clock 12 12 while input is high Interrupt Request Flag Setting CI input falling edge CI inputNete 1 input while TO is highNete 1 Notes 1 Falling edge input 2 The TO signal cannot be used wh TO falling edgeNote 2 en timer F F input is used as internal clock see Figure 5 1 Timer Block
29. bit is or when the serial register contains no data to be transmitted the TxD pin assumes the mark status 1 Transmit data is transmitted on the falling edge of SCK from the TxD pin with a clock rate of serial clock x 1 _1 orx data transfer rate in transmission is set as shown in Table 7 2 according SCK and the clock rate at 15 MHz operation Caution When TxE changes from 0 to 1 transmission enabled while the transmit buffer register is empty INTST is generated Table 7 2 Maximum Data Transfer Rate at Transmission Internal Clock External Clock Clock Rate SCK Data Transfer Rate SCK Data Transfer Rate 625 kHz 625 kbps 1 25 MHz 1 25 Mbps 2 5 MHz 156 kbps 2 5 MHz 156 kbps 39 1 kbps 39 1 kbps Data reception A receive operation is enabled by setting 1 the RxE bit of the serial mode high register SMH The start bit is confirmed by detecting a low level RxD input and then detecting the low level again after a 1 2 bit time This is effective in preventing errors due to noise in the mark state Reception is performed by sampling the center of the subsequent character bits parity bit and stop bit Remark 1 2 bit timer for each clock rate is as follows x1 1 2 SCK clock pulse x 16 8 5 SCK clock pulse x 64 32 5 SCK clock pulse 119 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 120 When the prescribed data is input from the RxD pin to the serial register data i
30. gt gt gt e gt 2 lt gt 2 gt gt gt D oer or 9j monmu r ODOC er OOH gt gt 2 H p 70 dlo o oc o djooooooo c c c oooocooo oococooc cloo ooc c diOoooooooooooooo ooooo diloooo lO oOooooocooooooooooooooooooo c 7 N rp gt GI N 2 irloo o _ E lt o gt m ocru o o gGio o o alo o o g ejo T e e gt E E ow q ay a OT ui 2 lo o o dlo diooooc 215 CHAPTER 14 INSTRUCTION SET 14 3 Instruction Address Addressing The instruction address is determined by the contents of the program counter PC and is normally incremented by one for each byte automatically according to the number of instruction bytes fetched each time an instruction is executed However when an instruction associated with a branch is executed the jump address information is loaded into the PC in accordance with the addressing methods shown below and a jump is performed 14 3 1 Register addressing The contents of the B
31. our customers Old Company Name in Catalogs and Other Documents On April 1 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NC S AS 10 11 12 Notice information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise i
32. 1 Operation code O 1 1 0 1 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Function i V wa byte Skip if no zero Subtracts the immediate data in the 3rd byte from the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and skips if the result of the subtraction is not zero V wa zbyte b Flags affected Z SK HC L1 e 0 LO 0 CY EOIW wa byte Equal Immediate with Working Register 1 Operation code O 1 1 1 0 1 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Function V wa byte Skip if zero Subtracts the immediate data in the 3rd byte from the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and skips if the result of the subtraction is zero V wa byte 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY ONIW wa byte On Test Immediate with Working Register 1 Operation code O 1 0 0 1 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Function V wa A byte Skip if no zero Obtains the logical product of the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and the immediate data in the 3rd byte and skips if the result is not zero lt
33. 4 4 Port D PD7 to PDO uPD78C18 78C14 78C14A 78C12A 78C11A 78CP18 78CP14 Port D is an 8 bit special input output port in addition to functioning as a general purpose input output port port mode this port also functions as a multiplexed address data bus Port expansion mode can be specified for port D as a byte unit by means of the memory mapping register see Table 4 1 Table 4 1 Operation of PD7 to PDO uPD78C18 78C14 78C14A 78C12A 78C11A 78CP 18 78CP 14 P MM2 MM1 0 0 MM2 MM1 0 0 PD7 to PDO Port mode Expansion mode Port D is set to port mode when the MM2 and MM1 bits of the memory mapping register are reset 0 and to expansion mode in all other cases see 11 1 1 Memory mapping register MM 70 1 2 Port mode Port D is an 8 bit input output port which has input output buffer and output latch functions in the same way as port A except that input or output port setting is performed as a byte 8 bit unit Port D can be set as input or output as a byte unit by the MMO bit of the memory mapping register It functions as an input port when the bit is reset 0 and as an output port when the bit is set 1 Except for having input output specified as a byte unit port D operation is the same as for port A Direct bit setting resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator and data transfer to from an accumulat
34. After execution 0001010 RLL r2 Rotate Logical Left Register 1 Operation code O 1 0 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function r2m 1 lt 2 r20 lt CY CY lt 127 7 0 8 Performs 1 bit left rotation including the CY of the contents of the register r2 B C specified by RiRo 1 to 3 b Flags affected SK 0 L1 0 LO 0 CY 307 CHAPTER 14 INSTRUCTION SET RLR r2 Rotate Logical Right Register 1 Operation code O 1 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function r2m 1 lt 12m r27 lt CY lt 120 7 0 2 Performs 1 bit right rotation including the CY flag of the contents of the register r2 A specified by R1Ro 1 to 3 b Flags affected SK 0 L1 0 10 lt 0 CY SLL r2 Shift Logical Left Register 1 Operation code O 1 0 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function r2m 1 lt 12m r20 lt 0 lt 127 7 0 Performs 1 bit left shift of the contents of the register r2 A B C specified by RiRo 1 to 3 r27 is shifted into the CY flag and 0 is loaded into r2o lt 5 gt Flags affected SK amp 0 L1 amp 0 LO lt 0 CY 308 CHAPTER 14 INSTRUCTION SET SLR r2 Shift Logical Right Register 1 Operation code O 1 0
35. Expanded ROM RAM capacity On chip pull up resistor LPD78C14A Mask option we uPD78CP14 PROM uPD78C14 g product Expanded capacit 5 TO On chip pull up 5 resistor 2 Mask option On chip pull up uPD78C11 resistor uPD78C11A Note LPD78C10 Mask option LPD78C10A ROM less product ROM less product CMOS process on chip pull up resistors Mask option LPD7811H HPD7810H ROM less product Time of product release Note 4PD78C10 78C11 are maintenance products TABLE CONTENTS CHAPTER 1 GENERAL DESCRIPTION 1 1 a yx E RR ERERPEERRR GREEN R RR RERO 1 2 Ordering Information and Quality 24 2 1 1 2 1 Ordering eR 12 2 Quality GLA Se pee nee ur eres a Een qo 1 3 Pin Configurations Top 1 3 1 shrink DIP QUIP straight 37 1 3 2 OEBPUTB SBE WOEN 2329 COP AB Byte Baste a ne b e s Ud 1 3 4 1 4 BIOCK DET INEO 1 5 Functional Comparison of 87AD Series CMOS 1 6 Differences between 87AD
36. Input Output Function 8 bit input output port with input output specifiable bit wise PB7 to PBO Port B 8 bit input output port with input output specifiable bit wise PCO TxD O output PC1 RxD O input PC2 SCK PC3 INT2 T O input input O output O input PC6 COO PC7 CO1 I O output Port C 8 bit input output port with input output specifiable bit wise Transmit data Serial data output pin Receive data Serial data input pin Serial clock Serial clock input output pin Output when internal clock is used input when external clock is used Interrupt request timer input Edge triggered falling edge maskable interrupt input pin or timer external clock input pin can also be used as AC input zero cross detection pin Timer output Square wave is output with timer count time or one internal clock cycle as one half cycle Counter input Input pin for external pulses to timer event counter Counter output 0 amp 1 Rectangular wave output programmable by timer event counter PD7 to PDO AD7 to ADO Port D 8 bit input output port with input output specifiable bit wise Address data bus Functions as multiplexed address data bus when external memory is used to PFO AB15 to AB8 340 O output Port F 8 bit input output port with input output specifiable bit w
37. interface mode Disable Enable Disable Enable 111 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 7 2 2 Serial mode low register SML The individual bits of the serial mode low register are used to specify the operating mode as shown below The configuration of this register is shown in Figure 7 3 1 2 3 4 5 112 B1 amp B2 bits 0 amp 1 These bits determine asynchronous mode and synchronous operation switching and the data rate in the synchronous mode In the asynchronous mode the serial clock is divided by the clock rate specified by these bits and used for data transfer For synchronous operation the B1 and B2 bits are set to 00 L1 amp L2 bits 2 amp 3 These bits specify the number of bits comprising a character PEN bit 4 This bit determines whether odd even parity is added to the transfer data and whether an odd even parity check is made on the transfer data When the PEN bit is set 1 a parity bit is added to each character before transmission and a parity check is performed during reception if a parity error is generated the error flag is set When the PEN bit is reset 0 parity addition and checking is not performed EP bit 5 This bit controls whether odd or even parity is used Even parity is used when the EP bit is set 1 and odd parity when reset 0 The EP bit is only valid when the PEN bit is set 1 S1 amp S2 bits 6 amp 7 These bits
38. 0 L0 0 SKIT irf Skip if Interrupt 1 Operation code O 1 1 0 0 0 O 1 0 4 lz lt 10 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if irf 1 then reset irf Skips if the interrupt request flag or test flag NMI FTO FT1 F1 F2 FEO 1 FEIN FAD FSR FST ER OV ANA AN5 AN6 AN7 SB specified by 141312110 O to C 10 to 14 is set to 1 then resets the checked interrupt request flag The NMI flag is not affected 5 Flags affected SK L1 0 10 0 SKNIT irf Skip if No Interrupt 1 Operation code O 1 1 0 O 1 1 k gt kh 10 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if irf 0 Skips if the interrupt request flag or test flag NMI FTO FT1 F1 F2 FEO 1 FEIN FAD FSR FST ER OV AN5 AN6 AN7 SB specified by 1413121110 0 to C 10 to 14 is set 0 If the checked interrupt request flag is 1 that interrupt request flag is reset The NMI flag is not affected 5 Flags affected SK L1 0 10 0 322 CHAPTER 14 INSTRUCTION SET 14 6 16 CPU control instructions NOP No Operation 1 Operation code 0 0 0 0 0 2 Number of bytes 1 3 Number of states 4 4 4 Function Expends 4 states without performing any operation b Flags affected SK lt 0 11 lt 0 10 0 El Enable Interrupt lt 1 gt Operation code 1 0 2 dO
39. 2 1 O Vpop O VPP 007 Oo O6 905 004 003 02 Open 2 1 68 67 6665 64 63 62 61 A70 0 60 201 11 59 o O0 2 58 lt 2 gt 254 3 57 O 2 14 56 OA13 5 55 OA12 Lo 16 54 11 CEO 17 53 10 OEO 8 52 lt 2 gt 19 51 OA8 DA o 49 lt 2 gt 48 OJ Open 47 O lt 1 gt 46 O Open S lt 2 gt 4 45 44 O 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 U QUO Q Or Q VOY OAL A lt uju v O v Oo V gt gt Cautions Open Leave open 1 Connect directly to Vss 2 Pull down individually to Vss potential via a resistor 17 8L 16 15 PF7 0 X10 se 15 8 T n PCO TxDO PC2 SCKO B 25 0 Program memory Depends on product NMI oc INTI Data INT control Note memory Depends PC7 0 on product PC3 INT2J TI PCA TOO Internal data bus 7 0 16 16 PC5 Clo Timer event E PC6 CO0 o counter 8 PC7 CO1 INST REG PA7 0 AN7 0 INST decoder AVssO converter Note Can only be used when the RAE bit of the MM register is 1 when 0 external memory is de 5 required RD WR ALE MODE RESET STOP Vss
40. 2 Number of bytes 3 3 Number of states 14 11 4 Function amp Ax V wa Obtains the exclusive logical sum of the contents of the accumulator land the contents the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits and stores the result in the accumulator 5 Flags affected Z 5 lt 0 1 lt 0 0 0 GTAW wa Greater Than Working Register 1 Operation code O 1 1 1 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function A V wa 1 Skip if no borrow Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits and 1 from the contents of the accumulator Skips if no borrow is generated as a result of the subtraction A V wa 5 Flags affected Z SK L1 lt 0 LO lt 0 CY 288 CHAPTER 14 INSTRUCTION SET LTAW wa Less Than Working Register 1 Operation code O 1 1 1 0 1 0 0 lt 2 gt Number of bytes 3 lt 3 gt Number of states 14 11 lt 4 gt Function A V wa Skip if borrow Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits from the contents of the accumulator Skips if a borrow is generated as a result of the subtraction A V wa b Flag
41. 32 byte data of 256 byte on chip RAM retained at low supply voltage 3 2 V HLT instruction states 12 11 HALT mode CPU operation Stopped M3 T2 cycle repetition ALE Low level High level Self bias control of zero cross detector Self bias control possible by ZCM register specification Self bias control not possible NMI RESET noise elimination method By analog delay By clock sampling converter Operation stoppable Vaner pin manipulation Operation not stoppable RD WR ALE Operation during reset PD PF ROM less products High impedance High level Output 0 output to pin specified by address bus Remainder are high impedance Power Operating 65 mW 15 MHz Note 1 750 mW Typ consumption Standby 5 uW Typ 4 8 mW Typ PackageNote 2 64 pin plastic shrink DIP 64 pin plastic QUIP straight 64 pin plastic QUIP 64 plastic bent leads 68 pin plastic 64 pin plastic shrink DIP 64 pin plastic QUIP straight 64 pin plastic QUIP Pin connection except amp OFJ Notes 1 Voo 64 64 STOP 63 Voo pin 63 80 mW 15 on the uPD78C18 78C17 78C14 78C144A 2 Correspondence between pin connection and pin number depends on the type of package Caution There also differences in electrical specificatio
42. Flags affected SK lt 0 11 lt 0 LO lt 0 b Example LXI D 4000H DE lt 4000H STAX D 4000H lt DE lt 4001H STAX D 10H 4011H A DE 4001H This example stores A in addresses 4000H and 4011H 239 CHAPTER 14 INSTRUCTION SET LDAX rpa2 Load A with Memory addressed by Register Pair 1 Operation code 0 1 0 1 2 Number of bytes states The number of bytes and number of states are as shown below depending on the rpa2 specification Le Number of bytes Number of states 3 Function A e 2 Loads the contents of the memory addressed by the register pair rpa2 DE DE HL DE HL DE byte HL A HL B HL EA HL byte specified by AsA2A1Ao 1 to 7 B F into the accumulator If auto increment auto decrement is specified the contents of the register pair DE or HL are automatically incremented or decremented by 1 after the accumulator has been loaded If DE byte or HL byte is specified as rpa2 the memory is addressed by the result of adding the 2nd byte Data of the instruction to the contents of DE HL If HL A HL B or HL EA is specified the memory is addressed by the result of adding the contents of the register A B EA to the contents of HL 4 Flags affected SK lt 0 11 lt 0 10 lt 0 b Example LXI H 4000H HL lt 4000H MVI B 20H B lt 20H LDAX A lt 4020H This
43. Operation code JO 1 1 1 0 0 0 0 1 1 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function i r byte 1 Skip if no borrow Subtracts the immediate data in the 3rd byte and 1 from the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 Skip if no borrow is generated as a result of the subtraction r gt byte b Flags affected Z SK HC L1 e 0 LO 0 CY GTI sr2 byte Greater Than Immediate 1 Operation code 0 1 1 0 S 0 1 0 1 52 Si So lt 2 gt Number of bytes 3 3 Number of states 14 11 4 Function 5 sr2 byte 1 Skip if no borrow Subtracts the immediate data in the 3rd byte and 1 from the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH TMM specified by 53525150 0 to 5 to 9 B D Skips if no borrow is generated as a result of the subtraction sr2 gt byte 5 Flags affected Z SK L1 lt 0 10 lt 0 CY 279 CHAPTER 14 INSTRUCTION SET LTI A byte Less Than Immediate 1 Operation code 0 0 1 1 0 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function 3 A byte Skip if borrow Subtracts the immediate data in the 2nd byte from the contents of the accumulator Skips if a borrow is generated as a result of the subtraction A lt byte 5 Flags affected Z SK L1 lt 0 LO lt 0 CY LTI r byte Less Than I
44. Operation code 0 1 0 0 0 1 1 0 If 79H is used as byte the instruction is written as shown below ADI A 79H lt A 79H The corresponding operation code is shown below Operation code 0 1 0 0 0 1 1 O 229 CHAPTER 14 INSTRUCTION SET 14 4 11 Extended immediate addressing This addressing method has 2 byte operand data for manipulation in the operation code Extended immediate addressing is used when an instruction with the following operand format is executed Notation Description Method word Label numeric value up to 16 bits Example 1 LXI rp2 word Operation code P2 Pi Po 0 1 0 High byte If HL is used as rp2 and 3F54H as word the instruction is written as shown below LXI 3F54H HL lt 3F54H The corresponding operation code is shown below Operation code 0 0 1 1 0 1 0 230 CHAPTER 14 INSTRUCTION SET 14 4 12 Direct addressing With this addressing method the memory to be manipulated is addressed using the immediate data in the instruction as the operand address Direct addressing is used when an instruction with the following operand format is executed Notation Description Method word Label numeric value up to 16 bits Example 1 MOV r word Operation code O 1 1 1 0 0 0 0 If the B register is used as r and EEFFH as word the instruction is written as shown below MOV B OEEFFH The corresponding operation code is shown below Operation code 0 231 CHAPTER 14 INS
45. changed to a different mode Table 2 2 Operation of PF7 to PFO uPD78C18 78C14 78C14A 78C12A 78C11A 78CP18 78CP14 External Address Space Up to 256 bytes Up to 4K bytes Up to 16K bytes Up to 31K 48K 56K 60K bytesNete Note 31K uPD78C18 48K uPD78C14 78C144 56K uPD78C12A 60K uPD78C11A The operation of the uPD78CP18 and 78CP14 differ depending on the setting of bits MM5 to MM7 of the memory mapping register In the reset state RESET input low or in the hardware STOP mode STOP input low pins PF7 to PFO become high impedance When the RESET input or STOP input subsequently returns to the high level they are set as address bus or port according to the status of the MODE1 and MODEO pins 26 CHAPTER 2 PIN FUNCTIONS uPD78C17 78C10A These pins can be specified as an address bus AB15 to AB8 corresponding to the size of the externally installed device by means of the MODEO and pin settings and the remaining pins can be used as general purpose input output ports see Table 2 3 Table 2 3 Operation of to PFO uPD78C17 78C10A External Address Space AB11 AB10 bytes AB11 AB10 16K bytes Setting prohibit AB11 AB10 63K 64K bytesNote Note 63K uPD78C17 64K uPD78C10A In the reset state RESET input low or in the hardware STOP mode STOP input low pins PF7 to PFO become high impedan
46. urejBeiq 12014 NOlLdlHOS3G 1VH3N3O9 L H3ldVHO 6L uPD78C10A uPD78C11A uPD78C12A uPD78C14 uPD78C14A Instructions 159 Minimum instruction 0 8 us at 15 MHz operation execution time On chip ROM x 8 bits 8K x 8 bits 16K x 8 bits On chip RAM 256 x 8 bits Interrupts External 3 Internal 8 Timer counter 8 bit timer x 2 16 bit timer event counter x 1 converter 8 bit x 8 channels Serial interface UART full duplex clocked linesNote 32 44 Package 64 pin plastic shrink 64 pin plastic shrink DIP 750 mil 64 pin plastic OFP DIP 750 mil e 64 pin plastic QFP 14 x 20 mm 14 x 14 mm 64 pin plastic OFP 64 pin plastic QUIP 14 x 20 mm 64 pin plastic QUIP straight 64 pin plastic QUIP 68 pin plastic OFJ 68 pin plastic OFJ sjonpoJd SOIND seues 8 uosueduio to be continued NOILdIlHOS3Q 1VH3N3O 1 H3ldVHO Note Incorporation of pull up resistors be specified by mask option for port A and port C of the 78 11 78 12 0c Product Instructions uPD78CP14 uPD78CG14 uPD78C17 uPD78C18 159 uPD78CP18 Minimum instruction execution time 0 8 us at 15 MHz operation On chip ROM 16K x 8 bits PROM 16K x 8 bits piggyback ROM less 32K x 8 bits 32K x 8 bits PROM On chip RAM 256 x 8 bits 1K x 8 bits
47. 0 0 0 0 0 0 O 1 2 Number of bytes 2 3 Number of states 10 7 4 Function lt V wa Loads the contents of the working register addressed by the V register specifying the high order 8 bits of the memory address and the 2nd byte specifying the low order 8 bits into the accumulator lt 5 gt Flags affected i lt 0 11 lt 0 10 lt 0 238 CHAPTER 14 INSTRUCTION SET STAX rpa2 Store A to Memory addressed by Register Pair 1 Operation code 0 1 1 1 Ao 2 Number of bytes states The number of bytes and number of states are as shown below depending on the rpa2 specification o_o 0 Number of bytes Number of states 3 Function 3 2 lt A Stores the accumulator contents in the memory addressed by the register pair rpa2 BC DE HL DE HL DE HL DE byte HL A HL B HL EA HL byte specified by AsA2A1Ao 1 to 7 B to F If auto increment auto decrement is specified the contents of the register pair DE or HL are automatically incremented or decremented by 1 after the accumulator contents have been stored If DE byte or HL byte is specified as rpa2 the memory is addressed by the result of adding the 2nd byte Data of the instruction to the contents of DE HL If HL A HL B or HL EA is specified the memory is addressed by the result of adding the contents of the register A B EA to the contents of HL 4
48. 00 ECNT is cleared to 0000H and counting up is not performed When the EMO and bits are set to any value other than 00 ECNT counts up using the input clock ECNT is cleared by the conditions shown in Figure 6 2 after which the count starts again from 0000H When 0 and EM1 1 the conditions for clearing ECNT are as follows according to the input clock specification e When ET1 0 and 0 or ET1 0 and 1 ECNT is cleared by the falling edge of the Cl input see 6 3 4 Pulse width measurement mode e When ET1 1 ETO 0 or 1 1 and 1 ECNT is cleared by the falling edge of the TO input see 6 3 3 Frequency measurement mode 000 amp bits 4 amp 5 These bits specify the timing for transfer to the output latch of the level of the LVO level F F shown in Figure 6 3 When CO00 0 and CO01 1 the LVO level is transferred to the output latch in the event of either a match between ECNT and or a fall of the input When 00 1 and 01 1 the level is transferred in the event of a match between ECNT ETMO or a match between ECNT ETM1 When the LDO bit of the timer event counter output mode register EOM is set 1 the LVO level is inverted after transfer to the output latch 85 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 86 4 CO10 amp CO11 bits 6 amp 7 In a similar way to the 00 and COO bits these bits specify the timing for tra
49. 1 Operation code O 1 0 0 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function 1 EAn 1 lt EAn lt CY CY lt 15 Performs 1 bit left rotation including the CY flag of the contents of the extended accumulator b Flags affected SK 0 L1 0 LO lt 0 CY 310 CHAPTER 14 INSTRUCTION SET DRLR EA Rotate Logical Right EA 1 Operation code 0 1 0 0 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function EAn 1 lt EAn EAis lt CY CY lt EAo 15 0 MM Performs 1 bit right rotation including the CY flag of the contents of the extended accumulator 5 Flags affected SKe 0 L1 lt 0 LO lt 0 CY DSLL EA Shift Logical Left EA 1 Operation code O 1 0 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function EAn 1 lt EAn lt 0 lt 15 15 0 Performs 1 bit left shift of the contents of the extended accumulator EA sis shifted into the CY flag and 0 is loaded into EAo b Flags affected gt SKe 0 L1 0 10 lt 0 CY 311 CHAPTER 14 INSTRUCTION SET DSLR EA Shift Logical Right EA 1 Operation code O 1 0 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function EAn 1 lt EAn EAis lt 0 CY lt EAo 15 0 Performs a 1 bit right shift of the contents of the e
50. 1 Release by RESET signal When the RESET signal changes from the high to low level in the software STOP mode the software STOP mode is released and clock oscillation starts as soon as the reset state is set When the RESET signal is driven high after oscillation has stabilized the CPU starts program execution at address 0 When the RESET signal changes from the high to low level clock oscillation starts but it takes time for oscillation to stabilize The RESET signal low level width must therefore be longer than the oscillation stabilization time When the RESET signal is input the RAM contents are retained but the contents of other registers are indeterminate Figure 10 4 Software STOP Mode Release Timing RESET Signal Input Execution of address 0 CPU instruction operation OSC If the software STOP mode is released by the RESET signal program execution starts at address 0 as the case of a normal power on reset The SB Standby flag can be used to identify the program execution mode The SB flag is set 1 when the Voo pin rises from the specified low level or below to the specified high level or above and is reset 0 by executing a skip instruction Thus testing the SB flag using a skip instruction in the program executed after RESET input makes it possible to differentiate between a power on start and a start due to release of the software STOP mode see Figure 10 5 A set 1 SB flag indi
51. 10 0 305 CHAPTER 14 INSTRUCTION SET 14 6 11 Rotation shift instructions RLD Rotate Left Digit 1 Operation code O 1 0 1 0 0 0 0 0 1 1 1 0 0 0 2 Number of bytes 2 3 Number of states 17 8 4 Function lt HL 74 HL 7 4 lt HL HL a o lt y 43 0 7 43 0 Performs left rotation as 4 bit digit units of the low order 4 bits of the accumulator and the high order 4 bits and low order 4 bits of the memory addressed by the HL register pair Bits 7 to 4 of the accumulator are not affected b Flags affected SK 0 L1 lt 0 10 lt 0 6 Example A HL 7 4 3 0 7 4 3 0 Before execution 0 0 0 000 0 1 01010011 7 4 3 0 7 4 3 0 1 After execution 306 CHAPTER 14 INSTRUCTION SET RRD Rotate Right Digit 1 Operation code 0 1 1 0 0 0 2 Number of bytes 2 3 Number of states 17 8 4 Function lt Aa HL 2o lt HL 7 4 lt HL 3 0 7 43 0 7 43 0 Performs right rotation as 4 bit digit units of the low order 4 bits of the accumulator and the high order 4 bits and low order 4 bits of the memory addressed by the HL register pair Bits 7 to 4 of the accumulator are not affected b Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example A HL 7 4 3 0 7 4 3 0 Before execution 0 0 0 00001 010 1 0011 7 4 3 0 7 4 3 0
52. 13 3 PROM Reading Procedure etre renta 210 13 4 Erasure Procedure Ceramic Package Products 211 13 5 One Time PROM Products Screening eese eene nnne 211 CHAPTER 14 INSTRUCTION SET aues ko ERR y 213 14 1 Operand Notation and Description 2 24 2 411 2 213 14 2 Explanation of Operation Code 2 442 1 215 14 3 Instruction Address 4 90 216 14 37 ead 216 1433 2 Immediate addressing s i 217 143 2 Dire t addresSsSiNg ned naia 218 14234 R lative addressirigi sere rre erret Sedat ra Gema ede 218 143 5 Extended relative GddreSSinG ie ctossteu ci tret eene ce peret boire ocaecat 219 14 4 Operand Address 220 TEAS Register Ad ChESSING bb agri LEE p HER 220 14 4 2 Register indirect addressing 222 1443 Auto increment addiesslirigiiu oae 223 14 4 4
53. 78 1 2212 2 2020220000 000000000 197 11 10 MM R gister Format 4PD78C 17 78 C 10A acea etes trade rati qure sut tet V Ded rae dec gal 199 11 11 uPD78C17 Address SACS citans Fen tip urb Dodo edic od 199 11 12 HuPD79CT0A Address Space iiti emt eterne xen Rede dre dra SEHR TES 200 1 13 OP Code Fetch reprint irren egeret sue 202 11 14 External DevicecRead e cedat 202 1 15 External Device Witte TIMING aui inca Fede bonds ces noA 202 2 Memory Mapping Register Format 78 18 204 12 2 Memory Mapping Register Format 78 14 205 13 1 PROM Wiite Verity te 209 3 2 PROM Read atts 210 5 Analog Inp t Circuit Block DidQram eher dex eere E 331 15 2 When Both NMI STOP Are tectae 332 5 3 Control Timing of NMI and STOP eterne 333 15 4 When Both NMikand STOP Are Used ate cette desse tete etd eet toda 334 5 5 Control Timing f RESET and STOP crx ta tesi nsa sue
54. 78C12A Standards 78C14 Standards and E 78C14A 78CG14 Details Ifthe hardware STOP mode is executed not in synchronization with the CPU operation power supply current consumption may become approximately 20 mA even after entering the hardware STOP mode Remedy Use any of the following signals in combination with the STOP input then use the JR instruction to synchronize the hardware STOP mode with the CPU operation NMI 1 When both NMI and STOP are used As shown in Figure 15 2 input the power off detect signal to the NMI pin as an non maskable interrupt request then input the delayed signal thus obtained to the STOP pin as the hardware STOP mode setting signal Figure 15 2 When Both NMI and STOP Are Used 87AD Series Power off NMI signal R STOP C 332 CHAPTER 15 OPERATING PRECAUTIONS The operation sequence is as follows a When the power off detect signal is input the NMI routine starts b Then JR instruction is executed as the start of NMI routine the program is looped to wait STOP Determine values of R and C so that the delay of STOP behind NMI is longer than the longest interrupt wait period 75 states 10 us 28 75 us at 12 MHz operation Figure 15 3 Control Timing of and STOP pe NMI routine Instruction execution 5 Vi Hardware STOP mode When executing the power off processing before execu
55. Example A B A B 1 A skip is performed if A is greater than B Greater Than 1 Operation code O 1 1 0 0 0 0 0 0 1 0 1 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function r A 1 lt Skip if no borrow Subtracts the contents of the accumulator and 1 from the contents of the register r V A B C D E H L specified by R2R Ro 0 to 7 Skips if no borrow is generated as a result of the subtraction gt lt 5 gt Flags affected Z SK HC L1 0 LO lt 0 CY 6 Example GTA B A B A 1 A skip is performed if B is greater than A 259 CHAPTER 14 INSTRUCTION SET Less Than Register 1 Operation code O 1 1 0 0 0 0 1 O 1 1 1 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if borrow Subtracts the contents of the register V A B C D E H L specified by R2R Ro 0 to 7 from the contents of the accumulator Skips if a borrow is generated as a result of the subtraction A r 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6 Example 5 A L A L A skip is performed if A is less than the L register A Less Than 1 Operation code 0 1 1 0 0 0 0 0 0 1 1 1 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function i Skip if borrow Subtracts the contents of the accumulator fro
56. General registers B C D and E are used as counters to enable the A D conversion results to be stored in the specified memory The B register is used to check that A D conversion has been performed four times for pins ANO to AN3 or pins ANA to AN7 Therefore 03H is set in the B register The C D and E register are stored in the respective memory areas and 01 is set in each c A D channel mode register is set to specify the scan mode and ANO to as the input pins Figure 8 9 A D Channel Mode Register Settings 7 6 5 4 3 2 1 0 Scan mode Pins ANO to AN3 Oscillator frequency 9 MHz 147 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS d The A D channel mode register is cleared to 00H when a reset is performed and A D conversion is performed on pins ANO to AN3 in the scan mode The conversion values are stored in register CRO to CR3 anditis possible that the interrupt request flag INTFAD may be set 1 Therefore the interrupt request flag is reset 0 by a skip operation before setting the MKAD bit of the interrupt mask register MKH to 0 and releasing masking e The MKAD bit of the interrupt mask register MKH is reset 0 releasing masking of INTAD internal interrupts The A D converter initialization routine is shown below SF A D CONVERTER INITIALIZATION ADIN LXI H 4000 Set data pointer a LXI B 0301H Set counter
57. MODE irf interrupt flag E L L E byte L A L B L EA L byte OVERFLOW ANALOG INPUT 4 7 STANDBY 214 INSTRUCTION SET CHAPTER 14 14 2 Explanation of Operation Code Symbols rpa m o gt a D oO LL o f n g 2g Soon lt gt gt lt gt gt 9 mui 9 o 2 OR 5 Se a sae Ble bk gt gt 2222 OW ou u iu Z LL LL LL LL LL LL LL iL uj O o OQOLTALTALALIICIC SOLIOLIOQOLILIILI 2 4o o lo o o oc Glo o o oc 49 OO e OC e HK OO O e e 4Iloo ioo oosc Or eo 4loooo o 2Sloooooooo c c c c ooooo 4loooooooo c c c c SOloooo c l3lo0o0oooooooooooc c c c g E go d gt lt gt PEZmoaura aN Tee cn gt gt Tz 5 jo o o oc B ui KC BEoo ooc c a 5 gt gt e N D T 5 9 Q gt o
58. PD7 to PDO Output port PF7 to PFO Port mode PD7 to PDO Expansion mode 256 bytes PF7 to PFO Port mode PD7 to PDO 4K bytes PF3 to PFO PF7 to PF4 Port mode Expansion mode Expansion mode PD7 to PDO 16K bytes PF5 to PFO PF7 amp PF6 Port mode n Expansion mode 48K 56K PD7 to Expansion mode 60K bytes Note to PFO Note Depending on setting of bits MM7 amp MM6 On chip RAM access Disable Enable On chip EPROM access Access to on chip EPROM addresses 0000H to 3FFFH uPD78C14 mode Access to on chip EPROM addresses 0000H to 1FFFH uPD78C12A mode Access to on chip EPROM addresses 0000H to OFFFH uPD78C11A mode Setting prohibited 205 206 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS uPD78CP18 78CP14 ONLY memory The pins shown in The uPD78CP18 and uPD78CP14 incorporate 32768 x 8 bit and 16384 x 8 bit PROM respectively as program Table 13 1 are used for write verify operations on this PROM he uPD78CP18 78CP14 program timing is uPD27C256A compatible and this chapter should be read in conjunction with documentation on the uPD27C2564A Table 13 1 Pin Functions in PROM Programming Pin Name Function RESET Low level input in write verify and read MODEO High level input in write verify and read MODE1 Low level input in write verify and rea
59. Receive disable e INTSR disable lt f gt Recover register Recover accumulator Enable interrupt Return 135 136 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS The uPD78C18 incorporates high precision 8 bit A D converter with 8 analog inputs which uses the successive approximation method and four conversion result registers CRO to CR3 to hold the conversion results The provision of a scan mode and select mode for analog input selection minimizes the software overhead 8 1 Analog Digital Converter Configuration The A D converter consists of an input circuit series resistance string voltage comparator successive approximation logic and registers CRO to CR3 see Figure 8 1 The 8 analog inputs are multiplexed on the chip and are selected by the specification of the A D channel mode register ANM The selected analog input is sampled by the sampling amp hold circuit and becomes one of the voltage comparator inputs The voltage comparator amplifies the difference between the analog input and the voltage tap of the series resistance string The series resistance string is connected between the A D reference voltage pin Vaner and the A D ground AVss and consists of a total of 257 resistors comprising 255 equal resistors and two resistors equal to half that value to provide 256 voltage steps between the two pins The series resistance string voltage tap is selected by the tap decoder This decode
60. a receive data is checked for errors if an error is found control passes to the error handling routine Caution If the RXB datais not read out when an error is generated an overrun error will be generated again when the next receive operation is performed 134 CHAPTER 7 SERIAL INTERFACE FUNCTIONS b lt C gt lt d gt lt e gt lt f gt The receive data is stored in the memory A check is made to see if the data buffer is full if it is not control returns to the main routine PC7 output is set to 1 inactivating CTS and uPD71051 data transmission is stopped The RxE bit of the serial mode high register SMH is reset 0 and the receive operation is stopped The MKSR bit of the interrupt mask register MKH is set 1 disabling INTSR internal interrupts The interrupt service routine is shown below Either this interrupt service routine must be stored starting at the INTSR interrupt address 0028H or else a JMP RECV instruction must be stored in that address EXA EXX SKNIT JMP MOV STAX DCR JR ORI ANI ORI RECO EXX EXA 80H SMH 7 MKH 02H D D D D D Save accumulator Save register Test ERflag skip if ER 0 lt gt Jump ERROR routine Input received data Store received data to memory zd Skip if buffer full c CTSe1 d
61. is set to 12 5 V and to 6 V driving CE and OE low is inhibited Table 13 3 Recommended Connection of Unused Pins In PROM Programming Mode Pin Name Recommended Connection Connect to Vss X1 ANO to AN7 VAREF AVDD AVss Pins other than the above Connect to Vss individually via a resistor 2 Leave open 208 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS 78 13 2 PROM Writing Procedure The procedure for writing data to the PROM is as shown below allowing high speed writing Connect unused pins to Vss with a pull down resistor Supply 6 V to the pin and 12 5 V to the VPP pin 2 Supply initial address 3 Supply write data 4 Supply a 1 ms program pulse active low to the CE pin 5 Verify mode If written go to 7 if not written repeat 3 through 5 If not written after 25 repetitions to 6 6 Halt write operation due to defective device 7 Supply write data and supply times repeated in 3 through 5 x x 3 ms program pulse additional write 8 Increment address 9 Repeat 3 through 8 up to final address Figure 13 1 Write Verify Timing Repeat X times u Write mn Verify EE Additional write A14 10 PF6 2 Address high order 7 bits A8 PFO 7 0 7 0 Address low order 8 bits Data VPP Vep Vop 1 6 N N Vit
62. lt 2 gt Number of bytes 2 3 Number of states 7 7 lt 4 gt Function A byte Adds the immediate data in the 2nd byte to the contents of the accumulator and stores the result in the accumulator 5 Flags affected Z SK lt 0 L1 lt 0 10 lt 0 CY ADI r byte Add Immediate to Register 1 Operation code O 1 1 1 0 1 0 0 0 1 0 0 0 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function r byte Adds the immediate data in the 3rd byte to the contents of the register r V A B C D E H L specified by R2R1Ro 0 7 and stores the result in the specified register lt 5 gt Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY ADI sr2 byte Add Immediate to Special Register 1 Operation code O 1 1 0 O 1 0 0 Ss 1 0 0 0 52 Si So 2 Number of bytes 3 3 Number of states 20 11 4 Function sr2 lt sr2 byte Adds the immediate data in the 3rd byte to the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and stores the result in the specified special register b Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY 270 CHAPTER 14 INSTRUCTION SET ACI A byte Add Immediate to A with Carry 1 Operation code O 1 0 1 0 1 1 0 2 Number of bytes 2 3 Number of states 7 7 4 Functio
63. mask all interrupts except those used to release the HALT mode This function is valid when pins PC7 to PCO are in the control signal input output mode Therefore TO output and serial transmission reception is enabled in the HALT mode 171 CHAPTER 10 CONTROL FUNCTIONS 10 1 2 HALT mode release 1 2 172 Release by RESET signal When the RESET signal changes from the high to low level in the HALT mode the HALT mode is released and the reset state is set When the RESET signal returns to the high level the CPU starts program execution at address 0 When the RESET signal is input the RAM contents are retained but the contents of other registers are indeterminate Figure 10 1 HALT Mode Release Timing RESET Signal Input Execution of address 0 instruction CPU HLT s JUIN SUL RESET Release by interrupt request flag The HALT mode is released if at least one interrupt request flag is set by the generation of a non maskable interrupt NMI or one of ten unmasked maskable interrupts INTTO INTT1 INT1 INT2 INTEO INTE1 INTEIN INTAD INTST and INTSR When the HALT mode is released by a non maskable interrupt the instruction following the HLT instruction is not executed and the program jumps to the interrupt address 00044 irrespective of the interrupt enabled disabled EI DI state When the HALT mode is released by a maskable interrupt operation after release differs depending o
64. n is zero b Flags affected ZL SK L1 lt 0 LO 0 CY 6 Example SKIP IF DE skip is performed when the contents of and the contents of the memory addressed by the DE register pair are equal ONAX rpa On Test Memory addressed by Register Pair with A 1 Operation code O 1 1 1 0 0 0 0 1 1 0 O 1 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function A Skip if no zero Obtains the logical product of the contents of the accumulator and the contents of the memory addressed by the register pair rpa BC DE HL DE HL DE HL specified by AzA1Ao 1 to 7 and skips if the logical product is not zero 5 Flags affected ZSK11 0 L0 0 OFFAX rpa Off Test Memory addressed by Register Pair with A 1 Operation code 0 1 1 1 0 0 0 0 1 1 O 1 1 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function Skip if zero Obtains the logical product of the contents of the accumulator and the contents of the memory addressed by the register pair rpa BC DE HL DE HL DE HL specified by A2A1Ao 1 to 7 and skips if the logical product is zero 5 Flags affected 5 116 0 10 0 269 CHAPTER 14 INSTRUCTION SET 14 6 5 Immediate data operation instructions ADI A byte Add Immediate to A 1 Operation code 0 1 0 1 1 0
65. uPD78CP14 Murata Mfg Co Ltd CSA12 0MT 30 30 CST12 0MTW Built in Built in CSA10 0MT 30 30 CST10 0MTW Built in Built in CSA8 00MT 30 30 CST8 00MTW Built in Built in uPD78C17 Murata Mfg Co Ltd 5 15 00 001 22 22 78 18 CST15 00MXW001 Built in Built in CSA10 0MT 30 30 CST10 0MTW Built in Built in CSA8 00MT 30 30 CST8 00MTW Built in Built in FCR15 0MC Built in Built in FCR10 0MC Built in Built in FCR8 0MC Built in in Remark Use of crystal and ceramic resonator Generally speaking the oscillation frequency of a crystal is extremely stable and it is therefore ideal for high precision time management for example in clocks and watches measuring instruments etc The oscillation frequency stability of a ceramic resonator is not as high as that of a crystal but it offers three advantages a fast oscillation start up time small size and low cost It is therefore suitable for general applications in which high precision time management is not required In addition products with built in capacitors etc are available offering the advantage of fewer parts and reduced mounting area 186 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11 1 uPD78C18 78C14 78C14A 78C12A 78C11A External Device Accesses For the uPD78C18 78C14 78C14A 78C12A 78C11A the areas shown below can be used for external device expansion data memory program memory
66. use of an external capacitor In this case each pin responds as a digital input However an input load current is necessary and an external circuit output driver must be considered Thus when no zero cross detection is executed and each pin is used simply as an interrupt input or timer input the ZC1 and ZC2 bits of the zero cross mode register should be set to 0 RESET input sets both the ZC1 and ZC2 bit to 1 and a self bias is generated When the INT2 TI pins is in port mode self bias is generated regardless of the ZCM register setting Cautions 1 Unlike other CMOS circuits a supply current is always present in the zero cross detector because of its operation points This also applies in the standby modes HALT and software hardware STOP modes Thus when the zero cross detector is operated with self bias generation ZCx 1 slightly more current flows than without zero cross detector operation and its effect is greater in the software STOP mode 2 When the pin is used for zero cross detection in the uPD78C18 78C14A 78C12A 78C11A no pull up resistor should be incorporated In the hardware STOP mode self bias generation is stopped automatically 59 60 CHAPTER 4 PORT FUNCTIONS 4 1 Port A PA7 to PAO This is an 8 bit input output port which has input output buffer and output latch functions see Figure 4 1 Port A can be set as to input or output bit wise using the mode A registe
67. 0 2 Number of bytes 2 3 Number of states 11 8 4 Function EA Arp3 Skip if zero Obtains the product of the contents of the extended accumulator and the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 and skips if the result is zero 5 Flags affected 7 5 116 0 0 0 299 CHAPTER 14 INSTRUCTION SET 14 6 8 Multiplication division instructions MUL r2 Multiply A by Register 1 Operation code 0 1 0 0 1 0 0 0 0 0 1 0 1 1 R Ro 2 Number of bytes 2 3 Number of states 32 8 4 Function EA lt Axr2 Performs unsigned multiplication of the contents of the accumulator by the contents of the register r2 A B C specified by RiRo 1 to 3 and stores the result in the extended accumulator 5 Flags affected SK 0 L1 0 10 0 DIV r2 Divide EA by Register 1 Operation code 010 1 0 0 0 0 0 1 1 1 1 Rac Re 2 Number of bytes 2 3 Number of states 59 8 4 Function EA lt EA r2 r2 lt remainder Divides unsigned division the contents of the extended accumulator by the contents of the register r2 A B C specified by RiRo 1 to 3 and stores the quotient in the extended accumulator and the remainder in register r2 If r2 O 0 divisor FFFFH is stored in EA and the contents of the low order 8 bits of EA prior to execution of the instruction are stored in r2 b Flags affected SK 0
68. 0 1 0 0 0 0 0 1 0 0 0 R Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function r2m 1 r2m r27 lt 0 lt 120 7 0 Performs 1 bit right shift of the contents of the register r2 A B C specified by R1Ro 1 to 3 r2ois shifted into the CY flag and 0 is loaded into r27 b Flags affected SK 0 L1 amp 0 10 lt 0 CY SLLC r2 Shift Logical Left Register Skip if Carry 1 Operation code O 1 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function r2m 1 lt 12m r20 lt 0 CY lt r27 Skip if carry Performs 1 bit left shift of the contents of the register r2 A B C specified by RiRo 1 to 3 r27 is shifted into the CY flag and 0 is loaded into 20 Skips if a carry is generated as a result of the shift 5 Flags affected SK L1 0 LO 0 CY 309 CHAPTER 14 INSTRUCTION SET SLRC r2 Shift Logical Right Register Skip if Carry 1 Operation code O 1 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function 2 1 lt r27 lt 0 lt r2o 7 0 Performs 1 bit right shift of the contents of the register r2 A B C specified by R1Ro 1 to 3 r2ois shifted into the CY flag and 0 is loaded into r27 Skips if a carry is generated as a result of the shift b Flags affected SK L1 0 LO 0 CY DRLL EA Rotate Logical Left EA
69. 1 1 0 0 1 1 Ss Sa 52 Si So 2 Number of bytes 2 3 Number of states 10 7 4 Function lt sr1 Transfers the contents of the special register sr1 PA PD MKL ANM SMH CRO CR2 specified 555453525150 0 to 5 to 9 B D 19 20 to 23 to the accumulator 5 Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example i MOV A Transfer timer mode register contents to A 234 CHAPTER 14 INSTRUCTION SET MOV r word Move Memory to Register 1 Operation code O 1 1 1 0 0 0 0 O 1 1 0 1 R2 Ro Low address High address 2 Number of bytes 4 3 Number of states 17 14 4 Function r lt word Transfers the contents of the memory addressed by the 3rd byte Low address and 4th byte High address to the register V A B C D E H L specified by R2RiRo 0 to 7 5 Flags affected lt 0 11 lt 0 LO lt 0 lt 6 gt MOV 89 Transfer contents of address 89ABH to MOV word r Move Register to Memory 1 Operation code O 1 1 1 0 0 0 0 R2 Ro Low address e High address lt 2 gt Number of bytes 4 lt 3 gt Number of states 17 14 lt 4 gt Function word lt Transfers the contents of the register V B C D E H L specified by 2 1 0 to 7 to the memory addressed by th
70. 2 Memory Map uPD78C12A Mode 0000H Piggyback EPROM 8192 x 8 bits 1FFFH 2000H External memory 57088 x 8 bits FEFFH FFOOH On chip 256 x 8 bits FFFFH Standby area Call table 0000H 0004H 0008H 0010H 0018H 0020H 0028H 0060H 0080H 0081H 0082H 0083H OOBEH OOBFH 1FFFH Note Can only be used when the RAE bit of the MM register is 1 344 1 2 INTEO INTE1 INTEIN INTAD INTSR INTST SOFTI Low address High address Low address High address Low address 31 High address User s area APPENDIX INTRODUCTION PIGGYBACK PRO 0000H 0009 or dd 4096 x 8 bits 0008H INTTO INTT1 OFFFH 1000H 0010H INT1 INT2 External memory 0018H INTEO INTE1 61184 x 8 bits 0020H INTEIN INTAD FEFFH FFOOH 2 On chip RAMNete 5 0028 INTSR INTST x its 2 49 FFFFH 0060H SOFTI 0080H Low address t 0 0081H High address 0082 Low address 1 0083H High address T OOBEH Low address t 31 OOBFH High address User s area OFFFH Note Can only be used when the RAE bit of the MM register is 1 345 APPENDIX INTRODUCTION PIGGYBACK PRODUCT A 3 Memory Mapping Regi
71. 263 14 6 5 Immediate data operation 270 14 6 6 Working register operation instructions 2 12 9 285 14 6 7 T16 bit operation INSTIUCTIONS 294 14 6 8 Multiplication division 5 22 9 300 14 6 9 lIncrement decrement 4 1 1 seiner drinnen etn 301 14 6 10 Other operatiorn Instructions usce ctt 304 12 6 14 Gun earn 306 14 06 12 J rmp INSTRUCTIONS RAER RIT 313 TACAS CA Eioitigufeuo n TER RR TTE 316 14 6 14 CHONS ceo ccu 319 14 6 15 SKIP 321 14 6 16 CPU control 5 323 14 7 Stacked Instructions oon inei remit er RE 326 CHAPTER 15 OPERATING PRECAUTION GS 0 2 00000 4000 327 151 RAE Bit Setting corriere reco rs ei ac E RE tee 327 152 DF UR EE Seu EE 328 15 3 Timer Timer Event Counter Compare Register Setting 328 15 4 Restrictions on Serial Interface and Asynchronous Modes 329 15 5 Serial I
72. 5 gt Flags affected 7 5 116 0 0 0 292 CHAPTER 14 INSTRUCTION SET OFFIW wa byte Off Test Immediate with Working Register 1 Operation code O 1 0 1 O 1 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Function V wa byte Skip if zero Obtains the logical product of the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and the immediate data in the 3rd byte and skips if the result is zero 5 Flags affected 5 1 lt 0 0 0 293 CHAPTER 14 INSTRUCTION SET 14 6 7 16 bit operation instructions EADD EA r2 Add Register to EA 1 Operation code O 1 1 1 0 0 0 0 0 1 0 00 0 R Ro 2 Number of bytes 2 3 Number of states 11 8 4 Function EA lt 2 Adds the contents of the register r2 A C specified by RiRo 1 to 3 to the contents of the low order 8 bits of the extended accumulator and stores the result in the extended accumulator 5 Flags affected Z SK lt 0 L1 0 LO lt 0 CY DADD EA rp3 Add Register Pair to EA 1 Operation code O 1 1 1 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function EA lt EA rp3 Adds the contents of the register pair rp3 BC DE HL specified by P Po 1 to 3 to the contents of the extended accumulator and stores the result i
73. Auto decrement addressirig uote dtc 224 14 4 5 Double auto increment 0 1 1 0 0 6 1 000000 110000000000 225 14 4 6 Base addressiFig uoces cedem un Beute e 226 14 4 7 Base index addressing 227 14 4 8 Working register cose rena eR XR o dE PN RR a 228 14 4 9 Accumulator indirect addressing 2 229 144 10 Immediate addressing dicun 229 14 4 11 Extended immediate addressing on ael i tu ede 230 14 4212 Drect AD OlESSING Pes tes epi ea Re e 231 14 5 Number of States Required for 232 14 6 Instruction adanan Pea EE RR RR RR RR 233 14 6 1 8 bit data transfer instructions 42424 2222 00 0000000000000000 enne nean 233 74 62 16 bit data transfer Instr ctions isses esci pet d UR E dh dag dia 242 146 3 8 bit operation instructions Register bec sie a a Ret 252 14 6 4 8 bit operation instructions Memory sssini eene rennen
74. BC DE HL B C D E H L Four register pairs DE D E HL and H L in particular a base register function When the two sets are used if an interrupt occurs in one set the register contents are saved into the other register set without saving them into the memory so that interrupt servicing can be carried out The other set of registers can also be used as a data pointer expansion registers Single step auto increment decrement modes and a two step auto increment addressing mode are available for the register pairs DE HL D E and H L so that the processing time can be reduced BC DE and HL can be simultaneously replaced with the ALT register by means of the EXX instruction The HL register can be independently replaced with the ALT register by means of the EXH instruction Program counter PC This is a 16 bit register which holds information on the next program address to be executed This register is normally incremented automatically according to the number of bytes of the instruction to be fetched When an instruction associated with a branch is executed immediate data or register contents are loaded RESET input clears this counter to 0000H Stack pointer SP This is a 16 bit register which holds the start address of the memory stack area LIFO format SP contents are decremented when a call or PUSH instruction is executed or an interrupt is generated and incremented when a return or POP instruction is executed
75. C MCC register When the corresponding bit of mode control C register is set 1 the port C is set to control mode and if reset 0 set to port mode see Figure 4 6 When RESET is input or the hardware STOP mode is set all bits of the mode control C register are reset and all bits of port C are set to port mode In the uPD78C18 78C14A 78C124 78C114 pull up resistors can be incorporated bit wise Figure 4 6 Mode Control C Register Format 0 7 6 5 4 3 2 MCC PCO Port mode PCO TxD output PC1 Port mode PC1 RxD input PC2 Port mode 2 SCK input output PC3 Port mode PC3 INT2 TI input 4 Port mode 4 TO output PC5 Port mode PC5 Cl input PC6 Port mode PC6 COO output 7 Port mode 7 output 66 4 5 1 2 Port mode Like port A port C is an 8 bit input output port with input output buffer and output latch functions see Figure 4 1 When port C is set to port mode by the mode control C register it can be set bit wise as an input or output port by means of the mode C register MC When set to input port the pins become high impedance When the corresponding bit of the mode C register is set 1 a port C pin functions as an input port pin and when reset 0 as an output port pin see Figure 4 7 When RESET is in
76. D H L specified by R2R1Ro 0 to 7 including the CY flag and stores the result in the specified register 5 Flags affected Z SK lt 0 L1 0 LO lt 0 CY 6 Example Add the register pairs HL and DE and store the result in HL MOV AE A amp E ADD LA Le Llt A MOV AD ADC lt H A CY ADDNC Add Register to Skip if Carry 1 Operation code O 1 1 0 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if no carry Adds the contents of the register V A C D E H L specified by R2R1Ro 0 to 7 to the contents of the accumulator and stores the result in the accumulator Skips if no carry is generated as a result of the addition b Flags affected 7 SK L1 0 LO 0 6 Example ADDNC A V lt A V A skip is performed if no carry is generated as a result of the addition 253 CHAPTER 14 INSTRUCTION SET ADDNC r A Add A to Register Skip if No Carry 1 Operation code 0 1 1 0 0 0 0 0 0 1 0 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function lt Skip if no carry Adds the contents of the accumulator to the contents of the register r V A B C D E H L specified by R2R 1Ro 0 to 7 and stores the result in the specified register Skips if no carry is generated as a result of the addition 5 F
77. Diagram 84 CHAPTER 6 TIMER EVENT COUNTER FUNCTIO 8 9 Output control circuit This circuit controls the two channel pulse outputs COO amp and operates as a timer event counter enabling the pulse width and cycle to be varied Pulse output is varied by the following signals i Match of ECNT and ETMO ii Match of ECNT and ETM1 ii Cl input edge Mode registers These are two 8 bit registers which specify the operation of the timer event counter and output control circuit see 6 2 Mode Registers for details 6 2 Mode Registers The timer event counter has two mode registers The timer event counter mode register which specifies the operating mode and the timer event counter output mode register EOM which specifies the operation of the output control circuit 6 2 1 Timer event counter mode register ETMM This is an 8 bit register which controls the timer event counter its configuration is shown in Figure 6 2 1 2 3 amp ET1 bits 0 amp 1 These bits specify the timer event counter upcounter ECNT input clock latch timing and INTEIN interrupt flag setting conditions They may also be used for clear mode specification when EM1 1 and 0 The internal clock 12 is obtained by dividing the oscillator frequency by 12 EMO amp EM1 bits 2 amp 3 These bits control the ECNT clear mode When the value of the EMO bit and EM1 bit is
78. EVENT COUNTER Figure 6 19 Timer Event Counter Mode Register Setting Programmable Rectangular Wave Output ECNT Operation Setting 5 4 3 2 1 0 1 7 6 ECNT input clock Internal clock 12 ECNT clear mode Match between ECNT and ETM1 COO output timing Match between ECNT and or match between ECNT and ETM1 e LVOis set so that a high level signal will be output to the COO pin by the first comparator match signal F TIMER EVENT COUNTER INITIALIZATION x INIT MVI 00H MOV Clear timer event counter lt a gt MVI EOM 07H Initialize counter output 0 J MVI A 40H COO 1 MOV MCC A Set Port C mode control J LXI EA 00C8H Low level 200 us at 12 MHz DMOV EA Set count value E ceps LXI EA O1F4H High level 300 us at 12 MHz DMOV ETM1 EA Set count value 2 START MVI A 3CH MOV ETMM A Set timer event counter mode amp start a ORI EOM 08H Set LVO lt e gt 99 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 2 Single pulse output In single pulse output as shown in Figure 6 20 a pulse is output to the COO pin a specific time after the fall of the Cl input In this program example a pulse with a high level width of 200 us is output 100 us after the fall of the input at 12 MHz operation Figure 6 20 Single Pulse
79. FUNCTIONS for details 57 3 INTERNAL BLOCK FUNCTIOS 3 11 Zero Cross Detector he INT1 pin and INT2 TI dual function can be made to execute zero cross detection operations by setting the zero cross mode register he zero cross detector has a self bias type high gain amplifier It biases the input to the switching point and generates digital displacement in response to a small input displacement Figure 3 13 Zero Cross Detector 78 18 External capacitor INTI AC input signal gt gt To internal circuitry 1 to 1 8 Ver Self bias circuit enable The zero cross detector detects a negative to positive or positive to negative transition of the AC signal input through an external capacitor and generates a digital pulse which changes from 0 to 1 or 1 to 0 at each transition point Figure 3 14 Zero Cross Detection Signal AC input signal Zero cross detection signal A digital pulse generated in the zero cross detector of the INT1 pin is set to the interrupt control circuit The INTF1 interrupt request flag is set at the zero cross point from negative to positive of the AC signal rising edge and if INT1 interruptis enabled interrupt servicing is started A digital pulse generated in the INT2 TI pin zero cross detector is sent to the interrupt control circuit and interrupt servicing can be started at the zero cross point from posi
80. Function r byte Skip if no zero Obtains the logical product of the contents of the register V A B D H L specified by RzR1Ro 0 to 7 and the immediate data in the 3rd byte and skips if the result is not zero 5 Flags affected 5 116 0 0 0 ONI sr2 byte On Test Immediate with Special Register 1 Operation code O 1 1 O 1 0 0 Ss 1 0 0 1 52 Si So 2 Number of bytes 3 3 Number of states 14 11 4 Function sr2Abyte Skip if no zero Obtains the logical product of the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM specified by 53525150 0 to 3 5 to 9 B D and the immediate data in the 3rd byte and skips if the result is not zero 5 Flags affected 5 1 lt 0 0 0 6 Example To test bit O PCO of port C and jump to XX if 0 or skip and execute the next instruction if 1 on ONI PC 01H PC 00000001 JMP XX 283 CHAPTER 14 INSTRUCTION SET OFFI A byte Off Test Immediate with A 1 Operation code O 1 0 1 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function A byte Skip if zero Obtains the logical product of the contents of the accumulator and the contents of the immediate data in the 2nd byte and skips if the result is zero 5 Flags affected SK 1 lt 0 0 0 byte Off Test Immediate with Register 1 O
81. GND pin at same potential as lower Vss pin Supplies OE signal always low to 27C256 27C256A at same potential as lower Vss pin A 2 Memory Configuration Supplies A14 signal always low to 27 256 27 256 at same potential as lower Vss pin The memory of the uPD78CG14allows implementation of the same functions and configuration as the uPD78C11A 78C12A 78C14 Also the piggyback EPROM address range can be selected by means of the memory mapping register for efficient setting of external memory excluding EPROM The vector addresses call table area and data memory area are the same for all three product types The memory maps are shown in Figures A 1 to A 3 342 APPENDIX INTRODUCTION PIGGYBACK PRO 0000H 0000H or nu 16384 x 8 bits 0008H INTTO INTT1 3FFFH 4000H 0010H INT1 INT2 External memory 0018H INTEO INTE1 48896 x 8 bits 0020H INTEIN INTAD FEFFH A hi n cnip E 0028H INTSR INTST 256 x 8 bits f FFFFH 0060H SOFTI 0080H Low address t 0 0081H High address 0082 Low address 6 1 0083H High address Low address t 31 OOBFH High address User s area Note Can only used when the RAE bit of the MM register is 1 343 APPENDIX INTRODUCTION PIGGYBACK PRODUCT Figure A
82. H L specified by 2 1 0 to 7 and the immediate data in the 3rd byte and stores the result in the specified register 5 Flags affected Z 5 lt 0 1 lt 0 10 0 ANI sr2 byte And Immediate with Special Register 1 Operation code O 1 1 O 1 0 0 Ss 0 0 0 1 52 Si So 2 Number of bytes 3 3 Number of states 20 11 4 Function sr2 lt 512 byte Obtains the logical product of the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and the immediate data in the 3rd byte and stores the result in the specified special register b Flags affected Z 5 lt 0 11 lt 0 10 0 6 Example To reset bit 2 PB2 of port B ANI PB OFBH lt PB 11111011 276 CHAPTER 14 INSTRUCTION SET ORI A byte Or Immediate with A 1 Operation code 100010 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function lt Av byte Obtains the logical sum of the contents of the accumulator and the contents of the immediate data in the 2nd byte and stores the result in the accumulator 5 Flags affected Z 5 lt 0 1 lt 0 10 0 ORI byte Or Immediate with Register 1 Operation code O 1 1 0 2 Number of bytes 3 3 Number of states 11 11 4 Function lt rv byte Obtains the logical sum of the conten
83. LXI D 0101 Set counter Exchange register set MVI ANM 00H c SKIT FAD Reset INTFAD NOP lt gt ANI OFEH INTAD enable e In the INTAD interrupt service routine the A D conversion values in CRO to are stored in the prescribed memory locations The operation flow is shown below 148 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNC Store contents of to memory lt gt b Y ue c N Breg lt d gt 4020H end lt e gt N Creg Y 4004H end Set memory 4 Dreg Y gt address 4024H HL lt 4020H end Set memory Ereg address HL lt 4004H Set memory Set memory address address HL lt 4024H HL lt 4000H Set counter Set counters C 0 Dc 0 Set counter Bc3 Set A D channel mode register invert ANI2 bit a RETI lt a gt lt b gt lt C gt The contents of CRO to CR3 which hold the A D conversion values for pins ANO to AN3 or pins AN4 to AN7 are stored in the prescribed memory locations A check is made to see if an INTAD internal interrupt has been generated 4 times If fewer than 4 the HL register pair is incremented by 1 and control returns from the routine If there have been A interrupts the program jumps to c The B register is the counter used to check whether 4 interrupts have been generated As the A D conversion values are stored in memory blocks starting at a
84. Operation of Arithmetic and Logical Operation Instruction Involving Port Immediate Data With the following instructions which perform arithmetic and logical operations involving a port and immediate data the operation differs depending on the input output setting of the port Table 4 4 Operation of Arithmetic Logical Operation Instructions Involving a Port Mnemonic ACI ADI ADINC SBI SUI SUINB ANI ORI XRI GTI LTI NEI OFFI ONI Instruction operations are as follows 1 The port status is input Operand sr2 byte Output mode pin Output latch status is input Input mode pin Pin external status is input 2 The arithmetic logical operation is performed on the input data and immediate data 3 The entire 8 bit operation result data is transferred to the port output latch For input mode pins the result of the operation with the pin external status is transferred to the output latch Instruction Arithmetic operation Logical operation Comparison Match detection Test Caution 3 applies only to the arithmetic operations and logical operations in Table 4 4 Port output latch initialization should be performed by a transfer instruction MOV 73 74 5 5 5 1 Timer Configuration The timer system in the uPD78C18 consists of two 8 bit interval timers TIMERO and TIMER1 an
85. Output COO i i 4100 5 200 ws 1 INTEIN 1 The following are required in order to perform this operation An initialization program service routine to handle internal interrupts INTEIN generated by the fall of the Cl input and a service routine to handle internal interrupts INTE1 generated by a match between the contents of ECNT and First the initialization routine will be described The operation flow is shown below INITIAL Timer event counter initialization Port C initialization b Interrupt mask register mode setting Timer event counter mode setting lt d gt 100 CHAPTER 6 TIMER EVENT COUNTER FUNCTIO a The timer event counter ECNT is cleared COO output is driven low and LVO is set This is done in the same way as in step lt a gt of 1 programmable rectangular wave output lt b gt The 5 in of port C is set as Cl input and the PC6 pin as COO output Figure 6 21 Port C Setting Single Pulse Output PC5 as Cl input PC6 as COO output c Internal interrupt INTEIN masking is released by means of the interrupt mask register MKL Internal interrupts INTAD with the same priority as INTEIN must be masked by the interrupt mask register MKH Figure 6 22 Interrupt Mask Register Setting Single Pulse Output INTEIN Mask Release INTEIN masking released INTAD masking d Timer event counter
86. Relationship Between Analog Input Voltage and A D Conversion Results 145 Memory Map Store Example of A D Conversion Result 146 AJD Chanriel Mod Register Setting Seus tee bec peret de een en e 147 Interrupt Control Circuit Block Diagram 2 2 3 3 022200292 5 154 Mask Register MKL MKH Format 2 2 2 2 0 010000000000 nnn nr nis 156 Iiterr pt Sambplifig 159 Interrupt Operation Proce Gul Ger mi senex msi lees pdt Ronda 161 internal Configuration of NMI coe E 162 Interrupt Servicing Sequence Masking released for both INT1 and 2 164 Interrupt Servicing Sequence Masking released for either INT1 or 2 165 3 Level Multiple Interrupts 2 Sp duae Duns e duda 169 HALT Mode Release Timing RESET Signal 222 1 2 5 172 HALT Mode Release Timing Iri E State e rne tete e te tta ar dec des 173 HALT Mode Release Timing In DI State icto gt eR p abso ce Ex bee sass 173 Software STOP Mode Release Timing RESET Signal Input 175 176 Software STOP Mode Release Timing NMI Signal Input 176 Hardware STOP Mode Release
87. SCK the data transfer rate is determined from the oscillator frequency and the clock rate by the following expressions where f is the oscillator frequency is the clock rate 1 16 64 C is the timer count value and B is the data transfer rate For internal clock 24 fxx Banm M 24x N For internal clock 384 fxx 384 x N For TO output used as internal clock When the timer input clock is 12 fxx Be 24xNxC When the timer input clock is 384 CE 768xNxC When the timer F F input is _ 6xN When the timer F F input is s when the TO output is used as the internal clock the clock can only be used when the clock rate is 16 or 64 When TIMERO is used and the clock rate is 16 the set values of the timer mode register TMM and the serial mode registers SML SMH are as follows xxx00000B SML 10 SMH 0000xx00B x Set by user When the TO output is specified as the internal clock and the input clock to the timer is used as the internal clock 12 the timer count values shown in Table 7 1 are set to perform transmission reception at data transfer rates of 110 to 9600 bps 117 CHAPTER 7 SERIAL INTERFACE FUNCTIONS Table 7 1 Timer Setting Oscillator Frequency MHz 11 0592 14 7456 Data Transfer Speed bps The data format in asynchronous mode is shown in Figure 7 5 Figure 7 5 Asynchronous Data Format INTSR INTST gene
88. STOP Stop control input 2 2 2 2 0 0 60 010010000000 eet esta cete M ME 2118 RESET 2 7519 M ANB MB C NG seis sa 2 2 EPROM MERE 2 2 1 14 40 AO AGGEESS 2 2 2 0710 00 EE EE A EOR 223 eb oO 10 13 15 16 18 19 21 22 23 23 23 23 23 25 26 27 27 27 28 28 28 28 28 28 29 29 29 29 29 29 29 30 30 30 30 2 244 Ouitputenable conscendere ente atn cde pn Cases 30 2 2 5 MODET ctii 30 220 RESET 8 30 2 2 7 MB 30 2 2 8 A Hn 30 2 2 9 30 2 3 Pin Input Output Circuits reor rero eere p 31 2 4 Pin Mask Options uPD78C18 78C14A 78C12A 78C11A Only 37 2 5 Processing of Unused
89. Serial Mode Register Format in I O Interface 123 I O Interface Mode TIMING sese orent detener vex e 124 Example of Serial Data Transfer System 127 Serial Mode Register Setting mec eie a 128 Timer Mode Register Setting 129 Port C Setting Serial Interface 130 Serial Mode High Register SMH Setting Serial Interface Transmission Enable 130 Interrupt Mask Register MKH Setting Serial Interface INTSR Mask Release 133 Serial Mode High Register SMH Setting Serial Interface Reception Enable 133 A D Converter Block Diagram uer inedite tede metet dab ed epe qn 138 A D Channel Mode Register Forrnat e iie epa c ehe e epa 141 A D Channel Mode Register in Scan Mode 2212 2 2 2 22000000 000 142 Outline of A D Converter Operation Timing in Scan 143 Channel Mode Register in Select 2 2 22 9 143 Outline of A D Converter Operation Timing in Select Mode 144
90. Series CMOS and NMOS Products 1 7 Differences between Standard and Special Quality Grade Products CHAPTER 2 PIN FUNCTIONS 02 2 20204 0 44 000 0 asas 2 1 Normal Operation Mode 00 0 40 40008 00 2 1 1 PAT tO PAO cedes eee b 2 1 2 PBZ 19 PBO POM iet ena ed etin ae rbv tns eed Ee 2 113 PCI to PCOIPOFE u eee aeneo bere saxea erga dep pecado eo va Pu Ro dcc bed 214 PORE ID 2 1 5 PFA tO PFO 24 6 257 ADS REA Strobe 2 1 8 ALE Address latch enable iude tte ras tal 2 19 MODEO MODET Mode in a 2 1 10 NMI Noni maskable bc detecte 2 1 11 1 1 Interrupt 2 7512 ANZ to ANO Analog Inl 25 exu e Lena date 2 1 13 V nEE Reference Voltage iic cet cde see trea cet trt re cq queat n 24 VbD uiu ctr rite rob to CORE HI lanes te eR UE aves 251 15 2 55 Analog VSS seni o Eod de e RR d let ae tuf ertt 2 1 16
91. after loading address information into BC by means of the TABLE instruction 5 Flags affected SK lt 0 11 lt 0 10 0 313 CHAPTER 14 INSTRUCTION SET JR word Jump Relative 1 Operation code jdisp1 lt 2 gt Number of bytes 1 3 Number of states 10 4 4 Function i lt PC 1 jdisp1 Jumps to the address obtained by adding the 6 bit displacement value jdisp1 to the start address of the next instruction jdisp1 is handled as signed two s complement data 32 to 31 with bit 5 as the sign bit 15 0 T 15 654 0 8 jdisp1 15 0 When 20 X All O s When 1 X All 1 s A jump destination address or label which takes account of the jump range should be directly written as the operand of the JR instruction Thus when a JR instruction is executed at address 1000 for example the possible jump range is from address 969 to address 1032 lt 5 gt Flags affected SK 0 L1 0 L0 0 6 Example i CLWR LXI D 2000H DE 2000H MVI C 7 C27 LOOP COUNTER XRA CLEAR 98LOOP STAX D lt 0 DE lt DE 1 99 DCR 1 SKIP IF BORROW 100 JR LOOP JUMP TO LOOP RET The loop is executed repeatedly by means of the JR instruction until the 8 addresses starting at memory address 2000H i e addresses up to the including address 2007H have been cleared Since the displacement value is this case is 3 the actual operation code is as follow
92. bits e Standby functions HALT mode hardware software STOP mode e CMOS e Single power supply 5 V 10 Ordering Information Part Number Package uPD78CG14E 64 pin ceramic piggyback QUIP 337 APPENDIX INTRODUCTION PIGGYBACK PRODUCT Pin Configuration Top View PAO PA1 PA2 PA3 4 5 6 PBO PB1 PB2 PB3 4 5 6 7 PCO TxD PC1 RxD PC2 SCK PC3 INT2 PC4 TO PC6 COO PC7 CO1 NMI MODE1 RESET MODEO X2 X1 Vss Oa AUN B 2 _ 338 PCO TxD PC1 RxD PC2 SCK NMI PC3 INT2 TI PCA TO PC6 COO PC7 CO1 AN7 0 VAREF AVcc AVss 655 Timer event counter 8 Converter 14 13 0 16 EA 17 0 PF7 0 AB15 8 PD7 0 AD7 0 6 Vcc RD WR PC7 0 8 INST REG INST om Decoder PA7 0 STOP RESET MODE ALE V XIGNAddV 19naoud NOVEADSld OL NOILINAOYLNI APPENDIX A INTRODUCTION TO PIGGYBACK PRODUCT A 1 Pin Functions A 1 1 Lower pins uPD78C11A 78C12A 78C14 QUIP type compatible Pin Name PA7 to Port A
93. control the number of stop bits transmitted in the asynchronous mode CHAPTER 7 SERIAL INTERFACE FUNCTIONS SML Figure 7 3 Serial Mode Low Register SML Format 6 5 4 3 S1 12 Clock rate Synchronous operation x1 Setting prohibited Setting prohibited 7 bits 8 bits Disable Enable Even parity generation check 0 Odd 1 Even Number of stop bits Setting prohibited 1 bit Setting prohibited 2 bits The serial mode low register SML is set to 48H by RESET input and in the hardware STOP mode 113 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 7 2 3 Serial mode register initialization The following procedure should be used for serial mode register initialization 1 2 3 4 b Set the mode to be used in the SMH register while the TxE bit and RxE bit are both 0 transmission and reception disabled Set the SML register When the TO output is used as the serial clock perform timer mode setting unless the timer mode has already been specified Set the port C pins to be used for the serial interface to control mode Enable transmission or reception by manipulating the SMH register 7 3 Serial Interface Operation The uPD78C18 serial interface has 3 operation modes Asynchronous start stop mode synchronous mode and interface mode Each of these modes is descri
94. counter output mode register EOM This is an 8 bit register which controls the operation of the timer event counter output control circuit First the configuration of the functions of the output control cycle will be described The block diagram of the COO output of the output control circuit is shown in Figure 6 3 The COO output is a master slave type output and the first stage level F F LVO holds the level to be output next The next stage output latch is used to output the LVO level off chip For the timing for inversion of the LVO level and output off chip from LVO the output timing specified by the timer event counter mode register is used The configuration of the CO1 output is the same as that of the COO output Figure 6 3 Output Control Circuit Block Diagram COO Output Level F F Output latch O PC6 COO CPO CP1 CI The timer event counter output mode register performs initialization and operation control for the output control circuit above its configuration is shown in Figure 6 4 1 LOO amp LO1 bits 0 amp 4 When LOO or LO1 bit is set 1 the level of the level F F LVO or LV1 is output to the output pin These bits are automatically reset 0 when the level is output 2 LDO amp LD1 bits 1 amp 5 These bits determine whether or not the LVO LV1 level is inverted using the timing specified by the timer event counter mode register When the LDO LD1 bitis set 1 the LVO LV1 level is inverted u
95. emulator Relevant register MM register MMO to 2 MF register Remedy Once a mode is set never the same mode again 15 3 Timer Timer Event Counter Compare Register Setting e Target products All products Details When the compare register value setting competes with compareter match the latter takes preference over the former Therefore match interrupt occurrence and output control are disabled Table 15 1 lists compare register match signal and match interrupt of each timer Table 15 1 Compare Register Match Signal and Match Interrupt of Each Timer Timer and Timer Event Counter Compare Register Match Signal Match Interrupt TIMERO Timer REGO TMO TIMER1 Timer REG1 TM1 Timer event counter Timer event counter REGO ECNT ETMO Timer event counter REG1 ETM1 e Remedy When setting the compare register value do not allow the set value to compete with the comparator match signal 328 CHAPTER 15 OPERATING PRECAUTIONS 15 4 Restrictions on Serial Interface and Asynchronous Modes Target products uPD78C10 78C11 78C14 Standards and 78C14A 78CG14 Details When the serial data reception is made in the asynchronous mode using external clock SCK signal the ER flag may not be set normally event if the reception is made normally Remedy Examine the following methods 1 Correction by software When the ER flag is set issue the transmit
96. example CSEG AT 00 GJMP START Branches to initial routine START LXI SP Stack pointer setting CALL INIT INIT MVI 1 In a state in which the RAE bit is not set the on chip RAM cannot be used In addition the RAE bit is indefinite when reset is cleared The indefinite condition varies with a power source voltage rising condition unevenness between product lots difference between masked PROM and on chip PROM etc Therefore in Initialization Example 2 above the RAE bit is indefinite when the INIT routine is called In case the RAE bit is reset stack cannot be used when the INIT routine branches This will result in an inadvertent running due to incapability in normal restore from the INIT routine 327 CHAPTER 15 OPERATING PRECAUTIONS Even when the RAE bit is set and operates normally an abnormality will result due to power source voltage rising condition unevenness between product lots difference between masked PROM and on chip PROM etc e Remedy As shown in Initialization Example 1 set the stack pointer and MM register before interrupt enable and subroutine call to enable the use of on chip RAM 15 2 Port D F Setting e Target products All products Details A program to dynamically change the port D F operation mode from port mode to expand mode and vice versa from input port to output port and vice versa and expansion space change cannot be emulate by an
97. example loads the contents of address 4020H into A EXX Exchange Register Sets 1 Operation code O 0 1 0 0 0 1 2 Number of bytes 1 3 Number of states 4 4 4 Function 2 D2D EZE LeL Exchanges the contents of registers C D L with the contents of registers B C D L b Flags affected 0 11 lt 0 10 lt 0 240 CHAPTER 14 INSTRUCTION SET EXA Exchange V A EA and V A EA 1 Operation code 0 0 0 1 0 0 0 0 2 Number of bytes 1 3 Number of states 4 4 4 Function gt VOV EAZEA Exchanges the contents of V and A registers and EA with the contents of the V and A registers and EA 5 Flags affected SK 0 1160 1060 Exchange HL H L 1 Operation code 0 1 0 1 0 0 0 0 2 Number of bytes 1 3 Number of states 4 4 4 Function ELE Exchanges the contents of H and L registers with the contents of the H and L registers 5 Flags affected SK lt 0 11 0 10 0 BLOCK Block Data Transfer 1 Operation code 0 0 1 1 0 0 0 1 2 Number of bytes 1 3 Number of states 13 x C 1 4 4 Function DE lt HL DE lt DE 1 HL lt HL 1 C lt C 1 end if borrow Performs a block transfer to the memory addressed by the DE register pair comprising the number of bytes specified by the C
98. fixed and are shown in Table 9 1 Internal Priority External External Table 9 1 Priorities and Interrupt Addresses Interrupt Request Falling edge non maskable interrupt Interrupt Address Decimal Hexadecimal Internal Match signal from TIMERO Match signal from TIMER1 External Ri sing edge Falling edge Internal Match signal from timer event counter Match signal from timer event counter C pin or TO fall signal A D converter interrupt Serial reception interrupt Serial transmission interrupt SOFTI instruction 153 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9 1 Interrupt Control Circuit Configuration The interrupt control circuit consists of a request register a mask register a priority control a test control an interrupt enable F F IE F F and a test flag register Figure 9 1 Interrupt Control Circuit Block Diagram 0 l est Skip control control T F 4 Mask SOFTI register T Interrupt INTAD IE F F generation INTST Priority control gt m e Request register OV ER Test flag SB register AN7 4 Internal bus 1 Request register This register consists of 11 interrupt request flags which are set by the different interrupt requests A flag is reset when an interrupt request is ack
99. gt Count value setting ps Timer event counter mode setting lt d gt Rectangular wave output to CO0 97 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS a The timer event counter ECNT is cleared and COO output is driven low To drive the COO output low LVO is reset and that level is output to COO Figure 6 17 Timer Event Counter Mode Register Setting Programmable Rectangular Wave Output ECNT Clear COO Output Reset 7 6 5 4 3 2 1 0 SIEXEXENEIZEZEEZEIEX L Clear and stop ECNT 7 6 5 4 3 2 1 0 Output of contents LVO level inversion enabled LVO reset b The PC6 pin of port C is set as COO output Figure 6 18 Port C Setting Programmable Rectangular Wave Output PC6 as COO output c determine the low level width and cycle of the rectangular wave to be output to the COO pin 00C8H low level 200 us is set in ETMO timer event counter REGO and 01F4H cycle 500 us is ETM1 at 12 MHz operation d Timer event counter operation setting is performed by the timer event counter mode register Settings are as follows An internal clock 12 as the ECNT input clock a match between ECNT and 1 as the ECNT clear mode and a match between ECNT and ETMO or between ECNT and ETM1 as the COO output timing Timer event counter operation is started by setting the timer event counter mode register 98 CHAPTER 6 TIMER
100. have a noise elimination function to prevent errors due to noise signals 1 2 3 4 158 NMI input This is the falling edge active non maskable interrupt input When the NMI signal is detected to be low for atleast a given time by the analog delay circuit it is recognized as a normal signal and the INTFNMI interrupt request flag is set At the end of the instruction INTFNMI is checked and if set the program jumps to the interrupt address for non maskable interrupts regardless of the EI DI state When an interrupt request is acknowledged INTFNMI is automatically reset INT1 input This is the rising edge active maskable interrupt input When the INT1 signal changes from low to high and the high level is detected in 3 or more successive 1 cycle sampling pulses 12 states 2 4 us at 15 MHz the input is recognized as a normal signal and the INTF1 interrupt request flag is set When masking is released in the El state a check is made that the INTF1 is set at the end of the instruction and if there is no other interrupt request of higher priority the INT1 interrupt is acknowledged and the program jumps to the interrupt address Interrupt request flag resetting is described in 9 4 Maskable Interrupt Operation A new INT1 interrupt is detected when the INT1 signal is high for at least 12 states after first returning to the low level INT2 input This is the falling edge active maskable interrupt input Except for having th
101. ic resin thickness 2 7mm inter pin pitch 0 8 mm ceramic piggyback QUIP plastic shrink DIP ceramic shrink DIP with window plast plast ceramic WOFN plast ic QUIP resin thickness 2 7 mm ceramic QUIP with window plastic QUIP CHAPTER 1 GENERAL DESCRIPTION uPD78C17 78C17 A uPD78C uPD78C uPD78C uPD78C uPD78C Part number 7CW 7GF 3BE 7GQ 36 7GF A 3BE 7GO A 36 64 pin 64 pin 64 pin 64 pin 64 pin 6 uPD78C18 78C18 A 78CP18 78CP18 A uPD78C uPD78C uPD78C uPD78C uPD78C Part number 8CW xxx 8GF xxx 3BE 8 36 8GF A xxx 3BE 8GOQO A xxx 36 uPD78CP18CW uPD78CP18DW uPD78CP18GF 3BE uPD78CP18GQ 36 uPD78CP18KB uPD78CP18GF A 3BE uPD78CP18GO A 36 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin 64 pin Remark xxx indicates ROM code number plast plast plast plast plast plast plast plast plast plast plast Package ic shrink DIP ic OFP resin thickness 2 7 mm ic QUIP resin thickness 2 7 mm ic QUIP Package ic shrink DIP ic OFP resin thickness 2 7 mm ic QUIP resin thickness 2 7 mm ic QUIP ic shrink DIP ceramic shrink DIP with window plast plast resin thickness 2 7 mm ic QUIP ceramic WOFN plast plast resin thickne
102. in the specified special register Skips if no carry is generated as a result of the addition 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 272 CHAPTER 14 INSTRUCTION SET SUI A byte Subtract Immediate from A 1 Operation code O 1 1 0 O 1 1 0 2 Number of bytes 2 3 Number of states 7 7 4 Function 5 lt A byte Subtracts the immediate data in the 2nd byte from the contents of the accumulator and stores the result in the accumulator 5 Flags affected 7 lt 0 11 lt 0 LO lt 0 CY SUI byte Subtract Immediate from Register 1 Operation code O 1 1 0 O 1 1 0 O Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function r r byte Subtracts the immediate data in the 3rd byte from the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 and stores the result in the specified register b Flags affected Z SK e0 L1 0 LO lt 0 CY SUI sr2 byte Subtract Immediate from Special Register 1 Operation code O 1 1 0 O 1 0 0 Ss 1 1 0 0 52 51 50 lt 2 gt Number of bytes 3 3 Number of states 20 11 4 Function Sr2 lt sr2 byte Subtracts the immediate data in the 3rd byte from the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and stores the result in the
103. is added in addition to on chip memory PD7 PDO are used as a multiplexed address data bus AD7 to ADO When an instruction which references an external device is executed the lower address information for the external device is outputin the first state of the external device reference machine cycle of that instruction and the pins become a bidirectional 8 bit data bus in the second and third states Atall other times PD7 to PDO are high impedance Cautions 1 When pins PD7 to PDO are functioning as an address data bus the contents of the internal address bus are output as they are in synchronization with ALE in the first state of all machine cycles 2 Emulation cannot be performed by an emulator for a program which varies the port D operating mode dynamically Therefore once the mode has been set it should not be changed to a different mode Upon RESET input PD7 to PDO are set as input port high impedance PD7 to PDO also become high impedance in the hardware STOP mode 78 17 78 10 These pins function only as time division address output and data input output multiplexed address data bus pins for accessing externally installed memory The pins output the lower 8 bits of the memory address in the first state and become a bidirectional 8 bit data bus in the second and third states When the RESET signal is low or when in the hardware STOP mode or a standby mode HALT or STOP PD7 to PDO are high imped
104. lt 0 10 0 i MVI V 50H DCRW 0 5000 lt 5000 1 This example decrements the contents of the working register in address 5000H CHAPTER 14 INSTRUCTION SET DCX rp Decrement Register Pair 1 Operation code 2 Number of bytes 3 Number of states 4 Function i Decrements SP or the lt 5 gt Flags affected lt 6 gt Example DCX EA Decrement EA lt 1 gt Operation code lt 2 gt Number of bytes 3 Number of states 4 Function Decrements the exten b Flags affected 0 0 Pi Po 0 O 1 1 1 7 4 rp lt 1 contents of the register pair DE HL specified by 1 0 to SK 0 L1 lt 0 LO lt 0 DCX H HL HL 1 1 0 1 0 1 0 0 1 1 7 4 lt EA 1 ded accumulator SK lt 0 11 lt 0 10 lt 0 303 CHAPTER 14 INSTRUCTION SET 14 6 10 Other operation instructions DAA Decimal Adjust A 1 Operation code O 1 1 0 0 0 O 1 2 Number of bytes 1 3 Number of states 4 4 4 Function Determines the contents of the accumulator CY flag and HC flag and performs decimal adjustment as shown below This instruction is only meaningful after execution of an operation between decimal BCD data items Condition Operation lt 9 7 4 lt 9 0 lt HC 0 Az42 10 or CY 1 A lt A 01100000 gt 10
105. of these products from Japan is regulated by the Japanese government The export of some or all of these products may be prohibited without governmental license To export or re export some or all of these products from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative The customer must judge the need for license uPD78C11 78C11A 78C12A 78C14 78C14A 78CP14CW 78CP14G 36 78CP14GF 3BE 78CP14L 78C18 78CP18CW 78CP18GF 3BE 78CP18GO 36 78C11 A 78C11A A 78C12A A 78C14 A 78 14 78C18 A 78CP18 A License not needed uPD78C10 78C10A 78CG14 78CP14DW 78CP14KB 78CP14R 78C17 78CP18DW 78CP18KB 78C10 A 78C10A A 78C17 A The information in this document is subject to change without notice No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation NEC Corporation assumes no responsibility for any errors which may appear in this document NEC Corporation does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device No license either express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC Corporation or others While NEC Corporation has b
106. register FFH clears and stops the upcounter of both TIMERO TIMER1 and resets the timer F F 77 5 5 78 Figure 5 2 Timer Mode Register TMM Format 7 6 5 4 3 2 1 0 TMM 751 CK10 TSO TF1 Timer F F input amp operating mode specification TIMERO comparator match signal TIMER1 comparator match signal Internal clock Timer F F reset Internal clock 12 Internal clock External pulse TI pin falling edge input Disable Count up Reset TIMER input clock specification Internal clock 912 Internal clock 384 External pulse TI pin falling edge input TIMERO comparator match signal Count up Reset CHAPTER 5 TIMER FUNCTIONS 5 3 Timer Operations Interval timer operation is performed for the two timers using the following input clocks according to the specification of the timer mode register TMM 1 2 3 4 Internal clock 12 When the internal clock 12 is specified as the upcounter input clock the timer operates as an interval timer with an interval from 1 us to 256 us at 12 MHz operation with a 1 resolution of 1 us Internal clock 63a4 When the internal clock 384 is specified as the upcounter input clock an interval time from 32 us to 8 192 ms can be selected a
107. register used as a counter C register value 1 of the contents of the memory addressed by the HL register pair Each time a byte is transferred HL and DE are auto incremented and the C register is decremented When the C register value reaches FFH the instruction is terminated and the program moves on to the next instruction Interrupts can be acknowledged during repeated transfers by means of a BLOCK instruction in which case the transfer continues after returning from the interrupt service routine 5 Flags affected gt SK 0 L1 0 10 0 241 CHAPTER 14 INSTRUCTION SET 14 6 2 16 bit data transfer instructions DMOV rp3 EA Move EA to Register Pair 1 Operation code 1 0 1 1 0 1 Pr Po 2 Number of bytes 1 3 Number of states 4 4 4 Function k lt EAL lt EAH Transfers the contents of the lower half EAL of the extended accumulator to the lower register C E L of the register pair rp3 DE HL specified by P Po 1 to 3 and the contents of the upper half EAH to the upper register B D H of the register pair 5 Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example DMOV B EA C lt EAL B lt EAH DMOV EA rp3 Move Register Pair to EA 1 Operation code 1 0 1 0 0 1 Po 2 Number of bytes 1 3 Number of states 4 4 4 Function 5 EAL lt lt 3 Transfers the contents of the lower re
108. specified special register b Flags affected Z SK 0 HC L1 0 LO lt 0 CY 273 CHAPTER 14 INSTRUCTION SET SBI A byte Subtract Immediate from A with Borrow 1 Operation code 0 1 1 1 0 1 1 0 2 Number of bytes 2 3 Number of states 7 7 4 Function A lt A byte CY Subtracts the immediate data in the 2nd byte including the CY flag from the contents of the accumulator and stores the result in the accumulator 5 Flags affected Z SK lt 0 L1 0 10 lt 0 CY 6 Example SBI A lt A 30H CY This example subtracts 30H from A including the CY flag SBI r byte Subtract Immediate from Register with Borrow 1 Operation code O 1 1 1 0 0 O 1 1 1 O R2 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function r r byte CY Subtracts the immediate data in the 3rd byte including the CY flag from the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 and stores the result in the specified register 5 Flags affected Z SK lt 0 L1 amp 0 LO 0 CY SBI sr2 byte Subtract Immediate from Special Register with Borrow 1 Operation code 0110 1 0 0 S 1 1 1 0 S 1 50 2 Number of bytes 3 3 Number of states 20 11 4 Function sr2 lt sr2 byte CY Subtracts the immediate data in the 3rd byte including the CY flag from the contents of the spe
109. the TxD pin Transmit buffer register This register is used to write the parallel data to be transmitted when serial register data transmission ends the contents of the transmit buffer register are transferred to the serial register When the buffer register becomes empty an interrupt request INTST is generated Transmission control circuit This circuit performs all control required for serial data transmission and generates related internal signals Reception unit a Serial register S P This register converts serial data input from the RxD pin into parallel data and transfers it to the receive buffer register Receive buffer register Parallel data converted by the serial register is transferred to this register When the receive buffer register becomes full an interrupt request INTSR is generated Reception control circuit This circuit performs all control required for serial data reception and also sets the ER flag if a serial error is generated The ER flag can be checked by an SKIT instruction Resetting the ER flag does not affect the receive buffer Serial mode registers These are two 8 bit registers which control the operating mode of the serial interface see 7 2 Serial Mode Registers for details As the serial interface has a serial register and a buffer for send and receive operations it can send and receive data independently full duplex double buffer method transmitter receiver However a
110. the interrupt request flag of the unmasked interrupt 1 set In the HALT mode the CPU clock stops and program execution also stops However the contents of all registers and on chip RAM just before the stoppage are retained In the HALT mode the timer timer event counter serial interface A D converter and interrupt control circuit are operational Table 10 1 shows the status of the uPD78C18 output pins in the HALT mode Cautions 1 Table 10 1 Output Pin Statuses Output Pin Single ChipNote 1 External Expansion PA7 to Data retained Data retained PB7 to PBO Data retained Data retained PC7 to PCO Data retained Data retained PD7 to PDO Data retained High impedance PF7 to PFO Data retained Next address retainedNote 2 Data retainedNote 3 WR RD High level High level ALE High level High level Notes 1 4uPD78C18 78C14 78C144 78C12A 78C11A 78CP18 78CP14 2 Address output pin 3 Port data output pin Because an interrupt request flag is used to release the HALT mode HLT instruction execution does not set the HALT mode if even a single interrupt request flag for an unmasked interrupt is set Thus when setting the HALT mode when there is a possibility that an interrupt request flag may have been set when there is a pending interrupt one of the following procedures should be followed First process the pending interrupt or reset the interrupt request flag by executing a skip instruction or
111. 0 2 Number of bytes 3 3 Number of states 11 11 4 Function r byte Skip if zero Subtracts the immediate data in the 3rd byte from the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 Skips if the result of the subtraction is not zero rzbyte 5 Flags affected Z SK HC L1 lt 0 LO 0 CY NEI sr2 byte Not Equal Immediate with Special Register 1 Operation code O 1 1 0 O 1 0 0 Ss 1 1 0 1 52 Si So 2 Number of bytes 3 3 Number of states 14 11 4 Function sr2 byte Skip if no zero Subtracts the immediate data in the 3rd byte from the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D Skips if the result of the subtraction is not zero sr2zbyte b Flags affected Z SK HC L1 lt 0 LO 0 CY 281 CHAPTER 14 INSTRUCTION SET EQI A byte Equal Immediate with A 1 Operation code O 1 1 1 O 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function A byte Skip if zero Subtracts the immediate data in the 2nd byte from the contents of the accumulator Skips if the result of the subtraction is zero A byte 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY byte Equal Immediate with Register 1 Operation code O 1 1 1 0 2 Number of bytes 3 3 N
112. 0 0 0 1 1 1 1 0 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function gt A r CY Subtracts the contents of the register r V A B C D H L specified by R2R1Ro 0 to 7 including the CY flag from the contents of the accumulator and stores the result in the accumulator b Flags affected Z SK 0 L1 lt 0 LO lt 0 CY 6 Example 2 SBB A L lt A L CY SBBr A Subtract A from Register with Borrow 1 Operation code 0 1 1 0 0 0 0 O 1 1 1 0 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function r r A CY Subtracts the contents of the accumulator including the CY flag from the contents of the register r V A B C D E H L specified by R2R Ro 0 to 7 and stores the result in the specified register 5 Flags affected Z SK 0 HC L1 lt 0 LO lt 0 CY 6 Example SBBB A lt B A CY 255 CHAPTER 14 INSTRUCTION SET SUBNB A r Subtract Register from A Skip if No Borrow 1 Operation code O 1 1 0 0 0 0 0 1 O 1 1 0 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function lt Skip if no borrow Subtracts the contents of the register r V A B C D E H L specified by Ra2R Ro 0 to 7 from the contents of the accumulator and stores the result in the accumulator Skips if no borrow is generated as a result of the subtraction 5 Flags affect
113. 0H INTEIN INTAD FEFFH FFOOH 5 amp oO 0028H INTSR INTST E 0060H SOFT 0080H LOW ADRS 0081 HIGH ADRS i gt 0082H LOW ADRS t 1 3 0083H HIGH ADRS 5 O 00 LOW ADRS HIGH ADRS User s area 1FFFH Note Can only be used when the RAE bit of the MM register is 1 55 3 INTERNAL BLOCK FUNCTIOS Figure 3 12 Memory Map uPD78C11A Mode 0000 0000H On chip EPROM 0004H 4096 x 8 bit 0008H INTTO INTT1 OFFFH 1000H 0010H INT1 INT2 External memory 61184 x 8 bit 0018H INTEO INTE1 0020H INTEIN INTAD FEFFH FFOOH to Note nenie RAM ES 0028H INTSR INTST E 0060H SOFT 0080H LOW ADRS 0081 HIGH ADRS B a 0082H LOW ADRS t 1 0083H HIGH ADRS 5 O 00 LOW ADRS 00BFH HIGH ADRS EM User s area OFFFH Note Can only be used when the RAE bit of the MM register is 1 3 INTERNAL BLOCK FUNCTIONS 3 6 Timers The timer system comprises two 8 bit interval timers The two interval timers can also be cascaded to operate as a 16 bit interval timer The elapse of the interval time can be identified by the generation of a timer interrupt In addition a square wave with the interval time as a half cycle is obtained from the TO pin see CHAPTER 5 TIMER FU
114. 1 0 10 0 316 CHAPTER 14 INSTRUCTION SET CALF word Call Subroutine in Fixed Area lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Operation code 0 1 1 1 1 Number of bytes 2 Number of states 13 7 Function SP 1 lt PC 215 8 5 2 lt PC 27 0 SP lt SP 2 5 11 00001 PC10 0 lt fa Stores the high order 8 bits of the start address of the next instruction in the stack memory indicated by 5 1 and stores the low order 8 bits in the stack memory indicated by 5 2 then loads 00001 into the high order 5 bits PC15 11 of the program counter and loads the 11 bit immediate data fa into the low order 11 bits PC10 0 and jumps to the address indicated by the immediate data A label or number from 800H to FFFH 2K byte range should be directly as the operand of the CALF instruction Flags affected SK 0 L1 0 L0 0 CALT word Call Table Address lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Operation code 1 Number of bytes Number of states 16 4 Function SP 1 lt PC 115 8 5 2 lt PC 17 0 SP lt SP 2 PC7 0 lt 128 2ta PCis 8 lt 129 2ta 15 8765 1 0 0000000010 ta 0 Effective address Effective address High address Memory Jump address table Effective address 1 Stores the high order 8 bits of the start address of the next instruction in the stack memory indicated by SP 1 and stores the low o
115. 13 2 PROM Programming Modes ustedes deeem he tee per prete sd eda Luce Beaune 208 3 3 Recommended Connection of Unused Pins In PROM Programming Mode 208 5 1 Compare Register Match Signal and Match Interrupt of Each Timer 328 xi CHAPTER 1 GENERAL DESCRIPTION CMOS version products in the 87AD series have the following functions integrated in a single chip e except uPD78C17 78C10A e RAM e 16 bit ALU e A D converter e Multi function timers event counters e General purpose serial interface etc 87AD series CMOS products offer enhanced standby functions and a wide range of packages while maintaining compatibility with existing NMOS products This allows further reductions in system low power consumption and size to be achieved The features of the various products are shown below Product Name PD78C10A uPD78C10A A On Chip ROM None On Chip RAM 256 x 8 bits External Expansion Memory Up to 64K bytes Remarks ROM less product PD78C11A uPD78C11A A x 8 bits 256 x 8 bi Up to 60K bytes On chip pull up resistor specifiable PD78C uPD78C 8K x 8 bits 256 x 8 bi Up to 56K bytes On chip pull up resistor specifiable PD78C PD78C uPD78C PD78CP14 78 14 16K x 8 bits uPD78CG14 16K x 8 bits external 256 x 8 bi Up to 48K bytes On chip pull up
116. 14 pull up resistors can be incorporated bit wise 23 CHAPTER 2 PIN FUNCTIONS Table 2 1 Operation of PC7 to PCO 0 Port Mode Control Signal Input Output Mode Input output por TxD output Input output por RxD input Input output por SCK input output Input output por INT2 TI input Input output por TO output Input output por input Input output por COO output Input output por CO1 output Remark 0 to 7 1 Port mode When PC7 to PCO are specified as input output port by means of the mode control C register they can be set bit wise as input or output port by means of the mode C register MC 2 Control signal input output mode PC7 to PCO can be set bit wise as control pins by means of the mode control C register MCC The functions of the various control pins are shown below a b c d e f g TxD Transmit data Output The serial data transmission pin from which the contents of the serial register are output RxD Receive data Input The serial data reception pin Data on RxD is loaded into the serial register SCK Serial clock Input output The serial input output data control clock Functions as an output when the internal clock is used and as an input when an external clock is used INT2 TI Interrupt request Timer input Input The edge triggered falling edge maskable interrupt input pin
117. 39IA3Q TVNH31X3 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND 5 Figure 11 6 Memory Map uPD78C18 0000H 7FFFH 8000H BFFFH FBFFH FCOOH FFFFH On chip ROM 32K bytes External expansion RAM 16K bytes External expansion On chip Note Can only be used when the RAE bit of the MM register is 1 Figure 11 7 Memory Map uPD78C14 78C14A 0000H 4000H 7FFFH 8000H BFFFH CO00H FEFFH FFOOH FFFFH On chip ROM 16K bytes External expansion ROM 16K bytes External expansion ROM 16K bytes External expansion O On chip Note Can only be used when the RAE bit of the MM register is 1 196 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND Tif Figure 11 8 Memory uPD78C124A 0000H On chip ROM 8K bytes 1FFFH 2000H External expansion ROM 24K bytes 7FFFH 8000H External expansion RAM 16K bytes BFFFH C000H External FEFFH expansion FFOOH F On chip FFFFH Note Can only be used when the RAE bit of the MM register is 1 Figure 11 9 Memory Map uPD78C11A 0000H On chip ROM bytes 1FFFH 1000H External expansion ROM 28K bytes 7FFFH 8000H External expansion RAM 16K bytes BFFFH CO00H External FEFFH expansion I O FFOOH On chip FFFFH Note Can only used when the RAE bit of the MM register is 1 197 CHAPTER 11
118. 5 6 110 TxE bit 2 This bit determines whether or not the operation is a transmit operation When the bit is reset 0 the TxD pin is driven high and data transmission is not performed When the TxE bit is set 1 data transmission is enabled and if data has previously been written into the transmit buffer register that data is output Alternatively when data is written into the transmit buffer register serial data is transmitted from the TxD pin However when the TxE bit is changed from the set 1 status to the reset 0 status transmission is disabled after the data in the serial register has been transmitted Therefore when there is data in both the transmit buffer register and the serial register transmission is disabled after the serial register data has been transmitted and the transmit buffer register data is retained without being transmitted The data in the transmit buffer register is transmitted as serial data when transmission is next enabled 1 Thus when transmission is to be disabled TxE 0 after all transmit data has been transmitted itis necessary to check that the serial transmission interrupt request flag INTFST is set 1 and the transmit buffer register is empty before executing the operation RxE bit 3 Controls whether or not a receive operation is performed When the RxE bit is reset 0 data reception is not performed When the RxE bit is set 1 data reception is enabled SE b
119. 56K uPD78C12A 60K uPD78C11A The operation of the 78 18 and 78CP14 differ depending on the setting of bits to of the memory mapping register uPD78C17 78C10A These pins function as address outputs corresponding to the size of externally installed memory according to the MODEO and MODE pin settings Pins which are not used as address outputs can be used as general purpose input output port pins which have the same port functions as port A with input output setting performed by the mode F register Table 4 3 Operation of PF7 to PFO uPD78C17 78C10A External Address Space 11 10 AB8 bytes 11 10 AB8 16K bytes Setting prohibited 11 10 AB9 AB8 63K 64K bytesNote Note 63K uPD78C17 64K uPD78C10A Cautions 1 Pins not used as address bus pins output the internal address bus status in all machine cycles When the address changes undefined data is output 2 Emulation cannot be performed by an emulator for a program which varies the port F operating mode dynamically Therefore once the mode has been set it should not be changed to a different mode When the 63K 64K byte mode is used with the uPD78C17 78C104 instructions which output data to port D or port F should not be executed if such an instruction is executed the WR signal will be output 72 4 5 4 6
120. 64 pin 78 12 64 78 12 36 64 78 12 37 64 uPD78C12AL xxx 68 pin 78 12 64 78 12 36 64 78 12 68 Remark indicates ROM code number Package plastic shrink DIP p p p p ast ast ast ast ast ast ast ic OFP resin thickness 2 7 mm ic QUIP ic QUIP straight ic OFJ ic resin thickness 2 7 mm ic QUIP ic OFJ 1 GENERAL DESCRIPTION 4 uPD78C14 78C14 A 78C14A 78CG14 78CP14 78CP 14 A uPD78C uPD78C uPD78C uPD78C uPD78C uPD78C uPD78C uPD78C uPD78C uPD78C Part number 4CW xxx 4G xxx 36 4G xxx 37 4G xxx 1B 4GF xxx 3BE AL xxx AG A xxx 36 AGF A xxx 3BE AL A xxx 4 8 uPD78CG14E uPD78CP14CW uPD78CP14DW uPD78CP14G 36 uPD78CP14GF 3BE uPD78CP14KB uPD78CP14L uPD78CP14R uPD78CP14G A 36 64 pi 64 pi 64 pi 64 pi 64 pi 68 pi 64 pi 64 pi 68 pi 64 pi 64 pi 64 pi 64 pi 64 pi 64 pi 64 pi 68 pi 64 pi 64 pi Remark xxx indicates ROM code number n 42 5 5 n n n Package plastic shrink DIP plast p p p p ast ast ast ast ast ast ast ast ic QUIP ic QUIP straight ic OFP resin thickness 2 05 mm ic OFP resin thickness 2 7 mm QUIP
121. 7 010 lt 2 gt Number of bytes 1 lt 3 gt Number of states 4 4 lt 4 gt Function Sets the interrupt enabled state Interrupts are actually enabled after execution of the instruction return instruction etc located after the instruction and excess stack space is not used for subsequently occurring interrupts Non maskable interrupts and the SOFTI instruction can be executed at all times without regard to the El instruction 5 Flags affected SK 0 L1 0 10 0 6 Example PUSH B A PUSH D Interrupts disabled Next interrupt enabled POPD POP B Y Y RETI 323 CHAPTER 14 INSTRUCTION SET DI Disable Interrupt 1 Operation code 1 0 1 1 1 0 1 0 2 Number of bytes 1 3 Number of states 4 4 4 Function Sets the state in which all interrupts except non maskable interrupts and interrupts generated by the 5 instruction are disabled Execution of the DI instruction sets the interrupt disabled state during execution of the DI instruction lt 5 gt Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example CALL JYUYO Interrupts enabled v JYUYO PUSH A PUSH PUSH PUSH DI 7 Interrupts enabled lt El RET Y Interrupts disabled lt Halt 1 Operation code O 1 0 1 0 0 0 2 Number of bytes 2 3 Number of state
122. 7 4 lt 9 CY 0 00000110 HC 0 74 gt 9 or CY 1 A 01100110 1 7 4 lt 9 0 A lt 00000110 gt 10 CY 1 lt 01100110 b Flags affected Z SK lt 0 L1 lt 0 10 lt 0 CY 6 Example MVI 88 ADI A 79H A 01H CY 1 1 DAA A lt A 66H A 67H 1 88479 2167 10001000 88H ADI 01111001 79H 00000001 01H DAA Carry HC 01100110 66H 01100111 67H lt 7 gt Caution This instruction cannot be used for adjustment after execution of a subtract instruction When decimal BCD data subtraction is performed a complement instruction should be used 304 CHAPTER 14 INSTRUCTION SET STC Set Carry 1 Operation code O 1 0 O 1 0 0 0 0 0 1 0 1 0 1 1 2 Number of bytes 2 3 Number of states 8 8 4 Function CY 1 Sets 1 the CY flag 5 Flags affected 5 lt 0 11 lt 0 10 lt 0 lt 1 Clear Carry 1 Operation code O 1 0 1 0 0 0 0 0 1 0 1 O 1 2 Number of bytes 2 3 Number of states 8 8 4 Function CY 0 Sets 0 the CY flag 5 Flags affected 0 11 lt 0 10 lt 0 CY 0 1 Operation code O 1 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function DO ACA Obtains the two s complement of the accumulator contents 5 Flags affected SK 0 1160
123. 8 CR2 H 10 18 ARIN ARSTO A D A 5 1 A E A ARST2 H 4000 D 0101 C 01H RET1 2 4020 1 4004 D A RETO H 4024H A D 00H C 00 B 03 ANM 08H H R H R Save accumulator Save register Store A D conversion data Store A D conversion data Store A D conversion data Store A D conversion data Set data pointer Set counter Set counter Increment HL Set data pointer Set data pointer Set data pointer Invert ANI2 bit Recover accumulator Recover register Enable interrupt Return memory memory memory memory Decrement counter skip if borrow Y P CN OE NND V a b lt C gt lt d gt lt gt lt f gt lt b gt lt C gt lt d gt lt e gt 151 152 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS There are 3 kinds of external interrupt request NMI INT1 INT2 and 8 kinds of internal interrupt requests INTTO INTT1 INTEO INTE1 INTEIN INTAD INTSR INTST plus a software interrupt instruction SOFTI The 11 kinds of interrupt requests excluding the SOFTI instruction are divided into 6 groups each of which is assigned a different priority The interrupt addresses for the 6 interrupt request groups and the SOFTI instruction are
124. 8 78C14 78C14A 78CP14 78C12A 78C1 1A 28 uPD78C17 78C10A Edge detected inputs 4 inputs Zero cross detection function Standby functions HALT mode e Hardware software STOP mode e Incorporation of pull up resistors can be specified bit wise for port A and port C Note On chip clock oscillator Wide variety of packages Note 4PD78C18 78C14A 78C12A 78C11A only CHAPTER 1 GENERAL DESCRIPTION 1 2 Ordering Information and Quality Grade 1 2 1 Ordering information 1 uPD78C10A 78C10A A Part number Package uPD78C10ACW 64 pin plastic shrink DIP uPD78C10AGF 3BE 64 pin plastic resin thickness 2 7 mm uPD78C10AGO 36 64 pin plastic QUIP uPD78C10AL 68 pin plastic uPD78C10AGF A 3BE 64 pin plastic OFP resin thickness 2 7 mm uPD78C10AGO A 36 64 pin plastic QUIP uPD78C10AL A 68 pin plastic 2 uPD78C11A 78C11A A Part number Package uPD78C11ACW ex 64 pin plastic shrink DIP uPD78C11AGF ooc 3BE 64 pin plastic OFP resin thickness 2 7 mm 78 11 36 64 plastic QUIP 78 11 37 64 plastic QUIP straight uPD78C11AL xxx 68 pin plastic uPD78C11AGF A o2coc 3BE 64 pin plastic OFP resin thickness 2 7 mm uPD78C11AGO A 2cc 36 64 pin plastic QUIP uPD78C11AL A xxx 68 pin plastic QFJ Remark xxx indicates ROM code number CHAPTER 1 GENERAL DESCRIPTION 3 uPD78C12A 78C12A A Part number uPD78C12ACW xxx
125. 8C14A 48K bytes addresses 4000H to FEFFH e pPD78C12A b6K bytes addresses 2000H to FEFFH e uPD78C11A 60K bytes addresses 1000H to FEFFH External memory be expanded in steps in a 63K byte area addresses 0000H to FBFFH for the uPD78C17 and in a 64K byte area addresses OOOOH to FEFFH for the uPD78C10A This setting is performed by the MODEO and The external memory is accessed using PD7 to PDO multiplexed address data bus PF7 to address bus and the RD WR and ALE signals Both programs and data can be stored in the external memory Working register area A 256 byte working register area can be set in any memory locations specified by the V register 45 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 46 Figure 3 3 Memory Map uPD78C18 0000H 0000H On chip ROM 0004H 32768 x 8 bit 0008H INTTO INTT1 7FFFH 8000H 0010H INT1 INT2 External memory 31744 x 8 bit 0018H INTEO INTE1 0020H INTEIN INTAD FBFFH FCOOH On chip RAM 0028H INTSR INTST 1024 x 8 bit Standby area FFFFH 0060H SOFT 0080H LOW ADRS 0 0081 HIGH ADRS ivt 0082H LOW ADRS 2 t 1 0083H HIGH ADRS 55 00BEH LOW ADRS 00BFH HIGH ADRS iG Note Can only be used when the RAE bit of the MM register is 1 User s area CHAPTE
126. AX HL LDAX H A HL JMP KORED Memory 4000H 20H 4100H 30H In this example since the contents of A contents of address 4000H 20H are less than the memory contents addressed by the HL register pair contents of address 4100H 30H the LDAX instruction is skipped and the JMP instruction is executed The CY SK and HC flags are set as a result of this subtraction rpa Not Equal Memory addressed by Register Pair with A lt 1 gt Operation code O 1 1 1 0 0 0 0 lt 2 gt Number of bytes 2 lt 3 gt Number of states 11 8 lt 4 gt Function lt Skip if no zero Subtracts the contents of the memory addressed by the register pair DE DE HL DE HL specified by A2A1Ao 1 to 7 from the contents of the accumulator Skips if the result of the subtraction is no zero Az rpa lt 5 gt Flags affected Z SK HC L1 0 LO 0 CY 6 Example SKIP IF A BC 268 CHAPTER 14 INSTRUCTION SET EQAX rpa Equal Memory addressed by Register Pair with A 1 Operation code O 1 1 1 0 0 0 0 1 1 1 1 1 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function A rpa Skip if zero Subtracts the contents of the memory addressed by the register pair DE HL DE HL D HL specified by A2A1Ao 1 to 7 from the contents of the accumulator Skips if the result of the subtracti o
127. C Ote dd Electronic musical instrument POS Point of sales terminal inverter electronic sewing machine auto focus cameras etc The Special Products e Automobile Automobile electronic equipment fuel control CHAPTER 1 GENERAL DESCRIPTION 1 1 Features 159 types of instructions e Multiplication division instructions 16 bit operation instructions possible Minimum instruction execution time 0 8 us at 15 MHz operation ROM capacity e 32768 x 8 bits uPD78C18 78CP18Note 1 e 16384 x 8 bits uPD78C14 78C14A 78CP14Nete 1 e 8192 x 8 bits 78 12 e 4096 x 8 bits uPD78C114 ROM less 78 17 78 10 RAM capacityNote 2 1024 x 8 bits uPD78C18 78CP18 78C17 256 x 8 bits uPD78C14 78C14A 78CP14 78C12A 78C1 1A 78C10A 8 bit resolution A D converter 8 channels General purpose serial interface e Asynchronous mode e Synchronous mode e O interface mode 16 bit timer event counter e 1 channel 8 bit timer e 2 channels nterrupt functions 3 external 8 internal e Non maskable interrupt 1 Mlaskable interrupts 10 6 priority levels 6 interrupt addresses Notes 1 4PD78CP18 78CP14 have on chip one time PROM or EPROM 2 On chip RAM can only be used when the RAE bit of the MM register is 1 CHAPTER 1 GENERAL DESCRIPTION O lines e nput output ports 40 uPD78C18 78CP1
128. C register pair or the EA accumulator are loaded into the PC and a jump is performed This is performed when the following instructions are executed JB CALB 7 07 0 Y 15 87 0 JEA 216 CHAPTER 14 INSTRUCTION SET 14 3 2 Immediate addressing The immediate data in the 2nd and 3rd bytes of the instruction is loaded into the PC and a jump is performed This is performed when the following instructions are executed JMP word CALL word CALF word In the case of the CALF instruction the immediate data in the low order 3 bits of the 1st byte and the 2nd byte is loaded into the PC CALL or JMP Low address High address 217 CHAPTER 14 INSTRUCTION SET 14 3 3 Direct addressing The contents of the memory addressed by the immediate data in the low order 5 bits of the operation code are loaded into the PC and a jump is performed This is performed when the following instruction is executed CALT word 7654 0 15 8765 10 Effective address 00000000 10 ta 0 Memory Effective address Low address Effective address 1 High address PC 14 3 4 Relative addressing The result of adding the immediate data displacement value jdisp1 in the low order 6 bits of the operation code to the start address of the next instruction is loaded into the PC and a jump is performed The displacement value is handled as signed two s complement data 32 to 31 with bit 5 as the si
129. EVENT COUNTER FUNCTIONS The INTEIN interrupt service program is shown below A JMP EINSV instruction must be stored in the INTEIN interrupt start address 0020H TIMER EVENT COUNTER SERVICE EINSV EXA EXX DMOV LXI DADD DMOV LXI DADD DMOV MVI MOV ORI ANI EXX EXA 0064 B 00C8H EA B 1 EA A 34H ETMM A EOM MKL OBFH Save accumulator Save register Low level 100 us at 12 MHz Set count value High level 200 us at 12 MHz Set count value Set level F F inversion enable INTEIN INTE1 enable Recover register Recover accumulator TEO masking TE1 masking released lt a gt b lt C gt After the interrupt service program by INTEIN an internal interrupt INTE1 is generated when the contents of ECNT ETM1 are the same The flowchart of this interrupt processing is shown below 104 CHAPTER 6 TIMER EVENT COUNTER Timer event counter mode setting See Interrupt mask b register setting SO lt a gt COO output operation is stopped by setting the timer event counter output mode register lt b gt INTE1 interrupts are masked disabled by setting the interrupt mask register MKL S TIMER EVENT COUNTER SERVICE 15 MVI EOM 00H lt a gt ORI MKL 40H INTE1 disable b EI RETI 105
130. EXTERNAL DEVICE ACCESSES AND TIMINGS 11 2 uPD78C17 78C10A External Device Access As the uPD78C17 78C10A have no on chip ROM it is possible to install an external device program memory data memory or a peripheral device in an external 63K byte area 0000H to FBFFH 64K byte area 0000H to FEFFH in addition to on chip RAM The address space of an externally installed device is set by the MODEO and MODE1 pins with a choice of 4K bytes addresses 0000H to OFFFH 16K bytes addresses 0000H to 3FFFH or 63K bytes addresses 0000H to FBFFH 64K bytes addresses 0000H to FEFFH Control Pins Operation Mode MODE1 MODEO External Address Area On Chip RAM Area 4K byte access AK bytes addresses 0000 to OFFFH Address FFOOH to FFFFH 16K byte access 16K bytes addresses 0000 to 3FFFH Addresses FFOOH to FFFFH Setting Prohibited 63K byte access bytes addresses 0000H to FBFFH Addresses FCOOH to FFFFH uPD78C17 only 64K byte access bytes addresses 0000H to FEFFH Addresses FFOOH to FFFFH uPD78C10A only The external device is accessed using the RD WR and ALE signals with pins PD7 to PDO functioning as a multiplexed address data bus AD7 to ADO and pins PF7 to PFO as an address bus AB15 to AB8 When accessing a4K byte or 16K byte area external device pins PF7 to PFO which are not used as address lines can be used as general purpose input output port pins The size
131. F Reference voltage Dual function as A D converter reference voltage input pin and A D converter operation control pin Analog VoD A D converter power supply AVss Analog Vss converter GND pin X1 X2 Crystal System clock oscillation crystal connected inputs When clock is supplied externally it is input to X1 Input inverted phase clock of X1 to X2 RESET Reset Low level active system reset input STOP Stop Hardware STOP mode control signal input pin When driven low oscillator operation stops VoD Positive power supply pin Vss GND pin Note Should be pulled up The pull up resistor R specification is 4 kQ lt R 0 4 tcvc in ns units 341 APPENDIX INTRODUCTION PIGGYBACK PRODUCT 1 2 Upper pins 27C256 27C256A compatible Pin Name Input Output Function Outputs 14 bits PCO to PC13 of program counter comprising 27C256 27C256A address signals Ao to A13 After Reset Undefined data to 07 read from 27 256 27 256 Supplies chip enable signal to 27C256 27C256A CE pin High in hardware software STOP amp HALT mode low at all other times Supplies Vcc power supply Ver to 27C256 27C256A at same potential as lower VoD pin Supplies Vcc power supply Vcc to 27 256 27 256 at same potential as lower VoD pin Connected to 27C256 27C256A
132. FNMI set at the end of each instruction If INTFNMI is set a non maskable interrupt is acknowledged at INTFNMI is reset ii When the non maskable interrupt is acknowledged the IE F F is reset and all interrupts except for non maskable interrupts and the SOFTI instruction are placed in the disabled state DI state iii PSW PC high byte and PC low byte are saved into the stack memory in that order The program jumps to the interrupt address 0004H These interrupt operations are automatically carried out in 16 states Caution Operations when a non maskable interrupt is generated directly after a maskable interrupt 1 The PC value at the time of the interrupt is saved to the stack 2 The vector address of the maskable interrupt is stored in the PC and the corresponding interrupt request flag is reset 3 Non maskable interrupt servicing is executed before execution of the maskable interrupt routine 4 The non maskable interrupt routine is executed In this case the return destination from the non maskable interrupt routine is the maskable interrupt routine 160 CHAPTER 9 INTERRUPT CONTROL Figure 9 4 Interrupt Operation Procedure End of instruction All masked Check nonmasked Reset INTFNMI INTEx 2 or more Number of flags set Other interrupt Y Next instruction Check priority Pending Highest priority interrupt
133. FO Port ALE Address Latch Enable NMI Non Maskable Interrupt RESET Reset INT1 Interrupt Request VAREF Reference Voltage MODEO 1 1 STOP Stop Control Input 11 CHAPTER 1 GENERAL DESCRIPTION 12 2 EPROM mode uPD78CP18 78CP14 only Cautions lt 1 gt lt 2 gt lt 3 gt 1 2 VPP A20 3 O 07 4 06 4 5 O5 6 O 04 7 03 8 02 9 01 O 10 00 O 11 O lt 2 gt 12 14 lt 3 gt 13 1 O 14 OA12 CEO 15 11 16 O A10 17 O lt gt 8 O A8 O 9 O lt 2 gt 4 S O J O O O O LO O A9O O lt 1 gt O MODE1 O RESET O MODEO O O 250 O 9 O J Connect directly to Vss Pull down individually to Vss potential via a resistor 78 18 only In case of 78 14 pull down to Vss potential via a resistor CHAPTER 1 GENERAL DESCRIPTION 1 3 2 1B 3BE WOFN 1 Normal operation mode 02 QN lt lt lt lt lt lt gt n0 0 0 0 64 63 62 61 60 59 54 53 52 PAG 1 51 o PD2 2 50 o PD1 PBOO 3 49 1 4 48 7 2 5 47 14 6 46 PF5 PB4 7 45 4 8 44 o PF3 PB6 9 43 o PF2 7 10 42 o 1 PCO TxD 11 41 o PF
134. H 1 External memory 0010H INT1 INT2 65280 x 8 bit 0018H INTEO INTE1 0020H INTEIN INTAD D On chip E 256 x 8 bit 8 5 0028H INTSR INTST 2 0060H SOFTI 0080H LOW ADRS E 0081H HIGH ADRS E ol 0082H LOW ADRS E 38 0083H HIGH ADRS T LOW ADRS t 31 HIGH ADRS Note Can only be used when the RAE bit of the MM register is 1 51 3 INTERNAL BLOCK FUNCTIOS 3 5 2 uPD78CP18 78CP14 memory configuration The uPD78CP18 can operate in any of 4 modes and the uPD78CP14 in any of 3 modes according to the MM register mode specification e uPD78C18 modeNote e uPD78C14 mode e J uPD78C12A mode e uPD78C11A mode Note Only the uPD78CP18 can operate in this mode In addition the on chip ROM address range can be specified to allow efficient mapping of external memory excluding PROM The vector area and call table area are the same in all modes Setting the hardware software STOP mode or HALT mode allows on chip RAM data to be retained with a low consumption current The memory map for each mode is shown in Figures 3 9 to 3 12 52 3 INTERNAL BLOCK FUNCTIONS Figure 3 9 Memory Map uPD78C18 Mode 0000H 0000H On chip EPROM 0004H 32768 x 8 bit 0008H INTTO INTT1 7FFFH 8000H 0010H INT1 INT2 External memory 31744 x 8 bit 0018H INTEO INTE1 0020H INTEIN INTAD FBFFH FCOOH
135. Interrupts External 3 Internal 8 Timer counter 8 bit timer x 2 16 bit timer event counter x 1 A D converter 8 bit x 8 channels Serial interface UART full duplex clocked linesNote 44 32 Package Note Incorporation of pull up resistors be specified by mask option for port and port C of the uPD78C144 78C18 64 pin plastic shrink DIP 750 mil e 64 pin plastic QFP 14 x 20 mm 64 pin plastic QUIP e 68 pin plastic 64 pin ceramic shrink DIP with window 750 mil 64 pin ceramic QUIP with window 64 pin ceramic WOFN 64 pin ceramic piggyback QUIP 64 pin plastic shrink DIP 750 mil 64 pin plastic OFP 14 x 20 mm 64 pin plastic QUIP 64 pin plastic shrink DIP 750 mil 64 pin plastic OFP 14 x 20 mm 64 pin plastic QUIP 64 pin ceramic shrink DIP with window 750 mil 64 pin ceramic WOFN NOlLdIlHOS3G 1VH3N3O9 1 YALdVHO 1 GENERAL DESCRIPTION 1 6 Differences between 87AD Series CMOS and NMOS Products Process Product name uPD78C18 78C17 78C14 78C14A 78C12A 78C11A 78C10A uPD7811 7810 Instructions 159 STOP instruction added Special registers 28 ZCM register added 27 Standby function 3 modes HALT mode software STOP mode hardware STOP mode On chip RAM data retained at low supply voltage 2 5 V in software hardware STOP mode
136. K 0 1160 10 0 6 Example INX D DE lt DE 1 In this example the 16 bit register with D as the high order 8 bits and E as the low order 8 bits is incremented 301 CHAPTER 14 INSTRUCTION SET INX EA Increment EA lt 1 gt lt 2 gt lt 3 gt lt 4 gt lt 5 gt Operation code 1 0 1 0 1 00 0 Number of bytes 1 Number of states 7 4 Function EA lt 1 Increments the extended accumulator Flags affected lt 0 11 lt 0 10 lt 0 2 Decrement Register 1 2 3 lt 4 gt lt 5 gt lt 6 gt Operation code 0 1 0 1 0 0 Ro Number of bytes 1 Number of states 4 4 Function i r2 lt r2 1 Skip if borrow Decrements the contents of the register r2 A B C specified by R Ro 1 to 3 and skips if a borrow is generated as a result of the decrement Flags affected 12 SK 11 lt 0 10 0 Example DCR B B B 1 DCRW wa Decrement Working Register lt 1 gt lt 2 gt lt 3 gt lt 4 gt 5 6 302 Operation code O 0 1 1 0 0 0 0 Offset Number of bytes 2 Number of states 16 7 Function V wa V wa 1 Skip if borrow Decrements the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and skips if a borrow is generated as a result of the decrement Flags affected Z SK L1
137. L r1 EAH EAL B C D E H L r2 A B C sr PA PB PC PD PF MKH MKL ANM SMH SML EOM ETMM TMM MM MCC MA MB MC MF TXB TMO TM1 ZCM sr PA PB PC PD PF MKL ANM SMH EOM TMM RXB CRO CR2 CR3 sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM sr3 ETMO ETM1 sr4 ECNT ECPT rp SP B D H 1 V D H EA rp2 SP B D H EA rp3 B D H f CY HC Z irf NMINote FT1 F1 F2 FEO FE1 FEIN FAD FSR FST ER OV AN5 AN6 AN7 SB Note can also be written as FNMI 220 CHAPTER 14 INSTRUCTION SET Examples 1 MOV A Operation code 0 0 0 1 1 T2 Ti To If the E register is selected as r1 the instruction is written as shown below The part after the semicolon is a comment and has no effect on the operation of the instruction The corresponding operation code is shown below Operation code 0 0 0 1 1 1 0 1 DCX rp Operation code 0 0 Pi Po 0 O 1 1 If the HL register pair selected as rp the instruction is written as shown below DCX H HL e HL 1 The corresponding operation code is as shown below Operation code 0 0 1 1 0 O 1 1 221 CHAPTER 14 INSTRUCTION SET 14 4 2 Register indirect addressing With this addressing method the memory to be manipulated is addressed using the contents of the register pair specified by the register pair specification code 2 1 2 1 in the ins
138. L ar BL DL DC 6 OO O 16 0 0O O O GO O O O OQ 55 54 53 52 7 1 1 O PA6 NMI o 2 O PAS INT1O 3 MODE1 4 O PA3 RESET 5 O PA2 MODEOO 6 O PA1 X20 7 O X10 8 O Vop Vss O STOP AVss O PD7 ANOO O PD6 AN1 0 O PD5 AN2 O PD4 AN3 O 4 O PD2 AN5 0 OPD1 19 20 21 22 23 24 25 26 27 28 29 30 31 Q Q QO QO O O O Q O O zz fle zy WE ons gue DL abl He 7D cy 15 CHAPTER 1 GENERAL DESCRIPTION 1 3 4 OFJ 16 1 Normal operation mode PA70 PBO PB10 PB2 0 PB3 PB40 PB50 PB6 PB70 PCO TxD PC1 RxD PC2 SCK o PC3 INT2 o IC o PCA TO O o 6 0 0 1 12 3 14 15 6 17 18 9 OIC O PAG O PAS 4 2 1 27 28293031 7 1 INT1 O MODE1 O PAO O VoD O STOP O PD7 O PD6 O PD5 O PD4 O PD2 OIC 3 2 1 68 67 6665 64 63 62 61 X20 X10 Vss RESET MODEO AVss ANO AN10O AN2 0 AN3 AN4 0 AN5 O Remark Internally connected 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 32 33 34 35 36 37 38 39 40 41 42 43 O PD1 O PDO O PF7 O PF6 O PF5 O PF4 2 1 OALE OWR oRD O AVDD OIC O VaREF O AN7 CHAPTER 1 GENERAL DESCRIPTION 2 EPROM mode uPD78CP14 only O Open O A6 5 O A4
139. L1 0 10 0 246 CHAPTER 14 INSTRUCTION SET LHLD word Load H amp L Direct 1 Operation code Low address gt gt gt gt High address 2 Number of bytes 4 3 Number of states 20 14 4 Function L lt word H lt word 1 Loads the contents of the memory addressed by the 3rd byte lower address and 4th byte upper address into the L register and loads the contents of the next memory address into the H register 5 Flags affected lt 0 11 lt 0 10 lt 0 LSPD word Load SP Direct 1 Operation code Low address gt a lo High address 2 Number of bytes 4 3 Number of states 20 14 4 Function SPL word SPH lt word 1 Loads the contents of the memory addressed the 3rd byte lower address and 4th byte upper address into the low order 8 bits SPL of the stack pointer and loads the contents of the next memory address into the high order 8 bits 5 5 Flags affected SK 0 L1 0 L0 0 247 CHAPTER 14 INSTRUCTION SET LDEAX rpa3 Load EA with Memory addressed by Register Pair 1 Operation code 010 0 1 0 0 0 1 000 C2 Co 2 Number of bytes states The number of bytes and number of states are as shown below depending on the rpa3 specification Her Debra
140. L1 0 10 0 300 CHAPTER 14 INSTRUCTION SET 14 6 9 Increment decrement instructions INR r2 Increment Register 1 Operation code 0 1 0 0 0 0 R Ro 2 Number of bytes 1 3 Number of states 4 4 4 Function r2 lt r2 1 Skip if carry Increments the contents of the register r2 A B C specified by R1Ro 1 to 3 skips if a carry is generated as a result of the increment b Flags affected Z SK 11 lt 0 10 0 6 Example INR A lt A 1 INRW wa Increment Working Register 1 Operation code 0 0 1 0 0 0 0 0 lt 2 gt Number of bytes 2 lt 3 gt Number of states 16 7 lt 4 gt Function V wa lt V wa 1 Skip if carry Increments the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and skips if a carry is generated as a result of the increment lt 5 gt Flags affected Z SK HC L1 lt 0 10 lt 0 lt 6 gt MVI V OFFH INRW OFFH FFFFH lt FFFFH 1 This example increments the contents of the working register in address FFFFH INX rp Increment Register Pair 1 Operation code 0 0 Pi Po 0 0 1 0 2 Number of bytes 1 3 Number of states 7 4 4 Function rp lt 1 Increments SP or the contents of the register pair BC DE HL specified by 1 0 to 3 5 Flags affected S
141. MA acc preteen 61 4 3 Port A Specifled as Output POFt 2 eodd eg 62 4 4 Port A Specified as Iriput det cas e te dede duda 62 4 5 Mode B Register 65 4 6 Mode Control C Register cn ted aa a a leer d duis 66 4 7 ModerG Register Format 67 4 8 Port C Specified as Control Signal Output 2 42 4 422098290 68 4 9 Port C Specified as Control Signal 1 68 4 10 Model REGIStEr FORM at secte 71 5 1 76 5 2 Timer Mode Register TMM 2 00002 eem 78 6 1 Timer Event Counter Block Diagraimi 81 6 2 Timer Event Counter Mode Register Format 2 2 2000200 00000000000 0 87 6 3 Output Control Circuit Block Diagram COO Output 2 2 2 3 22 5 3 9 88 6 4 Timer Event Counter Output Mode Register Format 89 6 5 Timer Event Counter Setting Procedure 4202022222220 90 6 6 Timer Event Counter Mode Register Setting Interval Timer 91 6 7 Interval Timer Mode Operation
142. MI Non maskable interrupt Input The edge triggered falling edge non maskable interrupt input 2 1 11 INT1 Interrupt request Input The edge triggered rising edge maskable interrupt input Can also be used as the AC input zero cross detection pin 2 1 12 AN7 to ANO Analog input Input The 8 analog inputs to the A D converter AN7 to AN4 can also be used as input pins for falling edge detection when a falling edge is detected the test flag is set 1 2 1 13 Reference voltage Input The A D converter reference voltage input pin Also used as the A D converter operation control pin 2 1 14 Analog The A D converter power supply supply pin 28 CHAPTER 2 PIN FUNCTIONS 2 1 15 AVss Analog Vss The A D converter GND pin 2 1 16 STOP Stop control input The hardware STOP mode control pin oscillation is stopped when this pin is driven low 2 1 17 X1 X2 Crystal Crystal connection pins for internal clock oscillation When the clock is supplied from off chip the clock should be input to X1 and the inverted X1 clock to X2 2 1 18 RESET Reset Input The low level active reset pin 2 1 19 The positive power supply pin 2 1 20 Vss GND potential 2 1 21 ICNote Internally connected pin Leave open Note OFJ package only 29 CHAPTER 2 PIN FUNCTIONS 2 2 EPROM Mode The EPROM mode can only be specified for the uPD78CP18 78CP14 2 2 1 A14 t
143. MKSR bit of the interrupt mask register MKH is reset 0 releasing masking of INTSR internal interrupts The interrupt mask flag for INTST interrupts which have the same priority as INTSR interrupts is set 1 setting INTST interrupts as masked Figure 7 15 Interrupt Mask Register MKH Setting Serial Interface INTSR Mask Release INTAD masked INTSR masking released INTST masked d The RxE bit of the serial mode high register SMH is set 1 enabling reception Figure 7 16 Serial Mode High Register SMH Setting Serial Interface Reception Enable Previous status Reception enable Previous status e PC7 output is set to 0 activating CTS A program which performs the initialization required for reception is shown below 133 CHAPTER 7 SERIAL INTERFACE FUNCTIONS RVEN LXI H 2000H Set data pointer DP 2000H lt a gt MVI OFH Set data counter b EXX ANI MKH 05H INTST enable c ORI SMH 08H Receive enable d ANI PC 7FH OTSSD lt e gt Following the above settings an INTSR internal interrupt is generated each time the prescribed data is received The operation flow of the interrupt service routine is shown below lt a gt Error processing lt b gt lt C gt Y CTS 1 d Disable reception lt e gt Set interrupt mask register lt f gt 1 RETI
144. NCTIONS for details 3 7 Timer Event Counter This is a 16 bit timer event counter which performs the following operations according to the operating mode set by the program see CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS for details Interval timer function Event counter function e Frequency measurement Pulse width measurement Programmable square wave output 3 8 Serial Interface This interface is used to perform serial data transfers in a multi processor configuration or with various terminals and operates in asynchronous mode synchronous mode and interface mode see CHAPTER 7 SERIAL INTERFACE FUNCTIONS for details 3 9 Analog Digital Converter This consists of an 8 bit A D converter with 8 analog inputs which uses the high precision successive approximation method and 4 conversion result registers CRO to CR3 which hold the conversion results With two analog input selection methods scan mode and select mode and 4 registers CRO to CR3 to hold the conversion results software overheadis minimized see CHAPTER8 ANALOG DIGITAL CONVERTER FUNCTIONS for details 3 10 Interrupt Control There are 3 kinds of external interrupt request and 8 kinds of internal interrupt request controlled according to the status and priority of the interrupt mask register The 11 kinds of interrupt requests are divided into 6 groups with 6 different priorities and 6 different interrupt addresses see CHAPTER 9 INTERRUPT CONTROL
145. NCTIOS 3 3 Arithmetic Logical Unit ALU The ALU executes data processing such as 8 bit arithmetic and logical operations shift and rotation data processing such as 16 bit arithmetic and logical operations and shift operations 8 bit multiplication and 16 bit by 8 bit division 3 4 Program Status Word PSW This word consists of 6 types of flags which are set reset according to instruction execution results Three of these flags Z HC and CY can be tested by an instruction PSW contents are automatically saved to the stack when an interrupt external internal or SOFTI instruction is generated and restored by the RETI instruction RESET input resets all bits to 0 1 2 3 4 5 6 Figure 3 2 PSW Configuration 7 6 5 4 3 2 1 0 o z sk jw ju j Jj o Z Zero When the operation result is zero this flag is set 1 In all other cases it is reset 0 SK Skip When the skip condition is satisfied this flag is set 1 If the condition is not satisfied it is reset 0 HC Half carry If an operation generates a carry out of bit 3 or a borrow into bit 3 this flag is set 1 In all other cases it is reset 0 L1 When MVI A byte instructions are stacked this flag is set 1 In all other cases it is reset 0 10 When MVI L byte LXI H word instructions are stacked this flag is set 1 In all other cases it is reset 0 CY Carry When an operation generates a carr
146. NM This register controls A D converter operations As shown in Figure 8 2 bit 0 MS of the A D channel mode register controls the operation mode and bits 1 to 3 ANIO to ANI2 select the analog input for A D conversion Bit 4 FR is used to maintain the optimum conversion speed the conversion speed for one operation can be calculated by means of the oscillator frequency and the FR bit using the following expressions and is set as shown in Table 8 1 FR 0 Conversion speed 48 x 12 fxra us FR 1 Conversion speed 36 x 12 fxtat us fxra Oscillator frequency MHz Table 8 1 Conversion Speed Settings 0 0 0 0 1 1 1 FR bit Conversion speed 38 4 us 48 us 52 4 us 57 6 us 48 us 54 us 61 7us Reading the contents of the A D channel mode register allows the current conversion mode to be ascertained RESET input or hardware STOP mode resets the A D channel mode register to 00 Writing to the ANM register initializes the A D converter stops the A D conversion currently being performed and starts A D conversion from the beginning in accordance with the contents written to ANM Thus if a write is performed on the ANM register after the INTFAD flag has been cleared A D conversion is started in accordance with the written contents Therefore when the INTAD flag is set again the post change result is stored in the CR registers CRO to CR3 140 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNC Figure 8 2 A D Channel Mode Re
147. O PC1 RxD 12 40 o ALE 2 5 13 39 o WR PC3 INT2 o 14 38 o RD PCA TO 15 37 O AVop 16 36 VAREF 6 17 35 PC7 CO1 18 34 AN6 NMI o 19 33 o AN5 20 21 22 23 24 25 26 27 28 29 30 31 32 sos e gt gt gt LLII gt gt 13 CHAPTER 1 GENERAL DESCRIPTION 2 EPROM mode uPD78CP18 78CP14 only 5 4 2 1 007 06 005 004 003 64 63 62 61 60 59 58 57 56 55 54 53 52 A6 O 1 51 O 02 A70 2 50 O1 3 49 o 00 O 4 48 O lt 2 gt O 5 47 O A14 lt 3 gt se 6 46 O A13 O 7 45 O A12 O 8 44 O A11 9 43 OA10 OE 0 42 lt 2 gt 1 41 O A8 2 40 3 39 lt 2 gt O 4 38 7 O 5 37 O O 6 36 O 7 35 lt 1 gt 0 8 34 O A90 9 33 O 20 21 22 23 24 25 26 27 28 29 30 31 32 0 0 J 150 MODE1 lt 2 gt 0 RESETO MODEOO Cautions 1 Connect directly to Vss 2 Pull down individually to Vss potential via a resistor 3 uPD78CP18 only In the case of uPD78CP14 pull down to Vss potential via a resistor 14 CHAPTER 1 GENERAL DESCRIPTION 1 3 3 OFP 8 N 9 gt s ON x OA OO OO O O O m rm cdm lt aa G BL DL G DL D
148. O 1 1 0 0 0 0 0 1 00 1 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function Avr Obtains the exclusive logical sum of the contents of the accumulator and the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 and stores the result in the accumulator 5 Flags affected Z 5 lt 0 1 lt 0 10 0 6 Example A A B A Exclusive Or with Register 1 Operation code O 1 1 0 0 0 0 0 0 0 0 1 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function i Obtains the exclusive logical sum of the contents of the register r V A B C D E H L specified by R2R Ro 0 to 7 and the contents of the accumulator and stores the result in the specified register 5 Flags affected Z lt 0 1 lt 0 10 0 6 Example C A lt 258 CHAPTER 14 INSTRUCTION SET Greater Than Register 1 Operation code O 1 1 0 0 0 0 0 1 0 1 0 1 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function A r 1 lt Skip if no borrow Subtracts the contents of the register V A B C D E H L specified by R2R Ro 0 to 7 1 from the contents of the accumulator Skips if no borrow is generated as a result of the subtraction A r 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6
149. O INTE1 0018H 2 Call address table The call address of a 1 byte call instruction CALT can be stored in the 64 byte area for 32 call addresses from address 0080H to address OOBFH 3 Specific memory area Thereset start address interrupt start addresses and the call table are allocated to addresses 0000H to OOBFH and this area takes account of these in use Addresses 0800H to OFFFH are directly addressable by a 2 byte call instruction CALF On chip mask ROM allocation is shown below e uPD78C18 Addresses 0000H to 7FFFH e uPD78C17 No mask ROM incorporated e uPD78C14 78C14A Addresses 0000H to 3FFFH e uPD78C12A Addresses 0000H to 1FFFH e uPD78C11A Addresses 0000H to OFFFH e uPD78C10A No mask ROM incorporated With the uPD78C17 78C10A a specific area can be set up externally 44 3 INTERNAL BLOCK FUNCTIONS 4 5 6 On chip data memory area 1K byte RAM is incorporated in addresses FCOOH to FFFFH in the uPD78C18 and 256 byte RAM in addresses FFOOH to in the wPD78C14A 78C12A 78C11A 78C10A The RAM contents are retained in standby operation Caution When internal RAM is used the RAE bit of the MM register must be set to 1 External memory area The possible area for external memory expansion is shown below This area can be expanded in steps by setting the memory mapping register e uPD78C18 31K bytes addresses 8000H to FBFFH e uPD78C14 7
150. On chip RAM SONIWIL ANY S3SS3229V 39IA3Q 1TVNH3IX3 LL H3ldVHO CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11 1 1 Memory mapping register MIM The memory mapping register is an 8 bit register which performs the following controls Port expansion mode specification for PD7 to PDO and PF7 to PFO e Enabling disabling of on chip RAM accesses e Specification of on chip EPROM access range uPD78CP18 78CP14 only See CHAPTER 12 PROM ACCESSES uPD78CP18 78CP14 ONLY The configuration of the memory mapping register is shown in Figure 11 2 1 Bits to MM2 These bits control the PD7 to PDO port expansion mode and input output specification and the PF7 to PFO address output specification As shown in Figure 11 2 there is a choice of four capacities for the connectable external memory e 256 bytes e AK bytes e 16K bytes 31K 48K 56K 60K bytes 31K bytes of external expansion memory can be connected to the uPD78C18 48K bytes to the uPD78C14 78C144A 56K bytes to the uPD78C12A and 60K bytes to the uPD78C11A Any of the pins PF7 to PFO not used as address outputs can be used as general purpose port pins RESET input or the hardware STOP mode resets 0 these bits and sets PD7 to PDO to input port mode high impedance 2 bit RAE This bit controls enabling RAE 1 and disabling RAE 0 of on chip RAM accesses This bit should be set to 0 during standby operation and when externally connect
151. P 15 lt SP 1 SP lt SP 2 lt PC n Number of bytes the skipped instruction Restores the contents of the stack memory addressed by the SP to the low order 8 bits PC7 0 of the program counter and restores the contents of the stack memory addressed by SP 1 to the high order 8 bits PC1s 8 then skips unconditionally 5 Flags affected gt SK 1 L1 0 10 0 6 Example EXAM EQU 0600H 0500 CALL EXAM STACK lt 0503H 0503 JMP 0700H 0506 JMP 0800H 0509 0600 EXAM PUSH V PUSH B POP B POP V RETS PC e STACK lt PC 3 After returning from the subroutine EXAM JMP 0700H is skipped and JMP 0800H is executed 319 CHAPTER 14 INSTRUCTION SET RETI Return from Interrupt 1 Operation code O 1 1 00 01 0 2 Number of bytes 1 3 Number of states 13 4 4 Function PC7 0 lt SP PCis s lt SP 1 PSW lt SP 2 SP lt SP 3 Restores the contents of the stack memory addressed by the SP to the low order 8 bits PC7 0 of the program counter restores the contents of the stack memory addressed by SP 1 to the high order 8 bits PC15 8 of the program counter and restores the contents of the stack memory addressed by SP 2 to the PSW This instruction is used to return from the interrupt service routine for an external interrupt NMI INT1 INT2 an internal interrupt timer serial transfer etc or a SOFTI instruction interrupt lt 5 gt F
152. PT ROUTINE PUSH V PUSH B PUSH D PUSH H PUSH EA POP EA POPH POPD POP B POP V El RETI DFF6H DFF7H DFF8H DFF9H DFFAH Stack contents when PUSH EA is executed DFFBH DFFCH DFFDH DFFEH DFFFH 249 CHAPTER 14 INSTRUCTION SET POP rp1 Pop Register Pair off Stack 1 Operation code 1 0 1 00 Qi Oo 2 Number of bytes 1 3 Number of states 10 4 4 Function lt SP lt SP 1 SP lt SP 2 Restores the contents of the stack memory addressed by SP to the lower half A C E L EAL of the register pair rp1 VA BC DE HL or extended accumulator specified by Q2Q1Qo 0 to 4 and restores the contents of the stack memory addressed by SP 1 to the upper half V B D b Flags affected SK 0 L1 0 10 0 6 Example PUSH D POPD POP B As the stack pointer indicates the last stack address saved to the POP instruction restores items in the reverse order from that used in the PUSH instruction LXI rp2 word Load Register Pair with Immediate 1 Operation code 0 P2 Pi Po O 1 0 0 High byte 2 Number of bytes 3 3 Number of states 10 10 4 Function 2 lt Loads the 2nd byte into the low order 8 bits SPL of the SP the lower half C E L EAL of the register pair rp2 BC DE HL or extended address specified by P2P Po 0 to 4 and loads the 3rd
153. Pins sse nnn nnne nennt nannten anna 37 CHAPTER 3 INTERNAL BLOCK FUNCTIONS 222 4 440 024400 39 REGQISTOMS c 39 3 2 Mode Registers rre terne penu 41 3 3 Arithmetic Logical Unit 2 4 4 1 42 3 4 Program Status Word 5 0 00 00000 42 38 oit OPE dere T am 44 3 5 1 LPD78C18 78C17 78C14 78C14A 78C12A 78C114A 78C10A memory configuration 44 35 2 78 1 78 memory config ratiOri ccrtc ert ence eite deed 52 3 6 TAM evveves a a Kr Erai 57 3 7 Counter ccccceccsesssssseeceeceeeeeesesesssenaaneeseeseeeeeseeseesansasseseeseseeseesessssensanees 57 3 8 Serial Interface a eter OE Rea Yeu Ere 57 3 9 Analog Digital Converter 00 4444 000 57 3 107 Interrupt Control erret prre ERE FL eaa Ee ERE eu PER ERE RR 57 3411 Zero Cross Detector ooo eerie 58 4 2 e DENN RA 61 41 222025240 etr ree e terne Geass sin
154. R 3 INTERNAL BLOCK FUNCTIONS Figure 3 4 Memory Map uPD78C17 0000H 0000H 0004H 0008H INTTO INTT1 0010H INT1 INT2 External memory 64512 x 8 bit 0018H INTEO INTE1 0020H INTEIN INTAD Note M E 0028H INTSR INTST E 0060H SOFTI 0080H LOW ADRS 0081 HIGH ADRS 7 o 0082H LOW ADRS 2 P 0083H HIGH ADRS 55 OOBEH LOW ADRS OOBFH HIGH ADRS REM Note Can only be used when the RAE bit of the MM register is 1 47 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 48 Figure 3 5 Memory Map 78 14 78 14 0000H On chip ROM 16384 x 8 bit 4000H External memory 48896 x 8 bit FEFFH FFOOH On chip 256 x 8 bit Standby area FFFFH Note Can only be used when the RAE bit of the MM register is 1 Call table 0000H 0004H 0008H 0010H 0018H 0020H 0028H 0060H 0080H 0081H 0082H 0083H OOBEH OOBFH INTTO INTT1 2 INTEO INTE1 INTEIN INTAD INTSR INTST SOFTI LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS LOW ADRS t 31 HIGH ADRS User s area CHAPTER 3 INTERNAL BLOCK FUNCTIONS Figure 3 6 Memory Map uPD78C12A
155. RNAL DEVICE ACCESSES AND 5 11 1 2 Example of memory expansion Figure 11 3 shows an example of a configuration with 16K bytes of external expansion ROM and Figure 11 4 shows the data set in the memory mapping register for this configuration Figure 11 3 Example of Memory Expansion Reference Diagram 87AD series Oo 7 CE Standby control OE uPD27Cb12 t A 15 Ao 7 1 AD7 0 OE uPD74HC573 System reset Note 4PD27C512 uses only 16K bytes 192 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND Tif Figure 11 4 Memory Mapping Register Settings 7 6 5 4 3 2 1 0 0 ERERESESLENESEX PD7 to PDO Expansion mode PF5 to PFO Expansion mode PF7 amp PF6 Port mode On chip RAM access Disable Enable 193 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 11 1 3 Example of peripheral device connection In the uPD78C18 78C14 78C14A 78C12A 78C11A a uPD8085 type bus system is used in which the data bus and low order 8 bits of the address bus are multiplexed Therefore a large number of uPD8085 peripheral devices can be connected When peripheral devices are connected since the uPD78C18 78C14 78C14A 78C12A 78C11A has 1 0 address space memory mapped I O must be used for all of them The connection of typical peripheral devices is illustrated here Figure 11 5 shows an example of a conf
156. Register Format uPD78CP18 7 6 5 4 3 2 1 0 peer e owe Tree ne PD7 Input port PF7 to PFO Port mode Single chip PD7 Port mode o PDO Output port PF7 to Port mode 256 bytes PD o PDO Expansion mode PF7 to PFO Port mode PD7 4K bytes PF3 to PFO PF7 to PF4 Port mode y oe Expansion mode o c x PD7 to 16K bytes PF5 to PFO amp PF6 Port mode Expansion mode Note Depending on bits MM7 to 5 On chip RAM access Disable 31K 48K 56K PD7 to Expansion mode 60K bytesNete PF7 to PFO 204 Enable On chip PROM and on chip RAM access ranges On Chip PROM Access Range On Chip RAM Access Range 0000H to 7FFFH 32K bytes 78 18 mode FCOOH to FFFFH 1K bytes 0000H to 3FFFH 16K bytes 78 14 mode FFOOH to FFFFH 256 bytes 0000H to 1FFFH 8K bytes LPD78C12A mode FFOOH to FFFFH 256 bytes 0000H to OFFFH 4 bytes LPD78C11A mode FFOOH to FFFFH 256 bytes Other than the above Setting prohibited CHAPTER 12 ACCESSES uPD78CP18 78CP14 7 Figure 12 2 Memory Mapping Register Format 78 14 6 5 4 3 2 1 0 ao pron Ton PD7 to PDO Input port PF7 to PFO Port mode Single chip Port mode
157. Register Setting Single Pulse Output INTEIN Mask Release 101 6 23 Timer Event Counter Mode Register Setting Single Pulse Output ECNT Setting uses csset ee 102 Figure No LIST OF FIGURES 2 3 Title Page 6 24 6 25 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 7 7 7 J 7 7 7 OO 8 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 9 1 9 2 9 3 9 4 9 5 9 6 9 7 9 8 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 10 10 10 11 10 12 10 13 Timer Event Counter Mode Register Setting Single Pulse Output COO Output TMINA 103 Interrupt Mask Register MKL Setting Single Pulse Output INTE1 Mask Release 104 Serial Interface Configuration 107 Serial Mode High Register SMH Format n eene nennen 111 Serial Mode Low Register SML Format 4 113 Serial Mode Register Format in Asynchronous 115 Asynchronous Data 222 2 9995 9 118 Serial Mode Register Format in Synchronous 121 Synchronous Mode TIN extrae AMA ERROR tUe E ended 122
158. Same level interrupts both non maskable Y Reset Save PSW amp PC to stack memory PC lt interrupt address 161 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS When execution of the interrupt service routine ends processing is performed to return to the address at which the interrupt was acknowledged First registers flags etc other than the PSW which have been save are restored and if necessary the IE F F is set by the El instruction Next the RETI instruction is used to restore the previously saved return address and PSW in the order Lower PC byte upper PC byte PSW Since interrupt servicing is performed for non maskable interrupts irrespective of the status of the IE F F they are useful for program processing in the event of an emergency such as a power failure The configuration of the NMI pin is shown in Figure 9 5 Although INTFNMI cannot be tested by a skip instruction the NMI pin status can be tested by a skip instruction SKIT NMI or SKNIT NMI Thus in the non maskable interrupt Service routine relatively wide noise can be removed by testing the NMI pin status several times using a skip instruction The NMI pin status is not changed when tested by a skip instruction Caution The lE F F is reset unconditionally when a non maskable interrupt is generated and the contents of the IE F F prior to the non maskable interrupt are not saved Therefore when returning to the main routine the origin
159. TRUCTION SET Example 2 SDED word Operation code O 1 1 1 0 0 0 0 High address If the label DST is used as word the instruction is written as shown below SDED DST If DST is assumed to be 4000H the corresponding operation code is as follows Operation code 0 14 5 Number of States Required for Skipping The number in parentheses indicated in lt 3 gt Number of states in the instruction set descriptions is the number of idle states consumed without any operation when that instruction is skipped The number of idle states when the instruction is skipped is 4 in the case of the OP code and 3 in the case of immediate data Example MVI sr2 byte instruction 3 byte instruction Ss 0 0 0 0 52 51 So As the 1stand 2nd bytes are the OP code the number of idle states is 4 and as the 3rd byte is immediate data the number of idle states is 3 Therefore the number of idle states consumed when this instruction is skipped is 4 4 3 11 232 CHAPTER 14 INSTRUCTION SET 14 6 Instruction Descriptions 14 6 1 8 bit data transfer instructions MOV r1 Move A to Register 1 Operation code 0 0 0 1 1 T2 To 2 Number of bytes 1 3 Number of states 4 4 4 Function i r1 lt Transfers the accumulator contents to register r1 EAH EAL C D E 1 specified by T2T1To 0 to 7 When is specified by r1 the contents are transferred to the high order 8 bits of the extended
160. Test flag register 2 Timer event counter capture register ECPT ECPT register is a 16 bit buffer register which holds the ECNT contents The timing for latching of the ECNT contents by the ECPT register is as follows according to the input to the ECNT he ECPT register latches the ECNT contents on the fall of the Cl input when the input to ECNT is 5 i Internal clock 412 or ii Internal clock while Cl input is high and on the fall of TO when the input to ECNT is iii input or iv CI input while TO output is high Table 6 1 Timing for Latching in ECPT ECNT Input Internal clock 12 12 while is high ECNT Latch Timing CI input falling edge CI inputNete 1 input while TO is highNete 1 Notes 1 Falling edge input TO falling edgeNote 2 2 The TO signal cannot be used when timer F F input is used as internal clock see Figure 5 1 Timer Block Diagram 3 Timer event counter REGO 1 ETMO ETM1 These are two 16 bit registers used to set the count value Cautions 1 When 0 is set a match signal CPO CP1 is generated from the comparator every count of 65536 10000H 2 When data is written to ETM0 ETM1 output of the comparator match outputs 1 are disabled and therefore INTEO INTE1 are not generated 4 Comparator The comparator compares the contents of ECNT and and if a match is detected outputs a c
161. Timing STOP Signal 178 Hardware STOP Mode Release Timing RESET Signal Input 178 Hardware STOP Mode Release Timing STOP Signal Rising to RESET Signal Input 179 Relation between Von arid SB Flag cte n eet tee eats Mb c dade eg 179 Oscill tor Connection cus aei Edeka tna sequo cde Mead sess 182 Example of External Clock Input CIRCUIT ere rre toe d pere teer 182 Examples of Poor Resonator Connection nes 183 viii LIST OF FIGURES 3 3 Figure No Title Page 11 1 External Expansion Modes Set by Memory Mapping Register 189 11 2 Memory Mapping Register Format uPD78C18 78C14 78C144 78C124 78C114 191 1 3 Example of Memory Expansion Reference 192 11 4 Memory Mapping Register Settings 2 2 2 2 2 2202 00000000 0 193 1 5 71055 Connection Diagram Reference Diagram 195 11 6 Memory Map uPD786318 ciis ete eaim aa ettet ea HR rede nae utes 196 11 7 Memory Map uPD78614 78G TAA us acces ome ese ter quet pda ERR RE 196 11 8 Mernorymap 4PD 786124 eet pn drea reete De dE adea bua rab cre recs 197 1 9 Memory Map
162. a microcontroller RA87 In addition functions are provided for automatic symbol table generation branch instruction optimization processing etc Host Ordering code machine OS Supply medium Product name MS DOS M Ver 2 11 3 5 inch 2HD 55 1 87 PC 9800 series 1 Ver 5 00ANote DOSIM 3 5 inch 2HC uS7B13RA87 Ver 3 1 5 inch 2HC US7B10RA87 5 inch 2HD US5A10RA87 IBM Note Ver 5 00 5 00A are provided with a task swapping function but this software cannot use the function Remark Operation of the assembler is guaranteed only on the host machines and operating systems quoted above 349 APPENDIX B DEVELOPMENT TOOLS PROM Writing Tools Hardware PG 1500 This PROM programmer allows programming in standalone mode or via operation from a host machine of a single chip microcontroller with on chip PROM by connection of the board provided and a separately available programmer adapter It also permits programming of typical PROMs from 256K bits to 1M bits PA 78CP14CW PROM programmer adapter for uPD78CP14 78CP18 used connected to the PG 1500 GF GQ KB L PA 78CP14CW For uPD78CP14CW 78CP14DW 78CP18CW 78CP18DW PA 78CP14GF For uPD78CP14GF 3BE 78CP18GF 3BE PA 78CP14GO For uPD78CP14G 36 78CP14R 78CP18GO 36 PA 78CP14KB For uPD78CP14KB 78CP18KB PA 78CP14L For uPD78CP14L Software PG 1500 controller Connects PG 1500 and h
163. accumulator and when EAL is specified to the low order 8 bits 5 Flags affected lt 0 11 lt 0 10 lt 0 lt 6 gt MOV A Transfer A to B MOV A r1 Move Register to A 1 Operation code 0 0 0 0 1 To 2 Number of bytes 1 3 Number of states 4 4 4 Function lt r1 Transfers the contents of register r1 EAH EAL B C D E L specified by T2T1To 0 to 7 to the accumulator When EAH is specified by r1 the contents of the high order 8 bits of the extended accumulator are transferred to the accumulator and when EAL is specified the low order 8 bits of the extended accumulator are transferred 5 Flags affected SK 0 L1 0 10 0 6 Example MOV A C Transfer C to A 233 CHAPTER 14 INSTRUCTION SET MOV sr A Move A to Special Register 1 Operation code O 1 00 1 1 0 1 1 1 Ss Sa 52 Si So 2 Number of bytes 2 3 Number of states 10 7 4 Function i sre A Transfers the accumulator contents to the special register sr PA PB PC PD PF MKH MKL ANM SMH SML EOM MA MB MC MF TXB TM1 ZCM specified by 555453525150 0 to 3 5 to D 10 to 14 17 18 1A 1B 28 5 Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example MOV PA A Transfer A to port A latch MOV A sr1 Move Special Register to A 1 Operation code 0 1 0 0
164. al Input Interrupt execution CPU OSC NMI INTFNMI II Wait programmable TIMER1 match signal CHAPTER 10 CONTROL FUNCTIONS 10 1 5 Hardware STOP mode When the STOP signal changes from the high to low level the hardware STOP mode is set In this mode all clocks stop When the hardware STOP mode is set program execution stops and the on chip RAM contents just before stoppage are retained and the STOP signal used to release the hardware STOP mode is valid All other functions stop and the reset state is set In the hardware STOP mode the uPD78C18 output pins become high impedance However the port output latch values are retained Cautions 1 Crystal oscillation or ceramic oscillation should be used when using the hardware STOP mode The hardware STOP mode must not be used when an external clock is input The STOP mode is entered at a machine cycle boundary Thus memory contents are not corrupted but the STOP mode may be entered midway through execution of an instruction Therefore with instructions which perform a 16 bit data transfer the STOP mode may be entered after only 8 bits have been transferred with the transfer of the remaining 8 bits incomplete 16 bit data transfer instructions and call instructions If the STOP signal is input high low level during reset input RESET low level a transition is made from the r
165. al status of the IE F F should be determined by means of the stack address when the non maskable interrupt was generated Figure 9 5 Internal Configuration of NMI Pin c gt sob Poo Non maskable interrupt request Non maskable interrupt acknowledgment Test control 78 18 162 CHAPTER 9 INTERRUPT CONTROL FUNCTION 9 4 Maskable Interrupt Operation Interrupt requests except non maskable interrupts and the SOFTI instruction are maskable interrupts which can be enabled disabled IE F F set reset by the EI DI instructions and can be masked individually by means of the mask register When an external maskable interrupt is recognized as a normal interrupt signal by an active level input for more than the specified time an interrupt request flag is set If an internal interrupt request is generated an interrupt request flag is immediately set Once the interrupt request flag is set both the external and internal interrupts are serviced using the following procedure see Figure 9 3 Interrupt Sampling In the El state IE F F 1 a check is made to see if the interrupt request flag has been set at the end checked at end of each instruction If the flag has been set the interrupt cycle starts However interrupt requests masked by the mask register are not checked If two or more interrupt request flags have been set simultaneously their priorities are chec
166. ance Caution Port D can only be used as an address data bus 25 CHAPTER 2 PIN FUNCTIONS 2 1 5 PF7 to PFO Port F 3 state input output uPD78C18 78C14 78C14A 78C12A 78C11A 78CP 18 78CP 14 These are the 8 bit input output pins of port F 8 bit input output port with output latch but in addition to functioning as an input output port they also function as address outputs AB15 to AB8 for accessing externally expanded memory Pins PF7 to PFO be specified as shown below by setting the memory mapping register 1 Port mode As port F input output pins PF7 to PFO can be specified bit wise as input or output by means of the mode F register 2 Expansion mode When an external device is expanded in addition to on chip memory PF7 to PFO are used as an address bus AB15 to AB8 corresponding to the size of the external device as shown in Table 2 2 When an instruction which references an external device is executed the upper address information for the external device is output in the external device reference machine cycle of that instruction Caution Pins PF7 to 0 set as an address bus have output to them the contents of the internal address bus as they are in all machine cycles Pins not specified as address output pins are in port mode Caution Emulation cannot be performed by an emulator for a program which varies the port F operating mode dynamically Therefore once the mode has been set it should not be
167. and the previous data transfer is terminated the transmit buffer register contents are transferred to the serial register converted into serial data and transmitted LSB first from TxD in synchronization with the falling edge of SCK Serial data is transmitted at the same rate as SCK When data is transferred from the transmit buffer register to the serial register and the transmit buffer register becomes empty an interrupt request INTST is generated Serial transmission interrupts are disabled by setting 1 the MKST bit of the interrupt mask register When the TxE bit is 0 or when the serial register contains not data to be transmitted the TxD pin assumes the mark status 1 However when an external clock is used the mark status is assumed after output of a 1 bit low level pulse The maximum data transfer rate in transmission is 625 kbps when an internal clock is used as SCK and 1 25 Mbps when an external clock is used at 15 MHz operation Data reception A receive operation in the synchronous mode is enabled by setting 1 the RxE bit of serial mode high register SMH Receive data is input on the rising edge of SCK Two kinds of receive operations are available in the synchronous mode and can be controlled by the SE bit of the serial mode high register SMH When the SE bit is set 1 the search mode is set Each time one bit is sent to the MSB of the serial register from the RxD pin the serial register contents are transferred t
168. and timer external clock input pin Can also be used as the AC signal zero cross detection pin Caution Whenpull up resistors are incorporated of the uPD78C18 78C14A 78C12A 78C11A the zero cross function can not be operated correctly TO Timer output Output Outputs a square wave with the timer count time or one cycle of the internal clock as a half cycle CI Counter input Input The timer event counter external pulse input COO CO1 Counter output Output These pins output a rectangular wave which is programmable by the timer event counter Upon RESET input PC7 to PCO are set as input port high impedance PC7 to PCO also become high impedance in the hardware STOP mode 24 CHAPTER 2 PIN FUNCTIONS 2 1 4 PD7 to PDO Port D 3 state input output uPD78C18 78C14 78C14A 78C12A 78C11A 78CP18 78CP14 These are the 8 bit input output pins of port D 8 bit input output port with output latch but in addition to functioning as an input output port they also function as time division address output and data input output multiplexed address data bus pins for accessing externally expanded memory Pins PD7 to PDO can be specified as shown below by setting the memory mapping register 1 Port mode As port D input output pins PD7 to PDO can be specified as input or output as a byte 8 bit unit 2 Expansion mode When an external device program memory data memory or a peripheral device
169. ansmit buffer register by a MOV TXB A instruction and the previous data transfer is terminated the transmit buffer register contents are transferred to the serial register When SCK is an internal clock when the data is transferred to the serial register a controlled SCK 8 pulses for one data item is automatically generated and the transmit data is sent MSB first on the SCK falling edge When an external clock is used the transmit data is sent MSB first on the falling edge of the controlled SCK input to SCK In this mode synchronization is implemented by means of a controlled SCK 8 serial clock pulses and SCK should be driven high except during a data transfer When the transmit buffer register becomes empty a serial transmission interrupt INTST is generated Serial transmission interrupts are disabled by setting 1 the MKST bit of the interrupt mask register MKH The maximum data transfer rate in transmission is 625 kbps when an internal clock is used as SCK and 1 25 Mbps when an external clock is used at 15 MHz operation CHAPTER 7 SERIAL INTERFACE FUNCTIONS 2 Data reception A receive operation in the 1 interface mode is enabled by setting 1 the RxE bit of the serial mode high register SMH and receive data RxD is input to the serial register in order from MSB on the rising edge of SCK When the serial register receives 8 bit data the data is transferred from the serial register to the receive buf
170. b Flags affected Z SK 0 HC L1 0 LO 0 CY 6 Example C Add A and C registers and store result A ADDr A Add A to Register 1 Operation code O 1 1 0 0 0 0 0 0 1 0 0 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function lt Adds the contents of the accumulator to the contents of the register V A B C D E H 1 specified by R2RiRo 0 to 7 and stores the result in the specified register 5 Flags affected Z SK 0 L1 0 LO lt 0 CY lt 6 gt Example ADD B A Add B and A registers and store the result in ADC A r Add Register to A with Carry lt 1 gt Operation code O 1 1 0 0 0 0 0 1 1 0 1 0 R2 Ri Ro lt 2 gt Number of bytes 2 lt 3 gt Number of states 8 8 lt 4 gt Function A r CY Adds the contents of the register V A B C D H L specified by R2RiRo 0 to 7 to the contents of the accumulator including the CY flag and stores the result in the accumulator b Flags affected Z SK 0 L1 lt 0 LO lt 0 CY 6 Example ADC E lt A E CY 252 CHAPTER 14 INSTRUCTION SET ADCr A Add A to Register with Carry 1 Operation code 0 1 1 0 0 0 0 0 0 1 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function lt rt A CY Adds the contents of the accumulator to the contents of the register V A B C
171. bed below 7 3 1 Asynchronous mode the asynchronous mode transmission reception is performed by means of start stop bits with data bit synchronization and character synchronization performed by means of the start bit When data transmission reception is performed in this mode the transmission reception parameters character length clock rate number of stop bits odd even parity serial clock transmission reception enabling etc are set in the serial mode register SMH and SML as shown in Figure 7 4 114 CHAPTER 7 SERIAL INTERFACE FUNCTIONS SML Figure 7 4 Serial Mode Register Format in Asynchronous Mode 1 2 6 5 4 3 2 1 0 Clock rate Setting prohibited Setting prohibited 7 bits 8 bits Disable Enable Even parity generation check 0 Odd 1 Even Number of stop bits Setting prohibited 1 bit Setting prohibited 2 bits 115 7 SERIAL INTERFACE FUNCTIONS Figure 7 4 Serial Mode Register Format in Asynchronous Mode 2 2 7 6 5 4 3 2 1 0 ww S T T T Tee De e Te SCK selection Internal clock TO output Internal clock Internal clock External clock Disable Enable Reception enable Disable Enable 116 CHAPTER 7 SERIAL INTERFACE FUNCTIONS When an internal clock is specified as the serial clock
172. ble rectangular wave output mode programmable rectangular waves can be output to two independent outputs COO and 1 The same operations are performed for both COO and Here programmable rectangular wave output for the COO output is described After first clearing ECNT the count value is set in ETMO and 1 Next the data shown in Figure 6 14 is set in the timer event counter output mode register EOM to initialize the output control circuit and specify the operation The data shown in Figure 6 15 is set in the timer event counter mode register and timer event counter operation Figure 6 14 Timer Event Counter Output Mode Register Setting 7 6 5 4 3 2 1 0 No operation LVO level inversion enabled LVO set 95 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS Figure 6 15 Timer Event Counter Mode Register Setting Programmable Rectangular Wave Output Mode 5 4 3 2 1 0 1 7 6 mw TS T IS Internal clock 12 count ECNT cleared by match of ECNT and 1 contents LVO level output by match of ECNT and ETMO contents or ECNT and ETM1 contents In the same way as in the interval timer mode ECNT counts up every 12 and the respective comparator compares the ECNT count with the ETMO ETM 1 contents and if a match is detected generates a match signal CPO CP1 and an interrupt INTEO INTE1 In response to the match signal the output control cir
173. by the 3rd byte lower address and 4th byte upper address and stores the contents of the B register in the next memory address 5 Flags affected SK 0 1160 10 0 lt 6 gt Example 5 4000H Store C register contents in address 4000H and store B register contents in address 4001H SDED word Store D amp E Direct 1 Operation code Low address oli oli a lo a lo High address 2 Number of bytes 4 3 Number of states 20 14 4 Function word lt E word 1 lt D Stores the contents of the E register in the memory addressed by the 3rd byte lower address and 4th byte upper address and stores the contents of the D register in the next memory address 5 Flags affected 2 SK lt 0 11 lt 0 10 lt 0 243 CHAPTER 14 INSTRUCTION SET SHLD word Store H amp L Direct 1 Operation code Low address oli gt gt High address 2 Number of bytes 4 3 Number of states 20 14 4 Function word L word 1 lt Stores the contents of the L register the memory addressed by the 3rd byte lower address and 4th byte upper address and stores the contents of the H register in the next memory address 5 Flags affected SK 0 L1 0 10 0 SSPD word Store SP Direct 1 Operation code 1 1 Low address High address o lo
174. byte expansion mode the wPD78C18 78C14 78C14A 78C12A 78C11A masks the high order 4 bits of the 16 bit external reference address and outputs a value from 000H to FFFH from pins PF3 to PFO AB11 to AB8 and pins PD7 to PDO as address information Similarly in the 16K byte expansion mode the uPD78C18 78C14 78C14A 78C12A 78C11A masks the high order 2 bits of the 16 bit external reference address and outputs value from 0000H to 3FFFH from pins to PFO AB13 to AB8 and pins PD7 to PDO as address information As the high order bits of the 16 bit address are masked in this way in the 256 byte AK byte 16K byte expansion modes the external device be located in any desired 256 byte AK byte 16K byte area in the external 60K byte area However if in the 16K byte expansion mode external ROM is connected in the expansion area and addresses 1000H to 4FFFH following the on chip ROM are used as the external ROM area it should be noted that there will be the following differences between the program counter PC and the address which is actually output from pins through PFO and PD7 through PDO PC PF5 0 PD7 0 1000H 1000 4000H 0000 AFFFH OFFF When external ROM addresses are used as consecutive addresses the external ROM area should be set in addresses 4000H to 7FFFH Since in this case on chip ROM and external ROM are not in consecutive addresses a jump instruction must be used to move the prog
175. byte into the upper half SPu B D H EAH A stacking effect is produced when HL is specified as the register pair 5 Flags affected SK 0 L1 0 10 lt 1 when rp2 HL SK 0 L1 lt 0 LO lt 0 other cases 6 Example LXI 4000H Load 40H into B register and OOH into C register 250 CHAPTER 14 INSTRUCTION SET TABLE Table pick up 1 Operation code O 1 1 0 0 0 lt 2 gt Number of bytes 2 lt 3 gt Number of states 17 8 lt 4 gt Function lt 3 lt 3 1 Loads the table contents addressed by PC 3 A into the C register and loads the table contents addressed by PC 3 A 1 into the B register 5 Flags affected lt 0 11 lt 0 10 lt 0 6 Example TBO MVI A 0 Az0 TB1 MVI A 1 A21 TB2 MVI 2 A22 SLL Shift Logical Left Accumulator PC TABLE BC TABLE 2 JB PC BC PC 3 4 azo PC 5 PC 6 7 8 n 251 CHAPTER 14 INSTRUCTION SET 14 6 3 8 bit operation instructions Register ADD Add Register to 1 Operation code 0 1 1 0 0 0 0 0 1 1 0 0 0 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function Adds the contents of the register V A B C D H L specified by R2RiRo 0 to 7 to the contents of the accumulator and stores the result in the accumulator
176. cates a power on start and a reset 0 SB flag indicates a start due to release of the software STOP mode 175 CHAPTER 10 CONTROL FUNCTIONS Figure 10 5 SB Flag Operation 5 Vpop RESET SB flag CPU operation Software STOP mode Notes 1 Execution of address 0 instruction 2 Execution of SKIT SB or SKNIT SB instruction 3 Execution of STOP instruction 2 Release by NMI pin input 176 When the non maskable interrupt request flag is set i e when the NMI pin input changes from high to low in the software STOP mode the software STOP mode is released and simultaneously clock oscillation starts When clock oscillation starts the timer upcounter starts counting up from in accordance with the setting before execution of the STOP instruction CPU operation is started by a match signal wait time taking account of the oscillation stabilization time from the TIMER1 upcounter In this case the upcounter match signal does not set the interrupt request flag The timer mode register of the timer after generation of the match signal is set to FFH and timer operation is stopped After the elapse of the oscillation stabilization time the program jumps to the interrupt address 0004H irrespective of the interrupt enabled disabled EI DI state and without executing the instruction following the STOP instruction Figure 10 6 Software STOP Mode Release Timing NMI Sign
177. ce When the RESET input or STOP input subsequently returns to the high level they are set as address bus or port according to the status of the MODE1 and MODEO pins Caution Emulation cannot be performed by an emulator for a program which varies the port F operating mode dynamically Therefore once the mode has been set it should not be changed to different mode 2 1 6 WR Write strobe 3 state output The strobe signal output for a write operation to external memory This pin is driven high except in external memory data write machine cycles When the RESET signal is low or when in the hardware STOP mode WR become high impedance Remark In a data write to internal RAM WR is driven high 2 1 7 RD Read strobe 3 state output The strobe signal output for a read operation on external memory This is driven high except in external memory data read machine cycles When the RESET signal is low or when in the hardware STOP mode RD become high impedance Remark a data read from internal ROM or RAM RD is driven high 2 1 8 ALE Address latch enable 3 state output The strobe signal which externally latches the lower address information output to pins PD7 to PDO for an access to external memory When the RESET signal is low or when in the hardware STOP mode ALE is high impedance Caution ALE output continues while the CPU is operating Therefore address latching by ALE is effective external access machine
178. ce an accumulator type architecture is used data processing such as 8 bit arithmetic and logical operation instructions centers on this accumulator This accumulator can be replaced with the ALT register paired with the vector register V by means of the EXA instruction Expansion accumulator EA Data processing such as 16 bit arithmetic and logical operation instructions centers on this accumulator This accumulator can be replaced with the ALT register EA by means of the EXA instruction 39 CHAPTER 3 INTERNAL BLOCK FUNCTIOS 40 3 4 5 6 Working register vector register V When a working area is set in the memory space the high order 8 bits of the memory address are selected using the V register and the low order 8 bits are addressed by the immediate data in the instruction Thus the memory area specified with the V register be used as working registers with a 256 x 8 bit configuration Because a working register can be specified with a 1 byte address field program reduction is possible by using the working area for software flags parameters and counters The V register can be replaced with the ALT register paired with an accumulator by means of the EXA instruction General registers B C D E H L There two sets of general registers main B C D E H L ALT B C D E L They function as auxiliary registers for the accumulator and have a data pointer function as register pairs
179. ce and Asynchronous Modes and 15 8 Limitations on Hardware STOP mode Therefore the above defects are found in the course of debugging e Remedy If the defective product is replaced by the improved product or trouble free product is used for debugging change emulation CPU from Standard of uPD78C10A to any of standards other than 15 12 Electrostatic Withstand Limit of Vpp Pin Target products uPD78CP18 Standard Details The VPP pin can withstand a maximum of 500V static electricity in the MIL standard measuring method Remedy Take suitable precautions when writing to the PROM or mounting the device 336 APPENDIX INTROCUTION PIGGYBACK PRODUCT uPD78CG14 On Chip EPROM Type 8 Bit Microcontroller with A D Converter The uPD78CG14 8 bit microcontroller allows program memory standard 27C256 27C256A EPROM to be connected by the piggyback method The uPD78CG14 is pin compatible with the uPD78C114 78C124 78C14 OUIP type 8 bit shingle chip microcontrollers with on chip mask ROM and has identical functions The uPD78CG 14allows the program to be changed by rewriting the EPROM andis suitable for uPD78C1 1A 78C12A 78C14 evaluation and limited production Features e Compatible with uPD78C114 78C12A 78C14 QUIP type products Capacity accessible as piggyback memory be changed by software 16K 8K 4K bytes e Program memory addressing capacity 65280 x 8 bits On chip RAM capacity 256 x 8
180. characteristics exceeds the specified value accuracy cannot be expected from the value obtained Then analog input circuit is as shown in Figure 15 1 It is connected to the sample hold capacitor via the protection register protection diode and analog switch There are one sample hold capacitor and one A D converter The analog input samples the input signal selected by the analog switch In this case if a voltage exceeding the specified analog voltage is applied to the analog input pin the analog switch conducts even if it is not selected This causes the sample hold capacitor to be charged When the analog input voltage Vian or discharged when the analog input voltage lt Vian making the selected analog input voltage change unreliable CHAPTER 15 OPERATING PRECAUTIONS Figure 15 1 Analog Input Circuit Block Diagram Analog switch configuration Es Y AN7 Analog switch N EN _ LP TT Lj ANn To A D converter i Sample hold capacitor gl e Remedy Limit the analog input voltage as described below 1 Limit the output voltage in the analog detecting circuit to the specified analog input voltage 2 Cramp the analog input pin using a Schottkey Barrier diode 78 18 331 CHAPTER 15 OPERATING PRECAUTIONS 15 8 Limitations on Hardware STOP Mode Target products uPD78C10 78C11 78C10A Standards 78C11A Standards
181. cial register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and stores the result in the specified special register b Flags affected Z SK lt 0 L1 0 LO lt 0 CY 274 CHAPTER 14 INSTRUCTION SET SUINB A byte Subtract Immediate from A Skip if No Borrow 1 Operation code O 0 1 1 0 1 1 0 2 Number of bytes 2 3 Number of states 7 7 4 Function lt A byte Skip if no borrow Subtracts the immediate data in the 2nd byte from the contents of the accumulator and stores the result in the accumulator Skips if no borrow is generated as a result of the subtraction 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY SUINB r byte Subtract Immediate from Register Skip if No Borrow 1 Operation code O 1 1 1 0 0 1 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function r lt r byte Skip if no borrow Subtracts the immediate data in the 3rd byte from the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 and stores the result in the specified register Skips if no borrow is generated as a result of the subtraction b Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6 Example To subtract immediate data from the HL register pair SUINB L IMM L c L IMM SKIP IF NO BORROW SUI H 1 SUINB sr2 byte Subtra
182. ct Immediate from Special Register Skip if No Borrow 1 Operation code O 1 1 0 1 0 0 S 0 1 1 52 Si So 2 Number of bytes 3 3 Number of states 20 11 4 Function Sr2 lt sr2 byte Skip if no borrow Subtracts the immediate data in the 3rd byte from the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 D and stores the result in the specified special register Skips if no borrow is generated as a result of the subtraction b Flags affected Z SK HC L1 e 0 LO lt 0 CY 6 Example 0 EQU 10H SUINB PA GENSU PA lt PA 10H This example subtracts GENSU defined by EQU from the contents of port A and stores the result in port A 275 CHAPTER 14 INSTRUCTION SET ANI A byte Add Immediate with A 1 Operation code 0 0 0 O 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function lt byte Obtains the logical product of the contents of the accumulator and the contents of the immediate data in the 2nd byte and stores the result in the accumulator 5 Flags affected ZSK 0 L1 0 L0 0 ANI r byte And Immediate with Register 1 Operation code O 1 1 1 0 1 0 0 2 Number of bytes 3 3 Number of states 11 11 4 Function byte Obtains the logical product of the contents of the register V B D
183. cuit outputs the contents of the level F F LVO to the COO pin and inverts the LVO contents Only in the event of a match between ECNT ETM1 the ECNT contents are cleared and the count starts again from 0000H Thus a rectangular wave output is obtained from COO with a pulse width equal to the count time determined by the count value set in ETMO and ETM1 see Figure 6 16 Internal interrupts can be disabled by setting 1 the MKEO MKE1 bits of the interrupt mask register MKL Rectangular wave output from the CO1 pin is implemented in the same way as square wave output from the COO pin by changing the mode register setting Figure 6 16 Programmable Rectangular Wave Output Mode Operation Internal clock 12 Start ECNT clearance ECNT clearance Remark ETMO2m lt m n count value ETM1 n 96 CHAPTER 6 TIMER EVENT COUNTER FUNCTIO 6 3 6 Timer event counter program examples Two examples of timer event counter programs are given here for programmable rectangular wave output and single pulse output synchronized with the fall of the Cl input 1 Programmable rectangular wave output The programmable rectangular wave output example outputs a rectangular wave from the COO pin as shown in Figure 6 16 In this example the low level width is 200 us and the high level width 300 us at 12 MHz operation The operation flow is shown below Timer event counter initialization Port C initialization lt b
184. cycles 27 2 5 2 1 9 MODEO MODE1 Mode Input output uPD78C18 78C14 78C14A 78C12A 78C11A The MODEO pin is set to 0 low level and the MODE pin is set 1 high level via a pull up resistor pull up resistor R is 4 KO R 0 4 tcvc kO tcvc unit is ns When the MODEO pin is set to 0 low level and the MODE is 1 high level on chip ROM is not accessed and these pins are functioned in the same way as those of the uPD78C17 78C10A uPD78C17 78C10A The size of the externally installed memory be selected as 4 bytes 16K bytes or 63K 64K bytes according to the settings of the MODEO and MODE 1 pins Table 2 4 MODEO and Functions uPD78C17 78C10A External Address Space 4K bytes addresses 0000H to OFFFH 16K bytes addresses 0000H to 3FFFH Setting prohibited 63K bytes addresses 0000H to FBFFH Note 2 64K bytes addresses 0000H to FEFFH Notes 1 Pull up resistor required The pull up resistor is 4 KO R 0 4 tcvc tcvc unit is ns 2 63K uPD78C17 64K uPD78C10A When the MODEO and pins are pulled high up 1 a control signal is output in synchronization with ALE MODEO and input signals are sampled periodically and the mode is set Caution The uPD78CP18 and 78CP14 use the MODEO pin for input and the pin for input output 2 1 10 N
185. d yppNote1 High voltage input in write verify high level input in read CENote1 Chip enable input OENote1 Output enable input A13 to AQNotes1 2 Address input A14 to AQNotes1 3 Address input PFENote2 Low level input in write verify and read O7 Oo0Note1 Data input in write data output in verity read VppNote1 Notes 1 These pin 2 uPD78CP 3 uPD78CP Power supply voltage input S correspond to the uPD27C256A 14 only 18 only Cautions 1 The uPD78CP18DW 78CP18KB 78CP14DW 78CP14KB 78CP14R which are provided with an erase window should be fitted with a light protective cover film when EPROM erasure is not being performed 2 The uP D78CP18CW 78CP18GF 3BE 78CP18GOQ 36 78CP14CW 78CP14G 36 78CP 14GF 3BE 78CP14L one time PROM products are not provided with an erase window and thus UV erasure cannot be used on these devices 207 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS uPD78CP18 78 13 1 PROM Programming Operating Modes The PROM programming operating mode is set as shown in table 13 2 Pins not used for programming should be connected as shown in Table 13 3 Table 13 2 PROM Programming Modes Operating Mode PFGNote2 Program Program verify Program inhibit Read Output disable Standby Notes 1 These pins correspond to the uPD27C256A 2 uPD78CP14 only Caution When
186. d a timer F F Timer operation and square wave output is controlled by the timer mode register Each interval timer TIMERO and TIMER1 consists of an 8 bit upcounter 8 bit comparator and 8 bit timer REGO 1 TMO and 1 1 2 3 4 Upcounter This counts up using the input clock specified by the timer mode register TMM Timer REGO 1 TMO TM1 These are 8 bit registers used to set the interval time Comparator The comparator compares the upcounter contents with the timer REGO 1 contents and if they match clears the upcounter and generates an internal interrupt INTTO INTT1 Timer F F This F F is inverted by a TIMERO TIMER1 match signal or the internal clock The output of this timer F can be output to the TO pin dual function as PC4 The timer F F output can be used irrespective of the pin mode status as the basic timer of the timer event counter according to the specification of the timer event counter mode register or as the serial clock SCK according to the serial mode register specification The timer is also used for generation of the oscillator stabilization time when standby mode STOP is released see 10 1 Standby Functions for details 75 5 5 TIMERO Figure 5 1 Timer Block Diagram 1 o 12 384 Timer mode register Timer REG1 1
187. d accumulator and stores the result the extended accumulator Skips if no borrow is generated as a result of the subtraction 5 Flags affected Z SK HC L1 lt 0 10 lt 0 CY DAN EA rp3 And Register Pair with EA 1 Operation code O 1 1 1 0 1 0 0 1 00 0 1 1 Pi Po 2 Number of bytes 2 3 Number of states 11 8 4 Function EA lt EA rp3 Obtains the logical product of the contents of the extended accumulator and the contents of the register pair rp3 BC DE HL specified by P1Po 1 to 3 and stores the result in the extended accumulator 5 Flags affected Z 5 lt 0 1 lt 0 0 0 296 CHAPTER 14 INSTRUCTION SET DOR EA rp3 Or Register Pair with EA 1 Operation code O 1 1 1 0 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function lt v rp3 Obtains the logical sum of the contents of the extended accumulator and the contents of the register pair rp3 DE HL specified by P1Po 1 to 3 and stores the result in the extended accumulator 5 Flags affected Z 5 lt 0 1 lt 0 10 0 DXR EA rp3 Exclusive Or Register Pair with EA 1 Operation code O 1 1 1 0 1 0 0 1 0 0 1 0 1 Pi Po 2 Number of bytes 2 3 Number of states 11 8 4 Function EA lt EA v rp3 Obtains the exclusive logical sum of the contents of the extended accumulator and the contents of the register pa
188. ddress 4000H 4000H to 4003H 4008H to 400BH 4010H to 4013H and 4018H to 401BH the start address 4020H of the next block is stored in the HL register pair and OSH in the B register The ANI2 bit of the A D channel mode register is inverted to change the input pin on which A D conversion is to be performed and a return is made from the routine When A D conversion values are stored in the memory blocks starting at 4020H 4020H to 4023H 4028H to 402BH 4030H to 4033H and 4038H to 403BH the program jumps to d The C register is the counter used to check whether or not A D conversion values have been stored in the memory blocks starting at 4020H 149 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS d e lt f gt As the A D conversion values are stored in memory blocks stating at address 4020H the start address 4004H of the next block is stored in the HL register pair in the B register and in the C register The ANI2 bit of the A D channel mode register is inverted to change the input pin on which A D conversion is to be performed and a return is made from the routine When A D conversion values are stored in the memory blocks starting at 4004H 4004H to 4007H 400CH to 400FH 4014H to 4017H and 401CH to 401FH the program jumps to e The D register is the counter used to check whether or not A D conversion values have been stored in the memory blocks starting at 4004H As the A D conversion valu
189. de 334 15 6 78 8 Read Operation ee tede ee res e ads RR Rue BR ed 335 1 Memory 78 614 tds 343 A 2 Memory Map uPD78G12A 344 A 3 Memory uPD78C11A 0 2 222 22020000000 000000 345 4 Memory Mapping Register Format UPD78CG14 347 5 10 27 256 348 LIST TABLES Table No Title Page 2 1 PEO Cm 24 2 2 Operation of to PFO 78 18 78 14 78 14 78 12 78 11 78 18 78 14 26 2 3 Operation of PF7 to PFO uPDZ8C17 78C 10A uicina t cett id 27 2 4 MODEO and Functions 78 17 78 10 28 2 b DG oA 31 3 1 Mode Register FUNCtHONS uii 41 3 2 Flag 43 4 1 Operation of PD7 to PDO 78 18 78 14 78 14 78 12 78 11 78 18 78 14 70 4 2 Operation of to PFO uPD78C18 78C14 78C144 78C12A 78C114 78CP18 78CP14 72 4 3 Op ration of PF7 to PEO uPD7BC 17 78 TO nnd ceres tte re nenne d ei a 72 4 4 O
190. de setting lt b gt Interrupt mask register setting SET RETI 102 CHAPTER 6 COUNTER a 100 us after the fall of the Cl input a pulse with a width of 200 us is output to the COO pin and thus the value obtained by adding 0064H 100 us to the ECPT value is set in ETMO and the value obtained by adding 012CH 300 us to the ECPT value is set in ETM1 at 12 MHz operation b COO output timing is specified by setting the timer event counter mode register ETMM to a match between ECNT ETMO or between and ETM1 The ECNT input clock and ECNT clear mode are kept as they are LVO of the output control circuit is set and L VO level inversion enabled by setting the timer event counter output mode register EOM Figure 6 24 Timer Event Counter Mode Register Setting Single Pulse Output COO Output Timing Setting 5 4 3 2 1 0 1 7 6 mw TS T CEST TIS ECNT input clock Internal clock 6 2 ECNT clear mode Free running COO output timing Match between ECNT and ETMO or match between ECNT and ETM1 7 6 5 4 3 2 1 0 XJENEXNEZESESESEHRX LVO level inversion enabled LVO set c Masking of interrupts INTE1 generated by a match between ECNT and ETM1 is released by setting the interrupt mask register MKL INTEO interrupts which have the same priority as interrupts must be masked 103 CHAPTER 6 TIMER
191. dgement is enabled even for that interrupt request itself or interrupt requests of lower priority In this case too if multiple interrupt requests are generated simultaneously the highest priority request is acknowledged and the lower priority requests are held pending The pending interrupt requests are acknowledged when the state is subsequently entered if no other interrupt requests of higher priority have been generated Since there are practically no restrictions on the stack area used when an interrupt is generated as long as the memory size is sufficient multiple interrupt levels can also be used without restriction see Figure 9 8 Figure 9 8 3 Level Multiple Interrupts 0010H 0008H 18 INTI 0018H INTTO EI ORI MKH 02H INTEO INTSR Not acknowledged y ANI MKH OFDH 0028H RETI RETI El RETI El RETI Remark f masking is released by the mask register for two interrupt sources of the same priority which of the two interrupt requests is concerned must be determined before executing the El instruction at the start of the interrupt service routine 169 170 CHAPTER 10 CONTROL FUNCTIONS 10 1 Standby Functions Three standby modes are available for the uPD78C18 to save power consumption in the program standby state The HALT mode software STOP mode and hardware STOP mode 10 1 1 HALT mode When the HLT instruction is executed the HALT mode is set unless
192. dress 500 500 SOFTI 501 502 Memory SP 3 SP 2 SP 1 0 Z SK HC L1 LO O CY 500 01 The following functional difference between the 87 87AD series should be noted The uCOM 87 SOFTI instruction saves the address of the SOFTI instruction itself to the stack memory whereas the address saved to the stack memory by the 87AD series SOFTI instruction is the start address of the next instruction Even if the skip condition is satisfied by execution of the instruction arithmetic or logical operation increment decrement skip or RETS instruction immediately preceding the SOFTI instruction the SOFTI is executed not skipped see 9 4 Maskable Interrupt Operation CHAPTER 14 INSTRUCTION SET 14 6 14 Return instructions RET Return from Subroutine 1 Operation code L0 3d 151 9 0 0 2 Number of bytes 1 3 Number of states 10 4 4 Function PC7 0 SP lt SP 1 SP lt SP 2 Restores the contents of the stack memory addressed by the SP to the low order 8 bits PC7 0 of the program counter and restores the contents of the stack memory addressed by SP 1 to the high order 8 bits PC1s 8 5 Flags affected lt 0 11 lt 0 10 lt 0 RETS Return from Subroutine and Skip 1 Operation code 1 0 1 1 1 0 0 1 2 Number of bytes 1 3 Number of states 10 4 4 Function PC7 0 lt S
193. dressed by Register Pair from A Skip if No Borrow 1 Operation code O 1 1 1 0 0 0 0 1 0 1 1 0 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function A lt A rpa Skip if no borrow Subtracts the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by A2A1Ao 1 to 7 from the contents of the accumulator and stores the result in the accumulator Skips if no borrow is generated as a result of the subtraction b Flags affected Z SK L1 lt 0 LO 0 CY 6 Example SUBNBX B A A BC A skip is performed if no borrow is generated as a result of the subtraction 265 CHAPTER 14 INSTRUCTION SET ANAX rpa And Memory addressed by Register Pair with A 1 Operation code O 1 1 1 0 0 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function lt rpa Obtains the logical product of the contents of the accumulator and the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by 1 1 to 7 and stores the result in the accumulator b Flags affected 2 lt 0 11 lt 0 10 lt 0 6 Example lt AA HL HL HL 1 This example obtains the logical product of and the memory contents addressed by the HL register pair and stores the result in A and then decrements HL ORAX rpa Or Me
194. e T Tee De Te e SCK selection Internal clock TO output Internal clock Internal clock External clock Disable Enable Reception enable Disable Enable I O interface mode SCK trigger Disable Enable 123 CHAPTER 7 SERIAL INTERFACE FUNCTIONS In the I O interface mode the transmit data TxD is transferred MSB first on the falling edge of the serial clock SCK Receive data RxD is input on the rising edge of SCK Serial data Figure 7 9 1 Interface Mode Timing SCK In this mode character synchronization is implemented using the controlled SCK 8 serial clock pulses An external clock or internal clock can be selected as SCK by means of the serial mode high register When an internal clock is used as SCK the controlled clock 8 pulses per data item is output from the SCK pin When an external clock is used as SCK 8 clock pulses should be accurately supplied to SCK as the single data item transfer 8 bit unit by the control signal supply source Caution Inthel O interface mode one pulse is output at low level from the TxD pin at the time of changing from the transmit enable state to receive enable state transmit disable 1 Data transmission 124 A transmit operation in the 1 0 interface mode is enabled by setting 1 the TxE bit of the serial mode high register When data is written to the tr
195. e 3rd byte Low address and 4th byte High address 5 Flags affected SK lt 0 11 lt 0 LO lt 0 lt 6 gt 5 MOV EXAM A Transfer to memory addressed by label EXAM 235 CHAPTER 14 INSTRUCTION SET MVI r byte Move Immediate to Register 1 Operation code O 1 1 0 1 Ri Ro 2 Number of bytes 2 3 Number of states 7 7 4 Function i r byte Transfers the immediate data in the 2nd byte Data to the register r V A B C D E H L specified by 2 1 0 to 7 Has a stacking effect when A or L is specified as r b Flags affected SK 0 L1 lt 1 LO 0 when r A SK 0 L1 0 LO lt 1 when r L SK lt 0 L1 lt 0 LO lt 0 other cases 6 Example MVI D OAFH Load AFH into the D register MVI sr2 byte Move Immediate to Special Register 1 Operation code O 1 1 0 53 0 0 0 0 52 Si So 2 Number of bytes 3 3 Number of states 14 11 4 Function Sr2 lt byte Transfers the immediate data in the 3rd byte to the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 D 5 Flags affected SK 0 L1 0 10 0 236 CHAPTER 14 INSTRUCTION SET MVIW wa byte Move Immediate to Working Register 1 Operation code O 1 1 1 0 0 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Funct
196. e opposite active state its functions are the same as those of the INT1 input AN7 to AN4 inputs A falling edge is detected by the same method as for the INT2 input and the test flag is set AN7 to 4 of the test flag register These flags can be tested by an instruction SKIT or SKNIT and are automatically reset when tested In setting a testable flag again the criterion for detection is a low level input signal for a duration of at least 12 states after first returning to the high level CHAPTER 9 INTERRUPT CONTROL FUNCTION Figure 9 3 Interrupt Sampling pret Sampling pulses INT2 Valid AN7 5 INT1 INTF1 2 AN7 AN4 As can be seen from the above diagram INT1 INT2 and AN7 to AN4 are determined to be correct interrupt signals when the active level is detected in 3 or more 12 0 8 us at 15 MHz operation cycle sampling pulses Therefore noise signals of 8 states 1 6 us at 15 MHz operation or shorter duration are eliminated and the interrupt request flag is properly set by a high level or low level input of at least 12 states 2 4 us at 15 MHz operation 159 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9 3 Non Maskable Interrupt Operation When the INTFNMI interrupt request flag is set by a falling edge input to the NMI pin a non maskable interrupt is acknowledged by means of the following procedure irrespective of the EI DI state see Figure 9 4 i Acheck is made to see if INT
197. e register pair BC DE DE HL DE HL specified by 2 1 1 to 7 to the contents of the accumulator including the CY flag and stores the result in the accumulator 5 Flags affected Z SK 0 L1 0 LO 0 CY 6 Example ADCX D lt DE CY DE e DE 1 This example adds the contents of the memory addressed by the DE register pair to A and stores the result in A and then increments DE 263 CHAPTER 14 INSTRUCTION SET ADDNCX rpa Add Memory addressed by Register Pair to A Skip if No Carry 1 Operation code O 1 1 1 0 0 0 0 1 0 1 0 0 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function lt A Skip if carry Adds the contents of the memory addressed by the register pair BC DE DE HL DE HL specified A2A 1Ao 1 7 and the contents of the accumulator and stores the result in the accumulator Skips if no carry is generated as a result of the addition 5 Flags affected Z SK L1 lt 0 LO lt 0 CY 6 Example LXI H 4200H HL lt 4200H LXI D 4000H DE lt 4000H MOV 4100H lt 4100H ADDNCX D lt A DE DE lt DE 1 STAX H HL A JMP MOTOE This example adds together the contents of address 4100H and address 4000H and stores the result in address 4200H if no carry is generated If a carry is generated the STAX i
198. ed Z SK HC L1 lt 0 LO 0 CY 6 Example SUBNB A D amp A D A skip is performed if no borrow is generated as a result of the subtraction SUBNB r A Subtract A from Register Skip if No Borrow 1 Operation code O 1 1 0 0 0 0 0 0 0 1 1 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function 5 lt r A Skip if no borrow Subtracts the contents of the accumulator from the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 and stores the result in the specified register Skips if no borrow is generated as a result of the subtraction 5 Flags affected Z SK HC L1 lt 0 10 lt 0 CY 6 Example To subtract A from the HL register pair SUBNB L A L lt L A SKIP IF NO BORROW SUI H lt H 1 256 CHAPTER 14 INSTRUCTION SET ANA A r And Register with A 1 Operation code O 1 1 0 0 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function lt A r Obtains the logical product of the contents of the accumulator and the contents of the register V A B C D E H L specified by R2R Ro 0 to 7 and stores the result in the accumulator 5 Flags affected Z 5 lt 0 1 lt 0 10 0 6 Example lt A with Register 1 Operation code 0 1 1 0 0 0 0 0 0 0 0 1 Ri Ro 2 Number of bytes 2
199. ed Next a RETI instruction is executed to restore the previously saved return address and PSW in the order lower PC byte upper PC byte PSW Caution If the skip condition is satisfied by the instruction arithmetic or logical operation increment decrement shift skip or RETS instruction immediately before the SOFTI instruction the SOFTI instruction is executed and not skipped When SOFTI instruction is executed the SK flag of the PSW is saved as set 1 to the stack area Thus when the return is made from the SOFTI service routine the PSW SK flag remains set and the instruction following the SOFTI instruction is skipped Note that the 87AD series SOFTI instruction differs from that of the 87 in that the address contents saved to the stack memory are the start address of the next instruction 167 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9 6 Interrupt Wait Time The time required from acknowledgement by the CPU of an asynchronously generated external interrupt until execution of the first instruction of the relevant interrupt service routine begins the interrupt wait time is the sum of time components and shown in Table 9 2 This interrupt wait time varies depending on the kind of instruction being executed when the interrupt occurs and the instruction timing at which the interrupt occurs Table 9 2 shows maximum interrupt wait times The 14 states of component 10 us max in the case of NMI indicate the t
200. ed RAM and not on chip RAM is used In normal operation this bit retains its value when RESET is input Cautions 1 Overwriting the RAE bit during program execution allows an apparent increase of 256 bytes in the memory space However this operation cannot be emulated by an emulator and should therefore not be performed 2 The RAE bit is undefined after a power on reset and must therefore be initialized by an instruction 190 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND In the uPD78CP18 78CP14 bit MM5 to MM7 are also valid These are used to specify the access range of the on chip EPROM See CHAPTER 12 PROM ACCESSES uPD78CP18 78CP14 ONLY for details Figure 11 2 Memory Mapping Register Format uPD78C18 78C14 78C14A 78C12A 78C11A 7 6 5 4 3 2 1 0 Te Pe e Single chip Port mode PD7 to PDO Input port PF7 to PFO Port mode PD7 to Output port PF7 to PFO Port mode 256 bytes PD7 to Expansion mode PF7 to PFO Port mode bytes PD7 to PDO PF3 to PFO PF7 to PF4 Expansion mode Port mode Expansion mode 16K bytes PD7 to PDO to PFO PF7 amp PF6 Expansion mode Port mode 31K 48K 56K 60K Disable PD7 to PDO PF7 to PFO Expansion mode Enable Note 31K uPD78C18 48K uPD78C14 78C14A 56K uPD78C12A 60K uPD78C11A 191 CHAPTER 11 EXTE
201. eed to be taken for PW boards with semiconductor devices on it HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset function QTOP is a trademark of NEC Corporation MS DOS is a trademark of Microsoft Corporation PC AT and PC DOS are trademarks of IBM Corporation The export
202. een making continuous effort to enhance the reliability of its semiconductor devices the possibility of defects cannot be eliminated entirely To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device customer must incorporate sufficient safety measures in its design such as redundancy fire containment and anti failure features NEC devices are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application The recommended applications of a device depend on its quality grade as indicated below Customers must check the quality grade of each device before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support c Aircrafts aerospace equipment submersible repeaters nuclear reactor control systems life support systems or medical equipment for life support etc The quality grade of NEC devices in Standa
203. egister to A with Carry 1 Operation code 0 1 1 0 2 Number of bytes 3 3 Number of states 14 11 4 Function DA lt A V wa CY Adds the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits to the contents of the accumulator including the CY flag and stores the result in the accumulator b Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY ADDNCW wa Add Working Register to A Skip if No Carry 1 Operation code O 1 1 1 1 0 0 1 0 1 0 0 0 0 0 lt 2 gt Number of bytes 3 3 Number of states 14 11 4 Function lt A V wa Skip if no carry Adds the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits to the contents of the accumulator and stores the result in the accumulator Skips if no carry is generated as a result of the addition b Flags affected Z SK HC L1 e 0 LO 0 CY 285 CHAPTER 14 INSTRUCTION SET SUBW wa Subtract Working Register from A 1 Operation code O 1 1 1 0 1 0 0 1 1 1 0 0 0 0 0 lt 2 gt Number of bytes 3 3 Number of states 14 11 4 Function lt A V wa Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits
204. enne 8 2 A D Channel Mode Register 414 400022 8 3 Analog Digital Converter Operation 8 3 1 Scan MIA OC Scat Cr 832 JSelecEmode cassette 8 3 3 A Dconverter operatiori control Method i a mrt tare tao ecce 8 3 4 Input voltage and conversion results 2 2 222 2 8 3 5 Example of analog digital converter program 222222 2 2 21 98 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9 1 Interrupt Control Circuit Configuration 4 4244422 222 22 9 2 External Interrupt Sampling rero ouo peres ose 9 3 Non Maskable Interrupt Operation 9 4 Maskable Interrupt 0 0 9 5 Interrupt Operation by SOFTI Instruction 4 2442 2 2222 9 6 Interrupt Wait 4 9 7 Multiple Interrupts icciccsicscccsiccscccsssssesccaseceeccececsesesinsssecenccsecderanecessansenaecsoueesesseeteenacs daadaa CHAPTER 10 CONTROL FUNCTIONS 10 1 Standby Functions HALT HALT mode release Software STOP mode 10 1 1 10 1 2 10 1 3 10 1 4 Software STOP mode release 10 75 Hardware STOP
205. er in Select Mode 7 6 5 4 3 2 1 0 1 J Select mode Analog input specification gt gt gt gt gt gt gt gt 192 states 144 states 143 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS A D conversion is performed on the single analog input specified by the A D channel mode register and the A D conversion result is stored in the order CRO gt CR1 CR2 CR3 When the conversion values have been stored in all four CR registers CRO to CR3 an INTAD internal interrupt is generated The A D converter continues A D conversion again irrespective of whether or not an interrupt request has been acknowledged and stores the A D conversion results in order starting with CRO Thus the most recent conversion values are always stored in the CR registers The A D converter repeats the above operation until the contents of the A D channel mode register are changed This mode holds the most recent conversion values for the selected analog inputs and is useful for averaging conversion values or preventing noise input etc Internal interrupts are disabled by setting 1 the MKAD bit of the interrupt mask register MKH Figure 8 6 Outline of A D Converter Operation Timing in Select Mode ANn ANn ANn ANn ANn conversion conversion conversion conversion conversion operation operation operation operation operation Sampling Sampling Sampling Sampling ANM Conv
206. ersion Conversion Conversion Conversion Conversion register result write result write result write result write result write write to CRO register to CR1 register to CR2 register to CR3 register to CRO register INTFAD flag setting 8 3 3 A D converter operation control method A D converter operation can be stopped by controlling the Varer input voltage When a voltage of Viu or more is input to the Varer pin the A D converter starts the conversion operation and the conversion result is guaranteed for 3 4 V to AVop If the Vaner pin input voltage is made Vii or less during the conversion operation the A D converter conversion operation stops and CRO to CR3 contents are undefined If the Varer input voltage is changed for A D converter to stop control the A D channel mode register ANM is not affected Thus if the Varer input voltage is increased to 3 4 V or more to reset the operating state from the stop state the A D converter restarts its operation by storing a conversion value in CRO in the mode in effect just before it stopped If the Varer input voltage level is changed the edge detection function of inputs AN4 AN7 is not affected Caution When Varer is low inputs ANO to AN7 must be in the range from AVss to AVpp 144 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNC 8 3 4 Input voltage and conversion results Relationship between the analog input voltage input to the analog input pin ANO to AN7 and the A D conver
207. es are stored in memory blocks starting at address 4004H the start address 4024H of the next block is stored in the HL register pair in the B register and OOH in the C register and D register The ANI2 bit of the A D channel mode register is inverted to change the input pin on which A D conversion is to be performed and a return is made from the routine When A D conversion values are stored in the memory blocks starting at 4024H 4024H to 4027H 402CH to 402FH 4034H to 4037H and 403 to 403FH the program jumps to f The E register is the counter used to check whether or not A D conversion values have been stored in the memory blocks starting at 4024H The A D conversion values are stored in memory blocks starting at address 4024H and A D conversion values are stored in the entire area from 4000H to 403 Therefore initialization is performed in order to store A D conversion values in the memory blocks starting at address 4000H once again The interrupt service routine is shown below A JMP ADSE instruction must be stored in the INTAD interrupt address 0020H 150 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNC A D CONVERTER SERVICE ADSE ARIN ARSTO ARST1 ARST2 RETO RET1 RET2 EXA EXX MOV DCR JR MOV DCR JR LXI LXI MVI JR INX JR LXI JR LXI MOV JR LXI MOV MVI MVI XRI CRO 1
208. escribes the uPD78C18 as a representative product as long as there no differences in the functions Using this manual as the other 87AD series CMOS products manual refer to the manual by changing uPD78C18 to each product name For the uPD78CG14 referto APPENDIX A INTRODUCTION TO PIGGYBACK PRODUCT For the Special quality grade product refer to the manual by changing it to the Standard quality grade product Legend lt For general understanding of the 87AD series CMOS product functions Read in order of contents gt For searching for an instruction function by mnemonics Use APPENDIX C INDEX OF INSTRUCTIONS ALPHABETICAL ORDER For searching for mnemonics by the outline of functions Search 14 6 Instruction Descriptions for the functions Usage examples in this manual is produced for the Standard quality grade Using this manual for the Special quality grade applications make use of parts and circuits actually used after checking the quality grade Operating Precaution Be sure to read CHAPTER 15 OPERATING PRECAUTIONS in which operating precautions of the 87AD series CMOS products are compiled For the latest information of this products contact our salesman or special agent Data notation weight Upper digits to the left lower digits to the right Notation of active low Xxx A line over pin or signal names Address the memory map Lower address to the upper part higher addr
209. eset period or automatically used timer when returning from the hardware STOP mode 3 RESET input or preset timer when returning from the software STOP mode Using a crystal resonator C1 C2 10 pF should be kept The values of C1 and C2 as recommended resonator when ceramic resonator is used are shown in Table 10 5 184 CHAPTER 10 CONTROL FUNCTIONS Table 10 5 Recommended Ceramic Resonator 1 2 Recommended C1 pF C2 pF uPD78C10A Murata Mfg Co Ltd CSA15 00MX001 15 78C11A CSA12 0MT 30 78C12A CST12 0MT Build in Product Name Manufacturer Part Name CST12 0MTW uilt in CSA7 37MT 30 CST7 37MT CST7 37MTW FCR15 0MC FCR10 0MC FCR8 0MC uPD78C14 Murata Mfg Co Ltd CSA15 0MX3 CSA12 0MT CST12 0MT CST12 0MTW CSA10 0MT CST10 0MT CST10 0MTW CSA6 00MG CST6 00MG FCR15 0MC FCR12 0MC FCR10 0MC FCR8 0MC 78 14 Murata Mfg Co Ltd CSA15 0MX3 CSA12 0MT CST12 0MT CST12 0MTW CSA10 0MT CST10 0MT CST10 0MTW CSA6 00MG CST6 00MG FCR12 0MC 185 CHAPTER 10 CONTROL FUNCTIONS Table 10 5 Recommended Ceramic Resonator 2 2 Recommended C1 pF C2 pF uPD78CG14 Murata Mfg Co Ltd CSA15 0MX3 22 22 CSA12 0MT 30 30 CST12 0MT Built in Built in Product Name Manufacturer Part Name
210. eset state to the STOP mode The STOP pin must be driven high after powering on The reset will not function correctly if the STOP pin is left low The STOP pin can be driven low after oscillator operation has stabilized 177 CHAPTER 10 CONTROL FUNCTIONS 10 1 6 Hardware STOP mode release When the STOP signal changes from the low to high level in the hardware STOP mode the hardware STOP mode is released and simultaneously clock oscillation starts After the elapse of the wait time approximately 65 ms at 12 MHz which takes account of the oscillation stabilization time the CPU starts program execution at address 0 see Figure 10 7 Figure 10 7 Hardware STOP Mode Release Timing STOP Signal Input Execution of STOP Instruction Wait approx 65 ms 12 MHz address 0 execution 4 instruction CPU operation The hardware STOP mode is not released by a high to low transition of the RESET signal When the STOP signal changes from low to high while the RESET signal is low the hardware STOP mode is released and clock oscillation starts If the RESET signal returns from the low to high level the CPU starts program execution at address 0 without waiting for the elapse of the oscillation stabilization time see Figure 10 8 If the RESET signal changes from the high to low level just after the hardware STOP mode has been released after the STOP signal has changed from the low to high level program execut
211. esirable voltage is maintained in a state where 2 5 V operational voltage range Therefore the SB flag cannot be used for a test as to whether the RAM back is normal after releasing software hardware STOP mode e Remedy Keep the data retention voltage over 2 5 V by hardware in the software hardware STOP mode 15 10 Bus Interface Target products All products Details Incase where a is expanded externally connecting a comparatively speedy SRAM may cause large current to run in the read operation due to collision of address output signal from address data PD7 to PDO with SRAM output signal Figure 15 6 78 18 Read Operation PF7 0 A8 A14 PD7 0 A0 A7 Address Low order tLDR ALE Data read SRAM read cycle Remark Symbols in are SRAM uPD43256A pin names Remedy connect SRAM insert gates etc between the RD SRAM OE pins to give a delay to the RD active signal In this case be sure to satisfy the trp specification as given below toe tDELY lt tRD 335 CHAPTER 15 OPERATING PRECAUTIONS Sample Solution u PD78C18 uPD74HC04 L Lead another peripheral 15 11 Restrictions on IE 78C11 M Operation e Target products 1 78 11 Details The 78 11 uses the uPD78C10G 36 as the emulation CPU includes defects mentioned in 15 4 Restrictions on Serial Interfa
212. ess to the lower part Note Explanation of Note in text Caution Content to be read carefully Remark Complementary explanation of text Numeric notation Binary or Decimal Hexadecimal xxxxH Related Documents The following documents are provided for 87AD series CMOS version products Numbers in the table are document numbers Document Name Product Name 078 uPD78C Data Sheet 1872 078 uPD78C 078 2678 uPD78C 2417 078 2565 uPD78CG14 2564 uPD78CP14 2533 uPD78C17 2788 78 18 2789 uPD78CP18 3033 078 uPD78C 2814 uPD78C10A A uPD78C11A A 78 12 2846 uPD78C14 A 2813 uPD78CP14 A 3068 uPD78C 078 3127 PD78CP18 A 3233 User s Manual This manual Application Note e 1 Software fundamental IEM 1131 Floating point format operation package IEM 1242 e 111 Hardware IEM 1240 The contents of the above documents are subject to change without prior notification Please check whether requested documentation is the latest version 87AD Series CMOS Version Development uPD78C18 HPD78CP18 PROM product uPD78C17 ROM less product
213. et is a power on reset The SB flag is set 1 only when the supply voltage changes from a given voltage or below to a given voltage or above This flag can be tested by the SKIT SB or SKNIT SB instruction and is automatically reset 0 when either of these instructions is executed Figure 10 10 Relation between Vpop and SB Flag SB flag j STOP mode entered SKIT SB Instruction SKNIT SB execution Caution The software hardware STOP mode should not be released while in the low supply voltage data retention mode must be raised to the normal operating voltage before the release is performed 179 CHAPTER 10 CONTROL FUNCTIONS 10 2 Reset Functions When a low level signal is input to the RESET pin a system reset is effected and initialization is performed as shown below Table 10 3 Hardware States after Reset 1 2 Hardware State after Reset Internal data Power on reset Previous contents retained memory Reset input During CPU Write address data Undefined during normal write operation Data in other addresses Previous contents retained operation During non write CPU operation Extended accumulator EA EA Undefined Accumulators A A General purpose register C D E H L B C D E H 17 Working register vector register V V Program counter PC 0000H Stack pointer SP Undefined Ports ode reg
214. fer register and a serial reception interrupt INTSR is generated When SCK is an external clock the data sent in synchronization with SCK is input to the serial register on the rising edge of SCK When SCK is an internal clock it must be started by setting 1 the TSK bit of the serial mode high register SMH Serial reception interrupts are disabled by setting 1 the MKSR bit of the interrupt mask register MKH The maximum data transfer rate in reception is 625 kbps when an internal clock is used as SCK and 660 kbps when an external clock is used at 15 MHz operation The high level width of the 8th SCK pulse must be at least 6 states Caution 1 When fewer than 8 external clock pulses are input in transmission The correction procedure is shown below for the case where fewer than 8 external clock pulses are input when performing transmission reception in the I O interface mode using external clock input 1 TxE bit reset to 0 Disable transmission 2 Change MC register MC 2 5 set to 1 Set to input port 0 reset to 0 Outputs high level PC 0 set to 1 Set to output port 3 Change MMC register 2 reset to 0 SCK pin set to port mode 0 reset to 0 TxD pin set to port mode 4 Change SMH SK1 0 or SK1 1 Set to internal clock mode 5 2 1 SK2 0 5 MKST bit gt set to 1 Mask INTST 6 INTFST flag reset to 0 7 TxE bit gt set
215. fice equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions unde
216. formed by testing the interrupt request flag INTFST The operation flow is shown below a b 131 CHAPTER 7 SERIAL INTERFACE FUNCTIONS a The interrupt request flag INTFST is tested to determine whether or not data can be written to the transmit buffer TXB b The accumulator contents are transferred to the transmit buffer The data transmission routine is shown below When data is transmitted from the uPD78C18 the uPD71051 must be in the reception enabled state TRNS SKIT FST Test FST skip if FST 1 zas JR TRNS Wait until FST 1 MOV TXB A Output transmit data b RET Return 3 uPD78C18 data reception For data reception hardware interrupts INTSR are used Initialization is therefore necessary beforehand including setting of the memory address used to store the receive data the number of received bytes the interrupt mask register etc The operation flow is shown below RVEN Set memory address Set number of received bytes eps Set interrupt mask register Spe Enable reception d CTS PC7 lt 0 lt e gt 132 CHAPTER 7 SERIAL INTERFACE FUNCTIONS a memory address for storing the receive data is set in the HL register pair The setting here is for storage of the receive data in address 2000H onward b The number of receive data bytes is set in the B register The setting here is for reception of 16 OFH data bytes c The
217. from the contents of the accumulator and stores the result in the accumulator b Flags affected Z SK 0 HC L1 010 lt 0 CY SBBW wa Subtract Working Register from A with Borrow 1 Operation code O 1 1 1 O 0 1 1 1 1 00 0 2 Number of bytes 3 3 Number of states 14 11 4 Function DA A V wa CY Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data the 3rd byte low order 8 bits including the CY from the contents the accumulator and stores the result in the accumulator 5 Flags affected Z SK 0 11 amp 0 LO lt 0 CY 286 CHAPTER 14 INSTRUCTION SET SUBNBW wa Subtract Working Register from A Skip if No Borrow 1 Operation code O 1 1 1 1 0 1 10000 lt 2 gt Number of bytes 3 lt 3 gt Number of states 14 11 lt 4 gt Function A lt A V wa Skip if no borrow Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits from the contents of the accumulator and stores the result in the accumulator Skips if no borrow is generated as a result of the subtraction b Flags affected ZL SK HC L1 lt 0 LO 0 CY 6 Example WORK EQU WORK EOH LOCA EQU 0 00 MVI V WORK V lt EOH SUBNBW LOCA lt A E000H When th
218. gister C E L of the register pair rp3 BC DE HL specified by P1Po 1 to 3 to the lower half EAL of the extended accumulator and the contents of the upper register B D H of the register pair to the upper half EAH b Flags affected SK 0 L1 0 10 0 6 Example DMOV EA B EAL lt C lt B DMOV sr3 EA Move EA to Special Register 1 Operation code O 1 0 1 0 0 0 2 Number of bytes 2 3 Number of states 14 8 4 Function i sr3 lt EA Transfers the extended accumulator contents to the special register sr3 1 specified by Uo 0 1 lt 5 gt Flags affected SK lt 0 11 lt 0 LO lt 0 6 Example DMOV EA Transfer EA to ETMO 242 CHAPTER 14 INSTRUCTION SET DMOV EA sr4 Move Special Register to EA 1 Operation code 010 0 1 0 0 0 1 10000 0 Vo 2 Number of bytes 2 3 Number of states 14 8 4 Function EA lt sr4 Transfers the contents of the special register sr4 ECNT ECPT specified by Vo 0 1 to the extended accumulator 5 Flags affected gt SK 0 L1 0 10 0 SBCD word Store B amp C Direct 1 Operation code Low address o lo olli J o o o lo High address 2 Number of bytes 4 3 Number of states 20 14 4 Function word lt word 1 B Stores the contents of the C register the memory addressed
219. gister Format 7 6 5 4 3 2 1 0 wow D pompe ons Operating mode specification Scan mode Select mode Select mode Scan mode ANO AN3 192 states AN4 AN7 144 states 141 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS 8 3 Analog Digital Converter Operation Either the scan mode or select mode can be specified for the A D converter by means of the MS bit of the A D channel mode register ANM 8 3 1 Scan mode In the scan mode as shown in Figure 8 3 the A D channel mode register ANM specifies either analog inputs ANO to 12 0 or analog inputs AN4 to ANI2 1 Remark Each of the analog inputs AN4 to has a function for detecting falling edge and setting a test flag which is unrelated to A D conversion operations see 9 2 External Interrupt Sampling Figure 8 3 A D Channel Mode Register in Scan Mode 7 6 5 4 3 2 1 0 ow T TER 5 Scan mode Analog input specification ANO AN3 AN4 AN7 Conversion speed 192 states 144 states When the ANI2 bit of the A D channel mode register is set to 0 analog inputs are selected in the order 0 gt 1 gt 2 gt 3 and the A D conversion value of each input is stored in the order gt 1 gt 2 gt Similarly when the ANI2 bit of the A D channel mode register is set to 1 analog inputs are selected in the order
220. gn bit This is performed when the following instruction is executed JR word Operation code jdisp1 15 0 T 15 654 0 ee jdisp1 15 0 5 0 O s 5 1 AI 1 s 218 CHAPTER 14 INSTRUCTION SET 14 3 5 Extended relative addressing The result of adding the 9 bit immediate data displacement value jdisp in the instruction to the start address of the next instruction is loaded into the PC and a jump is performed The displacement value is handled as signed two s complement data 256 to 255 with bit 8 bit O of the 1st byte of the operation code as the sign bit This is performed when the following instruction is executed JRE word 010011 1 j 5 0 X All0 s 5 1 AI 1 s 219 CHAPTER 14 INSTRUCTION SET 14 4 Operand Address Addressing There are several methods addressing methods as described below for specifying the register memory etc to be manipulated when executing an instruction 14 4 1 Register addressing With this addressing method the register to be manipulated is specified by the contents of the register specification code R2R Ro T2T1To 555453525150 etc in the instruction Register addressing is used when an instruction with the following operand formats is executed In some cases an 8 bit register is specified and in others a register pair 16 bits is specified Notation Description Method r V A C D E H
221. he HALT mode as shown in Table 10 2 Cautions 1 174 Table 10 2 Output Pin Statuses Output Pin Single ChipNete 1 External Expansion PA7 to Data retained Data retained PB7 to PBO Data retained Data retained PC7 to PCO Data retained Data retained PD7 to PDO Data retained High impedance PF7 to PFO Data retained Next address retainedNote 2 Data retainedNote 3 WR RD High level High level ALE High level High level Notes 1 4PD78C18 78C14 78C144 78C12A 78C11A 78CP18 78CP14 2 Address output pin 3 Port data output pin Internal interrupts should be masked before executing the STOP instruction to prevent errors due to an internal interrupt with the oscillation stabilization time upon release of the software STOP mode The TIMER1 coincidence signal is used as the signal to start CPU operation to secure oscillation stabilization period after the software STOP mode has been released by setting the non maskable interrupt request flag Thus it is necessary to set a count value in timer REG which takes account of the oscillation stabilization time and to set the timer mode register to the timer operating state before executing the STOP instruction Crystal oscillation or ceramic oscillation should be used when using the software STOP mode The software STOP mode must not be used when an external clock is input CHAPTER 10 CONTROL FUNCTIONS 10 1 4 Software STOP mode release
222. he contents of HL 4 Flags affected SK 0 L1 0 10 0 b Example LXI D 4000H DE lt 4000H STEAX D 4000H lt 4001H lt EAH DE lt 4002H STEAX D 10H 4012H lt EAL 4013H lt DE24002H This example stores the low order 8 bits EAL of the extended accumulator in address 4000H and address 4012H and stores the high order 8 bits EAH in address 4001H and address 4013H 245 CHAPTER 14 INSTRUCTION SET LBCD word Load B amp C Direct 1 Operation code Low address allo allo alto allo High address 2 Number of bytes 4 3 Number of states 20 14 4 Function C lt word lt word 1 Loads the contents of the memory addressed by the 3rd byte lower address and 4th byte upper address into the C register and loads the contents of the next memory address into the B register 5 Flags affected gt SK 0 L1 0 10 0 LDED word Load D amp E Direct 1 Operation code 1 1 1 Low address High address allo allo 2 Number of bytes 4 3 Number of states 20 14 4 Function E word D word 1 Loads the contents of the memory addressed by the 3rd byte lower address and 4th byte upper address into the E register and loads the contents of the next memory address into the D register 5 Flags affected SK 0
223. ide x a cea decer rhe e Veo re 177 10 16 Hardware STOP mode release ices i tee ER xd cR Edd 178 10 1 7 Low supply voltage data retention 2 2 9 9 179 10 2 5 Sui 180 10 3 Clock Generation 62 182 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS 187 11 1 uPD78C18 78C14 78C14A 78C12A 78C11A External Device Accesses 187 11 1 1 Memory mapping register 2 190 11 1 2 Example of memory expanso sirin dro det E t e Peto tae een gaa Tea d REY RR CRAS 192 11 1 3 Example of peripheral device connection 194 11 2 uPD78C17 78C10A External Device 1 04 21 198 112 1 MIMIegiSEer Setting ioc teca eto tap a Luna Eb RR RE ERR Rd 199 11 3 TIMINGS 201 CHAPTER 12 PROM ACCESSES uPD78CP18 78CP14 203 CHAPTER 13 PROM WRITE AND VERIFY OPERATIONS uPD78CP18 78CP14 ONLY 207 13 1 PROM Programming Operating 002 0 nnn 208 13 2 PROM Writing Procedu re roten rene tienne Brea nno E EE NR Enn 209
224. iguration in which external memory and a parallel interface unit uPD71055 are connected The memory maps for the wPD78C18 78C14 78C14A 78C12A 78C11A when set to the full expansion mode are shown in Figure 11 6 to 11 9 An example of the control program for the uPD71055 is shown below PPIST LXI H 0CO3 H Set base address MVI A 1000001 1 B 23 to P20 Input 17 to P10 Input Mode 0 Selection anangisi P27 to P24 Output E ME c e 07 to POO Output Mode 0 Selection Mode selection STAX H Set control word 1C03H C003H MVI A OFOH STAX H Port 2 output 1 02 C002H MVI A 0C3H MVI L 00H STAX H PortO OC3H output 1COOH C000H 194 961 87AD series Figure 11 5 71055 Connection Diagram Reference Diagram PF7 uPD74HC139 A Y2 7 0 15 8 ALE Standby control CE CS A130 uPD27C512Nete 1 uPD43256 ete 2 uPD74HC573 OE OE WE 10 Au Notes 1 027 512 2 uPD43256 16K bytes used with uPD78C14 78C14A 24K bytes with 78 2 28K bytes with uPD78C11A Only 16K bytes used 71055 7 00 17 10 27 20 D7 DO RESET WR Voo GND PortO Port1 Port2 System reset LL H31dVHO SONIINILL ANY 5355429
225. ime required until the interrupt request signal becomes active and is recognized as a normal signal and INTFx is set 1 Therefore this time is only required in the case of NMI INT1 and INT2 interrupts The 59 states of component Il indicate the instruction execution time for the longest instruction This time depends on the performance of the INTFx check at the end of each instruction Thus the required time for component varies depending on the instruction being executed at that time from a minimum of 4 states to a maximum of 59 states The 16 states of component Ill represent the time required to save the contents of the PSW and PC to the stack memory Table 9 2 Maximum Interrupt Wait Time Wait Time Components INT1 INT2 Time required for noise elimination 14 states 10 us MAX 0 states Time required for instruction execution divide instruction 59 states 59 states 59 states Time required for automatic save processing 16 states 16 states 16 states 89 states 75 states 10 us 75 states 22 25 us 12 MHz 28 75 us 12 MHz 18 75 us 12 Total time 168 CHAPTER 9 INTERRUPT CONTROL FUNCTION 9 7 Multiple Interrupts When the El instruction is executed all external and internal interrupt requests are enabled even when an interrupt service routine is being executed Therefore when the instruction is executed during execution of an interrupt service routine acknowle
226. ing are not acknowledged when the interrupt request flag is set When the pending interrupt requests are unmasked they are acknowledged if there are no other interrupt requests of higher priority in the interrupt enabled state When execution of the interrupt service routine ends processing is performed to return to the address at which the interrupt was acknowledged First registers flags etc other than the PSW which have been savedare restored and the IE F F is set by the El instruction Next an RETI instruction is executed to restore the previously saved return address and PSW in the order lower PC byte upper PC byte PSW 166 CHAPTER 9 INTERRUPT CONTROL 9 5 Interrupt Operation by SOFTI Instruction When the SOFTI instruction is executed the program jumps unconditionally to the interrupt address 0060H he SOFTI instruction interrupt is not affected by the IE F F and the IE F F is not affected when this instruction is executed The servicing procedure for an interrupt generated by the SOFTI instruction is as follows i PSW upper PC byte and lower PC byte are saved to the stack memory in that order ii The program jumps to the interrupt address 0060H When execution of the interrupt service routine ends processing is performed to return to the address at which the interrupt was acknowledged First registers flags etc other than the PSW which have been saved are restor
227. ing the unmasked interrupt request flag and that interrupt request Is acknowledged in accordance with the interrupt operation the interrupt request flag is automatically reset When the masked interrupt request flag is set that interrupt request is held pending When the pending interrupt request is unmasked it is acknowledged if there are no other interrupt requests of higher priority in the interrupt enable state Whether or not the interrupt request flag for the acknowledged interrupt is automatically reset depends on the setting of the mask register of the same priority If the other interrupt request is masked when masking is released the interrupt request flag is automatically reset but if the other interrupt request remains unmasked when masking is released the interrupt request flag is not reset even though the interrupt request is acknowledged see 9 4 1 When both types are unmasked Figure 9 7 Interrupt Servicing Sequence Masking released for either INT1 or INT2 Save registers INT Interrupt service program Restore registers E Remark In this example masking is released the mask register for one of the interrupt requests which the same priority 165 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 3 When both types are masked The corresponding bits of the mask register for two types of interrupt request are both set to 1 In this case the interrupt requests are held pend
228. ion V wa lt byte Transfers the immediate data Data in the 3rd byte to the working register addressed by the V register specifying the high order 8 bits of the memory address and the 2nd byte specifying the low order 8 bits 5 Flags affected SK 0 L1 0 10 0 6 Example MVIV OOH 20H Store 20H in working register in address 4000H MVIX rpa1 byte Move Immediate to Memory addressed by Register Pair 1 Operation code O 1 0 0 1 0 Ao 2 Number of bytes 2 3 Number of states 10 7 4 Function 1 byte Transfers the immediate data Data in the 2nd byte to the memory addressed by the register pair 1 BC DE HL specified by 1 1 to 3 5 Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example MVIX B Store 0 in memory addressed by the BC register pair 237 CHAPTER 14 INSTRUCTION SET STAW wa Store A to Working Register 1 Operation code O 1 1 0 1 1 2 Number of bytes 2 3 Number of states 10 7 4 Function B V wa HA Stores the accumulator contents in the working register addressed by the V register specifying the high order 8 bits of the memory address and the 2nd byte specifying the low order 8 bits 5 Flags affected SK lt 0 11 lt 0 10 lt 0 6 Example MVI V OEEH STAW OFFH Store A in address EEFFH LDAW wa Load A With Working Register 1 Operation code
229. ion starts when the RESET signal chnages from the low to high level see Figure 10 9 The oscillation stabilization time should therefore be taken into account when returning the RESET signal to the high level After RESET signal input RAM contents are retained but the contents of other registers are undefined Figure 10 8 Hardware STOP Mode Release Timing RESET Signal Input STOP Instruction Execution of address 0 execution instruction CPU operation RESET OSC 178 CHAPTER 10 CONTROL FUNCTIONS Figure 10 9 Hardware STOP Mode Release Timing STOP Signal Rising to RESET Signal Input STOP Instruction Execution of address 0 execution instruction CPU operation RESET oc UUUUUV In the case of a hardware STOP mode release as with a release of the software STOP mode by means of the RESET signal it is possible to differentiate between a power on start and a start due to release of the hardware STOP mode by testing the SB flag using a skip instruction 10 1 7 Low supply voltage data retention mode The low supply voltage data retention mode can be set by decreasing the Voo supply voltage after setting the software hardware STOP mode RAM contents can be retained with lower power dissipation than in the software hardware STOP mode When returning from the software hardware STOP mode by means of a reset the SB flag is used to determine whether the res
230. ir rp3 BC DE HL specified by 1 1 to and stores the result in the extended accumulator 5 Flags affected Z 5 lt 0 1 lt 0 10 0 rp3 Greater Than Register Pair 1 Operation code O 1 1 1 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function EA rp3 1 Skip if no borrow Subtracts the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 and 1 from the contents of the extended accumulator and skips if no borrow is generated as a result of the subtraction EA rp3 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6 Example DGT EA B EA BC 1 A skip is performed if EA is greater than BC 297 CHAPTER 14 INSTRUCTION SET DLT EA rp3 Less Than Register Pair 1 Operation code O 1 1 1 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function i EA rp3 Skip if borrow Subtracts the contents of the register pair rp3 BC DE HL specified by P Po 1 to 3 from the contents of the extended accumulator and skips if a borrow is generated as a result of the subtraction EA rp3 5 Flags affected Z SK HC L1 lt 0 10 lt 0 CY 6 Example DLT EA B EA BC A skip is performed if BC is greater than EA DNE EA rp3 Not Equal Register Pair with EA 1 Operation code O 1 1 1 0 0 lt 2 gt Number of bytes 2 3 Number of states 11 8 4 Functi
231. is detected generates an internal interrupt INTEO INTE1 by means of a match signal CP1 Only in the event of a match between ETM1 the ECNT contents are cleared and the count starts again from 0000H Thus the timer functions as an interval timer which repeatedly generates interrupts using the count time determined by the count value set in ETM1 as the interval see Figure 6 7 Caution Since setting and the start of the internal clock are asynchronous it should be noted that some degree of error may arise in the first interval Internal interrupts can be disabled by setting 1 the MKEO MKE1 bits of the interrupt mask register MKL Figure 6 7 Interval Timer Mode Operation Internal clock 0 m nO m CP1 INTEO Interrupt Interrupt Interrupt acknowledgment ECNT acknowledgment ECNT acknowledgment Start clearance clearance ETMM setting Remark m n m n count value ETM1 n 91 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 6 3 2 Event counter mode In this mode external pulses input to the pin dual function as PC5 are counted After first clearing ECNT the external even count is performed by setting the data shown in Figure 6 8 in the timer event counter mode register Figure 6 8 Timer Event Counter Mode Register Setting Event Counter Mode 0 7 6 5 4 3 2 1
232. is instruction is executed the upper 8 bit address of the area to be accessed must be loaded beforehand into the V register which specifies the 256 byte working register area Next the lower 8 bit address is selected by the value of the SUBNBW instruction operand and then the processing is performed ANAW wa And Working Register with A 1 Operation code O 1 1 1 O 1 0 0 1 0001 0 0 0 lt 2 gt Number of bytes 3 lt 3 gt Number of states 14 11 lt 4 gt Function A A V wa Obtains the logical product of the contents of the accumulator and the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits and stores the result in the accumulator 5 Flags affected gt ZSKc 0 L1 0 L 0 287 CHAPTER 14 INSTRUCTION SET ORAW wa Or Working Register with A 1 Operation code O 1 1 1 0 1 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function amp Obtains the logical sum the contents of the accumulator and the contents the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits and stores the result in the accumulator b Flags affected Z 5 lt 0 1 lt 0 10 0 XRAW wa Exclusive Or Working Register with A 1 Operation code O 1 1 0 T 0 0 70 0 0 0
233. ise Address bus Functions as address bus when external memory is used APPENDIX A INTRODUCTION TO PIGGYBACK Pin Name WR Write strobe Input Output Function Strobe signal output for external memory write operations High level except in external memory data write machine cycles Becomes high impedance output when RESET signal is low or in hardware STOP mode RD Read strobe Srtobe signal output for external memory read operations High level except in external memory data read machine cycles Becomes high impedance output when RESET signal is low or in hardware STOP mode ALE Address latch enable Strobe signal output for external latching of lower address information output to pins PD7 to PDO to access external memory Becomes high impedance output when RESET signal is low or in hardware STOP mode MODEO MODE1 Mode Set MODEO pin to 0 low level MODE1 pin to 1 high level Nete When MODEO and MODE pins are both set to 1 Nete control signal is output in synchronization with ALE NMI Non maskable interrupt Edge triggered falling edge non maskable interrupt input pin INT1 Interrupt request Edge triggered rising edge maskable interrupt input pin can also be used as AC input zero cross detection pin AN7 to ANO Analog input 8 analog inputs to A D converter AN7 to AN4 can also be used as edge detected falling edge inputs VARE
234. ister high order 8 bits and the immediate data in the 3rd byte low order 8 bits and skips if the result is not zero b Flags affected 5 116 0 0 0 OFFAW wa Off Test Working Register with A 1 Operation code 0 1 1 1 0 1 0 0 t Tt 0 T 1 0 0 9 2 Number of bytes 3 3 Number of states 14 11 4 Function A V wa Skip if zero Obtains the logical product of the contents of the accumulator and the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits and skips if the result is zero lt 5 gt Flags affected 12 5 116 0 1060 ANIW wa byte And Immediate with Working Register 1 Operation code O 0 0 0 1 0 1 2 Number of bytes 3 3 Number of states 19 10 4 Function 5 V wa lt V wa byte Obtains the logical product of the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and the immediate data in the 3rd byte and stores the result in the addressed working register 5 Flags affected 2 SK 0 L1 0 L0 0 290 CHAPTER 14 INSTRUCTION SET ORIW wa byte Or Immediate with Working Register 1 Operation code 0 0 0 1 0 1 2 Number of bytes 3 3 Number of states 19 10 4 Function V wa lt V wa v byte Obtains the l
235. isters MA MB MC MF FFH ode control register MMC M registers MMO 1 2 Port output latches Undefined Interrupts nterrupt enable 0 Request flags ask register Test flags except SB flag 0 Standby flag SB Power on reset 1 n standby mode Previous contents retained Reset input during normal operation Contents before RESET input retained Timer mode register TMM FFH Timer F F 0 Timer registers TMO TM1 Undefined Timer event counter Timer event counter mode register ETMM OOH Timer event counter output mode register Timer event counter registers ETMO ETM1 Undefined Timer event counter capture register ECPT Timer event counter ECNT Serial interface Serial mode high register SMH Serial mode low register SML 180 CHAPTER 10 CONTROL FUNCTIONS Table 10 3 Hardware States after Reset 2 2 Hardware State after Reset A D channel mode register ANM OOH MM register RAE bit MM3 Undefined Zero cross mode register ZC 1 Table 10 4 Pin States after Reset State after Reset WR High impedance RD ALE All ports PA PB PC PD PF When the RESET input changes from low to high program execution starts at address 0000 the contents of the various registers should be initialized or re initialized as required in the program Cau
236. it 4 Controls whether or not search mode is entered in synchronous mode set by SML When the SE bit is set 1 the serial register contents are transferred to the receive buffer register and a serial reception interrupt INTSR is generated each time a data bit is received When the SE bit is reset 0 the serial register contents are transferred to the receive buffer register and a serial reception interrupt INTSR is generated each time 8 data bits are received IOE bit 5 Controls whether the synchronous mode or I O interface mode is entered the case of synchronous operation set by SML The synchronous mode is selected when the IOE bit is reset 0 and the I O interface mode is selected when the IOE bit is set 1 TSK bit 6 This bit is used to start the serial clock when data is received using an internal clock in the I O interface mode When the TSK bit is set 1 and the serial clock is started this bit is automatically reset 0 CHAPTER 7 SERIAL INTERFACE FUNCTIONS The serial mode high register SMH is reset to 00H by RESET input and in the hardware STOP mode Figure 7 2 Serial Mode High Register SMH Format 0 7 6 5 4 3 2 1 se o Tree e Tee ye s sc SCK selection Internal clock TO output Internal clock 3a4 Internal clock 24 External clock Disable Enable Reception enable Disable Enable Search mode Disable Enable
237. ked The interrupt with the highest priority is acknowledged and the others are held pending When an interrupt request is acknowledged the interrupt request flag is automatically reset If two types of interrupt requests with the same priority have both been unmasked by the mask register the interrupt request flag is not reset This is because the two types are identified by software at a later stage When an interrupt request is acknowledged the IE F F is reset and all interrupts except non maskable interrupts and the SOFTI instruction are placed in the disabled state DI state The PSW upper PC byte and lower PC byte are saved to the stack memory in that order The program jumps to the interrupt address These interrupt operations are automatically carried out in 16 states The pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority when interrupts are enabled by execution of the El instruction With maskable interrupts there are two types of interrupt requests with the same priority and same interrupt address Unmasking both types unmasking one type or masking both kinds can be selected by setting the mask register 163 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 1 When both types are unmasked The corresponding bits of the mask register for two types of interrupt requests are both set to 0 In this case the interrupt request is the logical sum of the two interrupt reques
238. lag is set Thus the STAX instruction is skipped by the following SK Z instruction and the JMP instruction is executed GTAX rpa Greater Than Memory addressed by Register Pair 1 Operation code O 1 1 1 0 0 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function A rpa 1 Skip if no borrow Subtracts the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by A2A1Ao 1 to 7 and 1 from the contents of the accumulator Skips if no borrow is generated as a result of the subtraction gt b Flags affected Z SK L1 lt 0 LO lt 0 CY 6 Example GTAX D A DE 1 A skip is performed if A is greater than the contents of the memory addressed by the DE register pair 267 CHAPTER 14 INSTRUCTION SET LTAX rpa Less Than Memory addressed by Register Pair 1 Operation code O 1 1 1 0 0 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function A rpa Skip if borrow Subtracts the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by 2 1 1 to 7 from the contents of the accumulator Skips if a borrow is generated as a result of the subtraction A rpa 5 Flags affected Z SK HC L1 lt 0 10 lt 0 CY 6 Example LXI D 4000 lt 4000H LXI H 1100H HL lt 4100H LDAX D A lt 4000H LT
239. lags affected SK L1 LO 320 CHAPTER 14 INSTRUCTION SET 14 6 15 Skip instructions BIT bit wa Bit Test Working Register 1 Operation code 0 1 0 1 1 Bi Bo 2 Number of bytes 2 3 Number of states 10 7 4 Function Skip if bit on Skips if the bit specified by B2B1Bo 0 to 7 of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits is 1 5 Flags affected gt SK L1 0 L0 0 6 Example When the contents of address 10 MVI V 40H BIT 3 42 RET Working register 76543210 40FOH 010 1 1 0 1 0 In this example since the specified bit of the specified address is 1 the JR instruction is skipped and the RET instruction is performed SK f Skip if Flag 1 Operation code O 1 0 1 0 0 0 0 00 0 1 Fz Fo 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if 4 1 Skips if flag f CY HC Z specified by FzF Fo 2 to 4 is set to 1 5 Flags affected gt SK L1 0 L0 0 321 CHAPTER 14 INSTRUCTION SET SKN f Skip if No Flag 1 Operation code O 1 1 0 0 0 0 0 0 1 1 F Fo 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if 4 0 Skips if flag f CY Z specified by F2F1Fo 2 to 4 is set to 0 5 Flags affected gt SK L1
240. lags affected 2 7 SK HC L1 0 LO 0 6 Example i Add A to the HL register pair ADDNC L A L lt L A SKIP IF NO CARRY ADI H l H e H 1 If no carry is generated a skip is performed and the addition ends if a carry is generated the carry is added to the upper byte and the addition ends SUB A r Subtract Register from A 1 Operation code O 1 1 0 0 0 0 0 1 1 1 0 0 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function lt Subtracts the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 from the contents of the accumulator and stores the result in the accumulator 5 Flags affected Z SK lt 0 11 0 LO lt 0 CY 6 Example SUB B lt 254 CHAPTER 14 INSTRUCTION SET Subtract from Register 1 Operation code 0 1 1 0 0 0 0 O 1 1 0 0 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function r lt r A Subtracts the contents of the accumulator from the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 and stores the result in the specified register 5 Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY 6 Example i SUB A lt A A 0 This operation clears the HC and CY flags and sets the Z flag SBB A r Subtract Register from A with Borrow 1 Operation code 0 1 1 0 0
241. lator 182 CHAPTER 10 CONTROL FUNCTIONS Figure 10 13 Examples of Poor Resonator Connection Circuit a Long Connection Circuit Wiring 78 18 Signal Line Close to Varying High Current 78 18 High current e Signal is Picked Up 78 18 b Crossed Signal Lines uPD78C18 PAn X2 Vss d Current Flows an Oscillator Ground Line Potentials at A B and C fluctuate 78 18 183 CHAPTER 10 CONTROL FUNCTIONS The wiring should also be kept as short as possible when an external clock is input to prevent the effects of extraneous electromagnetic wave radiation or external noise When the hardware software STOP mode is entered the X1 and X2 pin levels are fixed Therefore the hardware software STOP mode should not be used when an external clock is used When the hardware software STOP mode is used a crystal or ceramic resonator should be used When the device is powered on and when returning from the hardware software STOP mode sufficient time must be allowed for the oscillation to stabilize The time required for oscillation stabilization is several ms when a crystal is used and several hundred us when a ceramic resonator is used An adequate oscillation stabilization period should be secured by the following means 1 RESET input when powering on reset period 2 RESET input r
242. lled by inputting a low level signal to 137 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS gt gt gt gt gt gt NO oO FR Oo Figure 8 1 A D Converter Block Diagram Sampling amp hold r 777777 1 5 2 Loo o Series resistance a 1 string Ti ONCE R 2 R Pou channel mode Comparator l register 8 S i 8 1 1 1 1 Internal bus R 2 amo AVss L From Internal bus Caution A capacitor should be connected to the analog input pins AN7 to ANO and the reference voltage 138 input pin to prevent errors due to noise A voltage outside the range from AVss to should not be applied to any of the pins AN7 to ANO which are not used or which use an edge detection function as this will adversely affect the conversion precision An effective means of noise protection in this case is clamping with a diode with a small Vr such as Schottky diode In addition the impedance of the analog signal input source and the reference voltage input source should be as small as possible ANn Analog input O mu 1000 T 777 78 18 Reference voltage input I 100 1000 pF 1 777 VAREF 139 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS 8 2 A D Channel Mode Register A
243. m the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 Skips if a borrow is generated as a result of the subtraction lt 5 Flags affected Z SK L1 lt 0 LO lt 0 CY 6 Example H A H A skip is performed if the register is less than 260 CHAPTER 14 INSTRUCTION SET NEA Not Equal Register with 1 Operation code O 1 1 0 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function A r Skip if no zero Subtracts the contents of the register V A B C D E H L specified by R2R Ro 0 to 7 from the contents of the accumulator Skips if the result of the subtraction is not zero A z r 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6 Example A B SKIP IFAz B If A B the CY flag is set if A B the 7 flag is set NEAr A Not Equal A with Register 1 Operation code O 1 1 0 0 0 0 O 1 1 O 1 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if no zero Subtracts the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 Skips if the result of the subtraction is not zero b Flags affected Z SK 11 lt 0 LO lt 0 CY 6 Example NEA C A SKIP IF C A If C A the CY flag is set if C 2 A the Z flag is set Equal Register with 1 Operati
244. mmediate 1 Operation code 0 1 1 1 0 0 2 Number of bytes 3 3 Number of states 11 11 4 Function r byte Skip if borrow Subtracts the immediate data in the 3rd byte from the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 Skips if a borrow is generated as a result of the subtraction r byte 5 Flags affected Z SK L1 lt 0 LO lt 0 CY LTI sr2 byte Less Than Immediate 1 Operation code 0 1 1 0 1 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function sr2 byte Skip if borrow Subtracts the immediate data in the 3rd byte from the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D Skips if a borrow is generated as a result of the subtraction sr2 byte b Flags affected Z SK HC L1 lt 0 10 lt 0 CY 280 CHAPTER 14 INSTRUCTION SET NEI A byte Not Equal Immediate with A 1 Operation code O 1 1 0 O 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function A byte Skip if no zero Subtracts the immediate data in the 2nd byte from the contents of the accumulator Skips if the result of the subtraction is not zero Azbyte 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY NEI r byte Not Equal Immediate with Register 1 Operation code O 1 1 1 O 1 0
245. mory addressed by Register Pair with A 1 Operation code O 1 1 1 0 0 0 0 1 0 0 1 1 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function lt Av Obtains the logical sum of the contents of the accumulator and the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by A2A1Ao 1 to 7 and stores the result in the accumulator lt 5 gt Flags affected 2 5 lt 0 1 lt 0 10 0 6 Example D Av DE 266 CHAPTER 14 INSTRUCTION SET XRAX rpa Exclusive Or Memory addressed by Register Pair with A 1 Operation code O 1 1 1 0 0 0 0 1 0 0 1 0 Az Ao lt 2 gt Number of bytes 2 3 Number of states 11 8 4 Function lt Ax rpa Obtains the exculsive logical sum of the contents of the accumulator and the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by A2A1Ao 1 to 7 and stores the result in the accumulator 5 Flags affected Z 5 lt 0 1 lt 0 10 0 lt 6 gt LXI H 4000H HL lt 4000H MVI 0 8 A lt A8H XRAX H A lt AHL SK Z SKIP IF ZERO STAX D DE JMP KORED Memory 10101000 A8H v 10101000 A8H 4000H A8H 00000000 00H In this example since the contents of A and the contents of address 4000H are the same the exclusive logical sum is 0 and the Z f
246. n lt Adds the immediate data the 2nd byte the contents of the accumulator including the CY flag and stores the result in the accumulator 5 Flags affected Z SK 0 HC L1 lt 0 LO 0 CY ACI r byte Add Immediate to Register with Carry 1 Operation code O 1 1 1 0 1 0 1 0 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4 Function i r r byte CY Adds the immediate data in the 3rd byte to the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 including the CY flag and stores the result in the specified register 5 Flags affected Z SK 0 L1 0 LO lt 0 CY ACI sr2 byte Add Immediate to Special Register with Carry 1 Operation code O 1 1 0 O 1 O0 0 2 Number of bytes 3 3 Number of states 20 11 4 Function sr2 lt sr2 byte CY Adds the immediate data in the 3rd byte to the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D including the CY flag and stores the result in the specified special register 5 Flags affected 12 5 lt 0 11 lt 0 LO lt 0 CY 271 CHAPTER 14 INSTRUCTION SET ADINC A byte Add Immediate to A Skip if No Carry 1 Operation code O 0 1 0 O 1 1 0 2 Number of bytes 2 3 Number of states 7 7 4 Function
247. n whether the El or DI state is set CHAPTER 10 CONTROL FUNCTIONS i ii El state The instruction following the HLT instruction is not executed and the program jumps to the corresponding interrupt address Figure 10 2 HALT Mode Release Timing In El State CPU Interrupt Interrupt operation HLT routine OSC DI state Execution restarts with the instruction following the HLT instruction without jumping to the interrupt address Since the interrupt request flag used for release remains set it should be reset by a skip instruction when required Figure 10 3 HALT Mode Release Timing In DI State Execution of next CPU instruction operation HLT 173 CHAPTER 10 CONTROL FUNCTIONS 10 1 3 Software STOP mode When the STOP instruction is executed the software STOP mode is set unless the interrupt request flag for an unmasked external interrupt is set In the software STOP mode all clocks stop When this mode is set program execution stops and the contents of all registers on chip RAM and flags except FTO and FT1 just before stoppage are retained the timer upcounter is cleared to 00H Only the and RESET signals used to release the software STOP mode are valid and all other functions stop The statuses of the uPD78C18 output pins in the software STOP mode are the same as for t
248. n interrupt request 5 Interrupt enable F F IE F F This is a flip flop which is set by the El instruction and reset by the DI instruction This flip flop is reset when an interrupt is acknowledged and by RESET input hardware and in STOP mode Interrupts are enabled when this flip flop is set and disabled when it is reset Non maskable interrupts can be acknowledged at any time irrespective of the status of this flip flop 6 Test flag register This register consists of 8 test flags which do not generate interrupt requests 4 NMI Enables the NMI pin status to be tested This flag is set to 1 when the NMI pin input level is 1 and 0 when the level is 0 e OV Set 1 when the timer event counter ECNT overflows Set 1 in the event of a parity error framing error or overrun error in serial reception e SB Set 1 if pin increases from a level lower than specified to a level higher than specified e AN7 to ANA Set 1 by a falling edge input to pins AN7 to Falling edge detection is performed by the same method as in the case of the INT2 pin The above test flags can be tested by a skip instruction SKIT or SKNIT Test flags other than NMI are cleared when tested The NMI test flag is not changed by execution of an instruction and the pin status can be tested as it is 157 CHAPTER 9 INTERRUPT CONTROL FUNCTIONS 9 2 External Interrupt Sampling Pins NMI INT1 INT2 and AN7 to
249. n be loaded into an accumulator by a transfer instruction They can also be directly tested bit wise by an arithmetic or logical operation instruction without the use of an accumulator In this case too writing to the output latch is possible and data transferred from the accumulator by a transfer instruction is stored in the entire output latch without regard to the input output setting of the port However the output latch contents for bits specified as input port bits cannot be loaded into the accumulator and since the output buffer is high impedance the contents are not output to an external pin operating as an input pin Thus data stored in the output latch can be output to the external pin and loaded into the accumulator when the bit is switched to output port mode Since input data is not latched stable input is necessary when executing a data transfer instruction or a bit test etc Figure 4 4 Port A Specified as Input Port Internal bus 4 5 3 Port manipulation Actual execution of an instruction which manipulates port A is performed as 8 bit unit If a port A read instruction MOV A PA is executed the input line contents of the port specified for input and the output latch contents of the port specified for output are loaded into an accumulator When a port A write instruction MOV PA A is executed data is written to the output latch of both port
250. n the extended accumulator 5 Flags affected Z SK 0 L1 lt 0 LO lt 0 CY DADC EA rp3 Add Register Pair to EA with Carry 1 Operation code O 1 1 1 O 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function i EA lt EA rp3 CY Adds the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 to the contents of the extended accumulator including the CY flag and stores the result in the extended accumulator 5 Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY 294 CHAPTER 14 INSTRUCTION SET DADDNC EA rp3 Add Register Pair to EA Skip if no Carry 1 Operation code O 1 1 1 O 1 0 0 120 1070271 Pr Po 2 Number of bytes 2 11 8 4 Function EA lt EA rp3 Skip if no carry Adds the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 to the contents of the extended accumulator and stores the result in the extended accumulator Skips if no carry is generated 3 Number of states as a result of the addition b Flags affected Z SK HC L1 0 LO 0 CY ESUB EA r2 Subtract Register from EA 1 Operation code 0 1 1 1 0 0 0 0 2 Number of bytes 2 11 8 EA lt 2 Subtracts the contents of the register r2 A B C specified by R1Ro 1 to 3 from the contents of the extended 3 Number of states 4 Function accumulator and stores the re
251. nabled An example of the system configuration is shown in Figure 7 10 Three lines are necessary for serial data transfer the TxD and RxD serial data input and output lines and the CTS clear to send control line In this example PC7 is functions as the CTS control line which is used when the uPD78C18 receives data As PC7 is in input port mode from resetting until the mode is set 1 is written to the output latch before it is pulled high with a pull up resistor and set as an output port Figure 7 10 Example of Serial Data Transfer System Configuration uPD78C18 71051 CTS PC7 CTS TxD RxDATA RxD TxDATA Baud TxCLK rate generator RxCLK 127 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 1 Initialization The serial mode registers timer port C etc must be initialized in advance to allow uPD78C18 serial data transmission reception The operation flow is shown below Set serial lt a gt interface mode Initialize timer lt b gt Initialize port C lt gt mE d transmission a The parameters required for serial data transmission reception character length clock rate number of stop bits odd even parity serial clock are set in the serial mode registers Figure 7 11 Serial Mode Register Setting NN Clock rate 16 Character length 8 bits Parity Enabled Odd even parity Even parity Number of stop bits 2 bits 7 6 5 4 3 2 1 0
252. ne via RS 232 C and controls the IE program IE controller 78C11 M on the host machine Host Ordering code machine OS Supply medium Product name MS DOS 3 5 inch 2HD uS5A13IE78C11 Ver 2 11 PC 9800 series i 5 inch 2 155 101 78 11 Ver 3 30D IBM PC AT Po DOS 5 inch 2 uS7B101E78C11 Ver 3 1 Remark Operation of IE controller is guaranteed only on the host machines and operating systems quoted above Related Documents e Hardware tools E 78C11 Control Program User s Manual EEU 1368 e Software tools RA87 Assembler Package User s Manual PC 9800 Series MS DOS Based IBM PC PC DOS Based EEM 1202 e Macro Processor User s Manual EEM 1041 351 352 APPENDIX INDEX OF INSTRUCTIONS ALPHABETICAL ORDER Instruction A byte r byte sr2 byte A r byte byte sr2 byte A byte r byte sr2 byte A r wa rpa A byte r byte sr2 byte wa byte Instruction CALL CALT CLC D DAA DADC DADD DADDNC DAN DCR DCRW DCX DCX DEQ DGT DI V LT MOV MOV MOV MOV DNE DOFF DON DOR DRLL DRLR DSBB DSLL DSLR DSUB DSUBNB DXR E EADD Instruction A r rA wa rpa A byte r byte sr2 byte wa byte 353 APPENDIX INDEX OF INSTRUCTIONS ALPHABETICAL ORD
253. ng bit of the mask register is 1 or 0 respectively When RESET is input and in the hardware STOP mode all bits of the mask register are set 1 masking all interrupt requests except non maskable interrupts 155 9 INTERRUPT CONTROL FUNCTIONS Figure 9 2 Mask Register MKL MKH Format 7 6 5 3 2 1 MKEIN 1 MKEO MKT1 MKTO MKL TO masking released TO masked T1 masking released T1 masked masking released masked INT2 masking released INT2 masked INTEO masking released INTEO masked INTE1 masking released INTE1 masked INTEIN masking released INTEIN masked 7 6 5 4 3 2 1 0 LT T esr INTAD masking released INTAD masked INTSR masking released INTSR masked INTST masking released INTST masked 156 CHAPTER 9 INTERRUPT CONTROL FUNCTION 3 Priority control circuit This circuit controls the 6 priority levels described earlier If two or more interrupt request flags are set simultaneously the interrupt with the highest priority according to Table 9 1 is acknowledged and the remainder are held pending 4 Test control circuit This circuit comes into operation when a skip instruction SKIT or SKNIT is executed to test interrupt request flags except INTFNMI for each interrupt source NMI pin states and test flags which do not generate a
254. nowledged or a skip instruction SKIT or SKNIT is executed RESET input resets all flags The interrupt request flags are not affected by the interrupt mask register e Set 1 by a falling edge input to the NMI pin Unlike other interrupt request flags this flag cannot be tested by a skipinstruction However the status of the NMI pin can be tested see 6 Test flag register e Set 1 by TIMERO match signal e INTFT1 Set 1 by TIMER1 match signal e Set 1 by a rising edge input to the INT1 pin e NTF2 Set 1 by a falling edge input to the INT2 pin e NTFEO Set 1 when timer event counter ECNT and ETMO register contents match e INTFE1 Set 1 when timer event counter ECNT and ETM1 register contents match e Set 1 by a falling edge of the timer event countr input CI input or timer output TO 154 CHAPTER 9 INTERRUPT CONTROL FUNCTION e Set 1 when A D converter conversion values are transferred to the four registers CRO to CR3 e NTFSR Set 1 when the serial interface receive buffer becomes full e INTFST Set 1 when the serial interface transmit buffer becomes empty 2 Mask register This is a 10 bit mask register which handles all interrupt requests except non maskable interrupts NMI It can be set 1 or reset 0 bit wise by an instruction An interrupt request is masked disabled or enabled when the correspondi
255. ns oscillator characteristics and some internal operation timings These should be noted when directly replacing a uPD7811 7810 with a uPD78C18 78C17 78C14 78C14A 78C12A 78C11A 78C10A 21 ec Product Name uPD78C10A uPD78C14 Ouality grade uPD78C11A uPD78CP14 uPD78C12A Standard uPD78C17 uPD78C18 uPD78C10A A uPD78C11A A uPD78C12A A uPD78C14 A uPD78CP14 A Special uPD78C17 A uPD78C18 A uPD78CP18 A Electrical specifications Input leak current to ANO 10 uA MAX Input leak current to ANO 1 uA MAX Package Notes 1 2 64 pin plastic shrink DIP 64 pin plastic QUIP 64 pin plastic QUIP straight Nete 1 64 pin plastic OFP 68 pin plastic OFJ Except uPD78C10 78C104A Except uPD78CP14 A 64 pin plastic shrink DIP 64 pin plastic OFP 64 pin plastic QUIP 64 pin plastic OFP 64 pin plastic QUIP 68 pin plastic OFJ 64 pin plastic OFPNote 2 64 pin plastic QUIP 68 pin plastic QFJNote 2 64 pin plastic OFP 64 pin plastic QUIP 3 pue p1epuejs usa eq LL NOlLdIlHOS3GQ 1VH3N3O9 1 H3ldVHO CHAPTER 2 FUNCTIONS uPD78C18 78C17 78C14 78C144 78C12A 78C1 1A 78C10A operate with normal operation mode pin functions 78 18 78 14 pin functions are of two kinds Normal operation mode and EPROM mode EPROM m
256. ns 1 Instructions on port D or port F must not be executed in the 64K byte access mode as this will result in an unpredictable operation 2 Aprogram which dynamically changes the port F input output mode cannot be emulated by an emulator and therefore should not be used 3 AWR pulse is output if an output instruction is executed on port D or port F in the 64K byte mode and this must therefore on no account be performed 4 With an emulator the device may operate normally even if the RAE bit is not initialized by an instruction 5 Overwriting the RAE bit during program execution allows an apparent increase of 256 bytes inthe memory space However this operation cannot be emulated by an emulator and should therefore not be performed 200 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND 11 3 Timings uUPD78C18 operation timings are shown in Figures 11 13 to 11 15 Three oscillator frequency cycles from rise to fall are defined as one state represented by Tn One machine cycle is completed in 3 states 9 clock cycles for all normal read and write operations but 4 states 12 clock cycles are required for an OP code fetch Wait states TW cannot be inserted 1 2 3 OP code fetch timing see Figure 11 13 This is the timing for fetching the OP operation code of all instructions and consists of 4 states T1 to T4 two states T1 and 2 are used for the program memory read and 4 are u
257. nsfer to the output latch of the level of the LV1 level F F When 10 0 11 1 CO10 1 and CO11 1 the LV1 level is transferred to the output latch as with the and bits When the LD1 bit of the timer event counter output mode register EOM is set 1 the LV1 level is inverted after transfer to the output latch The timer event counter mode register is reset to 00H by RESET input and in the hardware STOP mode CHAPTER 6 TIMER EVENT COUNTER FUNCTIO Figure 6 2 Timer Event Counter Mode Register Format 7i 6 5 4 3 2 1 0 11 CO01 EMO ECNT input clock Internal clock 12 12 While Cl input is high Cl input Cl input while TO is high Stop after clearing Free running eared every full count eared on fall of Cl input 1 0 eared on fall of TO 1 1 eared by match between 1 COO output timing Match between ECN Setting prohibited Match between ECN or fall of Cl input Match between ECNT and ETMO or match between and ETM1 Match between ECN Setting prohibited Match between ECN or fall of Cl input Match between ECNT and ETMO or match between and ETM1 87 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 6 2 2 Timer event
258. nstruction is skipped and the JMP instruction is executed to jump to MOTOE SUBX rpa Subtract Memory addressed by Register Pair from A 1 Operation code O 1 1 1 0 0 0 0 1 1 1 0 0 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function lt Subtracts the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by A2A Ao 1 to 7 from the contents of the accumulator and stores the result in the accumulator 5 Flags affected Z SK lt 0 L1 0 LO lt 0 CY 6 Example SUBX D A lt A DE 264 CHAPTER 14 INSTRUCTION SET SBBX rpa Subtract Memory addressed by Register Pair from A 1 Operation code O 1 1 1 0 0 0 0 1 1 1 1 0 Ao 2 Number of bytes 2 3 Number of states 11 8 4 Function lt Subtracts the contents of the memory addressed by the register pair BC DE HL DE HL DE HL specified by A2A1Ao 1 to 7 including the CY flag from the contents of the accumulator and stores the result in the accumulator b Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY 6 Example SBBX lt A DE CY DE lt DE 1 This example subtracts the contents of the memory addressed by the DE register pair including the CY flag from A and stores the result in A and then decrements DE SUBNBX rpa Subtract Memory ad
259. nterface Start Bit ener nnne 330 15 6 Serial Interface and Transmission Format Change 330 15 7 Input Voltage to Analog Input 44 244 11 121 330 15 8 Limitations on Hardware STOP 004224422 1 332 159 How to Use Standby Flag rere terree suras Een Ee rer pasasaan aaa 335 15 10 B s Interface 335 15 11 Restrictions on IE 78C11 M nnne nnn 336 15 12 Electrostatic Withstand Limit of Vp 2 4 4 enne 336 APPENDIX INTROCUTION TO PIGGYBACK PRODUCT 2222244444121 337 A 1 Pin FUN CEOS 25520 ET 340 A 1 1 Lower pins uPD78C11A 78C12A 78C14 QUIP type compatible 340 A 1 2 Upper pins 27C256 27C256A compatible 2 122 2 022 0 000000 342 A 2 Memory Configuration coiere ropes Eee ERRARE RR E ORRRAR S RDDRR RENE RUFEN RR RR ERE aai 342 Memory Mapping Register 346 AA Interface with 2 lt ERE REX ME GER RR EF SERE 348 APPENDIX DEVELOPMENT 85 0200000422244 349 APPENDIX INDEX OF INSTRUCTIONS ALPHABETICAL ORDER 353
260. o 0 Address Input The 15 bit address input pins for an EPROM wvrite verify or read operation The on chip EPROM of the uPD78CP14 is 16K bytes in size and is therefore addressed by the lower 14 bits A13 to AO PF6 should be fixed low 2 2 2 O7 to 00 Data Input output The 8 bit data input output pins for an EPROM wvrite verify or read operation 2 2 3 CE Chip enable Input The Chip Enable signal input pin 2 2 4 OE Output enable Input The Output Enable signal input pin 2 2 5 MODE1 MODEO Mode Input The MODE1 pin should be set to 0 low level the MODEO pin to 1 high level 2 2 6 RESET Reset Input Should be set to 0 low level 2 2 7 The high voltage application pin for an EPROM wvrite verify operation Inputs 1 high level in EPROM read 2 2 8 The power supply application pin 2 2 9 Vss The GND potential pin 30 CHAPTER 2 PIN FUNCTIONS 2 3 Pin Input Output Circuits The input output circuits for the pins are shown in partially simplified format in Table 2 5 and Figures 1 to 15 Table 2 5 Pin Type Type No Pin Name uPD78C17 78C14 78C10A uPD78C18 78C14A 78C12A 78C11A to PA7 PBO to PB7 PCO PC1 PC2 SCK PC3 INT2 to PDO to PD7 PFO to NMI RESET RD WR ALE STOP MODEO MODE1 ANO to AN3 4 to AN7 ala
261. o the receive buffer register and a serial reception interrupt INTSR is generated Since the uPD78C18 is not provided with a circuit for detecting synchronization characters by hardware it is necessary to detect the synchronization characters by software When a synchronization character is detected and reception is synchronized the SE bit is reset 0 Resetting 0 the SE bit sets the character reception mode Each time 8 bit data is received the serial register contents are transferred to the receive buffer register and a serial reception interrupt INTSR is generated Serial reception interrupts are disabled by setting 1 the MKSR bit of the interrupt mask register MKH The maximum data transfer rate in reception is 625 kbps when an internal clock is used as SCK and 1 25 Mbps when an external clock is used at 15 MHz operation CHAPTER 7 SERIAL INTERFACE FUNCTIONS 7 3 3 interface mode In the interface mode synchronization is implemented by the controlled serial clock as with the serial data transfer method of the uPD7801 uPD78C064 etc In this mode data is transferred received with a fixed character length of 8 bits with no parity bit The serial mode register settings are therefore as shown in Figure 7 8 Figure 7 8 Serial Mode Register Format I O Interface Mode 7 6 ZSENENEXZEZEREEZEGES NN Synchronous operation Fixed 8 bit character length Parity disable 0 7 6 5 4 3 2 1 s
262. ode is entered by driving the MODE pin low and the MODEO pin high 2 1 Normal Operation Mode 2 1 1 PA7 to PAO Port A 3 state input output These are the 8 bit input output pins of port A 8 bit input output port with output latch and can be specified bit wise as input output by means of the Mode A register Upon RESET input PA7 to PAO are set as input port high impedance PA7 to PAO also become high impedance in the hardware STOP mode In the uPD78C18 78C144 78C124 78C114 pull up resistors be incorporated bit wise 2 1 2 PB7 to PBO Port B 3 state input output These are the 8 bit input output pins of port B 8 bit input output port with output latch and can be specified bit wise as input output by means of the Mode B register MB Upon RESET input PB7 to PBO setas an input port high impedance PB7 to PBO also become high impedance in the hardware STOP mode In the uPD78C18 78C144 78C124 78C114 pull up resistors can be incorporated bit wise 2 1 3 PC7 to PCO Port C 3 state input output These pins operate as the 8 bit input output pins of port C 8 bit input output port with output latch but in addition to functioning as an input output port they also function as pins for various control signals The PC7 to PCO operating mode can be set bit wise to port or control signal input output mode by means of the Mode Control C register MCC see Table 2 1 In the uPD78C18 78C144 78C124 78C1
263. of the external address space is determined by the setting of the MODEO and MODE 1 pins 198 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND 11 2 1 MM register setting The low order 3 bits of the uPD78C17 78C10A MM register should be set to 0 The RAE bit controls enabling and disabling of on chip RAM accesses When on chip RAM is not used and that area is used by externally connected memory the RAE bit should be set to 0 to disable on chip RAM accesses In normal operation the RAE bit retains its current value when RESET signal is input However the RAE bit is undefined after a power on reset and must therefore be initialized by an instruction Figure 11 10 MM Register Format uPD78C17 78C10A 7 6 5 4 3 2 1 0 Disable Enable Figure 11 11 4PD78C17 Address Space 4k byte access 16K byte access 63K byte access 0000H External device External device External device FC00H On chip RAM On chip RAM On chip RAM MODEO 0 MODEO 1 MODEO 1 MODE1 0 MODE1 0 1 199 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11 12 u PD78C10A Address Space 4K byte access 16K byte access 64 access 0000H 57 External device External device External device FEOOH On chip On chip On chip RAM FFFFH CCS NM N 6 MODEO 0 MODEO 1 MODEO 1 MODE1 0 MODE1 20 MODE1 1 Cautio
264. ogical sum of the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits and the immediate data in the 3rd byte and stores the result in the addressed working register 5 Flags affected Z SK 0 L1 0 L0 0 GTIW wa byte Greater Than Immediate 1 Operation code 0 0 1 0 0 1 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Function V wa byte 1 Skip if no borrow Subtracts the immediate data in the 3rd byte and 1 from the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits Skips if no borrow is generated as a result of the subtraction V wa byte 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY LTIW wa byte Less Than Immediate 1 Operation code O 0 1 1 0 1 0 1 2 Number of bytes 3 3 Number of states 13 10 4 Function j V wa byte Skip if borrow Subtracts the immediate data in the 3rd byte from the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 2nd byte low order 8 bits Skips if a borrow is generated as a result of the subtraction V wa byte 5 Flags affected Z SK HC L1 lt 0 10 lt 0 CY 291 CHAPTER 14 INSTRUCTION SET NEIW wa byte Not Equal Immediate with Working Register
265. ogram which clears a 4 byte register located in a specific area of memory in this case with 10H as the upper address byte can be written as shown below 8 9 A B C D E F 0 1 2 3 4 5 6 7 CLX MVI L OOH CLEAR X REG CLY MVI L 04H CLEAR Y REG CLZ MVI L 08H CLEAR Z REG CLW MVI L OCH CLEAR W REG MVI H 40H MVI C 3 SET COUNTER XRA CLEAR A LOOP STAX HL 0 HL e HL 1 DCR C SKIP IF BORROW JR LOOP RET When is called for example 04H is loaded into the L register and the two stacked instructions MVI L 08H and MVI L OCH are replaced with an idle cycle NOP cycle comprising a total of 14 states the upper byte of the address is determined by the next MVI 40H instruction and the Y REG start address 4004H is loaded into the HL register pair 326 CHAPTER 15 OPERATING PRECAUTIONS Be sure to read the following before using an 87AD series CMOS products 15 1 RAE Bit Setting Target products All products Details When using on chip memory be sure to set the MM register RAE bit to 1 If it is not the on chip memory cannot be used Also when using the on chip RAM for stack be sure to set the RAE bit to 1 before entering interrupt enable and subroutine call Initialization Example 1 CSEG AT 00 GJMP START Branches to initial routine START LXI SP Stack pointer setting MVI xxxx1xxxB MOV MM A Initialization Example 2 Bad
266. oincidence signal CPO CP1 CHAPTER 6 TIMER EVENT COUNTER 5 6 Input control circuit This circuit controls input to ECNT The input to ECNT is determined as follows according to the specification of the timer event counter mode register ETMM i Internal clock 12 ii Internal clock while input is high iii Cl input iv Cl input while TO output is high To prevent errors due to noise signals in the Cl pin sampling is performed by a sampling pulse with cycle 250 ns at 12 MHz operation Thus an input signal of less than 1 state 250 ns at 12 MHz operation is eliminated and a high level or low level duration of 2 states 500 ns at 12 MHz operation or more is necessary for a signal to be acknowledged as a CI pin input signal Caution n CI pin edge detection noise elimination is performed by the internal sampling clock Table 6 2 ECNT Inputs ECNT Input Internal clock 912 12 while input is high Cl inputNote Cl input while TO is highNete Note Falling edge input Clear control circuit This circuit clears ECNT as follows according to the specification of the timer event counter mode register ETMM i Remains cleared ii Not cleared iii Match of ECNT ETM1 Cl input falling edge or TO falling edge In case iv the operation is as shown in Table 6 3 according to the ECNT input 83 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS
267. on EA rp3 Skip if no zero Subtracts the contents of the register pair rp3 BC DE HL specified by P Po 1 to 3 from the contents of the extended accumulator and skips if the result of the subtraction is not zero EAzrp3 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6 Example DNE EA B EA BC A skip is performed if EA and BC are not equal DEO EA rp3 Equal Register Pair with EA 1 Operation code O 1 1 1 0 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function EA rp3 Skip if zero Subtracts the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 from the contents of the extended accumulator and skips if the result of the subtraction is zero EA rp3 lt 5 gt Flags affected Z SK HC L1 lt 0 LO lt 0 CY 6 Example DEO EA EA BC A skip is performed if EA and BC are equal 298 CHAPTER 14 INSTRUCTION SET DON EA rp3 On Test Register Pair with EA 1 Operation code O 1 1 1 1 0 0 2 Number of bytes 2 3 Number of states 11 8 4 Function EA rp3 Skip if no zero Obtains the product of the contents of the extended accumulator and the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 and skips if the result is not zero 5 Flags affected 5 1 lt 0 10 0 DOFF EA rp3 Off Test Register Pair with EA 1 Operation code O 1 1 1 O 1 0
268. on code O 1 1 0 0 0 0 1 1 1 1 1 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function A r Skip if zero Subtracts the contents of the register V A B C D E H L specified by R2R1Ro 0 to 7 from the contents of the accumulator Skips if the result of the subtraction is zero r b Flags affected Z SK L1 lt 0 LO 0 CY 6 Example D SKIP IF A D 261 CHAPTER 14 INSTRUCTION SET Equal A with Register 1 Operation code O 1 1 0 0 0 O 1 1 1 1 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function Skip if zero Subtracts the contents of the accumulator from the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 Skips if the result of the subtraction is zero A 5 Flags affected Z SK L1 lt 0 LO lt 0 CY 6 Example E A SKIPIFE A On Test Register with 1 Operation code O 1 1 0 0 0 0 1 1 0 O 1 R2 Ri Ro 2 Number of bytes 2 3 Number of states 8 8 4 Function 3 A r Skip if no zero Obtains the logical product of the contents of the accumulator and the contents of the register r V A B C D E H L specified by R2R1Ro 0 to 7 Skips if the logical product is not zero 5 Flags affected Z SK 116 0 10 60 Off Test Register with
269. operation setting is performed by the timer event counter mode register The following settings are made in the timer event counter mode register ETMM An internal clock 12 as the ECNT input clock and free running as the ECNT clear mode Timer event counter operation is started by setting the timer event counter mode register 101 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS Figure 6 23 Timer Event Counter Mode Register Setting Single Pulse Output ECNT Operation Setting 2 0 7 6 5 4 3 NUIESERESEEEZENENESN ECNT input clock Internal clock 612 ECNT clear mode Free running An example of the initialization program is shown below F TIMER EVENT COUNTER INITIALIZATION INIT MVI A 00H B MOV ETMM A Clear timer event counter gt lt a gt MVI EOM 05H Initialize counter output 0 J MVI 60H PC5 CI PC6 COO MOV MCC A Set port mode control J ape ANI MKL 7FH INTEIN enable lt gt START A 04H ECNT free running D MOV ETMM A Set timer event counter mode amp start lt d gt 2 After initialization when the input falls the value of the free running ECNT the value at the time of the input fall is latched in the ECPT TIMER EVENT COUNTER CAPTURE REG andan internal interrupt INTEIN is generated The operation flow for the servicing of this interrupt is shown below EINSV Count value setting Timer event counter mo
270. or is also possible Expansion mode External memory expansion up to 256 bytes is possible using the port D input output pins PD7 to PDO as a multiplexed address data bus Also when a large external memory expansion is made this is done by using PF7 to PFO as the address bus see CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS for details uPD78C17 78C10A The port operates only as a multiplexed address data bus AD7 to ADO and has no port function Cautions 1 When the port D input output pins PD7 to PDO are functioning as an address data bus AD7 to ADO the internal address bus status is output in synchronization with ALE in all machine cycles 2 Emulation cannot be performed by an emulator for a program which varies the port D operating mode dynamically Therefore once the mode has been set it should not be changed to a different mode CHAPTER 4 PORT FUNCTIONS 4 5 Port F PF7 to PFO uPD78C18 78C14 78C14A 78C12A 78C11A 78CP18 78CP14 Port F is an 8 bit special input output port in addition to functioning as a general purpose input output port port mode this port also functions as an address bus Port expansion mode can be specified in steps for PF7 to by means of the memory mapping register see 11 1 1 Memory mapping register 1 Port mode Like port A port F is an 8 bit input output port with input output buffer and output latch functions see Figure 4 1 Port A Port F can be set bit wi
271. or peripheral devices uPD78C18 Addresses 8000H to FBFFH uPD78C14 78C14A Addresses 4000H to FEFFH e uPD78C12A Addresses 2000H to FEFFH 56K bytes uPD78C11A Addresses 1000H to FEFFH 31K bytes The memory mapping register MM is used for external device expansion Pins PD7 to PDO are used as a multiplexed address data bus AD7 to ADO and pins PFO are used as an address bus 15 to AB8 With pins PF7 to PFO the number of bits functioning as the address bus can be varied according to the size of the external expansion memory and memory can be expanded in steps from 256 bytes up to 31K 48K 56K 60K bytes depending on the product Pins which are not used for the address bus can be used as general purpose input output port pins see Table 11 1 Table 11 1 PF7 to PFO Address Bus Selection External Address Space Up to 256 bytes Up to 4K bytes Up to 16K bytes Up to 31K 48K 56K 60K bytesNote Note 31K uPD78C18 48K uPD78C14 78C14A 56K uPD78C124 60K uPD78C114A When external device reference instruction is executed in the 256 byte expansion mode the uPD78C18 78C14 78C14A 78C12A 78C11A masks the high order 8 bits of the 16 bit external reference address and outputs a value from 00H to FFH from pins PD7 to PDO AD7 to ADO as address information 187 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Similarly in the 4K
272. ost machine via a serial and parallel interface and controls the PG 1500 on the host machine Host Ordering code machine OS Supply medium Product name MS DOS 3 5 inch 2HD LS5A13PG1500 Ver 3 10 PC 9800 series 1 Ver 5 00ANote BOS 3 5 inch 2HD uS7B13PG1500 Ver 3 1 5 inch 2HC LS7B10PG1500 5 2HD 5 10 1500 Note Ver 5 00 5 00 provided with a task swapping function but this software cannot use the function Remark Operation of PG 1500 controller is guaranteed only on the host machines and operating systems quoted above 350 APPENDIX B DEVELOPMENT TOOLS Debugging Tools An in circuit emulator IE 78C1 1 M is available as a program debugging tool for 87AD series products The system configuration is shown below Hardware IE 78C11 M The 78 11 is an in circuit emulator for the 87AD series The 78 11 is used alone for a plastic QUIP or in conjunction with the conversion Socket for a plastic shrink DIP Efficient debugging is possible by connection to a host machine EV 9001 64 Conversion socket for use with a plastic shrink DIP Used in conjunction with the IE 78C11 M EV 9200G 64 64 WOFN socket Can be used in conjunction with the UPD78CP14KB 78CP18KB by which 64 pin plastic products with window are superseded Software IE 78C11 M control Connects the IE 78C11 M to the host machi
273. ous mode In the synchronous mode character synchronization is implemented by means of synchronization characters and bit synchronization by means of the serial clock In this mode data is transferred with a fixed character length of 8 bits with no parity bit The serial mode register settings are therefore as shown in Figure 7 6 Figure 7 6 Serial Mode Register Format in Synchronous Mode 5 4 3 2 1 0 7 6 Synchronous operation Fixed 8 bit character length Parity disable 7 6 5 4 3 2 1 0 o TS T Te Toe De Te L SCK selection Internal clock TO output Internal clock 384 Internal clock External clock Disable Enable Reception enable Disable Enable Search mode Disable Enable 121 CHAPTER 7 SERIAL INTERFACE FUNCTIONS In the synchronous mode as shown in Figure 7 7 the transmit data has a fixed character length of 8 bits with no parity bit and is transferred LSB first on the falling edge of the serial clock SCK Receive data is input on the rising edge of SCK Serial data 1 2 122 Figure 7 7 Synchronous Mode Timing 1 data transfer Data transmission A transmit operation in the synchronous mode is enabled by setting 1 the TxE bit of the serial mode high register SMH When data is written to the transmit buffer register by a MOV TXB A instruction
274. out at a distance of 2 5 cm or less from the UV lamp Remark The erasure time may be increased due to deterioration of the UV lamp or dirt on the package window 13 5 One Time PROM Products Screening One time PROM products uPD78CP18CW 78CP18GF 3BE 78CP18GO 36 78CP14CW 78CP14G 36 78CP14GF 3BE 78CP14L can not be completely examined for shipment in NEC according to their structure matters After needed data is written screening in which PROM verification is performed after high temperature storage based on the conditions below is recommended Storage Temperature Storage Time 125 C 24 hours NEC performs fee charged service named microcontroller for one time PROM writing marking and screening including verification For details contact our salesman 211 12 2 CHAPTER 14 INSTRUCTION SET 14 1 Operand Notation and Description Method Operands are written in the operand field of an instruction in accordance with the description method for the operand notation for that instruction For details depends on assembler specifications When there are severalitems listed under the description method one of these is selected Alphanumeric characters written in upper case and the symbols and are keywords and are written in that form The relevant numeric value or label is written as immediate data 213 14 INSTRUCTION SET Notation Description Method
275. peration code O 1 1 1 0 2 Number of bytes 3 3 Number of states 11 11 4 Function B rAbyte Skip if zero Obtains the logical product of the contents of the register V A B C D E H L specified by 2 1 0 to 7 and the immediate data in the 3rd byte and skips if the result is zero 5 Flags affected ZSK11 0 L0 0 OFFI sr2 byte Off Test Immediate with Special Register 1 Operation code O 1 1 O 1 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function sr2 Abyte Skip if zero Obtains the logical product of the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and the immediate data in the 3rd byte and skips if the result is zero lt 5 gt Flags affected 7 5 1 lt 0 0 0 284 CHAPTER 14 INSTRUCTION SET 14 6 6 Working register operation instructions ADDW wa Add Working Register to A 1 Operation code O 1 1 1 O 1 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function lt A V wa Adds the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits to the contents of the accumulator and stores the result in the accumulator b Flags affected Z SK lt 0 L1 lt 0 LO lt 0 CY ADCW wa Add Working R
276. peration of Arithmetic Logical Operation Instructions Involving a 73 6 1 Timing Tor sss 82 6 2 ECNT INPUTS dan ina 83 6 3 84 6 4 INTEIN Interrupt Request Flag Setting iet penetret cede eme a estet eee bees 84 7 1 Timer Seting ec ved EE RENS 118 7 2 Maximum Data Transfer Rate at Transmission 22 9299 119 7 3 Maximum Data Transfer Rate at Reception 120 8 1 Conversion Speed Settings iie te Dd tg eee Od aede e ea a Pedo Fd cdd 140 9 1 Prioriti sarid Interr pt AddEeSSesusu s e taste e tee dest tra n donate ages 153 9 2 Maximum Interrupt Walt TIME 2 anten apo a ge 168 0 1 OUTDO UTP IA 171 10 2 Q tp t Pil Statusesu agetur taedet aat 174 0 3 Hardware States aft r Reset ineo ebat Rei PUR PRENNE EIER tone Pipe Eg Rande dpa RARE 180 10 4 States alter Reset nivei beg era y ed dado dh 181 0 5 Recommended Ceramic 21 2 212020202 20 00289 nnne nennen 185 1 1 PF7 to PFO Address BUS 187 3 1 Pin Functions in PROM Programming 22 2 2 222 207
277. put clock cycle while the comparator constantly compares the contents of the counting upcounter and the contents of timer REGO and generates an internal interrupt INTTO if they match When a match occurs the upcounter is cleared and the count up starts again from 00H Thus TIMERO functions as an interval timer which generates repeated interrupt requests using the value set in timer REGO as the interval When timer REGO is set an interrupt is generated on the 256th count Cautions 1 When data is written to timer REGO output of the comparator match signal is disabled and therefore INTTO is not generated 2 After RESET input the contents of TMO are undefined Ensure that TMO initialization is performed by the program before the timer is started When the TIMERO match signal is selected as the timer F F input and the upcounter contents and the timer REGO contents match the timer F F contents are inverted and a square wave can be output from the TO pin The pulse width of the square wave output to the TO pin is determined by the count value set in timer REGO If 0 is set the timer F F contents are inverted and INTTO is generated by the comparator match signal generated every 256 counts The INTTO timer interrupt is disabled by setting MKTO bit 1 of the interrupt mask register MKL 79 80 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS The uPD78C18 is equipped with a multi function 16 bit timer event counter
278. put or the hardware STOP mode is set all bits of the mode C register are set and port C functions as an input port high impedance Figure 4 7 Mode C Register Format 7 6 5 4 3 2 1 0 wes wes wes s ez wer Tues PC Output port PC Input port n 20 7 7 6 5 4 3 2 1 0 eer oos rox ees e As with port A direct bit setting resetting of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator Data transfer to from an accumulator is also possible Control signal input output mode Port C input output pins PC7 to PCO can be used bit wise as control signal inputs or outputs by setting 1 the relevant bit of the mode control C register regardless of the mode C register setting When the PCn pin is used for a control signal 1 the control signal status is ascertained by execution of a port C read instruction or test instruction a When PCn is control signal output When 1 the status of the PCn pin control signal can be read into an accumulator or tested by executing a port C read instruction or test instruction When MCn 0 the internal control signal status can be read into an accumulator or tested by executing a port C read instruction or test instruction see Figure 4 8 67 CHAPTER 4 PORT FUNCTIONS 68 Figure 4 8 Port C Specified as Control Signal Output Control PC Control signal o
279. r Figure 6 10 Timer Event Counter Mode Register Setting Frequency Measurement Mode 0 7 6 5 4 3 2 1 Cl input count while TO is high ECNT cleared on fall of TO ECNT counts the external pulses input to the CI pin while the timer output is high When the timer output falls the ECNT contents are transferred to the timer event counter capture register ECPT ECNT is cleared and an interrupt INTEIN is generated see Figure 6 11 Since the input to ECNT is the CI input while TO is high ECNT is cleared and the interrupt generated by the fall of TO see 6 1 6 Clear control circuit and 7 Interrupt control circuit Figure 6 11 Frequency Measurement Mode Operation Timer output TO Cl input ECNT input INTEIN c N ECNT contents transferred to ECPT ECNT cleared Interrupt acknowledgment 93 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 6 3 4 Pulse width measurement mode The pulse width measurement mode is used to measure the high level width of external pulses input to the CI pin After first clearing ECNT the operationis started by setting the data shownin Figure 6 12 in the timer event counter mode register ETMM Caution The timer event counter count should be started while TO is low ECNT input is masked If the timer is started when TO is high the counter contents should be read by the second INTEIN onward after the timer is started Figu
280. r MA When set to input the pins become high impedance In the uPD78C18 78C144 78C124 78C114 pull up resistors can be incorporated bit wise Figure 4 1 Port A gt O PAn Internal bus O RDi 4 When the corresponding bit of the mode A register is set 1 a port A pin functions as an input port pin and when reset 0 as an output port pin see Figure 4 2 When RESET is input or the hardware STOP mode is set all bits of the mode A register are set and port A functions as an input port high impedance Figure 4 2 Mode A Register Format 7 6 5 4 3 2 1 0 ws warn nz un Tv MA 0 PAn Output port 1 PAn Input port n 2 0 7 7 6 5 4 3 2 1 0 pa par Tee Tm os To 61 CHAPTER 4 PORT FUNCTIONS 1 When specified as output port 0 The output latch is effective enabling data exchange by a transfer instruction between the output latch and the accumulator Direct bit setting resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator Once data is written to the output latch the data is held until a port A manipulation instruction is executed or the data is reset Figure 4 3 Port A Specified as Output Port gt PAn Internal bus 2 When specified as input port MAn 1 PA line contents ca
281. r certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Elec
282. r is driven by the 8 bit successive approximation register SAR One bit of the SAR is set ata time starting from the most significant bit MSB until the value of the series resistance string voltage tap matches the voltage value of the analog input That is when conversion starts the MSB of the SAR is set 1 and the series resistance string voltage tap is made 1 2 Varer and is compared with the analog input If the analog input is greater than 1 2 Varer the MSB of the SAR remains set if smaller than 1 2 Varer the MSB is reset and the operation proceeds to comparison with the next upper bit after the MSB reset Here i e for bit 7 the series resistance string voltage tap is made 3 4 Varer or 1 4 Varer and is compared with the analog input The comparison process continues this way up to the least significant bit of the SAR binary search method When the 8 bit comparison ends the SAR contains the valid digital result and this result is serially latched into registers CRO to CR3 When the A D conversion result has been latched into all the registers CRO to CR3 and INTAD A D conversion termination interrupt is generated The A D converter has independent power supply pins AVbp and AVss and the effects of power supply fluctuations and system noise can be minimized by supplying a stable power supply to these pins The A D converter can also vary the voltage range for conversion by varying Varer and the A D converter operation can be contro
283. ram to the respective areas The same applies if the external ROM area is set in addresses 8000H to BFFFH Cautions 1 The internal address bus contents are output in all machine cycles to port D when it is functioning as an address data bus Also the internal address bus contents are output in all machine cycles from port F pins functioning as an address bus However RD and WR signals are only output in a memory cycle 2 Software which dynamically changes the operating mode of port D and port F cannot be emulated by an emulator and therefore should not be used 188 681 64K Port mode On chip ROM 4K 8K 16K 32K bytes Not used On chip RAM Figure 11 1 External Expansion Modes Set by Memory Mapping Register 256 byte expansion mode On chip ROM 4K 8K 16K 32K bytes Not used External memory 256 bytes Not used On chip RAM 4k byte expansion mode On chip ROM 4K 8K 16K 32K bytes Not used 16K byte expansion mode On chip ROM 4K 8K 16K 32K bytes QR RRQ External memory X 4K bytes 2 5555 5 External memory 16K bytes 555 0600060006000 259260005620 Not used Not used On chip RAM On chip RAM 31K 48K 56K 60K byte expansion mode On chip ROM 4K 8K 16K 32K bytes 55 55555 External memory 31K 48K 56K 60K tes 5755
284. ration Start Stop 1 or 2 bits Odd even no parity Note INTSR is generated by the first stop bit INTST is generated by the first bit when there is only one stop bit and by the second bit when there are two stop bits 1 Data transmission A transmit operation in the asynchronous mode is enabled by setting 1 the TxE bit of the serial data high register SMH When data is written to the transmit buffer register by the MOV TXB A instruction and the previous data transfer is terminated the transmit buffer register contents are automatically transferred to the serial register The start bit 1 bit the parity bit odd even no parity and the stop bit s 1 or 2 bits are automatically added tothe data transferred to the serial register and the data is then transmitted LSB first from the TxD pin When the transmit buffer register becomes empty a serial transmission interrupt INTST is generated Serial transmission interrupts are disabled by setting 1 the MKST bit of the interrupt mask register MKH 118 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 2 When the transmit buffer register is full when the next data write is performed the previous data is corrupted Therefore when writing data to the transmit buffer register it is necessary to check that the serial transmission interrupt request flag INTFST is set 1 and the transmit buffer register is empty before executing the operation When the
285. rd unless otherwise specified in NEC s Data Sheets or Data Books If customers intend to use NEC devices for applications other than those specified for Standard quality grade they should contact NEC Sales Representative in advance Anti radioactive design is not implemented in this product Specif M7 94 11 Intended Readership Purpose Organization Using This Information INTRODUCTION This manual is intended for engineers who require an understanding of 87AD series products functions prior to designing an application system or an application program The relevant products are the following 87AD series CMOS version products uPD78C10A 78C11A 78C10A A 78C11A A uPD78C12A 78C12A A uPD78C14 78C14A 78CG14 78 14 78C14 A 78CP14 A 78 17 78C18 78CP18 78C17 A 78C18 A 78CP18 A Remark PD78C10 78C11 78C10 A 78C11 A have been maintenance products since October 1991 The purposes of this manual is that users understand the hardware functions of 87AD series products shown in the organization below This manual is mainly composed of the following contents General description e Pin functions nternal block functions nterrupt control functions e m xternal device accesses and timing e TU ROM accesses nstruction set Operating precautions Use of this information requires general knowledge of electricity logic circuits and microcontrollers This manual d
286. rder 8 bits in the stack memory indicated by SP 2 then loads the contents of the memory addressed by the effective address comprising the 5 bit immediate data ta into the low order 8 bits of the program counter and loads the contents of the memory addressed by the effective address 1 into the high order 8 bits PC1s 8 and jumps to the address indicated by the memory contents The jump address table must be located in memory address 128 to 191 The table address should be directly written as a label or a number of up to 16 bits in the operand field of the CALT instruction Flags affected SK lt 0 1160 10 0 317 CHAPTER 14 INSTRUCTION SET SOFTI Software Interrupt 1 Operation code 2 Number of bytes 3 Number of states 4 Function 0 1 1 1 0 0 1 0 1 16 SP 1 lt PSW SP 2 lt 115 SP 3 lt PC 17 0 SP lt SP 3 PC lt 0060H This is the software interrupt instruction which stores the PSW contents Z SK HC L1 LO CY in the stack memory indicated by SP 1 then stores the high order 8 bits of the start address of the next instruction in the stack memory addressed by SP 2 and stores the low order 8 bits in the stack memory addressed by SP 3 The instruction then loads the 0060H into the program counter and jumps to address 0060H 5 Flags affected 6 Example 7 NOTE 318 SK lt 0 11 lt 0 10 0 When SOFTI instruction is executed at ad
287. re 6 12 Timer Event Counter Mode Register Setting Pulse Width Measurement Mode 7 6 5 4 3 2 1 0 Count while input is high Cleared on fall of Cl input When the CI input rises the internal clock 12 is supplied to ECNT and the count is started ECNT continues the internal clock while the Cl input is high When the CI input falls the internal clock supply to ECNT is stopped the ECNT contents are transferred to the ECPT register ECNT is cleared and an internal interrupt INTEIN is generated see Figure 6 13 The transfer of the ECNT contents to the ECPT register clearing of ECNT and interrupt generation are performed on the fall of the Cl input see 6 1 2 Timer event counter capture register ECPT 6 Clear control circuit and 7 Interrupt control circuit In the pulse width measurement mode both the high level and low level width of pulses input to the CI pin must be at least 16 states 4 us at 12 MHz operation if less than 12 states ECNT contents will not be transferred to the ECPT register and ECNT will not be cleared 94 CHAPTER 6 TIMER EVENT COUNTER FUNCTIO Figure 6 13 Pulse Width Measurement Mode Operation Internal clock 12 Cl input Internal signal 1 ECNT input Internal signal 2 INTEIN ECNT contents transferred to ECPT ECNT cleared 6 3 5 Programmable rectangular wave output mode In the programma
288. request to transmitting side This is the most desirable method as a remedy against error occurrence 2 Using the internal clock as SCK signal source Use the internal clock as the SCK signal source In this case do not output the from the PC2 pin MCC2 0 with PC2 placed in the port mode 3 Inputting an external clock signal to PC3 TI Input an external clock signal to PC3 TI and count TI with the timer Reverse TO by the timer comparator match signal and use the reversed TO as SCK signal In this case never output SCK from the PC2 pin MCC220 Receving processing initialization program example MVI SMH 00H SCK TO MV SML setting MOV SML A MVI xxH data to scale the TI input setting MOV TMO A MV TMM xxx01000B TIMERO TI count TO is reversed by the TIMERO match signal MV A xxxx101xB PC1 RxD input PC2 Port mode TI input MOV MCC A ORI SMH 08H Receive enabled Remarks 1 Relationship between input frequency fri data transfer speed B and clock rate is as given below fn 2xCxN Where C is TMO set value 2 The TI input high low level width is 6 b oscillation frequency or more The level width is 0 4 us or more when fxx 15 MHz and the maximum frequency of fri is 1 25 MHz for 50 duty 329 CHAPTER 15 OPERATING PRECAUTIONS 15 5 Serial Interface Start Bit Input e Target products e Details e Remedy All produc
289. resistor specifiable PROM product Piggy back product PD78C17 uPD78C17 A None 1K x 8 bits Up to 63K bytes ROM less product PD78C18 PD78C18 A PD78CP18 uPD78CP18 A 32K x 8 bits 1K x 8 bits Up to 31K bytes On chip pull up resistor specifiable PROM product CHAPTER 1 GENERAL DESCRIPTION In the uPD78CP18 78CP14 the on chip mask ROM of the uPD78C18 78C14 is replaced with one time PROM or EPROM One time PROM products can be programmed once only and are useful for short run and multiple device set production and early start up EPROM products can be programmed and reprogrammed and are ideally suited to system evaluation The relationship between Standard quality grade products and Special quality grade products Standard Quality Grade Products Quality Grade Products 78 10 uPD78C LPD78C11A 078 uPD78C12A uPD78C 78 14 078 78 14 LPD78CP14 A uPD78C17 uPD78C 078 18 078 PD78CP18 PD78CP18 A Applications The Standard Products Stationary machine and OA equipment PPC Plain paper copier printer electronic typewriter ECR Electronic cash register FAX bar code reader etc e Automobile Automobile air conditioner cellular phone communication etc Home electric appliances Air conditioner VCRs etc sc
290. s 1 1 1 1 1 1 0 1 Two s complement of 3 314 CHAPTER 14 INSTRUCTION SET JRE word Jump Relative Extended 1 Operation code 0 1 0 O 1 1 2 Number of bytes 2 3 Number of states 10 7 4 Function lt PC 2 jdisp 15 0 15 98 7 0 S When 20 X All O s When 1 AI 1 s Jumps to the address obtained by adding the 9 bit displacement value jdisp to the start address of the next instruction jdisp is handled as signed two s complement data 256 to 255 with bit 8 bit O of the 1st byte as the sign bit A jump destination address or label which takes account of the jump range should be directly written as the operand of the JRE instruction Thus when a JRE instruction is executed at address 1000 for example the possible jump range is from address 746 to address 1257 5 Flags affected SK 0 L1 0 10 0 JEA Jump EA indirect 1 Operation code O 1 1 0 0 0 2 Number of bytes 2 3 Number of states 8 8 4 Function 2 PC EA Loads the contents of the high order 8 bits EAH of the extended accumulator into the high order 8 bits 15 of the program counter loads the low order 8 bits EAL of the extended accumulator into the low order 8 bits PC7 0 and jumps to the address indicated by the extended accumulator 5 Flags affected SK lt 0 11 lt 0 10 lt 0 315 CHAPTER 14 INSTRUCTION SET
291. s 12 8 4 Function Sets the HALT mode lt 5 gt Flags affected SK 0 L1 0 L0 0 324 CHAPTER 14 INSTRUCTION SET STOP Stop 1 Operation code 2 Number of bytes 3 Number of states 4 Function b Flags affected 12 8 Sets the software STOP mode SK lt 0 11 lt 0 10 0 325 CHAPTER 14 INSTRUCTION SET 14 7 Stacked Instructions If instructions in the same group group A or group B from among the 3 kinds of instructions shown below are stacked in a program i e if located in two or more consecutive addresses the instruction located at the start point among the stacked instructions is executed and thereafter the number of states fundamentally required for execution of that instruction are expended without any operation being performed the same state as NOP Group A MVI A byte L1 flag Group B MVI L byte LXI H word LO flag When a group A instruction is executed the L1 flag is set and when a group B instruction is executed the LO flag is set and a check is made of whether instructions in the same group are stacked Interrupts are not disabled during stacked instruction execution but since the L1 and LO flags are automatically saved when an interrupt is generated it is possible on returning from the interrupt service routine to determine whether the next instruction is one which should be given a stacking effect Using stacked MVI instructions a pr
292. s affected Z SK HC L1 lt 0 10 lt 0 CY NEAW wa Not Equal Working Register with A 1 Operation code O 1 1 1 0 0 1 1 101 0 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function A V wa Skip if no zero Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits from the contents of the accumulator Skips if the result of the subtraction is not zero Az V wa 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY EQAW wa Equal Working Register with A 1 Operation code O 1 1 1 0 1 0 0 2 Number of bytes 3 3 Number of states 14 11 4 Function A V wa Skip if zero Subtracts the contents of the working register addressed by the V register high order 8 bits and the immediate data in the 3rd byte low order 8 bits from the contents of the accumulator Skips if the result of the subtraction is zero A V wa 5 Flags affected Z SK L1 0 LO lt 0 CY 289 CHAPTER 14 INSTRUCTION SET ONAW wa On Test Working Register with A 1 Operation code O 1 1 1 0 1 0 0 1 1 0 O 1 0 0 0 lt 2 gt Number of bytes 3 lt 3 gt Number of states 14 11 lt 4 gt Function A V wa Skip if no zero Obtains the logical product of the contents of the accumulator and the contents of the working register addressed by the V reg
293. s granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this documen
294. s specified for input and output but the output latch contents of a port specified as input are not output to an external pin Here the data input output manipulation is described when the high order 4 bits PA7 to PA4 of port A are used as an active low output port and the low order 4 bits to PAO are used as an input port Since the initial status of to PAO after a reset is the input port status high impedance the output port pins used as active low have to be raised to the high level with a pull up resistor to make them inactive Also since the output latch contents are undefined after a reset the active level low may be output at the point of specification as an output port Therefore all ones should be written to the PA7 to 4 output latches before specification as an output port oe uPD78C18 PA7 Active low output Y vv v PA4 63 4 5 PA Input Output PA Output Latch PA Pin 76543210 76543210 765432170 PET LLL TIN xxx x x 1111 24 By pull up resistor OFOH 11110000 1111xxxx VL By pull up resistor MVI A OFH Y MOV 0 111 11110000 1111xxxx NET eet OEFH 1117011141 1110 CENE MOV A 11101010 Y 117101711 11101010 tu ee SR Input data Pin input da
295. s the serial clock SCK is used for both send and receive operations a half duplex method is employed in the synchronous mode and the O interface mode 108 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 7 2 Serial Mode Registers These are two 8 bit registers which specify the serial interface operation mode serial clock data format etc 7 2 1 Serial mode high register SMH The individual bits of the serial mode high register are used to specify the operating mode as shown below The configuration of this register is shown in Figure 7 2 1 SK1 SK2 bits 0 amp 1 These bits specify whether an internal clock or external clock is used as the serial clock SCK When an internal clock is specified as the serial clock the serial clock value is determined by the following expressions For internal clock 24 SCK SCK 24 For internal clock 384 Sck SCK 384 For TO output used as internal clock When the timer input clock is 12 erp fxx enm 24x C C When the timer input clock is 384 fxx SCK 768 x C When the timer F F input is SCK 2X co where fxx is the oscillator frequency SCK is the serial clock and C is the timer count value When the timer F F input is when the TO output is used as the internal clock the clock can only be used in asynchronous mode when the clock rate is 16 or 64 109 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 2 3 4
296. s transferred to the receive buffer register When the receive buffer register becomes full an interrupt request INTSR is generated Serial reception interrupts are disabled by setting 1 the MKSR bit of the interrupt mask register MKH An odd even parity check is made in data reception when the PEN bit 1 If there is a mismatch parity error the stop bit is low framing error or the next data is transferred to the receive buffer when the receive buffer is full overrun error the error flag is set However because no error interrupt feature is provided testing must be performed by skip instructions SKIT or SKNIT in the program When an error is generated also an overrun error will be generated again in the next receive operation if the RXB data is not read The maximum data transfer rate in reception is set as shown in Table 7 3 according to SCK and the clock rate at 15 MHz operation Table 7 3 Maximum Data Transfer Rate at Reception SCK Internal Clock External Clock Clock Rate SCK Data Transfer Rate SCK Transfer Rate x 1Note 2 625 kHz 625 kbps 830 kHz 830 kbps 1 25 MHz 1 25 MbpsNete 1 x 16 2 5 MHz 156 kbps 2 5 MHz 156 kbps x 64 39 1 kbps 39 1 kbps Notes 1 When data is received at transfer rates between 830 kbps and 1 25 Mbps 2 stop bits are necessary 2 At the x 1 clock rate RxD must input a signal synchronized with SCK CHAPTER 7 SERIAL INTERFACE FUNCTIONS 7 3 2 Synchron
297. se as an input or output port by means of the mode F register MF When set to input the pins become high impedance When the corresponding bit of the mode F register is set 1 a port F pin functions as an input port pin and when reset 0 as an output port pin When RESET is input or the hardware STOP mode is set all bits of the mode F register are set Figure 4 10 Mode F Register Format 7 6 5 4 3 2 1 0 wes ere Tw PF Output port PF Input port n 2 0 7 7 6 5 4 3 2 1 0 rer ee ea oa en one As with port A direct bit setting resetting and bit testing of port F output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator Data transfer to from an accumulator is also possible 71 4 5 2 Expansion mode Port F input output pins PF7 to PFO can be used as address outputs corresponding to the size of external expansion memory as shown in Table 4 2 This setting is performed by means of the memory mapping register Pins not used as address outputs are set to port mode Table 4 2 Operation of PF7 to PFO PD78C18 78C14 78C14A 78C12A 78C11A 78CP18 78CP 14 External Address Space Up to 256 bytes Up to 4K bytes Up to 16K bytes Up to 31K 48K 56K 60K bytesNote Note 31K uPD78C18 48K uPD78C14 78C14A
298. sed as rpa2 the instruction is written as shown below STAX D DE DE lt DE 1 The corresponding operation code is shown below Operation code 0 0 1 1 1 1 0 0 2 Execution of the BLOCK instruction Although not specified by an operand when the BLOCK instruction is executed the HL register pair is automatically selected as the source address register and the DE register pair as the destination address register After the data transfer from the source address to the destination address has been performed the HL and the DE register pairs are both automatically incremented by 1 BLOCK DE lt HL DE DE 1 HL HL 1 3 Execution of a return instruction on POP instruction Although not specified by an operand when a return instruction or POP instruction which restores data saved to the stack area is executed auto incrementing of the stack pointer SP is performed RET PCL lt SP PCH lt 1 SP lt SP 2 223 CHAPTER 14 INSTRUCTION SET 14 4 4 Auto decrement addressing This is a special mode of register indirect addressing using the HL and DE register pairs in which after the memory to be manipulated is addressed using the contents of the register pair specified by the addressing specification code in the instruction as the operand address the contents of that register pair are automatically decremented by 1 thus preparing for the next addressing operation Auto decremen
299. sed for internal processing decoding The upper address signal from the low order 8 bits of the external memory reference address is output to AB15 through AB8 through PFO from the start of T1 to the end of 4 AD7 to ADO PD7 to PDO function as the multiplexed address data bus The low order 8 bits of the external memory reference address are output during T1 and then AD7 to ADO become high impedance Since the address information on the AD7 to ADO bus is only output temporarily it must be latched by the external device In the 87AD series a special timing signal ALE is provided for latching AD7 to ADO The ALE signal is output in the T1 state of each machine cycle A low level RD signal is output low from midway through the T1 state to the beginning of T4 External device read timing see Figure 11 14 The data read machine cycle when an external device reference instruction is executed consists of T1 to T3 Except for the absence of T4 the timing for AB15 to AB8 PFO AD7 ADO PD7 to PDO and ALE is the same as an OP code fetch A low level RD signal is output from midway through T1 to the beginning of T3 External device write timing see Figure 11 15 The data write machine cycle when an external device reference instruction is executed consists of 3 states T1 to T3 The address outputs AB15 to AB8 and AD7 to ADO and the ALE signal are the same as for the read timing machine cycle The write data is outp
300. sing the specified output timing When the LDO LD1 bit is reset 0 inversion is disabled 3 LREO LRE1 LRE2 LRE3 bits 2 3 6 7 These bits perform level F F setting resetting When the LREO or LRE2 bit is set 1 LVO or LV1 is reset respectively and when is set 1 LVO LV1 is set These bits automatically return to 0 when the level F F is set reset 88 6 The timer event counter output mode register is reset to by RESET input and the hardware STOP mode Figure 6 4 Timer Event Counter Output Mode Register Format 7 6 5 4 3 2 1 0 LRE2 1 1 LO1 LRE1 LREO LVO data output No operation LVO contents output output trigger LVO level inversion Disable Enable LVO set reset No operation LVO reset LVO set Setting prohibited No operation LV1 contents output LV1 level inversion Disable Enable LV1 set reset No operation LV1 reset LV1 set Setting prohibited 89 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 6 3 Timer Event Counter Operation Timer event counter operation is started by setting the count value and operating mode following the procedure shown in Figure 6 5 Once these settings have been made operation continues in that mode until the mode register is se
301. sion results a value stored in CRO to CR3 is shown in the following expression CRO to INT x 256 0 5 VAREF Or CRO to 0 5 x 2 lt lt CRO to 0 5 x VAREF 256 Remark A function which returns an integer in parentheses VIN Analog input voltage VAREF pin voltage CRO to CR3 CRO to CRG register value Relationship between the analog input voltage and the A D conversion results is shown in Figure 8 7 Figure 8 7 Relationship Between Analog Input Voltage and A D Conversion Results 255 254 253 results 1 3 Did ah qe Reb nis eee 1 1 1 1 3 2 5 3 507 254 509 255 511 512 256 512 256 512 256 512 256 512 256 512 Input voltage Vantr 145 CHAPTER 8 ANALOG DIGITAL CONVERTER FUNCTIONS 8 3 5 Example of analog digital converter program The example of an analog digital converter program given here stores the A D conversion values for pins ANO to AN7 in the memory area from 4000H to 403FH shown in Figure 8 8 Figure 8 8 Memory Map Store Example of A D Conversion Result 8 9 A B C D E 0 1 2 3 4 5 6 7 4000H lt ANO 4008H lt 4010H lt AN2 4018H lt AN3 4020H lt ANA 4028H lt AN5 4030H lt 4038 lt
302. ss 2 7 mm ic QUIP CHAPTER 1 GENERAL DESCRIPTION 1 2 2 Quality grade Standard uPD78C10A uPD78C14A uPD78C18 78 11 uPD78CG14 uPD78CP18 78 12 78 14 uPD78C14 uPD78C17 Special uPD78C10A A uPD78C14 A uPD78C18 A uPD78C11A A uPD78CP14 A _ uPD78CP18 A uPD78C12A A uPD78C17 A Please refer to Quality grade on NEC Semiconductor Devices Document number IEI 1209 published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications CHAPTER 1 GENERAL DESCRIPTION 1 3 Pin Configurations Top View 1 3 1 Shrink DIP QUIP straight 37 QUIP 36 1 Normal operation mode 1 1 2 O STOP 2 3 O PD7 PA3O 4 O PD6 PALO 5 O PD5 6 O PD4 PA6O 7 O PD3 PA7O 8 O PD2 9 O PD1 0 2 1 7 2 O PF6 PB40 3 O PF5 4 6 5 PB7O 6 O PF2 PCO TxD 7 OPF1 PC1 RxD 8 O PFO PC2 SCK O 9 O ALE PC3 INT2 O O WR ORD PC5 CI O AVpb PC6 CO0 O PC7 CO1 AN7 NMI O O ANG INT O ANB MODE1 O ANA RESET O AN3 MODEO O AN2 X20 O ANI X10 O ANO Vss O AVss 10 CHAPTER 1 GENERAL DESCRIPTION PA7 to PAO Port A X1 X2 Crystal PB7 to PBO Port B AN7 to ANO Analog Input PC7 to PCO Port C RD Read Strobe PD7 to PDO Port D WR Write Strobe PF7 to P
303. states 11 11 4 Function lt rx byte Obtains the exclusive logical sum of the contents of the register V A B C D H L specified by R2R 1Ro 0 to 7 and the immediate data in the 3rd byte and stores the result in the specified register 5 Flags affected Z lt 0 1 lt 0 10 0 sr2 byte Exclusive Or Immediate with Special Register 1 Operation code O 1 1 O 1 0 0 S 0 0 1 0 52 Si So 2 Number of bytes 3 3 Number of states 20 11 4 Function sr2 lt sr24 byte Obtains the exclusive logical sum of the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D and the immediate data in the 3rd byte and stores the result in the specified special register b Flags affected ZSK 0 L1 0 L0 0 6 Example To invert bit 2 PA2 of A XRI PA 04H PA lt 00000100 278 CHAPTER 14 INSTRUCTION SET GTI A byte Greater Than Immediate 1 Operation code 0 0 1 0 0 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function A byte 1 Skip if no borrow Subtracts the immediate data in the 2nd byte and 1 from the contents of the accumulator Skips if no borrow is generated as a result of the subtraction A gt byte lt 5 gt Flags affected Z SK HC L1 lt 0 LO 0 CY GTI r byte Greater Than Immediate 1
304. ster MIM This is an 8 bit register in which the function of specifying the piggyback EPROM access address MM6 amp MM7 is added to the control functions of the uPD78C114 78C12A 78C14 The configuration of the memory mapping register is shown in Figure A 4 When MM7 and MM6 are set to 00 piggyback EPROM addresses 0000H to 3FFFH 16K bytes are accessed and the external memory capacity is 48K bytes When set to 10 addresses 0000H to OFFFH bytes are accessed and thus the external memory capacity is 60K bytes The MM7 and MM6 bits are only valid in the uPD78CG14 78CP14Nete if data is written to these bits in the uPD78C11A 78C124 78C14 it is ignored by the CPU Therefore a program developed piggyback mode be transferred without modification to mask ROM In the uPD78CG14 MM7 MM6 MM2 MM1 are initialized to 0 by RESET input Therefore the 78 14 starts operating in single chip mode Also the RAE bit is undefined after RESET input and must be initialized at the start of the program Note See CHAPTER 12 PROM ACCESSES uPD78CP18 78CP14 ONLY 346 APPENDIX INTRODUCTION PIGGYBACK PRO Figure A 4 Memory Mapping Register Format uPD78CG14 7 6 5 4 3 2 1 0 Jove PD7 to input port PFO port mode Single chip PD7 to PDO output port PF7 to port mode Port mode PD7 to PDO expansion mode PF7 to
305. sult in the extended accumulator 5 Flags affected Z SK 0 HC L1 0 LO 0 CY DSUB EA rp3 Subtract Register Pair from EA 1 Operation code 2 Number of bytes 3 Number of states 4 Function 1 1 1 0 1 0 0 1 1 0 0 1 P Po 2 11 8 EA lt EA rp3 Subtracts the contents of the register pair rp3 BC DE HL specified by 1 1 to 3 from the contents of the extended accumulator and stores the result in the extended accumulator 5 Flags affected Z SK 0 HC L1 0 LO 0 CY 295 CHAPTER 14 INSTRUCTION SET DSBB EA rp3 Subtract Register Pair from EA with Borrow 1 Operation code O 1 1 1 0 0 1 1 1 1 0 1 2 Number of bytes 2 3 Number of states 11 8 4 Function i EA lt EA rp3 CY Subtracts the contents of the register pair rp3 BC DE HL specified by P1Po 1 to 3 including the CY flag from the contents of the extended accumulator and stores the result in the extended accumulator 5 Flags affected Z SK lt 0 11 lt 0 LO lt 0 CY DSUBNB EA rp3 Subtract Register Pair from EA Skip if No Borrow 1 Operation code JO 1 1 1 0 1 0 0 1 0 1 1 0 1 2 Number of bytes 2 3 Number of states 11 8 4 Function EA lt EA rp3 Skip if no borrow Subtracts the contents of the register pair rp3 BC DE HL specified by P Po 1 to 3 from the contents of the extende
306. t but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers of
307. t 12 MHz operation with a resolution of 32 us External pulse When an external pulse TI input is specified as the upcounter input clock the timer operates as an interval timer of any desired resolution Also when the upcounter counts external pulses up to the value set in timer REGO 1 1 it can also be used as an event counter which generates internal timer interrupts INTTO INTT1 However it is not possible to read the count data the upcounter contents during the count To prevent errors due to noise signals in the TI pin sampling is performed by a sampling pulse with a 1 state 250 ns 12 MHz cycle Thus an input signal of less than 1 state is eliminated and a high level or low level duration of 2 states or more is necessary for a signal to be acknowledged as a TI pin input signal The upcounter count operation is performed by falling edge input on the pin TIMERO output can only be specified for 1 This can only be specified for TIMER1 The timer operates as a 16 bit interval timer which counts TIMERO match signals as the TIMER1 upcounter input An interval from 1 us to 65 536 ms or from 32 us to 2 1 s can be selected at 12 MHz operation Since both TIMERO and TIMER1 perform the same operation TIMERO operation is described here Interval timer operation is started by setting the count value in timer REGO and writing the necessary data to the timer mode register The upcounter counts up every in
308. t addressing is used when an instruction with the following operand formats is executed Notation Description Method rpa D H rpa2 D H Examples 1 ADDX Operation code 0 1 1 1 0 0 0 0 1 1 0 0 0 Az Ai Ao If the auto decrement mode is selected for the HL register pair used as rpa the instruction is written as shown below ADDX H HL HL HL 1 The corresponding operation code is shown below Operation code 0 1 1 1 0 0 2 Interrupt generation or execution of a CALL instruction or PUSH instruction Although not specified by an operand when an interrupt is generated or a CALL instruction or PUSH instruction is executed in all of which cases register contents are stored in the stack auto decrementing of the stack pointer SP is performed SOFTI SP 1 lt PSW SP 2 lt PC 1H SP 3 lt 11 PC lt 0060H 224 CHAPTER 14 INSTRUCTION SET 14 4 5 Double auto increment addressing This is a special mode of register indirect addressing using the HL and DE register pairs which is effective for 16 bit data transfers between the extended accumulator EA and memory With double auto increment addressing after the memory to be manipulated is addressed using the contents of the register pair specified by the addressing specification code 2 1 in the instruction as the operand address the contents of that register pair are automatically incremented by 2 thus preparing for the ne
309. t again Figure 6 5 Timer Event Counter Setting Procedure Clear timer event counter RESET input upcounter ECNT Set count value in timer event counter REGO 1 ETMO 1 Timer event counter output In case of programmable mode register setting rectangular wave output Timer event counter mode register setting y Port C mode setting MCC Start of count gt Interrupt m Pin output 6 3 1 Interval timer mode In this mode the timer functions as an interval timer which generates interrupts repeatedly with the specified count time as the interval This interval timer allows a count to be specified from 1 us to 65 535 ms with a resolution of 1 us at 12 MHz operation After the timer event counter upcounter ECNT is cleared the count value is set in timer event counter REGO 1 ETMO ETM1 Then when the data shown in Figure 6 6 is set in the timer event counter mode register the timer event counter operates as an interval timer using the internal clock 12 as the input clock 90 CHAPTER 6 TIMER EVENT COUNTER FUNCTIO Figure 6 6 Timer Event Counter Mode Register Setting Interval Timer Mode 3 2 1 0 1 7 6 5 4 ZGUENESESEGESESERES Internal clock 12 count ECNT cleared by match of ECNT and ETM1 contents ECNT counts up every 1 us and the respective comparator compares the ECNT count with the ETMO ETM1 contents and if a match
310. t flags If an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one or both interrupt request flags having the same priority and the program jumps to the interrupt address the interrupt request flag is notreset Therefore the interrupt requestis identified by executing a skip instruction which tests the interrupt request flag at the beginning of the interrupt service routine and the interrupt request flag is reset The priority of interrupt requests with the same priority can be freely decided by the user by determining which of the two is first subject to execution of the skip instruction The interrupt servicing sequence when both INT1 and INT2 are unmasked is shown in Figure 9 6 Figure 9 6 Interrupt Servicing Sequence Masking released for both INT1 and INT2 0010H Save registers INT1 interrupt service program INT1 INT2 INT2 interrupt service program __ Restore registers El Remark In this example masking is released for both INT1 INT2 interrupt requests which have the same priority 164 CHAPTER 9 INTERRUPT CONTROL FUNCTION 2 When one type is unmasked For two types of interrupt requests having the same priority the corresponding bit of the mask register for the interrupt request to be unmasked is set to and the other bit is set to 1 In this case if an interrupt requestis generated by sett
311. ta Output latch contents Note Input O Output 64 CHAPTER 4 PORT FUNCTIONS 4 2 Port B PB7 to PBO Like port A port B is an 8 bit input output port with input output buffer and output latch functions see Figure 4 1 Port B can be set as an input or output port bit wise using the mode B register MB When set to input the pins become high impedance When the corresponding bit of the mode B register is set 1 a port B pin functions as an input port pin and when reset 0 as an output port pin see Figure 4 5 When RESET is input or the hardware STOP mode is set all bits of the mode B register are set and port B functions as an input port high impedance In the uPD78C18 78C144 78C124 78C114 pull up resistors can be incorporated bit wise Figure 4 5 Mode B Register Format MB 7 6 5 4 3 2 1 0 uer es ws wes ez ues eo PB Output port PBn Input port n 0 7 yi 6 5 4 3 2 1 0 rer Treo es vos rez with port A direct bit setting resetting of port B output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator Data transfer to from an accumulator is also possible 65 CHAPTER 4 PORT FUNCTIONS 4 3 Port C PC7 to PCO Port C PC7 to PCO is an 8 bit special input output port which functions in either port mode or control signal input output mode according to the setting of the mode control
312. ting the JR in the NMI routine delay of STOP is required to be larger in proportion to time shortened 333 CHAPTER 15 OPERATING PRECAUTIONS 2 When both RESET and STOP are used During reset period RESET low level STOP input can be acknowledged normally Therefore if the RESET input is activated before entering STOP a normal hardware STOP mode can be expected Figure 15 4 When Both NMI and STOP Are Used 87AD Series Power off detecting signal The operation sequence is as follows a When the power supply off detect signal RESET signal enters the 87AD series is placed in the reset state b The RESET signal is caused to be delayed 10 us or more to change it to be the STOP signal c The 87AD series enters the hardware STOP mode in the reset state However this method may damage the data memory contents by RESET in other words if the RESET signal is input to the CPU data memory while data is written the relevant data may be undefined Figure 15 5 Control Timing of RESET and STOP RESET RESET status PM 10 us or more AERE STOP Vi gt Hardware STOP mode 334 CHAPTER 15 OPERATING PRECAUTIONS 15 9 How to Use Standby Flag Target products All products Details Assurance is not given to voltage level where the standby SB flag is set again after the power supply voltage subsequent to entering the software hardware STOP mode The d
313. tion With an external clock input if is within the operating voltage range all the pins are high impedance after RESET signal input Then a system reset is effected after X1 input However this does not apply when the clock is not input at all to X1 after powering on X1 input 1 k System reset 1 Ports become high impedance 181 CHAPTER 10 CONTROL FUNCTIONS 10 3 Clock Generation Circuit The uPD78C18 incorporates a clock generation circuit allowing the necessary clock to be generated simply by connecting a crystal or a ceramic resonator and capacitors It is also possible to input an externally generated clock Figure 10 11 shows a circuit with a resonator connected and Figure 10 12 shows an example of a circuit when an external clock is input Figure 10 11 Oscillator Connection Circuit Figure 10 12 Example of External Clock Input Circuit 78 18 78 18 x1 x1 HCMOS inverter Caution When using the system clock oscillator the shaded area in Figure 10 11 should be wired in order to avoid effects of wiring capacitor etc as shown below Minimize the length of wiring Do not cross other signal lines or position wiring close to a variable high current The connecting point of the oscillator capacitor should always be the same potential as Vss Do not connect it to the gland pattern where there is a high current Do not pick up the signal from the oscil
314. tion code te OS 1 2 226 CHAPTER 14 INSTRUCTION SET 14 4 7 Base index addressing This is a special mode of register indirect addressing using the HL and DE register pairs in which the memory to be manipulated is addressed using as the operand address the sum of the contents of the register pair base register specified by the addressing specification code AsA2A1Ao 2 1 in the instruction and a register A B EA Base index addressing is used when an instruction with the following operand formats is executed The register A B data is handled as a non negative number Notation Description Method rpa2 H A H B H A H B Example 1 LDAX rpa2 Operation code As 0 1 0 1 Ao If base index addressing is selected using the sum of the HL register pair and the register as rpa2 the instruction is written as shown below LDAX H B A HL The corresponding operation code is shown below Operation code 1 0 1 0 1 1 0 1 227 CHAPTER 14 INSTRUCTION SET 14 4 8 Working register addressing With this addressing method a working register in the memory area to be manipulated is selected with the working register vector register V as the high order 8 bits of the address and the 8 bit immediate data in the instruction as the low order 8 bits of the address This kind of addressing combines register indirect addressing by the V register and direct addressing b
315. tive to negative of the AC signal as with the INT1 pin and can also be used as a timer input clock 58 3 INTERNAL BLOCK FUNCTIONS The zero cross detection function can use the 50 60 Hz power signal as the basis for system timing Further a special characteristic of the zero cross function is that it can be used for servicing of interrupts at the zero voltage point This makes it possible to control a device which uses voltage phase sensing such as a TRIAC or SCR and allows the uPD78C18 to be used for applications such as shaft speed and angle measurement When a capacitor is not connected to the INT1 and INT2 pins they function as digital input pins The format of the zero cross mode register ZCM which controls self bias for zero cross detection of the INT1 and INT2 TI pins is shown in Figure 3 15 Figure 3 15 Zero Cross Mode Register Format pin O No self bias generation Self bias generation INT2 TI pin O No self bias generation Self bias generation When the ZC1 and ZC2 bits of the zero cross mode register are set to to 0 a self bias for zero cross detection of each pin is not generated and each pin responds as a normal digital input When the ZC1 and ZC2 bits are set to 1 a self bias is generated and an AC input signal zero cross can be detected by connecting a capacitor to each pin Each pin with ZC1 and ZC2 bits set to 1 can be directly driven without the
316. to 1 Enable transmission and start output of remaining serial register data 8 Test FST flag Wait until FST is set to 1 9 SK1 amp SK2 bits set to 1 Set to external clock 10 To initial setting of MCC MC MKST 125 CHAPTER 7 SERIAL INTERFACE FUNCTIONS 126 Caution 2 When fewer than 8 external clock pulses are input in reception 1 2 3 4 5 6 7 8 9 RxE bit reset to 0 MC 2 gt set to 1 MMC 2 reset to 0 Change SMH SK1 0 SK1 1 SK2 1 SK2 0 MKSR bit set to 1 INTFSR flag reset to 0 RxE bit set to 1 SCK trigger bit set to 1 Test FSR flag 10 SK1 amp SK2 bits set to 1 11 To initial setting of MCC MC RxE MKSR Disable reception Set to input port SCK pin set to port mode Set to internal clock mode Mask INTSR Enable reception Start internal clock and start remaining control count Wait until FSR is set to 1 Set to external clock CHAPTER 7 SERIAL INTERFACE FUNCTIONS 7 3 4 Example of serial interface program In the following example of serial interface programming data is exchanged with a uPD71051 in the asynchronous mode This example uses the following parameters uPD78C18 oscillator frequency of 11 0592 MHz TO output internal clock used as the serial clock 110 bps data transfer rate clock rate of 16 8 bit character length 2 stop bits and even parity e
317. tronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics lt 1 USER S MANUAL 87AD SERIES uPD78C18 8 BIT SINGLE CHIP MICROCONTROLLER Documen tNo U10199EJ5VOUMO O 5th edition Previous No IEU 1314 Date Published August 1995 P Corporation 1991 Printed in Japan NOTES FOR CMOS DEVICES PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environ mental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work bench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions n
318. truction as the operand address Register indirect addressing is used when an instruction with the following operand formats is executed Items with auto increment decrement double auto increment base and base index functions are described separately Notation Description Method rpa B D H D H D H 1 B D H rpa2 B D H D H D H D byte H A H B H EA H byte rpa3 D H D H D byte H A H B H EA H byte Example 1 LDAX rpa2 Operation code As 0 1 0 1 Ao If the BC register pair is selected as rpa2 the instruction is written as shown below LDAX B A lt The corresponding operation code is shown below Operation code 0 0 1 0 1 0 O 1 222 CHAPTER 14 INSTRUCTION SET 14 4 3 Auto increment addressing This is a special mode of register indirect addressing using the HL and DE register pairs in which after the memory to be manipulated is addressed using the contents of the register pair specified by the addressing specification code AsA2A1A0 in the instruction as the operand address the contents of that register pair are automatically incremented by 1 thus preparing for the next addressing operation Auto increment addressing is used when an instruction with the following operand formats is executed Notation Description Method rpa D H rpa2 D H Examples 1 STAX rpa2 Operation code As 0 1 1 1 Ao If the auto increment mode is selected for the DE register pair u
319. ts When receiving serial data in the asynchronous mode if approximately 1 2 bit pulse is input to the RxD pin the data parity stop bit input is prohibited and an overrun error may result at the time next data Is input Examine the following methods 1 Never input approximately 1 2 bit start bit to the RxD pin 2 When the ER flag is set issue the retransmit request to the transmitting side 15 6 Serial Interface and Transmission Format Change e Target products Details e Remedy All products Serial interface may hang up if a transmit data format is changed by manipulating the SML and SMH registers while transmitting data in the serial register This may occur event if the TxE bit is reset 0 The reasons are as follows When the TxE bit is changed from the set 1 state to reset 0 state the send disabled will result after completing data sending from the serial register Therefore if change is made while data is left in the serial register the serial interface may not be sent Examine the following methods 1 Set the destination mode so that the transfer format needs not be changed 2 When changing transfer format take measure on software so that the transfer format is not be change until the serial register data is sent out after resetting 0 TxE bit 15 7 Input Voltage to Analog Input Pin e Target products Details 330 All products When analog input voltage Vian specified by the A D converter
320. ts of the register V B C D L specified by R2RiRo 0 to 7 and the immediate data in the 3rd byte and stores the result in the specified register 5 Flags affected Z 5 lt 0 11 lt 0 10 0 ORI sr2 byte Or Immediate with Special Register 1 Operation code O 1 1 O 0 2 Number of bytes 3 3 Number of states 20 11 4 Function Sr2 lt sr2 v byte Obtains the logical sum of the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 D and the immediate data in the 3rd byte and stores the result in the specified special register lt 5 gt Flags affected Z 5 lt 0 1 lt 0 10 0 6 Example set bit 1 PC1 of port C ORI PC 02H lt PCv 00000010 277 CHAPTER 14 INSTRUCTION SET XRI A byte Exclusive Or Immediate with A 1 Operation code 0 0 0 1 O 1 1 0 2 Number of bytes 2 3 Number of states 7 7 4 Function amp byte Obtains the exclusive logical sum of the contents of the accumulator and the contents of the immediate data in the 2nd byte and stores the result in the accumulator 5 Flags affected ZSK 0 L1 0 L0 0 6 Example A 8BH lt A 8BH XRI r byte Exclusive Or Immediate with Register 1 Operation code O 1 1 1 O 1 0 0 2 Number of bytes 3 3 Number of
321. umber of states 11 11 4 Function r byte Skip if zero Subtracts the immediate data in the 3rd byte from the contents of the register r V A B C D E H L specified by R2RiRo 0 to 7 Skips if the result of the subtraction is zero r byte b Flags affected Z SK L1 lt 0 LO lt 0 CY sr2 byte Equal Immediate with Special Register 1 Operation code O 1 1 O 0 2 Number of bytes 3 3 Number of states 14 11 4 Function sr2 byte Skip if no zero Subtracts the immediate data in the 3rd byte from the contents of the special register sr2 PA PB PC PD PF MKH MKL ANM SMH EOM TMM specified by 53525150 0 to 3 5 to 9 B D Skips if the result of the subtraction is zero sr2 byte 5 Flags affected Z SK HC L1 lt 0 LO lt 0 CY 282 CHAPTER 14 INSTRUCTION SET ONI A byte On Test Immediate with A 1 Operation code O 1 0 1 1 1 2 Number of bytes 2 3 Number of states 7 7 4 Function A byte Skip if no zero Obtains the logical product of the contents of the accumulator and the contents of the immediate data in the 2nd byte and skips if the result is not zero lt 5 gt Flags affected 7 5 1 lt 0 0 0 byte On Test Immediate with Register 1 Operation code O 1 1 1 0 0 0 1 0 0 1 Ri Ro 2 Number of bytes 3 3 Number of states 11 11 4
322. ut to AD7 through ADO from the beginning of T2 to the end of T3 To enable writing to the addressed device a low level WR signal is output from midway through T1 to the beginning of T3 When PD7 to PDO are set as the multiplexed address data bus AD7 to ADO and PFO as the address bus AB15 to AB8 both the RD signal and the WR signal become high in machine cycles in which the external device is not accessed However the ALE signal is output and the contents of the internal address bus are output directly to port D and port F 201 CHAPTER 11 EXTERNAL DEVICE ACCESSES AND TIMINGS Figure 11 13 OP Code Fetch Timing T1 T2 T3 T4 frequency ALE 4 15 8 PF7 0 AD7 0 ncs PD7 0 dress lower OP code RD Address upper Figure 11 14 External Device Read Timing T1 T2 T3 frequency ALE 1 8 Address PF7 0 ress upper AD7 0 PD7 0 Address lower j Readdaa RD NN Figure 11 15 External Device Write Timing T1 T2 T3 Oscillator S A ALE AB15 8 PF7 0 Address upper AD7 0 POUR Address X WR N 202 CHAPTER 12 PROM ACCESSES uPD78CP18 78CP14 ONLY The uPD78CP18 and uPD78CP14 incorporate 32K byte and 16K byte EPROM respectively Four modes can be selected for the on chip EPROM access range by means of bits MM5 to MM7 of the memory mapping register
323. utput signal gt T Internal 6 bus b When PCn is control signal input When 1 the status of the PCn pin control signal can be read into an accumulator a port C read instruction or tested by a port C test instruction Figure 4 9 Port C Specified as Control Signal Input 1 lt PC Control signal output 1 Internal Y bus Cautions 1 When MCC3 is rewritten INTF2 may be set After rewriting INTF2 should be reset by the SKIT instruction 2 When TO 4 COO PC6 and CO1 PC7 are used as active low signal outputs the following manipulation is required Since port C is entirely set as an input port high impedance in its initial status after a reset TO COO and CO1 used as active low have to be raised to the high level with a pull up resistor to make them inactive Also before switching to the control signal output mode by means of the mode control C register 1 must be written to the port C output latch to make the port C output level and output latch contents equal Port C is then switched to the control signal output mode by means of the mode control C register 4 5 78 18 me TO 4 Active low output COO PC6 CO1 MVI PC OFFH PORT OUTPUT LATCH 1 MVI A OFFH MOV PORT C CONTROL MODE 69 CHAPTER 4 PORT FUNCTIONS
324. which performs the following operations e Interval timer function see 6 3 1 Interval timer mode External event counter function see 6 3 2 Event counter mode e Frequency measurement see 6 3 3 Frequency measurement mode Pulse width measurement see 6 3 4 Pulse width measurement mode e Programmable square wave output see 6 3 5 Programmable rectangular wave output mode 6 1 Timer Event Counter Configuration The configuration of the timer event counter is shown in Figure 6 1 Figure 6 1 Timer Event Counter Block Diagram Internal bus Tq al Timer event counter capture REG ECPT 12 OV Me Timer event counter Clear PCS CI L upcounter ECNT control TO Timer event counter Timer event counter CPO 1 REGO ETMO CP1 Mode registers ETMM EOM EIN L Internal bus Edge detection Remark ambe X fxx Oscillator frequency 12 Interrupt 2 o PC6 COO PC7 CO1 1 INTE IN 81 CHAPTER 6 TIMER EVENT COUNTER FUNCTIONS 82 1 Timer event counter upcounter ECNT ECNT is a 16 bit upcounter which counts input pulses and is cleared by the clear control circuit The OV flag is set if overflow occurs The OV flag can be tested by the SKIT instruction see 9 1 6
325. xt addressing operation Double auto increment addressing is used when an instruction with the following operand format is executed Notation Description Method rpa3 D Example 1 STEAX rpa3 Operation code 0 1 0 0 1 0 1 00 1 Co If the double auto increment mode is selected for the HL register pair used as rpa3 the instruction is written as shown below STEAX HL lt EAL HL 1 lt HL lt HL 2 The corresponding operation code is shown below Operation code 0 1 0 0 1 0 0 0 22b CHAPTER 14 INSTRUCTION SET 14 4 6 Base addressing This is a special mode of register indirect addressing using the HL and DE register pairs in which the memory to be manipulated is addressed using as the operand address the sum of the contents of the register pair base register specified by the addressing specification code AsA2A1Ao 2 1 in the instruction and the immediate data of the operand displacement value Base addressing is used when an instruction with the following operand formats is executed The immediate data displacement value is handled as a non negative number Notation Description Method rpa2 D byte H byte rpa3 D byte H byte Example 1 STAX 2 Operation code As 0 1 1 1 Ao If base addressing is selected using the sum of the HL register pair and 10H as rpa2 the instruction is written as shown below STAX 10H HL A Opera
326. xtended accumulator 15 shifted into the CY flag and 0 is loaded into 15 b Flags affected SKe 0 L1 0 LO lt 0 CY 312 CHAPTER 14 INSTRUCTION SET 14 6 12 Jump instructions JMP word Jump direct 1 Operation code O 1 0 1 0 1 0 0 High address lt 2 gt Number of bytes 3 lt 3 gt Number of states 10 10 lt 4 gt Function lt word Loads the immediate data in the 2nd byte into the low order 8 bits PC7 0 of the program counter loads the immediate data in the 3rd byte into the high order 8 bits PCi5 8 and jumps to the address indicated by the immediate data 5 Flags affected gt SK 0 L1 0 1L0 0 6 Example MVI C 7FH 127 LXI H 4000H HL 4000H LXI D 5000H DE 5000H BLOCK DE lt HL lt C 1 JMP OWARI PC lt OWARI JUMP TO OWARI When the 128 byte block transfer is completed the program jumps to the address indicated by the label OWARI JB Jump BC indirect 1 Operationcode 0 0 1 0 0 0 0 1 2 Number of bytes 1 3 Number of states 4 4 4 Function lt 7 lt C Loads the contents of the register into the high order 8 bits 15 of the program counter loads the contents of the C register into the low order 8 bits PC7 0 and jumps to the address indicated by the BC register pair An effective method is for example to jump using the JB instruction
327. y out of or a borrow into bit 7 or 15 this flag is set 1 In all other cases it is reset 0 When one of 35 types of ALU instructions a rotation instruction or a carry manipulation instruction is executed various flags are affected as shown in Table 3 2 42 3 INTERNAL BLOCK FUNCTIONS Table 3 2 Flag Operations Operation reg memory immediate ADDNCW ADDNCX SUBNBW SUBNBX GTAW GTAX LTAW LTAX DEQ INR INRW DCR DCRW DAA RLR RLL SLR SLL DRLR DRLL DSLR DSLL SLRC SLLC STC CLC MVI A byte MVI L byte LXI H word other instructions Affected set or reset 1 Set 0 Reset Not affected 43 3 INTERNAL BLOCK FUNCTIOS 3 5 Memory 3 5 1 uPD78C18 78C17 78C14 78C14A 78C12A 78C11A 78C10A memory configuration The uPD78C18 78C17 78C14 78C144 78C124A 78C114 78C10A can address a maximum of 64K bytes of memory The memory maps are shown in Figures 3 3 to 3 8 The external memory area and the on chip RAM area can be freely used as program memory and data memory Since the access time for on chip memory and external memory are the same processing can be executed at high speeds 1 Interrupt start addresses The interrupt start addresses are all fixed as follows NMI 0004H INTTO INTT1 0008H INTT INT2 0010H INTE
328. y the immediate data wa Working register addressing is used when an instruction with the following operand format is executed Notation Description Method wa Label numeric value up to 8 bits Example 1 DCRW wa Operation code 0 0 1 1 0 0 0 0 If 77H is specified as wa the instruction is written as shown below DCRW 77H The corresponding operation code is shown below Operation code 0 0 1 1 0 0 0 0 If the contents of the V register are assumed to be 20H the generated operand address will be 2077H and the contents of the working register in that address will be decremented by 1 228 CHAPTER 14 INSTRUCTION SET 14 4 9 Accumulator indirect addressing This is a special example of register indirect addressing in which the contents of the memory addressed by PC 3 A are loaded into the C register and the contents of the memory addressed by 3 A 1 are loaded into the B register Accumulator indirect addressing is used when the TABLE instruction is executed Example 1 Assuming the accumulator contents to be 0 and the PC contents to be 100H the operation is as follows TABLE lt 103H lt 104H 14 4 10 Immediate addressing This addressing method has 1 byte operand data for manipulation in the operation code Immediate addressing is used when an instruction with the following operand format is executed Notation Description Method byte Label numeric value up to 8 bits Example 1 ADI A byte

ANI sr2, byte - Renesas Electronics

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